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Generate the Verilog code corresponding to the following Chisel files.
File ShiftReg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
// Similar to the Chisel ShiftRegister but allows the user to suggest a
// name to the registers that get instantiated, and
// to provide a reset value.
object ShiftRegInit {
def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T =
(0 until n).foldRight(in) {
case (i, next) => {
val r = RegNext(next, init)
name.foreach { na => r.suggestName(s"${na}_${i}") }
r
}
}
}
/** These wrap behavioral
* shift registers into specific modules to allow for
* backend flows to replace or constrain
* them properly when used for CDC synchronization,
* rather than buffering.
*
* The different types vary in their reset behavior:
* AsyncResetShiftReg -- Asynchronously reset register array
* A W(width) x D(depth) sized array is constructed from D instantiations of a
* W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg,
* but only used for timing applications
*/
abstract class AbstractPipelineReg(w: Int = 1) extends Module {
val io = IO(new Bundle {
val d = Input(UInt(w.W))
val q = Output(UInt(w.W))
}
)
}
object AbstractPipelineReg {
def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = {
val chain = Module(gen)
name.foreach{ chain.suggestName(_) }
chain.io.d := in.asUInt
chain.io.q.asTypeOf(in)
}
}
class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) {
require(depth > 0, "Depth must be greater than 0.")
override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}"
val chain = List.tabulate(depth) { i =>
Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}")
}
chain.last.io.d := io.d
chain.last.io.en := true.B
(chain.init zip chain.tail).foreach { case (sink, source) =>
sink.io.d := source.io.q
sink.io.en := true.B
}
io.q := chain.head.io.q
}
object AsyncResetShiftReg {
def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T =
AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name)
def apply [T <: Data](in: T, depth: Int, name: Option[String]): T =
apply(in, depth, 0, name)
def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T =
apply(in, depth, init.litValue.toInt, name)
def apply [T <: Data](in: T, depth: Int, init: T): T =
apply (in, depth, init.litValue.toInt, None)
}
File SynchronizerReg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util.{RegEnable, Cat}
/** These wrap behavioral
* shift and next registers into specific modules to allow for
* backend flows to replace or constrain
* them properly when used for CDC synchronization,
* rather than buffering.
*
*
* These are built up of *ResetSynchronizerPrimitiveShiftReg,
* intended to be replaced by the integrator's metastable flops chains or replaced
* at this level if they have a multi-bit wide synchronizer primitive.
* The different types vary in their reset behavior:
* NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin
* AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep
* 1-bit-wide shift registers.
* SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg
*
* [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference.
*
* ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross
* Clock Domains.
*/
object SynchronizerResetType extends Enumeration {
val NonSync, Inferred, Sync, Async = Value
}
// Note: this should not be used directly.
// Use the companion object to generate this with the correct reset type mixin.
private class SynchronizerPrimitiveShiftReg(
sync: Int,
init: Boolean,
resetType: SynchronizerResetType.Value)
extends AbstractPipelineReg(1) {
val initInt = if (init) 1 else 0
val initPostfix = resetType match {
case SynchronizerResetType.NonSync => ""
case _ => s"_i${initInt}"
}
override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}"
val chain = List.tabulate(sync) { i =>
val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B)
reg.suggestName(s"sync_$i")
}
chain.last := io.d.asBool
(chain.init zip chain.tail).foreach { case (sink, source) =>
sink := source
}
io.q := chain.head.asUInt
}
private object SynchronizerPrimitiveShiftReg {
def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = {
val gen: () => SynchronizerPrimitiveShiftReg = resetType match {
case SynchronizerResetType.NonSync =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType)
case SynchronizerResetType.Async =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset
case SynchronizerResetType.Sync =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset
case SynchronizerResetType.Inferred =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType)
}
AbstractPipelineReg(gen(), in)
}
}
// Note: This module may end up with a non-AsyncReset type reset.
// But the Primitives within will always have AsyncReset type.
class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int)
extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
withReset(reset.asAsyncReset){
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async)
}
}
io.q := Cat(output.reverse)
}
object AsyncResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
// Note: This module may end up with a non-Bool type reset.
// But the Primitives within will always have Bool reset type.
@deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2")
class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
withReset(reset.asBool){
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync)
}
}
io.q := Cat(output.reverse)
}
object SyncResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred)
}
io.q := Cat(output.reverse)
}
object ResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}"
val output = Seq.tabulate(w) { i =>
SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync)
}
io.q := Cat(output.reverse)
}
object SynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T =
if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, None)
def apply [T <: Data](in: T): T =
apply (in, 3, None)
}
class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module {
override def desiredName = s"ClockCrossingReg_w${w}"
val io = IO(new Bundle{
val d = Input(UInt(w.W))
val q = Output(UInt(w.W))
val en = Input(Bool())
})
val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en)
io.q := cdc_reg
}
object ClockCrossingReg {
def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = {
val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit))
name.foreach{ cdc_reg.suggestName(_) }
cdc_reg.io.d := in.asUInt
cdc_reg.io.en := en
cdc_reg.io.q.asTypeOf(in)
}
}
| module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_486( // @[SynchronizerReg.scala:68:19]
input clock, // @[SynchronizerReg.scala:68:19]
input reset, // @[SynchronizerReg.scala:68:19]
input io_d, // @[ShiftReg.scala:36:14]
output io_q // @[ShiftReg.scala:36:14]
);
wire io_d_0 = io_d; // @[SynchronizerReg.scala:68:19]
wire _sync_2_T = io_d_0; // @[SynchronizerReg.scala:54:22, :68:19]
wire io_q_0; // @[SynchronizerReg.scala:68:19]
reg sync_0; // @[SynchronizerReg.scala:51:87]
assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19]
reg sync_1; // @[SynchronizerReg.scala:51:87]
reg sync_2; // @[SynchronizerReg.scala:51:87]
always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19]
if (reset) begin // @[SynchronizerReg.scala:68:19]
sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87]
sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87]
sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87]
end
else begin // @[SynchronizerReg.scala:68:19]
sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87]
sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87]
sync_2 <= _sync_2_T; // @[SynchronizerReg.scala:51:87, :54:22]
end
always @(posedge, posedge) |
Generate the Verilog code corresponding to the following Chisel files.
File Buffer.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import org.chipsalliance.diplomacy.lazymodule._
import freechips.rocketchip.diplomacy.BufferParams
class TLBufferNode (
a: BufferParams,
b: BufferParams,
c: BufferParams,
d: BufferParams,
e: BufferParams)(implicit valName: ValName) extends TLAdapterNode(
clientFn = { p => p.v1copy(minLatency = p.minLatency + b.latency + c.latency) },
managerFn = { p => p.v1copy(minLatency = p.minLatency + a.latency + d.latency) }
) {
override lazy val nodedebugstring = s"a:${a.toString}, b:${b.toString}, c:${c.toString}, d:${d.toString}, e:${e.toString}"
override def circuitIdentity = List(a,b,c,d,e).forall(_ == BufferParams.none)
}
class TLBuffer(
a: BufferParams,
b: BufferParams,
c: BufferParams,
d: BufferParams,
e: BufferParams)(implicit p: Parameters) extends LazyModule
{
def this(ace: BufferParams, bd: BufferParams)(implicit p: Parameters) = this(ace, bd, ace, bd, ace)
def this(abcde: BufferParams)(implicit p: Parameters) = this(abcde, abcde)
def this()(implicit p: Parameters) = this(BufferParams.default)
val node = new TLBufferNode(a, b, c, d, e)
lazy val module = new Impl
class Impl extends LazyModuleImp(this) {
def headBundle = node.out.head._2.bundle
override def desiredName = (Seq("TLBuffer") ++ node.out.headOption.map(_._2.bundle.shortName)).mkString("_")
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
out.a <> a(in .a)
in .d <> d(out.d)
if (edgeOut.manager.anySupportAcquireB && edgeOut.client.anySupportProbe) {
in .b <> b(out.b)
out.c <> c(in .c)
out.e <> e(in .e)
} else {
in.b.valid := false.B
in.c.ready := true.B
in.e.ready := true.B
out.b.ready := true.B
out.c.valid := false.B
out.e.valid := false.B
}
}
}
}
object TLBuffer
{
def apply() (implicit p: Parameters): TLNode = apply(BufferParams.default)
def apply(abcde: BufferParams) (implicit p: Parameters): TLNode = apply(abcde, abcde)
def apply(ace: BufferParams, bd: BufferParams)(implicit p: Parameters): TLNode = apply(ace, bd, ace, bd, ace)
def apply(
a: BufferParams,
b: BufferParams,
c: BufferParams,
d: BufferParams,
e: BufferParams)(implicit p: Parameters): TLNode =
{
val buffer = LazyModule(new TLBuffer(a, b, c, d, e))
buffer.node
}
def chain(depth: Int, name: Option[String] = None)(implicit p: Parameters): Seq[TLNode] = {
val buffers = Seq.fill(depth) { LazyModule(new TLBuffer()) }
name.foreach { n => buffers.zipWithIndex.foreach { case (b, i) => b.suggestName(s"${n}_${i}") } }
buffers.map(_.node)
}
def chainNode(depth: Int, name: Option[String] = None)(implicit p: Parameters): TLNode = {
chain(depth, name)
.reduceLeftOption(_ :*=* _)
.getOrElse(TLNameNode("no_buffer"))
}
}
File Nodes.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import org.chipsalliance.diplomacy.nodes._
import freechips.rocketchip.util.{AsyncQueueParams,RationalDirection}
case object TLMonitorBuilder extends Field[TLMonitorArgs => TLMonitorBase](args => new TLMonitor(args))
object TLImp extends NodeImp[TLMasterPortParameters, TLSlavePortParameters, TLEdgeOut, TLEdgeIn, TLBundle]
{
def edgeO(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeOut(pd, pu, p, sourceInfo)
def edgeI(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeIn (pd, pu, p, sourceInfo)
def bundleO(eo: TLEdgeOut) = TLBundle(eo.bundle)
def bundleI(ei: TLEdgeIn) = TLBundle(ei.bundle)
def render(ei: TLEdgeIn) = RenderedEdge(colour = "#000000" /* black */, label = (ei.manager.beatBytes * 8).toString)
override def monitor(bundle: TLBundle, edge: TLEdgeIn): Unit = {
val monitor = Module(edge.params(TLMonitorBuilder)(TLMonitorArgs(edge)))
monitor.io.in := bundle
}
override def mixO(pd: TLMasterPortParameters, node: OutwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLMasterPortParameters =
pd.v1copy(clients = pd.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })
override def mixI(pu: TLSlavePortParameters, node: InwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLSlavePortParameters =
pu.v1copy(managers = pu.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })
}
trait TLFormatNode extends FormatNode[TLEdgeIn, TLEdgeOut]
case class TLClientNode(portParams: Seq[TLMasterPortParameters])(implicit valName: ValName) extends SourceNode(TLImp)(portParams) with TLFormatNode
case class TLManagerNode(portParams: Seq[TLSlavePortParameters])(implicit valName: ValName) extends SinkNode(TLImp)(portParams) with TLFormatNode
case class TLAdapterNode(
clientFn: TLMasterPortParameters => TLMasterPortParameters = { s => s },
managerFn: TLSlavePortParameters => TLSlavePortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLImp)(clientFn, managerFn) with TLFormatNode
case class TLJunctionNode(
clientFn: Seq[TLMasterPortParameters] => Seq[TLMasterPortParameters],
managerFn: Seq[TLSlavePortParameters] => Seq[TLSlavePortParameters])(
implicit valName: ValName)
extends JunctionNode(TLImp)(clientFn, managerFn) with TLFormatNode
case class TLIdentityNode()(implicit valName: ValName) extends IdentityNode(TLImp)() with TLFormatNode
object TLNameNode {
def apply(name: ValName) = TLIdentityNode()(name)
def apply(name: Option[String]): TLIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLIdentityNode = apply(Some(name))
}
case class TLEphemeralNode()(implicit valName: ValName) extends EphemeralNode(TLImp)()
object TLTempNode {
def apply(): TLEphemeralNode = TLEphemeralNode()(ValName("temp"))
}
case class TLNexusNode(
clientFn: Seq[TLMasterPortParameters] => TLMasterPortParameters,
managerFn: Seq[TLSlavePortParameters] => TLSlavePortParameters)(
implicit valName: ValName)
extends NexusNode(TLImp)(clientFn, managerFn) with TLFormatNode
abstract class TLCustomNode(implicit valName: ValName)
extends CustomNode(TLImp) with TLFormatNode
// Asynchronous crossings
trait TLAsyncFormatNode extends FormatNode[TLAsyncEdgeParameters, TLAsyncEdgeParameters]
object TLAsyncImp extends SimpleNodeImp[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncEdgeParameters, TLAsyncBundle]
{
def edge(pd: TLAsyncClientPortParameters, pu: TLAsyncManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLAsyncEdgeParameters(pd, pu, p, sourceInfo)
def bundle(e: TLAsyncEdgeParameters) = new TLAsyncBundle(e.bundle)
def render(e: TLAsyncEdgeParameters) = RenderedEdge(colour = "#ff0000" /* red */, label = e.manager.async.depth.toString)
override def mixO(pd: TLAsyncClientPortParameters, node: OutwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncClientPortParameters =
pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }))
override def mixI(pu: TLAsyncManagerPortParameters, node: InwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncManagerPortParameters =
pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }))
}
case class TLAsyncAdapterNode(
clientFn: TLAsyncClientPortParameters => TLAsyncClientPortParameters = { s => s },
managerFn: TLAsyncManagerPortParameters => TLAsyncManagerPortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLAsyncImp)(clientFn, managerFn) with TLAsyncFormatNode
case class TLAsyncIdentityNode()(implicit valName: ValName) extends IdentityNode(TLAsyncImp)() with TLAsyncFormatNode
object TLAsyncNameNode {
def apply(name: ValName) = TLAsyncIdentityNode()(name)
def apply(name: Option[String]): TLAsyncIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLAsyncIdentityNode = apply(Some(name))
}
case class TLAsyncSourceNode(sync: Option[Int])(implicit valName: ValName)
extends MixedAdapterNode(TLImp, TLAsyncImp)(
dFn = { p => TLAsyncClientPortParameters(p) },
uFn = { p => p.base.v1copy(minLatency = p.base.minLatency + sync.getOrElse(p.async.sync)) }) with FormatNode[TLEdgeIn, TLAsyncEdgeParameters] // discard cycles in other clock domain
case class TLAsyncSinkNode(async: AsyncQueueParams)(implicit valName: ValName)
extends MixedAdapterNode(TLAsyncImp, TLImp)(
dFn = { p => p.base.v1copy(minLatency = p.base.minLatency + async.sync) },
uFn = { p => TLAsyncManagerPortParameters(async, p) }) with FormatNode[TLAsyncEdgeParameters, TLEdgeOut]
// Rationally related crossings
trait TLRationalFormatNode extends FormatNode[TLRationalEdgeParameters, TLRationalEdgeParameters]
object TLRationalImp extends SimpleNodeImp[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalEdgeParameters, TLRationalBundle]
{
def edge(pd: TLRationalClientPortParameters, pu: TLRationalManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLRationalEdgeParameters(pd, pu, p, sourceInfo)
def bundle(e: TLRationalEdgeParameters) = new TLRationalBundle(e.bundle)
def render(e: TLRationalEdgeParameters) = RenderedEdge(colour = "#00ff00" /* green */)
override def mixO(pd: TLRationalClientPortParameters, node: OutwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalClientPortParameters =
pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }))
override def mixI(pu: TLRationalManagerPortParameters, node: InwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalManagerPortParameters =
pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }))
}
case class TLRationalAdapterNode(
clientFn: TLRationalClientPortParameters => TLRationalClientPortParameters = { s => s },
managerFn: TLRationalManagerPortParameters => TLRationalManagerPortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLRationalImp)(clientFn, managerFn) with TLRationalFormatNode
case class TLRationalIdentityNode()(implicit valName: ValName) extends IdentityNode(TLRationalImp)() with TLRationalFormatNode
object TLRationalNameNode {
def apply(name: ValName) = TLRationalIdentityNode()(name)
def apply(name: Option[String]): TLRationalIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLRationalIdentityNode = apply(Some(name))
}
case class TLRationalSourceNode()(implicit valName: ValName)
extends MixedAdapterNode(TLImp, TLRationalImp)(
dFn = { p => TLRationalClientPortParameters(p) },
uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLRationalEdgeParameters] // discard cycles from other clock domain
case class TLRationalSinkNode(direction: RationalDirection)(implicit valName: ValName)
extends MixedAdapterNode(TLRationalImp, TLImp)(
dFn = { p => p.base.v1copy(minLatency = 1) },
uFn = { p => TLRationalManagerPortParameters(direction, p) }) with FormatNode[TLRationalEdgeParameters, TLEdgeOut]
// Credited version of TileLink channels
trait TLCreditedFormatNode extends FormatNode[TLCreditedEdgeParameters, TLCreditedEdgeParameters]
object TLCreditedImp extends SimpleNodeImp[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedEdgeParameters, TLCreditedBundle]
{
def edge(pd: TLCreditedClientPortParameters, pu: TLCreditedManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLCreditedEdgeParameters(pd, pu, p, sourceInfo)
def bundle(e: TLCreditedEdgeParameters) = new TLCreditedBundle(e.bundle)
def render(e: TLCreditedEdgeParameters) = RenderedEdge(colour = "#ffff00" /* yellow */, e.delay.toString)
override def mixO(pd: TLCreditedClientPortParameters, node: OutwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedClientPortParameters =
pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }))
override def mixI(pu: TLCreditedManagerPortParameters, node: InwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedManagerPortParameters =
pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }))
}
case class TLCreditedAdapterNode(
clientFn: TLCreditedClientPortParameters => TLCreditedClientPortParameters = { s => s },
managerFn: TLCreditedManagerPortParameters => TLCreditedManagerPortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLCreditedImp)(clientFn, managerFn) with TLCreditedFormatNode
case class TLCreditedIdentityNode()(implicit valName: ValName) extends IdentityNode(TLCreditedImp)() with TLCreditedFormatNode
object TLCreditedNameNode {
def apply(name: ValName) = TLCreditedIdentityNode()(name)
def apply(name: Option[String]): TLCreditedIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLCreditedIdentityNode = apply(Some(name))
}
case class TLCreditedSourceNode(delay: TLCreditedDelay)(implicit valName: ValName)
extends MixedAdapterNode(TLImp, TLCreditedImp)(
dFn = { p => TLCreditedClientPortParameters(delay, p) },
uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLCreditedEdgeParameters] // discard cycles from other clock domain
case class TLCreditedSinkNode(delay: TLCreditedDelay)(implicit valName: ValName)
extends MixedAdapterNode(TLCreditedImp, TLImp)(
dFn = { p => p.base.v1copy(minLatency = 1) },
uFn = { p => TLCreditedManagerPortParameters(delay, p) }) with FormatNode[TLCreditedEdgeParameters, TLEdgeOut]
File LazyModuleImp.scala:
package org.chipsalliance.diplomacy.lazymodule
import chisel3.{withClockAndReset, Module, RawModule, Reset, _}
import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo}
import firrtl.passes.InlineAnnotation
import org.chipsalliance.cde.config.Parameters
import org.chipsalliance.diplomacy.nodes.Dangle
import scala.collection.immutable.SortedMap
/** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]].
*
* This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy.
*/
sealed trait LazyModuleImpLike extends RawModule {
/** [[LazyModule]] that contains this instance. */
val wrapper: LazyModule
/** IOs that will be automatically "punched" for this instance. */
val auto: AutoBundle
/** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */
protected[diplomacy] val dangles: Seq[Dangle]
// [[wrapper.module]] had better not be accessed while LazyModules are still being built!
require(
LazyModule.scope.isEmpty,
s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}"
)
/** Set module name. Defaults to the containing LazyModule's desiredName. */
override def desiredName: String = wrapper.desiredName
suggestName(wrapper.suggestedName)
/** [[Parameters]] for chisel [[Module]]s. */
implicit val p: Parameters = wrapper.p
/** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and
* submodules.
*/
protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = {
// 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]],
// 2. return [[Dangle]]s from each module.
val childDangles = wrapper.children.reverse.flatMap { c =>
implicit val sourceInfo: SourceInfo = c.info
c.cloneProto.map { cp =>
// If the child is a clone, then recursively set cloneProto of its children as well
def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = {
require(bases.size == clones.size)
(bases.zip(clones)).map { case (l, r) =>
require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}")
l.cloneProto = Some(r)
assignCloneProtos(l.children, r.children)
}
}
assignCloneProtos(c.children, cp.children)
// Clone the child module as a record, and get its [[AutoBundle]]
val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName)
val clonedAuto = clone("auto").asInstanceOf[AutoBundle]
// Get the empty [[Dangle]]'s of the cloned child
val rawDangles = c.cloneDangles()
require(rawDangles.size == clonedAuto.elements.size)
// Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s
val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) }
dangles
}.getOrElse {
// For non-clones, instantiate the child module
val mod = try {
Module(c.module)
} catch {
case e: ChiselException => {
println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}")
throw e
}
}
mod.dangles
}
}
// Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]].
// This will result in a sequence of [[Dangle]] from these [[BaseNode]]s.
val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate())
// Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]]
val allDangles = nodeDangles ++ childDangles
// Group [[allDangles]] by their [[source]].
val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*)
// For each [[source]] set of [[Dangle]]s of size 2, ensure that these
// can be connected as a source-sink pair (have opposite flipped value).
// Make the connection and mark them as [[done]].
val done = Set() ++ pairing.values.filter(_.size == 2).map {
case Seq(a, b) =>
require(a.flipped != b.flipped)
// @todo <> in chisel3 makes directionless connection.
if (a.flipped) {
a.data <> b.data
} else {
b.data <> a.data
}
a.source
case _ => None
}
// Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module.
val forward = allDangles.filter(d => !done(d.source))
// Generate [[AutoBundle]] IO from [[forward]].
val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*))
// Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]]
val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) =>
if (d.flipped) {
d.data <> io
} else {
io <> d.data
}
d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name)
}
// Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]].
wrapper.inModuleBody.reverse.foreach {
_()
}
if (wrapper.shouldBeInlined) {
chisel3.experimental.annotate(new ChiselAnnotation {
def toFirrtl = InlineAnnotation(toNamed)
})
}
// Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]].
(auto, dangles)
}
}
/** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike {
/** Instantiate hardware of this `Module`. */
val (auto, dangles) = instantiate()
}
/** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike {
// These wires are the default clock+reset for all LazyModule children.
// It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the
// [[LazyRawModuleImp]] children.
// Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly.
/** drive clock explicitly. */
val childClock: Clock = Wire(Clock())
/** drive reset explicitly. */
val childReset: Reset = Wire(Reset())
// the default is that these are disabled
childClock := false.B.asClock
childReset := chisel3.DontCare
def provideImplicitClockToLazyChildren: Boolean = false
val (auto, dangles) =
if (provideImplicitClockToLazyChildren) {
withClockAndReset(childClock, childReset) { instantiate() }
} else {
instantiate()
}
}
File MixedNode.scala:
package org.chipsalliance.diplomacy.nodes
import chisel3.{Data, DontCare, Wire}
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.{Field, Parameters}
import org.chipsalliance.diplomacy.ValName
import org.chipsalliance.diplomacy.sourceLine
/** One side metadata of a [[Dangle]].
*
* Describes one side of an edge going into or out of a [[BaseNode]].
*
* @param serial
* the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to.
* @param index
* the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to.
*/
case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] {
import scala.math.Ordered.orderingToOrdered
def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that))
}
/** [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]]
* connects.
*
* [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] ,
* [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]].
*
* @param source
* the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within
* that [[BaseNode]].
* @param sink
* sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that
* [[BaseNode]].
* @param flipped
* flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to
* `danglesIn`.
* @param dataOpt
* actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module
*/
case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) {
def data = dataOpt.get
}
/** [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often
* derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually
* implement the protocol.
*/
case class Edges[EI, EO](in: Seq[EI], out: Seq[EO])
/** A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. */
case object MonitorsEnabled extends Field[Boolean](true)
/** When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented.
*
* For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but
* [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink
* nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the
* [[LazyModule]].
*/
case object RenderFlipped extends Field[Boolean](false)
/** The sealed node class in the package, all node are derived from it.
*
* @param inner
* Sink interface implementation.
* @param outer
* Source interface implementation.
* @param valName
* val name of this node.
* @tparam DI
* Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters
* describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected
* [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port
* parameters.
* @tparam UI
* Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing
* the protocol parameters of a sink. For an [[InwardNode]], it is determined itself.
* @tparam EI
* Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers
* specified for a sink according to protocol.
* @tparam BI
* Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface.
* It should extends from [[chisel3.Data]], which represents the real hardware.
* @tparam DO
* Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters
* describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself.
* @tparam UO
* Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing
* the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]].
* Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters.
* @tparam EO
* Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers
* specified for a source according to protocol.
* @tparam BO
* Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source
* interface. It should extends from [[chisel3.Data]], which represents the real hardware.
*
* @note
* Call Graph of [[MixedNode]]
* - line `─`: source is process by a function and generate pass to others
* - Arrow `→`: target of arrow is generated by source
*
* {{{
* (from the other node)
* ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐
* ↓ │
* (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │
* [[InwardNode.accPI]] │ │ │
* │ │ (based on protocol) │
* │ │ [[MixedNode.inner.edgeI]] │
* │ │ ↓ │
* ↓ │ │ │
* (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │
* [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │
* │ │ ↑ │ │ │
* │ │ │ [[OutwardNode.doParams]] │ │
* │ │ │ (from the other node) │ │
* │ │ │ │ │ │
* │ │ │ │ │ │
* │ │ │ └────────┬──────────────┤ │
* │ │ │ │ │ │
* │ │ │ │ (based on protocol) │
* │ │ │ │ [[MixedNode.inner.edgeI]] │
* │ │ │ │ │ │
* │ │ (from the other node) │ ↓ │
* │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │
* │ ↑ ↑ │ │ ↓ │
* │ │ │ │ │ [[MixedNode.in]] │
* │ │ │ │ ↓ ↑ │
* │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │
* ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │
* │ │ │ [[MixedNode.bundleOut]]─┐ │ │
* │ │ │ ↑ ↓ │ │
* │ │ │ │ [[MixedNode.out]] │ │
* │ ↓ ↓ │ ↑ │ │
* │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │
* │ │ (from the other node) ↑ │ │
* │ │ │ │ │ │
* │ │ │ [[MixedNode.outer.edgeO]] │ │
* │ │ │ (based on protocol) │ │
* │ │ │ │ │ │
* │ │ │ ┌────────────────────────────────────────┤ │ │
* │ │ │ │ │ │ │
* │ │ │ │ │ │ │
* │ │ │ │ │ │ │
* (immobilize after elaboration)│ ↓ │ │ │ │
* [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │
* ↑ (inward port from [[OutwardNode]]) │ │ │ │
* │ ┌─────────────────────────────────────────┤ │ │ │
* │ │ │ │ │ │
* │ │ │ │ │ │
* [[OutwardNode.accPO]] │ ↓ │ │ │
* (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │
* │ ↑ │ │
* │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │
* └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘
* }}}
*/
abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data](
val inner: InwardNodeImp[DI, UI, EI, BI],
val outer: OutwardNodeImp[DO, UO, EO, BO]
)(
implicit valName: ValName)
extends BaseNode
with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO]
with InwardNode[DI, UI, BI]
with OutwardNode[DO, UO, BO] {
// Generate a [[NodeHandle]] with inward and outward node are both this node.
val inward = this
val outward = this
/** Debug info of nodes binding. */
def bindingInfo: String = s"""$iBindingInfo
|$oBindingInfo
|""".stripMargin
/** Debug info of ports connecting. */
def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}]
|${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}]
|""".stripMargin
/** Debug info of parameters propagations. */
def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}]
|${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}]
|${diParams.size} downstream inward parameters: [${diParams.mkString(",")}]
|${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}]
|""".stripMargin
/** For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and
* [[MixedNode.iPortMapping]].
*
* Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward
* stars and outward stars.
*
* This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type
* of node.
*
* @param iKnown
* Number of known-size ([[BIND_ONCE]]) input bindings.
* @param oKnown
* Number of known-size ([[BIND_ONCE]]) output bindings.
* @param iStar
* Number of unknown size ([[BIND_STAR]]) input bindings.
* @param oStar
* Number of unknown size ([[BIND_STAR]]) output bindings.
* @return
* A Tuple of the resolved number of input and output connections.
*/
protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int)
/** Function to generate downward-flowing outward params from the downward-flowing input params and the current output
* ports.
*
* @param n
* The size of the output sequence to generate.
* @param p
* Sequence of downward-flowing input parameters of this node.
* @return
* A `n`-sized sequence of downward-flowing output edge parameters.
*/
protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO]
/** Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]].
*
* @param n
* Size of the output sequence.
* @param p
* Upward-flowing output edge parameters.
* @return
* A n-sized sequence of upward-flowing input edge parameters.
*/
protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI]
/** @return
* The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with
* [[BIND_STAR]].
*/
protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR)
/** @return
* The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of
* output bindings bound with [[BIND_STAR]].
*/
protected[diplomacy] lazy val sourceCard: Int =
iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR)
/** @return list of nodes involved in flex bindings with this node. */
protected[diplomacy] lazy val flexes: Seq[BaseNode] =
oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2)
/** Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin
* greedily taking up the remaining connections.
*
* @return
* A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return
* value is not relevant.
*/
protected[diplomacy] lazy val flexOffset: Int = {
/** Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex
* operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a
* connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of
* each node in the current set and decide whether they should be added to the set or not.
*
* @return
* the mapping of [[BaseNode]] indexed by their serial numbers.
*/
def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = {
if (visited.contains(v.serial) || !v.flexibleArityDirection) {
visited
} else {
v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum))
}
}
/** Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node.
*
* @example
* {{{
* a :*=* b :*=* c
* d :*=* b
* e :*=* f
* }}}
*
* `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)`
*/
val flexSet = DFS(this, Map()).values
/** The total number of :*= operators where we're on the left. */
val allSink = flexSet.map(_.sinkCard).sum
/** The total number of :=* operators used when we're on the right. */
val allSource = flexSet.map(_.sourceCard).sum
require(
allSink == 0 || allSource == 0,
s"The nodes ${flexSet.map(_.name)} which are inter-connected by :*=* have ${allSink} :*= operators and ${allSource} :=* operators connected to them, making it impossible to determine cardinality inference direction."
)
allSink - allSource
}
/** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. */
protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = {
if (flexibleArityDirection) flexOffset
else if (n.flexibleArityDirection) n.flexOffset
else 0
}
/** For a node which is connected between two nodes, select the one that will influence the direction of the flex
* resolution.
*/
protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = {
val dir = edgeArityDirection(n)
if (dir < 0) l
else if (dir > 0) r
else 1
}
/** Ensure that the same node is not visited twice in resolving `:*=`, etc operators. */
private var starCycleGuard = false
/** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star"
* connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also
* need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct
* edge parameters and later build up correct bundle connections.
*
* [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding
* operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort
* (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N :*= foo` or `N :*=* foo :*=
* bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo :*=* N`
*/
protected[diplomacy] lazy val (
oPortMapping: Seq[(Int, Int)],
iPortMapping: Seq[(Int, Int)],
oStar: Int,
iStar: Int
) = {
try {
if (starCycleGuard) throw StarCycleException()
starCycleGuard = true
// For a given node N...
// Number of foo :=* N
// + Number of bar :=* foo :*=* N
val oStars = oBindings.count { case (_, n, b, _, _) =>
b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) < 0)
}
// Number of N :*= foo
// + Number of N :*=* foo :*= bar
val iStars = iBindings.count { case (_, n, b, _, _) =>
b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) > 0)
}
// 1 for foo := N
// + bar.iStar for bar :*= foo :*=* N
// + foo.iStar for foo :*= N
// + 0 for foo :=* N
val oKnown = oBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, 0, n.iStar)
case BIND_QUERY => n.iStar
case BIND_STAR => 0
}
}.sum
// 1 for N := foo
// + bar.oStar for N :*=* foo :=* bar
// + foo.oStar for N :=* foo
// + 0 for N :*= foo
val iKnown = iBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, n.oStar, 0)
case BIND_QUERY => n.oStar
case BIND_STAR => 0
}
}.sum
// Resolve star depends on the node subclass to implement the algorithm for this.
val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars)
// Cumulative list of resolved outward binding range starting points
val oSum = oBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar)
case BIND_QUERY => n.iStar
case BIND_STAR => oStar
}
}.scanLeft(0)(_ + _)
// Cumulative list of resolved inward binding range starting points
val iSum = iBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar)
case BIND_QUERY => n.oStar
case BIND_STAR => iStar
}
}.scanLeft(0)(_ + _)
// Create ranges for each binding based on the running sums and return
// those along with resolved values for the star operations.
(oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar)
} catch {
case c: StarCycleException => throw c.copy(loop = context +: c.loop)
}
}
/** Sequence of inward ports.
*
* This should be called after all star bindings are resolved.
*
* Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding.
* `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this
* connection was made in the source code.
*/
protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] =
oBindings.flatMap { case (i, n, _, p, s) =>
// for each binding operator in this node, look at what it connects to
val (start, end) = n.iPortMapping(i)
(start until end).map { j => (j, n, p, s) }
}
/** Sequence of outward ports.
*
* This should be called after all star bindings are resolved.
*
* `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of
* outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection
* was made in the source code.
*/
protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] =
iBindings.flatMap { case (i, n, _, p, s) =>
// query this port index range of this node in the other side of node.
val (start, end) = n.oPortMapping(i)
(start until end).map { j => (j, n, p, s) }
}
// Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree
// Thus, there must exist an Eulerian path and the below algorithms terminate
@scala.annotation.tailrec
private def oTrace(
tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)
): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match {
case (i, n, p, s) => n.iForward(i) match {
case None => (i, n, p, s)
case Some((j, m)) => oTrace((j, m, p, s))
}
}
@scala.annotation.tailrec
private def iTrace(
tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)
): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match {
case (i, n, p, s) => n.oForward(i) match {
case None => (i, n, p, s)
case Some((j, m)) => iTrace((j, m, p, s))
}
}
/** Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved.
*
* Each Port is a tuple of:
* - Numeric index of this binding in the [[InwardNode]] on the other end.
* - [[InwardNode]] on the other end of this binding.
* - A view of [[Parameters]] where the binding occurred.
* - [[SourceInfo]] for source-level error reporting.
*/
lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace)
/** Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved.
*
* Each Port is a tuple of:
* - numeric index of this binding in [[OutwardNode]] on the other end.
* - [[OutwardNode]] on the other end of this binding.
* - a view of [[Parameters]] where the binding occurred.
* - [[SourceInfo]] for source-level error reporting.
*/
lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace)
private var oParamsCycleGuard = false
protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) }
protected[diplomacy] lazy val doParams: Seq[DO] = {
try {
if (oParamsCycleGuard) throw DownwardCycleException()
oParamsCycleGuard = true
val o = mapParamsD(oPorts.size, diParams)
require(
o.size == oPorts.size,
s"""Diplomacy has detected a problem with your graph:
|At the following node, the number of outward ports should equal the number of produced outward parameters.
|$context
|$connectedPortsInfo
|Downstreamed inward parameters: [${diParams.mkString(",")}]
|Produced outward parameters: [${o.mkString(",")}]
|""".stripMargin
)
o.map(outer.mixO(_, this))
} catch {
case c: DownwardCycleException => throw c.copy(loop = context +: c.loop)
}
}
private var iParamsCycleGuard = false
protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) }
protected[diplomacy] lazy val uiParams: Seq[UI] = {
try {
if (iParamsCycleGuard) throw UpwardCycleException()
iParamsCycleGuard = true
val i = mapParamsU(iPorts.size, uoParams)
require(
i.size == iPorts.size,
s"""Diplomacy has detected a problem with your graph:
|At the following node, the number of inward ports should equal the number of produced inward parameters.
|$context
|$connectedPortsInfo
|Upstreamed outward parameters: [${uoParams.mkString(",")}]
|Produced inward parameters: [${i.mkString(",")}]
|""".stripMargin
)
i.map(inner.mixI(_, this))
} catch {
case c: UpwardCycleException => throw c.copy(loop = context +: c.loop)
}
}
/** Outward edge parameters. */
protected[diplomacy] lazy val edgesOut: Seq[EO] =
(oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) }
/** Inward edge parameters. */
protected[diplomacy] lazy val edgesIn: Seq[EI] =
(iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) }
/** A tuple of the input edge parameters and output edge parameters for the edges bound to this node.
*
* If you need to access to the edges of a foreign Node, use this method (in/out create bundles).
*/
lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut)
/** Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. */
protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e =>
val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out")
// TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue,
// In the future, we should add an option to decide whether allowing unconnected in the LazyModule
x := DontCare
x
}
/** Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. */
protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e =>
val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In")
// TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue,
// In the future, we should add an option to decide whether allowing unconnected in the LazyModule
x := DontCare
x
}
private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) =>
Dangle(
source = HalfEdge(serial, i),
sink = HalfEdge(n.serial, j),
flipped = false,
name = wirePrefix + "out",
dataOpt = None
)
}
private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) =>
Dangle(
source = HalfEdge(n.serial, j),
sink = HalfEdge(serial, i),
flipped = true,
name = wirePrefix + "in",
dataOpt = None
)
}
/** Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. */
protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) =>
d.copy(dataOpt = Some(bundleOut(i)))
}
/** Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. */
protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) =>
d.copy(dataOpt = Some(bundleIn(i)))
}
private[diplomacy] var instantiated = false
/** Gather Bundle and edge parameters of outward ports.
*
* Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within
* [[LazyModuleImp]] code or after its instantiation has completed.
*/
def out: Seq[(BO, EO)] = {
require(
instantiated,
s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun"
)
bundleOut.zip(edgesOut)
}
/** Gather Bundle and edge parameters of inward ports.
*
* Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within
* [[LazyModuleImp]] code or after its instantiation has completed.
*/
def in: Seq[(BI, EI)] = {
require(
instantiated,
s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun"
)
bundleIn.zip(edgesIn)
}
/** Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires,
* instantiate monitors on all input ports if appropriate, and return all the dangles of this node.
*/
protected[diplomacy] def instantiate(): Seq[Dangle] = {
instantiated = true
if (!circuitIdentity) {
(iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) }
}
danglesOut ++ danglesIn
}
protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn
/** Connects the outward part of a node with the inward part of this node. */
protected[diplomacy] def bind(
h: OutwardNode[DI, UI, BI],
binding: NodeBinding
)(
implicit p: Parameters,
sourceInfo: SourceInfo
): Unit = {
val x = this // x := y
val y = h
sourceLine(sourceInfo, " at ", "")
val i = x.iPushed
val o = y.oPushed
y.oPush(
i,
x,
binding match {
case BIND_ONCE => BIND_ONCE
case BIND_FLEX => BIND_FLEX
case BIND_STAR => BIND_QUERY
case BIND_QUERY => BIND_STAR
}
)
x.iPush(o, y, binding)
}
/* Metadata for printing the node graph. */
def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) =>
val re = inner.render(e)
(n, re.copy(flipped = re.flipped != p(RenderFlipped)))
}
/** Metadata for printing the node graph */
def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) }
}
| module TLBuffer_a21d64s7k1z3u( // @[Buffer.scala:40:9]
input clock, // @[Buffer.scala:40:9]
input reset, // @[Buffer.scala:40:9]
output auto_in_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_in_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [6:0] auto_in_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [20:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_in_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_in_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_in_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_in_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_in_d_bits_param, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_in_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [6:0] auto_in_d_bits_source, // @[LazyModuleImp.scala:107:25]
output auto_in_d_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_in_d_bits_denied, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_in_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_out_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_out_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [6:0] auto_out_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [20:0] auto_out_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_out_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_out_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_out_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_out_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [6:0] auto_out_d_bits_source, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_out_d_bits_data // @[LazyModuleImp.scala:107:25]
);
wire auto_in_a_valid_0 = auto_in_a_valid; // @[Buffer.scala:40:9]
wire [2:0] auto_in_a_bits_opcode_0 = auto_in_a_bits_opcode; // @[Buffer.scala:40:9]
wire [2:0] auto_in_a_bits_param_0 = auto_in_a_bits_param; // @[Buffer.scala:40:9]
wire [2:0] auto_in_a_bits_size_0 = auto_in_a_bits_size; // @[Buffer.scala:40:9]
wire [6:0] auto_in_a_bits_source_0 = auto_in_a_bits_source; // @[Buffer.scala:40:9]
wire [20:0] auto_in_a_bits_address_0 = auto_in_a_bits_address; // @[Buffer.scala:40:9]
wire [7:0] auto_in_a_bits_mask_0 = auto_in_a_bits_mask; // @[Buffer.scala:40:9]
wire [63:0] auto_in_a_bits_data_0 = auto_in_a_bits_data; // @[Buffer.scala:40:9]
wire auto_in_a_bits_corrupt_0 = auto_in_a_bits_corrupt; // @[Buffer.scala:40:9]
wire auto_in_d_ready_0 = auto_in_d_ready; // @[Buffer.scala:40:9]
wire auto_out_a_ready_0 = auto_out_a_ready; // @[Buffer.scala:40:9]
wire auto_out_d_valid_0 = auto_out_d_valid; // @[Buffer.scala:40:9]
wire [2:0] auto_out_d_bits_opcode_0 = auto_out_d_bits_opcode; // @[Buffer.scala:40:9]
wire [2:0] auto_out_d_bits_size_0 = auto_out_d_bits_size; // @[Buffer.scala:40:9]
wire [6:0] auto_out_d_bits_source_0 = auto_out_d_bits_source; // @[Buffer.scala:40:9]
wire [63:0] auto_out_d_bits_data_0 = auto_out_d_bits_data; // @[Buffer.scala:40:9]
wire auto_out_d_bits_sink = 1'h0; // @[Decoupled.scala:362:21]
wire auto_out_d_bits_denied = 1'h0; // @[Decoupled.scala:362:21]
wire auto_out_d_bits_corrupt = 1'h0; // @[Decoupled.scala:362:21]
wire nodeOut_d_bits_sink = 1'h0; // @[Decoupled.scala:362:21]
wire nodeOut_d_bits_denied = 1'h0; // @[Decoupled.scala:362:21]
wire nodeOut_d_bits_corrupt = 1'h0; // @[Decoupled.scala:362:21]
wire [1:0] auto_out_d_bits_param = 2'h0; // @[Decoupled.scala:362:21]
wire nodeIn_a_ready; // @[MixedNode.scala:551:17]
wire [1:0] nodeOut_d_bits_param = 2'h0; // @[Decoupled.scala:362:21]
wire nodeIn_a_valid = auto_in_a_valid_0; // @[Buffer.scala:40:9]
wire [2:0] nodeIn_a_bits_opcode = auto_in_a_bits_opcode_0; // @[Buffer.scala:40:9]
wire [2:0] nodeIn_a_bits_param = auto_in_a_bits_param_0; // @[Buffer.scala:40:9]
wire [2:0] nodeIn_a_bits_size = auto_in_a_bits_size_0; // @[Buffer.scala:40:9]
wire [6:0] nodeIn_a_bits_source = auto_in_a_bits_source_0; // @[Buffer.scala:40:9]
wire [20:0] nodeIn_a_bits_address = auto_in_a_bits_address_0; // @[Buffer.scala:40:9]
wire [7:0] nodeIn_a_bits_mask = auto_in_a_bits_mask_0; // @[Buffer.scala:40:9]
wire [63:0] nodeIn_a_bits_data = auto_in_a_bits_data_0; // @[Buffer.scala:40:9]
wire nodeIn_a_bits_corrupt = auto_in_a_bits_corrupt_0; // @[Buffer.scala:40:9]
wire nodeIn_d_ready = auto_in_d_ready_0; // @[Buffer.scala:40:9]
wire nodeIn_d_valid; // @[MixedNode.scala:551:17]
wire [2:0] nodeIn_d_bits_opcode; // @[MixedNode.scala:551:17]
wire [1:0] nodeIn_d_bits_param; // @[MixedNode.scala:551:17]
wire [2:0] nodeIn_d_bits_size; // @[MixedNode.scala:551:17]
wire [6:0] nodeIn_d_bits_source; // @[MixedNode.scala:551:17]
wire nodeIn_d_bits_sink; // @[MixedNode.scala:551:17]
wire nodeIn_d_bits_denied; // @[MixedNode.scala:551:17]
wire [63:0] nodeIn_d_bits_data; // @[MixedNode.scala:551:17]
wire nodeIn_d_bits_corrupt; // @[MixedNode.scala:551:17]
wire nodeOut_a_ready = auto_out_a_ready_0; // @[Buffer.scala:40:9]
wire nodeOut_a_valid; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_a_bits_param; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_a_bits_size; // @[MixedNode.scala:542:17]
wire [6:0] nodeOut_a_bits_source; // @[MixedNode.scala:542:17]
wire [20:0] nodeOut_a_bits_address; // @[MixedNode.scala:542:17]
wire [7:0] nodeOut_a_bits_mask; // @[MixedNode.scala:542:17]
wire [63:0] nodeOut_a_bits_data; // @[MixedNode.scala:542:17]
wire nodeOut_a_bits_corrupt; // @[MixedNode.scala:542:17]
wire nodeOut_d_ready; // @[MixedNode.scala:542:17]
wire nodeOut_d_valid = auto_out_d_valid_0; // @[Buffer.scala:40:9]
wire [2:0] nodeOut_d_bits_opcode = auto_out_d_bits_opcode_0; // @[Buffer.scala:40:9]
wire [2:0] nodeOut_d_bits_size = auto_out_d_bits_size_0; // @[Buffer.scala:40:9]
wire [6:0] nodeOut_d_bits_source = auto_out_d_bits_source_0; // @[Buffer.scala:40:9]
wire [63:0] nodeOut_d_bits_data = auto_out_d_bits_data_0; // @[Buffer.scala:40:9]
wire auto_in_a_ready_0; // @[Buffer.scala:40:9]
wire [2:0] auto_in_d_bits_opcode_0; // @[Buffer.scala:40:9]
wire [1:0] auto_in_d_bits_param_0; // @[Buffer.scala:40:9]
wire [2:0] auto_in_d_bits_size_0; // @[Buffer.scala:40:9]
wire [6:0] auto_in_d_bits_source_0; // @[Buffer.scala:40:9]
wire auto_in_d_bits_sink_0; // @[Buffer.scala:40:9]
wire auto_in_d_bits_denied_0; // @[Buffer.scala:40:9]
wire [63:0] auto_in_d_bits_data_0; // @[Buffer.scala:40:9]
wire auto_in_d_bits_corrupt_0; // @[Buffer.scala:40:9]
wire auto_in_d_valid_0; // @[Buffer.scala:40:9]
wire [2:0] auto_out_a_bits_opcode_0; // @[Buffer.scala:40:9]
wire [2:0] auto_out_a_bits_param_0; // @[Buffer.scala:40:9]
wire [2:0] auto_out_a_bits_size_0; // @[Buffer.scala:40:9]
wire [6:0] auto_out_a_bits_source_0; // @[Buffer.scala:40:9]
wire [20:0] auto_out_a_bits_address_0; // @[Buffer.scala:40:9]
wire [7:0] auto_out_a_bits_mask_0; // @[Buffer.scala:40:9]
wire [63:0] auto_out_a_bits_data_0; // @[Buffer.scala:40:9]
wire auto_out_a_bits_corrupt_0; // @[Buffer.scala:40:9]
wire auto_out_a_valid_0; // @[Buffer.scala:40:9]
wire auto_out_d_ready_0; // @[Buffer.scala:40:9]
assign auto_in_a_ready_0 = nodeIn_a_ready; // @[Buffer.scala:40:9]
assign auto_in_d_valid_0 = nodeIn_d_valid; // @[Buffer.scala:40:9]
assign auto_in_d_bits_opcode_0 = nodeIn_d_bits_opcode; // @[Buffer.scala:40:9]
assign auto_in_d_bits_param_0 = nodeIn_d_bits_param; // @[Buffer.scala:40:9]
assign auto_in_d_bits_size_0 = nodeIn_d_bits_size; // @[Buffer.scala:40:9]
assign auto_in_d_bits_source_0 = nodeIn_d_bits_source; // @[Buffer.scala:40:9]
assign auto_in_d_bits_sink_0 = nodeIn_d_bits_sink; // @[Buffer.scala:40:9]
assign auto_in_d_bits_denied_0 = nodeIn_d_bits_denied; // @[Buffer.scala:40:9]
assign auto_in_d_bits_data_0 = nodeIn_d_bits_data; // @[Buffer.scala:40:9]
assign auto_in_d_bits_corrupt_0 = nodeIn_d_bits_corrupt; // @[Buffer.scala:40:9]
assign auto_out_a_valid_0 = nodeOut_a_valid; // @[Buffer.scala:40:9]
assign auto_out_a_bits_opcode_0 = nodeOut_a_bits_opcode; // @[Buffer.scala:40:9]
assign auto_out_a_bits_param_0 = nodeOut_a_bits_param; // @[Buffer.scala:40:9]
assign auto_out_a_bits_size_0 = nodeOut_a_bits_size; // @[Buffer.scala:40:9]
assign auto_out_a_bits_source_0 = nodeOut_a_bits_source; // @[Buffer.scala:40:9]
assign auto_out_a_bits_address_0 = nodeOut_a_bits_address; // @[Buffer.scala:40:9]
assign auto_out_a_bits_mask_0 = nodeOut_a_bits_mask; // @[Buffer.scala:40:9]
assign auto_out_a_bits_data_0 = nodeOut_a_bits_data; // @[Buffer.scala:40:9]
assign auto_out_a_bits_corrupt_0 = nodeOut_a_bits_corrupt; // @[Buffer.scala:40:9]
assign auto_out_d_ready_0 = nodeOut_d_ready; // @[Buffer.scala:40:9]
TLMonitor_27 monitor ( // @[Nodes.scala:27:25]
.clock (clock),
.reset (reset),
.io_in_a_ready (nodeIn_a_ready), // @[MixedNode.scala:551:17]
.io_in_a_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17]
.io_in_a_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17]
.io_in_a_bits_param (nodeIn_a_bits_param), // @[MixedNode.scala:551:17]
.io_in_a_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17]
.io_in_a_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17]
.io_in_a_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17]
.io_in_a_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17]
.io_in_a_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17]
.io_in_a_bits_corrupt (nodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17]
.io_in_d_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17]
.io_in_d_valid (nodeIn_d_valid), // @[MixedNode.scala:551:17]
.io_in_d_bits_opcode (nodeIn_d_bits_opcode), // @[MixedNode.scala:551:17]
.io_in_d_bits_param (nodeIn_d_bits_param), // @[MixedNode.scala:551:17]
.io_in_d_bits_size (nodeIn_d_bits_size), // @[MixedNode.scala:551:17]
.io_in_d_bits_source (nodeIn_d_bits_source), // @[MixedNode.scala:551:17]
.io_in_d_bits_sink (nodeIn_d_bits_sink), // @[MixedNode.scala:551:17]
.io_in_d_bits_denied (nodeIn_d_bits_denied), // @[MixedNode.scala:551:17]
.io_in_d_bits_data (nodeIn_d_bits_data), // @[MixedNode.scala:551:17]
.io_in_d_bits_corrupt (nodeIn_d_bits_corrupt) // @[MixedNode.scala:551:17]
); // @[Nodes.scala:27:25]
Queue2_TLBundleA_a21d64s7k1z3u nodeOut_a_q ( // @[Decoupled.scala:362:21]
.clock (clock),
.reset (reset),
.io_enq_ready (nodeIn_a_ready),
.io_enq_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17]
.io_enq_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17]
.io_enq_bits_param (nodeIn_a_bits_param), // @[MixedNode.scala:551:17]
.io_enq_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17]
.io_enq_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17]
.io_enq_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17]
.io_enq_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17]
.io_enq_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17]
.io_enq_bits_corrupt (nodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17]
.io_deq_ready (nodeOut_a_ready), // @[MixedNode.scala:542:17]
.io_deq_valid (nodeOut_a_valid),
.io_deq_bits_opcode (nodeOut_a_bits_opcode),
.io_deq_bits_param (nodeOut_a_bits_param),
.io_deq_bits_size (nodeOut_a_bits_size),
.io_deq_bits_source (nodeOut_a_bits_source),
.io_deq_bits_address (nodeOut_a_bits_address),
.io_deq_bits_mask (nodeOut_a_bits_mask),
.io_deq_bits_data (nodeOut_a_bits_data),
.io_deq_bits_corrupt (nodeOut_a_bits_corrupt)
); // @[Decoupled.scala:362:21]
Queue2_TLBundleD_a21d64s7k1z3u nodeIn_d_q ( // @[Decoupled.scala:362:21]
.clock (clock),
.reset (reset),
.io_enq_ready (nodeOut_d_ready),
.io_enq_valid (nodeOut_d_valid), // @[MixedNode.scala:542:17]
.io_enq_bits_opcode (nodeOut_d_bits_opcode), // @[MixedNode.scala:542:17]
.io_enq_bits_size (nodeOut_d_bits_size), // @[MixedNode.scala:542:17]
.io_enq_bits_source (nodeOut_d_bits_source), // @[MixedNode.scala:542:17]
.io_enq_bits_data (nodeOut_d_bits_data), // @[MixedNode.scala:542:17]
.io_deq_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17]
.io_deq_valid (nodeIn_d_valid),
.io_deq_bits_opcode (nodeIn_d_bits_opcode),
.io_deq_bits_param (nodeIn_d_bits_param),
.io_deq_bits_size (nodeIn_d_bits_size),
.io_deq_bits_source (nodeIn_d_bits_source),
.io_deq_bits_sink (nodeIn_d_bits_sink),
.io_deq_bits_denied (nodeIn_d_bits_denied),
.io_deq_bits_data (nodeIn_d_bits_data),
.io_deq_bits_corrupt (nodeIn_d_bits_corrupt)
); // @[Decoupled.scala:362:21]
assign auto_in_a_ready = auto_in_a_ready_0; // @[Buffer.scala:40:9]
assign auto_in_d_valid = auto_in_d_valid_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_opcode = auto_in_d_bits_opcode_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_param = auto_in_d_bits_param_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_size = auto_in_d_bits_size_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_source = auto_in_d_bits_source_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_sink = auto_in_d_bits_sink_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_denied = auto_in_d_bits_denied_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_data = auto_in_d_bits_data_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_corrupt = auto_in_d_bits_corrupt_0; // @[Buffer.scala:40:9]
assign auto_out_a_valid = auto_out_a_valid_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_opcode = auto_out_a_bits_opcode_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_param = auto_out_a_bits_param_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_size = auto_out_a_bits_size_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_source = auto_out_a_bits_source_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_address = auto_out_a_bits_address_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_mask = auto_out_a_bits_mask_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_data = auto_out_a_bits_data_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_corrupt = auto_out_a_bits_corrupt_0; // @[Buffer.scala:40:9]
assign auto_out_d_ready = auto_out_d_ready_0; // @[Buffer.scala:40:9]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File util.scala:
//******************************************************************************
// Copyright (c) 2015 - 2019, The Regents of the University of California (Regents).
// All Rights Reserved. See LICENSE and LICENSE.SiFive for license details.
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
// Utility Functions
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
package boom.v4.util
import chisel3._
import chisel3.util._
import freechips.rocketchip.rocket.Instructions._
import freechips.rocketchip.rocket._
import freechips.rocketchip.util.{Str}
import org.chipsalliance.cde.config.{Parameters}
import freechips.rocketchip.tile.{TileKey}
import boom.v4.common.{MicroOp}
import boom.v4.exu.{BrUpdateInfo}
/**
* Object to XOR fold a input register of fullLength into a compressedLength.
*/
object Fold
{
def apply(input: UInt, compressedLength: Int, fullLength: Int): UInt = {
val clen = compressedLength
val hlen = fullLength
if (hlen <= clen) {
input
} else {
var res = 0.U(clen.W)
var remaining = input.asUInt
for (i <- 0 to hlen-1 by clen) {
val len = if (i + clen > hlen ) (hlen - i) else clen
require(len > 0)
res = res(clen-1,0) ^ remaining(len-1,0)
remaining = remaining >> len.U
}
res
}
}
}
/**
* Object to check if MicroOp was killed due to a branch mispredict.
* Uses "Fast" branch masks
*/
object IsKilledByBranch
{
def apply(brupdate: BrUpdateInfo, flush: Bool, uop: MicroOp): Bool = {
return apply(brupdate, flush, uop.br_mask)
}
def apply(brupdate: BrUpdateInfo, flush: Bool, uop_mask: UInt): Bool = {
return maskMatch(brupdate.b1.mispredict_mask, uop_mask) || flush
}
def apply[T <: boom.v4.common.HasBoomUOP](brupdate: BrUpdateInfo, flush: Bool, bundle: T): Bool = {
return apply(brupdate, flush, bundle.uop)
}
def apply[T <: boom.v4.common.HasBoomUOP](brupdate: BrUpdateInfo, flush: Bool, bundle: Valid[T]): Bool = {
return apply(brupdate, flush, bundle.bits)
}
}
/**
* Object to return new MicroOp with a new BR mask given a MicroOp mask
* and old BR mask.
*/
object GetNewUopAndBrMask
{
def apply(uop: MicroOp, brupdate: BrUpdateInfo)
(implicit p: Parameters): MicroOp = {
val newuop = WireInit(uop)
newuop.br_mask := uop.br_mask & ~brupdate.b1.resolve_mask
newuop
}
}
/**
* Object to return a BR mask given a MicroOp mask and old BR mask.
*/
object GetNewBrMask
{
def apply(brupdate: BrUpdateInfo, uop: MicroOp): UInt = {
return uop.br_mask & ~brupdate.b1.resolve_mask
}
def apply(brupdate: BrUpdateInfo, br_mask: UInt): UInt = {
return br_mask & ~brupdate.b1.resolve_mask
}
}
object UpdateBrMask
{
def apply(brupdate: BrUpdateInfo, uop: MicroOp): MicroOp = {
val out = WireInit(uop)
out.br_mask := GetNewBrMask(brupdate, uop)
out
}
def apply[T <: boom.v4.common.HasBoomUOP](brupdate: BrUpdateInfo, bundle: T): T = {
val out = WireInit(bundle)
out.uop.br_mask := GetNewBrMask(brupdate, bundle.uop.br_mask)
out
}
def apply[T <: boom.v4.common.HasBoomUOP](brupdate: BrUpdateInfo, flush: Bool, bundle: Valid[T]): Valid[T] = {
val out = WireInit(bundle)
out.bits.uop.br_mask := GetNewBrMask(brupdate, bundle.bits.uop.br_mask)
out.valid := bundle.valid && !IsKilledByBranch(brupdate, flush, bundle.bits.uop.br_mask)
out
}
}
/**
* Object to check if at least 1 bit matches in two masks
*/
object maskMatch
{
def apply(msk1: UInt, msk2: UInt): Bool = (msk1 & msk2) =/= 0.U
}
/**
* Object to clear one bit in a mask given an index
*/
object clearMaskBit
{
def apply(msk: UInt, idx: UInt): UInt = (msk & ~(1.U << idx))(msk.getWidth-1, 0)
}
/**
* Object to shift a register over by one bit and concat a new one
*/
object PerformShiftRegister
{
def apply(reg_val: UInt, new_bit: Bool): UInt = {
reg_val := Cat(reg_val(reg_val.getWidth-1, 0).asUInt, new_bit.asUInt).asUInt
reg_val
}
}
/**
* Object to shift a register over by one bit, wrapping the top bit around to the bottom
* (XOR'ed with a new-bit), and evicting a bit at index HLEN.
* This is used to simulate a longer HLEN-width shift register that is folded
* down to a compressed CLEN.
*/
object PerformCircularShiftRegister
{
def apply(csr: UInt, new_bit: Bool, evict_bit: Bool, hlen: Int, clen: Int): UInt = {
val carry = csr(clen-1)
val newval = Cat(csr, new_bit ^ carry) ^ (evict_bit << (hlen % clen).U)
newval
}
}
/**
* Object to increment an input value, wrapping it if
* necessary.
*/
object WrapAdd
{
// "n" is the number of increments, so we wrap at n-1.
def apply(value: UInt, amt: UInt, n: Int): UInt = {
if (isPow2(n)) {
(value + amt)(log2Ceil(n)-1,0)
} else {
val sum = Cat(0.U(1.W), value) + Cat(0.U(1.W), amt)
Mux(sum >= n.U,
sum - n.U,
sum)
}
}
}
/**
* Object to decrement an input value, wrapping it if
* necessary.
*/
object WrapSub
{
// "n" is the number of increments, so we wrap to n-1.
def apply(value: UInt, amt: Int, n: Int): UInt = {
if (isPow2(n)) {
(value - amt.U)(log2Ceil(n)-1,0)
} else {
val v = Cat(0.U(1.W), value)
val b = Cat(0.U(1.W), amt.U)
Mux(value >= amt.U,
value - amt.U,
n.U - amt.U + value)
}
}
}
/**
* Object to increment an input value, wrapping it if
* necessary.
*/
object WrapInc
{
// "n" is the number of increments, so we wrap at n-1.
def apply(value: UInt, n: Int): UInt = {
if (isPow2(n)) {
(value + 1.U)(log2Ceil(n)-1,0)
} else {
val wrap = (value === (n-1).U)
Mux(wrap, 0.U, value + 1.U)
}
}
}
/**
* Object to decrement an input value, wrapping it if
* necessary.
*/
object WrapDec
{
// "n" is the number of increments, so we wrap at n-1.
def apply(value: UInt, n: Int): UInt = {
if (isPow2(n)) {
(value - 1.U)(log2Ceil(n)-1,0)
} else {
val wrap = (value === 0.U)
Mux(wrap, (n-1).U, value - 1.U)
}
}
}
/**
* Object to mask off lower bits of a PC to align to a "b"
* Byte boundary.
*/
object AlignPCToBoundary
{
def apply(pc: UInt, b: Int): UInt = {
// Invert for scenario where pc longer than b
// (which would clear all bits above size(b)).
~(~pc | (b-1).U)
}
}
/**
* Object to rotate a signal left by one
*/
object RotateL1
{
def apply(signal: UInt): UInt = {
val w = signal.getWidth
val out = Cat(signal(w-2,0), signal(w-1))
return out
}
}
/**
* Object to sext a value to a particular length.
*/
object Sext
{
def apply(x: UInt, length: Int): UInt = {
if (x.getWidth == length) return x
else return Cat(Fill(length-x.getWidth, x(x.getWidth-1)), x)
}
}
/**
* Object to translate from BOOM's special "packed immediate" to a 32b signed immediate
* Asking for U-type gives it shifted up 12 bits.
*/
object ImmGen
{
import boom.v4.common.{LONGEST_IMM_SZ, IS_B, IS_I, IS_J, IS_S, IS_U, IS_N}
def apply(i: UInt, isel: UInt): UInt = {
val ip = Mux(isel === IS_N, 0.U(LONGEST_IMM_SZ.W), i)
val sign = ip(LONGEST_IMM_SZ-1).asSInt
val i30_20 = Mux(isel === IS_U, ip(18,8).asSInt, sign)
val i19_12 = Mux(isel === IS_U || isel === IS_J, ip(7,0).asSInt, sign)
val i11 = Mux(isel === IS_U, 0.S,
Mux(isel === IS_J || isel === IS_B, ip(8).asSInt, sign))
val i10_5 = Mux(isel === IS_U, 0.S, ip(18,14).asSInt)
val i4_1 = Mux(isel === IS_U, 0.S, ip(13,9).asSInt)
val i0 = Mux(isel === IS_S || isel === IS_I, ip(8).asSInt, 0.S)
return Cat(sign, i30_20, i19_12, i11, i10_5, i4_1, i0)
}
}
/**
* Object to see if an instruction is a JALR.
*/
object DebugIsJALR
{
def apply(inst: UInt): Bool = {
// TODO Chisel not sure why this won't compile
// val is_jalr = rocket.DecodeLogic(inst, List(Bool(false)),
// Array(
// JALR -> Bool(true)))
inst(6,0) === "b1100111".U
}
}
/**
* Object to take an instruction and output its branch or jal target. Only used
* for a debug assert (no where else would we jump straight from instruction
* bits to a target).
*/
object DebugGetBJImm
{
def apply(inst: UInt): UInt = {
// TODO Chisel not sure why this won't compile
//val csignals =
//rocket.DecodeLogic(inst,
// List(Bool(false), Bool(false)),
// Array(
// BEQ -> List(Bool(true ), Bool(false)),
// BNE -> List(Bool(true ), Bool(false)),
// BGE -> List(Bool(true ), Bool(false)),
// BGEU -> List(Bool(true ), Bool(false)),
// BLT -> List(Bool(true ), Bool(false)),
// BLTU -> List(Bool(true ), Bool(false))
// ))
//val is_br :: nothing :: Nil = csignals
val is_br = (inst(6,0) === "b1100011".U)
val br_targ = Cat(Fill(12, inst(31)), Fill(8,inst(31)), inst(7), inst(30,25), inst(11,8), 0.U(1.W))
val jal_targ= Cat(Fill(12, inst(31)), inst(19,12), inst(20), inst(30,25), inst(24,21), 0.U(1.W))
Mux(is_br, br_targ, jal_targ)
}
}
/**
* Object to return the lowest bit position after the head.
*/
object AgePriorityEncoder
{
def apply(in: Seq[Bool], head: UInt): UInt = {
val n = in.size
val width = log2Ceil(in.size)
val n_padded = 1 << width
val temp_vec = (0 until n_padded).map(i => if (i < n) in(i) && i.U >= head else false.B) ++ in
val idx = PriorityEncoder(temp_vec)
idx(width-1, 0) //discard msb
}
}
/**
* Object to determine whether queue
* index i0 is older than index i1.
*/
object IsOlder
{
def apply(i0: UInt, i1: UInt, head: UInt) = ((i0 < i1) ^ (i0 < head) ^ (i1 < head))
}
object IsYoungerMask
{
def apply(i: UInt, head: UInt, n: Integer): UInt = {
val hi_mask = ~MaskLower(UIntToOH(i)(n-1,0))
val lo_mask = ~MaskUpper(UIntToOH(head)(n-1,0))
Mux(i < head, hi_mask & lo_mask, hi_mask | lo_mask)(n-1,0)
}
}
/**
* Set all bits at or below the highest order '1'.
*/
object MaskLower
{
def apply(in: UInt) = {
val n = in.getWidth
(0 until n).map(i => in >> i.U).reduce(_|_)
}
}
/**
* Set all bits at or above the lowest order '1'.
*/
object MaskUpper
{
def apply(in: UInt) = {
val n = in.getWidth
(0 until n).map(i => (in << i.U)(n-1,0)).reduce(_|_)
}
}
/**
* Transpose a matrix of Chisel Vecs.
*/
object Transpose
{
def apply[T <: chisel3.Data](in: Vec[Vec[T]]) = {
val n = in(0).size
VecInit((0 until n).map(i => VecInit(in.map(row => row(i)))))
}
}
/**
* N-wide one-hot priority encoder.
*/
object SelectFirstN
{
def apply(in: UInt, n: Int) = {
val sels = Wire(Vec(n, UInt(in.getWidth.W)))
var mask = in
for (i <- 0 until n) {
sels(i) := PriorityEncoderOH(mask)
mask = mask & ~sels(i)
}
sels
}
}
/**
* Connect the first k of n valid input interfaces to k output interfaces.
*/
class Compactor[T <: chisel3.Data](n: Int, k: Int, gen: T) extends Module
{
require(n >= k)
val io = IO(new Bundle {
val in = Vec(n, Flipped(DecoupledIO(gen)))
val out = Vec(k, DecoupledIO(gen))
})
if (n == k) {
io.out <> io.in
} else {
val counts = io.in.map(_.valid).scanLeft(1.U(k.W)) ((c,e) => Mux(e, (c<<1)(k-1,0), c))
val sels = Transpose(VecInit(counts map (c => VecInit(c.asBools)))) map (col =>
(col zip io.in.map(_.valid)) map {case (c,v) => c && v})
val in_readys = counts map (row => (row.asBools zip io.out.map(_.ready)) map {case (c,r) => c && r} reduce (_||_))
val out_valids = sels map (col => col.reduce(_||_))
val out_data = sels map (s => Mux1H(s, io.in.map(_.bits)))
in_readys zip io.in foreach {case (r,i) => i.ready := r}
out_valids zip out_data zip io.out foreach {case ((v,d),o) => o.valid := v; o.bits := d}
}
}
/**
* Create a queue that can be killed with a branch kill signal.
* Assumption: enq.valid only high if not killed by branch (so don't check IsKilled on io.enq).
*/
class BranchKillableQueue[T <: boom.v4.common.HasBoomUOP](gen: T, entries: Int, flush_fn: boom.v4.common.MicroOp => Bool = u => true.B, fastDeq: Boolean = false)
(implicit p: org.chipsalliance.cde.config.Parameters)
extends boom.v4.common.BoomModule()(p)
with boom.v4.common.HasBoomCoreParameters
{
val io = IO(new Bundle {
val enq = Flipped(Decoupled(gen))
val deq = Decoupled(gen)
val brupdate = Input(new BrUpdateInfo())
val flush = Input(Bool())
val empty = Output(Bool())
val count = Output(UInt(log2Ceil(entries).W))
})
if (fastDeq && entries > 1) {
// Pipeline dequeue selection so the mux gets an entire cycle
val main = Module(new BranchKillableQueue(gen, entries-1, flush_fn, false))
val out_reg = Reg(gen)
val out_valid = RegInit(false.B)
val out_uop = Reg(new MicroOp)
main.io.enq <> io.enq
main.io.brupdate := io.brupdate
main.io.flush := io.flush
io.empty := main.io.empty && !out_valid
io.count := main.io.count + out_valid
io.deq.valid := out_valid
io.deq.bits := out_reg
io.deq.bits.uop := out_uop
out_uop := UpdateBrMask(io.brupdate, out_uop)
out_valid := out_valid && !IsKilledByBranch(io.brupdate, false.B, out_uop) && !(io.flush && flush_fn(out_uop))
main.io.deq.ready := false.B
when (io.deq.fire || !out_valid) {
out_valid := main.io.deq.valid && !IsKilledByBranch(io.brupdate, false.B, main.io.deq.bits.uop) && !(io.flush && flush_fn(main.io.deq.bits.uop))
out_reg := main.io.deq.bits
out_uop := UpdateBrMask(io.brupdate, main.io.deq.bits.uop)
main.io.deq.ready := true.B
}
} else {
val ram = Mem(entries, gen)
val valids = RegInit(VecInit(Seq.fill(entries) {false.B}))
val uops = Reg(Vec(entries, new MicroOp))
val enq_ptr = Counter(entries)
val deq_ptr = Counter(entries)
val maybe_full = RegInit(false.B)
val ptr_match = enq_ptr.value === deq_ptr.value
io.empty := ptr_match && !maybe_full
val full = ptr_match && maybe_full
val do_enq = WireInit(io.enq.fire && !IsKilledByBranch(io.brupdate, false.B, io.enq.bits.uop) && !(io.flush && flush_fn(io.enq.bits.uop)))
val do_deq = WireInit((io.deq.ready || !valids(deq_ptr.value)) && !io.empty)
for (i <- 0 until entries) {
val mask = uops(i).br_mask
val uop = uops(i)
valids(i) := valids(i) && !IsKilledByBranch(io.brupdate, false.B, mask) && !(io.flush && flush_fn(uop))
when (valids(i)) {
uops(i).br_mask := GetNewBrMask(io.brupdate, mask)
}
}
when (do_enq) {
ram(enq_ptr.value) := io.enq.bits
valids(enq_ptr.value) := true.B
uops(enq_ptr.value) := io.enq.bits.uop
uops(enq_ptr.value).br_mask := GetNewBrMask(io.brupdate, io.enq.bits.uop)
enq_ptr.inc()
}
when (do_deq) {
valids(deq_ptr.value) := false.B
deq_ptr.inc()
}
when (do_enq =/= do_deq) {
maybe_full := do_enq
}
io.enq.ready := !full
val out = Wire(gen)
out := ram(deq_ptr.value)
out.uop := uops(deq_ptr.value)
io.deq.valid := !io.empty && valids(deq_ptr.value)
io.deq.bits := out
val ptr_diff = enq_ptr.value - deq_ptr.value
if (isPow2(entries)) {
io.count := Cat(maybe_full && ptr_match, ptr_diff)
}
else {
io.count := Mux(ptr_match,
Mux(maybe_full,
entries.asUInt, 0.U),
Mux(deq_ptr.value > enq_ptr.value,
entries.asUInt + ptr_diff, ptr_diff))
}
}
}
// ------------------------------------------
// Printf helper functions
// ------------------------------------------
object BoolToChar
{
/**
* Take in a Chisel Bool and convert it into a Str
* based on the Chars given
*
* @param c_bool Chisel Bool
* @param trueChar Scala Char if bool is true
* @param falseChar Scala Char if bool is false
* @return UInt ASCII Char for "trueChar" or "falseChar"
*/
def apply(c_bool: Bool, trueChar: Char, falseChar: Char = '-'): UInt = {
Mux(c_bool, Str(trueChar), Str(falseChar))
}
}
object CfiTypeToChars
{
/**
* Get a Vec of Strs that can be used for printing
*
* @param cfi_type specific cfi type
* @return Vec of Strs (must be indexed to get specific char)
*/
def apply(cfi_type: UInt) = {
val strings = Seq("----", "BR ", "JAL ", "JALR")
val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })
multiVec(cfi_type)
}
}
object BpdTypeToChars
{
/**
* Get a Vec of Strs that can be used for printing
*
* @param bpd_type specific bpd type
* @return Vec of Strs (must be indexed to get specific char)
*/
def apply(bpd_type: UInt) = {
val strings = Seq("BR ", "JUMP", "----", "RET ", "----", "CALL", "----", "----")
val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })
multiVec(bpd_type)
}
}
object RobTypeToChars
{
/**
* Get a Vec of Strs that can be used for printing
*
* @param rob_type specific rob type
* @return Vec of Strs (must be indexed to get specific char)
*/
def apply(rob_type: UInt) = {
val strings = Seq("RST", "NML", "RBK", " WT")
val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })
multiVec(rob_type)
}
}
object XRegToChars
{
/**
* Get a Vec of Strs that can be used for printing
*
* @param xreg specific register number
* @return Vec of Strs (must be indexed to get specific char)
*/
def apply(xreg: UInt) = {
val strings = Seq(" x0", " ra", " sp", " gp",
" tp", " t0", " t1", " t2",
" s0", " s1", " a0", " a1",
" a2", " a3", " a4", " a5",
" a6", " a7", " s2", " s3",
" s4", " s5", " s6", " s7",
" s8", " s9", "s10", "s11",
" t3", " t4", " t5", " t6")
val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })
multiVec(xreg)
}
}
object FPRegToChars
{
/**
* Get a Vec of Strs that can be used for printing
*
* @param fpreg specific register number
* @return Vec of Strs (must be indexed to get specific char)
*/
def apply(fpreg: UInt) = {
val strings = Seq(" ft0", " ft1", " ft2", " ft3",
" ft4", " ft5", " ft6", " ft7",
" fs0", " fs1", " fa0", " fa1",
" fa2", " fa3", " fa4", " fa5",
" fa6", " fa7", " fs2", " fs3",
" fs4", " fs5", " fs6", " fs7",
" fs8", " fs9", "fs10", "fs11",
" ft8", " ft9", "ft10", "ft11")
val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })
multiVec(fpreg)
}
}
object BoomCoreStringPrefix
{
/**
* Add prefix to BOOM strings (currently only adds the hartId)
*
* @param strs list of strings
* @return String combining the list with the prefix per line
*/
def apply(strs: String*)(implicit p: Parameters) = {
val prefix = "[C" + s"${p(TileKey).tileId}" + "] "
strs.map(str => prefix + str + "\n").mkString("")
}
}
class BranchKillablePipeline[T <: boom.v4.common.HasBoomUOP](gen: T, stages: Int)
(implicit p: org.chipsalliance.cde.config.Parameters)
extends boom.v4.common.BoomModule()(p)
with boom.v4.common.HasBoomCoreParameters
{
val io = IO(new Bundle {
val req = Input(Valid(gen))
val flush = Input(Bool())
val brupdate = Input(new BrUpdateInfo)
val resp = Output(Vec(stages, Valid(gen)))
})
require(stages > 0)
val uops = Reg(Vec(stages, Valid(gen)))
uops(0).valid := io.req.valid && !IsKilledByBranch(io.brupdate, io.flush, io.req.bits)
uops(0).bits := UpdateBrMask(io.brupdate, io.req.bits)
for (i <- 1 until stages) {
uops(i).valid := uops(i-1).valid && !IsKilledByBranch(io.brupdate, io.flush, uops(i-1).bits)
uops(i).bits := UpdateBrMask(io.brupdate, uops(i-1).bits)
}
for (i <- 0 until stages) { when (reset.asBool) { uops(i).valid := false.B } }
io.resp := uops
}
| module BranchKillablePipeline( // @[util.scala:688:7]
input clock, // @[util.scala:688:7]
input reset, // @[util.scala:688:7]
input io_req_valid, // @[util.scala:693:14]
input [31:0] io_req_bits_uop_inst, // @[util.scala:693:14]
input [31:0] io_req_bits_uop_debug_inst, // @[util.scala:693:14]
input io_req_bits_uop_is_rvc, // @[util.scala:693:14]
input [39:0] io_req_bits_uop_debug_pc, // @[util.scala:693:14]
input io_req_bits_uop_iq_type_0, // @[util.scala:693:14]
input io_req_bits_uop_iq_type_1, // @[util.scala:693:14]
input io_req_bits_uop_iq_type_2, // @[util.scala:693:14]
input io_req_bits_uop_iq_type_3, // @[util.scala:693:14]
input io_req_bits_uop_fu_code_0, // @[util.scala:693:14]
input io_req_bits_uop_fu_code_1, // @[util.scala:693:14]
input io_req_bits_uop_fu_code_2, // @[util.scala:693:14]
input io_req_bits_uop_fu_code_3, // @[util.scala:693:14]
input io_req_bits_uop_fu_code_4, // @[util.scala:693:14]
input io_req_bits_uop_fu_code_5, // @[util.scala:693:14]
input io_req_bits_uop_fu_code_6, // @[util.scala:693:14]
input io_req_bits_uop_fu_code_7, // @[util.scala:693:14]
input io_req_bits_uop_fu_code_8, // @[util.scala:693:14]
input io_req_bits_uop_fu_code_9, // @[util.scala:693:14]
input io_req_bits_uop_iw_issued, // @[util.scala:693:14]
input io_req_bits_uop_iw_issued_partial_agen, // @[util.scala:693:14]
input io_req_bits_uop_iw_issued_partial_dgen, // @[util.scala:693:14]
input [2:0] io_req_bits_uop_iw_p1_speculative_child, // @[util.scala:693:14]
input [2:0] io_req_bits_uop_iw_p2_speculative_child, // @[util.scala:693:14]
input io_req_bits_uop_iw_p1_bypass_hint, // @[util.scala:693:14]
input io_req_bits_uop_iw_p2_bypass_hint, // @[util.scala:693:14]
input io_req_bits_uop_iw_p3_bypass_hint, // @[util.scala:693:14]
input [2:0] io_req_bits_uop_dis_col_sel, // @[util.scala:693:14]
input [15:0] io_req_bits_uop_br_mask, // @[util.scala:693:14]
input [3:0] io_req_bits_uop_br_tag, // @[util.scala:693:14]
input [3:0] io_req_bits_uop_br_type, // @[util.scala:693:14]
input io_req_bits_uop_is_sfb, // @[util.scala:693:14]
input io_req_bits_uop_is_fence, // @[util.scala:693:14]
input io_req_bits_uop_is_fencei, // @[util.scala:693:14]
input io_req_bits_uop_is_sfence, // @[util.scala:693:14]
input io_req_bits_uop_is_amo, // @[util.scala:693:14]
input io_req_bits_uop_is_eret, // @[util.scala:693:14]
input io_req_bits_uop_is_sys_pc2epc, // @[util.scala:693:14]
input io_req_bits_uop_is_rocc, // @[util.scala:693:14]
input io_req_bits_uop_is_mov, // @[util.scala:693:14]
input [4:0] io_req_bits_uop_ftq_idx, // @[util.scala:693:14]
input io_req_bits_uop_edge_inst, // @[util.scala:693:14]
input [5:0] io_req_bits_uop_pc_lob, // @[util.scala:693:14]
input io_req_bits_uop_taken, // @[util.scala:693:14]
input io_req_bits_uop_imm_rename, // @[util.scala:693:14]
input [2:0] io_req_bits_uop_imm_sel, // @[util.scala:693:14]
input [4:0] io_req_bits_uop_pimm, // @[util.scala:693:14]
input [19:0] io_req_bits_uop_imm_packed, // @[util.scala:693:14]
input [1:0] io_req_bits_uop_op1_sel, // @[util.scala:693:14]
input [2:0] io_req_bits_uop_op2_sel, // @[util.scala:693:14]
input io_req_bits_uop_fp_ctrl_ldst, // @[util.scala:693:14]
input io_req_bits_uop_fp_ctrl_wen, // @[util.scala:693:14]
input io_req_bits_uop_fp_ctrl_ren1, // @[util.scala:693:14]
input io_req_bits_uop_fp_ctrl_ren2, // @[util.scala:693:14]
input io_req_bits_uop_fp_ctrl_ren3, // @[util.scala:693:14]
input io_req_bits_uop_fp_ctrl_swap12, // @[util.scala:693:14]
input io_req_bits_uop_fp_ctrl_swap23, // @[util.scala:693:14]
input [1:0] io_req_bits_uop_fp_ctrl_typeTagIn, // @[util.scala:693:14]
input [1:0] io_req_bits_uop_fp_ctrl_typeTagOut, // @[util.scala:693:14]
input io_req_bits_uop_fp_ctrl_fromint, // @[util.scala:693:14]
input io_req_bits_uop_fp_ctrl_toint, // @[util.scala:693:14]
input io_req_bits_uop_fp_ctrl_fastpipe, // @[util.scala:693:14]
input io_req_bits_uop_fp_ctrl_fma, // @[util.scala:693:14]
input io_req_bits_uop_fp_ctrl_div, // @[util.scala:693:14]
input io_req_bits_uop_fp_ctrl_sqrt, // @[util.scala:693:14]
input io_req_bits_uop_fp_ctrl_wflags, // @[util.scala:693:14]
input io_req_bits_uop_fp_ctrl_vec, // @[util.scala:693:14]
input [6:0] io_req_bits_uop_rob_idx, // @[util.scala:693:14]
input [4:0] io_req_bits_uop_ldq_idx, // @[util.scala:693:14]
input [4:0] io_req_bits_uop_stq_idx, // @[util.scala:693:14]
input [1:0] io_req_bits_uop_rxq_idx, // @[util.scala:693:14]
input [6:0] io_req_bits_uop_pdst, // @[util.scala:693:14]
input [6:0] io_req_bits_uop_prs1, // @[util.scala:693:14]
input [6:0] io_req_bits_uop_prs2, // @[util.scala:693:14]
input [6:0] io_req_bits_uop_prs3, // @[util.scala:693:14]
input [4:0] io_req_bits_uop_ppred, // @[util.scala:693:14]
input io_req_bits_uop_prs1_busy, // @[util.scala:693:14]
input io_req_bits_uop_prs2_busy, // @[util.scala:693:14]
input io_req_bits_uop_prs3_busy, // @[util.scala:693:14]
input io_req_bits_uop_ppred_busy, // @[util.scala:693:14]
input [6:0] io_req_bits_uop_stale_pdst, // @[util.scala:693:14]
input io_req_bits_uop_exception, // @[util.scala:693:14]
input [63:0] io_req_bits_uop_exc_cause, // @[util.scala:693:14]
input [4:0] io_req_bits_uop_mem_cmd, // @[util.scala:693:14]
input [1:0] io_req_bits_uop_mem_size, // @[util.scala:693:14]
input io_req_bits_uop_mem_signed, // @[util.scala:693:14]
input io_req_bits_uop_uses_ldq, // @[util.scala:693:14]
input io_req_bits_uop_uses_stq, // @[util.scala:693:14]
input io_req_bits_uop_is_unique, // @[util.scala:693:14]
input io_req_bits_uop_flush_on_commit, // @[util.scala:693:14]
input [2:0] io_req_bits_uop_csr_cmd, // @[util.scala:693:14]
input io_req_bits_uop_ldst_is_rs1, // @[util.scala:693:14]
input [5:0] io_req_bits_uop_ldst, // @[util.scala:693:14]
input [5:0] io_req_bits_uop_lrs1, // @[util.scala:693:14]
input [5:0] io_req_bits_uop_lrs2, // @[util.scala:693:14]
input [5:0] io_req_bits_uop_lrs3, // @[util.scala:693:14]
input [1:0] io_req_bits_uop_dst_rtype, // @[util.scala:693:14]
input [1:0] io_req_bits_uop_lrs1_rtype, // @[util.scala:693:14]
input [1:0] io_req_bits_uop_lrs2_rtype, // @[util.scala:693:14]
input io_req_bits_uop_frs3_en, // @[util.scala:693:14]
input io_req_bits_uop_fcn_dw, // @[util.scala:693:14]
input [4:0] io_req_bits_uop_fcn_op, // @[util.scala:693:14]
input io_req_bits_uop_fp_val, // @[util.scala:693:14]
input [2:0] io_req_bits_uop_fp_rm, // @[util.scala:693:14]
input [1:0] io_req_bits_uop_fp_typ, // @[util.scala:693:14]
input io_req_bits_uop_xcpt_pf_if, // @[util.scala:693:14]
input io_req_bits_uop_xcpt_ae_if, // @[util.scala:693:14]
input io_req_bits_uop_xcpt_ma_if, // @[util.scala:693:14]
input io_req_bits_uop_bp_debug_if, // @[util.scala:693:14]
input io_req_bits_uop_bp_xcpt_if, // @[util.scala:693:14]
input [2:0] io_req_bits_uop_debug_fsrc, // @[util.scala:693:14]
input [2:0] io_req_bits_uop_debug_tsrc, // @[util.scala:693:14]
input [63:0] io_req_bits_rs1_data, // @[util.scala:693:14]
input [63:0] io_req_bits_rs2_data, // @[util.scala:693:14]
input [63:0] io_req_bits_imm_data, // @[util.scala:693:14]
input io_flush, // @[util.scala:693:14]
input [15:0] io_brupdate_b1_resolve_mask, // @[util.scala:693:14]
input [15:0] io_brupdate_b1_mispredict_mask, // @[util.scala:693:14]
input [31:0] io_brupdate_b2_uop_inst, // @[util.scala:693:14]
input [31:0] io_brupdate_b2_uop_debug_inst, // @[util.scala:693:14]
input io_brupdate_b2_uop_is_rvc, // @[util.scala:693:14]
input [39:0] io_brupdate_b2_uop_debug_pc, // @[util.scala:693:14]
input io_brupdate_b2_uop_iq_type_0, // @[util.scala:693:14]
input io_brupdate_b2_uop_iq_type_1, // @[util.scala:693:14]
input io_brupdate_b2_uop_iq_type_2, // @[util.scala:693:14]
input io_brupdate_b2_uop_iq_type_3, // @[util.scala:693:14]
input io_brupdate_b2_uop_fu_code_0, // @[util.scala:693:14]
input io_brupdate_b2_uop_fu_code_1, // @[util.scala:693:14]
input io_brupdate_b2_uop_fu_code_2, // @[util.scala:693:14]
input io_brupdate_b2_uop_fu_code_3, // @[util.scala:693:14]
input io_brupdate_b2_uop_fu_code_4, // @[util.scala:693:14]
input io_brupdate_b2_uop_fu_code_5, // @[util.scala:693:14]
input io_brupdate_b2_uop_fu_code_6, // @[util.scala:693:14]
input io_brupdate_b2_uop_fu_code_7, // @[util.scala:693:14]
input io_brupdate_b2_uop_fu_code_8, // @[util.scala:693:14]
input io_brupdate_b2_uop_fu_code_9, // @[util.scala:693:14]
input io_brupdate_b2_uop_iw_issued, // @[util.scala:693:14]
input io_brupdate_b2_uop_iw_issued_partial_agen, // @[util.scala:693:14]
input io_brupdate_b2_uop_iw_issued_partial_dgen, // @[util.scala:693:14]
input [2:0] io_brupdate_b2_uop_iw_p1_speculative_child, // @[util.scala:693:14]
input [2:0] io_brupdate_b2_uop_iw_p2_speculative_child, // @[util.scala:693:14]
input io_brupdate_b2_uop_iw_p1_bypass_hint, // @[util.scala:693:14]
input io_brupdate_b2_uop_iw_p2_bypass_hint, // @[util.scala:693:14]
input io_brupdate_b2_uop_iw_p3_bypass_hint, // @[util.scala:693:14]
input [2:0] io_brupdate_b2_uop_dis_col_sel, // @[util.scala:693:14]
input [15:0] io_brupdate_b2_uop_br_mask, // @[util.scala:693:14]
input [3:0] io_brupdate_b2_uop_br_tag, // @[util.scala:693:14]
input [3:0] io_brupdate_b2_uop_br_type, // @[util.scala:693:14]
input io_brupdate_b2_uop_is_sfb, // @[util.scala:693:14]
input io_brupdate_b2_uop_is_fence, // @[util.scala:693:14]
input io_brupdate_b2_uop_is_fencei, // @[util.scala:693:14]
input io_brupdate_b2_uop_is_sfence, // @[util.scala:693:14]
input io_brupdate_b2_uop_is_amo, // @[util.scala:693:14]
input io_brupdate_b2_uop_is_eret, // @[util.scala:693:14]
input io_brupdate_b2_uop_is_sys_pc2epc, // @[util.scala:693:14]
input io_brupdate_b2_uop_is_rocc, // @[util.scala:693:14]
input io_brupdate_b2_uop_is_mov, // @[util.scala:693:14]
input [4:0] io_brupdate_b2_uop_ftq_idx, // @[util.scala:693:14]
input io_brupdate_b2_uop_edge_inst, // @[util.scala:693:14]
input [5:0] io_brupdate_b2_uop_pc_lob, // @[util.scala:693:14]
input io_brupdate_b2_uop_taken, // @[util.scala:693:14]
input io_brupdate_b2_uop_imm_rename, // @[util.scala:693:14]
input [2:0] io_brupdate_b2_uop_imm_sel, // @[util.scala:693:14]
input [4:0] io_brupdate_b2_uop_pimm, // @[util.scala:693:14]
input [19:0] io_brupdate_b2_uop_imm_packed, // @[util.scala:693:14]
input [1:0] io_brupdate_b2_uop_op1_sel, // @[util.scala:693:14]
input [2:0] io_brupdate_b2_uop_op2_sel, // @[util.scala:693:14]
input io_brupdate_b2_uop_fp_ctrl_ldst, // @[util.scala:693:14]
input io_brupdate_b2_uop_fp_ctrl_wen, // @[util.scala:693:14]
input io_brupdate_b2_uop_fp_ctrl_ren1, // @[util.scala:693:14]
input io_brupdate_b2_uop_fp_ctrl_ren2, // @[util.scala:693:14]
input io_brupdate_b2_uop_fp_ctrl_ren3, // @[util.scala:693:14]
input io_brupdate_b2_uop_fp_ctrl_swap12, // @[util.scala:693:14]
input io_brupdate_b2_uop_fp_ctrl_swap23, // @[util.scala:693:14]
input [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagIn, // @[util.scala:693:14]
input [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagOut, // @[util.scala:693:14]
input io_brupdate_b2_uop_fp_ctrl_fromint, // @[util.scala:693:14]
input io_brupdate_b2_uop_fp_ctrl_toint, // @[util.scala:693:14]
input io_brupdate_b2_uop_fp_ctrl_fastpipe, // @[util.scala:693:14]
input io_brupdate_b2_uop_fp_ctrl_fma, // @[util.scala:693:14]
input io_brupdate_b2_uop_fp_ctrl_div, // @[util.scala:693:14]
input io_brupdate_b2_uop_fp_ctrl_sqrt, // @[util.scala:693:14]
input io_brupdate_b2_uop_fp_ctrl_wflags, // @[util.scala:693:14]
input io_brupdate_b2_uop_fp_ctrl_vec, // @[util.scala:693:14]
input [6:0] io_brupdate_b2_uop_rob_idx, // @[util.scala:693:14]
input [4:0] io_brupdate_b2_uop_ldq_idx, // @[util.scala:693:14]
input [4:0] io_brupdate_b2_uop_stq_idx, // @[util.scala:693:14]
input [1:0] io_brupdate_b2_uop_rxq_idx, // @[util.scala:693:14]
input [6:0] io_brupdate_b2_uop_pdst, // @[util.scala:693:14]
input [6:0] io_brupdate_b2_uop_prs1, // @[util.scala:693:14]
input [6:0] io_brupdate_b2_uop_prs2, // @[util.scala:693:14]
input [6:0] io_brupdate_b2_uop_prs3, // @[util.scala:693:14]
input [4:0] io_brupdate_b2_uop_ppred, // @[util.scala:693:14]
input io_brupdate_b2_uop_prs1_busy, // @[util.scala:693:14]
input io_brupdate_b2_uop_prs2_busy, // @[util.scala:693:14]
input io_brupdate_b2_uop_prs3_busy, // @[util.scala:693:14]
input io_brupdate_b2_uop_ppred_busy, // @[util.scala:693:14]
input [6:0] io_brupdate_b2_uop_stale_pdst, // @[util.scala:693:14]
input io_brupdate_b2_uop_exception, // @[util.scala:693:14]
input [63:0] io_brupdate_b2_uop_exc_cause, // @[util.scala:693:14]
input [4:0] io_brupdate_b2_uop_mem_cmd, // @[util.scala:693:14]
input [1:0] io_brupdate_b2_uop_mem_size, // @[util.scala:693:14]
input io_brupdate_b2_uop_mem_signed, // @[util.scala:693:14]
input io_brupdate_b2_uop_uses_ldq, // @[util.scala:693:14]
input io_brupdate_b2_uop_uses_stq, // @[util.scala:693:14]
input io_brupdate_b2_uop_is_unique, // @[util.scala:693:14]
input io_brupdate_b2_uop_flush_on_commit, // @[util.scala:693:14]
input [2:0] io_brupdate_b2_uop_csr_cmd, // @[util.scala:693:14]
input io_brupdate_b2_uop_ldst_is_rs1, // @[util.scala:693:14]
input [5:0] io_brupdate_b2_uop_ldst, // @[util.scala:693:14]
input [5:0] io_brupdate_b2_uop_lrs1, // @[util.scala:693:14]
input [5:0] io_brupdate_b2_uop_lrs2, // @[util.scala:693:14]
input [5:0] io_brupdate_b2_uop_lrs3, // @[util.scala:693:14]
input [1:0] io_brupdate_b2_uop_dst_rtype, // @[util.scala:693:14]
input [1:0] io_brupdate_b2_uop_lrs1_rtype, // @[util.scala:693:14]
input [1:0] io_brupdate_b2_uop_lrs2_rtype, // @[util.scala:693:14]
input io_brupdate_b2_uop_frs3_en, // @[util.scala:693:14]
input io_brupdate_b2_uop_fcn_dw, // @[util.scala:693:14]
input [4:0] io_brupdate_b2_uop_fcn_op, // @[util.scala:693:14]
input io_brupdate_b2_uop_fp_val, // @[util.scala:693:14]
input [2:0] io_brupdate_b2_uop_fp_rm, // @[util.scala:693:14]
input [1:0] io_brupdate_b2_uop_fp_typ, // @[util.scala:693:14]
input io_brupdate_b2_uop_xcpt_pf_if, // @[util.scala:693:14]
input io_brupdate_b2_uop_xcpt_ae_if, // @[util.scala:693:14]
input io_brupdate_b2_uop_xcpt_ma_if, // @[util.scala:693:14]
input io_brupdate_b2_uop_bp_debug_if, // @[util.scala:693:14]
input io_brupdate_b2_uop_bp_xcpt_if, // @[util.scala:693:14]
input [2:0] io_brupdate_b2_uop_debug_fsrc, // @[util.scala:693:14]
input [2:0] io_brupdate_b2_uop_debug_tsrc, // @[util.scala:693:14]
input io_brupdate_b2_mispredict, // @[util.scala:693:14]
input io_brupdate_b2_taken, // @[util.scala:693:14]
input [2:0] io_brupdate_b2_cfi_type, // @[util.scala:693:14]
input [1:0] io_brupdate_b2_pc_sel, // @[util.scala:693:14]
input [39:0] io_brupdate_b2_jalr_target, // @[util.scala:693:14]
input [20:0] io_brupdate_b2_target_offset, // @[util.scala:693:14]
output io_resp_2_valid, // @[util.scala:693:14]
output [31:0] io_resp_2_bits_uop_inst, // @[util.scala:693:14]
output [31:0] io_resp_2_bits_uop_debug_inst, // @[util.scala:693:14]
output io_resp_2_bits_uop_is_rvc, // @[util.scala:693:14]
output [39:0] io_resp_2_bits_uop_debug_pc, // @[util.scala:693:14]
output io_resp_2_bits_uop_iq_type_0, // @[util.scala:693:14]
output io_resp_2_bits_uop_iq_type_1, // @[util.scala:693:14]
output io_resp_2_bits_uop_iq_type_2, // @[util.scala:693:14]
output io_resp_2_bits_uop_iq_type_3, // @[util.scala:693:14]
output io_resp_2_bits_uop_fu_code_0, // @[util.scala:693:14]
output io_resp_2_bits_uop_fu_code_1, // @[util.scala:693:14]
output io_resp_2_bits_uop_fu_code_2, // @[util.scala:693:14]
output io_resp_2_bits_uop_fu_code_3, // @[util.scala:693:14]
output io_resp_2_bits_uop_fu_code_4, // @[util.scala:693:14]
output io_resp_2_bits_uop_fu_code_5, // @[util.scala:693:14]
output io_resp_2_bits_uop_fu_code_6, // @[util.scala:693:14]
output io_resp_2_bits_uop_fu_code_7, // @[util.scala:693:14]
output io_resp_2_bits_uop_fu_code_8, // @[util.scala:693:14]
output io_resp_2_bits_uop_fu_code_9, // @[util.scala:693:14]
output io_resp_2_bits_uop_iw_issued, // @[util.scala:693:14]
output io_resp_2_bits_uop_iw_issued_partial_agen, // @[util.scala:693:14]
output io_resp_2_bits_uop_iw_issued_partial_dgen, // @[util.scala:693:14]
output [2:0] io_resp_2_bits_uop_iw_p1_speculative_child, // @[util.scala:693:14]
output [2:0] io_resp_2_bits_uop_iw_p2_speculative_child, // @[util.scala:693:14]
output io_resp_2_bits_uop_iw_p1_bypass_hint, // @[util.scala:693:14]
output io_resp_2_bits_uop_iw_p2_bypass_hint, // @[util.scala:693:14]
output io_resp_2_bits_uop_iw_p3_bypass_hint, // @[util.scala:693:14]
output [2:0] io_resp_2_bits_uop_dis_col_sel, // @[util.scala:693:14]
output [15:0] io_resp_2_bits_uop_br_mask, // @[util.scala:693:14]
output [3:0] io_resp_2_bits_uop_br_tag, // @[util.scala:693:14]
output [3:0] io_resp_2_bits_uop_br_type, // @[util.scala:693:14]
output io_resp_2_bits_uop_is_sfb, // @[util.scala:693:14]
output io_resp_2_bits_uop_is_fence, // @[util.scala:693:14]
output io_resp_2_bits_uop_is_fencei, // @[util.scala:693:14]
output io_resp_2_bits_uop_is_sfence, // @[util.scala:693:14]
output io_resp_2_bits_uop_is_amo, // @[util.scala:693:14]
output io_resp_2_bits_uop_is_eret, // @[util.scala:693:14]
output io_resp_2_bits_uop_is_sys_pc2epc, // @[util.scala:693:14]
output io_resp_2_bits_uop_is_rocc, // @[util.scala:693:14]
output io_resp_2_bits_uop_is_mov, // @[util.scala:693:14]
output [4:0] io_resp_2_bits_uop_ftq_idx, // @[util.scala:693:14]
output io_resp_2_bits_uop_edge_inst, // @[util.scala:693:14]
output [5:0] io_resp_2_bits_uop_pc_lob, // @[util.scala:693:14]
output io_resp_2_bits_uop_taken, // @[util.scala:693:14]
output io_resp_2_bits_uop_imm_rename, // @[util.scala:693:14]
output [2:0] io_resp_2_bits_uop_imm_sel, // @[util.scala:693:14]
output [4:0] io_resp_2_bits_uop_pimm, // @[util.scala:693:14]
output [19:0] io_resp_2_bits_uop_imm_packed, // @[util.scala:693:14]
output [1:0] io_resp_2_bits_uop_op1_sel, // @[util.scala:693:14]
output [2:0] io_resp_2_bits_uop_op2_sel, // @[util.scala:693:14]
output io_resp_2_bits_uop_fp_ctrl_ldst, // @[util.scala:693:14]
output io_resp_2_bits_uop_fp_ctrl_wen, // @[util.scala:693:14]
output io_resp_2_bits_uop_fp_ctrl_ren1, // @[util.scala:693:14]
output io_resp_2_bits_uop_fp_ctrl_ren2, // @[util.scala:693:14]
output io_resp_2_bits_uop_fp_ctrl_ren3, // @[util.scala:693:14]
output io_resp_2_bits_uop_fp_ctrl_swap12, // @[util.scala:693:14]
output io_resp_2_bits_uop_fp_ctrl_swap23, // @[util.scala:693:14]
output [1:0] io_resp_2_bits_uop_fp_ctrl_typeTagIn, // @[util.scala:693:14]
output [1:0] io_resp_2_bits_uop_fp_ctrl_typeTagOut, // @[util.scala:693:14]
output io_resp_2_bits_uop_fp_ctrl_fromint, // @[util.scala:693:14]
output io_resp_2_bits_uop_fp_ctrl_toint, // @[util.scala:693:14]
output io_resp_2_bits_uop_fp_ctrl_fastpipe, // @[util.scala:693:14]
output io_resp_2_bits_uop_fp_ctrl_fma, // @[util.scala:693:14]
output io_resp_2_bits_uop_fp_ctrl_div, // @[util.scala:693:14]
output io_resp_2_bits_uop_fp_ctrl_sqrt, // @[util.scala:693:14]
output io_resp_2_bits_uop_fp_ctrl_wflags, // @[util.scala:693:14]
output io_resp_2_bits_uop_fp_ctrl_vec, // @[util.scala:693:14]
output [6:0] io_resp_2_bits_uop_rob_idx, // @[util.scala:693:14]
output [4:0] io_resp_2_bits_uop_ldq_idx, // @[util.scala:693:14]
output [4:0] io_resp_2_bits_uop_stq_idx, // @[util.scala:693:14]
output [1:0] io_resp_2_bits_uop_rxq_idx, // @[util.scala:693:14]
output [6:0] io_resp_2_bits_uop_pdst, // @[util.scala:693:14]
output [6:0] io_resp_2_bits_uop_prs1, // @[util.scala:693:14]
output [6:0] io_resp_2_bits_uop_prs2, // @[util.scala:693:14]
output [6:0] io_resp_2_bits_uop_prs3, // @[util.scala:693:14]
output [4:0] io_resp_2_bits_uop_ppred, // @[util.scala:693:14]
output io_resp_2_bits_uop_prs1_busy, // @[util.scala:693:14]
output io_resp_2_bits_uop_prs2_busy, // @[util.scala:693:14]
output io_resp_2_bits_uop_prs3_busy, // @[util.scala:693:14]
output io_resp_2_bits_uop_ppred_busy, // @[util.scala:693:14]
output [6:0] io_resp_2_bits_uop_stale_pdst, // @[util.scala:693:14]
output io_resp_2_bits_uop_exception, // @[util.scala:693:14]
output [63:0] io_resp_2_bits_uop_exc_cause, // @[util.scala:693:14]
output [4:0] io_resp_2_bits_uop_mem_cmd, // @[util.scala:693:14]
output [1:0] io_resp_2_bits_uop_mem_size, // @[util.scala:693:14]
output io_resp_2_bits_uop_mem_signed, // @[util.scala:693:14]
output io_resp_2_bits_uop_uses_ldq, // @[util.scala:693:14]
output io_resp_2_bits_uop_uses_stq, // @[util.scala:693:14]
output io_resp_2_bits_uop_is_unique, // @[util.scala:693:14]
output io_resp_2_bits_uop_flush_on_commit, // @[util.scala:693:14]
output [2:0] io_resp_2_bits_uop_csr_cmd, // @[util.scala:693:14]
output io_resp_2_bits_uop_ldst_is_rs1, // @[util.scala:693:14]
output [5:0] io_resp_2_bits_uop_ldst, // @[util.scala:693:14]
output [5:0] io_resp_2_bits_uop_lrs1, // @[util.scala:693:14]
output [5:0] io_resp_2_bits_uop_lrs2, // @[util.scala:693:14]
output [5:0] io_resp_2_bits_uop_lrs3, // @[util.scala:693:14]
output [1:0] io_resp_2_bits_uop_dst_rtype, // @[util.scala:693:14]
output [1:0] io_resp_2_bits_uop_lrs1_rtype, // @[util.scala:693:14]
output [1:0] io_resp_2_bits_uop_lrs2_rtype, // @[util.scala:693:14]
output io_resp_2_bits_uop_frs3_en, // @[util.scala:693:14]
output io_resp_2_bits_uop_fcn_dw, // @[util.scala:693:14]
output [4:0] io_resp_2_bits_uop_fcn_op, // @[util.scala:693:14]
output io_resp_2_bits_uop_fp_val, // @[util.scala:693:14]
output [2:0] io_resp_2_bits_uop_fp_rm, // @[util.scala:693:14]
output [1:0] io_resp_2_bits_uop_fp_typ, // @[util.scala:693:14]
output io_resp_2_bits_uop_xcpt_pf_if, // @[util.scala:693:14]
output io_resp_2_bits_uop_xcpt_ae_if, // @[util.scala:693:14]
output io_resp_2_bits_uop_xcpt_ma_if, // @[util.scala:693:14]
output io_resp_2_bits_uop_bp_debug_if, // @[util.scala:693:14]
output io_resp_2_bits_uop_bp_xcpt_if, // @[util.scala:693:14]
output [2:0] io_resp_2_bits_uop_debug_fsrc, // @[util.scala:693:14]
output [2:0] io_resp_2_bits_uop_debug_tsrc // @[util.scala:693:14]
);
wire io_req_valid_0 = io_req_valid; // @[util.scala:688:7]
wire [31:0] io_req_bits_uop_inst_0 = io_req_bits_uop_inst; // @[util.scala:688:7]
wire [31:0] io_req_bits_uop_debug_inst_0 = io_req_bits_uop_debug_inst; // @[util.scala:688:7]
wire io_req_bits_uop_is_rvc_0 = io_req_bits_uop_is_rvc; // @[util.scala:688:7]
wire [39:0] io_req_bits_uop_debug_pc_0 = io_req_bits_uop_debug_pc; // @[util.scala:688:7]
wire io_req_bits_uop_iq_type_0_0 = io_req_bits_uop_iq_type_0; // @[util.scala:688:7]
wire io_req_bits_uop_iq_type_1_0 = io_req_bits_uop_iq_type_1; // @[util.scala:688:7]
wire io_req_bits_uop_iq_type_2_0 = io_req_bits_uop_iq_type_2; // @[util.scala:688:7]
wire io_req_bits_uop_iq_type_3_0 = io_req_bits_uop_iq_type_3; // @[util.scala:688:7]
wire io_req_bits_uop_fu_code_0_0 = io_req_bits_uop_fu_code_0; // @[util.scala:688:7]
wire io_req_bits_uop_fu_code_1_0 = io_req_bits_uop_fu_code_1; // @[util.scala:688:7]
wire io_req_bits_uop_fu_code_2_0 = io_req_bits_uop_fu_code_2; // @[util.scala:688:7]
wire io_req_bits_uop_fu_code_3_0 = io_req_bits_uop_fu_code_3; // @[util.scala:688:7]
wire io_req_bits_uop_fu_code_4_0 = io_req_bits_uop_fu_code_4; // @[util.scala:688:7]
wire io_req_bits_uop_fu_code_5_0 = io_req_bits_uop_fu_code_5; // @[util.scala:688:7]
wire io_req_bits_uop_fu_code_6_0 = io_req_bits_uop_fu_code_6; // @[util.scala:688:7]
wire io_req_bits_uop_fu_code_7_0 = io_req_bits_uop_fu_code_7; // @[util.scala:688:7]
wire io_req_bits_uop_fu_code_8_0 = io_req_bits_uop_fu_code_8; // @[util.scala:688:7]
wire io_req_bits_uop_fu_code_9_0 = io_req_bits_uop_fu_code_9; // @[util.scala:688:7]
wire io_req_bits_uop_iw_issued_0 = io_req_bits_uop_iw_issued; // @[util.scala:688:7]
wire io_req_bits_uop_iw_issued_partial_agen_0 = io_req_bits_uop_iw_issued_partial_agen; // @[util.scala:688:7]
wire io_req_bits_uop_iw_issued_partial_dgen_0 = io_req_bits_uop_iw_issued_partial_dgen; // @[util.scala:688:7]
wire [2:0] io_req_bits_uop_iw_p1_speculative_child_0 = io_req_bits_uop_iw_p1_speculative_child; // @[util.scala:688:7]
wire [2:0] io_req_bits_uop_iw_p2_speculative_child_0 = io_req_bits_uop_iw_p2_speculative_child; // @[util.scala:688:7]
wire io_req_bits_uop_iw_p1_bypass_hint_0 = io_req_bits_uop_iw_p1_bypass_hint; // @[util.scala:688:7]
wire io_req_bits_uop_iw_p2_bypass_hint_0 = io_req_bits_uop_iw_p2_bypass_hint; // @[util.scala:688:7]
wire io_req_bits_uop_iw_p3_bypass_hint_0 = io_req_bits_uop_iw_p3_bypass_hint; // @[util.scala:688:7]
wire [2:0] io_req_bits_uop_dis_col_sel_0 = io_req_bits_uop_dis_col_sel; // @[util.scala:688:7]
wire [15:0] io_req_bits_uop_br_mask_0 = io_req_bits_uop_br_mask; // @[util.scala:688:7]
wire [3:0] io_req_bits_uop_br_tag_0 = io_req_bits_uop_br_tag; // @[util.scala:688:7]
wire [3:0] io_req_bits_uop_br_type_0 = io_req_bits_uop_br_type; // @[util.scala:688:7]
wire io_req_bits_uop_is_sfb_0 = io_req_bits_uop_is_sfb; // @[util.scala:688:7]
wire io_req_bits_uop_is_fence_0 = io_req_bits_uop_is_fence; // @[util.scala:688:7]
wire io_req_bits_uop_is_fencei_0 = io_req_bits_uop_is_fencei; // @[util.scala:688:7]
wire io_req_bits_uop_is_sfence_0 = io_req_bits_uop_is_sfence; // @[util.scala:688:7]
wire io_req_bits_uop_is_amo_0 = io_req_bits_uop_is_amo; // @[util.scala:688:7]
wire io_req_bits_uop_is_eret_0 = io_req_bits_uop_is_eret; // @[util.scala:688:7]
wire io_req_bits_uop_is_sys_pc2epc_0 = io_req_bits_uop_is_sys_pc2epc; // @[util.scala:688:7]
wire io_req_bits_uop_is_rocc_0 = io_req_bits_uop_is_rocc; // @[util.scala:688:7]
wire io_req_bits_uop_is_mov_0 = io_req_bits_uop_is_mov; // @[util.scala:688:7]
wire [4:0] io_req_bits_uop_ftq_idx_0 = io_req_bits_uop_ftq_idx; // @[util.scala:688:7]
wire io_req_bits_uop_edge_inst_0 = io_req_bits_uop_edge_inst; // @[util.scala:688:7]
wire [5:0] io_req_bits_uop_pc_lob_0 = io_req_bits_uop_pc_lob; // @[util.scala:688:7]
wire io_req_bits_uop_taken_0 = io_req_bits_uop_taken; // @[util.scala:688:7]
wire io_req_bits_uop_imm_rename_0 = io_req_bits_uop_imm_rename; // @[util.scala:688:7]
wire [2:0] io_req_bits_uop_imm_sel_0 = io_req_bits_uop_imm_sel; // @[util.scala:688:7]
wire [4:0] io_req_bits_uop_pimm_0 = io_req_bits_uop_pimm; // @[util.scala:688:7]
wire [19:0] io_req_bits_uop_imm_packed_0 = io_req_bits_uop_imm_packed; // @[util.scala:688:7]
wire [1:0] io_req_bits_uop_op1_sel_0 = io_req_bits_uop_op1_sel; // @[util.scala:688:7]
wire [2:0] io_req_bits_uop_op2_sel_0 = io_req_bits_uop_op2_sel; // @[util.scala:688:7]
wire io_req_bits_uop_fp_ctrl_ldst_0 = io_req_bits_uop_fp_ctrl_ldst; // @[util.scala:688:7]
wire io_req_bits_uop_fp_ctrl_wen_0 = io_req_bits_uop_fp_ctrl_wen; // @[util.scala:688:7]
wire io_req_bits_uop_fp_ctrl_ren1_0 = io_req_bits_uop_fp_ctrl_ren1; // @[util.scala:688:7]
wire io_req_bits_uop_fp_ctrl_ren2_0 = io_req_bits_uop_fp_ctrl_ren2; // @[util.scala:688:7]
wire io_req_bits_uop_fp_ctrl_ren3_0 = io_req_bits_uop_fp_ctrl_ren3; // @[util.scala:688:7]
wire io_req_bits_uop_fp_ctrl_swap12_0 = io_req_bits_uop_fp_ctrl_swap12; // @[util.scala:688:7]
wire io_req_bits_uop_fp_ctrl_swap23_0 = io_req_bits_uop_fp_ctrl_swap23; // @[util.scala:688:7]
wire [1:0] io_req_bits_uop_fp_ctrl_typeTagIn_0 = io_req_bits_uop_fp_ctrl_typeTagIn; // @[util.scala:688:7]
wire [1:0] io_req_bits_uop_fp_ctrl_typeTagOut_0 = io_req_bits_uop_fp_ctrl_typeTagOut; // @[util.scala:688:7]
wire io_req_bits_uop_fp_ctrl_fromint_0 = io_req_bits_uop_fp_ctrl_fromint; // @[util.scala:688:7]
wire io_req_bits_uop_fp_ctrl_toint_0 = io_req_bits_uop_fp_ctrl_toint; // @[util.scala:688:7]
wire io_req_bits_uop_fp_ctrl_fastpipe_0 = io_req_bits_uop_fp_ctrl_fastpipe; // @[util.scala:688:7]
wire io_req_bits_uop_fp_ctrl_fma_0 = io_req_bits_uop_fp_ctrl_fma; // @[util.scala:688:7]
wire io_req_bits_uop_fp_ctrl_div_0 = io_req_bits_uop_fp_ctrl_div; // @[util.scala:688:7]
wire io_req_bits_uop_fp_ctrl_sqrt_0 = io_req_bits_uop_fp_ctrl_sqrt; // @[util.scala:688:7]
wire io_req_bits_uop_fp_ctrl_wflags_0 = io_req_bits_uop_fp_ctrl_wflags; // @[util.scala:688:7]
wire io_req_bits_uop_fp_ctrl_vec_0 = io_req_bits_uop_fp_ctrl_vec; // @[util.scala:688:7]
wire [6:0] io_req_bits_uop_rob_idx_0 = io_req_bits_uop_rob_idx; // @[util.scala:688:7]
wire [4:0] io_req_bits_uop_ldq_idx_0 = io_req_bits_uop_ldq_idx; // @[util.scala:688:7]
wire [4:0] io_req_bits_uop_stq_idx_0 = io_req_bits_uop_stq_idx; // @[util.scala:688:7]
wire [1:0] io_req_bits_uop_rxq_idx_0 = io_req_bits_uop_rxq_idx; // @[util.scala:688:7]
wire [6:0] io_req_bits_uop_pdst_0 = io_req_bits_uop_pdst; // @[util.scala:688:7]
wire [6:0] io_req_bits_uop_prs1_0 = io_req_bits_uop_prs1; // @[util.scala:688:7]
wire [6:0] io_req_bits_uop_prs2_0 = io_req_bits_uop_prs2; // @[util.scala:688:7]
wire [6:0] io_req_bits_uop_prs3_0 = io_req_bits_uop_prs3; // @[util.scala:688:7]
wire [4:0] io_req_bits_uop_ppred_0 = io_req_bits_uop_ppred; // @[util.scala:688:7]
wire io_req_bits_uop_prs1_busy_0 = io_req_bits_uop_prs1_busy; // @[util.scala:688:7]
wire io_req_bits_uop_prs2_busy_0 = io_req_bits_uop_prs2_busy; // @[util.scala:688:7]
wire io_req_bits_uop_prs3_busy_0 = io_req_bits_uop_prs3_busy; // @[util.scala:688:7]
wire io_req_bits_uop_ppred_busy_0 = io_req_bits_uop_ppred_busy; // @[util.scala:688:7]
wire [6:0] io_req_bits_uop_stale_pdst_0 = io_req_bits_uop_stale_pdst; // @[util.scala:688:7]
wire io_req_bits_uop_exception_0 = io_req_bits_uop_exception; // @[util.scala:688:7]
wire [63:0] io_req_bits_uop_exc_cause_0 = io_req_bits_uop_exc_cause; // @[util.scala:688:7]
wire [4:0] io_req_bits_uop_mem_cmd_0 = io_req_bits_uop_mem_cmd; // @[util.scala:688:7]
wire [1:0] io_req_bits_uop_mem_size_0 = io_req_bits_uop_mem_size; // @[util.scala:688:7]
wire io_req_bits_uop_mem_signed_0 = io_req_bits_uop_mem_signed; // @[util.scala:688:7]
wire io_req_bits_uop_uses_ldq_0 = io_req_bits_uop_uses_ldq; // @[util.scala:688:7]
wire io_req_bits_uop_uses_stq_0 = io_req_bits_uop_uses_stq; // @[util.scala:688:7]
wire io_req_bits_uop_is_unique_0 = io_req_bits_uop_is_unique; // @[util.scala:688:7]
wire io_req_bits_uop_flush_on_commit_0 = io_req_bits_uop_flush_on_commit; // @[util.scala:688:7]
wire [2:0] io_req_bits_uop_csr_cmd_0 = io_req_bits_uop_csr_cmd; // @[util.scala:688:7]
wire io_req_bits_uop_ldst_is_rs1_0 = io_req_bits_uop_ldst_is_rs1; // @[util.scala:688:7]
wire [5:0] io_req_bits_uop_ldst_0 = io_req_bits_uop_ldst; // @[util.scala:688:7]
wire [5:0] io_req_bits_uop_lrs1_0 = io_req_bits_uop_lrs1; // @[util.scala:688:7]
wire [5:0] io_req_bits_uop_lrs2_0 = io_req_bits_uop_lrs2; // @[util.scala:688:7]
wire [5:0] io_req_bits_uop_lrs3_0 = io_req_bits_uop_lrs3; // @[util.scala:688:7]
wire [1:0] io_req_bits_uop_dst_rtype_0 = io_req_bits_uop_dst_rtype; // @[util.scala:688:7]
wire [1:0] io_req_bits_uop_lrs1_rtype_0 = io_req_bits_uop_lrs1_rtype; // @[util.scala:688:7]
wire [1:0] io_req_bits_uop_lrs2_rtype_0 = io_req_bits_uop_lrs2_rtype; // @[util.scala:688:7]
wire io_req_bits_uop_frs3_en_0 = io_req_bits_uop_frs3_en; // @[util.scala:688:7]
wire io_req_bits_uop_fcn_dw_0 = io_req_bits_uop_fcn_dw; // @[util.scala:688:7]
wire [4:0] io_req_bits_uop_fcn_op_0 = io_req_bits_uop_fcn_op; // @[util.scala:688:7]
wire io_req_bits_uop_fp_val_0 = io_req_bits_uop_fp_val; // @[util.scala:688:7]
wire [2:0] io_req_bits_uop_fp_rm_0 = io_req_bits_uop_fp_rm; // @[util.scala:688:7]
wire [1:0] io_req_bits_uop_fp_typ_0 = io_req_bits_uop_fp_typ; // @[util.scala:688:7]
wire io_req_bits_uop_xcpt_pf_if_0 = io_req_bits_uop_xcpt_pf_if; // @[util.scala:688:7]
wire io_req_bits_uop_xcpt_ae_if_0 = io_req_bits_uop_xcpt_ae_if; // @[util.scala:688:7]
wire io_req_bits_uop_xcpt_ma_if_0 = io_req_bits_uop_xcpt_ma_if; // @[util.scala:688:7]
wire io_req_bits_uop_bp_debug_if_0 = io_req_bits_uop_bp_debug_if; // @[util.scala:688:7]
wire io_req_bits_uop_bp_xcpt_if_0 = io_req_bits_uop_bp_xcpt_if; // @[util.scala:688:7]
wire [2:0] io_req_bits_uop_debug_fsrc_0 = io_req_bits_uop_debug_fsrc; // @[util.scala:688:7]
wire [2:0] io_req_bits_uop_debug_tsrc_0 = io_req_bits_uop_debug_tsrc; // @[util.scala:688:7]
wire [63:0] io_req_bits_rs1_data_0 = io_req_bits_rs1_data; // @[util.scala:688:7]
wire [63:0] io_req_bits_rs2_data_0 = io_req_bits_rs2_data; // @[util.scala:688:7]
wire [63:0] io_req_bits_imm_data_0 = io_req_bits_imm_data; // @[util.scala:688:7]
wire io_flush_0 = io_flush; // @[util.scala:688:7]
wire [15:0] io_brupdate_b1_resolve_mask_0 = io_brupdate_b1_resolve_mask; // @[util.scala:688:7]
wire [15:0] io_brupdate_b1_mispredict_mask_0 = io_brupdate_b1_mispredict_mask; // @[util.scala:688:7]
wire [31:0] io_brupdate_b2_uop_inst_0 = io_brupdate_b2_uop_inst; // @[util.scala:688:7]
wire [31:0] io_brupdate_b2_uop_debug_inst_0 = io_brupdate_b2_uop_debug_inst; // @[util.scala:688:7]
wire io_brupdate_b2_uop_is_rvc_0 = io_brupdate_b2_uop_is_rvc; // @[util.scala:688:7]
wire [39:0] io_brupdate_b2_uop_debug_pc_0 = io_brupdate_b2_uop_debug_pc; // @[util.scala:688:7]
wire io_brupdate_b2_uop_iq_type_0_0 = io_brupdate_b2_uop_iq_type_0; // @[util.scala:688:7]
wire io_brupdate_b2_uop_iq_type_1_0 = io_brupdate_b2_uop_iq_type_1; // @[util.scala:688:7]
wire io_brupdate_b2_uop_iq_type_2_0 = io_brupdate_b2_uop_iq_type_2; // @[util.scala:688:7]
wire io_brupdate_b2_uop_iq_type_3_0 = io_brupdate_b2_uop_iq_type_3; // @[util.scala:688:7]
wire io_brupdate_b2_uop_fu_code_0_0 = io_brupdate_b2_uop_fu_code_0; // @[util.scala:688:7]
wire io_brupdate_b2_uop_fu_code_1_0 = io_brupdate_b2_uop_fu_code_1; // @[util.scala:688:7]
wire io_brupdate_b2_uop_fu_code_2_0 = io_brupdate_b2_uop_fu_code_2; // @[util.scala:688:7]
wire io_brupdate_b2_uop_fu_code_3_0 = io_brupdate_b2_uop_fu_code_3; // @[util.scala:688:7]
wire io_brupdate_b2_uop_fu_code_4_0 = io_brupdate_b2_uop_fu_code_4; // @[util.scala:688:7]
wire io_brupdate_b2_uop_fu_code_5_0 = io_brupdate_b2_uop_fu_code_5; // @[util.scala:688:7]
wire io_brupdate_b2_uop_fu_code_6_0 = io_brupdate_b2_uop_fu_code_6; // @[util.scala:688:7]
wire io_brupdate_b2_uop_fu_code_7_0 = io_brupdate_b2_uop_fu_code_7; // @[util.scala:688:7]
wire io_brupdate_b2_uop_fu_code_8_0 = io_brupdate_b2_uop_fu_code_8; // @[util.scala:688:7]
wire io_brupdate_b2_uop_fu_code_9_0 = io_brupdate_b2_uop_fu_code_9; // @[util.scala:688:7]
wire io_brupdate_b2_uop_iw_issued_0 = io_brupdate_b2_uop_iw_issued; // @[util.scala:688:7]
wire io_brupdate_b2_uop_iw_issued_partial_agen_0 = io_brupdate_b2_uop_iw_issued_partial_agen; // @[util.scala:688:7]
wire io_brupdate_b2_uop_iw_issued_partial_dgen_0 = io_brupdate_b2_uop_iw_issued_partial_dgen; // @[util.scala:688:7]
wire [2:0] io_brupdate_b2_uop_iw_p1_speculative_child_0 = io_brupdate_b2_uop_iw_p1_speculative_child; // @[util.scala:688:7]
wire [2:0] io_brupdate_b2_uop_iw_p2_speculative_child_0 = io_brupdate_b2_uop_iw_p2_speculative_child; // @[util.scala:688:7]
wire io_brupdate_b2_uop_iw_p1_bypass_hint_0 = io_brupdate_b2_uop_iw_p1_bypass_hint; // @[util.scala:688:7]
wire io_brupdate_b2_uop_iw_p2_bypass_hint_0 = io_brupdate_b2_uop_iw_p2_bypass_hint; // @[util.scala:688:7]
wire io_brupdate_b2_uop_iw_p3_bypass_hint_0 = io_brupdate_b2_uop_iw_p3_bypass_hint; // @[util.scala:688:7]
wire [2:0] io_brupdate_b2_uop_dis_col_sel_0 = io_brupdate_b2_uop_dis_col_sel; // @[util.scala:688:7]
wire [15:0] io_brupdate_b2_uop_br_mask_0 = io_brupdate_b2_uop_br_mask; // @[util.scala:688:7]
wire [3:0] io_brupdate_b2_uop_br_tag_0 = io_brupdate_b2_uop_br_tag; // @[util.scala:688:7]
wire [3:0] io_brupdate_b2_uop_br_type_0 = io_brupdate_b2_uop_br_type; // @[util.scala:688:7]
wire io_brupdate_b2_uop_is_sfb_0 = io_brupdate_b2_uop_is_sfb; // @[util.scala:688:7]
wire io_brupdate_b2_uop_is_fence_0 = io_brupdate_b2_uop_is_fence; // @[util.scala:688:7]
wire io_brupdate_b2_uop_is_fencei_0 = io_brupdate_b2_uop_is_fencei; // @[util.scala:688:7]
wire io_brupdate_b2_uop_is_sfence_0 = io_brupdate_b2_uop_is_sfence; // @[util.scala:688:7]
wire io_brupdate_b2_uop_is_amo_0 = io_brupdate_b2_uop_is_amo; // @[util.scala:688:7]
wire io_brupdate_b2_uop_is_eret_0 = io_brupdate_b2_uop_is_eret; // @[util.scala:688:7]
wire io_brupdate_b2_uop_is_sys_pc2epc_0 = io_brupdate_b2_uop_is_sys_pc2epc; // @[util.scala:688:7]
wire io_brupdate_b2_uop_is_rocc_0 = io_brupdate_b2_uop_is_rocc; // @[util.scala:688:7]
wire io_brupdate_b2_uop_is_mov_0 = io_brupdate_b2_uop_is_mov; // @[util.scala:688:7]
wire [4:0] io_brupdate_b2_uop_ftq_idx_0 = io_brupdate_b2_uop_ftq_idx; // @[util.scala:688:7]
wire io_brupdate_b2_uop_edge_inst_0 = io_brupdate_b2_uop_edge_inst; // @[util.scala:688:7]
wire [5:0] io_brupdate_b2_uop_pc_lob_0 = io_brupdate_b2_uop_pc_lob; // @[util.scala:688:7]
wire io_brupdate_b2_uop_taken_0 = io_brupdate_b2_uop_taken; // @[util.scala:688:7]
wire io_brupdate_b2_uop_imm_rename_0 = io_brupdate_b2_uop_imm_rename; // @[util.scala:688:7]
wire [2:0] io_brupdate_b2_uop_imm_sel_0 = io_brupdate_b2_uop_imm_sel; // @[util.scala:688:7]
wire [4:0] io_brupdate_b2_uop_pimm_0 = io_brupdate_b2_uop_pimm; // @[util.scala:688:7]
wire [19:0] io_brupdate_b2_uop_imm_packed_0 = io_brupdate_b2_uop_imm_packed; // @[util.scala:688:7]
wire [1:0] io_brupdate_b2_uop_op1_sel_0 = io_brupdate_b2_uop_op1_sel; // @[util.scala:688:7]
wire [2:0] io_brupdate_b2_uop_op2_sel_0 = io_brupdate_b2_uop_op2_sel; // @[util.scala:688:7]
wire io_brupdate_b2_uop_fp_ctrl_ldst_0 = io_brupdate_b2_uop_fp_ctrl_ldst; // @[util.scala:688:7]
wire io_brupdate_b2_uop_fp_ctrl_wen_0 = io_brupdate_b2_uop_fp_ctrl_wen; // @[util.scala:688:7]
wire io_brupdate_b2_uop_fp_ctrl_ren1_0 = io_brupdate_b2_uop_fp_ctrl_ren1; // @[util.scala:688:7]
wire io_brupdate_b2_uop_fp_ctrl_ren2_0 = io_brupdate_b2_uop_fp_ctrl_ren2; // @[util.scala:688:7]
wire io_brupdate_b2_uop_fp_ctrl_ren3_0 = io_brupdate_b2_uop_fp_ctrl_ren3; // @[util.scala:688:7]
wire io_brupdate_b2_uop_fp_ctrl_swap12_0 = io_brupdate_b2_uop_fp_ctrl_swap12; // @[util.scala:688:7]
wire io_brupdate_b2_uop_fp_ctrl_swap23_0 = io_brupdate_b2_uop_fp_ctrl_swap23; // @[util.scala:688:7]
wire [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagIn_0 = io_brupdate_b2_uop_fp_ctrl_typeTagIn; // @[util.scala:688:7]
wire [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagOut_0 = io_brupdate_b2_uop_fp_ctrl_typeTagOut; // @[util.scala:688:7]
wire io_brupdate_b2_uop_fp_ctrl_fromint_0 = io_brupdate_b2_uop_fp_ctrl_fromint; // @[util.scala:688:7]
wire io_brupdate_b2_uop_fp_ctrl_toint_0 = io_brupdate_b2_uop_fp_ctrl_toint; // @[util.scala:688:7]
wire io_brupdate_b2_uop_fp_ctrl_fastpipe_0 = io_brupdate_b2_uop_fp_ctrl_fastpipe; // @[util.scala:688:7]
wire io_brupdate_b2_uop_fp_ctrl_fma_0 = io_brupdate_b2_uop_fp_ctrl_fma; // @[util.scala:688:7]
wire io_brupdate_b2_uop_fp_ctrl_div_0 = io_brupdate_b2_uop_fp_ctrl_div; // @[util.scala:688:7]
wire io_brupdate_b2_uop_fp_ctrl_sqrt_0 = io_brupdate_b2_uop_fp_ctrl_sqrt; // @[util.scala:688:7]
wire io_brupdate_b2_uop_fp_ctrl_wflags_0 = io_brupdate_b2_uop_fp_ctrl_wflags; // @[util.scala:688:7]
wire io_brupdate_b2_uop_fp_ctrl_vec_0 = io_brupdate_b2_uop_fp_ctrl_vec; // @[util.scala:688:7]
wire [6:0] io_brupdate_b2_uop_rob_idx_0 = io_brupdate_b2_uop_rob_idx; // @[util.scala:688:7]
wire [4:0] io_brupdate_b2_uop_ldq_idx_0 = io_brupdate_b2_uop_ldq_idx; // @[util.scala:688:7]
wire [4:0] io_brupdate_b2_uop_stq_idx_0 = io_brupdate_b2_uop_stq_idx; // @[util.scala:688:7]
wire [1:0] io_brupdate_b2_uop_rxq_idx_0 = io_brupdate_b2_uop_rxq_idx; // @[util.scala:688:7]
wire [6:0] io_brupdate_b2_uop_pdst_0 = io_brupdate_b2_uop_pdst; // @[util.scala:688:7]
wire [6:0] io_brupdate_b2_uop_prs1_0 = io_brupdate_b2_uop_prs1; // @[util.scala:688:7]
wire [6:0] io_brupdate_b2_uop_prs2_0 = io_brupdate_b2_uop_prs2; // @[util.scala:688:7]
wire [6:0] io_brupdate_b2_uop_prs3_0 = io_brupdate_b2_uop_prs3; // @[util.scala:688:7]
wire [4:0] io_brupdate_b2_uop_ppred_0 = io_brupdate_b2_uop_ppred; // @[util.scala:688:7]
wire io_brupdate_b2_uop_prs1_busy_0 = io_brupdate_b2_uop_prs1_busy; // @[util.scala:688:7]
wire io_brupdate_b2_uop_prs2_busy_0 = io_brupdate_b2_uop_prs2_busy; // @[util.scala:688:7]
wire io_brupdate_b2_uop_prs3_busy_0 = io_brupdate_b2_uop_prs3_busy; // @[util.scala:688:7]
wire io_brupdate_b2_uop_ppred_busy_0 = io_brupdate_b2_uop_ppred_busy; // @[util.scala:688:7]
wire [6:0] io_brupdate_b2_uop_stale_pdst_0 = io_brupdate_b2_uop_stale_pdst; // @[util.scala:688:7]
wire io_brupdate_b2_uop_exception_0 = io_brupdate_b2_uop_exception; // @[util.scala:688:7]
wire [63:0] io_brupdate_b2_uop_exc_cause_0 = io_brupdate_b2_uop_exc_cause; // @[util.scala:688:7]
wire [4:0] io_brupdate_b2_uop_mem_cmd_0 = io_brupdate_b2_uop_mem_cmd; // @[util.scala:688:7]
wire [1:0] io_brupdate_b2_uop_mem_size_0 = io_brupdate_b2_uop_mem_size; // @[util.scala:688:7]
wire io_brupdate_b2_uop_mem_signed_0 = io_brupdate_b2_uop_mem_signed; // @[util.scala:688:7]
wire io_brupdate_b2_uop_uses_ldq_0 = io_brupdate_b2_uop_uses_ldq; // @[util.scala:688:7]
wire io_brupdate_b2_uop_uses_stq_0 = io_brupdate_b2_uop_uses_stq; // @[util.scala:688:7]
wire io_brupdate_b2_uop_is_unique_0 = io_brupdate_b2_uop_is_unique; // @[util.scala:688:7]
wire io_brupdate_b2_uop_flush_on_commit_0 = io_brupdate_b2_uop_flush_on_commit; // @[util.scala:688:7]
wire [2:0] io_brupdate_b2_uop_csr_cmd_0 = io_brupdate_b2_uop_csr_cmd; // @[util.scala:688:7]
wire io_brupdate_b2_uop_ldst_is_rs1_0 = io_brupdate_b2_uop_ldst_is_rs1; // @[util.scala:688:7]
wire [5:0] io_brupdate_b2_uop_ldst_0 = io_brupdate_b2_uop_ldst; // @[util.scala:688:7]
wire [5:0] io_brupdate_b2_uop_lrs1_0 = io_brupdate_b2_uop_lrs1; // @[util.scala:688:7]
wire [5:0] io_brupdate_b2_uop_lrs2_0 = io_brupdate_b2_uop_lrs2; // @[util.scala:688:7]
wire [5:0] io_brupdate_b2_uop_lrs3_0 = io_brupdate_b2_uop_lrs3; // @[util.scala:688:7]
wire [1:0] io_brupdate_b2_uop_dst_rtype_0 = io_brupdate_b2_uop_dst_rtype; // @[util.scala:688:7]
wire [1:0] io_brupdate_b2_uop_lrs1_rtype_0 = io_brupdate_b2_uop_lrs1_rtype; // @[util.scala:688:7]
wire [1:0] io_brupdate_b2_uop_lrs2_rtype_0 = io_brupdate_b2_uop_lrs2_rtype; // @[util.scala:688:7]
wire io_brupdate_b2_uop_frs3_en_0 = io_brupdate_b2_uop_frs3_en; // @[util.scala:688:7]
wire io_brupdate_b2_uop_fcn_dw_0 = io_brupdate_b2_uop_fcn_dw; // @[util.scala:688:7]
wire [4:0] io_brupdate_b2_uop_fcn_op_0 = io_brupdate_b2_uop_fcn_op; // @[util.scala:688:7]
wire io_brupdate_b2_uop_fp_val_0 = io_brupdate_b2_uop_fp_val; // @[util.scala:688:7]
wire [2:0] io_brupdate_b2_uop_fp_rm_0 = io_brupdate_b2_uop_fp_rm; // @[util.scala:688:7]
wire [1:0] io_brupdate_b2_uop_fp_typ_0 = io_brupdate_b2_uop_fp_typ; // @[util.scala:688:7]
wire io_brupdate_b2_uop_xcpt_pf_if_0 = io_brupdate_b2_uop_xcpt_pf_if; // @[util.scala:688:7]
wire io_brupdate_b2_uop_xcpt_ae_if_0 = io_brupdate_b2_uop_xcpt_ae_if; // @[util.scala:688:7]
wire io_brupdate_b2_uop_xcpt_ma_if_0 = io_brupdate_b2_uop_xcpt_ma_if; // @[util.scala:688:7]
wire io_brupdate_b2_uop_bp_debug_if_0 = io_brupdate_b2_uop_bp_debug_if; // @[util.scala:688:7]
wire io_brupdate_b2_uop_bp_xcpt_if_0 = io_brupdate_b2_uop_bp_xcpt_if; // @[util.scala:688:7]
wire [2:0] io_brupdate_b2_uop_debug_fsrc_0 = io_brupdate_b2_uop_debug_fsrc; // @[util.scala:688:7]
wire [2:0] io_brupdate_b2_uop_debug_tsrc_0 = io_brupdate_b2_uop_debug_tsrc; // @[util.scala:688:7]
wire io_brupdate_b2_mispredict_0 = io_brupdate_b2_mispredict; // @[util.scala:688:7]
wire io_brupdate_b2_taken_0 = io_brupdate_b2_taken; // @[util.scala:688:7]
wire [2:0] io_brupdate_b2_cfi_type_0 = io_brupdate_b2_cfi_type; // @[util.scala:688:7]
wire [1:0] io_brupdate_b2_pc_sel_0 = io_brupdate_b2_pc_sel; // @[util.scala:688:7]
wire [39:0] io_brupdate_b2_jalr_target_0 = io_brupdate_b2_jalr_target; // @[util.scala:688:7]
wire [20:0] io_brupdate_b2_target_offset_0 = io_brupdate_b2_target_offset; // @[util.scala:688:7]
wire [2:0] io_req_bits_ftq_info_0_entry_cfi_idx_bits = 3'h0; // @[util.scala:688:7]
wire [2:0] io_req_bits_ftq_info_0_entry_cfi_type = 3'h0; // @[util.scala:688:7]
wire [2:0] io_req_bits_ftq_info_1_entry_cfi_idx_bits = 3'h0; // @[util.scala:688:7]
wire [2:0] io_req_bits_ftq_info_1_entry_cfi_type = 3'h0; // @[util.scala:688:7]
wire [2:0] io_resp_0_bits_ftq_info_0_entry_cfi_idx_bits = 3'h0; // @[util.scala:688:7]
wire [2:0] io_resp_0_bits_ftq_info_0_entry_cfi_type = 3'h0; // @[util.scala:688:7]
wire [2:0] io_resp_0_bits_ftq_info_1_entry_cfi_idx_bits = 3'h0; // @[util.scala:688:7]
wire [2:0] io_resp_0_bits_ftq_info_1_entry_cfi_type = 3'h0; // @[util.scala:688:7]
wire [2:0] uops_0_bits_out_ftq_info_0_entry_cfi_idx_bits = 3'h0; // @[util.scala:109:23]
wire [2:0] uops_0_bits_out_ftq_info_0_entry_cfi_type = 3'h0; // @[util.scala:109:23]
wire [2:0] uops_0_bits_out_ftq_info_1_entry_cfi_idx_bits = 3'h0; // @[util.scala:109:23]
wire [2:0] uops_0_bits_out_ftq_info_1_entry_cfi_type = 3'h0; // @[util.scala:109:23]
wire [2:0] uops_1_bits_out_ftq_info_0_entry_cfi_idx_bits = 3'h0; // @[util.scala:109:23]
wire [2:0] uops_1_bits_out_ftq_info_0_entry_cfi_type = 3'h0; // @[util.scala:109:23]
wire [2:0] uops_1_bits_out_ftq_info_1_entry_cfi_idx_bits = 3'h0; // @[util.scala:109:23]
wire [2:0] uops_1_bits_out_ftq_info_1_entry_cfi_type = 3'h0; // @[util.scala:109:23]
wire [7:0] io_req_bits_ftq_info_0_entry_br_mask = 8'h0; // @[util.scala:688:7]
wire [7:0] io_req_bits_ftq_info_1_entry_br_mask = 8'h0; // @[util.scala:688:7]
wire [7:0] io_resp_0_bits_ftq_info_0_entry_br_mask = 8'h0; // @[util.scala:688:7]
wire [7:0] io_resp_0_bits_ftq_info_1_entry_br_mask = 8'h0; // @[util.scala:688:7]
wire [7:0] uops_0_bits_out_ftq_info_0_entry_br_mask = 8'h0; // @[util.scala:109:23]
wire [7:0] uops_0_bits_out_ftq_info_1_entry_br_mask = 8'h0; // @[util.scala:109:23]
wire [7:0] uops_1_bits_out_ftq_info_0_entry_br_mask = 8'h0; // @[util.scala:109:23]
wire [7:0] uops_1_bits_out_ftq_info_1_entry_br_mask = 8'h0; // @[util.scala:109:23]
wire [63:0] io_req_bits_rs3_data = 64'h0; // @[util.scala:688:7]
wire [63:0] io_req_bits_ftq_info_0_ghist_old_history = 64'h0; // @[util.scala:688:7]
wire [63:0] io_req_bits_ftq_info_1_ghist_old_history = 64'h0; // @[util.scala:688:7]
wire [63:0] io_resp_0_bits_rs3_data = 64'h0; // @[util.scala:688:7]
wire [63:0] io_resp_0_bits_ftq_info_0_ghist_old_history = 64'h0; // @[util.scala:688:7]
wire [63:0] io_resp_0_bits_ftq_info_1_ghist_old_history = 64'h0; // @[util.scala:688:7]
wire [63:0] uops_0_bits_out_rs3_data = 64'h0; // @[util.scala:109:23]
wire [63:0] uops_0_bits_out_ftq_info_0_ghist_old_history = 64'h0; // @[util.scala:109:23]
wire [63:0] uops_0_bits_out_ftq_info_1_ghist_old_history = 64'h0; // @[util.scala:109:23]
wire [63:0] uops_1_bits_out_rs3_data = 64'h0; // @[util.scala:109:23]
wire [63:0] uops_1_bits_out_ftq_info_0_ghist_old_history = 64'h0; // @[util.scala:109:23]
wire [63:0] uops_1_bits_out_ftq_info_1_ghist_old_history = 64'h0; // @[util.scala:109:23]
wire [4:0] io_req_bits_ftq_info_0_entry_ras_idx = 5'h0; // @[util.scala:688:7]
wire [4:0] io_req_bits_ftq_info_0_ghist_ras_idx = 5'h0; // @[util.scala:688:7]
wire [4:0] io_req_bits_ftq_info_1_entry_ras_idx = 5'h0; // @[util.scala:688:7]
wire [4:0] io_req_bits_ftq_info_1_ghist_ras_idx = 5'h0; // @[util.scala:688:7]
wire [4:0] io_resp_0_bits_ftq_info_0_entry_ras_idx = 5'h0; // @[util.scala:688:7]
wire [4:0] io_resp_0_bits_ftq_info_0_ghist_ras_idx = 5'h0; // @[util.scala:688:7]
wire [4:0] io_resp_0_bits_ftq_info_1_entry_ras_idx = 5'h0; // @[util.scala:688:7]
wire [4:0] io_resp_0_bits_ftq_info_1_ghist_ras_idx = 5'h0; // @[util.scala:688:7]
wire [4:0] uops_0_bits_out_ftq_info_0_entry_ras_idx = 5'h0; // @[util.scala:109:23]
wire [4:0] uops_0_bits_out_ftq_info_0_ghist_ras_idx = 5'h0; // @[util.scala:109:23]
wire [4:0] uops_0_bits_out_ftq_info_1_entry_ras_idx = 5'h0; // @[util.scala:109:23]
wire [4:0] uops_0_bits_out_ftq_info_1_ghist_ras_idx = 5'h0; // @[util.scala:109:23]
wire [4:0] uops_1_bits_out_ftq_info_0_entry_ras_idx = 5'h0; // @[util.scala:109:23]
wire [4:0] uops_1_bits_out_ftq_info_0_ghist_ras_idx = 5'h0; // @[util.scala:109:23]
wire [4:0] uops_1_bits_out_ftq_info_1_entry_ras_idx = 5'h0; // @[util.scala:109:23]
wire [4:0] uops_1_bits_out_ftq_info_1_ghist_ras_idx = 5'h0; // @[util.scala:109:23]
wire [39:0] io_req_bits_ftq_info_0_entry_ras_top = 40'h0; // @[util.scala:688:7]
wire [39:0] io_req_bits_ftq_info_0_pc = 40'h0; // @[util.scala:688:7]
wire [39:0] io_req_bits_ftq_info_1_entry_ras_top = 40'h0; // @[util.scala:688:7]
wire [39:0] io_req_bits_ftq_info_1_pc = 40'h0; // @[util.scala:688:7]
wire [39:0] io_resp_0_bits_ftq_info_0_entry_ras_top = 40'h0; // @[util.scala:688:7]
wire [39:0] io_resp_0_bits_ftq_info_0_pc = 40'h0; // @[util.scala:688:7]
wire [39:0] io_resp_0_bits_ftq_info_1_entry_ras_top = 40'h0; // @[util.scala:688:7]
wire [39:0] io_resp_0_bits_ftq_info_1_pc = 40'h0; // @[util.scala:688:7]
wire [39:0] uops_0_bits_out_ftq_info_0_entry_ras_top = 40'h0; // @[util.scala:109:23]
wire [39:0] uops_0_bits_out_ftq_info_0_pc = 40'h0; // @[util.scala:109:23]
wire [39:0] uops_0_bits_out_ftq_info_1_entry_ras_top = 40'h0; // @[util.scala:109:23]
wire [39:0] uops_0_bits_out_ftq_info_1_pc = 40'h0; // @[util.scala:109:23]
wire [39:0] uops_1_bits_out_ftq_info_0_entry_ras_top = 40'h0; // @[util.scala:109:23]
wire [39:0] uops_1_bits_out_ftq_info_0_pc = 40'h0; // @[util.scala:109:23]
wire [39:0] uops_1_bits_out_ftq_info_1_entry_ras_top = 40'h0; // @[util.scala:109:23]
wire [39:0] uops_1_bits_out_ftq_info_1_pc = 40'h0; // @[util.scala:109:23]
wire io_req_bits_ftq_info_0_valid = 1'h0; // @[util.scala:688:7]
wire io_req_bits_ftq_info_0_entry_cfi_idx_valid = 1'h0; // @[util.scala:688:7]
wire io_req_bits_ftq_info_0_entry_cfi_taken = 1'h0; // @[util.scala:688:7]
wire io_req_bits_ftq_info_0_entry_cfi_mispredicted = 1'h0; // @[util.scala:688:7]
wire io_req_bits_ftq_info_0_entry_cfi_is_call = 1'h0; // @[util.scala:688:7]
wire io_req_bits_ftq_info_0_entry_cfi_is_ret = 1'h0; // @[util.scala:688:7]
wire io_req_bits_ftq_info_0_entry_cfi_npc_plus4 = 1'h0; // @[util.scala:688:7]
wire io_req_bits_ftq_info_0_entry_start_bank = 1'h0; // @[util.scala:688:7]
wire io_req_bits_ftq_info_0_ghist_current_saw_branch_not_taken = 1'h0; // @[util.scala:688:7]
wire io_req_bits_ftq_info_0_ghist_new_saw_branch_not_taken = 1'h0; // @[util.scala:688:7]
wire io_req_bits_ftq_info_0_ghist_new_saw_branch_taken = 1'h0; // @[util.scala:688:7]
wire io_req_bits_ftq_info_1_valid = 1'h0; // @[util.scala:688:7]
wire io_req_bits_ftq_info_1_entry_cfi_idx_valid = 1'h0; // @[util.scala:688:7]
wire io_req_bits_ftq_info_1_entry_cfi_taken = 1'h0; // @[util.scala:688:7]
wire io_req_bits_ftq_info_1_entry_cfi_mispredicted = 1'h0; // @[util.scala:688:7]
wire io_req_bits_ftq_info_1_entry_cfi_is_call = 1'h0; // @[util.scala:688:7]
wire io_req_bits_ftq_info_1_entry_cfi_is_ret = 1'h0; // @[util.scala:688:7]
wire io_req_bits_ftq_info_1_entry_cfi_npc_plus4 = 1'h0; // @[util.scala:688:7]
wire io_req_bits_ftq_info_1_entry_start_bank = 1'h0; // @[util.scala:688:7]
wire io_req_bits_ftq_info_1_ghist_current_saw_branch_not_taken = 1'h0; // @[util.scala:688:7]
wire io_req_bits_ftq_info_1_ghist_new_saw_branch_not_taken = 1'h0; // @[util.scala:688:7]
wire io_req_bits_ftq_info_1_ghist_new_saw_branch_taken = 1'h0; // @[util.scala:688:7]
wire io_req_bits_pred_data = 1'h0; // @[util.scala:688:7]
wire io_resp_0_bits_ftq_info_0_valid = 1'h0; // @[util.scala:688:7]
wire io_resp_0_bits_ftq_info_0_entry_cfi_idx_valid = 1'h0; // @[util.scala:688:7]
wire io_resp_0_bits_ftq_info_0_entry_cfi_taken = 1'h0; // @[util.scala:688:7]
wire io_resp_0_bits_ftq_info_0_entry_cfi_mispredicted = 1'h0; // @[util.scala:688:7]
wire io_resp_0_bits_ftq_info_0_entry_cfi_is_call = 1'h0; // @[util.scala:688:7]
wire io_resp_0_bits_ftq_info_0_entry_cfi_is_ret = 1'h0; // @[util.scala:688:7]
wire io_resp_0_bits_ftq_info_0_entry_cfi_npc_plus4 = 1'h0; // @[util.scala:688:7]
wire io_resp_0_bits_ftq_info_0_entry_start_bank = 1'h0; // @[util.scala:688:7]
wire io_resp_0_bits_ftq_info_0_ghist_current_saw_branch_not_taken = 1'h0; // @[util.scala:688:7]
wire io_resp_0_bits_ftq_info_0_ghist_new_saw_branch_not_taken = 1'h0; // @[util.scala:688:7]
wire io_resp_0_bits_ftq_info_0_ghist_new_saw_branch_taken = 1'h0; // @[util.scala:688:7]
wire io_resp_0_bits_ftq_info_1_valid = 1'h0; // @[util.scala:688:7]
wire io_resp_0_bits_ftq_info_1_entry_cfi_idx_valid = 1'h0; // @[util.scala:688:7]
wire io_resp_0_bits_ftq_info_1_entry_cfi_taken = 1'h0; // @[util.scala:688:7]
wire io_resp_0_bits_ftq_info_1_entry_cfi_mispredicted = 1'h0; // @[util.scala:688:7]
wire io_resp_0_bits_ftq_info_1_entry_cfi_is_call = 1'h0; // @[util.scala:688:7]
wire io_resp_0_bits_ftq_info_1_entry_cfi_is_ret = 1'h0; // @[util.scala:688:7]
wire io_resp_0_bits_ftq_info_1_entry_cfi_npc_plus4 = 1'h0; // @[util.scala:688:7]
wire io_resp_0_bits_ftq_info_1_entry_start_bank = 1'h0; // @[util.scala:688:7]
wire io_resp_0_bits_ftq_info_1_ghist_current_saw_branch_not_taken = 1'h0; // @[util.scala:688:7]
wire io_resp_0_bits_ftq_info_1_ghist_new_saw_branch_not_taken = 1'h0; // @[util.scala:688:7]
wire io_resp_0_bits_ftq_info_1_ghist_new_saw_branch_taken = 1'h0; // @[util.scala:688:7]
wire io_resp_0_bits_pred_data = 1'h0; // @[util.scala:688:7]
wire uops_0_bits_out_ftq_info_0_valid = 1'h0; // @[util.scala:109:23]
wire uops_0_bits_out_ftq_info_0_entry_cfi_idx_valid = 1'h0; // @[util.scala:109:23]
wire uops_0_bits_out_ftq_info_0_entry_cfi_taken = 1'h0; // @[util.scala:109:23]
wire uops_0_bits_out_ftq_info_0_entry_cfi_mispredicted = 1'h0; // @[util.scala:109:23]
wire uops_0_bits_out_ftq_info_0_entry_cfi_is_call = 1'h0; // @[util.scala:109:23]
wire uops_0_bits_out_ftq_info_0_entry_cfi_is_ret = 1'h0; // @[util.scala:109:23]
wire uops_0_bits_out_ftq_info_0_entry_cfi_npc_plus4 = 1'h0; // @[util.scala:109:23]
wire uops_0_bits_out_ftq_info_0_entry_start_bank = 1'h0; // @[util.scala:109:23]
wire uops_0_bits_out_ftq_info_0_ghist_current_saw_branch_not_taken = 1'h0; // @[util.scala:109:23]
wire uops_0_bits_out_ftq_info_0_ghist_new_saw_branch_not_taken = 1'h0; // @[util.scala:109:23]
wire uops_0_bits_out_ftq_info_0_ghist_new_saw_branch_taken = 1'h0; // @[util.scala:109:23]
wire uops_0_bits_out_ftq_info_1_valid = 1'h0; // @[util.scala:109:23]
wire uops_0_bits_out_ftq_info_1_entry_cfi_idx_valid = 1'h0; // @[util.scala:109:23]
wire uops_0_bits_out_ftq_info_1_entry_cfi_taken = 1'h0; // @[util.scala:109:23]
wire uops_0_bits_out_ftq_info_1_entry_cfi_mispredicted = 1'h0; // @[util.scala:109:23]
wire uops_0_bits_out_ftq_info_1_entry_cfi_is_call = 1'h0; // @[util.scala:109:23]
wire uops_0_bits_out_ftq_info_1_entry_cfi_is_ret = 1'h0; // @[util.scala:109:23]
wire uops_0_bits_out_ftq_info_1_entry_cfi_npc_plus4 = 1'h0; // @[util.scala:109:23]
wire uops_0_bits_out_ftq_info_1_entry_start_bank = 1'h0; // @[util.scala:109:23]
wire uops_0_bits_out_ftq_info_1_ghist_current_saw_branch_not_taken = 1'h0; // @[util.scala:109:23]
wire uops_0_bits_out_ftq_info_1_ghist_new_saw_branch_not_taken = 1'h0; // @[util.scala:109:23]
wire uops_0_bits_out_ftq_info_1_ghist_new_saw_branch_taken = 1'h0; // @[util.scala:109:23]
wire uops_0_bits_out_pred_data = 1'h0; // @[util.scala:109:23]
wire uops_1_bits_out_ftq_info_0_valid = 1'h0; // @[util.scala:109:23]
wire uops_1_bits_out_ftq_info_0_entry_cfi_idx_valid = 1'h0; // @[util.scala:109:23]
wire uops_1_bits_out_ftq_info_0_entry_cfi_taken = 1'h0; // @[util.scala:109:23]
wire uops_1_bits_out_ftq_info_0_entry_cfi_mispredicted = 1'h0; // @[util.scala:109:23]
wire uops_1_bits_out_ftq_info_0_entry_cfi_is_call = 1'h0; // @[util.scala:109:23]
wire uops_1_bits_out_ftq_info_0_entry_cfi_is_ret = 1'h0; // @[util.scala:109:23]
wire uops_1_bits_out_ftq_info_0_entry_cfi_npc_plus4 = 1'h0; // @[util.scala:109:23]
wire uops_1_bits_out_ftq_info_0_entry_start_bank = 1'h0; // @[util.scala:109:23]
wire uops_1_bits_out_ftq_info_0_ghist_current_saw_branch_not_taken = 1'h0; // @[util.scala:109:23]
wire uops_1_bits_out_ftq_info_0_ghist_new_saw_branch_not_taken = 1'h0; // @[util.scala:109:23]
wire uops_1_bits_out_ftq_info_0_ghist_new_saw_branch_taken = 1'h0; // @[util.scala:109:23]
wire uops_1_bits_out_ftq_info_1_valid = 1'h0; // @[util.scala:109:23]
wire uops_1_bits_out_ftq_info_1_entry_cfi_idx_valid = 1'h0; // @[util.scala:109:23]
wire uops_1_bits_out_ftq_info_1_entry_cfi_taken = 1'h0; // @[util.scala:109:23]
wire uops_1_bits_out_ftq_info_1_entry_cfi_mispredicted = 1'h0; // @[util.scala:109:23]
wire uops_1_bits_out_ftq_info_1_entry_cfi_is_call = 1'h0; // @[util.scala:109:23]
wire uops_1_bits_out_ftq_info_1_entry_cfi_is_ret = 1'h0; // @[util.scala:109:23]
wire uops_1_bits_out_ftq_info_1_entry_cfi_npc_plus4 = 1'h0; // @[util.scala:109:23]
wire uops_1_bits_out_ftq_info_1_entry_start_bank = 1'h0; // @[util.scala:109:23]
wire uops_1_bits_out_ftq_info_1_ghist_current_saw_branch_not_taken = 1'h0; // @[util.scala:109:23]
wire uops_1_bits_out_ftq_info_1_ghist_new_saw_branch_not_taken = 1'h0; // @[util.scala:109:23]
wire uops_1_bits_out_ftq_info_1_ghist_new_saw_branch_taken = 1'h0; // @[util.scala:109:23]
wire uops_1_bits_out_pred_data = 1'h0; // @[util.scala:109:23]
wire [31:0] uops_0_bits_out_uop_inst = io_req_bits_uop_inst_0; // @[util.scala:109:23, :688:7]
wire [31:0] uops_0_bits_out_uop_debug_inst = io_req_bits_uop_debug_inst_0; // @[util.scala:109:23, :688:7]
wire uops_0_bits_out_uop_is_rvc = io_req_bits_uop_is_rvc_0; // @[util.scala:109:23, :688:7]
wire [39:0] uops_0_bits_out_uop_debug_pc = io_req_bits_uop_debug_pc_0; // @[util.scala:109:23, :688:7]
wire uops_0_bits_out_uop_iq_type_0 = io_req_bits_uop_iq_type_0_0; // @[util.scala:109:23, :688:7]
wire uops_0_bits_out_uop_iq_type_1 = io_req_bits_uop_iq_type_1_0; // @[util.scala:109:23, :688:7]
wire uops_0_bits_out_uop_iq_type_2 = io_req_bits_uop_iq_type_2_0; // @[util.scala:109:23, :688:7]
wire uops_0_bits_out_uop_iq_type_3 = io_req_bits_uop_iq_type_3_0; // @[util.scala:109:23, :688:7]
wire uops_0_bits_out_uop_fu_code_0 = io_req_bits_uop_fu_code_0_0; // @[util.scala:109:23, :688:7]
wire uops_0_bits_out_uop_fu_code_1 = io_req_bits_uop_fu_code_1_0; // @[util.scala:109:23, :688:7]
wire uops_0_bits_out_uop_fu_code_2 = io_req_bits_uop_fu_code_2_0; // @[util.scala:109:23, :688:7]
wire uops_0_bits_out_uop_fu_code_3 = io_req_bits_uop_fu_code_3_0; // @[util.scala:109:23, :688:7]
wire uops_0_bits_out_uop_fu_code_4 = io_req_bits_uop_fu_code_4_0; // @[util.scala:109:23, :688:7]
wire uops_0_bits_out_uop_fu_code_5 = io_req_bits_uop_fu_code_5_0; // @[util.scala:109:23, :688:7]
wire uops_0_bits_out_uop_fu_code_6 = io_req_bits_uop_fu_code_6_0; // @[util.scala:109:23, :688:7]
wire uops_0_bits_out_uop_fu_code_7 = io_req_bits_uop_fu_code_7_0; // @[util.scala:109:23, :688:7]
wire uops_0_bits_out_uop_fu_code_8 = io_req_bits_uop_fu_code_8_0; // @[util.scala:109:23, :688:7]
wire uops_0_bits_out_uop_fu_code_9 = io_req_bits_uop_fu_code_9_0; // @[util.scala:109:23, :688:7]
wire uops_0_bits_out_uop_iw_issued = io_req_bits_uop_iw_issued_0; // @[util.scala:109:23, :688:7]
wire uops_0_bits_out_uop_iw_issued_partial_agen = io_req_bits_uop_iw_issued_partial_agen_0; // @[util.scala:109:23, :688:7]
wire uops_0_bits_out_uop_iw_issued_partial_dgen = io_req_bits_uop_iw_issued_partial_dgen_0; // @[util.scala:109:23, :688:7]
wire [2:0] uops_0_bits_out_uop_iw_p1_speculative_child = io_req_bits_uop_iw_p1_speculative_child_0; // @[util.scala:109:23, :688:7]
wire [2:0] uops_0_bits_out_uop_iw_p2_speculative_child = io_req_bits_uop_iw_p2_speculative_child_0; // @[util.scala:109:23, :688:7]
wire uops_0_bits_out_uop_iw_p1_bypass_hint = io_req_bits_uop_iw_p1_bypass_hint_0; // @[util.scala:109:23, :688:7]
wire uops_0_bits_out_uop_iw_p2_bypass_hint = io_req_bits_uop_iw_p2_bypass_hint_0; // @[util.scala:109:23, :688:7]
wire uops_0_bits_out_uop_iw_p3_bypass_hint = io_req_bits_uop_iw_p3_bypass_hint_0; // @[util.scala:109:23, :688:7]
wire [2:0] uops_0_bits_out_uop_dis_col_sel = io_req_bits_uop_dis_col_sel_0; // @[util.scala:109:23, :688:7]
wire [3:0] uops_0_bits_out_uop_br_tag = io_req_bits_uop_br_tag_0; // @[util.scala:109:23, :688:7]
wire [3:0] uops_0_bits_out_uop_br_type = io_req_bits_uop_br_type_0; // @[util.scala:109:23, :688:7]
wire uops_0_bits_out_uop_is_sfb = io_req_bits_uop_is_sfb_0; // @[util.scala:109:23, :688:7]
wire uops_0_bits_out_uop_is_fence = io_req_bits_uop_is_fence_0; // @[util.scala:109:23, :688:7]
wire uops_0_bits_out_uop_is_fencei = io_req_bits_uop_is_fencei_0; // @[util.scala:109:23, :688:7]
wire uops_0_bits_out_uop_is_sfence = io_req_bits_uop_is_sfence_0; // @[util.scala:109:23, :688:7]
wire uops_0_bits_out_uop_is_amo = io_req_bits_uop_is_amo_0; // @[util.scala:109:23, :688:7]
wire uops_0_bits_out_uop_is_eret = io_req_bits_uop_is_eret_0; // @[util.scala:109:23, :688:7]
wire uops_0_bits_out_uop_is_sys_pc2epc = io_req_bits_uop_is_sys_pc2epc_0; // @[util.scala:109:23, :688:7]
wire uops_0_bits_out_uop_is_rocc = io_req_bits_uop_is_rocc_0; // @[util.scala:109:23, :688:7]
wire uops_0_bits_out_uop_is_mov = io_req_bits_uop_is_mov_0; // @[util.scala:109:23, :688:7]
wire [4:0] uops_0_bits_out_uop_ftq_idx = io_req_bits_uop_ftq_idx_0; // @[util.scala:109:23, :688:7]
wire uops_0_bits_out_uop_edge_inst = io_req_bits_uop_edge_inst_0; // @[util.scala:109:23, :688:7]
wire [5:0] uops_0_bits_out_uop_pc_lob = io_req_bits_uop_pc_lob_0; // @[util.scala:109:23, :688:7]
wire uops_0_bits_out_uop_taken = io_req_bits_uop_taken_0; // @[util.scala:109:23, :688:7]
wire uops_0_bits_out_uop_imm_rename = io_req_bits_uop_imm_rename_0; // @[util.scala:109:23, :688:7]
wire [2:0] uops_0_bits_out_uop_imm_sel = io_req_bits_uop_imm_sel_0; // @[util.scala:109:23, :688:7]
wire [4:0] uops_0_bits_out_uop_pimm = io_req_bits_uop_pimm_0; // @[util.scala:109:23, :688:7]
wire [19:0] uops_0_bits_out_uop_imm_packed = io_req_bits_uop_imm_packed_0; // @[util.scala:109:23, :688:7]
wire [1:0] uops_0_bits_out_uop_op1_sel = io_req_bits_uop_op1_sel_0; // @[util.scala:109:23, :688:7]
wire [2:0] uops_0_bits_out_uop_op2_sel = io_req_bits_uop_op2_sel_0; // @[util.scala:109:23, :688:7]
wire uops_0_bits_out_uop_fp_ctrl_ldst = io_req_bits_uop_fp_ctrl_ldst_0; // @[util.scala:109:23, :688:7]
wire uops_0_bits_out_uop_fp_ctrl_wen = io_req_bits_uop_fp_ctrl_wen_0; // @[util.scala:109:23, :688:7]
wire uops_0_bits_out_uop_fp_ctrl_ren1 = io_req_bits_uop_fp_ctrl_ren1_0; // @[util.scala:109:23, :688:7]
wire uops_0_bits_out_uop_fp_ctrl_ren2 = io_req_bits_uop_fp_ctrl_ren2_0; // @[util.scala:109:23, :688:7]
wire uops_0_bits_out_uop_fp_ctrl_ren3 = io_req_bits_uop_fp_ctrl_ren3_0; // @[util.scala:109:23, :688:7]
wire uops_0_bits_out_uop_fp_ctrl_swap12 = io_req_bits_uop_fp_ctrl_swap12_0; // @[util.scala:109:23, :688:7]
wire uops_0_bits_out_uop_fp_ctrl_swap23 = io_req_bits_uop_fp_ctrl_swap23_0; // @[util.scala:109:23, :688:7]
wire [1:0] uops_0_bits_out_uop_fp_ctrl_typeTagIn = io_req_bits_uop_fp_ctrl_typeTagIn_0; // @[util.scala:109:23, :688:7]
wire [1:0] uops_0_bits_out_uop_fp_ctrl_typeTagOut = io_req_bits_uop_fp_ctrl_typeTagOut_0; // @[util.scala:109:23, :688:7]
wire uops_0_bits_out_uop_fp_ctrl_fromint = io_req_bits_uop_fp_ctrl_fromint_0; // @[util.scala:109:23, :688:7]
wire uops_0_bits_out_uop_fp_ctrl_toint = io_req_bits_uop_fp_ctrl_toint_0; // @[util.scala:109:23, :688:7]
wire uops_0_bits_out_uop_fp_ctrl_fastpipe = io_req_bits_uop_fp_ctrl_fastpipe_0; // @[util.scala:109:23, :688:7]
wire uops_0_bits_out_uop_fp_ctrl_fma = io_req_bits_uop_fp_ctrl_fma_0; // @[util.scala:109:23, :688:7]
wire uops_0_bits_out_uop_fp_ctrl_div = io_req_bits_uop_fp_ctrl_div_0; // @[util.scala:109:23, :688:7]
wire uops_0_bits_out_uop_fp_ctrl_sqrt = io_req_bits_uop_fp_ctrl_sqrt_0; // @[util.scala:109:23, :688:7]
wire uops_0_bits_out_uop_fp_ctrl_wflags = io_req_bits_uop_fp_ctrl_wflags_0; // @[util.scala:109:23, :688:7]
wire uops_0_bits_out_uop_fp_ctrl_vec = io_req_bits_uop_fp_ctrl_vec_0; // @[util.scala:109:23, :688:7]
wire [6:0] uops_0_bits_out_uop_rob_idx = io_req_bits_uop_rob_idx_0; // @[util.scala:109:23, :688:7]
wire [4:0] uops_0_bits_out_uop_ldq_idx = io_req_bits_uop_ldq_idx_0; // @[util.scala:109:23, :688:7]
wire [4:0] uops_0_bits_out_uop_stq_idx = io_req_bits_uop_stq_idx_0; // @[util.scala:109:23, :688:7]
wire [1:0] uops_0_bits_out_uop_rxq_idx = io_req_bits_uop_rxq_idx_0; // @[util.scala:109:23, :688:7]
wire [6:0] uops_0_bits_out_uop_pdst = io_req_bits_uop_pdst_0; // @[util.scala:109:23, :688:7]
wire [6:0] uops_0_bits_out_uop_prs1 = io_req_bits_uop_prs1_0; // @[util.scala:109:23, :688:7]
wire [6:0] uops_0_bits_out_uop_prs2 = io_req_bits_uop_prs2_0; // @[util.scala:109:23, :688:7]
wire [6:0] uops_0_bits_out_uop_prs3 = io_req_bits_uop_prs3_0; // @[util.scala:109:23, :688:7]
wire [4:0] uops_0_bits_out_uop_ppred = io_req_bits_uop_ppred_0; // @[util.scala:109:23, :688:7]
wire uops_0_bits_out_uop_prs1_busy = io_req_bits_uop_prs1_busy_0; // @[util.scala:109:23, :688:7]
wire uops_0_bits_out_uop_prs2_busy = io_req_bits_uop_prs2_busy_0; // @[util.scala:109:23, :688:7]
wire uops_0_bits_out_uop_prs3_busy = io_req_bits_uop_prs3_busy_0; // @[util.scala:109:23, :688:7]
wire uops_0_bits_out_uop_ppred_busy = io_req_bits_uop_ppred_busy_0; // @[util.scala:109:23, :688:7]
wire [6:0] uops_0_bits_out_uop_stale_pdst = io_req_bits_uop_stale_pdst_0; // @[util.scala:109:23, :688:7]
wire uops_0_bits_out_uop_exception = io_req_bits_uop_exception_0; // @[util.scala:109:23, :688:7]
wire [63:0] uops_0_bits_out_uop_exc_cause = io_req_bits_uop_exc_cause_0; // @[util.scala:109:23, :688:7]
wire [4:0] uops_0_bits_out_uop_mem_cmd = io_req_bits_uop_mem_cmd_0; // @[util.scala:109:23, :688:7]
wire [1:0] uops_0_bits_out_uop_mem_size = io_req_bits_uop_mem_size_0; // @[util.scala:109:23, :688:7]
wire uops_0_bits_out_uop_mem_signed = io_req_bits_uop_mem_signed_0; // @[util.scala:109:23, :688:7]
wire uops_0_bits_out_uop_uses_ldq = io_req_bits_uop_uses_ldq_0; // @[util.scala:109:23, :688:7]
wire uops_0_bits_out_uop_uses_stq = io_req_bits_uop_uses_stq_0; // @[util.scala:109:23, :688:7]
wire uops_0_bits_out_uop_is_unique = io_req_bits_uop_is_unique_0; // @[util.scala:109:23, :688:7]
wire uops_0_bits_out_uop_flush_on_commit = io_req_bits_uop_flush_on_commit_0; // @[util.scala:109:23, :688:7]
wire [2:0] uops_0_bits_out_uop_csr_cmd = io_req_bits_uop_csr_cmd_0; // @[util.scala:109:23, :688:7]
wire uops_0_bits_out_uop_ldst_is_rs1 = io_req_bits_uop_ldst_is_rs1_0; // @[util.scala:109:23, :688:7]
wire [5:0] uops_0_bits_out_uop_ldst = io_req_bits_uop_ldst_0; // @[util.scala:109:23, :688:7]
wire [5:0] uops_0_bits_out_uop_lrs1 = io_req_bits_uop_lrs1_0; // @[util.scala:109:23, :688:7]
wire [5:0] uops_0_bits_out_uop_lrs2 = io_req_bits_uop_lrs2_0; // @[util.scala:109:23, :688:7]
wire [5:0] uops_0_bits_out_uop_lrs3 = io_req_bits_uop_lrs3_0; // @[util.scala:109:23, :688:7]
wire [1:0] uops_0_bits_out_uop_dst_rtype = io_req_bits_uop_dst_rtype_0; // @[util.scala:109:23, :688:7]
wire [1:0] uops_0_bits_out_uop_lrs1_rtype = io_req_bits_uop_lrs1_rtype_0; // @[util.scala:109:23, :688:7]
wire [1:0] uops_0_bits_out_uop_lrs2_rtype = io_req_bits_uop_lrs2_rtype_0; // @[util.scala:109:23, :688:7]
wire uops_0_bits_out_uop_frs3_en = io_req_bits_uop_frs3_en_0; // @[util.scala:109:23, :688:7]
wire uops_0_bits_out_uop_fcn_dw = io_req_bits_uop_fcn_dw_0; // @[util.scala:109:23, :688:7]
wire [4:0] uops_0_bits_out_uop_fcn_op = io_req_bits_uop_fcn_op_0; // @[util.scala:109:23, :688:7]
wire uops_0_bits_out_uop_fp_val = io_req_bits_uop_fp_val_0; // @[util.scala:109:23, :688:7]
wire [2:0] uops_0_bits_out_uop_fp_rm = io_req_bits_uop_fp_rm_0; // @[util.scala:109:23, :688:7]
wire [1:0] uops_0_bits_out_uop_fp_typ = io_req_bits_uop_fp_typ_0; // @[util.scala:109:23, :688:7]
wire uops_0_bits_out_uop_xcpt_pf_if = io_req_bits_uop_xcpt_pf_if_0; // @[util.scala:109:23, :688:7]
wire uops_0_bits_out_uop_xcpt_ae_if = io_req_bits_uop_xcpt_ae_if_0; // @[util.scala:109:23, :688:7]
wire uops_0_bits_out_uop_xcpt_ma_if = io_req_bits_uop_xcpt_ma_if_0; // @[util.scala:109:23, :688:7]
wire uops_0_bits_out_uop_bp_debug_if = io_req_bits_uop_bp_debug_if_0; // @[util.scala:109:23, :688:7]
wire uops_0_bits_out_uop_bp_xcpt_if = io_req_bits_uop_bp_xcpt_if_0; // @[util.scala:109:23, :688:7]
wire [2:0] uops_0_bits_out_uop_debug_fsrc = io_req_bits_uop_debug_fsrc_0; // @[util.scala:109:23, :688:7]
wire [2:0] uops_0_bits_out_uop_debug_tsrc = io_req_bits_uop_debug_tsrc_0; // @[util.scala:109:23, :688:7]
wire [63:0] uops_0_bits_out_rs1_data = io_req_bits_rs1_data_0; // @[util.scala:109:23, :688:7]
wire [63:0] uops_0_bits_out_rs2_data = io_req_bits_rs2_data_0; // @[util.scala:109:23, :688:7]
wire [63:0] uops_0_bits_out_imm_data = io_req_bits_imm_data_0; // @[util.scala:109:23, :688:7]
wire io_resp_0_bits_uop_iq_type_0; // @[util.scala:688:7]
wire io_resp_0_bits_uop_iq_type_1; // @[util.scala:688:7]
wire io_resp_0_bits_uop_iq_type_2; // @[util.scala:688:7]
wire io_resp_0_bits_uop_iq_type_3; // @[util.scala:688:7]
wire io_resp_0_bits_uop_fu_code_0; // @[util.scala:688:7]
wire io_resp_0_bits_uop_fu_code_1; // @[util.scala:688:7]
wire io_resp_0_bits_uop_fu_code_2; // @[util.scala:688:7]
wire io_resp_0_bits_uop_fu_code_3; // @[util.scala:688:7]
wire io_resp_0_bits_uop_fu_code_4; // @[util.scala:688:7]
wire io_resp_0_bits_uop_fu_code_5; // @[util.scala:688:7]
wire io_resp_0_bits_uop_fu_code_6; // @[util.scala:688:7]
wire io_resp_0_bits_uop_fu_code_7; // @[util.scala:688:7]
wire io_resp_0_bits_uop_fu_code_8; // @[util.scala:688:7]
wire io_resp_0_bits_uop_fu_code_9; // @[util.scala:688:7]
wire io_resp_0_bits_uop_fp_ctrl_ldst; // @[util.scala:688:7]
wire io_resp_0_bits_uop_fp_ctrl_wen; // @[util.scala:688:7]
wire io_resp_0_bits_uop_fp_ctrl_ren1; // @[util.scala:688:7]
wire io_resp_0_bits_uop_fp_ctrl_ren2; // @[util.scala:688:7]
wire io_resp_0_bits_uop_fp_ctrl_ren3; // @[util.scala:688:7]
wire io_resp_0_bits_uop_fp_ctrl_swap12; // @[util.scala:688:7]
wire io_resp_0_bits_uop_fp_ctrl_swap23; // @[util.scala:688:7]
wire [1:0] io_resp_0_bits_uop_fp_ctrl_typeTagIn; // @[util.scala:688:7]
wire [1:0] io_resp_0_bits_uop_fp_ctrl_typeTagOut; // @[util.scala:688:7]
wire io_resp_0_bits_uop_fp_ctrl_fromint; // @[util.scala:688:7]
wire io_resp_0_bits_uop_fp_ctrl_toint; // @[util.scala:688:7]
wire io_resp_0_bits_uop_fp_ctrl_fastpipe; // @[util.scala:688:7]
wire io_resp_0_bits_uop_fp_ctrl_fma; // @[util.scala:688:7]
wire io_resp_0_bits_uop_fp_ctrl_div; // @[util.scala:688:7]
wire io_resp_0_bits_uop_fp_ctrl_sqrt; // @[util.scala:688:7]
wire io_resp_0_bits_uop_fp_ctrl_wflags; // @[util.scala:688:7]
wire io_resp_0_bits_uop_fp_ctrl_vec; // @[util.scala:688:7]
wire [31:0] io_resp_0_bits_uop_inst; // @[util.scala:688:7]
wire [31:0] io_resp_0_bits_uop_debug_inst; // @[util.scala:688:7]
wire io_resp_0_bits_uop_is_rvc; // @[util.scala:688:7]
wire [39:0] io_resp_0_bits_uop_debug_pc; // @[util.scala:688:7]
wire io_resp_0_bits_uop_iw_issued; // @[util.scala:688:7]
wire io_resp_0_bits_uop_iw_issued_partial_agen; // @[util.scala:688:7]
wire io_resp_0_bits_uop_iw_issued_partial_dgen; // @[util.scala:688:7]
wire [2:0] io_resp_0_bits_uop_iw_p1_speculative_child; // @[util.scala:688:7]
wire [2:0] io_resp_0_bits_uop_iw_p2_speculative_child; // @[util.scala:688:7]
wire io_resp_0_bits_uop_iw_p1_bypass_hint; // @[util.scala:688:7]
wire io_resp_0_bits_uop_iw_p2_bypass_hint; // @[util.scala:688:7]
wire io_resp_0_bits_uop_iw_p3_bypass_hint; // @[util.scala:688:7]
wire [2:0] io_resp_0_bits_uop_dis_col_sel; // @[util.scala:688:7]
wire [15:0] io_resp_0_bits_uop_br_mask; // @[util.scala:688:7]
wire [3:0] io_resp_0_bits_uop_br_tag; // @[util.scala:688:7]
wire [3:0] io_resp_0_bits_uop_br_type; // @[util.scala:688:7]
wire io_resp_0_bits_uop_is_sfb; // @[util.scala:688:7]
wire io_resp_0_bits_uop_is_fence; // @[util.scala:688:7]
wire io_resp_0_bits_uop_is_fencei; // @[util.scala:688:7]
wire io_resp_0_bits_uop_is_sfence; // @[util.scala:688:7]
wire io_resp_0_bits_uop_is_amo; // @[util.scala:688:7]
wire io_resp_0_bits_uop_is_eret; // @[util.scala:688:7]
wire io_resp_0_bits_uop_is_sys_pc2epc; // @[util.scala:688:7]
wire io_resp_0_bits_uop_is_rocc; // @[util.scala:688:7]
wire io_resp_0_bits_uop_is_mov; // @[util.scala:688:7]
wire [4:0] io_resp_0_bits_uop_ftq_idx; // @[util.scala:688:7]
wire io_resp_0_bits_uop_edge_inst; // @[util.scala:688:7]
wire [5:0] io_resp_0_bits_uop_pc_lob; // @[util.scala:688:7]
wire io_resp_0_bits_uop_taken; // @[util.scala:688:7]
wire io_resp_0_bits_uop_imm_rename; // @[util.scala:688:7]
wire [2:0] io_resp_0_bits_uop_imm_sel; // @[util.scala:688:7]
wire [4:0] io_resp_0_bits_uop_pimm; // @[util.scala:688:7]
wire [19:0] io_resp_0_bits_uop_imm_packed; // @[util.scala:688:7]
wire [1:0] io_resp_0_bits_uop_op1_sel; // @[util.scala:688:7]
wire [2:0] io_resp_0_bits_uop_op2_sel; // @[util.scala:688:7]
wire [6:0] io_resp_0_bits_uop_rob_idx; // @[util.scala:688:7]
wire [4:0] io_resp_0_bits_uop_ldq_idx; // @[util.scala:688:7]
wire [4:0] io_resp_0_bits_uop_stq_idx; // @[util.scala:688:7]
wire [1:0] io_resp_0_bits_uop_rxq_idx; // @[util.scala:688:7]
wire [6:0] io_resp_0_bits_uop_pdst; // @[util.scala:688:7]
wire [6:0] io_resp_0_bits_uop_prs1; // @[util.scala:688:7]
wire [6:0] io_resp_0_bits_uop_prs2; // @[util.scala:688:7]
wire [6:0] io_resp_0_bits_uop_prs3; // @[util.scala:688:7]
wire [4:0] io_resp_0_bits_uop_ppred; // @[util.scala:688:7]
wire io_resp_0_bits_uop_prs1_busy; // @[util.scala:688:7]
wire io_resp_0_bits_uop_prs2_busy; // @[util.scala:688:7]
wire io_resp_0_bits_uop_prs3_busy; // @[util.scala:688:7]
wire io_resp_0_bits_uop_ppred_busy; // @[util.scala:688:7]
wire [6:0] io_resp_0_bits_uop_stale_pdst; // @[util.scala:688:7]
wire io_resp_0_bits_uop_exception; // @[util.scala:688:7]
wire [63:0] io_resp_0_bits_uop_exc_cause; // @[util.scala:688:7]
wire [4:0] io_resp_0_bits_uop_mem_cmd; // @[util.scala:688:7]
wire [1:0] io_resp_0_bits_uop_mem_size; // @[util.scala:688:7]
wire io_resp_0_bits_uop_mem_signed; // @[util.scala:688:7]
wire io_resp_0_bits_uop_uses_ldq; // @[util.scala:688:7]
wire io_resp_0_bits_uop_uses_stq; // @[util.scala:688:7]
wire io_resp_0_bits_uop_is_unique; // @[util.scala:688:7]
wire io_resp_0_bits_uop_flush_on_commit; // @[util.scala:688:7]
wire [2:0] io_resp_0_bits_uop_csr_cmd; // @[util.scala:688:7]
wire io_resp_0_bits_uop_ldst_is_rs1; // @[util.scala:688:7]
wire [5:0] io_resp_0_bits_uop_ldst; // @[util.scala:688:7]
wire [5:0] io_resp_0_bits_uop_lrs1; // @[util.scala:688:7]
wire [5:0] io_resp_0_bits_uop_lrs2; // @[util.scala:688:7]
wire [5:0] io_resp_0_bits_uop_lrs3; // @[util.scala:688:7]
wire [1:0] io_resp_0_bits_uop_dst_rtype; // @[util.scala:688:7]
wire [1:0] io_resp_0_bits_uop_lrs1_rtype; // @[util.scala:688:7]
wire [1:0] io_resp_0_bits_uop_lrs2_rtype; // @[util.scala:688:7]
wire io_resp_0_bits_uop_frs3_en; // @[util.scala:688:7]
wire io_resp_0_bits_uop_fcn_dw; // @[util.scala:688:7]
wire [4:0] io_resp_0_bits_uop_fcn_op; // @[util.scala:688:7]
wire io_resp_0_bits_uop_fp_val; // @[util.scala:688:7]
wire [2:0] io_resp_0_bits_uop_fp_rm; // @[util.scala:688:7]
wire [1:0] io_resp_0_bits_uop_fp_typ; // @[util.scala:688:7]
wire io_resp_0_bits_uop_xcpt_pf_if; // @[util.scala:688:7]
wire io_resp_0_bits_uop_xcpt_ae_if; // @[util.scala:688:7]
wire io_resp_0_bits_uop_xcpt_ma_if; // @[util.scala:688:7]
wire io_resp_0_bits_uop_bp_debug_if; // @[util.scala:688:7]
wire io_resp_0_bits_uop_bp_xcpt_if; // @[util.scala:688:7]
wire [2:0] io_resp_0_bits_uop_debug_fsrc; // @[util.scala:688:7]
wire [2:0] io_resp_0_bits_uop_debug_tsrc; // @[util.scala:688:7]
wire [63:0] io_resp_0_bits_rs1_data; // @[util.scala:688:7]
wire [63:0] io_resp_0_bits_rs2_data; // @[util.scala:688:7]
wire [63:0] io_resp_0_bits_imm_data; // @[util.scala:688:7]
wire io_resp_0_valid; // @[util.scala:688:7]
wire io_resp_1_bits_uop_iq_type_0; // @[util.scala:688:7]
wire io_resp_1_bits_uop_iq_type_1; // @[util.scala:688:7]
wire io_resp_1_bits_uop_iq_type_2; // @[util.scala:688:7]
wire io_resp_1_bits_uop_iq_type_3; // @[util.scala:688:7]
wire io_resp_1_bits_uop_fu_code_0; // @[util.scala:688:7]
wire io_resp_1_bits_uop_fu_code_1; // @[util.scala:688:7]
wire io_resp_1_bits_uop_fu_code_2; // @[util.scala:688:7]
wire io_resp_1_bits_uop_fu_code_3; // @[util.scala:688:7]
wire io_resp_1_bits_uop_fu_code_4; // @[util.scala:688:7]
wire io_resp_1_bits_uop_fu_code_5; // @[util.scala:688:7]
wire io_resp_1_bits_uop_fu_code_6; // @[util.scala:688:7]
wire io_resp_1_bits_uop_fu_code_7; // @[util.scala:688:7]
wire io_resp_1_bits_uop_fu_code_8; // @[util.scala:688:7]
wire io_resp_1_bits_uop_fu_code_9; // @[util.scala:688:7]
wire io_resp_1_bits_uop_fp_ctrl_ldst; // @[util.scala:688:7]
wire io_resp_1_bits_uop_fp_ctrl_wen; // @[util.scala:688:7]
wire io_resp_1_bits_uop_fp_ctrl_ren1; // @[util.scala:688:7]
wire io_resp_1_bits_uop_fp_ctrl_ren2; // @[util.scala:688:7]
wire io_resp_1_bits_uop_fp_ctrl_ren3; // @[util.scala:688:7]
wire io_resp_1_bits_uop_fp_ctrl_swap12; // @[util.scala:688:7]
wire io_resp_1_bits_uop_fp_ctrl_swap23; // @[util.scala:688:7]
wire [1:0] io_resp_1_bits_uop_fp_ctrl_typeTagIn; // @[util.scala:688:7]
wire [1:0] io_resp_1_bits_uop_fp_ctrl_typeTagOut; // @[util.scala:688:7]
wire io_resp_1_bits_uop_fp_ctrl_fromint; // @[util.scala:688:7]
wire io_resp_1_bits_uop_fp_ctrl_toint; // @[util.scala:688:7]
wire io_resp_1_bits_uop_fp_ctrl_fastpipe; // @[util.scala:688:7]
wire io_resp_1_bits_uop_fp_ctrl_fma; // @[util.scala:688:7]
wire io_resp_1_bits_uop_fp_ctrl_div; // @[util.scala:688:7]
wire io_resp_1_bits_uop_fp_ctrl_sqrt; // @[util.scala:688:7]
wire io_resp_1_bits_uop_fp_ctrl_wflags; // @[util.scala:688:7]
wire io_resp_1_bits_uop_fp_ctrl_vec; // @[util.scala:688:7]
wire [31:0] io_resp_1_bits_uop_inst; // @[util.scala:688:7]
wire [31:0] io_resp_1_bits_uop_debug_inst; // @[util.scala:688:7]
wire io_resp_1_bits_uop_is_rvc; // @[util.scala:688:7]
wire [39:0] io_resp_1_bits_uop_debug_pc; // @[util.scala:688:7]
wire io_resp_1_bits_uop_iw_issued; // @[util.scala:688:7]
wire io_resp_1_bits_uop_iw_issued_partial_agen; // @[util.scala:688:7]
wire io_resp_1_bits_uop_iw_issued_partial_dgen; // @[util.scala:688:7]
wire [2:0] io_resp_1_bits_uop_iw_p1_speculative_child; // @[util.scala:688:7]
wire [2:0] io_resp_1_bits_uop_iw_p2_speculative_child; // @[util.scala:688:7]
wire io_resp_1_bits_uop_iw_p1_bypass_hint; // @[util.scala:688:7]
wire io_resp_1_bits_uop_iw_p2_bypass_hint; // @[util.scala:688:7]
wire io_resp_1_bits_uop_iw_p3_bypass_hint; // @[util.scala:688:7]
wire [2:0] io_resp_1_bits_uop_dis_col_sel; // @[util.scala:688:7]
wire [15:0] io_resp_1_bits_uop_br_mask; // @[util.scala:688:7]
wire [3:0] io_resp_1_bits_uop_br_tag; // @[util.scala:688:7]
wire [3:0] io_resp_1_bits_uop_br_type; // @[util.scala:688:7]
wire io_resp_1_bits_uop_is_sfb; // @[util.scala:688:7]
wire io_resp_1_bits_uop_is_fence; // @[util.scala:688:7]
wire io_resp_1_bits_uop_is_fencei; // @[util.scala:688:7]
wire io_resp_1_bits_uop_is_sfence; // @[util.scala:688:7]
wire io_resp_1_bits_uop_is_amo; // @[util.scala:688:7]
wire io_resp_1_bits_uop_is_eret; // @[util.scala:688:7]
wire io_resp_1_bits_uop_is_sys_pc2epc; // @[util.scala:688:7]
wire io_resp_1_bits_uop_is_rocc; // @[util.scala:688:7]
wire io_resp_1_bits_uop_is_mov; // @[util.scala:688:7]
wire [4:0] io_resp_1_bits_uop_ftq_idx; // @[util.scala:688:7]
wire io_resp_1_bits_uop_edge_inst; // @[util.scala:688:7]
wire [5:0] io_resp_1_bits_uop_pc_lob; // @[util.scala:688:7]
wire io_resp_1_bits_uop_taken; // @[util.scala:688:7]
wire io_resp_1_bits_uop_imm_rename; // @[util.scala:688:7]
wire [2:0] io_resp_1_bits_uop_imm_sel; // @[util.scala:688:7]
wire [4:0] io_resp_1_bits_uop_pimm; // @[util.scala:688:7]
wire [19:0] io_resp_1_bits_uop_imm_packed; // @[util.scala:688:7]
wire [1:0] io_resp_1_bits_uop_op1_sel; // @[util.scala:688:7]
wire [2:0] io_resp_1_bits_uop_op2_sel; // @[util.scala:688:7]
wire [6:0] io_resp_1_bits_uop_rob_idx; // @[util.scala:688:7]
wire [4:0] io_resp_1_bits_uop_ldq_idx; // @[util.scala:688:7]
wire [4:0] io_resp_1_bits_uop_stq_idx; // @[util.scala:688:7]
wire [1:0] io_resp_1_bits_uop_rxq_idx; // @[util.scala:688:7]
wire [6:0] io_resp_1_bits_uop_pdst; // @[util.scala:688:7]
wire [6:0] io_resp_1_bits_uop_prs1; // @[util.scala:688:7]
wire [6:0] io_resp_1_bits_uop_prs2; // @[util.scala:688:7]
wire [6:0] io_resp_1_bits_uop_prs3; // @[util.scala:688:7]
wire [4:0] io_resp_1_bits_uop_ppred; // @[util.scala:688:7]
wire io_resp_1_bits_uop_prs1_busy; // @[util.scala:688:7]
wire io_resp_1_bits_uop_prs2_busy; // @[util.scala:688:7]
wire io_resp_1_bits_uop_prs3_busy; // @[util.scala:688:7]
wire io_resp_1_bits_uop_ppred_busy; // @[util.scala:688:7]
wire [6:0] io_resp_1_bits_uop_stale_pdst; // @[util.scala:688:7]
wire io_resp_1_bits_uop_exception; // @[util.scala:688:7]
wire [63:0] io_resp_1_bits_uop_exc_cause; // @[util.scala:688:7]
wire [4:0] io_resp_1_bits_uop_mem_cmd; // @[util.scala:688:7]
wire [1:0] io_resp_1_bits_uop_mem_size; // @[util.scala:688:7]
wire io_resp_1_bits_uop_mem_signed; // @[util.scala:688:7]
wire io_resp_1_bits_uop_uses_ldq; // @[util.scala:688:7]
wire io_resp_1_bits_uop_uses_stq; // @[util.scala:688:7]
wire io_resp_1_bits_uop_is_unique; // @[util.scala:688:7]
wire io_resp_1_bits_uop_flush_on_commit; // @[util.scala:688:7]
wire [2:0] io_resp_1_bits_uop_csr_cmd; // @[util.scala:688:7]
wire io_resp_1_bits_uop_ldst_is_rs1; // @[util.scala:688:7]
wire [5:0] io_resp_1_bits_uop_ldst; // @[util.scala:688:7]
wire [5:0] io_resp_1_bits_uop_lrs1; // @[util.scala:688:7]
wire [5:0] io_resp_1_bits_uop_lrs2; // @[util.scala:688:7]
wire [5:0] io_resp_1_bits_uop_lrs3; // @[util.scala:688:7]
wire [1:0] io_resp_1_bits_uop_dst_rtype; // @[util.scala:688:7]
wire [1:0] io_resp_1_bits_uop_lrs1_rtype; // @[util.scala:688:7]
wire [1:0] io_resp_1_bits_uop_lrs2_rtype; // @[util.scala:688:7]
wire io_resp_1_bits_uop_frs3_en; // @[util.scala:688:7]
wire io_resp_1_bits_uop_fcn_dw; // @[util.scala:688:7]
wire [4:0] io_resp_1_bits_uop_fcn_op; // @[util.scala:688:7]
wire io_resp_1_bits_uop_fp_val; // @[util.scala:688:7]
wire [2:0] io_resp_1_bits_uop_fp_rm; // @[util.scala:688:7]
wire [1:0] io_resp_1_bits_uop_fp_typ; // @[util.scala:688:7]
wire io_resp_1_bits_uop_xcpt_pf_if; // @[util.scala:688:7]
wire io_resp_1_bits_uop_xcpt_ae_if; // @[util.scala:688:7]
wire io_resp_1_bits_uop_xcpt_ma_if; // @[util.scala:688:7]
wire io_resp_1_bits_uop_bp_debug_if; // @[util.scala:688:7]
wire io_resp_1_bits_uop_bp_xcpt_if; // @[util.scala:688:7]
wire [2:0] io_resp_1_bits_uop_debug_fsrc; // @[util.scala:688:7]
wire [2:0] io_resp_1_bits_uop_debug_tsrc; // @[util.scala:688:7]
wire io_resp_1_bits_ftq_info_0_entry_cfi_idx_valid; // @[util.scala:688:7]
wire [2:0] io_resp_1_bits_ftq_info_0_entry_cfi_idx_bits; // @[util.scala:688:7]
wire io_resp_1_bits_ftq_info_0_entry_cfi_taken; // @[util.scala:688:7]
wire io_resp_1_bits_ftq_info_0_entry_cfi_mispredicted; // @[util.scala:688:7]
wire [2:0] io_resp_1_bits_ftq_info_0_entry_cfi_type; // @[util.scala:688:7]
wire [7:0] io_resp_1_bits_ftq_info_0_entry_br_mask; // @[util.scala:688:7]
wire io_resp_1_bits_ftq_info_0_entry_cfi_is_call; // @[util.scala:688:7]
wire io_resp_1_bits_ftq_info_0_entry_cfi_is_ret; // @[util.scala:688:7]
wire io_resp_1_bits_ftq_info_0_entry_cfi_npc_plus4; // @[util.scala:688:7]
wire [39:0] io_resp_1_bits_ftq_info_0_entry_ras_top; // @[util.scala:688:7]
wire [4:0] io_resp_1_bits_ftq_info_0_entry_ras_idx; // @[util.scala:688:7]
wire io_resp_1_bits_ftq_info_0_entry_start_bank; // @[util.scala:688:7]
wire [63:0] io_resp_1_bits_ftq_info_0_ghist_old_history; // @[util.scala:688:7]
wire io_resp_1_bits_ftq_info_0_ghist_current_saw_branch_not_taken; // @[util.scala:688:7]
wire io_resp_1_bits_ftq_info_0_ghist_new_saw_branch_not_taken; // @[util.scala:688:7]
wire io_resp_1_bits_ftq_info_0_ghist_new_saw_branch_taken; // @[util.scala:688:7]
wire [4:0] io_resp_1_bits_ftq_info_0_ghist_ras_idx; // @[util.scala:688:7]
wire io_resp_1_bits_ftq_info_0_valid; // @[util.scala:688:7]
wire [39:0] io_resp_1_bits_ftq_info_0_pc; // @[util.scala:688:7]
wire io_resp_1_bits_ftq_info_1_entry_cfi_idx_valid; // @[util.scala:688:7]
wire [2:0] io_resp_1_bits_ftq_info_1_entry_cfi_idx_bits; // @[util.scala:688:7]
wire io_resp_1_bits_ftq_info_1_entry_cfi_taken; // @[util.scala:688:7]
wire io_resp_1_bits_ftq_info_1_entry_cfi_mispredicted; // @[util.scala:688:7]
wire [2:0] io_resp_1_bits_ftq_info_1_entry_cfi_type; // @[util.scala:688:7]
wire [7:0] io_resp_1_bits_ftq_info_1_entry_br_mask; // @[util.scala:688:7]
wire io_resp_1_bits_ftq_info_1_entry_cfi_is_call; // @[util.scala:688:7]
wire io_resp_1_bits_ftq_info_1_entry_cfi_is_ret; // @[util.scala:688:7]
wire io_resp_1_bits_ftq_info_1_entry_cfi_npc_plus4; // @[util.scala:688:7]
wire [39:0] io_resp_1_bits_ftq_info_1_entry_ras_top; // @[util.scala:688:7]
wire [4:0] io_resp_1_bits_ftq_info_1_entry_ras_idx; // @[util.scala:688:7]
wire io_resp_1_bits_ftq_info_1_entry_start_bank; // @[util.scala:688:7]
wire [63:0] io_resp_1_bits_ftq_info_1_ghist_old_history; // @[util.scala:688:7]
wire io_resp_1_bits_ftq_info_1_ghist_current_saw_branch_not_taken; // @[util.scala:688:7]
wire io_resp_1_bits_ftq_info_1_ghist_new_saw_branch_not_taken; // @[util.scala:688:7]
wire io_resp_1_bits_ftq_info_1_ghist_new_saw_branch_taken; // @[util.scala:688:7]
wire [4:0] io_resp_1_bits_ftq_info_1_ghist_ras_idx; // @[util.scala:688:7]
wire io_resp_1_bits_ftq_info_1_valid; // @[util.scala:688:7]
wire [39:0] io_resp_1_bits_ftq_info_1_pc; // @[util.scala:688:7]
wire [63:0] io_resp_1_bits_rs1_data; // @[util.scala:688:7]
wire [63:0] io_resp_1_bits_rs2_data; // @[util.scala:688:7]
wire [63:0] io_resp_1_bits_rs3_data; // @[util.scala:688:7]
wire io_resp_1_bits_pred_data; // @[util.scala:688:7]
wire [63:0] io_resp_1_bits_imm_data; // @[util.scala:688:7]
wire io_resp_1_valid; // @[util.scala:688:7]
wire io_resp_2_bits_uop_iq_type_0_0; // @[util.scala:688:7]
wire io_resp_2_bits_uop_iq_type_1_0; // @[util.scala:688:7]
wire io_resp_2_bits_uop_iq_type_2_0; // @[util.scala:688:7]
wire io_resp_2_bits_uop_iq_type_3_0; // @[util.scala:688:7]
wire io_resp_2_bits_uop_fu_code_0_0; // @[util.scala:688:7]
wire io_resp_2_bits_uop_fu_code_1_0; // @[util.scala:688:7]
wire io_resp_2_bits_uop_fu_code_2_0; // @[util.scala:688:7]
wire io_resp_2_bits_uop_fu_code_3_0; // @[util.scala:688:7]
wire io_resp_2_bits_uop_fu_code_4_0; // @[util.scala:688:7]
wire io_resp_2_bits_uop_fu_code_5_0; // @[util.scala:688:7]
wire io_resp_2_bits_uop_fu_code_6_0; // @[util.scala:688:7]
wire io_resp_2_bits_uop_fu_code_7_0; // @[util.scala:688:7]
wire io_resp_2_bits_uop_fu_code_8_0; // @[util.scala:688:7]
wire io_resp_2_bits_uop_fu_code_9_0; // @[util.scala:688:7]
wire io_resp_2_bits_uop_fp_ctrl_ldst_0; // @[util.scala:688:7]
wire io_resp_2_bits_uop_fp_ctrl_wen_0; // @[util.scala:688:7]
wire io_resp_2_bits_uop_fp_ctrl_ren1_0; // @[util.scala:688:7]
wire io_resp_2_bits_uop_fp_ctrl_ren2_0; // @[util.scala:688:7]
wire io_resp_2_bits_uop_fp_ctrl_ren3_0; // @[util.scala:688:7]
wire io_resp_2_bits_uop_fp_ctrl_swap12_0; // @[util.scala:688:7]
wire io_resp_2_bits_uop_fp_ctrl_swap23_0; // @[util.scala:688:7]
wire [1:0] io_resp_2_bits_uop_fp_ctrl_typeTagIn_0; // @[util.scala:688:7]
wire [1:0] io_resp_2_bits_uop_fp_ctrl_typeTagOut_0; // @[util.scala:688:7]
wire io_resp_2_bits_uop_fp_ctrl_fromint_0; // @[util.scala:688:7]
wire io_resp_2_bits_uop_fp_ctrl_toint_0; // @[util.scala:688:7]
wire io_resp_2_bits_uop_fp_ctrl_fastpipe_0; // @[util.scala:688:7]
wire io_resp_2_bits_uop_fp_ctrl_fma_0; // @[util.scala:688:7]
wire io_resp_2_bits_uop_fp_ctrl_div_0; // @[util.scala:688:7]
wire io_resp_2_bits_uop_fp_ctrl_sqrt_0; // @[util.scala:688:7]
wire io_resp_2_bits_uop_fp_ctrl_wflags_0; // @[util.scala:688:7]
wire io_resp_2_bits_uop_fp_ctrl_vec_0; // @[util.scala:688:7]
wire [31:0] io_resp_2_bits_uop_inst_0; // @[util.scala:688:7]
wire [31:0] io_resp_2_bits_uop_debug_inst_0; // @[util.scala:688:7]
wire io_resp_2_bits_uop_is_rvc_0; // @[util.scala:688:7]
wire [39:0] io_resp_2_bits_uop_debug_pc_0; // @[util.scala:688:7]
wire io_resp_2_bits_uop_iw_issued_0; // @[util.scala:688:7]
wire io_resp_2_bits_uop_iw_issued_partial_agen_0; // @[util.scala:688:7]
wire io_resp_2_bits_uop_iw_issued_partial_dgen_0; // @[util.scala:688:7]
wire [2:0] io_resp_2_bits_uop_iw_p1_speculative_child_0; // @[util.scala:688:7]
wire [2:0] io_resp_2_bits_uop_iw_p2_speculative_child_0; // @[util.scala:688:7]
wire io_resp_2_bits_uop_iw_p1_bypass_hint_0; // @[util.scala:688:7]
wire io_resp_2_bits_uop_iw_p2_bypass_hint_0; // @[util.scala:688:7]
wire io_resp_2_bits_uop_iw_p3_bypass_hint_0; // @[util.scala:688:7]
wire [2:0] io_resp_2_bits_uop_dis_col_sel_0; // @[util.scala:688:7]
wire [15:0] io_resp_2_bits_uop_br_mask_0; // @[util.scala:688:7]
wire [3:0] io_resp_2_bits_uop_br_tag_0; // @[util.scala:688:7]
wire [3:0] io_resp_2_bits_uop_br_type_0; // @[util.scala:688:7]
wire io_resp_2_bits_uop_is_sfb_0; // @[util.scala:688:7]
wire io_resp_2_bits_uop_is_fence_0; // @[util.scala:688:7]
wire io_resp_2_bits_uop_is_fencei_0; // @[util.scala:688:7]
wire io_resp_2_bits_uop_is_sfence_0; // @[util.scala:688:7]
wire io_resp_2_bits_uop_is_amo_0; // @[util.scala:688:7]
wire io_resp_2_bits_uop_is_eret_0; // @[util.scala:688:7]
wire io_resp_2_bits_uop_is_sys_pc2epc_0; // @[util.scala:688:7]
wire io_resp_2_bits_uop_is_rocc_0; // @[util.scala:688:7]
wire io_resp_2_bits_uop_is_mov_0; // @[util.scala:688:7]
wire [4:0] io_resp_2_bits_uop_ftq_idx_0; // @[util.scala:688:7]
wire io_resp_2_bits_uop_edge_inst_0; // @[util.scala:688:7]
wire [5:0] io_resp_2_bits_uop_pc_lob_0; // @[util.scala:688:7]
wire io_resp_2_bits_uop_taken_0; // @[util.scala:688:7]
wire io_resp_2_bits_uop_imm_rename_0; // @[util.scala:688:7]
wire [2:0] io_resp_2_bits_uop_imm_sel_0; // @[util.scala:688:7]
wire [4:0] io_resp_2_bits_uop_pimm_0; // @[util.scala:688:7]
wire [19:0] io_resp_2_bits_uop_imm_packed_0; // @[util.scala:688:7]
wire [1:0] io_resp_2_bits_uop_op1_sel_0; // @[util.scala:688:7]
wire [2:0] io_resp_2_bits_uop_op2_sel_0; // @[util.scala:688:7]
wire [6:0] io_resp_2_bits_uop_rob_idx_0; // @[util.scala:688:7]
wire [4:0] io_resp_2_bits_uop_ldq_idx_0; // @[util.scala:688:7]
wire [4:0] io_resp_2_bits_uop_stq_idx_0; // @[util.scala:688:7]
wire [1:0] io_resp_2_bits_uop_rxq_idx_0; // @[util.scala:688:7]
wire [6:0] io_resp_2_bits_uop_pdst_0; // @[util.scala:688:7]
wire [6:0] io_resp_2_bits_uop_prs1_0; // @[util.scala:688:7]
wire [6:0] io_resp_2_bits_uop_prs2_0; // @[util.scala:688:7]
wire [6:0] io_resp_2_bits_uop_prs3_0; // @[util.scala:688:7]
wire [4:0] io_resp_2_bits_uop_ppred_0; // @[util.scala:688:7]
wire io_resp_2_bits_uop_prs1_busy_0; // @[util.scala:688:7]
wire io_resp_2_bits_uop_prs2_busy_0; // @[util.scala:688:7]
wire io_resp_2_bits_uop_prs3_busy_0; // @[util.scala:688:7]
wire io_resp_2_bits_uop_ppred_busy_0; // @[util.scala:688:7]
wire [6:0] io_resp_2_bits_uop_stale_pdst_0; // @[util.scala:688:7]
wire io_resp_2_bits_uop_exception_0; // @[util.scala:688:7]
wire [63:0] io_resp_2_bits_uop_exc_cause_0; // @[util.scala:688:7]
wire [4:0] io_resp_2_bits_uop_mem_cmd_0; // @[util.scala:688:7]
wire [1:0] io_resp_2_bits_uop_mem_size_0; // @[util.scala:688:7]
wire io_resp_2_bits_uop_mem_signed_0; // @[util.scala:688:7]
wire io_resp_2_bits_uop_uses_ldq_0; // @[util.scala:688:7]
wire io_resp_2_bits_uop_uses_stq_0; // @[util.scala:688:7]
wire io_resp_2_bits_uop_is_unique_0; // @[util.scala:688:7]
wire io_resp_2_bits_uop_flush_on_commit_0; // @[util.scala:688:7]
wire [2:0] io_resp_2_bits_uop_csr_cmd_0; // @[util.scala:688:7]
wire io_resp_2_bits_uop_ldst_is_rs1_0; // @[util.scala:688:7]
wire [5:0] io_resp_2_bits_uop_ldst_0; // @[util.scala:688:7]
wire [5:0] io_resp_2_bits_uop_lrs1_0; // @[util.scala:688:7]
wire [5:0] io_resp_2_bits_uop_lrs2_0; // @[util.scala:688:7]
wire [5:0] io_resp_2_bits_uop_lrs3_0; // @[util.scala:688:7]
wire [1:0] io_resp_2_bits_uop_dst_rtype_0; // @[util.scala:688:7]
wire [1:0] io_resp_2_bits_uop_lrs1_rtype_0; // @[util.scala:688:7]
wire [1:0] io_resp_2_bits_uop_lrs2_rtype_0; // @[util.scala:688:7]
wire io_resp_2_bits_uop_frs3_en_0; // @[util.scala:688:7]
wire io_resp_2_bits_uop_fcn_dw_0; // @[util.scala:688:7]
wire [4:0] io_resp_2_bits_uop_fcn_op_0; // @[util.scala:688:7]
wire io_resp_2_bits_uop_fp_val_0; // @[util.scala:688:7]
wire [2:0] io_resp_2_bits_uop_fp_rm_0; // @[util.scala:688:7]
wire [1:0] io_resp_2_bits_uop_fp_typ_0; // @[util.scala:688:7]
wire io_resp_2_bits_uop_xcpt_pf_if_0; // @[util.scala:688:7]
wire io_resp_2_bits_uop_xcpt_ae_if_0; // @[util.scala:688:7]
wire io_resp_2_bits_uop_xcpt_ma_if_0; // @[util.scala:688:7]
wire io_resp_2_bits_uop_bp_debug_if_0; // @[util.scala:688:7]
wire io_resp_2_bits_uop_bp_xcpt_if_0; // @[util.scala:688:7]
wire [2:0] io_resp_2_bits_uop_debug_fsrc_0; // @[util.scala:688:7]
wire [2:0] io_resp_2_bits_uop_debug_tsrc_0; // @[util.scala:688:7]
wire io_resp_2_bits_ftq_info_0_entry_cfi_idx_valid; // @[util.scala:688:7]
wire [2:0] io_resp_2_bits_ftq_info_0_entry_cfi_idx_bits; // @[util.scala:688:7]
wire io_resp_2_bits_ftq_info_0_entry_cfi_taken; // @[util.scala:688:7]
wire io_resp_2_bits_ftq_info_0_entry_cfi_mispredicted; // @[util.scala:688:7]
wire [2:0] io_resp_2_bits_ftq_info_0_entry_cfi_type; // @[util.scala:688:7]
wire [7:0] io_resp_2_bits_ftq_info_0_entry_br_mask; // @[util.scala:688:7]
wire io_resp_2_bits_ftq_info_0_entry_cfi_is_call; // @[util.scala:688:7]
wire io_resp_2_bits_ftq_info_0_entry_cfi_is_ret; // @[util.scala:688:7]
wire io_resp_2_bits_ftq_info_0_entry_cfi_npc_plus4; // @[util.scala:688:7]
wire [39:0] io_resp_2_bits_ftq_info_0_entry_ras_top; // @[util.scala:688:7]
wire [4:0] io_resp_2_bits_ftq_info_0_entry_ras_idx; // @[util.scala:688:7]
wire io_resp_2_bits_ftq_info_0_entry_start_bank; // @[util.scala:688:7]
wire [63:0] io_resp_2_bits_ftq_info_0_ghist_old_history; // @[util.scala:688:7]
wire io_resp_2_bits_ftq_info_0_ghist_current_saw_branch_not_taken; // @[util.scala:688:7]
wire io_resp_2_bits_ftq_info_0_ghist_new_saw_branch_not_taken; // @[util.scala:688:7]
wire io_resp_2_bits_ftq_info_0_ghist_new_saw_branch_taken; // @[util.scala:688:7]
wire [4:0] io_resp_2_bits_ftq_info_0_ghist_ras_idx; // @[util.scala:688:7]
wire io_resp_2_bits_ftq_info_0_valid; // @[util.scala:688:7]
wire [39:0] io_resp_2_bits_ftq_info_0_pc; // @[util.scala:688:7]
wire io_resp_2_bits_ftq_info_1_entry_cfi_idx_valid; // @[util.scala:688:7]
wire [2:0] io_resp_2_bits_ftq_info_1_entry_cfi_idx_bits; // @[util.scala:688:7]
wire io_resp_2_bits_ftq_info_1_entry_cfi_taken; // @[util.scala:688:7]
wire io_resp_2_bits_ftq_info_1_entry_cfi_mispredicted; // @[util.scala:688:7]
wire [2:0] io_resp_2_bits_ftq_info_1_entry_cfi_type; // @[util.scala:688:7]
wire [7:0] io_resp_2_bits_ftq_info_1_entry_br_mask; // @[util.scala:688:7]
wire io_resp_2_bits_ftq_info_1_entry_cfi_is_call; // @[util.scala:688:7]
wire io_resp_2_bits_ftq_info_1_entry_cfi_is_ret; // @[util.scala:688:7]
wire io_resp_2_bits_ftq_info_1_entry_cfi_npc_plus4; // @[util.scala:688:7]
wire [39:0] io_resp_2_bits_ftq_info_1_entry_ras_top; // @[util.scala:688:7]
wire [4:0] io_resp_2_bits_ftq_info_1_entry_ras_idx; // @[util.scala:688:7]
wire io_resp_2_bits_ftq_info_1_entry_start_bank; // @[util.scala:688:7]
wire [63:0] io_resp_2_bits_ftq_info_1_ghist_old_history; // @[util.scala:688:7]
wire io_resp_2_bits_ftq_info_1_ghist_current_saw_branch_not_taken; // @[util.scala:688:7]
wire io_resp_2_bits_ftq_info_1_ghist_new_saw_branch_not_taken; // @[util.scala:688:7]
wire io_resp_2_bits_ftq_info_1_ghist_new_saw_branch_taken; // @[util.scala:688:7]
wire [4:0] io_resp_2_bits_ftq_info_1_ghist_ras_idx; // @[util.scala:688:7]
wire io_resp_2_bits_ftq_info_1_valid; // @[util.scala:688:7]
wire [39:0] io_resp_2_bits_ftq_info_1_pc; // @[util.scala:688:7]
wire [63:0] io_resp_2_bits_rs1_data; // @[util.scala:688:7]
wire [63:0] io_resp_2_bits_rs2_data; // @[util.scala:688:7]
wire [63:0] io_resp_2_bits_rs3_data; // @[util.scala:688:7]
wire io_resp_2_bits_pred_data; // @[util.scala:688:7]
wire [63:0] io_resp_2_bits_imm_data; // @[util.scala:688:7]
wire io_resp_2_valid_0; // @[util.scala:688:7]
reg uops_0_valid; // @[util.scala:700:17]
assign io_resp_0_valid = uops_0_valid; // @[util.scala:688:7, :700:17]
reg [31:0] uops_0_bits_uop_inst; // @[util.scala:700:17]
assign io_resp_0_bits_uop_inst = uops_0_bits_uop_inst; // @[util.scala:688:7, :700:17]
wire [31:0] uops_1_bits_out_uop_inst = uops_0_bits_uop_inst; // @[util.scala:109:23, :700:17]
reg [31:0] uops_0_bits_uop_debug_inst; // @[util.scala:700:17]
assign io_resp_0_bits_uop_debug_inst = uops_0_bits_uop_debug_inst; // @[util.scala:688:7, :700:17]
wire [31:0] uops_1_bits_out_uop_debug_inst = uops_0_bits_uop_debug_inst; // @[util.scala:109:23, :700:17]
reg uops_0_bits_uop_is_rvc; // @[util.scala:700:17]
assign io_resp_0_bits_uop_is_rvc = uops_0_bits_uop_is_rvc; // @[util.scala:688:7, :700:17]
wire uops_1_bits_out_uop_is_rvc = uops_0_bits_uop_is_rvc; // @[util.scala:109:23, :700:17]
reg [39:0] uops_0_bits_uop_debug_pc; // @[util.scala:700:17]
assign io_resp_0_bits_uop_debug_pc = uops_0_bits_uop_debug_pc; // @[util.scala:688:7, :700:17]
wire [39:0] uops_1_bits_out_uop_debug_pc = uops_0_bits_uop_debug_pc; // @[util.scala:109:23, :700:17]
reg uops_0_bits_uop_iq_type_0; // @[util.scala:700:17]
assign io_resp_0_bits_uop_iq_type_0 = uops_0_bits_uop_iq_type_0; // @[util.scala:688:7, :700:17]
wire uops_1_bits_out_uop_iq_type_0 = uops_0_bits_uop_iq_type_0; // @[util.scala:109:23, :700:17]
reg uops_0_bits_uop_iq_type_1; // @[util.scala:700:17]
assign io_resp_0_bits_uop_iq_type_1 = uops_0_bits_uop_iq_type_1; // @[util.scala:688:7, :700:17]
wire uops_1_bits_out_uop_iq_type_1 = uops_0_bits_uop_iq_type_1; // @[util.scala:109:23, :700:17]
reg uops_0_bits_uop_iq_type_2; // @[util.scala:700:17]
assign io_resp_0_bits_uop_iq_type_2 = uops_0_bits_uop_iq_type_2; // @[util.scala:688:7, :700:17]
wire uops_1_bits_out_uop_iq_type_2 = uops_0_bits_uop_iq_type_2; // @[util.scala:109:23, :700:17]
reg uops_0_bits_uop_iq_type_3; // @[util.scala:700:17]
assign io_resp_0_bits_uop_iq_type_3 = uops_0_bits_uop_iq_type_3; // @[util.scala:688:7, :700:17]
wire uops_1_bits_out_uop_iq_type_3 = uops_0_bits_uop_iq_type_3; // @[util.scala:109:23, :700:17]
reg uops_0_bits_uop_fu_code_0; // @[util.scala:700:17]
assign io_resp_0_bits_uop_fu_code_0 = uops_0_bits_uop_fu_code_0; // @[util.scala:688:7, :700:17]
wire uops_1_bits_out_uop_fu_code_0 = uops_0_bits_uop_fu_code_0; // @[util.scala:109:23, :700:17]
reg uops_0_bits_uop_fu_code_1; // @[util.scala:700:17]
assign io_resp_0_bits_uop_fu_code_1 = uops_0_bits_uop_fu_code_1; // @[util.scala:688:7, :700:17]
wire uops_1_bits_out_uop_fu_code_1 = uops_0_bits_uop_fu_code_1; // @[util.scala:109:23, :700:17]
reg uops_0_bits_uop_fu_code_2; // @[util.scala:700:17]
assign io_resp_0_bits_uop_fu_code_2 = uops_0_bits_uop_fu_code_2; // @[util.scala:688:7, :700:17]
wire uops_1_bits_out_uop_fu_code_2 = uops_0_bits_uop_fu_code_2; // @[util.scala:109:23, :700:17]
reg uops_0_bits_uop_fu_code_3; // @[util.scala:700:17]
assign io_resp_0_bits_uop_fu_code_3 = uops_0_bits_uop_fu_code_3; // @[util.scala:688:7, :700:17]
wire uops_1_bits_out_uop_fu_code_3 = uops_0_bits_uop_fu_code_3; // @[util.scala:109:23, :700:17]
reg uops_0_bits_uop_fu_code_4; // @[util.scala:700:17]
assign io_resp_0_bits_uop_fu_code_4 = uops_0_bits_uop_fu_code_4; // @[util.scala:688:7, :700:17]
wire uops_1_bits_out_uop_fu_code_4 = uops_0_bits_uop_fu_code_4; // @[util.scala:109:23, :700:17]
reg uops_0_bits_uop_fu_code_5; // @[util.scala:700:17]
assign io_resp_0_bits_uop_fu_code_5 = uops_0_bits_uop_fu_code_5; // @[util.scala:688:7, :700:17]
wire uops_1_bits_out_uop_fu_code_5 = uops_0_bits_uop_fu_code_5; // @[util.scala:109:23, :700:17]
reg uops_0_bits_uop_fu_code_6; // @[util.scala:700:17]
assign io_resp_0_bits_uop_fu_code_6 = uops_0_bits_uop_fu_code_6; // @[util.scala:688:7, :700:17]
wire uops_1_bits_out_uop_fu_code_6 = uops_0_bits_uop_fu_code_6; // @[util.scala:109:23, :700:17]
reg uops_0_bits_uop_fu_code_7; // @[util.scala:700:17]
assign io_resp_0_bits_uop_fu_code_7 = uops_0_bits_uop_fu_code_7; // @[util.scala:688:7, :700:17]
wire uops_1_bits_out_uop_fu_code_7 = uops_0_bits_uop_fu_code_7; // @[util.scala:109:23, :700:17]
reg uops_0_bits_uop_fu_code_8; // @[util.scala:700:17]
assign io_resp_0_bits_uop_fu_code_8 = uops_0_bits_uop_fu_code_8; // @[util.scala:688:7, :700:17]
wire uops_1_bits_out_uop_fu_code_8 = uops_0_bits_uop_fu_code_8; // @[util.scala:109:23, :700:17]
reg uops_0_bits_uop_fu_code_9; // @[util.scala:700:17]
assign io_resp_0_bits_uop_fu_code_9 = uops_0_bits_uop_fu_code_9; // @[util.scala:688:7, :700:17]
wire uops_1_bits_out_uop_fu_code_9 = uops_0_bits_uop_fu_code_9; // @[util.scala:109:23, :700:17]
reg uops_0_bits_uop_iw_issued; // @[util.scala:700:17]
assign io_resp_0_bits_uop_iw_issued = uops_0_bits_uop_iw_issued; // @[util.scala:688:7, :700:17]
wire uops_1_bits_out_uop_iw_issued = uops_0_bits_uop_iw_issued; // @[util.scala:109:23, :700:17]
reg uops_0_bits_uop_iw_issued_partial_agen; // @[util.scala:700:17]
assign io_resp_0_bits_uop_iw_issued_partial_agen = uops_0_bits_uop_iw_issued_partial_agen; // @[util.scala:688:7, :700:17]
wire uops_1_bits_out_uop_iw_issued_partial_agen = uops_0_bits_uop_iw_issued_partial_agen; // @[util.scala:109:23, :700:17]
reg uops_0_bits_uop_iw_issued_partial_dgen; // @[util.scala:700:17]
assign io_resp_0_bits_uop_iw_issued_partial_dgen = uops_0_bits_uop_iw_issued_partial_dgen; // @[util.scala:688:7, :700:17]
wire uops_1_bits_out_uop_iw_issued_partial_dgen = uops_0_bits_uop_iw_issued_partial_dgen; // @[util.scala:109:23, :700:17]
reg [2:0] uops_0_bits_uop_iw_p1_speculative_child; // @[util.scala:700:17]
assign io_resp_0_bits_uop_iw_p1_speculative_child = uops_0_bits_uop_iw_p1_speculative_child; // @[util.scala:688:7, :700:17]
wire [2:0] uops_1_bits_out_uop_iw_p1_speculative_child = uops_0_bits_uop_iw_p1_speculative_child; // @[util.scala:109:23, :700:17]
reg [2:0] uops_0_bits_uop_iw_p2_speculative_child; // @[util.scala:700:17]
assign io_resp_0_bits_uop_iw_p2_speculative_child = uops_0_bits_uop_iw_p2_speculative_child; // @[util.scala:688:7, :700:17]
wire [2:0] uops_1_bits_out_uop_iw_p2_speculative_child = uops_0_bits_uop_iw_p2_speculative_child; // @[util.scala:109:23, :700:17]
reg uops_0_bits_uop_iw_p1_bypass_hint; // @[util.scala:700:17]
assign io_resp_0_bits_uop_iw_p1_bypass_hint = uops_0_bits_uop_iw_p1_bypass_hint; // @[util.scala:688:7, :700:17]
wire uops_1_bits_out_uop_iw_p1_bypass_hint = uops_0_bits_uop_iw_p1_bypass_hint; // @[util.scala:109:23, :700:17]
reg uops_0_bits_uop_iw_p2_bypass_hint; // @[util.scala:700:17]
assign io_resp_0_bits_uop_iw_p2_bypass_hint = uops_0_bits_uop_iw_p2_bypass_hint; // @[util.scala:688:7, :700:17]
wire uops_1_bits_out_uop_iw_p2_bypass_hint = uops_0_bits_uop_iw_p2_bypass_hint; // @[util.scala:109:23, :700:17]
reg uops_0_bits_uop_iw_p3_bypass_hint; // @[util.scala:700:17]
assign io_resp_0_bits_uop_iw_p3_bypass_hint = uops_0_bits_uop_iw_p3_bypass_hint; // @[util.scala:688:7, :700:17]
wire uops_1_bits_out_uop_iw_p3_bypass_hint = uops_0_bits_uop_iw_p3_bypass_hint; // @[util.scala:109:23, :700:17]
reg [2:0] uops_0_bits_uop_dis_col_sel; // @[util.scala:700:17]
assign io_resp_0_bits_uop_dis_col_sel = uops_0_bits_uop_dis_col_sel; // @[util.scala:688:7, :700:17]
wire [2:0] uops_1_bits_out_uop_dis_col_sel = uops_0_bits_uop_dis_col_sel; // @[util.scala:109:23, :700:17]
reg [15:0] uops_0_bits_uop_br_mask; // @[util.scala:700:17]
assign io_resp_0_bits_uop_br_mask = uops_0_bits_uop_br_mask; // @[util.scala:688:7, :700:17]
reg [3:0] uops_0_bits_uop_br_tag; // @[util.scala:700:17]
assign io_resp_0_bits_uop_br_tag = uops_0_bits_uop_br_tag; // @[util.scala:688:7, :700:17]
wire [3:0] uops_1_bits_out_uop_br_tag = uops_0_bits_uop_br_tag; // @[util.scala:109:23, :700:17]
reg [3:0] uops_0_bits_uop_br_type; // @[util.scala:700:17]
assign io_resp_0_bits_uop_br_type = uops_0_bits_uop_br_type; // @[util.scala:688:7, :700:17]
wire [3:0] uops_1_bits_out_uop_br_type = uops_0_bits_uop_br_type; // @[util.scala:109:23, :700:17]
reg uops_0_bits_uop_is_sfb; // @[util.scala:700:17]
assign io_resp_0_bits_uop_is_sfb = uops_0_bits_uop_is_sfb; // @[util.scala:688:7, :700:17]
wire uops_1_bits_out_uop_is_sfb = uops_0_bits_uop_is_sfb; // @[util.scala:109:23, :700:17]
reg uops_0_bits_uop_is_fence; // @[util.scala:700:17]
assign io_resp_0_bits_uop_is_fence = uops_0_bits_uop_is_fence; // @[util.scala:688:7, :700:17]
wire uops_1_bits_out_uop_is_fence = uops_0_bits_uop_is_fence; // @[util.scala:109:23, :700:17]
reg uops_0_bits_uop_is_fencei; // @[util.scala:700:17]
assign io_resp_0_bits_uop_is_fencei = uops_0_bits_uop_is_fencei; // @[util.scala:688:7, :700:17]
wire uops_1_bits_out_uop_is_fencei = uops_0_bits_uop_is_fencei; // @[util.scala:109:23, :700:17]
reg uops_0_bits_uop_is_sfence; // @[util.scala:700:17]
assign io_resp_0_bits_uop_is_sfence = uops_0_bits_uop_is_sfence; // @[util.scala:688:7, :700:17]
wire uops_1_bits_out_uop_is_sfence = uops_0_bits_uop_is_sfence; // @[util.scala:109:23, :700:17]
reg uops_0_bits_uop_is_amo; // @[util.scala:700:17]
assign io_resp_0_bits_uop_is_amo = uops_0_bits_uop_is_amo; // @[util.scala:688:7, :700:17]
wire uops_1_bits_out_uop_is_amo = uops_0_bits_uop_is_amo; // @[util.scala:109:23, :700:17]
reg uops_0_bits_uop_is_eret; // @[util.scala:700:17]
assign io_resp_0_bits_uop_is_eret = uops_0_bits_uop_is_eret; // @[util.scala:688:7, :700:17]
wire uops_1_bits_out_uop_is_eret = uops_0_bits_uop_is_eret; // @[util.scala:109:23, :700:17]
reg uops_0_bits_uop_is_sys_pc2epc; // @[util.scala:700:17]
assign io_resp_0_bits_uop_is_sys_pc2epc = uops_0_bits_uop_is_sys_pc2epc; // @[util.scala:688:7, :700:17]
wire uops_1_bits_out_uop_is_sys_pc2epc = uops_0_bits_uop_is_sys_pc2epc; // @[util.scala:109:23, :700:17]
reg uops_0_bits_uop_is_rocc; // @[util.scala:700:17]
assign io_resp_0_bits_uop_is_rocc = uops_0_bits_uop_is_rocc; // @[util.scala:688:7, :700:17]
wire uops_1_bits_out_uop_is_rocc = uops_0_bits_uop_is_rocc; // @[util.scala:109:23, :700:17]
reg uops_0_bits_uop_is_mov; // @[util.scala:700:17]
assign io_resp_0_bits_uop_is_mov = uops_0_bits_uop_is_mov; // @[util.scala:688:7, :700:17]
wire uops_1_bits_out_uop_is_mov = uops_0_bits_uop_is_mov; // @[util.scala:109:23, :700:17]
reg [4:0] uops_0_bits_uop_ftq_idx; // @[util.scala:700:17]
assign io_resp_0_bits_uop_ftq_idx = uops_0_bits_uop_ftq_idx; // @[util.scala:688:7, :700:17]
wire [4:0] uops_1_bits_out_uop_ftq_idx = uops_0_bits_uop_ftq_idx; // @[util.scala:109:23, :700:17]
reg uops_0_bits_uop_edge_inst; // @[util.scala:700:17]
assign io_resp_0_bits_uop_edge_inst = uops_0_bits_uop_edge_inst; // @[util.scala:688:7, :700:17]
wire uops_1_bits_out_uop_edge_inst = uops_0_bits_uop_edge_inst; // @[util.scala:109:23, :700:17]
reg [5:0] uops_0_bits_uop_pc_lob; // @[util.scala:700:17]
assign io_resp_0_bits_uop_pc_lob = uops_0_bits_uop_pc_lob; // @[util.scala:688:7, :700:17]
wire [5:0] uops_1_bits_out_uop_pc_lob = uops_0_bits_uop_pc_lob; // @[util.scala:109:23, :700:17]
reg uops_0_bits_uop_taken; // @[util.scala:700:17]
assign io_resp_0_bits_uop_taken = uops_0_bits_uop_taken; // @[util.scala:688:7, :700:17]
wire uops_1_bits_out_uop_taken = uops_0_bits_uop_taken; // @[util.scala:109:23, :700:17]
reg uops_0_bits_uop_imm_rename; // @[util.scala:700:17]
assign io_resp_0_bits_uop_imm_rename = uops_0_bits_uop_imm_rename; // @[util.scala:688:7, :700:17]
wire uops_1_bits_out_uop_imm_rename = uops_0_bits_uop_imm_rename; // @[util.scala:109:23, :700:17]
reg [2:0] uops_0_bits_uop_imm_sel; // @[util.scala:700:17]
assign io_resp_0_bits_uop_imm_sel = uops_0_bits_uop_imm_sel; // @[util.scala:688:7, :700:17]
wire [2:0] uops_1_bits_out_uop_imm_sel = uops_0_bits_uop_imm_sel; // @[util.scala:109:23, :700:17]
reg [4:0] uops_0_bits_uop_pimm; // @[util.scala:700:17]
assign io_resp_0_bits_uop_pimm = uops_0_bits_uop_pimm; // @[util.scala:688:7, :700:17]
wire [4:0] uops_1_bits_out_uop_pimm = uops_0_bits_uop_pimm; // @[util.scala:109:23, :700:17]
reg [19:0] uops_0_bits_uop_imm_packed; // @[util.scala:700:17]
assign io_resp_0_bits_uop_imm_packed = uops_0_bits_uop_imm_packed; // @[util.scala:688:7, :700:17]
wire [19:0] uops_1_bits_out_uop_imm_packed = uops_0_bits_uop_imm_packed; // @[util.scala:109:23, :700:17]
reg [1:0] uops_0_bits_uop_op1_sel; // @[util.scala:700:17]
assign io_resp_0_bits_uop_op1_sel = uops_0_bits_uop_op1_sel; // @[util.scala:688:7, :700:17]
wire [1:0] uops_1_bits_out_uop_op1_sel = uops_0_bits_uop_op1_sel; // @[util.scala:109:23, :700:17]
reg [2:0] uops_0_bits_uop_op2_sel; // @[util.scala:700:17]
assign io_resp_0_bits_uop_op2_sel = uops_0_bits_uop_op2_sel; // @[util.scala:688:7, :700:17]
wire [2:0] uops_1_bits_out_uop_op2_sel = uops_0_bits_uop_op2_sel; // @[util.scala:109:23, :700:17]
reg uops_0_bits_uop_fp_ctrl_ldst; // @[util.scala:700:17]
assign io_resp_0_bits_uop_fp_ctrl_ldst = uops_0_bits_uop_fp_ctrl_ldst; // @[util.scala:688:7, :700:17]
wire uops_1_bits_out_uop_fp_ctrl_ldst = uops_0_bits_uop_fp_ctrl_ldst; // @[util.scala:109:23, :700:17]
reg uops_0_bits_uop_fp_ctrl_wen; // @[util.scala:700:17]
assign io_resp_0_bits_uop_fp_ctrl_wen = uops_0_bits_uop_fp_ctrl_wen; // @[util.scala:688:7, :700:17]
wire uops_1_bits_out_uop_fp_ctrl_wen = uops_0_bits_uop_fp_ctrl_wen; // @[util.scala:109:23, :700:17]
reg uops_0_bits_uop_fp_ctrl_ren1; // @[util.scala:700:17]
assign io_resp_0_bits_uop_fp_ctrl_ren1 = uops_0_bits_uop_fp_ctrl_ren1; // @[util.scala:688:7, :700:17]
wire uops_1_bits_out_uop_fp_ctrl_ren1 = uops_0_bits_uop_fp_ctrl_ren1; // @[util.scala:109:23, :700:17]
reg uops_0_bits_uop_fp_ctrl_ren2; // @[util.scala:700:17]
assign io_resp_0_bits_uop_fp_ctrl_ren2 = uops_0_bits_uop_fp_ctrl_ren2; // @[util.scala:688:7, :700:17]
wire uops_1_bits_out_uop_fp_ctrl_ren2 = uops_0_bits_uop_fp_ctrl_ren2; // @[util.scala:109:23, :700:17]
reg uops_0_bits_uop_fp_ctrl_ren3; // @[util.scala:700:17]
assign io_resp_0_bits_uop_fp_ctrl_ren3 = uops_0_bits_uop_fp_ctrl_ren3; // @[util.scala:688:7, :700:17]
wire uops_1_bits_out_uop_fp_ctrl_ren3 = uops_0_bits_uop_fp_ctrl_ren3; // @[util.scala:109:23, :700:17]
reg uops_0_bits_uop_fp_ctrl_swap12; // @[util.scala:700:17]
assign io_resp_0_bits_uop_fp_ctrl_swap12 = uops_0_bits_uop_fp_ctrl_swap12; // @[util.scala:688:7, :700:17]
wire uops_1_bits_out_uop_fp_ctrl_swap12 = uops_0_bits_uop_fp_ctrl_swap12; // @[util.scala:109:23, :700:17]
reg uops_0_bits_uop_fp_ctrl_swap23; // @[util.scala:700:17]
assign io_resp_0_bits_uop_fp_ctrl_swap23 = uops_0_bits_uop_fp_ctrl_swap23; // @[util.scala:688:7, :700:17]
wire uops_1_bits_out_uop_fp_ctrl_swap23 = uops_0_bits_uop_fp_ctrl_swap23; // @[util.scala:109:23, :700:17]
reg [1:0] uops_0_bits_uop_fp_ctrl_typeTagIn; // @[util.scala:700:17]
assign io_resp_0_bits_uop_fp_ctrl_typeTagIn = uops_0_bits_uop_fp_ctrl_typeTagIn; // @[util.scala:688:7, :700:17]
wire [1:0] uops_1_bits_out_uop_fp_ctrl_typeTagIn = uops_0_bits_uop_fp_ctrl_typeTagIn; // @[util.scala:109:23, :700:17]
reg [1:0] uops_0_bits_uop_fp_ctrl_typeTagOut; // @[util.scala:700:17]
assign io_resp_0_bits_uop_fp_ctrl_typeTagOut = uops_0_bits_uop_fp_ctrl_typeTagOut; // @[util.scala:688:7, :700:17]
wire [1:0] uops_1_bits_out_uop_fp_ctrl_typeTagOut = uops_0_bits_uop_fp_ctrl_typeTagOut; // @[util.scala:109:23, :700:17]
reg uops_0_bits_uop_fp_ctrl_fromint; // @[util.scala:700:17]
assign io_resp_0_bits_uop_fp_ctrl_fromint = uops_0_bits_uop_fp_ctrl_fromint; // @[util.scala:688:7, :700:17]
wire uops_1_bits_out_uop_fp_ctrl_fromint = uops_0_bits_uop_fp_ctrl_fromint; // @[util.scala:109:23, :700:17]
reg uops_0_bits_uop_fp_ctrl_toint; // @[util.scala:700:17]
assign io_resp_0_bits_uop_fp_ctrl_toint = uops_0_bits_uop_fp_ctrl_toint; // @[util.scala:688:7, :700:17]
wire uops_1_bits_out_uop_fp_ctrl_toint = uops_0_bits_uop_fp_ctrl_toint; // @[util.scala:109:23, :700:17]
reg uops_0_bits_uop_fp_ctrl_fastpipe; // @[util.scala:700:17]
assign io_resp_0_bits_uop_fp_ctrl_fastpipe = uops_0_bits_uop_fp_ctrl_fastpipe; // @[util.scala:688:7, :700:17]
wire uops_1_bits_out_uop_fp_ctrl_fastpipe = uops_0_bits_uop_fp_ctrl_fastpipe; // @[util.scala:109:23, :700:17]
reg uops_0_bits_uop_fp_ctrl_fma; // @[util.scala:700:17]
assign io_resp_0_bits_uop_fp_ctrl_fma = uops_0_bits_uop_fp_ctrl_fma; // @[util.scala:688:7, :700:17]
wire uops_1_bits_out_uop_fp_ctrl_fma = uops_0_bits_uop_fp_ctrl_fma; // @[util.scala:109:23, :700:17]
reg uops_0_bits_uop_fp_ctrl_div; // @[util.scala:700:17]
assign io_resp_0_bits_uop_fp_ctrl_div = uops_0_bits_uop_fp_ctrl_div; // @[util.scala:688:7, :700:17]
wire uops_1_bits_out_uop_fp_ctrl_div = uops_0_bits_uop_fp_ctrl_div; // @[util.scala:109:23, :700:17]
reg uops_0_bits_uop_fp_ctrl_sqrt; // @[util.scala:700:17]
assign io_resp_0_bits_uop_fp_ctrl_sqrt = uops_0_bits_uop_fp_ctrl_sqrt; // @[util.scala:688:7, :700:17]
wire uops_1_bits_out_uop_fp_ctrl_sqrt = uops_0_bits_uop_fp_ctrl_sqrt; // @[util.scala:109:23, :700:17]
reg uops_0_bits_uop_fp_ctrl_wflags; // @[util.scala:700:17]
assign io_resp_0_bits_uop_fp_ctrl_wflags = uops_0_bits_uop_fp_ctrl_wflags; // @[util.scala:688:7, :700:17]
wire uops_1_bits_out_uop_fp_ctrl_wflags = uops_0_bits_uop_fp_ctrl_wflags; // @[util.scala:109:23, :700:17]
reg uops_0_bits_uop_fp_ctrl_vec; // @[util.scala:700:17]
assign io_resp_0_bits_uop_fp_ctrl_vec = uops_0_bits_uop_fp_ctrl_vec; // @[util.scala:688:7, :700:17]
wire uops_1_bits_out_uop_fp_ctrl_vec = uops_0_bits_uop_fp_ctrl_vec; // @[util.scala:109:23, :700:17]
reg [6:0] uops_0_bits_uop_rob_idx; // @[util.scala:700:17]
assign io_resp_0_bits_uop_rob_idx = uops_0_bits_uop_rob_idx; // @[util.scala:688:7, :700:17]
wire [6:0] uops_1_bits_out_uop_rob_idx = uops_0_bits_uop_rob_idx; // @[util.scala:109:23, :700:17]
reg [4:0] uops_0_bits_uop_ldq_idx; // @[util.scala:700:17]
assign io_resp_0_bits_uop_ldq_idx = uops_0_bits_uop_ldq_idx; // @[util.scala:688:7, :700:17]
wire [4:0] uops_1_bits_out_uop_ldq_idx = uops_0_bits_uop_ldq_idx; // @[util.scala:109:23, :700:17]
reg [4:0] uops_0_bits_uop_stq_idx; // @[util.scala:700:17]
assign io_resp_0_bits_uop_stq_idx = uops_0_bits_uop_stq_idx; // @[util.scala:688:7, :700:17]
wire [4:0] uops_1_bits_out_uop_stq_idx = uops_0_bits_uop_stq_idx; // @[util.scala:109:23, :700:17]
reg [1:0] uops_0_bits_uop_rxq_idx; // @[util.scala:700:17]
assign io_resp_0_bits_uop_rxq_idx = uops_0_bits_uop_rxq_idx; // @[util.scala:688:7, :700:17]
wire [1:0] uops_1_bits_out_uop_rxq_idx = uops_0_bits_uop_rxq_idx; // @[util.scala:109:23, :700:17]
reg [6:0] uops_0_bits_uop_pdst; // @[util.scala:700:17]
assign io_resp_0_bits_uop_pdst = uops_0_bits_uop_pdst; // @[util.scala:688:7, :700:17]
wire [6:0] uops_1_bits_out_uop_pdst = uops_0_bits_uop_pdst; // @[util.scala:109:23, :700:17]
reg [6:0] uops_0_bits_uop_prs1; // @[util.scala:700:17]
assign io_resp_0_bits_uop_prs1 = uops_0_bits_uop_prs1; // @[util.scala:688:7, :700:17]
wire [6:0] uops_1_bits_out_uop_prs1 = uops_0_bits_uop_prs1; // @[util.scala:109:23, :700:17]
reg [6:0] uops_0_bits_uop_prs2; // @[util.scala:700:17]
assign io_resp_0_bits_uop_prs2 = uops_0_bits_uop_prs2; // @[util.scala:688:7, :700:17]
wire [6:0] uops_1_bits_out_uop_prs2 = uops_0_bits_uop_prs2; // @[util.scala:109:23, :700:17]
reg [6:0] uops_0_bits_uop_prs3; // @[util.scala:700:17]
assign io_resp_0_bits_uop_prs3 = uops_0_bits_uop_prs3; // @[util.scala:688:7, :700:17]
wire [6:0] uops_1_bits_out_uop_prs3 = uops_0_bits_uop_prs3; // @[util.scala:109:23, :700:17]
reg [4:0] uops_0_bits_uop_ppred; // @[util.scala:700:17]
assign io_resp_0_bits_uop_ppred = uops_0_bits_uop_ppred; // @[util.scala:688:7, :700:17]
wire [4:0] uops_1_bits_out_uop_ppred = uops_0_bits_uop_ppred; // @[util.scala:109:23, :700:17]
reg uops_0_bits_uop_prs1_busy; // @[util.scala:700:17]
assign io_resp_0_bits_uop_prs1_busy = uops_0_bits_uop_prs1_busy; // @[util.scala:688:7, :700:17]
wire uops_1_bits_out_uop_prs1_busy = uops_0_bits_uop_prs1_busy; // @[util.scala:109:23, :700:17]
reg uops_0_bits_uop_prs2_busy; // @[util.scala:700:17]
assign io_resp_0_bits_uop_prs2_busy = uops_0_bits_uop_prs2_busy; // @[util.scala:688:7, :700:17]
wire uops_1_bits_out_uop_prs2_busy = uops_0_bits_uop_prs2_busy; // @[util.scala:109:23, :700:17]
reg uops_0_bits_uop_prs3_busy; // @[util.scala:700:17]
assign io_resp_0_bits_uop_prs3_busy = uops_0_bits_uop_prs3_busy; // @[util.scala:688:7, :700:17]
wire uops_1_bits_out_uop_prs3_busy = uops_0_bits_uop_prs3_busy; // @[util.scala:109:23, :700:17]
reg uops_0_bits_uop_ppred_busy; // @[util.scala:700:17]
assign io_resp_0_bits_uop_ppred_busy = uops_0_bits_uop_ppred_busy; // @[util.scala:688:7, :700:17]
wire uops_1_bits_out_uop_ppred_busy = uops_0_bits_uop_ppred_busy; // @[util.scala:109:23, :700:17]
reg [6:0] uops_0_bits_uop_stale_pdst; // @[util.scala:700:17]
assign io_resp_0_bits_uop_stale_pdst = uops_0_bits_uop_stale_pdst; // @[util.scala:688:7, :700:17]
wire [6:0] uops_1_bits_out_uop_stale_pdst = uops_0_bits_uop_stale_pdst; // @[util.scala:109:23, :700:17]
reg uops_0_bits_uop_exception; // @[util.scala:700:17]
assign io_resp_0_bits_uop_exception = uops_0_bits_uop_exception; // @[util.scala:688:7, :700:17]
wire uops_1_bits_out_uop_exception = uops_0_bits_uop_exception; // @[util.scala:109:23, :700:17]
reg [63:0] uops_0_bits_uop_exc_cause; // @[util.scala:700:17]
assign io_resp_0_bits_uop_exc_cause = uops_0_bits_uop_exc_cause; // @[util.scala:688:7, :700:17]
wire [63:0] uops_1_bits_out_uop_exc_cause = uops_0_bits_uop_exc_cause; // @[util.scala:109:23, :700:17]
reg [4:0] uops_0_bits_uop_mem_cmd; // @[util.scala:700:17]
assign io_resp_0_bits_uop_mem_cmd = uops_0_bits_uop_mem_cmd; // @[util.scala:688:7, :700:17]
wire [4:0] uops_1_bits_out_uop_mem_cmd = uops_0_bits_uop_mem_cmd; // @[util.scala:109:23, :700:17]
reg [1:0] uops_0_bits_uop_mem_size; // @[util.scala:700:17]
assign io_resp_0_bits_uop_mem_size = uops_0_bits_uop_mem_size; // @[util.scala:688:7, :700:17]
wire [1:0] uops_1_bits_out_uop_mem_size = uops_0_bits_uop_mem_size; // @[util.scala:109:23, :700:17]
reg uops_0_bits_uop_mem_signed; // @[util.scala:700:17]
assign io_resp_0_bits_uop_mem_signed = uops_0_bits_uop_mem_signed; // @[util.scala:688:7, :700:17]
wire uops_1_bits_out_uop_mem_signed = uops_0_bits_uop_mem_signed; // @[util.scala:109:23, :700:17]
reg uops_0_bits_uop_uses_ldq; // @[util.scala:700:17]
assign io_resp_0_bits_uop_uses_ldq = uops_0_bits_uop_uses_ldq; // @[util.scala:688:7, :700:17]
wire uops_1_bits_out_uop_uses_ldq = uops_0_bits_uop_uses_ldq; // @[util.scala:109:23, :700:17]
reg uops_0_bits_uop_uses_stq; // @[util.scala:700:17]
assign io_resp_0_bits_uop_uses_stq = uops_0_bits_uop_uses_stq; // @[util.scala:688:7, :700:17]
wire uops_1_bits_out_uop_uses_stq = uops_0_bits_uop_uses_stq; // @[util.scala:109:23, :700:17]
reg uops_0_bits_uop_is_unique; // @[util.scala:700:17]
assign io_resp_0_bits_uop_is_unique = uops_0_bits_uop_is_unique; // @[util.scala:688:7, :700:17]
wire uops_1_bits_out_uop_is_unique = uops_0_bits_uop_is_unique; // @[util.scala:109:23, :700:17]
reg uops_0_bits_uop_flush_on_commit; // @[util.scala:700:17]
assign io_resp_0_bits_uop_flush_on_commit = uops_0_bits_uop_flush_on_commit; // @[util.scala:688:7, :700:17]
wire uops_1_bits_out_uop_flush_on_commit = uops_0_bits_uop_flush_on_commit; // @[util.scala:109:23, :700:17]
reg [2:0] uops_0_bits_uop_csr_cmd; // @[util.scala:700:17]
assign io_resp_0_bits_uop_csr_cmd = uops_0_bits_uop_csr_cmd; // @[util.scala:688:7, :700:17]
wire [2:0] uops_1_bits_out_uop_csr_cmd = uops_0_bits_uop_csr_cmd; // @[util.scala:109:23, :700:17]
reg uops_0_bits_uop_ldst_is_rs1; // @[util.scala:700:17]
assign io_resp_0_bits_uop_ldst_is_rs1 = uops_0_bits_uop_ldst_is_rs1; // @[util.scala:688:7, :700:17]
wire uops_1_bits_out_uop_ldst_is_rs1 = uops_0_bits_uop_ldst_is_rs1; // @[util.scala:109:23, :700:17]
reg [5:0] uops_0_bits_uop_ldst; // @[util.scala:700:17]
assign io_resp_0_bits_uop_ldst = uops_0_bits_uop_ldst; // @[util.scala:688:7, :700:17]
wire [5:0] uops_1_bits_out_uop_ldst = uops_0_bits_uop_ldst; // @[util.scala:109:23, :700:17]
reg [5:0] uops_0_bits_uop_lrs1; // @[util.scala:700:17]
assign io_resp_0_bits_uop_lrs1 = uops_0_bits_uop_lrs1; // @[util.scala:688:7, :700:17]
wire [5:0] uops_1_bits_out_uop_lrs1 = uops_0_bits_uop_lrs1; // @[util.scala:109:23, :700:17]
reg [5:0] uops_0_bits_uop_lrs2; // @[util.scala:700:17]
assign io_resp_0_bits_uop_lrs2 = uops_0_bits_uop_lrs2; // @[util.scala:688:7, :700:17]
wire [5:0] uops_1_bits_out_uop_lrs2 = uops_0_bits_uop_lrs2; // @[util.scala:109:23, :700:17]
reg [5:0] uops_0_bits_uop_lrs3; // @[util.scala:700:17]
assign io_resp_0_bits_uop_lrs3 = uops_0_bits_uop_lrs3; // @[util.scala:688:7, :700:17]
wire [5:0] uops_1_bits_out_uop_lrs3 = uops_0_bits_uop_lrs3; // @[util.scala:109:23, :700:17]
reg [1:0] uops_0_bits_uop_dst_rtype; // @[util.scala:700:17]
assign io_resp_0_bits_uop_dst_rtype = uops_0_bits_uop_dst_rtype; // @[util.scala:688:7, :700:17]
wire [1:0] uops_1_bits_out_uop_dst_rtype = uops_0_bits_uop_dst_rtype; // @[util.scala:109:23, :700:17]
reg [1:0] uops_0_bits_uop_lrs1_rtype; // @[util.scala:700:17]
assign io_resp_0_bits_uop_lrs1_rtype = uops_0_bits_uop_lrs1_rtype; // @[util.scala:688:7, :700:17]
wire [1:0] uops_1_bits_out_uop_lrs1_rtype = uops_0_bits_uop_lrs1_rtype; // @[util.scala:109:23, :700:17]
reg [1:0] uops_0_bits_uop_lrs2_rtype; // @[util.scala:700:17]
assign io_resp_0_bits_uop_lrs2_rtype = uops_0_bits_uop_lrs2_rtype; // @[util.scala:688:7, :700:17]
wire [1:0] uops_1_bits_out_uop_lrs2_rtype = uops_0_bits_uop_lrs2_rtype; // @[util.scala:109:23, :700:17]
reg uops_0_bits_uop_frs3_en; // @[util.scala:700:17]
assign io_resp_0_bits_uop_frs3_en = uops_0_bits_uop_frs3_en; // @[util.scala:688:7, :700:17]
wire uops_1_bits_out_uop_frs3_en = uops_0_bits_uop_frs3_en; // @[util.scala:109:23, :700:17]
reg uops_0_bits_uop_fcn_dw; // @[util.scala:700:17]
assign io_resp_0_bits_uop_fcn_dw = uops_0_bits_uop_fcn_dw; // @[util.scala:688:7, :700:17]
wire uops_1_bits_out_uop_fcn_dw = uops_0_bits_uop_fcn_dw; // @[util.scala:109:23, :700:17]
reg [4:0] uops_0_bits_uop_fcn_op; // @[util.scala:700:17]
assign io_resp_0_bits_uop_fcn_op = uops_0_bits_uop_fcn_op; // @[util.scala:688:7, :700:17]
wire [4:0] uops_1_bits_out_uop_fcn_op = uops_0_bits_uop_fcn_op; // @[util.scala:109:23, :700:17]
reg uops_0_bits_uop_fp_val; // @[util.scala:700:17]
assign io_resp_0_bits_uop_fp_val = uops_0_bits_uop_fp_val; // @[util.scala:688:7, :700:17]
wire uops_1_bits_out_uop_fp_val = uops_0_bits_uop_fp_val; // @[util.scala:109:23, :700:17]
reg [2:0] uops_0_bits_uop_fp_rm; // @[util.scala:700:17]
assign io_resp_0_bits_uop_fp_rm = uops_0_bits_uop_fp_rm; // @[util.scala:688:7, :700:17]
wire [2:0] uops_1_bits_out_uop_fp_rm = uops_0_bits_uop_fp_rm; // @[util.scala:109:23, :700:17]
reg [1:0] uops_0_bits_uop_fp_typ; // @[util.scala:700:17]
assign io_resp_0_bits_uop_fp_typ = uops_0_bits_uop_fp_typ; // @[util.scala:688:7, :700:17]
wire [1:0] uops_1_bits_out_uop_fp_typ = uops_0_bits_uop_fp_typ; // @[util.scala:109:23, :700:17]
reg uops_0_bits_uop_xcpt_pf_if; // @[util.scala:700:17]
assign io_resp_0_bits_uop_xcpt_pf_if = uops_0_bits_uop_xcpt_pf_if; // @[util.scala:688:7, :700:17]
wire uops_1_bits_out_uop_xcpt_pf_if = uops_0_bits_uop_xcpt_pf_if; // @[util.scala:109:23, :700:17]
reg uops_0_bits_uop_xcpt_ae_if; // @[util.scala:700:17]
assign io_resp_0_bits_uop_xcpt_ae_if = uops_0_bits_uop_xcpt_ae_if; // @[util.scala:688:7, :700:17]
wire uops_1_bits_out_uop_xcpt_ae_if = uops_0_bits_uop_xcpt_ae_if; // @[util.scala:109:23, :700:17]
reg uops_0_bits_uop_xcpt_ma_if; // @[util.scala:700:17]
assign io_resp_0_bits_uop_xcpt_ma_if = uops_0_bits_uop_xcpt_ma_if; // @[util.scala:688:7, :700:17]
wire uops_1_bits_out_uop_xcpt_ma_if = uops_0_bits_uop_xcpt_ma_if; // @[util.scala:109:23, :700:17]
reg uops_0_bits_uop_bp_debug_if; // @[util.scala:700:17]
assign io_resp_0_bits_uop_bp_debug_if = uops_0_bits_uop_bp_debug_if; // @[util.scala:688:7, :700:17]
wire uops_1_bits_out_uop_bp_debug_if = uops_0_bits_uop_bp_debug_if; // @[util.scala:109:23, :700:17]
reg uops_0_bits_uop_bp_xcpt_if; // @[util.scala:700:17]
assign io_resp_0_bits_uop_bp_xcpt_if = uops_0_bits_uop_bp_xcpt_if; // @[util.scala:688:7, :700:17]
wire uops_1_bits_out_uop_bp_xcpt_if = uops_0_bits_uop_bp_xcpt_if; // @[util.scala:109:23, :700:17]
reg [2:0] uops_0_bits_uop_debug_fsrc; // @[util.scala:700:17]
assign io_resp_0_bits_uop_debug_fsrc = uops_0_bits_uop_debug_fsrc; // @[util.scala:688:7, :700:17]
wire [2:0] uops_1_bits_out_uop_debug_fsrc = uops_0_bits_uop_debug_fsrc; // @[util.scala:109:23, :700:17]
reg [2:0] uops_0_bits_uop_debug_tsrc; // @[util.scala:700:17]
assign io_resp_0_bits_uop_debug_tsrc = uops_0_bits_uop_debug_tsrc; // @[util.scala:688:7, :700:17]
wire [2:0] uops_1_bits_out_uop_debug_tsrc = uops_0_bits_uop_debug_tsrc; // @[util.scala:109:23, :700:17]
reg [63:0] uops_0_bits_rs1_data; // @[util.scala:700:17]
assign io_resp_0_bits_rs1_data = uops_0_bits_rs1_data; // @[util.scala:688:7, :700:17]
wire [63:0] uops_1_bits_out_rs1_data = uops_0_bits_rs1_data; // @[util.scala:109:23, :700:17]
reg [63:0] uops_0_bits_rs2_data; // @[util.scala:700:17]
assign io_resp_0_bits_rs2_data = uops_0_bits_rs2_data; // @[util.scala:688:7, :700:17]
wire [63:0] uops_1_bits_out_rs2_data = uops_0_bits_rs2_data; // @[util.scala:109:23, :700:17]
reg [63:0] uops_0_bits_imm_data; // @[util.scala:700:17]
assign io_resp_0_bits_imm_data = uops_0_bits_imm_data; // @[util.scala:688:7, :700:17]
wire [63:0] uops_1_bits_out_imm_data = uops_0_bits_imm_data; // @[util.scala:109:23, :700:17]
reg uops_1_valid; // @[util.scala:700:17]
assign io_resp_1_valid = uops_1_valid; // @[util.scala:688:7, :700:17]
reg [31:0] uops_1_bits_uop_inst; // @[util.scala:700:17]
assign io_resp_1_bits_uop_inst = uops_1_bits_uop_inst; // @[util.scala:688:7, :700:17]
wire [31:0] uops_2_bits_out_uop_inst = uops_1_bits_uop_inst; // @[util.scala:109:23, :700:17]
reg [31:0] uops_1_bits_uop_debug_inst; // @[util.scala:700:17]
assign io_resp_1_bits_uop_debug_inst = uops_1_bits_uop_debug_inst; // @[util.scala:688:7, :700:17]
wire [31:0] uops_2_bits_out_uop_debug_inst = uops_1_bits_uop_debug_inst; // @[util.scala:109:23, :700:17]
reg uops_1_bits_uop_is_rvc; // @[util.scala:700:17]
assign io_resp_1_bits_uop_is_rvc = uops_1_bits_uop_is_rvc; // @[util.scala:688:7, :700:17]
wire uops_2_bits_out_uop_is_rvc = uops_1_bits_uop_is_rvc; // @[util.scala:109:23, :700:17]
reg [39:0] uops_1_bits_uop_debug_pc; // @[util.scala:700:17]
assign io_resp_1_bits_uop_debug_pc = uops_1_bits_uop_debug_pc; // @[util.scala:688:7, :700:17]
wire [39:0] uops_2_bits_out_uop_debug_pc = uops_1_bits_uop_debug_pc; // @[util.scala:109:23, :700:17]
reg uops_1_bits_uop_iq_type_0; // @[util.scala:700:17]
assign io_resp_1_bits_uop_iq_type_0 = uops_1_bits_uop_iq_type_0; // @[util.scala:688:7, :700:17]
wire uops_2_bits_out_uop_iq_type_0 = uops_1_bits_uop_iq_type_0; // @[util.scala:109:23, :700:17]
reg uops_1_bits_uop_iq_type_1; // @[util.scala:700:17]
assign io_resp_1_bits_uop_iq_type_1 = uops_1_bits_uop_iq_type_1; // @[util.scala:688:7, :700:17]
wire uops_2_bits_out_uop_iq_type_1 = uops_1_bits_uop_iq_type_1; // @[util.scala:109:23, :700:17]
reg uops_1_bits_uop_iq_type_2; // @[util.scala:700:17]
assign io_resp_1_bits_uop_iq_type_2 = uops_1_bits_uop_iq_type_2; // @[util.scala:688:7, :700:17]
wire uops_2_bits_out_uop_iq_type_2 = uops_1_bits_uop_iq_type_2; // @[util.scala:109:23, :700:17]
reg uops_1_bits_uop_iq_type_3; // @[util.scala:700:17]
assign io_resp_1_bits_uop_iq_type_3 = uops_1_bits_uop_iq_type_3; // @[util.scala:688:7, :700:17]
wire uops_2_bits_out_uop_iq_type_3 = uops_1_bits_uop_iq_type_3; // @[util.scala:109:23, :700:17]
reg uops_1_bits_uop_fu_code_0; // @[util.scala:700:17]
assign io_resp_1_bits_uop_fu_code_0 = uops_1_bits_uop_fu_code_0; // @[util.scala:688:7, :700:17]
wire uops_2_bits_out_uop_fu_code_0 = uops_1_bits_uop_fu_code_0; // @[util.scala:109:23, :700:17]
reg uops_1_bits_uop_fu_code_1; // @[util.scala:700:17]
assign io_resp_1_bits_uop_fu_code_1 = uops_1_bits_uop_fu_code_1; // @[util.scala:688:7, :700:17]
wire uops_2_bits_out_uop_fu_code_1 = uops_1_bits_uop_fu_code_1; // @[util.scala:109:23, :700:17]
reg uops_1_bits_uop_fu_code_2; // @[util.scala:700:17]
assign io_resp_1_bits_uop_fu_code_2 = uops_1_bits_uop_fu_code_2; // @[util.scala:688:7, :700:17]
wire uops_2_bits_out_uop_fu_code_2 = uops_1_bits_uop_fu_code_2; // @[util.scala:109:23, :700:17]
reg uops_1_bits_uop_fu_code_3; // @[util.scala:700:17]
assign io_resp_1_bits_uop_fu_code_3 = uops_1_bits_uop_fu_code_3; // @[util.scala:688:7, :700:17]
wire uops_2_bits_out_uop_fu_code_3 = uops_1_bits_uop_fu_code_3; // @[util.scala:109:23, :700:17]
reg uops_1_bits_uop_fu_code_4; // @[util.scala:700:17]
assign io_resp_1_bits_uop_fu_code_4 = uops_1_bits_uop_fu_code_4; // @[util.scala:688:7, :700:17]
wire uops_2_bits_out_uop_fu_code_4 = uops_1_bits_uop_fu_code_4; // @[util.scala:109:23, :700:17]
reg uops_1_bits_uop_fu_code_5; // @[util.scala:700:17]
assign io_resp_1_bits_uop_fu_code_5 = uops_1_bits_uop_fu_code_5; // @[util.scala:688:7, :700:17]
wire uops_2_bits_out_uop_fu_code_5 = uops_1_bits_uop_fu_code_5; // @[util.scala:109:23, :700:17]
reg uops_1_bits_uop_fu_code_6; // @[util.scala:700:17]
assign io_resp_1_bits_uop_fu_code_6 = uops_1_bits_uop_fu_code_6; // @[util.scala:688:7, :700:17]
wire uops_2_bits_out_uop_fu_code_6 = uops_1_bits_uop_fu_code_6; // @[util.scala:109:23, :700:17]
reg uops_1_bits_uop_fu_code_7; // @[util.scala:700:17]
assign io_resp_1_bits_uop_fu_code_7 = uops_1_bits_uop_fu_code_7; // @[util.scala:688:7, :700:17]
wire uops_2_bits_out_uop_fu_code_7 = uops_1_bits_uop_fu_code_7; // @[util.scala:109:23, :700:17]
reg uops_1_bits_uop_fu_code_8; // @[util.scala:700:17]
assign io_resp_1_bits_uop_fu_code_8 = uops_1_bits_uop_fu_code_8; // @[util.scala:688:7, :700:17]
wire uops_2_bits_out_uop_fu_code_8 = uops_1_bits_uop_fu_code_8; // @[util.scala:109:23, :700:17]
reg uops_1_bits_uop_fu_code_9; // @[util.scala:700:17]
assign io_resp_1_bits_uop_fu_code_9 = uops_1_bits_uop_fu_code_9; // @[util.scala:688:7, :700:17]
wire uops_2_bits_out_uop_fu_code_9 = uops_1_bits_uop_fu_code_9; // @[util.scala:109:23, :700:17]
reg uops_1_bits_uop_iw_issued; // @[util.scala:700:17]
assign io_resp_1_bits_uop_iw_issued = uops_1_bits_uop_iw_issued; // @[util.scala:688:7, :700:17]
wire uops_2_bits_out_uop_iw_issued = uops_1_bits_uop_iw_issued; // @[util.scala:109:23, :700:17]
reg uops_1_bits_uop_iw_issued_partial_agen; // @[util.scala:700:17]
assign io_resp_1_bits_uop_iw_issued_partial_agen = uops_1_bits_uop_iw_issued_partial_agen; // @[util.scala:688:7, :700:17]
wire uops_2_bits_out_uop_iw_issued_partial_agen = uops_1_bits_uop_iw_issued_partial_agen; // @[util.scala:109:23, :700:17]
reg uops_1_bits_uop_iw_issued_partial_dgen; // @[util.scala:700:17]
assign io_resp_1_bits_uop_iw_issued_partial_dgen = uops_1_bits_uop_iw_issued_partial_dgen; // @[util.scala:688:7, :700:17]
wire uops_2_bits_out_uop_iw_issued_partial_dgen = uops_1_bits_uop_iw_issued_partial_dgen; // @[util.scala:109:23, :700:17]
reg [2:0] uops_1_bits_uop_iw_p1_speculative_child; // @[util.scala:700:17]
assign io_resp_1_bits_uop_iw_p1_speculative_child = uops_1_bits_uop_iw_p1_speculative_child; // @[util.scala:688:7, :700:17]
wire [2:0] uops_2_bits_out_uop_iw_p1_speculative_child = uops_1_bits_uop_iw_p1_speculative_child; // @[util.scala:109:23, :700:17]
reg [2:0] uops_1_bits_uop_iw_p2_speculative_child; // @[util.scala:700:17]
assign io_resp_1_bits_uop_iw_p2_speculative_child = uops_1_bits_uop_iw_p2_speculative_child; // @[util.scala:688:7, :700:17]
wire [2:0] uops_2_bits_out_uop_iw_p2_speculative_child = uops_1_bits_uop_iw_p2_speculative_child; // @[util.scala:109:23, :700:17]
reg uops_1_bits_uop_iw_p1_bypass_hint; // @[util.scala:700:17]
assign io_resp_1_bits_uop_iw_p1_bypass_hint = uops_1_bits_uop_iw_p1_bypass_hint; // @[util.scala:688:7, :700:17]
wire uops_2_bits_out_uop_iw_p1_bypass_hint = uops_1_bits_uop_iw_p1_bypass_hint; // @[util.scala:109:23, :700:17]
reg uops_1_bits_uop_iw_p2_bypass_hint; // @[util.scala:700:17]
assign io_resp_1_bits_uop_iw_p2_bypass_hint = uops_1_bits_uop_iw_p2_bypass_hint; // @[util.scala:688:7, :700:17]
wire uops_2_bits_out_uop_iw_p2_bypass_hint = uops_1_bits_uop_iw_p2_bypass_hint; // @[util.scala:109:23, :700:17]
reg uops_1_bits_uop_iw_p3_bypass_hint; // @[util.scala:700:17]
assign io_resp_1_bits_uop_iw_p3_bypass_hint = uops_1_bits_uop_iw_p3_bypass_hint; // @[util.scala:688:7, :700:17]
wire uops_2_bits_out_uop_iw_p3_bypass_hint = uops_1_bits_uop_iw_p3_bypass_hint; // @[util.scala:109:23, :700:17]
reg [2:0] uops_1_bits_uop_dis_col_sel; // @[util.scala:700:17]
assign io_resp_1_bits_uop_dis_col_sel = uops_1_bits_uop_dis_col_sel; // @[util.scala:688:7, :700:17]
wire [2:0] uops_2_bits_out_uop_dis_col_sel = uops_1_bits_uop_dis_col_sel; // @[util.scala:109:23, :700:17]
reg [15:0] uops_1_bits_uop_br_mask; // @[util.scala:700:17]
assign io_resp_1_bits_uop_br_mask = uops_1_bits_uop_br_mask; // @[util.scala:688:7, :700:17]
reg [3:0] uops_1_bits_uop_br_tag; // @[util.scala:700:17]
assign io_resp_1_bits_uop_br_tag = uops_1_bits_uop_br_tag; // @[util.scala:688:7, :700:17]
wire [3:0] uops_2_bits_out_uop_br_tag = uops_1_bits_uop_br_tag; // @[util.scala:109:23, :700:17]
reg [3:0] uops_1_bits_uop_br_type; // @[util.scala:700:17]
assign io_resp_1_bits_uop_br_type = uops_1_bits_uop_br_type; // @[util.scala:688:7, :700:17]
wire [3:0] uops_2_bits_out_uop_br_type = uops_1_bits_uop_br_type; // @[util.scala:109:23, :700:17]
reg uops_1_bits_uop_is_sfb; // @[util.scala:700:17]
assign io_resp_1_bits_uop_is_sfb = uops_1_bits_uop_is_sfb; // @[util.scala:688:7, :700:17]
wire uops_2_bits_out_uop_is_sfb = uops_1_bits_uop_is_sfb; // @[util.scala:109:23, :700:17]
reg uops_1_bits_uop_is_fence; // @[util.scala:700:17]
assign io_resp_1_bits_uop_is_fence = uops_1_bits_uop_is_fence; // @[util.scala:688:7, :700:17]
wire uops_2_bits_out_uop_is_fence = uops_1_bits_uop_is_fence; // @[util.scala:109:23, :700:17]
reg uops_1_bits_uop_is_fencei; // @[util.scala:700:17]
assign io_resp_1_bits_uop_is_fencei = uops_1_bits_uop_is_fencei; // @[util.scala:688:7, :700:17]
wire uops_2_bits_out_uop_is_fencei = uops_1_bits_uop_is_fencei; // @[util.scala:109:23, :700:17]
reg uops_1_bits_uop_is_sfence; // @[util.scala:700:17]
assign io_resp_1_bits_uop_is_sfence = uops_1_bits_uop_is_sfence; // @[util.scala:688:7, :700:17]
wire uops_2_bits_out_uop_is_sfence = uops_1_bits_uop_is_sfence; // @[util.scala:109:23, :700:17]
reg uops_1_bits_uop_is_amo; // @[util.scala:700:17]
assign io_resp_1_bits_uop_is_amo = uops_1_bits_uop_is_amo; // @[util.scala:688:7, :700:17]
wire uops_2_bits_out_uop_is_amo = uops_1_bits_uop_is_amo; // @[util.scala:109:23, :700:17]
reg uops_1_bits_uop_is_eret; // @[util.scala:700:17]
assign io_resp_1_bits_uop_is_eret = uops_1_bits_uop_is_eret; // @[util.scala:688:7, :700:17]
wire uops_2_bits_out_uop_is_eret = uops_1_bits_uop_is_eret; // @[util.scala:109:23, :700:17]
reg uops_1_bits_uop_is_sys_pc2epc; // @[util.scala:700:17]
assign io_resp_1_bits_uop_is_sys_pc2epc = uops_1_bits_uop_is_sys_pc2epc; // @[util.scala:688:7, :700:17]
wire uops_2_bits_out_uop_is_sys_pc2epc = uops_1_bits_uop_is_sys_pc2epc; // @[util.scala:109:23, :700:17]
reg uops_1_bits_uop_is_rocc; // @[util.scala:700:17]
assign io_resp_1_bits_uop_is_rocc = uops_1_bits_uop_is_rocc; // @[util.scala:688:7, :700:17]
wire uops_2_bits_out_uop_is_rocc = uops_1_bits_uop_is_rocc; // @[util.scala:109:23, :700:17]
reg uops_1_bits_uop_is_mov; // @[util.scala:700:17]
assign io_resp_1_bits_uop_is_mov = uops_1_bits_uop_is_mov; // @[util.scala:688:7, :700:17]
wire uops_2_bits_out_uop_is_mov = uops_1_bits_uop_is_mov; // @[util.scala:109:23, :700:17]
reg [4:0] uops_1_bits_uop_ftq_idx; // @[util.scala:700:17]
assign io_resp_1_bits_uop_ftq_idx = uops_1_bits_uop_ftq_idx; // @[util.scala:688:7, :700:17]
wire [4:0] uops_2_bits_out_uop_ftq_idx = uops_1_bits_uop_ftq_idx; // @[util.scala:109:23, :700:17]
reg uops_1_bits_uop_edge_inst; // @[util.scala:700:17]
assign io_resp_1_bits_uop_edge_inst = uops_1_bits_uop_edge_inst; // @[util.scala:688:7, :700:17]
wire uops_2_bits_out_uop_edge_inst = uops_1_bits_uop_edge_inst; // @[util.scala:109:23, :700:17]
reg [5:0] uops_1_bits_uop_pc_lob; // @[util.scala:700:17]
assign io_resp_1_bits_uop_pc_lob = uops_1_bits_uop_pc_lob; // @[util.scala:688:7, :700:17]
wire [5:0] uops_2_bits_out_uop_pc_lob = uops_1_bits_uop_pc_lob; // @[util.scala:109:23, :700:17]
reg uops_1_bits_uop_taken; // @[util.scala:700:17]
assign io_resp_1_bits_uop_taken = uops_1_bits_uop_taken; // @[util.scala:688:7, :700:17]
wire uops_2_bits_out_uop_taken = uops_1_bits_uop_taken; // @[util.scala:109:23, :700:17]
reg uops_1_bits_uop_imm_rename; // @[util.scala:700:17]
assign io_resp_1_bits_uop_imm_rename = uops_1_bits_uop_imm_rename; // @[util.scala:688:7, :700:17]
wire uops_2_bits_out_uop_imm_rename = uops_1_bits_uop_imm_rename; // @[util.scala:109:23, :700:17]
reg [2:0] uops_1_bits_uop_imm_sel; // @[util.scala:700:17]
assign io_resp_1_bits_uop_imm_sel = uops_1_bits_uop_imm_sel; // @[util.scala:688:7, :700:17]
wire [2:0] uops_2_bits_out_uop_imm_sel = uops_1_bits_uop_imm_sel; // @[util.scala:109:23, :700:17]
reg [4:0] uops_1_bits_uop_pimm; // @[util.scala:700:17]
assign io_resp_1_bits_uop_pimm = uops_1_bits_uop_pimm; // @[util.scala:688:7, :700:17]
wire [4:0] uops_2_bits_out_uop_pimm = uops_1_bits_uop_pimm; // @[util.scala:109:23, :700:17]
reg [19:0] uops_1_bits_uop_imm_packed; // @[util.scala:700:17]
assign io_resp_1_bits_uop_imm_packed = uops_1_bits_uop_imm_packed; // @[util.scala:688:7, :700:17]
wire [19:0] uops_2_bits_out_uop_imm_packed = uops_1_bits_uop_imm_packed; // @[util.scala:109:23, :700:17]
reg [1:0] uops_1_bits_uop_op1_sel; // @[util.scala:700:17]
assign io_resp_1_bits_uop_op1_sel = uops_1_bits_uop_op1_sel; // @[util.scala:688:7, :700:17]
wire [1:0] uops_2_bits_out_uop_op1_sel = uops_1_bits_uop_op1_sel; // @[util.scala:109:23, :700:17]
reg [2:0] uops_1_bits_uop_op2_sel; // @[util.scala:700:17]
assign io_resp_1_bits_uop_op2_sel = uops_1_bits_uop_op2_sel; // @[util.scala:688:7, :700:17]
wire [2:0] uops_2_bits_out_uop_op2_sel = uops_1_bits_uop_op2_sel; // @[util.scala:109:23, :700:17]
reg uops_1_bits_uop_fp_ctrl_ldst; // @[util.scala:700:17]
assign io_resp_1_bits_uop_fp_ctrl_ldst = uops_1_bits_uop_fp_ctrl_ldst; // @[util.scala:688:7, :700:17]
wire uops_2_bits_out_uop_fp_ctrl_ldst = uops_1_bits_uop_fp_ctrl_ldst; // @[util.scala:109:23, :700:17]
reg uops_1_bits_uop_fp_ctrl_wen; // @[util.scala:700:17]
assign io_resp_1_bits_uop_fp_ctrl_wen = uops_1_bits_uop_fp_ctrl_wen; // @[util.scala:688:7, :700:17]
wire uops_2_bits_out_uop_fp_ctrl_wen = uops_1_bits_uop_fp_ctrl_wen; // @[util.scala:109:23, :700:17]
reg uops_1_bits_uop_fp_ctrl_ren1; // @[util.scala:700:17]
assign io_resp_1_bits_uop_fp_ctrl_ren1 = uops_1_bits_uop_fp_ctrl_ren1; // @[util.scala:688:7, :700:17]
wire uops_2_bits_out_uop_fp_ctrl_ren1 = uops_1_bits_uop_fp_ctrl_ren1; // @[util.scala:109:23, :700:17]
reg uops_1_bits_uop_fp_ctrl_ren2; // @[util.scala:700:17]
assign io_resp_1_bits_uop_fp_ctrl_ren2 = uops_1_bits_uop_fp_ctrl_ren2; // @[util.scala:688:7, :700:17]
wire uops_2_bits_out_uop_fp_ctrl_ren2 = uops_1_bits_uop_fp_ctrl_ren2; // @[util.scala:109:23, :700:17]
reg uops_1_bits_uop_fp_ctrl_ren3; // @[util.scala:700:17]
assign io_resp_1_bits_uop_fp_ctrl_ren3 = uops_1_bits_uop_fp_ctrl_ren3; // @[util.scala:688:7, :700:17]
wire uops_2_bits_out_uop_fp_ctrl_ren3 = uops_1_bits_uop_fp_ctrl_ren3; // @[util.scala:109:23, :700:17]
reg uops_1_bits_uop_fp_ctrl_swap12; // @[util.scala:700:17]
assign io_resp_1_bits_uop_fp_ctrl_swap12 = uops_1_bits_uop_fp_ctrl_swap12; // @[util.scala:688:7, :700:17]
wire uops_2_bits_out_uop_fp_ctrl_swap12 = uops_1_bits_uop_fp_ctrl_swap12; // @[util.scala:109:23, :700:17]
reg uops_1_bits_uop_fp_ctrl_swap23; // @[util.scala:700:17]
assign io_resp_1_bits_uop_fp_ctrl_swap23 = uops_1_bits_uop_fp_ctrl_swap23; // @[util.scala:688:7, :700:17]
wire uops_2_bits_out_uop_fp_ctrl_swap23 = uops_1_bits_uop_fp_ctrl_swap23; // @[util.scala:109:23, :700:17]
reg [1:0] uops_1_bits_uop_fp_ctrl_typeTagIn; // @[util.scala:700:17]
assign io_resp_1_bits_uop_fp_ctrl_typeTagIn = uops_1_bits_uop_fp_ctrl_typeTagIn; // @[util.scala:688:7, :700:17]
wire [1:0] uops_2_bits_out_uop_fp_ctrl_typeTagIn = uops_1_bits_uop_fp_ctrl_typeTagIn; // @[util.scala:109:23, :700:17]
reg [1:0] uops_1_bits_uop_fp_ctrl_typeTagOut; // @[util.scala:700:17]
assign io_resp_1_bits_uop_fp_ctrl_typeTagOut = uops_1_bits_uop_fp_ctrl_typeTagOut; // @[util.scala:688:7, :700:17]
wire [1:0] uops_2_bits_out_uop_fp_ctrl_typeTagOut = uops_1_bits_uop_fp_ctrl_typeTagOut; // @[util.scala:109:23, :700:17]
reg uops_1_bits_uop_fp_ctrl_fromint; // @[util.scala:700:17]
assign io_resp_1_bits_uop_fp_ctrl_fromint = uops_1_bits_uop_fp_ctrl_fromint; // @[util.scala:688:7, :700:17]
wire uops_2_bits_out_uop_fp_ctrl_fromint = uops_1_bits_uop_fp_ctrl_fromint; // @[util.scala:109:23, :700:17]
reg uops_1_bits_uop_fp_ctrl_toint; // @[util.scala:700:17]
assign io_resp_1_bits_uop_fp_ctrl_toint = uops_1_bits_uop_fp_ctrl_toint; // @[util.scala:688:7, :700:17]
wire uops_2_bits_out_uop_fp_ctrl_toint = uops_1_bits_uop_fp_ctrl_toint; // @[util.scala:109:23, :700:17]
reg uops_1_bits_uop_fp_ctrl_fastpipe; // @[util.scala:700:17]
assign io_resp_1_bits_uop_fp_ctrl_fastpipe = uops_1_bits_uop_fp_ctrl_fastpipe; // @[util.scala:688:7, :700:17]
wire uops_2_bits_out_uop_fp_ctrl_fastpipe = uops_1_bits_uop_fp_ctrl_fastpipe; // @[util.scala:109:23, :700:17]
reg uops_1_bits_uop_fp_ctrl_fma; // @[util.scala:700:17]
assign io_resp_1_bits_uop_fp_ctrl_fma = uops_1_bits_uop_fp_ctrl_fma; // @[util.scala:688:7, :700:17]
wire uops_2_bits_out_uop_fp_ctrl_fma = uops_1_bits_uop_fp_ctrl_fma; // @[util.scala:109:23, :700:17]
reg uops_1_bits_uop_fp_ctrl_div; // @[util.scala:700:17]
assign io_resp_1_bits_uop_fp_ctrl_div = uops_1_bits_uop_fp_ctrl_div; // @[util.scala:688:7, :700:17]
wire uops_2_bits_out_uop_fp_ctrl_div = uops_1_bits_uop_fp_ctrl_div; // @[util.scala:109:23, :700:17]
reg uops_1_bits_uop_fp_ctrl_sqrt; // @[util.scala:700:17]
assign io_resp_1_bits_uop_fp_ctrl_sqrt = uops_1_bits_uop_fp_ctrl_sqrt; // @[util.scala:688:7, :700:17]
wire uops_2_bits_out_uop_fp_ctrl_sqrt = uops_1_bits_uop_fp_ctrl_sqrt; // @[util.scala:109:23, :700:17]
reg uops_1_bits_uop_fp_ctrl_wflags; // @[util.scala:700:17]
assign io_resp_1_bits_uop_fp_ctrl_wflags = uops_1_bits_uop_fp_ctrl_wflags; // @[util.scala:688:7, :700:17]
wire uops_2_bits_out_uop_fp_ctrl_wflags = uops_1_bits_uop_fp_ctrl_wflags; // @[util.scala:109:23, :700:17]
reg uops_1_bits_uop_fp_ctrl_vec; // @[util.scala:700:17]
assign io_resp_1_bits_uop_fp_ctrl_vec = uops_1_bits_uop_fp_ctrl_vec; // @[util.scala:688:7, :700:17]
wire uops_2_bits_out_uop_fp_ctrl_vec = uops_1_bits_uop_fp_ctrl_vec; // @[util.scala:109:23, :700:17]
reg [6:0] uops_1_bits_uop_rob_idx; // @[util.scala:700:17]
assign io_resp_1_bits_uop_rob_idx = uops_1_bits_uop_rob_idx; // @[util.scala:688:7, :700:17]
wire [6:0] uops_2_bits_out_uop_rob_idx = uops_1_bits_uop_rob_idx; // @[util.scala:109:23, :700:17]
reg [4:0] uops_1_bits_uop_ldq_idx; // @[util.scala:700:17]
assign io_resp_1_bits_uop_ldq_idx = uops_1_bits_uop_ldq_idx; // @[util.scala:688:7, :700:17]
wire [4:0] uops_2_bits_out_uop_ldq_idx = uops_1_bits_uop_ldq_idx; // @[util.scala:109:23, :700:17]
reg [4:0] uops_1_bits_uop_stq_idx; // @[util.scala:700:17]
assign io_resp_1_bits_uop_stq_idx = uops_1_bits_uop_stq_idx; // @[util.scala:688:7, :700:17]
wire [4:0] uops_2_bits_out_uop_stq_idx = uops_1_bits_uop_stq_idx; // @[util.scala:109:23, :700:17]
reg [1:0] uops_1_bits_uop_rxq_idx; // @[util.scala:700:17]
assign io_resp_1_bits_uop_rxq_idx = uops_1_bits_uop_rxq_idx; // @[util.scala:688:7, :700:17]
wire [1:0] uops_2_bits_out_uop_rxq_idx = uops_1_bits_uop_rxq_idx; // @[util.scala:109:23, :700:17]
reg [6:0] uops_1_bits_uop_pdst; // @[util.scala:700:17]
assign io_resp_1_bits_uop_pdst = uops_1_bits_uop_pdst; // @[util.scala:688:7, :700:17]
wire [6:0] uops_2_bits_out_uop_pdst = uops_1_bits_uop_pdst; // @[util.scala:109:23, :700:17]
reg [6:0] uops_1_bits_uop_prs1; // @[util.scala:700:17]
assign io_resp_1_bits_uop_prs1 = uops_1_bits_uop_prs1; // @[util.scala:688:7, :700:17]
wire [6:0] uops_2_bits_out_uop_prs1 = uops_1_bits_uop_prs1; // @[util.scala:109:23, :700:17]
reg [6:0] uops_1_bits_uop_prs2; // @[util.scala:700:17]
assign io_resp_1_bits_uop_prs2 = uops_1_bits_uop_prs2; // @[util.scala:688:7, :700:17]
wire [6:0] uops_2_bits_out_uop_prs2 = uops_1_bits_uop_prs2; // @[util.scala:109:23, :700:17]
reg [6:0] uops_1_bits_uop_prs3; // @[util.scala:700:17]
assign io_resp_1_bits_uop_prs3 = uops_1_bits_uop_prs3; // @[util.scala:688:7, :700:17]
wire [6:0] uops_2_bits_out_uop_prs3 = uops_1_bits_uop_prs3; // @[util.scala:109:23, :700:17]
reg [4:0] uops_1_bits_uop_ppred; // @[util.scala:700:17]
assign io_resp_1_bits_uop_ppred = uops_1_bits_uop_ppred; // @[util.scala:688:7, :700:17]
wire [4:0] uops_2_bits_out_uop_ppred = uops_1_bits_uop_ppred; // @[util.scala:109:23, :700:17]
reg uops_1_bits_uop_prs1_busy; // @[util.scala:700:17]
assign io_resp_1_bits_uop_prs1_busy = uops_1_bits_uop_prs1_busy; // @[util.scala:688:7, :700:17]
wire uops_2_bits_out_uop_prs1_busy = uops_1_bits_uop_prs1_busy; // @[util.scala:109:23, :700:17]
reg uops_1_bits_uop_prs2_busy; // @[util.scala:700:17]
assign io_resp_1_bits_uop_prs2_busy = uops_1_bits_uop_prs2_busy; // @[util.scala:688:7, :700:17]
wire uops_2_bits_out_uop_prs2_busy = uops_1_bits_uop_prs2_busy; // @[util.scala:109:23, :700:17]
reg uops_1_bits_uop_prs3_busy; // @[util.scala:700:17]
assign io_resp_1_bits_uop_prs3_busy = uops_1_bits_uop_prs3_busy; // @[util.scala:688:7, :700:17]
wire uops_2_bits_out_uop_prs3_busy = uops_1_bits_uop_prs3_busy; // @[util.scala:109:23, :700:17]
reg uops_1_bits_uop_ppred_busy; // @[util.scala:700:17]
assign io_resp_1_bits_uop_ppred_busy = uops_1_bits_uop_ppred_busy; // @[util.scala:688:7, :700:17]
wire uops_2_bits_out_uop_ppred_busy = uops_1_bits_uop_ppred_busy; // @[util.scala:109:23, :700:17]
reg [6:0] uops_1_bits_uop_stale_pdst; // @[util.scala:700:17]
assign io_resp_1_bits_uop_stale_pdst = uops_1_bits_uop_stale_pdst; // @[util.scala:688:7, :700:17]
wire [6:0] uops_2_bits_out_uop_stale_pdst = uops_1_bits_uop_stale_pdst; // @[util.scala:109:23, :700:17]
reg uops_1_bits_uop_exception; // @[util.scala:700:17]
assign io_resp_1_bits_uop_exception = uops_1_bits_uop_exception; // @[util.scala:688:7, :700:17]
wire uops_2_bits_out_uop_exception = uops_1_bits_uop_exception; // @[util.scala:109:23, :700:17]
reg [63:0] uops_1_bits_uop_exc_cause; // @[util.scala:700:17]
assign io_resp_1_bits_uop_exc_cause = uops_1_bits_uop_exc_cause; // @[util.scala:688:7, :700:17]
wire [63:0] uops_2_bits_out_uop_exc_cause = uops_1_bits_uop_exc_cause; // @[util.scala:109:23, :700:17]
reg [4:0] uops_1_bits_uop_mem_cmd; // @[util.scala:700:17]
assign io_resp_1_bits_uop_mem_cmd = uops_1_bits_uop_mem_cmd; // @[util.scala:688:7, :700:17]
wire [4:0] uops_2_bits_out_uop_mem_cmd = uops_1_bits_uop_mem_cmd; // @[util.scala:109:23, :700:17]
reg [1:0] uops_1_bits_uop_mem_size; // @[util.scala:700:17]
assign io_resp_1_bits_uop_mem_size = uops_1_bits_uop_mem_size; // @[util.scala:688:7, :700:17]
wire [1:0] uops_2_bits_out_uop_mem_size = uops_1_bits_uop_mem_size; // @[util.scala:109:23, :700:17]
reg uops_1_bits_uop_mem_signed; // @[util.scala:700:17]
assign io_resp_1_bits_uop_mem_signed = uops_1_bits_uop_mem_signed; // @[util.scala:688:7, :700:17]
wire uops_2_bits_out_uop_mem_signed = uops_1_bits_uop_mem_signed; // @[util.scala:109:23, :700:17]
reg uops_1_bits_uop_uses_ldq; // @[util.scala:700:17]
assign io_resp_1_bits_uop_uses_ldq = uops_1_bits_uop_uses_ldq; // @[util.scala:688:7, :700:17]
wire uops_2_bits_out_uop_uses_ldq = uops_1_bits_uop_uses_ldq; // @[util.scala:109:23, :700:17]
reg uops_1_bits_uop_uses_stq; // @[util.scala:700:17]
assign io_resp_1_bits_uop_uses_stq = uops_1_bits_uop_uses_stq; // @[util.scala:688:7, :700:17]
wire uops_2_bits_out_uop_uses_stq = uops_1_bits_uop_uses_stq; // @[util.scala:109:23, :700:17]
reg uops_1_bits_uop_is_unique; // @[util.scala:700:17]
assign io_resp_1_bits_uop_is_unique = uops_1_bits_uop_is_unique; // @[util.scala:688:7, :700:17]
wire uops_2_bits_out_uop_is_unique = uops_1_bits_uop_is_unique; // @[util.scala:109:23, :700:17]
reg uops_1_bits_uop_flush_on_commit; // @[util.scala:700:17]
assign io_resp_1_bits_uop_flush_on_commit = uops_1_bits_uop_flush_on_commit; // @[util.scala:688:7, :700:17]
wire uops_2_bits_out_uop_flush_on_commit = uops_1_bits_uop_flush_on_commit; // @[util.scala:109:23, :700:17]
reg [2:0] uops_1_bits_uop_csr_cmd; // @[util.scala:700:17]
assign io_resp_1_bits_uop_csr_cmd = uops_1_bits_uop_csr_cmd; // @[util.scala:688:7, :700:17]
wire [2:0] uops_2_bits_out_uop_csr_cmd = uops_1_bits_uop_csr_cmd; // @[util.scala:109:23, :700:17]
reg uops_1_bits_uop_ldst_is_rs1; // @[util.scala:700:17]
assign io_resp_1_bits_uop_ldst_is_rs1 = uops_1_bits_uop_ldst_is_rs1; // @[util.scala:688:7, :700:17]
wire uops_2_bits_out_uop_ldst_is_rs1 = uops_1_bits_uop_ldst_is_rs1; // @[util.scala:109:23, :700:17]
reg [5:0] uops_1_bits_uop_ldst; // @[util.scala:700:17]
assign io_resp_1_bits_uop_ldst = uops_1_bits_uop_ldst; // @[util.scala:688:7, :700:17]
wire [5:0] uops_2_bits_out_uop_ldst = uops_1_bits_uop_ldst; // @[util.scala:109:23, :700:17]
reg [5:0] uops_1_bits_uop_lrs1; // @[util.scala:700:17]
assign io_resp_1_bits_uop_lrs1 = uops_1_bits_uop_lrs1; // @[util.scala:688:7, :700:17]
wire [5:0] uops_2_bits_out_uop_lrs1 = uops_1_bits_uop_lrs1; // @[util.scala:109:23, :700:17]
reg [5:0] uops_1_bits_uop_lrs2; // @[util.scala:700:17]
assign io_resp_1_bits_uop_lrs2 = uops_1_bits_uop_lrs2; // @[util.scala:688:7, :700:17]
wire [5:0] uops_2_bits_out_uop_lrs2 = uops_1_bits_uop_lrs2; // @[util.scala:109:23, :700:17]
reg [5:0] uops_1_bits_uop_lrs3; // @[util.scala:700:17]
assign io_resp_1_bits_uop_lrs3 = uops_1_bits_uop_lrs3; // @[util.scala:688:7, :700:17]
wire [5:0] uops_2_bits_out_uop_lrs3 = uops_1_bits_uop_lrs3; // @[util.scala:109:23, :700:17]
reg [1:0] uops_1_bits_uop_dst_rtype; // @[util.scala:700:17]
assign io_resp_1_bits_uop_dst_rtype = uops_1_bits_uop_dst_rtype; // @[util.scala:688:7, :700:17]
wire [1:0] uops_2_bits_out_uop_dst_rtype = uops_1_bits_uop_dst_rtype; // @[util.scala:109:23, :700:17]
reg [1:0] uops_1_bits_uop_lrs1_rtype; // @[util.scala:700:17]
assign io_resp_1_bits_uop_lrs1_rtype = uops_1_bits_uop_lrs1_rtype; // @[util.scala:688:7, :700:17]
wire [1:0] uops_2_bits_out_uop_lrs1_rtype = uops_1_bits_uop_lrs1_rtype; // @[util.scala:109:23, :700:17]
reg [1:0] uops_1_bits_uop_lrs2_rtype; // @[util.scala:700:17]
assign io_resp_1_bits_uop_lrs2_rtype = uops_1_bits_uop_lrs2_rtype; // @[util.scala:688:7, :700:17]
wire [1:0] uops_2_bits_out_uop_lrs2_rtype = uops_1_bits_uop_lrs2_rtype; // @[util.scala:109:23, :700:17]
reg uops_1_bits_uop_frs3_en; // @[util.scala:700:17]
assign io_resp_1_bits_uop_frs3_en = uops_1_bits_uop_frs3_en; // @[util.scala:688:7, :700:17]
wire uops_2_bits_out_uop_frs3_en = uops_1_bits_uop_frs3_en; // @[util.scala:109:23, :700:17]
reg uops_1_bits_uop_fcn_dw; // @[util.scala:700:17]
assign io_resp_1_bits_uop_fcn_dw = uops_1_bits_uop_fcn_dw; // @[util.scala:688:7, :700:17]
wire uops_2_bits_out_uop_fcn_dw = uops_1_bits_uop_fcn_dw; // @[util.scala:109:23, :700:17]
reg [4:0] uops_1_bits_uop_fcn_op; // @[util.scala:700:17]
assign io_resp_1_bits_uop_fcn_op = uops_1_bits_uop_fcn_op; // @[util.scala:688:7, :700:17]
wire [4:0] uops_2_bits_out_uop_fcn_op = uops_1_bits_uop_fcn_op; // @[util.scala:109:23, :700:17]
reg uops_1_bits_uop_fp_val; // @[util.scala:700:17]
assign io_resp_1_bits_uop_fp_val = uops_1_bits_uop_fp_val; // @[util.scala:688:7, :700:17]
wire uops_2_bits_out_uop_fp_val = uops_1_bits_uop_fp_val; // @[util.scala:109:23, :700:17]
reg [2:0] uops_1_bits_uop_fp_rm; // @[util.scala:700:17]
assign io_resp_1_bits_uop_fp_rm = uops_1_bits_uop_fp_rm; // @[util.scala:688:7, :700:17]
wire [2:0] uops_2_bits_out_uop_fp_rm = uops_1_bits_uop_fp_rm; // @[util.scala:109:23, :700:17]
reg [1:0] uops_1_bits_uop_fp_typ; // @[util.scala:700:17]
assign io_resp_1_bits_uop_fp_typ = uops_1_bits_uop_fp_typ; // @[util.scala:688:7, :700:17]
wire [1:0] uops_2_bits_out_uop_fp_typ = uops_1_bits_uop_fp_typ; // @[util.scala:109:23, :700:17]
reg uops_1_bits_uop_xcpt_pf_if; // @[util.scala:700:17]
assign io_resp_1_bits_uop_xcpt_pf_if = uops_1_bits_uop_xcpt_pf_if; // @[util.scala:688:7, :700:17]
wire uops_2_bits_out_uop_xcpt_pf_if = uops_1_bits_uop_xcpt_pf_if; // @[util.scala:109:23, :700:17]
reg uops_1_bits_uop_xcpt_ae_if; // @[util.scala:700:17]
assign io_resp_1_bits_uop_xcpt_ae_if = uops_1_bits_uop_xcpt_ae_if; // @[util.scala:688:7, :700:17]
wire uops_2_bits_out_uop_xcpt_ae_if = uops_1_bits_uop_xcpt_ae_if; // @[util.scala:109:23, :700:17]
reg uops_1_bits_uop_xcpt_ma_if; // @[util.scala:700:17]
assign io_resp_1_bits_uop_xcpt_ma_if = uops_1_bits_uop_xcpt_ma_if; // @[util.scala:688:7, :700:17]
wire uops_2_bits_out_uop_xcpt_ma_if = uops_1_bits_uop_xcpt_ma_if; // @[util.scala:109:23, :700:17]
reg uops_1_bits_uop_bp_debug_if; // @[util.scala:700:17]
assign io_resp_1_bits_uop_bp_debug_if = uops_1_bits_uop_bp_debug_if; // @[util.scala:688:7, :700:17]
wire uops_2_bits_out_uop_bp_debug_if = uops_1_bits_uop_bp_debug_if; // @[util.scala:109:23, :700:17]
reg uops_1_bits_uop_bp_xcpt_if; // @[util.scala:700:17]
assign io_resp_1_bits_uop_bp_xcpt_if = uops_1_bits_uop_bp_xcpt_if; // @[util.scala:688:7, :700:17]
wire uops_2_bits_out_uop_bp_xcpt_if = uops_1_bits_uop_bp_xcpt_if; // @[util.scala:109:23, :700:17]
reg [2:0] uops_1_bits_uop_debug_fsrc; // @[util.scala:700:17]
assign io_resp_1_bits_uop_debug_fsrc = uops_1_bits_uop_debug_fsrc; // @[util.scala:688:7, :700:17]
wire [2:0] uops_2_bits_out_uop_debug_fsrc = uops_1_bits_uop_debug_fsrc; // @[util.scala:109:23, :700:17]
reg [2:0] uops_1_bits_uop_debug_tsrc; // @[util.scala:700:17]
assign io_resp_1_bits_uop_debug_tsrc = uops_1_bits_uop_debug_tsrc; // @[util.scala:688:7, :700:17]
wire [2:0] uops_2_bits_out_uop_debug_tsrc = uops_1_bits_uop_debug_tsrc; // @[util.scala:109:23, :700:17]
reg [63:0] uops_1_bits_rs1_data; // @[util.scala:700:17]
assign io_resp_1_bits_rs1_data = uops_1_bits_rs1_data; // @[util.scala:688:7, :700:17]
wire [63:0] uops_2_bits_out_rs1_data = uops_1_bits_rs1_data; // @[util.scala:109:23, :700:17]
reg [63:0] uops_1_bits_rs2_data; // @[util.scala:700:17]
assign io_resp_1_bits_rs2_data = uops_1_bits_rs2_data; // @[util.scala:688:7, :700:17]
wire [63:0] uops_2_bits_out_rs2_data = uops_1_bits_rs2_data; // @[util.scala:109:23, :700:17]
reg [63:0] uops_1_bits_rs3_data; // @[util.scala:700:17]
assign io_resp_1_bits_rs3_data = uops_1_bits_rs3_data; // @[util.scala:688:7, :700:17]
wire [63:0] uops_2_bits_out_rs3_data = uops_1_bits_rs3_data; // @[util.scala:109:23, :700:17]
reg uops_1_bits_ftq_info_0_valid; // @[util.scala:700:17]
assign io_resp_1_bits_ftq_info_0_valid = uops_1_bits_ftq_info_0_valid; // @[util.scala:688:7, :700:17]
wire uops_2_bits_out_ftq_info_0_valid = uops_1_bits_ftq_info_0_valid; // @[util.scala:109:23, :700:17]
reg uops_1_bits_ftq_info_0_entry_cfi_idx_valid; // @[util.scala:700:17]
assign io_resp_1_bits_ftq_info_0_entry_cfi_idx_valid = uops_1_bits_ftq_info_0_entry_cfi_idx_valid; // @[util.scala:688:7, :700:17]
wire uops_2_bits_out_ftq_info_0_entry_cfi_idx_valid = uops_1_bits_ftq_info_0_entry_cfi_idx_valid; // @[util.scala:109:23, :700:17]
reg [2:0] uops_1_bits_ftq_info_0_entry_cfi_idx_bits; // @[util.scala:700:17]
assign io_resp_1_bits_ftq_info_0_entry_cfi_idx_bits = uops_1_bits_ftq_info_0_entry_cfi_idx_bits; // @[util.scala:688:7, :700:17]
wire [2:0] uops_2_bits_out_ftq_info_0_entry_cfi_idx_bits = uops_1_bits_ftq_info_0_entry_cfi_idx_bits; // @[util.scala:109:23, :700:17]
reg uops_1_bits_ftq_info_0_entry_cfi_taken; // @[util.scala:700:17]
assign io_resp_1_bits_ftq_info_0_entry_cfi_taken = uops_1_bits_ftq_info_0_entry_cfi_taken; // @[util.scala:688:7, :700:17]
wire uops_2_bits_out_ftq_info_0_entry_cfi_taken = uops_1_bits_ftq_info_0_entry_cfi_taken; // @[util.scala:109:23, :700:17]
reg uops_1_bits_ftq_info_0_entry_cfi_mispredicted; // @[util.scala:700:17]
assign io_resp_1_bits_ftq_info_0_entry_cfi_mispredicted = uops_1_bits_ftq_info_0_entry_cfi_mispredicted; // @[util.scala:688:7, :700:17]
wire uops_2_bits_out_ftq_info_0_entry_cfi_mispredicted = uops_1_bits_ftq_info_0_entry_cfi_mispredicted; // @[util.scala:109:23, :700:17]
reg [2:0] uops_1_bits_ftq_info_0_entry_cfi_type; // @[util.scala:700:17]
assign io_resp_1_bits_ftq_info_0_entry_cfi_type = uops_1_bits_ftq_info_0_entry_cfi_type; // @[util.scala:688:7, :700:17]
wire [2:0] uops_2_bits_out_ftq_info_0_entry_cfi_type = uops_1_bits_ftq_info_0_entry_cfi_type; // @[util.scala:109:23, :700:17]
reg [7:0] uops_1_bits_ftq_info_0_entry_br_mask; // @[util.scala:700:17]
assign io_resp_1_bits_ftq_info_0_entry_br_mask = uops_1_bits_ftq_info_0_entry_br_mask; // @[util.scala:688:7, :700:17]
wire [7:0] uops_2_bits_out_ftq_info_0_entry_br_mask = uops_1_bits_ftq_info_0_entry_br_mask; // @[util.scala:109:23, :700:17]
reg uops_1_bits_ftq_info_0_entry_cfi_is_call; // @[util.scala:700:17]
assign io_resp_1_bits_ftq_info_0_entry_cfi_is_call = uops_1_bits_ftq_info_0_entry_cfi_is_call; // @[util.scala:688:7, :700:17]
wire uops_2_bits_out_ftq_info_0_entry_cfi_is_call = uops_1_bits_ftq_info_0_entry_cfi_is_call; // @[util.scala:109:23, :700:17]
reg uops_1_bits_ftq_info_0_entry_cfi_is_ret; // @[util.scala:700:17]
assign io_resp_1_bits_ftq_info_0_entry_cfi_is_ret = uops_1_bits_ftq_info_0_entry_cfi_is_ret; // @[util.scala:688:7, :700:17]
wire uops_2_bits_out_ftq_info_0_entry_cfi_is_ret = uops_1_bits_ftq_info_0_entry_cfi_is_ret; // @[util.scala:109:23, :700:17]
reg uops_1_bits_ftq_info_0_entry_cfi_npc_plus4; // @[util.scala:700:17]
assign io_resp_1_bits_ftq_info_0_entry_cfi_npc_plus4 = uops_1_bits_ftq_info_0_entry_cfi_npc_plus4; // @[util.scala:688:7, :700:17]
wire uops_2_bits_out_ftq_info_0_entry_cfi_npc_plus4 = uops_1_bits_ftq_info_0_entry_cfi_npc_plus4; // @[util.scala:109:23, :700:17]
reg [39:0] uops_1_bits_ftq_info_0_entry_ras_top; // @[util.scala:700:17]
assign io_resp_1_bits_ftq_info_0_entry_ras_top = uops_1_bits_ftq_info_0_entry_ras_top; // @[util.scala:688:7, :700:17]
wire [39:0] uops_2_bits_out_ftq_info_0_entry_ras_top = uops_1_bits_ftq_info_0_entry_ras_top; // @[util.scala:109:23, :700:17]
reg [4:0] uops_1_bits_ftq_info_0_entry_ras_idx; // @[util.scala:700:17]
assign io_resp_1_bits_ftq_info_0_entry_ras_idx = uops_1_bits_ftq_info_0_entry_ras_idx; // @[util.scala:688:7, :700:17]
wire [4:0] uops_2_bits_out_ftq_info_0_entry_ras_idx = uops_1_bits_ftq_info_0_entry_ras_idx; // @[util.scala:109:23, :700:17]
reg uops_1_bits_ftq_info_0_entry_start_bank; // @[util.scala:700:17]
assign io_resp_1_bits_ftq_info_0_entry_start_bank = uops_1_bits_ftq_info_0_entry_start_bank; // @[util.scala:688:7, :700:17]
wire uops_2_bits_out_ftq_info_0_entry_start_bank = uops_1_bits_ftq_info_0_entry_start_bank; // @[util.scala:109:23, :700:17]
reg [63:0] uops_1_bits_ftq_info_0_ghist_old_history; // @[util.scala:700:17]
assign io_resp_1_bits_ftq_info_0_ghist_old_history = uops_1_bits_ftq_info_0_ghist_old_history; // @[util.scala:688:7, :700:17]
wire [63:0] uops_2_bits_out_ftq_info_0_ghist_old_history = uops_1_bits_ftq_info_0_ghist_old_history; // @[util.scala:109:23, :700:17]
reg uops_1_bits_ftq_info_0_ghist_current_saw_branch_not_taken; // @[util.scala:700:17]
assign io_resp_1_bits_ftq_info_0_ghist_current_saw_branch_not_taken = uops_1_bits_ftq_info_0_ghist_current_saw_branch_not_taken; // @[util.scala:688:7, :700:17]
wire uops_2_bits_out_ftq_info_0_ghist_current_saw_branch_not_taken = uops_1_bits_ftq_info_0_ghist_current_saw_branch_not_taken; // @[util.scala:109:23, :700:17]
reg uops_1_bits_ftq_info_0_ghist_new_saw_branch_not_taken; // @[util.scala:700:17]
assign io_resp_1_bits_ftq_info_0_ghist_new_saw_branch_not_taken = uops_1_bits_ftq_info_0_ghist_new_saw_branch_not_taken; // @[util.scala:688:7, :700:17]
wire uops_2_bits_out_ftq_info_0_ghist_new_saw_branch_not_taken = uops_1_bits_ftq_info_0_ghist_new_saw_branch_not_taken; // @[util.scala:109:23, :700:17]
reg uops_1_bits_ftq_info_0_ghist_new_saw_branch_taken; // @[util.scala:700:17]
assign io_resp_1_bits_ftq_info_0_ghist_new_saw_branch_taken = uops_1_bits_ftq_info_0_ghist_new_saw_branch_taken; // @[util.scala:688:7, :700:17]
wire uops_2_bits_out_ftq_info_0_ghist_new_saw_branch_taken = uops_1_bits_ftq_info_0_ghist_new_saw_branch_taken; // @[util.scala:109:23, :700:17]
reg [4:0] uops_1_bits_ftq_info_0_ghist_ras_idx; // @[util.scala:700:17]
assign io_resp_1_bits_ftq_info_0_ghist_ras_idx = uops_1_bits_ftq_info_0_ghist_ras_idx; // @[util.scala:688:7, :700:17]
wire [4:0] uops_2_bits_out_ftq_info_0_ghist_ras_idx = uops_1_bits_ftq_info_0_ghist_ras_idx; // @[util.scala:109:23, :700:17]
reg [39:0] uops_1_bits_ftq_info_0_pc; // @[util.scala:700:17]
assign io_resp_1_bits_ftq_info_0_pc = uops_1_bits_ftq_info_0_pc; // @[util.scala:688:7, :700:17]
wire [39:0] uops_2_bits_out_ftq_info_0_pc = uops_1_bits_ftq_info_0_pc; // @[util.scala:109:23, :700:17]
reg uops_1_bits_ftq_info_1_valid; // @[util.scala:700:17]
assign io_resp_1_bits_ftq_info_1_valid = uops_1_bits_ftq_info_1_valid; // @[util.scala:688:7, :700:17]
wire uops_2_bits_out_ftq_info_1_valid = uops_1_bits_ftq_info_1_valid; // @[util.scala:109:23, :700:17]
reg uops_1_bits_ftq_info_1_entry_cfi_idx_valid; // @[util.scala:700:17]
assign io_resp_1_bits_ftq_info_1_entry_cfi_idx_valid = uops_1_bits_ftq_info_1_entry_cfi_idx_valid; // @[util.scala:688:7, :700:17]
wire uops_2_bits_out_ftq_info_1_entry_cfi_idx_valid = uops_1_bits_ftq_info_1_entry_cfi_idx_valid; // @[util.scala:109:23, :700:17]
reg [2:0] uops_1_bits_ftq_info_1_entry_cfi_idx_bits; // @[util.scala:700:17]
assign io_resp_1_bits_ftq_info_1_entry_cfi_idx_bits = uops_1_bits_ftq_info_1_entry_cfi_idx_bits; // @[util.scala:688:7, :700:17]
wire [2:0] uops_2_bits_out_ftq_info_1_entry_cfi_idx_bits = uops_1_bits_ftq_info_1_entry_cfi_idx_bits; // @[util.scala:109:23, :700:17]
reg uops_1_bits_ftq_info_1_entry_cfi_taken; // @[util.scala:700:17]
assign io_resp_1_bits_ftq_info_1_entry_cfi_taken = uops_1_bits_ftq_info_1_entry_cfi_taken; // @[util.scala:688:7, :700:17]
wire uops_2_bits_out_ftq_info_1_entry_cfi_taken = uops_1_bits_ftq_info_1_entry_cfi_taken; // @[util.scala:109:23, :700:17]
reg uops_1_bits_ftq_info_1_entry_cfi_mispredicted; // @[util.scala:700:17]
assign io_resp_1_bits_ftq_info_1_entry_cfi_mispredicted = uops_1_bits_ftq_info_1_entry_cfi_mispredicted; // @[util.scala:688:7, :700:17]
wire uops_2_bits_out_ftq_info_1_entry_cfi_mispredicted = uops_1_bits_ftq_info_1_entry_cfi_mispredicted; // @[util.scala:109:23, :700:17]
reg [2:0] uops_1_bits_ftq_info_1_entry_cfi_type; // @[util.scala:700:17]
assign io_resp_1_bits_ftq_info_1_entry_cfi_type = uops_1_bits_ftq_info_1_entry_cfi_type; // @[util.scala:688:7, :700:17]
wire [2:0] uops_2_bits_out_ftq_info_1_entry_cfi_type = uops_1_bits_ftq_info_1_entry_cfi_type; // @[util.scala:109:23, :700:17]
reg [7:0] uops_1_bits_ftq_info_1_entry_br_mask; // @[util.scala:700:17]
assign io_resp_1_bits_ftq_info_1_entry_br_mask = uops_1_bits_ftq_info_1_entry_br_mask; // @[util.scala:688:7, :700:17]
wire [7:0] uops_2_bits_out_ftq_info_1_entry_br_mask = uops_1_bits_ftq_info_1_entry_br_mask; // @[util.scala:109:23, :700:17]
reg uops_1_bits_ftq_info_1_entry_cfi_is_call; // @[util.scala:700:17]
assign io_resp_1_bits_ftq_info_1_entry_cfi_is_call = uops_1_bits_ftq_info_1_entry_cfi_is_call; // @[util.scala:688:7, :700:17]
wire uops_2_bits_out_ftq_info_1_entry_cfi_is_call = uops_1_bits_ftq_info_1_entry_cfi_is_call; // @[util.scala:109:23, :700:17]
reg uops_1_bits_ftq_info_1_entry_cfi_is_ret; // @[util.scala:700:17]
assign io_resp_1_bits_ftq_info_1_entry_cfi_is_ret = uops_1_bits_ftq_info_1_entry_cfi_is_ret; // @[util.scala:688:7, :700:17]
wire uops_2_bits_out_ftq_info_1_entry_cfi_is_ret = uops_1_bits_ftq_info_1_entry_cfi_is_ret; // @[util.scala:109:23, :700:17]
reg uops_1_bits_ftq_info_1_entry_cfi_npc_plus4; // @[util.scala:700:17]
assign io_resp_1_bits_ftq_info_1_entry_cfi_npc_plus4 = uops_1_bits_ftq_info_1_entry_cfi_npc_plus4; // @[util.scala:688:7, :700:17]
wire uops_2_bits_out_ftq_info_1_entry_cfi_npc_plus4 = uops_1_bits_ftq_info_1_entry_cfi_npc_plus4; // @[util.scala:109:23, :700:17]
reg [39:0] uops_1_bits_ftq_info_1_entry_ras_top; // @[util.scala:700:17]
assign io_resp_1_bits_ftq_info_1_entry_ras_top = uops_1_bits_ftq_info_1_entry_ras_top; // @[util.scala:688:7, :700:17]
wire [39:0] uops_2_bits_out_ftq_info_1_entry_ras_top = uops_1_bits_ftq_info_1_entry_ras_top; // @[util.scala:109:23, :700:17]
reg [4:0] uops_1_bits_ftq_info_1_entry_ras_idx; // @[util.scala:700:17]
assign io_resp_1_bits_ftq_info_1_entry_ras_idx = uops_1_bits_ftq_info_1_entry_ras_idx; // @[util.scala:688:7, :700:17]
wire [4:0] uops_2_bits_out_ftq_info_1_entry_ras_idx = uops_1_bits_ftq_info_1_entry_ras_idx; // @[util.scala:109:23, :700:17]
reg uops_1_bits_ftq_info_1_entry_start_bank; // @[util.scala:700:17]
assign io_resp_1_bits_ftq_info_1_entry_start_bank = uops_1_bits_ftq_info_1_entry_start_bank; // @[util.scala:688:7, :700:17]
wire uops_2_bits_out_ftq_info_1_entry_start_bank = uops_1_bits_ftq_info_1_entry_start_bank; // @[util.scala:109:23, :700:17]
reg [63:0] uops_1_bits_ftq_info_1_ghist_old_history; // @[util.scala:700:17]
assign io_resp_1_bits_ftq_info_1_ghist_old_history = uops_1_bits_ftq_info_1_ghist_old_history; // @[util.scala:688:7, :700:17]
wire [63:0] uops_2_bits_out_ftq_info_1_ghist_old_history = uops_1_bits_ftq_info_1_ghist_old_history; // @[util.scala:109:23, :700:17]
reg uops_1_bits_ftq_info_1_ghist_current_saw_branch_not_taken; // @[util.scala:700:17]
assign io_resp_1_bits_ftq_info_1_ghist_current_saw_branch_not_taken = uops_1_bits_ftq_info_1_ghist_current_saw_branch_not_taken; // @[util.scala:688:7, :700:17]
wire uops_2_bits_out_ftq_info_1_ghist_current_saw_branch_not_taken = uops_1_bits_ftq_info_1_ghist_current_saw_branch_not_taken; // @[util.scala:109:23, :700:17]
reg uops_1_bits_ftq_info_1_ghist_new_saw_branch_not_taken; // @[util.scala:700:17]
assign io_resp_1_bits_ftq_info_1_ghist_new_saw_branch_not_taken = uops_1_bits_ftq_info_1_ghist_new_saw_branch_not_taken; // @[util.scala:688:7, :700:17]
wire uops_2_bits_out_ftq_info_1_ghist_new_saw_branch_not_taken = uops_1_bits_ftq_info_1_ghist_new_saw_branch_not_taken; // @[util.scala:109:23, :700:17]
reg uops_1_bits_ftq_info_1_ghist_new_saw_branch_taken; // @[util.scala:700:17]
assign io_resp_1_bits_ftq_info_1_ghist_new_saw_branch_taken = uops_1_bits_ftq_info_1_ghist_new_saw_branch_taken; // @[util.scala:688:7, :700:17]
wire uops_2_bits_out_ftq_info_1_ghist_new_saw_branch_taken = uops_1_bits_ftq_info_1_ghist_new_saw_branch_taken; // @[util.scala:109:23, :700:17]
reg [4:0] uops_1_bits_ftq_info_1_ghist_ras_idx; // @[util.scala:700:17]
assign io_resp_1_bits_ftq_info_1_ghist_ras_idx = uops_1_bits_ftq_info_1_ghist_ras_idx; // @[util.scala:688:7, :700:17]
wire [4:0] uops_2_bits_out_ftq_info_1_ghist_ras_idx = uops_1_bits_ftq_info_1_ghist_ras_idx; // @[util.scala:109:23, :700:17]
reg [39:0] uops_1_bits_ftq_info_1_pc; // @[util.scala:700:17]
assign io_resp_1_bits_ftq_info_1_pc = uops_1_bits_ftq_info_1_pc; // @[util.scala:688:7, :700:17]
wire [39:0] uops_2_bits_out_ftq_info_1_pc = uops_1_bits_ftq_info_1_pc; // @[util.scala:109:23, :700:17]
reg uops_1_bits_pred_data; // @[util.scala:700:17]
assign io_resp_1_bits_pred_data = uops_1_bits_pred_data; // @[util.scala:688:7, :700:17]
wire uops_2_bits_out_pred_data = uops_1_bits_pred_data; // @[util.scala:109:23, :700:17]
reg [63:0] uops_1_bits_imm_data; // @[util.scala:700:17]
assign io_resp_1_bits_imm_data = uops_1_bits_imm_data; // @[util.scala:688:7, :700:17]
wire [63:0] uops_2_bits_out_imm_data = uops_1_bits_imm_data; // @[util.scala:109:23, :700:17]
reg uops_2_valid; // @[util.scala:700:17]
assign io_resp_2_valid_0 = uops_2_valid; // @[util.scala:688:7, :700:17]
reg [31:0] uops_2_bits_uop_inst; // @[util.scala:700:17]
assign io_resp_2_bits_uop_inst_0 = uops_2_bits_uop_inst; // @[util.scala:688:7, :700:17]
reg [31:0] uops_2_bits_uop_debug_inst; // @[util.scala:700:17]
assign io_resp_2_bits_uop_debug_inst_0 = uops_2_bits_uop_debug_inst; // @[util.scala:688:7, :700:17]
reg uops_2_bits_uop_is_rvc; // @[util.scala:700:17]
assign io_resp_2_bits_uop_is_rvc_0 = uops_2_bits_uop_is_rvc; // @[util.scala:688:7, :700:17]
reg [39:0] uops_2_bits_uop_debug_pc; // @[util.scala:700:17]
assign io_resp_2_bits_uop_debug_pc_0 = uops_2_bits_uop_debug_pc; // @[util.scala:688:7, :700:17]
reg uops_2_bits_uop_iq_type_0; // @[util.scala:700:17]
assign io_resp_2_bits_uop_iq_type_0_0 = uops_2_bits_uop_iq_type_0; // @[util.scala:688:7, :700:17]
reg uops_2_bits_uop_iq_type_1; // @[util.scala:700:17]
assign io_resp_2_bits_uop_iq_type_1_0 = uops_2_bits_uop_iq_type_1; // @[util.scala:688:7, :700:17]
reg uops_2_bits_uop_iq_type_2; // @[util.scala:700:17]
assign io_resp_2_bits_uop_iq_type_2_0 = uops_2_bits_uop_iq_type_2; // @[util.scala:688:7, :700:17]
reg uops_2_bits_uop_iq_type_3; // @[util.scala:700:17]
assign io_resp_2_bits_uop_iq_type_3_0 = uops_2_bits_uop_iq_type_3; // @[util.scala:688:7, :700:17]
reg uops_2_bits_uop_fu_code_0; // @[util.scala:700:17]
assign io_resp_2_bits_uop_fu_code_0_0 = uops_2_bits_uop_fu_code_0; // @[util.scala:688:7, :700:17]
reg uops_2_bits_uop_fu_code_1; // @[util.scala:700:17]
assign io_resp_2_bits_uop_fu_code_1_0 = uops_2_bits_uop_fu_code_1; // @[util.scala:688:7, :700:17]
reg uops_2_bits_uop_fu_code_2; // @[util.scala:700:17]
assign io_resp_2_bits_uop_fu_code_2_0 = uops_2_bits_uop_fu_code_2; // @[util.scala:688:7, :700:17]
reg uops_2_bits_uop_fu_code_3; // @[util.scala:700:17]
assign io_resp_2_bits_uop_fu_code_3_0 = uops_2_bits_uop_fu_code_3; // @[util.scala:688:7, :700:17]
reg uops_2_bits_uop_fu_code_4; // @[util.scala:700:17]
assign io_resp_2_bits_uop_fu_code_4_0 = uops_2_bits_uop_fu_code_4; // @[util.scala:688:7, :700:17]
reg uops_2_bits_uop_fu_code_5; // @[util.scala:700:17]
assign io_resp_2_bits_uop_fu_code_5_0 = uops_2_bits_uop_fu_code_5; // @[util.scala:688:7, :700:17]
reg uops_2_bits_uop_fu_code_6; // @[util.scala:700:17]
assign io_resp_2_bits_uop_fu_code_6_0 = uops_2_bits_uop_fu_code_6; // @[util.scala:688:7, :700:17]
reg uops_2_bits_uop_fu_code_7; // @[util.scala:700:17]
assign io_resp_2_bits_uop_fu_code_7_0 = uops_2_bits_uop_fu_code_7; // @[util.scala:688:7, :700:17]
reg uops_2_bits_uop_fu_code_8; // @[util.scala:700:17]
assign io_resp_2_bits_uop_fu_code_8_0 = uops_2_bits_uop_fu_code_8; // @[util.scala:688:7, :700:17]
reg uops_2_bits_uop_fu_code_9; // @[util.scala:700:17]
assign io_resp_2_bits_uop_fu_code_9_0 = uops_2_bits_uop_fu_code_9; // @[util.scala:688:7, :700:17]
reg uops_2_bits_uop_iw_issued; // @[util.scala:700:17]
assign io_resp_2_bits_uop_iw_issued_0 = uops_2_bits_uop_iw_issued; // @[util.scala:688:7, :700:17]
reg uops_2_bits_uop_iw_issued_partial_agen; // @[util.scala:700:17]
assign io_resp_2_bits_uop_iw_issued_partial_agen_0 = uops_2_bits_uop_iw_issued_partial_agen; // @[util.scala:688:7, :700:17]
reg uops_2_bits_uop_iw_issued_partial_dgen; // @[util.scala:700:17]
assign io_resp_2_bits_uop_iw_issued_partial_dgen_0 = uops_2_bits_uop_iw_issued_partial_dgen; // @[util.scala:688:7, :700:17]
reg [2:0] uops_2_bits_uop_iw_p1_speculative_child; // @[util.scala:700:17]
assign io_resp_2_bits_uop_iw_p1_speculative_child_0 = uops_2_bits_uop_iw_p1_speculative_child; // @[util.scala:688:7, :700:17]
reg [2:0] uops_2_bits_uop_iw_p2_speculative_child; // @[util.scala:700:17]
assign io_resp_2_bits_uop_iw_p2_speculative_child_0 = uops_2_bits_uop_iw_p2_speculative_child; // @[util.scala:688:7, :700:17]
reg uops_2_bits_uop_iw_p1_bypass_hint; // @[util.scala:700:17]
assign io_resp_2_bits_uop_iw_p1_bypass_hint_0 = uops_2_bits_uop_iw_p1_bypass_hint; // @[util.scala:688:7, :700:17]
reg uops_2_bits_uop_iw_p2_bypass_hint; // @[util.scala:700:17]
assign io_resp_2_bits_uop_iw_p2_bypass_hint_0 = uops_2_bits_uop_iw_p2_bypass_hint; // @[util.scala:688:7, :700:17]
reg uops_2_bits_uop_iw_p3_bypass_hint; // @[util.scala:700:17]
assign io_resp_2_bits_uop_iw_p3_bypass_hint_0 = uops_2_bits_uop_iw_p3_bypass_hint; // @[util.scala:688:7, :700:17]
reg [2:0] uops_2_bits_uop_dis_col_sel; // @[util.scala:700:17]
assign io_resp_2_bits_uop_dis_col_sel_0 = uops_2_bits_uop_dis_col_sel; // @[util.scala:688:7, :700:17]
reg [15:0] uops_2_bits_uop_br_mask; // @[util.scala:700:17]
assign io_resp_2_bits_uop_br_mask_0 = uops_2_bits_uop_br_mask; // @[util.scala:688:7, :700:17]
reg [3:0] uops_2_bits_uop_br_tag; // @[util.scala:700:17]
assign io_resp_2_bits_uop_br_tag_0 = uops_2_bits_uop_br_tag; // @[util.scala:688:7, :700:17]
reg [3:0] uops_2_bits_uop_br_type; // @[util.scala:700:17]
assign io_resp_2_bits_uop_br_type_0 = uops_2_bits_uop_br_type; // @[util.scala:688:7, :700:17]
reg uops_2_bits_uop_is_sfb; // @[util.scala:700:17]
assign io_resp_2_bits_uop_is_sfb_0 = uops_2_bits_uop_is_sfb; // @[util.scala:688:7, :700:17]
reg uops_2_bits_uop_is_fence; // @[util.scala:700:17]
assign io_resp_2_bits_uop_is_fence_0 = uops_2_bits_uop_is_fence; // @[util.scala:688:7, :700:17]
reg uops_2_bits_uop_is_fencei; // @[util.scala:700:17]
assign io_resp_2_bits_uop_is_fencei_0 = uops_2_bits_uop_is_fencei; // @[util.scala:688:7, :700:17]
reg uops_2_bits_uop_is_sfence; // @[util.scala:700:17]
assign io_resp_2_bits_uop_is_sfence_0 = uops_2_bits_uop_is_sfence; // @[util.scala:688:7, :700:17]
reg uops_2_bits_uop_is_amo; // @[util.scala:700:17]
assign io_resp_2_bits_uop_is_amo_0 = uops_2_bits_uop_is_amo; // @[util.scala:688:7, :700:17]
reg uops_2_bits_uop_is_eret; // @[util.scala:700:17]
assign io_resp_2_bits_uop_is_eret_0 = uops_2_bits_uop_is_eret; // @[util.scala:688:7, :700:17]
reg uops_2_bits_uop_is_sys_pc2epc; // @[util.scala:700:17]
assign io_resp_2_bits_uop_is_sys_pc2epc_0 = uops_2_bits_uop_is_sys_pc2epc; // @[util.scala:688:7, :700:17]
reg uops_2_bits_uop_is_rocc; // @[util.scala:700:17]
assign io_resp_2_bits_uop_is_rocc_0 = uops_2_bits_uop_is_rocc; // @[util.scala:688:7, :700:17]
reg uops_2_bits_uop_is_mov; // @[util.scala:700:17]
assign io_resp_2_bits_uop_is_mov_0 = uops_2_bits_uop_is_mov; // @[util.scala:688:7, :700:17]
reg [4:0] uops_2_bits_uop_ftq_idx; // @[util.scala:700:17]
assign io_resp_2_bits_uop_ftq_idx_0 = uops_2_bits_uop_ftq_idx; // @[util.scala:688:7, :700:17]
reg uops_2_bits_uop_edge_inst; // @[util.scala:700:17]
assign io_resp_2_bits_uop_edge_inst_0 = uops_2_bits_uop_edge_inst; // @[util.scala:688:7, :700:17]
reg [5:0] uops_2_bits_uop_pc_lob; // @[util.scala:700:17]
assign io_resp_2_bits_uop_pc_lob_0 = uops_2_bits_uop_pc_lob; // @[util.scala:688:7, :700:17]
reg uops_2_bits_uop_taken; // @[util.scala:700:17]
assign io_resp_2_bits_uop_taken_0 = uops_2_bits_uop_taken; // @[util.scala:688:7, :700:17]
reg uops_2_bits_uop_imm_rename; // @[util.scala:700:17]
assign io_resp_2_bits_uop_imm_rename_0 = uops_2_bits_uop_imm_rename; // @[util.scala:688:7, :700:17]
reg [2:0] uops_2_bits_uop_imm_sel; // @[util.scala:700:17]
assign io_resp_2_bits_uop_imm_sel_0 = uops_2_bits_uop_imm_sel; // @[util.scala:688:7, :700:17]
reg [4:0] uops_2_bits_uop_pimm; // @[util.scala:700:17]
assign io_resp_2_bits_uop_pimm_0 = uops_2_bits_uop_pimm; // @[util.scala:688:7, :700:17]
reg [19:0] uops_2_bits_uop_imm_packed; // @[util.scala:700:17]
assign io_resp_2_bits_uop_imm_packed_0 = uops_2_bits_uop_imm_packed; // @[util.scala:688:7, :700:17]
reg [1:0] uops_2_bits_uop_op1_sel; // @[util.scala:700:17]
assign io_resp_2_bits_uop_op1_sel_0 = uops_2_bits_uop_op1_sel; // @[util.scala:688:7, :700:17]
reg [2:0] uops_2_bits_uop_op2_sel; // @[util.scala:700:17]
assign io_resp_2_bits_uop_op2_sel_0 = uops_2_bits_uop_op2_sel; // @[util.scala:688:7, :700:17]
reg uops_2_bits_uop_fp_ctrl_ldst; // @[util.scala:700:17]
assign io_resp_2_bits_uop_fp_ctrl_ldst_0 = uops_2_bits_uop_fp_ctrl_ldst; // @[util.scala:688:7, :700:17]
reg uops_2_bits_uop_fp_ctrl_wen; // @[util.scala:700:17]
assign io_resp_2_bits_uop_fp_ctrl_wen_0 = uops_2_bits_uop_fp_ctrl_wen; // @[util.scala:688:7, :700:17]
reg uops_2_bits_uop_fp_ctrl_ren1; // @[util.scala:700:17]
assign io_resp_2_bits_uop_fp_ctrl_ren1_0 = uops_2_bits_uop_fp_ctrl_ren1; // @[util.scala:688:7, :700:17]
reg uops_2_bits_uop_fp_ctrl_ren2; // @[util.scala:700:17]
assign io_resp_2_bits_uop_fp_ctrl_ren2_0 = uops_2_bits_uop_fp_ctrl_ren2; // @[util.scala:688:7, :700:17]
reg uops_2_bits_uop_fp_ctrl_ren3; // @[util.scala:700:17]
assign io_resp_2_bits_uop_fp_ctrl_ren3_0 = uops_2_bits_uop_fp_ctrl_ren3; // @[util.scala:688:7, :700:17]
reg uops_2_bits_uop_fp_ctrl_swap12; // @[util.scala:700:17]
assign io_resp_2_bits_uop_fp_ctrl_swap12_0 = uops_2_bits_uop_fp_ctrl_swap12; // @[util.scala:688:7, :700:17]
reg uops_2_bits_uop_fp_ctrl_swap23; // @[util.scala:700:17]
assign io_resp_2_bits_uop_fp_ctrl_swap23_0 = uops_2_bits_uop_fp_ctrl_swap23; // @[util.scala:688:7, :700:17]
reg [1:0] uops_2_bits_uop_fp_ctrl_typeTagIn; // @[util.scala:700:17]
assign io_resp_2_bits_uop_fp_ctrl_typeTagIn_0 = uops_2_bits_uop_fp_ctrl_typeTagIn; // @[util.scala:688:7, :700:17]
reg [1:0] uops_2_bits_uop_fp_ctrl_typeTagOut; // @[util.scala:700:17]
assign io_resp_2_bits_uop_fp_ctrl_typeTagOut_0 = uops_2_bits_uop_fp_ctrl_typeTagOut; // @[util.scala:688:7, :700:17]
reg uops_2_bits_uop_fp_ctrl_fromint; // @[util.scala:700:17]
assign io_resp_2_bits_uop_fp_ctrl_fromint_0 = uops_2_bits_uop_fp_ctrl_fromint; // @[util.scala:688:7, :700:17]
reg uops_2_bits_uop_fp_ctrl_toint; // @[util.scala:700:17]
assign io_resp_2_bits_uop_fp_ctrl_toint_0 = uops_2_bits_uop_fp_ctrl_toint; // @[util.scala:688:7, :700:17]
reg uops_2_bits_uop_fp_ctrl_fastpipe; // @[util.scala:700:17]
assign io_resp_2_bits_uop_fp_ctrl_fastpipe_0 = uops_2_bits_uop_fp_ctrl_fastpipe; // @[util.scala:688:7, :700:17]
reg uops_2_bits_uop_fp_ctrl_fma; // @[util.scala:700:17]
assign io_resp_2_bits_uop_fp_ctrl_fma_0 = uops_2_bits_uop_fp_ctrl_fma; // @[util.scala:688:7, :700:17]
reg uops_2_bits_uop_fp_ctrl_div; // @[util.scala:700:17]
assign io_resp_2_bits_uop_fp_ctrl_div_0 = uops_2_bits_uop_fp_ctrl_div; // @[util.scala:688:7, :700:17]
reg uops_2_bits_uop_fp_ctrl_sqrt; // @[util.scala:700:17]
assign io_resp_2_bits_uop_fp_ctrl_sqrt_0 = uops_2_bits_uop_fp_ctrl_sqrt; // @[util.scala:688:7, :700:17]
reg uops_2_bits_uop_fp_ctrl_wflags; // @[util.scala:700:17]
assign io_resp_2_bits_uop_fp_ctrl_wflags_0 = uops_2_bits_uop_fp_ctrl_wflags; // @[util.scala:688:7, :700:17]
reg uops_2_bits_uop_fp_ctrl_vec; // @[util.scala:700:17]
assign io_resp_2_bits_uop_fp_ctrl_vec_0 = uops_2_bits_uop_fp_ctrl_vec; // @[util.scala:688:7, :700:17]
reg [6:0] uops_2_bits_uop_rob_idx; // @[util.scala:700:17]
assign io_resp_2_bits_uop_rob_idx_0 = uops_2_bits_uop_rob_idx; // @[util.scala:688:7, :700:17]
reg [4:0] uops_2_bits_uop_ldq_idx; // @[util.scala:700:17]
assign io_resp_2_bits_uop_ldq_idx_0 = uops_2_bits_uop_ldq_idx; // @[util.scala:688:7, :700:17]
reg [4:0] uops_2_bits_uop_stq_idx; // @[util.scala:700:17]
assign io_resp_2_bits_uop_stq_idx_0 = uops_2_bits_uop_stq_idx; // @[util.scala:688:7, :700:17]
reg [1:0] uops_2_bits_uop_rxq_idx; // @[util.scala:700:17]
assign io_resp_2_bits_uop_rxq_idx_0 = uops_2_bits_uop_rxq_idx; // @[util.scala:688:7, :700:17]
reg [6:0] uops_2_bits_uop_pdst; // @[util.scala:700:17]
assign io_resp_2_bits_uop_pdst_0 = uops_2_bits_uop_pdst; // @[util.scala:688:7, :700:17]
reg [6:0] uops_2_bits_uop_prs1; // @[util.scala:700:17]
assign io_resp_2_bits_uop_prs1_0 = uops_2_bits_uop_prs1; // @[util.scala:688:7, :700:17]
reg [6:0] uops_2_bits_uop_prs2; // @[util.scala:700:17]
assign io_resp_2_bits_uop_prs2_0 = uops_2_bits_uop_prs2; // @[util.scala:688:7, :700:17]
reg [6:0] uops_2_bits_uop_prs3; // @[util.scala:700:17]
assign io_resp_2_bits_uop_prs3_0 = uops_2_bits_uop_prs3; // @[util.scala:688:7, :700:17]
reg [4:0] uops_2_bits_uop_ppred; // @[util.scala:700:17]
assign io_resp_2_bits_uop_ppred_0 = uops_2_bits_uop_ppred; // @[util.scala:688:7, :700:17]
reg uops_2_bits_uop_prs1_busy; // @[util.scala:700:17]
assign io_resp_2_bits_uop_prs1_busy_0 = uops_2_bits_uop_prs1_busy; // @[util.scala:688:7, :700:17]
reg uops_2_bits_uop_prs2_busy; // @[util.scala:700:17]
assign io_resp_2_bits_uop_prs2_busy_0 = uops_2_bits_uop_prs2_busy; // @[util.scala:688:7, :700:17]
reg uops_2_bits_uop_prs3_busy; // @[util.scala:700:17]
assign io_resp_2_bits_uop_prs3_busy_0 = uops_2_bits_uop_prs3_busy; // @[util.scala:688:7, :700:17]
reg uops_2_bits_uop_ppred_busy; // @[util.scala:700:17]
assign io_resp_2_bits_uop_ppred_busy_0 = uops_2_bits_uop_ppred_busy; // @[util.scala:688:7, :700:17]
reg [6:0] uops_2_bits_uop_stale_pdst; // @[util.scala:700:17]
assign io_resp_2_bits_uop_stale_pdst_0 = uops_2_bits_uop_stale_pdst; // @[util.scala:688:7, :700:17]
reg uops_2_bits_uop_exception; // @[util.scala:700:17]
assign io_resp_2_bits_uop_exception_0 = uops_2_bits_uop_exception; // @[util.scala:688:7, :700:17]
reg [63:0] uops_2_bits_uop_exc_cause; // @[util.scala:700:17]
assign io_resp_2_bits_uop_exc_cause_0 = uops_2_bits_uop_exc_cause; // @[util.scala:688:7, :700:17]
reg [4:0] uops_2_bits_uop_mem_cmd; // @[util.scala:700:17]
assign io_resp_2_bits_uop_mem_cmd_0 = uops_2_bits_uop_mem_cmd; // @[util.scala:688:7, :700:17]
reg [1:0] uops_2_bits_uop_mem_size; // @[util.scala:700:17]
assign io_resp_2_bits_uop_mem_size_0 = uops_2_bits_uop_mem_size; // @[util.scala:688:7, :700:17]
reg uops_2_bits_uop_mem_signed; // @[util.scala:700:17]
assign io_resp_2_bits_uop_mem_signed_0 = uops_2_bits_uop_mem_signed; // @[util.scala:688:7, :700:17]
reg uops_2_bits_uop_uses_ldq; // @[util.scala:700:17]
assign io_resp_2_bits_uop_uses_ldq_0 = uops_2_bits_uop_uses_ldq; // @[util.scala:688:7, :700:17]
reg uops_2_bits_uop_uses_stq; // @[util.scala:700:17]
assign io_resp_2_bits_uop_uses_stq_0 = uops_2_bits_uop_uses_stq; // @[util.scala:688:7, :700:17]
reg uops_2_bits_uop_is_unique; // @[util.scala:700:17]
assign io_resp_2_bits_uop_is_unique_0 = uops_2_bits_uop_is_unique; // @[util.scala:688:7, :700:17]
reg uops_2_bits_uop_flush_on_commit; // @[util.scala:700:17]
assign io_resp_2_bits_uop_flush_on_commit_0 = uops_2_bits_uop_flush_on_commit; // @[util.scala:688:7, :700:17]
reg [2:0] uops_2_bits_uop_csr_cmd; // @[util.scala:700:17]
assign io_resp_2_bits_uop_csr_cmd_0 = uops_2_bits_uop_csr_cmd; // @[util.scala:688:7, :700:17]
reg uops_2_bits_uop_ldst_is_rs1; // @[util.scala:700:17]
assign io_resp_2_bits_uop_ldst_is_rs1_0 = uops_2_bits_uop_ldst_is_rs1; // @[util.scala:688:7, :700:17]
reg [5:0] uops_2_bits_uop_ldst; // @[util.scala:700:17]
assign io_resp_2_bits_uop_ldst_0 = uops_2_bits_uop_ldst; // @[util.scala:688:7, :700:17]
reg [5:0] uops_2_bits_uop_lrs1; // @[util.scala:700:17]
assign io_resp_2_bits_uop_lrs1_0 = uops_2_bits_uop_lrs1; // @[util.scala:688:7, :700:17]
reg [5:0] uops_2_bits_uop_lrs2; // @[util.scala:700:17]
assign io_resp_2_bits_uop_lrs2_0 = uops_2_bits_uop_lrs2; // @[util.scala:688:7, :700:17]
reg [5:0] uops_2_bits_uop_lrs3; // @[util.scala:700:17]
assign io_resp_2_bits_uop_lrs3_0 = uops_2_bits_uop_lrs3; // @[util.scala:688:7, :700:17]
reg [1:0] uops_2_bits_uop_dst_rtype; // @[util.scala:700:17]
assign io_resp_2_bits_uop_dst_rtype_0 = uops_2_bits_uop_dst_rtype; // @[util.scala:688:7, :700:17]
reg [1:0] uops_2_bits_uop_lrs1_rtype; // @[util.scala:700:17]
assign io_resp_2_bits_uop_lrs1_rtype_0 = uops_2_bits_uop_lrs1_rtype; // @[util.scala:688:7, :700:17]
reg [1:0] uops_2_bits_uop_lrs2_rtype; // @[util.scala:700:17]
assign io_resp_2_bits_uop_lrs2_rtype_0 = uops_2_bits_uop_lrs2_rtype; // @[util.scala:688:7, :700:17]
reg uops_2_bits_uop_frs3_en; // @[util.scala:700:17]
assign io_resp_2_bits_uop_frs3_en_0 = uops_2_bits_uop_frs3_en; // @[util.scala:688:7, :700:17]
reg uops_2_bits_uop_fcn_dw; // @[util.scala:700:17]
assign io_resp_2_bits_uop_fcn_dw_0 = uops_2_bits_uop_fcn_dw; // @[util.scala:688:7, :700:17]
reg [4:0] uops_2_bits_uop_fcn_op; // @[util.scala:700:17]
assign io_resp_2_bits_uop_fcn_op_0 = uops_2_bits_uop_fcn_op; // @[util.scala:688:7, :700:17]
reg uops_2_bits_uop_fp_val; // @[util.scala:700:17]
assign io_resp_2_bits_uop_fp_val_0 = uops_2_bits_uop_fp_val; // @[util.scala:688:7, :700:17]
reg [2:0] uops_2_bits_uop_fp_rm; // @[util.scala:700:17]
assign io_resp_2_bits_uop_fp_rm_0 = uops_2_bits_uop_fp_rm; // @[util.scala:688:7, :700:17]
reg [1:0] uops_2_bits_uop_fp_typ; // @[util.scala:700:17]
assign io_resp_2_bits_uop_fp_typ_0 = uops_2_bits_uop_fp_typ; // @[util.scala:688:7, :700:17]
reg uops_2_bits_uop_xcpt_pf_if; // @[util.scala:700:17]
assign io_resp_2_bits_uop_xcpt_pf_if_0 = uops_2_bits_uop_xcpt_pf_if; // @[util.scala:688:7, :700:17]
reg uops_2_bits_uop_xcpt_ae_if; // @[util.scala:700:17]
assign io_resp_2_bits_uop_xcpt_ae_if_0 = uops_2_bits_uop_xcpt_ae_if; // @[util.scala:688:7, :700:17]
reg uops_2_bits_uop_xcpt_ma_if; // @[util.scala:700:17]
assign io_resp_2_bits_uop_xcpt_ma_if_0 = uops_2_bits_uop_xcpt_ma_if; // @[util.scala:688:7, :700:17]
reg uops_2_bits_uop_bp_debug_if; // @[util.scala:700:17]
assign io_resp_2_bits_uop_bp_debug_if_0 = uops_2_bits_uop_bp_debug_if; // @[util.scala:688:7, :700:17]
reg uops_2_bits_uop_bp_xcpt_if; // @[util.scala:700:17]
assign io_resp_2_bits_uop_bp_xcpt_if_0 = uops_2_bits_uop_bp_xcpt_if; // @[util.scala:688:7, :700:17]
reg [2:0] uops_2_bits_uop_debug_fsrc; // @[util.scala:700:17]
assign io_resp_2_bits_uop_debug_fsrc_0 = uops_2_bits_uop_debug_fsrc; // @[util.scala:688:7, :700:17]
reg [2:0] uops_2_bits_uop_debug_tsrc; // @[util.scala:700:17]
assign io_resp_2_bits_uop_debug_tsrc_0 = uops_2_bits_uop_debug_tsrc; // @[util.scala:688:7, :700:17]
reg [63:0] uops_2_bits_rs1_data; // @[util.scala:700:17]
assign io_resp_2_bits_rs1_data = uops_2_bits_rs1_data; // @[util.scala:688:7, :700:17]
reg [63:0] uops_2_bits_rs2_data; // @[util.scala:700:17]
assign io_resp_2_bits_rs2_data = uops_2_bits_rs2_data; // @[util.scala:688:7, :700:17]
reg [63:0] uops_2_bits_rs3_data; // @[util.scala:700:17]
assign io_resp_2_bits_rs3_data = uops_2_bits_rs3_data; // @[util.scala:688:7, :700:17]
reg uops_2_bits_ftq_info_0_valid; // @[util.scala:700:17]
assign io_resp_2_bits_ftq_info_0_valid = uops_2_bits_ftq_info_0_valid; // @[util.scala:688:7, :700:17]
reg uops_2_bits_ftq_info_0_entry_cfi_idx_valid; // @[util.scala:700:17]
assign io_resp_2_bits_ftq_info_0_entry_cfi_idx_valid = uops_2_bits_ftq_info_0_entry_cfi_idx_valid; // @[util.scala:688:7, :700:17]
reg [2:0] uops_2_bits_ftq_info_0_entry_cfi_idx_bits; // @[util.scala:700:17]
assign io_resp_2_bits_ftq_info_0_entry_cfi_idx_bits = uops_2_bits_ftq_info_0_entry_cfi_idx_bits; // @[util.scala:688:7, :700:17]
reg uops_2_bits_ftq_info_0_entry_cfi_taken; // @[util.scala:700:17]
assign io_resp_2_bits_ftq_info_0_entry_cfi_taken = uops_2_bits_ftq_info_0_entry_cfi_taken; // @[util.scala:688:7, :700:17]
reg uops_2_bits_ftq_info_0_entry_cfi_mispredicted; // @[util.scala:700:17]
assign io_resp_2_bits_ftq_info_0_entry_cfi_mispredicted = uops_2_bits_ftq_info_0_entry_cfi_mispredicted; // @[util.scala:688:7, :700:17]
reg [2:0] uops_2_bits_ftq_info_0_entry_cfi_type; // @[util.scala:700:17]
assign io_resp_2_bits_ftq_info_0_entry_cfi_type = uops_2_bits_ftq_info_0_entry_cfi_type; // @[util.scala:688:7, :700:17]
reg [7:0] uops_2_bits_ftq_info_0_entry_br_mask; // @[util.scala:700:17]
assign io_resp_2_bits_ftq_info_0_entry_br_mask = uops_2_bits_ftq_info_0_entry_br_mask; // @[util.scala:688:7, :700:17]
reg uops_2_bits_ftq_info_0_entry_cfi_is_call; // @[util.scala:700:17]
assign io_resp_2_bits_ftq_info_0_entry_cfi_is_call = uops_2_bits_ftq_info_0_entry_cfi_is_call; // @[util.scala:688:7, :700:17]
reg uops_2_bits_ftq_info_0_entry_cfi_is_ret; // @[util.scala:700:17]
assign io_resp_2_bits_ftq_info_0_entry_cfi_is_ret = uops_2_bits_ftq_info_0_entry_cfi_is_ret; // @[util.scala:688:7, :700:17]
reg uops_2_bits_ftq_info_0_entry_cfi_npc_plus4; // @[util.scala:700:17]
assign io_resp_2_bits_ftq_info_0_entry_cfi_npc_plus4 = uops_2_bits_ftq_info_0_entry_cfi_npc_plus4; // @[util.scala:688:7, :700:17]
reg [39:0] uops_2_bits_ftq_info_0_entry_ras_top; // @[util.scala:700:17]
assign io_resp_2_bits_ftq_info_0_entry_ras_top = uops_2_bits_ftq_info_0_entry_ras_top; // @[util.scala:688:7, :700:17]
reg [4:0] uops_2_bits_ftq_info_0_entry_ras_idx; // @[util.scala:700:17]
assign io_resp_2_bits_ftq_info_0_entry_ras_idx = uops_2_bits_ftq_info_0_entry_ras_idx; // @[util.scala:688:7, :700:17]
reg uops_2_bits_ftq_info_0_entry_start_bank; // @[util.scala:700:17]
assign io_resp_2_bits_ftq_info_0_entry_start_bank = uops_2_bits_ftq_info_0_entry_start_bank; // @[util.scala:688:7, :700:17]
reg [63:0] uops_2_bits_ftq_info_0_ghist_old_history; // @[util.scala:700:17]
assign io_resp_2_bits_ftq_info_0_ghist_old_history = uops_2_bits_ftq_info_0_ghist_old_history; // @[util.scala:688:7, :700:17]
reg uops_2_bits_ftq_info_0_ghist_current_saw_branch_not_taken; // @[util.scala:700:17]
assign io_resp_2_bits_ftq_info_0_ghist_current_saw_branch_not_taken = uops_2_bits_ftq_info_0_ghist_current_saw_branch_not_taken; // @[util.scala:688:7, :700:17]
reg uops_2_bits_ftq_info_0_ghist_new_saw_branch_not_taken; // @[util.scala:700:17]
assign io_resp_2_bits_ftq_info_0_ghist_new_saw_branch_not_taken = uops_2_bits_ftq_info_0_ghist_new_saw_branch_not_taken; // @[util.scala:688:7, :700:17]
reg uops_2_bits_ftq_info_0_ghist_new_saw_branch_taken; // @[util.scala:700:17]
assign io_resp_2_bits_ftq_info_0_ghist_new_saw_branch_taken = uops_2_bits_ftq_info_0_ghist_new_saw_branch_taken; // @[util.scala:688:7, :700:17]
reg [4:0] uops_2_bits_ftq_info_0_ghist_ras_idx; // @[util.scala:700:17]
assign io_resp_2_bits_ftq_info_0_ghist_ras_idx = uops_2_bits_ftq_info_0_ghist_ras_idx; // @[util.scala:688:7, :700:17]
reg [39:0] uops_2_bits_ftq_info_0_pc; // @[util.scala:700:17]
assign io_resp_2_bits_ftq_info_0_pc = uops_2_bits_ftq_info_0_pc; // @[util.scala:688:7, :700:17]
reg uops_2_bits_ftq_info_1_valid; // @[util.scala:700:17]
assign io_resp_2_bits_ftq_info_1_valid = uops_2_bits_ftq_info_1_valid; // @[util.scala:688:7, :700:17]
reg uops_2_bits_ftq_info_1_entry_cfi_idx_valid; // @[util.scala:700:17]
assign io_resp_2_bits_ftq_info_1_entry_cfi_idx_valid = uops_2_bits_ftq_info_1_entry_cfi_idx_valid; // @[util.scala:688:7, :700:17]
reg [2:0] uops_2_bits_ftq_info_1_entry_cfi_idx_bits; // @[util.scala:700:17]
assign io_resp_2_bits_ftq_info_1_entry_cfi_idx_bits = uops_2_bits_ftq_info_1_entry_cfi_idx_bits; // @[util.scala:688:7, :700:17]
reg uops_2_bits_ftq_info_1_entry_cfi_taken; // @[util.scala:700:17]
assign io_resp_2_bits_ftq_info_1_entry_cfi_taken = uops_2_bits_ftq_info_1_entry_cfi_taken; // @[util.scala:688:7, :700:17]
reg uops_2_bits_ftq_info_1_entry_cfi_mispredicted; // @[util.scala:700:17]
assign io_resp_2_bits_ftq_info_1_entry_cfi_mispredicted = uops_2_bits_ftq_info_1_entry_cfi_mispredicted; // @[util.scala:688:7, :700:17]
reg [2:0] uops_2_bits_ftq_info_1_entry_cfi_type; // @[util.scala:700:17]
assign io_resp_2_bits_ftq_info_1_entry_cfi_type = uops_2_bits_ftq_info_1_entry_cfi_type; // @[util.scala:688:7, :700:17]
reg [7:0] uops_2_bits_ftq_info_1_entry_br_mask; // @[util.scala:700:17]
assign io_resp_2_bits_ftq_info_1_entry_br_mask = uops_2_bits_ftq_info_1_entry_br_mask; // @[util.scala:688:7, :700:17]
reg uops_2_bits_ftq_info_1_entry_cfi_is_call; // @[util.scala:700:17]
assign io_resp_2_bits_ftq_info_1_entry_cfi_is_call = uops_2_bits_ftq_info_1_entry_cfi_is_call; // @[util.scala:688:7, :700:17]
reg uops_2_bits_ftq_info_1_entry_cfi_is_ret; // @[util.scala:700:17]
assign io_resp_2_bits_ftq_info_1_entry_cfi_is_ret = uops_2_bits_ftq_info_1_entry_cfi_is_ret; // @[util.scala:688:7, :700:17]
reg uops_2_bits_ftq_info_1_entry_cfi_npc_plus4; // @[util.scala:700:17]
assign io_resp_2_bits_ftq_info_1_entry_cfi_npc_plus4 = uops_2_bits_ftq_info_1_entry_cfi_npc_plus4; // @[util.scala:688:7, :700:17]
reg [39:0] uops_2_bits_ftq_info_1_entry_ras_top; // @[util.scala:700:17]
assign io_resp_2_bits_ftq_info_1_entry_ras_top = uops_2_bits_ftq_info_1_entry_ras_top; // @[util.scala:688:7, :700:17]
reg [4:0] uops_2_bits_ftq_info_1_entry_ras_idx; // @[util.scala:700:17]
assign io_resp_2_bits_ftq_info_1_entry_ras_idx = uops_2_bits_ftq_info_1_entry_ras_idx; // @[util.scala:688:7, :700:17]
reg uops_2_bits_ftq_info_1_entry_start_bank; // @[util.scala:700:17]
assign io_resp_2_bits_ftq_info_1_entry_start_bank = uops_2_bits_ftq_info_1_entry_start_bank; // @[util.scala:688:7, :700:17]
reg [63:0] uops_2_bits_ftq_info_1_ghist_old_history; // @[util.scala:700:17]
assign io_resp_2_bits_ftq_info_1_ghist_old_history = uops_2_bits_ftq_info_1_ghist_old_history; // @[util.scala:688:7, :700:17]
reg uops_2_bits_ftq_info_1_ghist_current_saw_branch_not_taken; // @[util.scala:700:17]
assign io_resp_2_bits_ftq_info_1_ghist_current_saw_branch_not_taken = uops_2_bits_ftq_info_1_ghist_current_saw_branch_not_taken; // @[util.scala:688:7, :700:17]
reg uops_2_bits_ftq_info_1_ghist_new_saw_branch_not_taken; // @[util.scala:700:17]
assign io_resp_2_bits_ftq_info_1_ghist_new_saw_branch_not_taken = uops_2_bits_ftq_info_1_ghist_new_saw_branch_not_taken; // @[util.scala:688:7, :700:17]
reg uops_2_bits_ftq_info_1_ghist_new_saw_branch_taken; // @[util.scala:700:17]
assign io_resp_2_bits_ftq_info_1_ghist_new_saw_branch_taken = uops_2_bits_ftq_info_1_ghist_new_saw_branch_taken; // @[util.scala:688:7, :700:17]
reg [4:0] uops_2_bits_ftq_info_1_ghist_ras_idx; // @[util.scala:700:17]
assign io_resp_2_bits_ftq_info_1_ghist_ras_idx = uops_2_bits_ftq_info_1_ghist_ras_idx; // @[util.scala:688:7, :700:17]
reg [39:0] uops_2_bits_ftq_info_1_pc; // @[util.scala:700:17]
assign io_resp_2_bits_ftq_info_1_pc = uops_2_bits_ftq_info_1_pc; // @[util.scala:688:7, :700:17]
reg uops_2_bits_pred_data; // @[util.scala:700:17]
assign io_resp_2_bits_pred_data = uops_2_bits_pred_data; // @[util.scala:688:7, :700:17]
reg [63:0] uops_2_bits_imm_data; // @[util.scala:700:17]
assign io_resp_2_bits_imm_data = uops_2_bits_imm_data; // @[util.scala:688:7, :700:17]
wire [15:0] _uops_0_valid_T = io_brupdate_b1_mispredict_mask_0 & io_req_bits_uop_br_mask_0; // @[util.scala:126:51, :688:7]
wire _uops_0_valid_T_1 = |_uops_0_valid_T; // @[util.scala:126:{51,59}]
wire _uops_0_valid_T_2 = _uops_0_valid_T_1 | io_flush_0; // @[util.scala:61:61, :126:59, :688:7]
wire _uops_0_valid_T_3 = ~_uops_0_valid_T_2; // @[util.scala:61:61, :701:36]
wire _uops_0_valid_T_4 = io_req_valid_0 & _uops_0_valid_T_3; // @[util.scala:688:7, :701:{33,36}]
wire [15:0] _uops_0_bits_out_uop_br_mask_T_1; // @[util.scala:97:21]
wire [15:0] uops_0_bits_out_uop_br_mask; // @[util.scala:109:23]
wire [15:0] _uops_0_bits_out_uop_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:97:23, :688:7]
assign _uops_0_bits_out_uop_br_mask_T_1 = io_req_bits_uop_br_mask_0 & _uops_0_bits_out_uop_br_mask_T; // @[util.scala:97:{21,23}, :688:7]
assign uops_0_bits_out_uop_br_mask = _uops_0_bits_out_uop_br_mask_T_1; // @[util.scala:97:21, :109:23]
wire [15:0] _uops_1_valid_T = io_brupdate_b1_mispredict_mask_0 & uops_0_bits_uop_br_mask; // @[util.scala:126:51, :688:7, :700:17]
wire _uops_1_valid_T_1 = |_uops_1_valid_T; // @[util.scala:126:{51,59}]
wire _uops_1_valid_T_2 = _uops_1_valid_T_1 | io_flush_0; // @[util.scala:61:61, :126:59, :688:7]
wire _uops_1_valid_T_3 = ~_uops_1_valid_T_2; // @[util.scala:61:61, :704:41]
wire _uops_1_valid_T_4 = uops_0_valid & _uops_1_valid_T_3; // @[util.scala:700:17, :704:{38,41}]
wire [15:0] _uops_1_bits_out_uop_br_mask_T_1; // @[util.scala:97:21]
wire [15:0] uops_1_bits_out_uop_br_mask; // @[util.scala:109:23]
wire [15:0] _uops_1_bits_out_uop_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:97:23, :688:7]
assign _uops_1_bits_out_uop_br_mask_T_1 = uops_0_bits_uop_br_mask & _uops_1_bits_out_uop_br_mask_T; // @[util.scala:97:{21,23}, :700:17]
assign uops_1_bits_out_uop_br_mask = _uops_1_bits_out_uop_br_mask_T_1; // @[util.scala:97:21, :109:23]
wire [15:0] _uops_2_valid_T = io_brupdate_b1_mispredict_mask_0 & uops_1_bits_uop_br_mask; // @[util.scala:126:51, :688:7, :700:17]
wire _uops_2_valid_T_1 = |_uops_2_valid_T; // @[util.scala:126:{51,59}]
wire _uops_2_valid_T_2 = _uops_2_valid_T_1 | io_flush_0; // @[util.scala:61:61, :126:59, :688:7]
wire _uops_2_valid_T_3 = ~_uops_2_valid_T_2; // @[util.scala:61:61, :704:41]
wire _uops_2_valid_T_4 = uops_1_valid & _uops_2_valid_T_3; // @[util.scala:700:17, :704:{38,41}]
wire [15:0] _uops_2_bits_out_uop_br_mask_T_1; // @[util.scala:97:21]
wire [15:0] uops_2_bits_out_uop_br_mask; // @[util.scala:109:23]
wire [15:0] _uops_2_bits_out_uop_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:97:23, :688:7]
assign _uops_2_bits_out_uop_br_mask_T_1 = uops_1_bits_uop_br_mask & _uops_2_bits_out_uop_br_mask_T; // @[util.scala:97:{21,23}, :700:17]
assign uops_2_bits_out_uop_br_mask = _uops_2_bits_out_uop_br_mask_T_1; // @[util.scala:97:21, :109:23]
always @(posedge clock) begin // @[util.scala:688:7]
if (reset) begin // @[util.scala:688:7]
uops_0_valid <= 1'h0; // @[util.scala:700:17]
uops_1_valid <= 1'h0; // @[util.scala:700:17]
uops_2_valid <= 1'h0; // @[util.scala:700:17]
end
else begin // @[util.scala:688:7]
uops_0_valid <= _uops_0_valid_T_4; // @[util.scala:700:17, :701:33]
uops_1_valid <= _uops_1_valid_T_4; // @[util.scala:700:17, :704:38]
uops_2_valid <= _uops_2_valid_T_4; // @[util.scala:700:17, :704:38]
end
uops_0_bits_uop_inst <= uops_0_bits_out_uop_inst; // @[util.scala:109:23, :700:17]
uops_0_bits_uop_debug_inst <= uops_0_bits_out_uop_debug_inst; // @[util.scala:109:23, :700:17]
uops_0_bits_uop_is_rvc <= uops_0_bits_out_uop_is_rvc; // @[util.scala:109:23, :700:17]
uops_0_bits_uop_debug_pc <= uops_0_bits_out_uop_debug_pc; // @[util.scala:109:23, :700:17]
uops_0_bits_uop_iq_type_0 <= uops_0_bits_out_uop_iq_type_0; // @[util.scala:109:23, :700:17]
uops_0_bits_uop_iq_type_1 <= uops_0_bits_out_uop_iq_type_1; // @[util.scala:109:23, :700:17]
uops_0_bits_uop_iq_type_2 <= uops_0_bits_out_uop_iq_type_2; // @[util.scala:109:23, :700:17]
uops_0_bits_uop_iq_type_3 <= uops_0_bits_out_uop_iq_type_3; // @[util.scala:109:23, :700:17]
uops_0_bits_uop_fu_code_0 <= uops_0_bits_out_uop_fu_code_0; // @[util.scala:109:23, :700:17]
uops_0_bits_uop_fu_code_1 <= uops_0_bits_out_uop_fu_code_1; // @[util.scala:109:23, :700:17]
uops_0_bits_uop_fu_code_2 <= uops_0_bits_out_uop_fu_code_2; // @[util.scala:109:23, :700:17]
uops_0_bits_uop_fu_code_3 <= uops_0_bits_out_uop_fu_code_3; // @[util.scala:109:23, :700:17]
uops_0_bits_uop_fu_code_4 <= uops_0_bits_out_uop_fu_code_4; // @[util.scala:109:23, :700:17]
uops_0_bits_uop_fu_code_5 <= uops_0_bits_out_uop_fu_code_5; // @[util.scala:109:23, :700:17]
uops_0_bits_uop_fu_code_6 <= uops_0_bits_out_uop_fu_code_6; // @[util.scala:109:23, :700:17]
uops_0_bits_uop_fu_code_7 <= uops_0_bits_out_uop_fu_code_7; // @[util.scala:109:23, :700:17]
uops_0_bits_uop_fu_code_8 <= uops_0_bits_out_uop_fu_code_8; // @[util.scala:109:23, :700:17]
uops_0_bits_uop_fu_code_9 <= uops_0_bits_out_uop_fu_code_9; // @[util.scala:109:23, :700:17]
uops_0_bits_uop_iw_issued <= uops_0_bits_out_uop_iw_issued; // @[util.scala:109:23, :700:17]
uops_0_bits_uop_iw_issued_partial_agen <= uops_0_bits_out_uop_iw_issued_partial_agen; // @[util.scala:109:23, :700:17]
uops_0_bits_uop_iw_issued_partial_dgen <= uops_0_bits_out_uop_iw_issued_partial_dgen; // @[util.scala:109:23, :700:17]
uops_0_bits_uop_iw_p1_speculative_child <= uops_0_bits_out_uop_iw_p1_speculative_child; // @[util.scala:109:23, :700:17]
uops_0_bits_uop_iw_p2_speculative_child <= uops_0_bits_out_uop_iw_p2_speculative_child; // @[util.scala:109:23, :700:17]
uops_0_bits_uop_iw_p1_bypass_hint <= uops_0_bits_out_uop_iw_p1_bypass_hint; // @[util.scala:109:23, :700:17]
uops_0_bits_uop_iw_p2_bypass_hint <= uops_0_bits_out_uop_iw_p2_bypass_hint; // @[util.scala:109:23, :700:17]
uops_0_bits_uop_iw_p3_bypass_hint <= uops_0_bits_out_uop_iw_p3_bypass_hint; // @[util.scala:109:23, :700:17]
uops_0_bits_uop_dis_col_sel <= uops_0_bits_out_uop_dis_col_sel; // @[util.scala:109:23, :700:17]
uops_0_bits_uop_br_mask <= uops_0_bits_out_uop_br_mask; // @[util.scala:109:23, :700:17]
uops_0_bits_uop_br_tag <= uops_0_bits_out_uop_br_tag; // @[util.scala:109:23, :700:17]
uops_0_bits_uop_br_type <= uops_0_bits_out_uop_br_type; // @[util.scala:109:23, :700:17]
uops_0_bits_uop_is_sfb <= uops_0_bits_out_uop_is_sfb; // @[util.scala:109:23, :700:17]
uops_0_bits_uop_is_fence <= uops_0_bits_out_uop_is_fence; // @[util.scala:109:23, :700:17]
uops_0_bits_uop_is_fencei <= uops_0_bits_out_uop_is_fencei; // @[util.scala:109:23, :700:17]
uops_0_bits_uop_is_sfence <= uops_0_bits_out_uop_is_sfence; // @[util.scala:109:23, :700:17]
uops_0_bits_uop_is_amo <= uops_0_bits_out_uop_is_amo; // @[util.scala:109:23, :700:17]
uops_0_bits_uop_is_eret <= uops_0_bits_out_uop_is_eret; // @[util.scala:109:23, :700:17]
uops_0_bits_uop_is_sys_pc2epc <= uops_0_bits_out_uop_is_sys_pc2epc; // @[util.scala:109:23, :700:17]
uops_0_bits_uop_is_rocc <= uops_0_bits_out_uop_is_rocc; // @[util.scala:109:23, :700:17]
uops_0_bits_uop_is_mov <= uops_0_bits_out_uop_is_mov; // @[util.scala:109:23, :700:17]
uops_0_bits_uop_ftq_idx <= uops_0_bits_out_uop_ftq_idx; // @[util.scala:109:23, :700:17]
uops_0_bits_uop_edge_inst <= uops_0_bits_out_uop_edge_inst; // @[util.scala:109:23, :700:17]
uops_0_bits_uop_pc_lob <= uops_0_bits_out_uop_pc_lob; // @[util.scala:109:23, :700:17]
uops_0_bits_uop_taken <= uops_0_bits_out_uop_taken; // @[util.scala:109:23, :700:17]
uops_0_bits_uop_imm_rename <= uops_0_bits_out_uop_imm_rename; // @[util.scala:109:23, :700:17]
uops_0_bits_uop_imm_sel <= uops_0_bits_out_uop_imm_sel; // @[util.scala:109:23, :700:17]
uops_0_bits_uop_pimm <= uops_0_bits_out_uop_pimm; // @[util.scala:109:23, :700:17]
uops_0_bits_uop_imm_packed <= uops_0_bits_out_uop_imm_packed; // @[util.scala:109:23, :700:17]
uops_0_bits_uop_op1_sel <= uops_0_bits_out_uop_op1_sel; // @[util.scala:109:23, :700:17]
uops_0_bits_uop_op2_sel <= uops_0_bits_out_uop_op2_sel; // @[util.scala:109:23, :700:17]
uops_0_bits_uop_fp_ctrl_ldst <= uops_0_bits_out_uop_fp_ctrl_ldst; // @[util.scala:109:23, :700:17]
uops_0_bits_uop_fp_ctrl_wen <= uops_0_bits_out_uop_fp_ctrl_wen; // @[util.scala:109:23, :700:17]
uops_0_bits_uop_fp_ctrl_ren1 <= uops_0_bits_out_uop_fp_ctrl_ren1; // @[util.scala:109:23, :700:17]
uops_0_bits_uop_fp_ctrl_ren2 <= uops_0_bits_out_uop_fp_ctrl_ren2; // @[util.scala:109:23, :700:17]
uops_0_bits_uop_fp_ctrl_ren3 <= uops_0_bits_out_uop_fp_ctrl_ren3; // @[util.scala:109:23, :700:17]
uops_0_bits_uop_fp_ctrl_swap12 <= uops_0_bits_out_uop_fp_ctrl_swap12; // @[util.scala:109:23, :700:17]
uops_0_bits_uop_fp_ctrl_swap23 <= uops_0_bits_out_uop_fp_ctrl_swap23; // @[util.scala:109:23, :700:17]
uops_0_bits_uop_fp_ctrl_typeTagIn <= uops_0_bits_out_uop_fp_ctrl_typeTagIn; // @[util.scala:109:23, :700:17]
uops_0_bits_uop_fp_ctrl_typeTagOut <= uops_0_bits_out_uop_fp_ctrl_typeTagOut; // @[util.scala:109:23, :700:17]
uops_0_bits_uop_fp_ctrl_fromint <= uops_0_bits_out_uop_fp_ctrl_fromint; // @[util.scala:109:23, :700:17]
uops_0_bits_uop_fp_ctrl_toint <= uops_0_bits_out_uop_fp_ctrl_toint; // @[util.scala:109:23, :700:17]
uops_0_bits_uop_fp_ctrl_fastpipe <= uops_0_bits_out_uop_fp_ctrl_fastpipe; // @[util.scala:109:23, :700:17]
uops_0_bits_uop_fp_ctrl_fma <= uops_0_bits_out_uop_fp_ctrl_fma; // @[util.scala:109:23, :700:17]
uops_0_bits_uop_fp_ctrl_div <= uops_0_bits_out_uop_fp_ctrl_div; // @[util.scala:109:23, :700:17]
uops_0_bits_uop_fp_ctrl_sqrt <= uops_0_bits_out_uop_fp_ctrl_sqrt; // @[util.scala:109:23, :700:17]
uops_0_bits_uop_fp_ctrl_wflags <= uops_0_bits_out_uop_fp_ctrl_wflags; // @[util.scala:109:23, :700:17]
uops_0_bits_uop_fp_ctrl_vec <= uops_0_bits_out_uop_fp_ctrl_vec; // @[util.scala:109:23, :700:17]
uops_0_bits_uop_rob_idx <= uops_0_bits_out_uop_rob_idx; // @[util.scala:109:23, :700:17]
uops_0_bits_uop_ldq_idx <= uops_0_bits_out_uop_ldq_idx; // @[util.scala:109:23, :700:17]
uops_0_bits_uop_stq_idx <= uops_0_bits_out_uop_stq_idx; // @[util.scala:109:23, :700:17]
uops_0_bits_uop_rxq_idx <= uops_0_bits_out_uop_rxq_idx; // @[util.scala:109:23, :700:17]
uops_0_bits_uop_pdst <= uops_0_bits_out_uop_pdst; // @[util.scala:109:23, :700:17]
uops_0_bits_uop_prs1 <= uops_0_bits_out_uop_prs1; // @[util.scala:109:23, :700:17]
uops_0_bits_uop_prs2 <= uops_0_bits_out_uop_prs2; // @[util.scala:109:23, :700:17]
uops_0_bits_uop_prs3 <= uops_0_bits_out_uop_prs3; // @[util.scala:109:23, :700:17]
uops_0_bits_uop_ppred <= uops_0_bits_out_uop_ppred; // @[util.scala:109:23, :700:17]
uops_0_bits_uop_prs1_busy <= uops_0_bits_out_uop_prs1_busy; // @[util.scala:109:23, :700:17]
uops_0_bits_uop_prs2_busy <= uops_0_bits_out_uop_prs2_busy; // @[util.scala:109:23, :700:17]
uops_0_bits_uop_prs3_busy <= uops_0_bits_out_uop_prs3_busy; // @[util.scala:109:23, :700:17]
uops_0_bits_uop_ppred_busy <= uops_0_bits_out_uop_ppred_busy; // @[util.scala:109:23, :700:17]
uops_0_bits_uop_stale_pdst <= uops_0_bits_out_uop_stale_pdst; // @[util.scala:109:23, :700:17]
uops_0_bits_uop_exception <= uops_0_bits_out_uop_exception; // @[util.scala:109:23, :700:17]
uops_0_bits_uop_exc_cause <= uops_0_bits_out_uop_exc_cause; // @[util.scala:109:23, :700:17]
uops_0_bits_uop_mem_cmd <= uops_0_bits_out_uop_mem_cmd; // @[util.scala:109:23, :700:17]
uops_0_bits_uop_mem_size <= uops_0_bits_out_uop_mem_size; // @[util.scala:109:23, :700:17]
uops_0_bits_uop_mem_signed <= uops_0_bits_out_uop_mem_signed; // @[util.scala:109:23, :700:17]
uops_0_bits_uop_uses_ldq <= uops_0_bits_out_uop_uses_ldq; // @[util.scala:109:23, :700:17]
uops_0_bits_uop_uses_stq <= uops_0_bits_out_uop_uses_stq; // @[util.scala:109:23, :700:17]
uops_0_bits_uop_is_unique <= uops_0_bits_out_uop_is_unique; // @[util.scala:109:23, :700:17]
uops_0_bits_uop_flush_on_commit <= uops_0_bits_out_uop_flush_on_commit; // @[util.scala:109:23, :700:17]
uops_0_bits_uop_csr_cmd <= uops_0_bits_out_uop_csr_cmd; // @[util.scala:109:23, :700:17]
uops_0_bits_uop_ldst_is_rs1 <= uops_0_bits_out_uop_ldst_is_rs1; // @[util.scala:109:23, :700:17]
uops_0_bits_uop_ldst <= uops_0_bits_out_uop_ldst; // @[util.scala:109:23, :700:17]
uops_0_bits_uop_lrs1 <= uops_0_bits_out_uop_lrs1; // @[util.scala:109:23, :700:17]
uops_0_bits_uop_lrs2 <= uops_0_bits_out_uop_lrs2; // @[util.scala:109:23, :700:17]
uops_0_bits_uop_lrs3 <= uops_0_bits_out_uop_lrs3; // @[util.scala:109:23, :700:17]
uops_0_bits_uop_dst_rtype <= uops_0_bits_out_uop_dst_rtype; // @[util.scala:109:23, :700:17]
uops_0_bits_uop_lrs1_rtype <= uops_0_bits_out_uop_lrs1_rtype; // @[util.scala:109:23, :700:17]
uops_0_bits_uop_lrs2_rtype <= uops_0_bits_out_uop_lrs2_rtype; // @[util.scala:109:23, :700:17]
uops_0_bits_uop_frs3_en <= uops_0_bits_out_uop_frs3_en; // @[util.scala:109:23, :700:17]
uops_0_bits_uop_fcn_dw <= uops_0_bits_out_uop_fcn_dw; // @[util.scala:109:23, :700:17]
uops_0_bits_uop_fcn_op <= uops_0_bits_out_uop_fcn_op; // @[util.scala:109:23, :700:17]
uops_0_bits_uop_fp_val <= uops_0_bits_out_uop_fp_val; // @[util.scala:109:23, :700:17]
uops_0_bits_uop_fp_rm <= uops_0_bits_out_uop_fp_rm; // @[util.scala:109:23, :700:17]
uops_0_bits_uop_fp_typ <= uops_0_bits_out_uop_fp_typ; // @[util.scala:109:23, :700:17]
uops_0_bits_uop_xcpt_pf_if <= uops_0_bits_out_uop_xcpt_pf_if; // @[util.scala:109:23, :700:17]
uops_0_bits_uop_xcpt_ae_if <= uops_0_bits_out_uop_xcpt_ae_if; // @[util.scala:109:23, :700:17]
uops_0_bits_uop_xcpt_ma_if <= uops_0_bits_out_uop_xcpt_ma_if; // @[util.scala:109:23, :700:17]
uops_0_bits_uop_bp_debug_if <= uops_0_bits_out_uop_bp_debug_if; // @[util.scala:109:23, :700:17]
uops_0_bits_uop_bp_xcpt_if <= uops_0_bits_out_uop_bp_xcpt_if; // @[util.scala:109:23, :700:17]
uops_0_bits_uop_debug_fsrc <= uops_0_bits_out_uop_debug_fsrc; // @[util.scala:109:23, :700:17]
uops_0_bits_uop_debug_tsrc <= uops_0_bits_out_uop_debug_tsrc; // @[util.scala:109:23, :700:17]
uops_0_bits_rs1_data <= uops_0_bits_out_rs1_data; // @[util.scala:109:23, :700:17]
uops_0_bits_rs2_data <= uops_0_bits_out_rs2_data; // @[util.scala:109:23, :700:17]
uops_0_bits_imm_data <= uops_0_bits_out_imm_data; // @[util.scala:109:23, :700:17]
uops_1_bits_uop_inst <= uops_1_bits_out_uop_inst; // @[util.scala:109:23, :700:17]
uops_1_bits_uop_debug_inst <= uops_1_bits_out_uop_debug_inst; // @[util.scala:109:23, :700:17]
uops_1_bits_uop_is_rvc <= uops_1_bits_out_uop_is_rvc; // @[util.scala:109:23, :700:17]
uops_1_bits_uop_debug_pc <= uops_1_bits_out_uop_debug_pc; // @[util.scala:109:23, :700:17]
uops_1_bits_uop_iq_type_0 <= uops_1_bits_out_uop_iq_type_0; // @[util.scala:109:23, :700:17]
uops_1_bits_uop_iq_type_1 <= uops_1_bits_out_uop_iq_type_1; // @[util.scala:109:23, :700:17]
uops_1_bits_uop_iq_type_2 <= uops_1_bits_out_uop_iq_type_2; // @[util.scala:109:23, :700:17]
uops_1_bits_uop_iq_type_3 <= uops_1_bits_out_uop_iq_type_3; // @[util.scala:109:23, :700:17]
uops_1_bits_uop_fu_code_0 <= uops_1_bits_out_uop_fu_code_0; // @[util.scala:109:23, :700:17]
uops_1_bits_uop_fu_code_1 <= uops_1_bits_out_uop_fu_code_1; // @[util.scala:109:23, :700:17]
uops_1_bits_uop_fu_code_2 <= uops_1_bits_out_uop_fu_code_2; // @[util.scala:109:23, :700:17]
uops_1_bits_uop_fu_code_3 <= uops_1_bits_out_uop_fu_code_3; // @[util.scala:109:23, :700:17]
uops_1_bits_uop_fu_code_4 <= uops_1_bits_out_uop_fu_code_4; // @[util.scala:109:23, :700:17]
uops_1_bits_uop_fu_code_5 <= uops_1_bits_out_uop_fu_code_5; // @[util.scala:109:23, :700:17]
uops_1_bits_uop_fu_code_6 <= uops_1_bits_out_uop_fu_code_6; // @[util.scala:109:23, :700:17]
uops_1_bits_uop_fu_code_7 <= uops_1_bits_out_uop_fu_code_7; // @[util.scala:109:23, :700:17]
uops_1_bits_uop_fu_code_8 <= uops_1_bits_out_uop_fu_code_8; // @[util.scala:109:23, :700:17]
uops_1_bits_uop_fu_code_9 <= uops_1_bits_out_uop_fu_code_9; // @[util.scala:109:23, :700:17]
uops_1_bits_uop_iw_issued <= uops_1_bits_out_uop_iw_issued; // @[util.scala:109:23, :700:17]
uops_1_bits_uop_iw_issued_partial_agen <= uops_1_bits_out_uop_iw_issued_partial_agen; // @[util.scala:109:23, :700:17]
uops_1_bits_uop_iw_issued_partial_dgen <= uops_1_bits_out_uop_iw_issued_partial_dgen; // @[util.scala:109:23, :700:17]
uops_1_bits_uop_iw_p1_speculative_child <= uops_1_bits_out_uop_iw_p1_speculative_child; // @[util.scala:109:23, :700:17]
uops_1_bits_uop_iw_p2_speculative_child <= uops_1_bits_out_uop_iw_p2_speculative_child; // @[util.scala:109:23, :700:17]
uops_1_bits_uop_iw_p1_bypass_hint <= uops_1_bits_out_uop_iw_p1_bypass_hint; // @[util.scala:109:23, :700:17]
uops_1_bits_uop_iw_p2_bypass_hint <= uops_1_bits_out_uop_iw_p2_bypass_hint; // @[util.scala:109:23, :700:17]
uops_1_bits_uop_iw_p3_bypass_hint <= uops_1_bits_out_uop_iw_p3_bypass_hint; // @[util.scala:109:23, :700:17]
uops_1_bits_uop_dis_col_sel <= uops_1_bits_out_uop_dis_col_sel; // @[util.scala:109:23, :700:17]
uops_1_bits_uop_br_mask <= uops_1_bits_out_uop_br_mask; // @[util.scala:109:23, :700:17]
uops_1_bits_uop_br_tag <= uops_1_bits_out_uop_br_tag; // @[util.scala:109:23, :700:17]
uops_1_bits_uop_br_type <= uops_1_bits_out_uop_br_type; // @[util.scala:109:23, :700:17]
uops_1_bits_uop_is_sfb <= uops_1_bits_out_uop_is_sfb; // @[util.scala:109:23, :700:17]
uops_1_bits_uop_is_fence <= uops_1_bits_out_uop_is_fence; // @[util.scala:109:23, :700:17]
uops_1_bits_uop_is_fencei <= uops_1_bits_out_uop_is_fencei; // @[util.scala:109:23, :700:17]
uops_1_bits_uop_is_sfence <= uops_1_bits_out_uop_is_sfence; // @[util.scala:109:23, :700:17]
uops_1_bits_uop_is_amo <= uops_1_bits_out_uop_is_amo; // @[util.scala:109:23, :700:17]
uops_1_bits_uop_is_eret <= uops_1_bits_out_uop_is_eret; // @[util.scala:109:23, :700:17]
uops_1_bits_uop_is_sys_pc2epc <= uops_1_bits_out_uop_is_sys_pc2epc; // @[util.scala:109:23, :700:17]
uops_1_bits_uop_is_rocc <= uops_1_bits_out_uop_is_rocc; // @[util.scala:109:23, :700:17]
uops_1_bits_uop_is_mov <= uops_1_bits_out_uop_is_mov; // @[util.scala:109:23, :700:17]
uops_1_bits_uop_ftq_idx <= uops_1_bits_out_uop_ftq_idx; // @[util.scala:109:23, :700:17]
uops_1_bits_uop_edge_inst <= uops_1_bits_out_uop_edge_inst; // @[util.scala:109:23, :700:17]
uops_1_bits_uop_pc_lob <= uops_1_bits_out_uop_pc_lob; // @[util.scala:109:23, :700:17]
uops_1_bits_uop_taken <= uops_1_bits_out_uop_taken; // @[util.scala:109:23, :700:17]
uops_1_bits_uop_imm_rename <= uops_1_bits_out_uop_imm_rename; // @[util.scala:109:23, :700:17]
uops_1_bits_uop_imm_sel <= uops_1_bits_out_uop_imm_sel; // @[util.scala:109:23, :700:17]
uops_1_bits_uop_pimm <= uops_1_bits_out_uop_pimm; // @[util.scala:109:23, :700:17]
uops_1_bits_uop_imm_packed <= uops_1_bits_out_uop_imm_packed; // @[util.scala:109:23, :700:17]
uops_1_bits_uop_op1_sel <= uops_1_bits_out_uop_op1_sel; // @[util.scala:109:23, :700:17]
uops_1_bits_uop_op2_sel <= uops_1_bits_out_uop_op2_sel; // @[util.scala:109:23, :700:17]
uops_1_bits_uop_fp_ctrl_ldst <= uops_1_bits_out_uop_fp_ctrl_ldst; // @[util.scala:109:23, :700:17]
uops_1_bits_uop_fp_ctrl_wen <= uops_1_bits_out_uop_fp_ctrl_wen; // @[util.scala:109:23, :700:17]
uops_1_bits_uop_fp_ctrl_ren1 <= uops_1_bits_out_uop_fp_ctrl_ren1; // @[util.scala:109:23, :700:17]
uops_1_bits_uop_fp_ctrl_ren2 <= uops_1_bits_out_uop_fp_ctrl_ren2; // @[util.scala:109:23, :700:17]
uops_1_bits_uop_fp_ctrl_ren3 <= uops_1_bits_out_uop_fp_ctrl_ren3; // @[util.scala:109:23, :700:17]
uops_1_bits_uop_fp_ctrl_swap12 <= uops_1_bits_out_uop_fp_ctrl_swap12; // @[util.scala:109:23, :700:17]
uops_1_bits_uop_fp_ctrl_swap23 <= uops_1_bits_out_uop_fp_ctrl_swap23; // @[util.scala:109:23, :700:17]
uops_1_bits_uop_fp_ctrl_typeTagIn <= uops_1_bits_out_uop_fp_ctrl_typeTagIn; // @[util.scala:109:23, :700:17]
uops_1_bits_uop_fp_ctrl_typeTagOut <= uops_1_bits_out_uop_fp_ctrl_typeTagOut; // @[util.scala:109:23, :700:17]
uops_1_bits_uop_fp_ctrl_fromint <= uops_1_bits_out_uop_fp_ctrl_fromint; // @[util.scala:109:23, :700:17]
uops_1_bits_uop_fp_ctrl_toint <= uops_1_bits_out_uop_fp_ctrl_toint; // @[util.scala:109:23, :700:17]
uops_1_bits_uop_fp_ctrl_fastpipe <= uops_1_bits_out_uop_fp_ctrl_fastpipe; // @[util.scala:109:23, :700:17]
uops_1_bits_uop_fp_ctrl_fma <= uops_1_bits_out_uop_fp_ctrl_fma; // @[util.scala:109:23, :700:17]
uops_1_bits_uop_fp_ctrl_div <= uops_1_bits_out_uop_fp_ctrl_div; // @[util.scala:109:23, :700:17]
uops_1_bits_uop_fp_ctrl_sqrt <= uops_1_bits_out_uop_fp_ctrl_sqrt; // @[util.scala:109:23, :700:17]
uops_1_bits_uop_fp_ctrl_wflags <= uops_1_bits_out_uop_fp_ctrl_wflags; // @[util.scala:109:23, :700:17]
uops_1_bits_uop_fp_ctrl_vec <= uops_1_bits_out_uop_fp_ctrl_vec; // @[util.scala:109:23, :700:17]
uops_1_bits_uop_rob_idx <= uops_1_bits_out_uop_rob_idx; // @[util.scala:109:23, :700:17]
uops_1_bits_uop_ldq_idx <= uops_1_bits_out_uop_ldq_idx; // @[util.scala:109:23, :700:17]
uops_1_bits_uop_stq_idx <= uops_1_bits_out_uop_stq_idx; // @[util.scala:109:23, :700:17]
uops_1_bits_uop_rxq_idx <= uops_1_bits_out_uop_rxq_idx; // @[util.scala:109:23, :700:17]
uops_1_bits_uop_pdst <= uops_1_bits_out_uop_pdst; // @[util.scala:109:23, :700:17]
uops_1_bits_uop_prs1 <= uops_1_bits_out_uop_prs1; // @[util.scala:109:23, :700:17]
uops_1_bits_uop_prs2 <= uops_1_bits_out_uop_prs2; // @[util.scala:109:23, :700:17]
uops_1_bits_uop_prs3 <= uops_1_bits_out_uop_prs3; // @[util.scala:109:23, :700:17]
uops_1_bits_uop_ppred <= uops_1_bits_out_uop_ppred; // @[util.scala:109:23, :700:17]
uops_1_bits_uop_prs1_busy <= uops_1_bits_out_uop_prs1_busy; // @[util.scala:109:23, :700:17]
uops_1_bits_uop_prs2_busy <= uops_1_bits_out_uop_prs2_busy; // @[util.scala:109:23, :700:17]
uops_1_bits_uop_prs3_busy <= uops_1_bits_out_uop_prs3_busy; // @[util.scala:109:23, :700:17]
uops_1_bits_uop_ppred_busy <= uops_1_bits_out_uop_ppred_busy; // @[util.scala:109:23, :700:17]
uops_1_bits_uop_stale_pdst <= uops_1_bits_out_uop_stale_pdst; // @[util.scala:109:23, :700:17]
uops_1_bits_uop_exception <= uops_1_bits_out_uop_exception; // @[util.scala:109:23, :700:17]
uops_1_bits_uop_exc_cause <= uops_1_bits_out_uop_exc_cause; // @[util.scala:109:23, :700:17]
uops_1_bits_uop_mem_cmd <= uops_1_bits_out_uop_mem_cmd; // @[util.scala:109:23, :700:17]
uops_1_bits_uop_mem_size <= uops_1_bits_out_uop_mem_size; // @[util.scala:109:23, :700:17]
uops_1_bits_uop_mem_signed <= uops_1_bits_out_uop_mem_signed; // @[util.scala:109:23, :700:17]
uops_1_bits_uop_uses_ldq <= uops_1_bits_out_uop_uses_ldq; // @[util.scala:109:23, :700:17]
uops_1_bits_uop_uses_stq <= uops_1_bits_out_uop_uses_stq; // @[util.scala:109:23, :700:17]
uops_1_bits_uop_is_unique <= uops_1_bits_out_uop_is_unique; // @[util.scala:109:23, :700:17]
uops_1_bits_uop_flush_on_commit <= uops_1_bits_out_uop_flush_on_commit; // @[util.scala:109:23, :700:17]
uops_1_bits_uop_csr_cmd <= uops_1_bits_out_uop_csr_cmd; // @[util.scala:109:23, :700:17]
uops_1_bits_uop_ldst_is_rs1 <= uops_1_bits_out_uop_ldst_is_rs1; // @[util.scala:109:23, :700:17]
uops_1_bits_uop_ldst <= uops_1_bits_out_uop_ldst; // @[util.scala:109:23, :700:17]
uops_1_bits_uop_lrs1 <= uops_1_bits_out_uop_lrs1; // @[util.scala:109:23, :700:17]
uops_1_bits_uop_lrs2 <= uops_1_bits_out_uop_lrs2; // @[util.scala:109:23, :700:17]
uops_1_bits_uop_lrs3 <= uops_1_bits_out_uop_lrs3; // @[util.scala:109:23, :700:17]
uops_1_bits_uop_dst_rtype <= uops_1_bits_out_uop_dst_rtype; // @[util.scala:109:23, :700:17]
uops_1_bits_uop_lrs1_rtype <= uops_1_bits_out_uop_lrs1_rtype; // @[util.scala:109:23, :700:17]
uops_1_bits_uop_lrs2_rtype <= uops_1_bits_out_uop_lrs2_rtype; // @[util.scala:109:23, :700:17]
uops_1_bits_uop_frs3_en <= uops_1_bits_out_uop_frs3_en; // @[util.scala:109:23, :700:17]
uops_1_bits_uop_fcn_dw <= uops_1_bits_out_uop_fcn_dw; // @[util.scala:109:23, :700:17]
uops_1_bits_uop_fcn_op <= uops_1_bits_out_uop_fcn_op; // @[util.scala:109:23, :700:17]
uops_1_bits_uop_fp_val <= uops_1_bits_out_uop_fp_val; // @[util.scala:109:23, :700:17]
uops_1_bits_uop_fp_rm <= uops_1_bits_out_uop_fp_rm; // @[util.scala:109:23, :700:17]
uops_1_bits_uop_fp_typ <= uops_1_bits_out_uop_fp_typ; // @[util.scala:109:23, :700:17]
uops_1_bits_uop_xcpt_pf_if <= uops_1_bits_out_uop_xcpt_pf_if; // @[util.scala:109:23, :700:17]
uops_1_bits_uop_xcpt_ae_if <= uops_1_bits_out_uop_xcpt_ae_if; // @[util.scala:109:23, :700:17]
uops_1_bits_uop_xcpt_ma_if <= uops_1_bits_out_uop_xcpt_ma_if; // @[util.scala:109:23, :700:17]
uops_1_bits_uop_bp_debug_if <= uops_1_bits_out_uop_bp_debug_if; // @[util.scala:109:23, :700:17]
uops_1_bits_uop_bp_xcpt_if <= uops_1_bits_out_uop_bp_xcpt_if; // @[util.scala:109:23, :700:17]
uops_1_bits_uop_debug_fsrc <= uops_1_bits_out_uop_debug_fsrc; // @[util.scala:109:23, :700:17]
uops_1_bits_uop_debug_tsrc <= uops_1_bits_out_uop_debug_tsrc; // @[util.scala:109:23, :700:17]
uops_1_bits_rs1_data <= uops_1_bits_out_rs1_data; // @[util.scala:109:23, :700:17]
uops_1_bits_rs2_data <= uops_1_bits_out_rs2_data; // @[util.scala:109:23, :700:17]
uops_1_bits_rs3_data <= 64'h0; // @[util.scala:700:17]
uops_1_bits_ftq_info_0_valid <= 1'h0; // @[util.scala:700:17]
uops_1_bits_ftq_info_0_entry_cfi_idx_valid <= 1'h0; // @[util.scala:700:17]
uops_1_bits_ftq_info_0_entry_cfi_idx_bits <= 3'h0; // @[util.scala:700:17]
uops_1_bits_ftq_info_0_entry_cfi_taken <= 1'h0; // @[util.scala:700:17]
uops_1_bits_ftq_info_0_entry_cfi_mispredicted <= 1'h0; // @[util.scala:700:17]
uops_1_bits_ftq_info_0_entry_cfi_type <= 3'h0; // @[util.scala:700:17]
uops_1_bits_ftq_info_0_entry_br_mask <= 8'h0; // @[util.scala:700:17]
uops_1_bits_ftq_info_0_entry_cfi_is_call <= 1'h0; // @[util.scala:700:17]
uops_1_bits_ftq_info_0_entry_cfi_is_ret <= 1'h0; // @[util.scala:700:17]
uops_1_bits_ftq_info_0_entry_cfi_npc_plus4 <= 1'h0; // @[util.scala:700:17]
uops_1_bits_ftq_info_0_entry_ras_top <= 40'h0; // @[util.scala:700:17]
uops_1_bits_ftq_info_0_entry_ras_idx <= 5'h0; // @[util.scala:700:17]
uops_1_bits_ftq_info_0_entry_start_bank <= 1'h0; // @[util.scala:700:17]
uops_1_bits_ftq_info_0_ghist_old_history <= 64'h0; // @[util.scala:700:17]
uops_1_bits_ftq_info_0_ghist_current_saw_branch_not_taken <= 1'h0; // @[util.scala:700:17]
uops_1_bits_ftq_info_0_ghist_new_saw_branch_not_taken <= 1'h0; // @[util.scala:700:17]
uops_1_bits_ftq_info_0_ghist_new_saw_branch_taken <= 1'h0; // @[util.scala:700:17]
uops_1_bits_ftq_info_0_ghist_ras_idx <= 5'h0; // @[util.scala:700:17]
uops_1_bits_ftq_info_0_pc <= 40'h0; // @[util.scala:700:17]
uops_1_bits_ftq_info_1_valid <= 1'h0; // @[util.scala:700:17]
uops_1_bits_ftq_info_1_entry_cfi_idx_valid <= 1'h0; // @[util.scala:700:17]
uops_1_bits_ftq_info_1_entry_cfi_idx_bits <= 3'h0; // @[util.scala:700:17]
uops_1_bits_ftq_info_1_entry_cfi_taken <= 1'h0; // @[util.scala:700:17]
uops_1_bits_ftq_info_1_entry_cfi_mispredicted <= 1'h0; // @[util.scala:700:17]
uops_1_bits_ftq_info_1_entry_cfi_type <= 3'h0; // @[util.scala:700:17]
uops_1_bits_ftq_info_1_entry_br_mask <= 8'h0; // @[util.scala:700:17]
uops_1_bits_ftq_info_1_entry_cfi_is_call <= 1'h0; // @[util.scala:700:17]
uops_1_bits_ftq_info_1_entry_cfi_is_ret <= 1'h0; // @[util.scala:700:17]
uops_1_bits_ftq_info_1_entry_cfi_npc_plus4 <= 1'h0; // @[util.scala:700:17]
uops_1_bits_ftq_info_1_entry_ras_top <= 40'h0; // @[util.scala:700:17]
uops_1_bits_ftq_info_1_entry_ras_idx <= 5'h0; // @[util.scala:700:17]
uops_1_bits_ftq_info_1_entry_start_bank <= 1'h0; // @[util.scala:700:17]
uops_1_bits_ftq_info_1_ghist_old_history <= 64'h0; // @[util.scala:700:17]
uops_1_bits_ftq_info_1_ghist_current_saw_branch_not_taken <= 1'h0; // @[util.scala:700:17]
uops_1_bits_ftq_info_1_ghist_new_saw_branch_not_taken <= 1'h0; // @[util.scala:700:17]
uops_1_bits_ftq_info_1_ghist_new_saw_branch_taken <= 1'h0; // @[util.scala:700:17]
uops_1_bits_ftq_info_1_ghist_ras_idx <= 5'h0; // @[util.scala:700:17]
uops_1_bits_ftq_info_1_pc <= 40'h0; // @[util.scala:700:17]
uops_1_bits_pred_data <= 1'h0; // @[util.scala:700:17]
uops_1_bits_imm_data <= uops_1_bits_out_imm_data; // @[util.scala:109:23, :700:17]
uops_2_bits_uop_inst <= uops_2_bits_out_uop_inst; // @[util.scala:109:23, :700:17]
uops_2_bits_uop_debug_inst <= uops_2_bits_out_uop_debug_inst; // @[util.scala:109:23, :700:17]
uops_2_bits_uop_is_rvc <= uops_2_bits_out_uop_is_rvc; // @[util.scala:109:23, :700:17]
uops_2_bits_uop_debug_pc <= uops_2_bits_out_uop_debug_pc; // @[util.scala:109:23, :700:17]
uops_2_bits_uop_iq_type_0 <= uops_2_bits_out_uop_iq_type_0; // @[util.scala:109:23, :700:17]
uops_2_bits_uop_iq_type_1 <= uops_2_bits_out_uop_iq_type_1; // @[util.scala:109:23, :700:17]
uops_2_bits_uop_iq_type_2 <= uops_2_bits_out_uop_iq_type_2; // @[util.scala:109:23, :700:17]
uops_2_bits_uop_iq_type_3 <= uops_2_bits_out_uop_iq_type_3; // @[util.scala:109:23, :700:17]
uops_2_bits_uop_fu_code_0 <= uops_2_bits_out_uop_fu_code_0; // @[util.scala:109:23, :700:17]
uops_2_bits_uop_fu_code_1 <= uops_2_bits_out_uop_fu_code_1; // @[util.scala:109:23, :700:17]
uops_2_bits_uop_fu_code_2 <= uops_2_bits_out_uop_fu_code_2; // @[util.scala:109:23, :700:17]
uops_2_bits_uop_fu_code_3 <= uops_2_bits_out_uop_fu_code_3; // @[util.scala:109:23, :700:17]
uops_2_bits_uop_fu_code_4 <= uops_2_bits_out_uop_fu_code_4; // @[util.scala:109:23, :700:17]
uops_2_bits_uop_fu_code_5 <= uops_2_bits_out_uop_fu_code_5; // @[util.scala:109:23, :700:17]
uops_2_bits_uop_fu_code_6 <= uops_2_bits_out_uop_fu_code_6; // @[util.scala:109:23, :700:17]
uops_2_bits_uop_fu_code_7 <= uops_2_bits_out_uop_fu_code_7; // @[util.scala:109:23, :700:17]
uops_2_bits_uop_fu_code_8 <= uops_2_bits_out_uop_fu_code_8; // @[util.scala:109:23, :700:17]
uops_2_bits_uop_fu_code_9 <= uops_2_bits_out_uop_fu_code_9; // @[util.scala:109:23, :700:17]
uops_2_bits_uop_iw_issued <= uops_2_bits_out_uop_iw_issued; // @[util.scala:109:23, :700:17]
uops_2_bits_uop_iw_issued_partial_agen <= uops_2_bits_out_uop_iw_issued_partial_agen; // @[util.scala:109:23, :700:17]
uops_2_bits_uop_iw_issued_partial_dgen <= uops_2_bits_out_uop_iw_issued_partial_dgen; // @[util.scala:109:23, :700:17]
uops_2_bits_uop_iw_p1_speculative_child <= uops_2_bits_out_uop_iw_p1_speculative_child; // @[util.scala:109:23, :700:17]
uops_2_bits_uop_iw_p2_speculative_child <= uops_2_bits_out_uop_iw_p2_speculative_child; // @[util.scala:109:23, :700:17]
uops_2_bits_uop_iw_p1_bypass_hint <= uops_2_bits_out_uop_iw_p1_bypass_hint; // @[util.scala:109:23, :700:17]
uops_2_bits_uop_iw_p2_bypass_hint <= uops_2_bits_out_uop_iw_p2_bypass_hint; // @[util.scala:109:23, :700:17]
uops_2_bits_uop_iw_p3_bypass_hint <= uops_2_bits_out_uop_iw_p3_bypass_hint; // @[util.scala:109:23, :700:17]
uops_2_bits_uop_dis_col_sel <= uops_2_bits_out_uop_dis_col_sel; // @[util.scala:109:23, :700:17]
uops_2_bits_uop_br_mask <= uops_2_bits_out_uop_br_mask; // @[util.scala:109:23, :700:17]
uops_2_bits_uop_br_tag <= uops_2_bits_out_uop_br_tag; // @[util.scala:109:23, :700:17]
uops_2_bits_uop_br_type <= uops_2_bits_out_uop_br_type; // @[util.scala:109:23, :700:17]
uops_2_bits_uop_is_sfb <= uops_2_bits_out_uop_is_sfb; // @[util.scala:109:23, :700:17]
uops_2_bits_uop_is_fence <= uops_2_bits_out_uop_is_fence; // @[util.scala:109:23, :700:17]
uops_2_bits_uop_is_fencei <= uops_2_bits_out_uop_is_fencei; // @[util.scala:109:23, :700:17]
uops_2_bits_uop_is_sfence <= uops_2_bits_out_uop_is_sfence; // @[util.scala:109:23, :700:17]
uops_2_bits_uop_is_amo <= uops_2_bits_out_uop_is_amo; // @[util.scala:109:23, :700:17]
uops_2_bits_uop_is_eret <= uops_2_bits_out_uop_is_eret; // @[util.scala:109:23, :700:17]
uops_2_bits_uop_is_sys_pc2epc <= uops_2_bits_out_uop_is_sys_pc2epc; // @[util.scala:109:23, :700:17]
uops_2_bits_uop_is_rocc <= uops_2_bits_out_uop_is_rocc; // @[util.scala:109:23, :700:17]
uops_2_bits_uop_is_mov <= uops_2_bits_out_uop_is_mov; // @[util.scala:109:23, :700:17]
uops_2_bits_uop_ftq_idx <= uops_2_bits_out_uop_ftq_idx; // @[util.scala:109:23, :700:17]
uops_2_bits_uop_edge_inst <= uops_2_bits_out_uop_edge_inst; // @[util.scala:109:23, :700:17]
uops_2_bits_uop_pc_lob <= uops_2_bits_out_uop_pc_lob; // @[util.scala:109:23, :700:17]
uops_2_bits_uop_taken <= uops_2_bits_out_uop_taken; // @[util.scala:109:23, :700:17]
uops_2_bits_uop_imm_rename <= uops_2_bits_out_uop_imm_rename; // @[util.scala:109:23, :700:17]
uops_2_bits_uop_imm_sel <= uops_2_bits_out_uop_imm_sel; // @[util.scala:109:23, :700:17]
uops_2_bits_uop_pimm <= uops_2_bits_out_uop_pimm; // @[util.scala:109:23, :700:17]
uops_2_bits_uop_imm_packed <= uops_2_bits_out_uop_imm_packed; // @[util.scala:109:23, :700:17]
uops_2_bits_uop_op1_sel <= uops_2_bits_out_uop_op1_sel; // @[util.scala:109:23, :700:17]
uops_2_bits_uop_op2_sel <= uops_2_bits_out_uop_op2_sel; // @[util.scala:109:23, :700:17]
uops_2_bits_uop_fp_ctrl_ldst <= uops_2_bits_out_uop_fp_ctrl_ldst; // @[util.scala:109:23, :700:17]
uops_2_bits_uop_fp_ctrl_wen <= uops_2_bits_out_uop_fp_ctrl_wen; // @[util.scala:109:23, :700:17]
uops_2_bits_uop_fp_ctrl_ren1 <= uops_2_bits_out_uop_fp_ctrl_ren1; // @[util.scala:109:23, :700:17]
uops_2_bits_uop_fp_ctrl_ren2 <= uops_2_bits_out_uop_fp_ctrl_ren2; // @[util.scala:109:23, :700:17]
uops_2_bits_uop_fp_ctrl_ren3 <= uops_2_bits_out_uop_fp_ctrl_ren3; // @[util.scala:109:23, :700:17]
uops_2_bits_uop_fp_ctrl_swap12 <= uops_2_bits_out_uop_fp_ctrl_swap12; // @[util.scala:109:23, :700:17]
uops_2_bits_uop_fp_ctrl_swap23 <= uops_2_bits_out_uop_fp_ctrl_swap23; // @[util.scala:109:23, :700:17]
uops_2_bits_uop_fp_ctrl_typeTagIn <= uops_2_bits_out_uop_fp_ctrl_typeTagIn; // @[util.scala:109:23, :700:17]
uops_2_bits_uop_fp_ctrl_typeTagOut <= uops_2_bits_out_uop_fp_ctrl_typeTagOut; // @[util.scala:109:23, :700:17]
uops_2_bits_uop_fp_ctrl_fromint <= uops_2_bits_out_uop_fp_ctrl_fromint; // @[util.scala:109:23, :700:17]
uops_2_bits_uop_fp_ctrl_toint <= uops_2_bits_out_uop_fp_ctrl_toint; // @[util.scala:109:23, :700:17]
uops_2_bits_uop_fp_ctrl_fastpipe <= uops_2_bits_out_uop_fp_ctrl_fastpipe; // @[util.scala:109:23, :700:17]
uops_2_bits_uop_fp_ctrl_fma <= uops_2_bits_out_uop_fp_ctrl_fma; // @[util.scala:109:23, :700:17]
uops_2_bits_uop_fp_ctrl_div <= uops_2_bits_out_uop_fp_ctrl_div; // @[util.scala:109:23, :700:17]
uops_2_bits_uop_fp_ctrl_sqrt <= uops_2_bits_out_uop_fp_ctrl_sqrt; // @[util.scala:109:23, :700:17]
uops_2_bits_uop_fp_ctrl_wflags <= uops_2_bits_out_uop_fp_ctrl_wflags; // @[util.scala:109:23, :700:17]
uops_2_bits_uop_fp_ctrl_vec <= uops_2_bits_out_uop_fp_ctrl_vec; // @[util.scala:109:23, :700:17]
uops_2_bits_uop_rob_idx <= uops_2_bits_out_uop_rob_idx; // @[util.scala:109:23, :700:17]
uops_2_bits_uop_ldq_idx <= uops_2_bits_out_uop_ldq_idx; // @[util.scala:109:23, :700:17]
uops_2_bits_uop_stq_idx <= uops_2_bits_out_uop_stq_idx; // @[util.scala:109:23, :700:17]
uops_2_bits_uop_rxq_idx <= uops_2_bits_out_uop_rxq_idx; // @[util.scala:109:23, :700:17]
uops_2_bits_uop_pdst <= uops_2_bits_out_uop_pdst; // @[util.scala:109:23, :700:17]
uops_2_bits_uop_prs1 <= uops_2_bits_out_uop_prs1; // @[util.scala:109:23, :700:17]
uops_2_bits_uop_prs2 <= uops_2_bits_out_uop_prs2; // @[util.scala:109:23, :700:17]
uops_2_bits_uop_prs3 <= uops_2_bits_out_uop_prs3; // @[util.scala:109:23, :700:17]
uops_2_bits_uop_ppred <= uops_2_bits_out_uop_ppred; // @[util.scala:109:23, :700:17]
uops_2_bits_uop_prs1_busy <= uops_2_bits_out_uop_prs1_busy; // @[util.scala:109:23, :700:17]
uops_2_bits_uop_prs2_busy <= uops_2_bits_out_uop_prs2_busy; // @[util.scala:109:23, :700:17]
uops_2_bits_uop_prs3_busy <= uops_2_bits_out_uop_prs3_busy; // @[util.scala:109:23, :700:17]
uops_2_bits_uop_ppred_busy <= uops_2_bits_out_uop_ppred_busy; // @[util.scala:109:23, :700:17]
uops_2_bits_uop_stale_pdst <= uops_2_bits_out_uop_stale_pdst; // @[util.scala:109:23, :700:17]
uops_2_bits_uop_exception <= uops_2_bits_out_uop_exception; // @[util.scala:109:23, :700:17]
uops_2_bits_uop_exc_cause <= uops_2_bits_out_uop_exc_cause; // @[util.scala:109:23, :700:17]
uops_2_bits_uop_mem_cmd <= uops_2_bits_out_uop_mem_cmd; // @[util.scala:109:23, :700:17]
uops_2_bits_uop_mem_size <= uops_2_bits_out_uop_mem_size; // @[util.scala:109:23, :700:17]
uops_2_bits_uop_mem_signed <= uops_2_bits_out_uop_mem_signed; // @[util.scala:109:23, :700:17]
uops_2_bits_uop_uses_ldq <= uops_2_bits_out_uop_uses_ldq; // @[util.scala:109:23, :700:17]
uops_2_bits_uop_uses_stq <= uops_2_bits_out_uop_uses_stq; // @[util.scala:109:23, :700:17]
uops_2_bits_uop_is_unique <= uops_2_bits_out_uop_is_unique; // @[util.scala:109:23, :700:17]
uops_2_bits_uop_flush_on_commit <= uops_2_bits_out_uop_flush_on_commit; // @[util.scala:109:23, :700:17]
uops_2_bits_uop_csr_cmd <= uops_2_bits_out_uop_csr_cmd; // @[util.scala:109:23, :700:17]
uops_2_bits_uop_ldst_is_rs1 <= uops_2_bits_out_uop_ldst_is_rs1; // @[util.scala:109:23, :700:17]
uops_2_bits_uop_ldst <= uops_2_bits_out_uop_ldst; // @[util.scala:109:23, :700:17]
uops_2_bits_uop_lrs1 <= uops_2_bits_out_uop_lrs1; // @[util.scala:109:23, :700:17]
uops_2_bits_uop_lrs2 <= uops_2_bits_out_uop_lrs2; // @[util.scala:109:23, :700:17]
uops_2_bits_uop_lrs3 <= uops_2_bits_out_uop_lrs3; // @[util.scala:109:23, :700:17]
uops_2_bits_uop_dst_rtype <= uops_2_bits_out_uop_dst_rtype; // @[util.scala:109:23, :700:17]
uops_2_bits_uop_lrs1_rtype <= uops_2_bits_out_uop_lrs1_rtype; // @[util.scala:109:23, :700:17]
uops_2_bits_uop_lrs2_rtype <= uops_2_bits_out_uop_lrs2_rtype; // @[util.scala:109:23, :700:17]
uops_2_bits_uop_frs3_en <= uops_2_bits_out_uop_frs3_en; // @[util.scala:109:23, :700:17]
uops_2_bits_uop_fcn_dw <= uops_2_bits_out_uop_fcn_dw; // @[util.scala:109:23, :700:17]
uops_2_bits_uop_fcn_op <= uops_2_bits_out_uop_fcn_op; // @[util.scala:109:23, :700:17]
uops_2_bits_uop_fp_val <= uops_2_bits_out_uop_fp_val; // @[util.scala:109:23, :700:17]
uops_2_bits_uop_fp_rm <= uops_2_bits_out_uop_fp_rm; // @[util.scala:109:23, :700:17]
uops_2_bits_uop_fp_typ <= uops_2_bits_out_uop_fp_typ; // @[util.scala:109:23, :700:17]
uops_2_bits_uop_xcpt_pf_if <= uops_2_bits_out_uop_xcpt_pf_if; // @[util.scala:109:23, :700:17]
uops_2_bits_uop_xcpt_ae_if <= uops_2_bits_out_uop_xcpt_ae_if; // @[util.scala:109:23, :700:17]
uops_2_bits_uop_xcpt_ma_if <= uops_2_bits_out_uop_xcpt_ma_if; // @[util.scala:109:23, :700:17]
uops_2_bits_uop_bp_debug_if <= uops_2_bits_out_uop_bp_debug_if; // @[util.scala:109:23, :700:17]
uops_2_bits_uop_bp_xcpt_if <= uops_2_bits_out_uop_bp_xcpt_if; // @[util.scala:109:23, :700:17]
uops_2_bits_uop_debug_fsrc <= uops_2_bits_out_uop_debug_fsrc; // @[util.scala:109:23, :700:17]
uops_2_bits_uop_debug_tsrc <= uops_2_bits_out_uop_debug_tsrc; // @[util.scala:109:23, :700:17]
uops_2_bits_rs1_data <= uops_2_bits_out_rs1_data; // @[util.scala:109:23, :700:17]
uops_2_bits_rs2_data <= uops_2_bits_out_rs2_data; // @[util.scala:109:23, :700:17]
uops_2_bits_rs3_data <= uops_2_bits_out_rs3_data; // @[util.scala:109:23, :700:17]
uops_2_bits_ftq_info_0_valid <= uops_2_bits_out_ftq_info_0_valid; // @[util.scala:109:23, :700:17]
uops_2_bits_ftq_info_0_entry_cfi_idx_valid <= uops_2_bits_out_ftq_info_0_entry_cfi_idx_valid; // @[util.scala:109:23, :700:17]
uops_2_bits_ftq_info_0_entry_cfi_idx_bits <= uops_2_bits_out_ftq_info_0_entry_cfi_idx_bits; // @[util.scala:109:23, :700:17]
uops_2_bits_ftq_info_0_entry_cfi_taken <= uops_2_bits_out_ftq_info_0_entry_cfi_taken; // @[util.scala:109:23, :700:17]
uops_2_bits_ftq_info_0_entry_cfi_mispredicted <= uops_2_bits_out_ftq_info_0_entry_cfi_mispredicted; // @[util.scala:109:23, :700:17]
uops_2_bits_ftq_info_0_entry_cfi_type <= uops_2_bits_out_ftq_info_0_entry_cfi_type; // @[util.scala:109:23, :700:17]
uops_2_bits_ftq_info_0_entry_br_mask <= uops_2_bits_out_ftq_info_0_entry_br_mask; // @[util.scala:109:23, :700:17]
uops_2_bits_ftq_info_0_entry_cfi_is_call <= uops_2_bits_out_ftq_info_0_entry_cfi_is_call; // @[util.scala:109:23, :700:17]
uops_2_bits_ftq_info_0_entry_cfi_is_ret <= uops_2_bits_out_ftq_info_0_entry_cfi_is_ret; // @[util.scala:109:23, :700:17]
uops_2_bits_ftq_info_0_entry_cfi_npc_plus4 <= uops_2_bits_out_ftq_info_0_entry_cfi_npc_plus4; // @[util.scala:109:23, :700:17]
uops_2_bits_ftq_info_0_entry_ras_top <= uops_2_bits_out_ftq_info_0_entry_ras_top; // @[util.scala:109:23, :700:17]
uops_2_bits_ftq_info_0_entry_ras_idx <= uops_2_bits_out_ftq_info_0_entry_ras_idx; // @[util.scala:109:23, :700:17]
uops_2_bits_ftq_info_0_entry_start_bank <= uops_2_bits_out_ftq_info_0_entry_start_bank; // @[util.scala:109:23, :700:17]
uops_2_bits_ftq_info_0_ghist_old_history <= uops_2_bits_out_ftq_info_0_ghist_old_history; // @[util.scala:109:23, :700:17]
uops_2_bits_ftq_info_0_ghist_current_saw_branch_not_taken <= uops_2_bits_out_ftq_info_0_ghist_current_saw_branch_not_taken; // @[util.scala:109:23, :700:17]
uops_2_bits_ftq_info_0_ghist_new_saw_branch_not_taken <= uops_2_bits_out_ftq_info_0_ghist_new_saw_branch_not_taken; // @[util.scala:109:23, :700:17]
uops_2_bits_ftq_info_0_ghist_new_saw_branch_taken <= uops_2_bits_out_ftq_info_0_ghist_new_saw_branch_taken; // @[util.scala:109:23, :700:17]
uops_2_bits_ftq_info_0_ghist_ras_idx <= uops_2_bits_out_ftq_info_0_ghist_ras_idx; // @[util.scala:109:23, :700:17]
uops_2_bits_ftq_info_0_pc <= uops_2_bits_out_ftq_info_0_pc; // @[util.scala:109:23, :700:17]
uops_2_bits_ftq_info_1_valid <= uops_2_bits_out_ftq_info_1_valid; // @[util.scala:109:23, :700:17]
uops_2_bits_ftq_info_1_entry_cfi_idx_valid <= uops_2_bits_out_ftq_info_1_entry_cfi_idx_valid; // @[util.scala:109:23, :700:17]
uops_2_bits_ftq_info_1_entry_cfi_idx_bits <= uops_2_bits_out_ftq_info_1_entry_cfi_idx_bits; // @[util.scala:109:23, :700:17]
uops_2_bits_ftq_info_1_entry_cfi_taken <= uops_2_bits_out_ftq_info_1_entry_cfi_taken; // @[util.scala:109:23, :700:17]
uops_2_bits_ftq_info_1_entry_cfi_mispredicted <= uops_2_bits_out_ftq_info_1_entry_cfi_mispredicted; // @[util.scala:109:23, :700:17]
uops_2_bits_ftq_info_1_entry_cfi_type <= uops_2_bits_out_ftq_info_1_entry_cfi_type; // @[util.scala:109:23, :700:17]
uops_2_bits_ftq_info_1_entry_br_mask <= uops_2_bits_out_ftq_info_1_entry_br_mask; // @[util.scala:109:23, :700:17]
uops_2_bits_ftq_info_1_entry_cfi_is_call <= uops_2_bits_out_ftq_info_1_entry_cfi_is_call; // @[util.scala:109:23, :700:17]
uops_2_bits_ftq_info_1_entry_cfi_is_ret <= uops_2_bits_out_ftq_info_1_entry_cfi_is_ret; // @[util.scala:109:23, :700:17]
uops_2_bits_ftq_info_1_entry_cfi_npc_plus4 <= uops_2_bits_out_ftq_info_1_entry_cfi_npc_plus4; // @[util.scala:109:23, :700:17]
uops_2_bits_ftq_info_1_entry_ras_top <= uops_2_bits_out_ftq_info_1_entry_ras_top; // @[util.scala:109:23, :700:17]
uops_2_bits_ftq_info_1_entry_ras_idx <= uops_2_bits_out_ftq_info_1_entry_ras_idx; // @[util.scala:109:23, :700:17]
uops_2_bits_ftq_info_1_entry_start_bank <= uops_2_bits_out_ftq_info_1_entry_start_bank; // @[util.scala:109:23, :700:17]
uops_2_bits_ftq_info_1_ghist_old_history <= uops_2_bits_out_ftq_info_1_ghist_old_history; // @[util.scala:109:23, :700:17]
uops_2_bits_ftq_info_1_ghist_current_saw_branch_not_taken <= uops_2_bits_out_ftq_info_1_ghist_current_saw_branch_not_taken; // @[util.scala:109:23, :700:17]
uops_2_bits_ftq_info_1_ghist_new_saw_branch_not_taken <= uops_2_bits_out_ftq_info_1_ghist_new_saw_branch_not_taken; // @[util.scala:109:23, :700:17]
uops_2_bits_ftq_info_1_ghist_new_saw_branch_taken <= uops_2_bits_out_ftq_info_1_ghist_new_saw_branch_taken; // @[util.scala:109:23, :700:17]
uops_2_bits_ftq_info_1_ghist_ras_idx <= uops_2_bits_out_ftq_info_1_ghist_ras_idx; // @[util.scala:109:23, :700:17]
uops_2_bits_ftq_info_1_pc <= uops_2_bits_out_ftq_info_1_pc; // @[util.scala:109:23, :700:17]
uops_2_bits_pred_data <= uops_2_bits_out_pred_data; // @[util.scala:109:23, :700:17]
uops_2_bits_imm_data <= uops_2_bits_out_imm_data; // @[util.scala:109:23, :700:17]
always @(posedge)
assign io_resp_2_valid = io_resp_2_valid_0; // @[util.scala:688:7]
assign io_resp_2_bits_uop_inst = io_resp_2_bits_uop_inst_0; // @[util.scala:688:7]
assign io_resp_2_bits_uop_debug_inst = io_resp_2_bits_uop_debug_inst_0; // @[util.scala:688:7]
assign io_resp_2_bits_uop_is_rvc = io_resp_2_bits_uop_is_rvc_0; // @[util.scala:688:7]
assign io_resp_2_bits_uop_debug_pc = io_resp_2_bits_uop_debug_pc_0; // @[util.scala:688:7]
assign io_resp_2_bits_uop_iq_type_0 = io_resp_2_bits_uop_iq_type_0_0; // @[util.scala:688:7]
assign io_resp_2_bits_uop_iq_type_1 = io_resp_2_bits_uop_iq_type_1_0; // @[util.scala:688:7]
assign io_resp_2_bits_uop_iq_type_2 = io_resp_2_bits_uop_iq_type_2_0; // @[util.scala:688:7]
assign io_resp_2_bits_uop_iq_type_3 = io_resp_2_bits_uop_iq_type_3_0; // @[util.scala:688:7]
assign io_resp_2_bits_uop_fu_code_0 = io_resp_2_bits_uop_fu_code_0_0; // @[util.scala:688:7]
assign io_resp_2_bits_uop_fu_code_1 = io_resp_2_bits_uop_fu_code_1_0; // @[util.scala:688:7]
assign io_resp_2_bits_uop_fu_code_2 = io_resp_2_bits_uop_fu_code_2_0; // @[util.scala:688:7]
assign io_resp_2_bits_uop_fu_code_3 = io_resp_2_bits_uop_fu_code_3_0; // @[util.scala:688:7]
assign io_resp_2_bits_uop_fu_code_4 = io_resp_2_bits_uop_fu_code_4_0; // @[util.scala:688:7]
assign io_resp_2_bits_uop_fu_code_5 = io_resp_2_bits_uop_fu_code_5_0; // @[util.scala:688:7]
assign io_resp_2_bits_uop_fu_code_6 = io_resp_2_bits_uop_fu_code_6_0; // @[util.scala:688:7]
assign io_resp_2_bits_uop_fu_code_7 = io_resp_2_bits_uop_fu_code_7_0; // @[util.scala:688:7]
assign io_resp_2_bits_uop_fu_code_8 = io_resp_2_bits_uop_fu_code_8_0; // @[util.scala:688:7]
assign io_resp_2_bits_uop_fu_code_9 = io_resp_2_bits_uop_fu_code_9_0; // @[util.scala:688:7]
assign io_resp_2_bits_uop_iw_issued = io_resp_2_bits_uop_iw_issued_0; // @[util.scala:688:7]
assign io_resp_2_bits_uop_iw_issued_partial_agen = io_resp_2_bits_uop_iw_issued_partial_agen_0; // @[util.scala:688:7]
assign io_resp_2_bits_uop_iw_issued_partial_dgen = io_resp_2_bits_uop_iw_issued_partial_dgen_0; // @[util.scala:688:7]
assign io_resp_2_bits_uop_iw_p1_speculative_child = io_resp_2_bits_uop_iw_p1_speculative_child_0; // @[util.scala:688:7]
assign io_resp_2_bits_uop_iw_p2_speculative_child = io_resp_2_bits_uop_iw_p2_speculative_child_0; // @[util.scala:688:7]
assign io_resp_2_bits_uop_iw_p1_bypass_hint = io_resp_2_bits_uop_iw_p1_bypass_hint_0; // @[util.scala:688:7]
assign io_resp_2_bits_uop_iw_p2_bypass_hint = io_resp_2_bits_uop_iw_p2_bypass_hint_0; // @[util.scala:688:7]
assign io_resp_2_bits_uop_iw_p3_bypass_hint = io_resp_2_bits_uop_iw_p3_bypass_hint_0; // @[util.scala:688:7]
assign io_resp_2_bits_uop_dis_col_sel = io_resp_2_bits_uop_dis_col_sel_0; // @[util.scala:688:7]
assign io_resp_2_bits_uop_br_mask = io_resp_2_bits_uop_br_mask_0; // @[util.scala:688:7]
assign io_resp_2_bits_uop_br_tag = io_resp_2_bits_uop_br_tag_0; // @[util.scala:688:7]
assign io_resp_2_bits_uop_br_type = io_resp_2_bits_uop_br_type_0; // @[util.scala:688:7]
assign io_resp_2_bits_uop_is_sfb = io_resp_2_bits_uop_is_sfb_0; // @[util.scala:688:7]
assign io_resp_2_bits_uop_is_fence = io_resp_2_bits_uop_is_fence_0; // @[util.scala:688:7]
assign io_resp_2_bits_uop_is_fencei = io_resp_2_bits_uop_is_fencei_0; // @[util.scala:688:7]
assign io_resp_2_bits_uop_is_sfence = io_resp_2_bits_uop_is_sfence_0; // @[util.scala:688:7]
assign io_resp_2_bits_uop_is_amo = io_resp_2_bits_uop_is_amo_0; // @[util.scala:688:7]
assign io_resp_2_bits_uop_is_eret = io_resp_2_bits_uop_is_eret_0; // @[util.scala:688:7]
assign io_resp_2_bits_uop_is_sys_pc2epc = io_resp_2_bits_uop_is_sys_pc2epc_0; // @[util.scala:688:7]
assign io_resp_2_bits_uop_is_rocc = io_resp_2_bits_uop_is_rocc_0; // @[util.scala:688:7]
assign io_resp_2_bits_uop_is_mov = io_resp_2_bits_uop_is_mov_0; // @[util.scala:688:7]
assign io_resp_2_bits_uop_ftq_idx = io_resp_2_bits_uop_ftq_idx_0; // @[util.scala:688:7]
assign io_resp_2_bits_uop_edge_inst = io_resp_2_bits_uop_edge_inst_0; // @[util.scala:688:7]
assign io_resp_2_bits_uop_pc_lob = io_resp_2_bits_uop_pc_lob_0; // @[util.scala:688:7]
assign io_resp_2_bits_uop_taken = io_resp_2_bits_uop_taken_0; // @[util.scala:688:7]
assign io_resp_2_bits_uop_imm_rename = io_resp_2_bits_uop_imm_rename_0; // @[util.scala:688:7]
assign io_resp_2_bits_uop_imm_sel = io_resp_2_bits_uop_imm_sel_0; // @[util.scala:688:7]
assign io_resp_2_bits_uop_pimm = io_resp_2_bits_uop_pimm_0; // @[util.scala:688:7]
assign io_resp_2_bits_uop_imm_packed = io_resp_2_bits_uop_imm_packed_0; // @[util.scala:688:7]
assign io_resp_2_bits_uop_op1_sel = io_resp_2_bits_uop_op1_sel_0; // @[util.scala:688:7]
assign io_resp_2_bits_uop_op2_sel = io_resp_2_bits_uop_op2_sel_0; // @[util.scala:688:7]
assign io_resp_2_bits_uop_fp_ctrl_ldst = io_resp_2_bits_uop_fp_ctrl_ldst_0; // @[util.scala:688:7]
assign io_resp_2_bits_uop_fp_ctrl_wen = io_resp_2_bits_uop_fp_ctrl_wen_0; // @[util.scala:688:7]
assign io_resp_2_bits_uop_fp_ctrl_ren1 = io_resp_2_bits_uop_fp_ctrl_ren1_0; // @[util.scala:688:7]
assign io_resp_2_bits_uop_fp_ctrl_ren2 = io_resp_2_bits_uop_fp_ctrl_ren2_0; // @[util.scala:688:7]
assign io_resp_2_bits_uop_fp_ctrl_ren3 = io_resp_2_bits_uop_fp_ctrl_ren3_0; // @[util.scala:688:7]
assign io_resp_2_bits_uop_fp_ctrl_swap12 = io_resp_2_bits_uop_fp_ctrl_swap12_0; // @[util.scala:688:7]
assign io_resp_2_bits_uop_fp_ctrl_swap23 = io_resp_2_bits_uop_fp_ctrl_swap23_0; // @[util.scala:688:7]
assign io_resp_2_bits_uop_fp_ctrl_typeTagIn = io_resp_2_bits_uop_fp_ctrl_typeTagIn_0; // @[util.scala:688:7]
assign io_resp_2_bits_uop_fp_ctrl_typeTagOut = io_resp_2_bits_uop_fp_ctrl_typeTagOut_0; // @[util.scala:688:7]
assign io_resp_2_bits_uop_fp_ctrl_fromint = io_resp_2_bits_uop_fp_ctrl_fromint_0; // @[util.scala:688:7]
assign io_resp_2_bits_uop_fp_ctrl_toint = io_resp_2_bits_uop_fp_ctrl_toint_0; // @[util.scala:688:7]
assign io_resp_2_bits_uop_fp_ctrl_fastpipe = io_resp_2_bits_uop_fp_ctrl_fastpipe_0; // @[util.scala:688:7]
assign io_resp_2_bits_uop_fp_ctrl_fma = io_resp_2_bits_uop_fp_ctrl_fma_0; // @[util.scala:688:7]
assign io_resp_2_bits_uop_fp_ctrl_div = io_resp_2_bits_uop_fp_ctrl_div_0; // @[util.scala:688:7]
assign io_resp_2_bits_uop_fp_ctrl_sqrt = io_resp_2_bits_uop_fp_ctrl_sqrt_0; // @[util.scala:688:7]
assign io_resp_2_bits_uop_fp_ctrl_wflags = io_resp_2_bits_uop_fp_ctrl_wflags_0; // @[util.scala:688:7]
assign io_resp_2_bits_uop_fp_ctrl_vec = io_resp_2_bits_uop_fp_ctrl_vec_0; // @[util.scala:688:7]
assign io_resp_2_bits_uop_rob_idx = io_resp_2_bits_uop_rob_idx_0; // @[util.scala:688:7]
assign io_resp_2_bits_uop_ldq_idx = io_resp_2_bits_uop_ldq_idx_0; // @[util.scala:688:7]
assign io_resp_2_bits_uop_stq_idx = io_resp_2_bits_uop_stq_idx_0; // @[util.scala:688:7]
assign io_resp_2_bits_uop_rxq_idx = io_resp_2_bits_uop_rxq_idx_0; // @[util.scala:688:7]
assign io_resp_2_bits_uop_pdst = io_resp_2_bits_uop_pdst_0; // @[util.scala:688:7]
assign io_resp_2_bits_uop_prs1 = io_resp_2_bits_uop_prs1_0; // @[util.scala:688:7]
assign io_resp_2_bits_uop_prs2 = io_resp_2_bits_uop_prs2_0; // @[util.scala:688:7]
assign io_resp_2_bits_uop_prs3 = io_resp_2_bits_uop_prs3_0; // @[util.scala:688:7]
assign io_resp_2_bits_uop_ppred = io_resp_2_bits_uop_ppred_0; // @[util.scala:688:7]
assign io_resp_2_bits_uop_prs1_busy = io_resp_2_bits_uop_prs1_busy_0; // @[util.scala:688:7]
assign io_resp_2_bits_uop_prs2_busy = io_resp_2_bits_uop_prs2_busy_0; // @[util.scala:688:7]
assign io_resp_2_bits_uop_prs3_busy = io_resp_2_bits_uop_prs3_busy_0; // @[util.scala:688:7]
assign io_resp_2_bits_uop_ppred_busy = io_resp_2_bits_uop_ppred_busy_0; // @[util.scala:688:7]
assign io_resp_2_bits_uop_stale_pdst = io_resp_2_bits_uop_stale_pdst_0; // @[util.scala:688:7]
assign io_resp_2_bits_uop_exception = io_resp_2_bits_uop_exception_0; // @[util.scala:688:7]
assign io_resp_2_bits_uop_exc_cause = io_resp_2_bits_uop_exc_cause_0; // @[util.scala:688:7]
assign io_resp_2_bits_uop_mem_cmd = io_resp_2_bits_uop_mem_cmd_0; // @[util.scala:688:7]
assign io_resp_2_bits_uop_mem_size = io_resp_2_bits_uop_mem_size_0; // @[util.scala:688:7]
assign io_resp_2_bits_uop_mem_signed = io_resp_2_bits_uop_mem_signed_0; // @[util.scala:688:7]
assign io_resp_2_bits_uop_uses_ldq = io_resp_2_bits_uop_uses_ldq_0; // @[util.scala:688:7]
assign io_resp_2_bits_uop_uses_stq = io_resp_2_bits_uop_uses_stq_0; // @[util.scala:688:7]
assign io_resp_2_bits_uop_is_unique = io_resp_2_bits_uop_is_unique_0; // @[util.scala:688:7]
assign io_resp_2_bits_uop_flush_on_commit = io_resp_2_bits_uop_flush_on_commit_0; // @[util.scala:688:7]
assign io_resp_2_bits_uop_csr_cmd = io_resp_2_bits_uop_csr_cmd_0; // @[util.scala:688:7]
assign io_resp_2_bits_uop_ldst_is_rs1 = io_resp_2_bits_uop_ldst_is_rs1_0; // @[util.scala:688:7]
assign io_resp_2_bits_uop_ldst = io_resp_2_bits_uop_ldst_0; // @[util.scala:688:7]
assign io_resp_2_bits_uop_lrs1 = io_resp_2_bits_uop_lrs1_0; // @[util.scala:688:7]
assign io_resp_2_bits_uop_lrs2 = io_resp_2_bits_uop_lrs2_0; // @[util.scala:688:7]
assign io_resp_2_bits_uop_lrs3 = io_resp_2_bits_uop_lrs3_0; // @[util.scala:688:7]
assign io_resp_2_bits_uop_dst_rtype = io_resp_2_bits_uop_dst_rtype_0; // @[util.scala:688:7]
assign io_resp_2_bits_uop_lrs1_rtype = io_resp_2_bits_uop_lrs1_rtype_0; // @[util.scala:688:7]
assign io_resp_2_bits_uop_lrs2_rtype = io_resp_2_bits_uop_lrs2_rtype_0; // @[util.scala:688:7]
assign io_resp_2_bits_uop_frs3_en = io_resp_2_bits_uop_frs3_en_0; // @[util.scala:688:7]
assign io_resp_2_bits_uop_fcn_dw = io_resp_2_bits_uop_fcn_dw_0; // @[util.scala:688:7]
assign io_resp_2_bits_uop_fcn_op = io_resp_2_bits_uop_fcn_op_0; // @[util.scala:688:7]
assign io_resp_2_bits_uop_fp_val = io_resp_2_bits_uop_fp_val_0; // @[util.scala:688:7]
assign io_resp_2_bits_uop_fp_rm = io_resp_2_bits_uop_fp_rm_0; // @[util.scala:688:7]
assign io_resp_2_bits_uop_fp_typ = io_resp_2_bits_uop_fp_typ_0; // @[util.scala:688:7]
assign io_resp_2_bits_uop_xcpt_pf_if = io_resp_2_bits_uop_xcpt_pf_if_0; // @[util.scala:688:7]
assign io_resp_2_bits_uop_xcpt_ae_if = io_resp_2_bits_uop_xcpt_ae_if_0; // @[util.scala:688:7]
assign io_resp_2_bits_uop_xcpt_ma_if = io_resp_2_bits_uop_xcpt_ma_if_0; // @[util.scala:688:7]
assign io_resp_2_bits_uop_bp_debug_if = io_resp_2_bits_uop_bp_debug_if_0; // @[util.scala:688:7]
assign io_resp_2_bits_uop_bp_xcpt_if = io_resp_2_bits_uop_bp_xcpt_if_0; // @[util.scala:688:7]
assign io_resp_2_bits_uop_debug_fsrc = io_resp_2_bits_uop_debug_fsrc_0; // @[util.scala:688:7]
assign io_resp_2_bits_uop_debug_tsrc = io_resp_2_bits_uop_debug_tsrc_0; // @[util.scala:688:7]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File ShiftRegisterPriorityQueue.scala:
package compressacc
import chisel3._
import chisel3.util._
import chisel3.util._
// TODO : support enq & deq at the same cycle
class PriorityQueueStageIO(keyWidth: Int, value: ValueInfo) extends Bundle {
val output_prev = KeyValue(keyWidth, value)
val output_nxt = KeyValue(keyWidth, value)
val input_prev = Flipped(KeyValue(keyWidth, value))
val input_nxt = Flipped(KeyValue(keyWidth, value))
val cmd = Flipped(Valid(UInt(1.W)))
val insert_here = Input(Bool())
val cur_input_keyval = Flipped(KeyValue(keyWidth, value))
val cur_output_keyval = KeyValue(keyWidth, value)
}
class PriorityQueueStage(keyWidth: Int, value: ValueInfo) extends Module {
val io = IO(new PriorityQueueStageIO(keyWidth, value))
dontTouch(io)
val CMD_DEQ = 0.U
val CMD_ENQ = 1.U
val MAX_VALUE = (1 << keyWidth) - 1
val key_reg = RegInit(MAX_VALUE.U(keyWidth.W))
val value_reg = Reg(value)
io.output_prev.key := key_reg
io.output_prev.value := value_reg
io.output_nxt.key := key_reg
io.output_nxt.value := value_reg
io.cur_output_keyval.key := key_reg
io.cur_output_keyval.value := value_reg
when (io.cmd.valid) {
switch (io.cmd.bits) {
is (CMD_DEQ) {
key_reg := io.input_nxt.key
value_reg := io.input_nxt.value
}
is (CMD_ENQ) {
when (io.insert_here) {
key_reg := io.cur_input_keyval.key
value_reg := io.cur_input_keyval.value
} .elsewhen (key_reg >= io.cur_input_keyval.key) {
key_reg := io.input_prev.key
value_reg := io.input_prev.value
} .otherwise {
// do nothing
}
}
}
}
}
object PriorityQueueStage {
def apply(keyWidth: Int, v: ValueInfo): PriorityQueueStage = new PriorityQueueStage(keyWidth, v)
}
// TODO
// - This design is not scalable as the enqued_keyval is broadcasted to all the stages
// - Add pipeline registers later
class PriorityQueueIO(queSize: Int, keyWidth: Int, value: ValueInfo) extends Bundle {
val cnt_bits = log2Ceil(queSize+1)
val counter = Output(UInt(cnt_bits.W))
val enq = Flipped(Decoupled(KeyValue(keyWidth, value)))
val deq = Decoupled(KeyValue(keyWidth, value))
}
class PriorityQueue(queSize: Int, keyWidth: Int, value: ValueInfo) extends Module {
val keyWidthInternal = keyWidth + 1
val CMD_DEQ = 0.U
val CMD_ENQ = 1.U
val io = IO(new PriorityQueueIO(queSize, keyWidthInternal, value))
dontTouch(io)
val MAX_VALUE = ((1 << keyWidthInternal) - 1).U
val cnt_bits = log2Ceil(queSize+1)
// do not consider cases where we are inserting more entries then the queSize
val counter = RegInit(0.U(cnt_bits.W))
io.counter := counter
val full = (counter === queSize.U)
val empty = (counter === 0.U)
io.deq.valid := !empty
io.enq.ready := !full
when (io.enq.fire) {
counter := counter + 1.U
}
when (io.deq.fire) {
counter := counter - 1.U
}
val cmd_valid = io.enq.valid || io.deq.ready
val cmd = Mux(io.enq.valid, CMD_ENQ, CMD_DEQ)
assert(!(io.enq.valid && io.deq.ready))
val stages = Seq.fill(queSize)(Module(new PriorityQueueStage(keyWidthInternal, value)))
for (i <- 0 until (queSize - 1)) {
stages(i+1).io.input_prev <> stages(i).io.output_nxt
stages(i).io.input_nxt <> stages(i+1).io.output_prev
}
stages(queSize-1).io.input_nxt.key := MAX_VALUE
// stages(queSize-1).io.input_nxt.value :=
stages(queSize-1).io.input_nxt.value.symbol := 0.U
// stages(queSize-1).io.input_nxt.value.child(0) := 0.U
// stages(queSize-1).io.input_nxt.value.child(1) := 0.U
stages(0).io.input_prev.key := io.enq.bits.key
stages(0).io.input_prev.value <> io.enq.bits.value
for (i <- 0 until queSize) {
stages(i).io.cmd.valid := cmd_valid
stages(i).io.cmd.bits := cmd
stages(i).io.cur_input_keyval <> io.enq.bits
}
val is_large_or_equal = WireInit(VecInit(Seq.fill(queSize)(false.B)))
for (i <- 0 until queSize) {
is_large_or_equal(i) := (stages(i).io.cur_output_keyval.key >= io.enq.bits.key)
}
val is_large_or_equal_cat = Wire(UInt(queSize.W))
is_large_or_equal_cat := Cat(is_large_or_equal.reverse)
val insert_here_idx = PriorityEncoder(is_large_or_equal_cat)
for (i <- 0 until queSize) {
when (i.U === insert_here_idx) {
stages(i).io.insert_here := true.B
} .otherwise {
stages(i).io.insert_here := false.B
}
}
io.deq.bits <> stages(0).io.output_prev
}
| module PriorityQueueStage_238( // @[ShiftRegisterPriorityQueue.scala:21:7]
input clock, // @[ShiftRegisterPriorityQueue.scala:21:7]
input reset, // @[ShiftRegisterPriorityQueue.scala:21:7]
output [30:0] io_output_prev_key, // @[ShiftRegisterPriorityQueue.scala:22:14]
output [9:0] io_output_prev_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14]
output [30:0] io_output_nxt_key, // @[ShiftRegisterPriorityQueue.scala:22:14]
output [9:0] io_output_nxt_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14]
input [30:0] io_input_prev_key, // @[ShiftRegisterPriorityQueue.scala:22:14]
input [9:0] io_input_prev_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14]
input [30:0] io_input_nxt_key, // @[ShiftRegisterPriorityQueue.scala:22:14]
input [9:0] io_input_nxt_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14]
input io_cmd_valid, // @[ShiftRegisterPriorityQueue.scala:22:14]
input io_cmd_bits, // @[ShiftRegisterPriorityQueue.scala:22:14]
input io_insert_here, // @[ShiftRegisterPriorityQueue.scala:22:14]
input [30:0] io_cur_input_keyval_key, // @[ShiftRegisterPriorityQueue.scala:22:14]
input [9:0] io_cur_input_keyval_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14]
output [30:0] io_cur_output_keyval_key, // @[ShiftRegisterPriorityQueue.scala:22:14]
output [9:0] io_cur_output_keyval_value_symbol // @[ShiftRegisterPriorityQueue.scala:22:14]
);
wire [30:0] io_input_prev_key_0 = io_input_prev_key; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [9:0] io_input_prev_value_symbol_0 = io_input_prev_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [30:0] io_input_nxt_key_0 = io_input_nxt_key; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [9:0] io_input_nxt_value_symbol_0 = io_input_nxt_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire io_cmd_valid_0 = io_cmd_valid; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire io_cmd_bits_0 = io_cmd_bits; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire io_insert_here_0 = io_insert_here; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [30:0] io_cur_input_keyval_key_0 = io_cur_input_keyval_key; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [9:0] io_cur_input_keyval_value_symbol_0 = io_cur_input_keyval_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [9:0] io_output_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [30:0] io_output_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [9:0] io_output_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [30:0] io_output_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [9:0] io_cur_output_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [30:0] io_cur_output_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
reg [30:0] key_reg; // @[ShiftRegisterPriorityQueue.scala:30:24]
assign io_output_prev_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]
assign io_output_nxt_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]
assign io_cur_output_keyval_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]
reg [9:0] value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:31:22]
assign io_output_prev_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]
assign io_output_nxt_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]
assign io_cur_output_keyval_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]
wire _T_2 = key_reg >= io_cur_input_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24, :52:30]
always @(posedge clock) begin // @[ShiftRegisterPriorityQueue.scala:21:7]
if (reset) // @[ShiftRegisterPriorityQueue.scala:21:7]
key_reg <= 31'h7FFFFFFF; // @[ShiftRegisterPriorityQueue.scala:30:24]
else if (io_cmd_valid_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7]
if (io_cmd_bits_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7]
if (io_insert_here_0) // @[ShiftRegisterPriorityQueue.scala:21:7]
key_reg <= io_cur_input_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]
else if (_T_2) // @[ShiftRegisterPriorityQueue.scala:52:30]
key_reg <= io_input_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]
end
else // @[ShiftRegisterPriorityQueue.scala:21:7]
key_reg <= io_input_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]
end
if (io_cmd_valid_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7]
if (io_cmd_bits_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7]
if (io_insert_here_0) // @[ShiftRegisterPriorityQueue.scala:21:7]
value_reg_symbol <= io_cur_input_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]
else if (_T_2) // @[ShiftRegisterPriorityQueue.scala:52:30]
value_reg_symbol <= io_input_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]
end
else // @[ShiftRegisterPriorityQueue.scala:21:7]
value_reg_symbol <= io_input_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]
end
always @(posedge)
assign io_output_prev_key = io_output_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
assign io_output_prev_value_symbol = io_output_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
assign io_output_nxt_key = io_output_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
assign io_output_nxt_value_symbol = io_output_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
assign io_cur_output_keyval_key = io_cur_output_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
assign io_cur_output_keyval_value_symbol = io_cur_output_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File Crossing.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.interrupts
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy.lazymodule._
import freechips.rocketchip.util.{SynchronizerShiftReg, AsyncResetReg}
@deprecated("IntXing does not ensure interrupt source is glitch free. Use IntSyncSource and IntSyncSink", "rocket-chip 1.2")
class IntXing(sync: Int = 3)(implicit p: Parameters) extends LazyModule
{
val intnode = IntAdapterNode()
lazy val module = new Impl
class Impl extends LazyModuleImp(this) {
(intnode.in zip intnode.out) foreach { case ((in, _), (out, _)) =>
out := SynchronizerShiftReg(in, sync)
}
}
}
object IntSyncCrossingSource
{
def apply(alreadyRegistered: Boolean = false)(implicit p: Parameters) =
{
val intsource = LazyModule(new IntSyncCrossingSource(alreadyRegistered))
intsource.node
}
}
class IntSyncCrossingSource(alreadyRegistered: Boolean = false)(implicit p: Parameters) extends LazyModule
{
val node = IntSyncSourceNode(alreadyRegistered)
lazy val module = if (alreadyRegistered) (new ImplRegistered) else (new Impl)
class Impl extends LazyModuleImp(this) {
def outSize = node.out.headOption.map(_._1.sync.size).getOrElse(0)
override def desiredName = s"IntSyncCrossingSource_n${node.out.size}x${outSize}"
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
out.sync := AsyncResetReg(Cat(in.reverse)).asBools
}
}
class ImplRegistered extends LazyRawModuleImp(this) {
def outSize = node.out.headOption.map(_._1.sync.size).getOrElse(0)
override def desiredName = s"IntSyncCrossingSource_n${node.out.size}x${outSize}_Registered"
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
out.sync := in
}
}
}
object IntSyncCrossingSink
{
@deprecated("IntSyncCrossingSink which used the `sync` parameter to determine crossing type is deprecated. Use IntSyncAsyncCrossingSink, IntSyncRationalCrossingSink, or IntSyncSyncCrossingSink instead for > 1, 1, and 0 sync values respectively", "rocket-chip 1.2")
def apply(sync: Int = 3)(implicit p: Parameters) =
{
val intsink = LazyModule(new IntSyncAsyncCrossingSink(sync))
intsink.node
}
}
class IntSyncAsyncCrossingSink(sync: Int = 3)(implicit p: Parameters) extends LazyModule
{
val node = IntSyncSinkNode(sync)
lazy val module = new Impl
class Impl extends LazyModuleImp(this) {
override def desiredName = s"IntSyncAsyncCrossingSink_n${node.out.size}x${node.out.head._1.size}"
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
out := SynchronizerShiftReg(in.sync, sync)
}
}
}
object IntSyncAsyncCrossingSink
{
def apply(sync: Int = 3)(implicit p: Parameters) =
{
val intsink = LazyModule(new IntSyncAsyncCrossingSink(sync))
intsink.node
}
}
class IntSyncSyncCrossingSink()(implicit p: Parameters) extends LazyModule
{
val node = IntSyncSinkNode(0)
lazy val module = new Impl
class Impl extends LazyRawModuleImp(this) {
def outSize = node.out.headOption.map(_._1.size).getOrElse(0)
override def desiredName = s"IntSyncSyncCrossingSink_n${node.out.size}x${outSize}"
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
out := in.sync
}
}
}
object IntSyncSyncCrossingSink
{
def apply()(implicit p: Parameters) =
{
val intsink = LazyModule(new IntSyncSyncCrossingSink())
intsink.node
}
}
class IntSyncRationalCrossingSink()(implicit p: Parameters) extends LazyModule
{
val node = IntSyncSinkNode(1)
lazy val module = new Impl
class Impl extends LazyModuleImp(this) {
def outSize = node.out.headOption.map(_._1.size).getOrElse(0)
override def desiredName = s"IntSyncRationalCrossingSink_n${node.out.size}x${outSize}"
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
out := RegNext(in.sync)
}
}
}
object IntSyncRationalCrossingSink
{
def apply()(implicit p: Parameters) =
{
val intsink = LazyModule(new IntSyncRationalCrossingSink())
intsink.node
}
}
File LazyModuleImp.scala:
package org.chipsalliance.diplomacy.lazymodule
import chisel3.{withClockAndReset, Module, RawModule, Reset, _}
import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo}
import firrtl.passes.InlineAnnotation
import org.chipsalliance.cde.config.Parameters
import org.chipsalliance.diplomacy.nodes.Dangle
import scala.collection.immutable.SortedMap
/** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]].
*
* This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy.
*/
sealed trait LazyModuleImpLike extends RawModule {
/** [[LazyModule]] that contains this instance. */
val wrapper: LazyModule
/** IOs that will be automatically "punched" for this instance. */
val auto: AutoBundle
/** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */
protected[diplomacy] val dangles: Seq[Dangle]
// [[wrapper.module]] had better not be accessed while LazyModules are still being built!
require(
LazyModule.scope.isEmpty,
s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}"
)
/** Set module name. Defaults to the containing LazyModule's desiredName. */
override def desiredName: String = wrapper.desiredName
suggestName(wrapper.suggestedName)
/** [[Parameters]] for chisel [[Module]]s. */
implicit val p: Parameters = wrapper.p
/** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and
* submodules.
*/
protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = {
// 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]],
// 2. return [[Dangle]]s from each module.
val childDangles = wrapper.children.reverse.flatMap { c =>
implicit val sourceInfo: SourceInfo = c.info
c.cloneProto.map { cp =>
// If the child is a clone, then recursively set cloneProto of its children as well
def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = {
require(bases.size == clones.size)
(bases.zip(clones)).map { case (l, r) =>
require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}")
l.cloneProto = Some(r)
assignCloneProtos(l.children, r.children)
}
}
assignCloneProtos(c.children, cp.children)
// Clone the child module as a record, and get its [[AutoBundle]]
val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName)
val clonedAuto = clone("auto").asInstanceOf[AutoBundle]
// Get the empty [[Dangle]]'s of the cloned child
val rawDangles = c.cloneDangles()
require(rawDangles.size == clonedAuto.elements.size)
// Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s
val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) }
dangles
}.getOrElse {
// For non-clones, instantiate the child module
val mod = try {
Module(c.module)
} catch {
case e: ChiselException => {
println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}")
throw e
}
}
mod.dangles
}
}
// Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]].
// This will result in a sequence of [[Dangle]] from these [[BaseNode]]s.
val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate())
// Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]]
val allDangles = nodeDangles ++ childDangles
// Group [[allDangles]] by their [[source]].
val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*)
// For each [[source]] set of [[Dangle]]s of size 2, ensure that these
// can be connected as a source-sink pair (have opposite flipped value).
// Make the connection and mark them as [[done]].
val done = Set() ++ pairing.values.filter(_.size == 2).map {
case Seq(a, b) =>
require(a.flipped != b.flipped)
// @todo <> in chisel3 makes directionless connection.
if (a.flipped) {
a.data <> b.data
} else {
b.data <> a.data
}
a.source
case _ => None
}
// Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module.
val forward = allDangles.filter(d => !done(d.source))
// Generate [[AutoBundle]] IO from [[forward]].
val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*))
// Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]]
val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) =>
if (d.flipped) {
d.data <> io
} else {
io <> d.data
}
d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name)
}
// Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]].
wrapper.inModuleBody.reverse.foreach {
_()
}
if (wrapper.shouldBeInlined) {
chisel3.experimental.annotate(new ChiselAnnotation {
def toFirrtl = InlineAnnotation(toNamed)
})
}
// Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]].
(auto, dangles)
}
}
/** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike {
/** Instantiate hardware of this `Module`. */
val (auto, dangles) = instantiate()
}
/** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike {
// These wires are the default clock+reset for all LazyModule children.
// It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the
// [[LazyRawModuleImp]] children.
// Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly.
/** drive clock explicitly. */
val childClock: Clock = Wire(Clock())
/** drive reset explicitly. */
val childReset: Reset = Wire(Reset())
// the default is that these are disabled
childClock := false.B.asClock
childReset := chisel3.DontCare
def provideImplicitClockToLazyChildren: Boolean = false
val (auto, dangles) =
if (provideImplicitClockToLazyChildren) {
withClockAndReset(childClock, childReset) { instantiate() }
} else {
instantiate()
}
}
File MixedNode.scala:
package org.chipsalliance.diplomacy.nodes
import chisel3.{Data, DontCare, Wire}
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.{Field, Parameters}
import org.chipsalliance.diplomacy.ValName
import org.chipsalliance.diplomacy.sourceLine
/** One side metadata of a [[Dangle]].
*
* Describes one side of an edge going into or out of a [[BaseNode]].
*
* @param serial
* the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to.
* @param index
* the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to.
*/
case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] {
import scala.math.Ordered.orderingToOrdered
def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that))
}
/** [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]]
* connects.
*
* [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] ,
* [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]].
*
* @param source
* the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within
* that [[BaseNode]].
* @param sink
* sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that
* [[BaseNode]].
* @param flipped
* flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to
* `danglesIn`.
* @param dataOpt
* actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module
*/
case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) {
def data = dataOpt.get
}
/** [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often
* derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually
* implement the protocol.
*/
case class Edges[EI, EO](in: Seq[EI], out: Seq[EO])
/** A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. */
case object MonitorsEnabled extends Field[Boolean](true)
/** When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented.
*
* For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but
* [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink
* nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the
* [[LazyModule]].
*/
case object RenderFlipped extends Field[Boolean](false)
/** The sealed node class in the package, all node are derived from it.
*
* @param inner
* Sink interface implementation.
* @param outer
* Source interface implementation.
* @param valName
* val name of this node.
* @tparam DI
* Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters
* describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected
* [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port
* parameters.
* @tparam UI
* Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing
* the protocol parameters of a sink. For an [[InwardNode]], it is determined itself.
* @tparam EI
* Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers
* specified for a sink according to protocol.
* @tparam BI
* Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface.
* It should extends from [[chisel3.Data]], which represents the real hardware.
* @tparam DO
* Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters
* describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself.
* @tparam UO
* Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing
* the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]].
* Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters.
* @tparam EO
* Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers
* specified for a source according to protocol.
* @tparam BO
* Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source
* interface. It should extends from [[chisel3.Data]], which represents the real hardware.
*
* @note
* Call Graph of [[MixedNode]]
* - line `─`: source is process by a function and generate pass to others
* - Arrow `→`: target of arrow is generated by source
*
* {{{
* (from the other node)
* ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐
* ↓ │
* (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │
* [[InwardNode.accPI]] │ │ │
* │ │ (based on protocol) │
* │ │ [[MixedNode.inner.edgeI]] │
* │ │ ↓ │
* ↓ │ │ │
* (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │
* [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │
* │ │ ↑ │ │ │
* │ │ │ [[OutwardNode.doParams]] │ │
* │ │ │ (from the other node) │ │
* │ │ │ │ │ │
* │ │ │ │ │ │
* │ │ │ └────────┬──────────────┤ │
* │ │ │ │ │ │
* │ │ │ │ (based on protocol) │
* │ │ │ │ [[MixedNode.inner.edgeI]] │
* │ │ │ │ │ │
* │ │ (from the other node) │ ↓ │
* │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │
* │ ↑ ↑ │ │ ↓ │
* │ │ │ │ │ [[MixedNode.in]] │
* │ │ │ │ ↓ ↑ │
* │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │
* ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │
* │ │ │ [[MixedNode.bundleOut]]─┐ │ │
* │ │ │ ↑ ↓ │ │
* │ │ │ │ [[MixedNode.out]] │ │
* │ ↓ ↓ │ ↑ │ │
* │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │
* │ │ (from the other node) ↑ │ │
* │ │ │ │ │ │
* │ │ │ [[MixedNode.outer.edgeO]] │ │
* │ │ │ (based on protocol) │ │
* │ │ │ │ │ │
* │ │ │ ┌────────────────────────────────────────┤ │ │
* │ │ │ │ │ │ │
* │ │ │ │ │ │ │
* │ │ │ │ │ │ │
* (immobilize after elaboration)│ ↓ │ │ │ │
* [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │
* ↑ (inward port from [[OutwardNode]]) │ │ │ │
* │ ┌─────────────────────────────────────────┤ │ │ │
* │ │ │ │ │ │
* │ │ │ │ │ │
* [[OutwardNode.accPO]] │ ↓ │ │ │
* (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │
* │ ↑ │ │
* │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │
* └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘
* }}}
*/
abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data](
val inner: InwardNodeImp[DI, UI, EI, BI],
val outer: OutwardNodeImp[DO, UO, EO, BO]
)(
implicit valName: ValName)
extends BaseNode
with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO]
with InwardNode[DI, UI, BI]
with OutwardNode[DO, UO, BO] {
// Generate a [[NodeHandle]] with inward and outward node are both this node.
val inward = this
val outward = this
/** Debug info of nodes binding. */
def bindingInfo: String = s"""$iBindingInfo
|$oBindingInfo
|""".stripMargin
/** Debug info of ports connecting. */
def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}]
|${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}]
|""".stripMargin
/** Debug info of parameters propagations. */
def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}]
|${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}]
|${diParams.size} downstream inward parameters: [${diParams.mkString(",")}]
|${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}]
|""".stripMargin
/** For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and
* [[MixedNode.iPortMapping]].
*
* Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward
* stars and outward stars.
*
* This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type
* of node.
*
* @param iKnown
* Number of known-size ([[BIND_ONCE]]) input bindings.
* @param oKnown
* Number of known-size ([[BIND_ONCE]]) output bindings.
* @param iStar
* Number of unknown size ([[BIND_STAR]]) input bindings.
* @param oStar
* Number of unknown size ([[BIND_STAR]]) output bindings.
* @return
* A Tuple of the resolved number of input and output connections.
*/
protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int)
/** Function to generate downward-flowing outward params from the downward-flowing input params and the current output
* ports.
*
* @param n
* The size of the output sequence to generate.
* @param p
* Sequence of downward-flowing input parameters of this node.
* @return
* A `n`-sized sequence of downward-flowing output edge parameters.
*/
protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO]
/** Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]].
*
* @param n
* Size of the output sequence.
* @param p
* Upward-flowing output edge parameters.
* @return
* A n-sized sequence of upward-flowing input edge parameters.
*/
protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI]
/** @return
* The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with
* [[BIND_STAR]].
*/
protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR)
/** @return
* The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of
* output bindings bound with [[BIND_STAR]].
*/
protected[diplomacy] lazy val sourceCard: Int =
iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR)
/** @return list of nodes involved in flex bindings with this node. */
protected[diplomacy] lazy val flexes: Seq[BaseNode] =
oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2)
/** Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin
* greedily taking up the remaining connections.
*
* @return
* A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return
* value is not relevant.
*/
protected[diplomacy] lazy val flexOffset: Int = {
/** Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex
* operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a
* connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of
* each node in the current set and decide whether they should be added to the set or not.
*
* @return
* the mapping of [[BaseNode]] indexed by their serial numbers.
*/
def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = {
if (visited.contains(v.serial) || !v.flexibleArityDirection) {
visited
} else {
v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum))
}
}
/** Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node.
*
* @example
* {{{
* a :*=* b :*=* c
* d :*=* b
* e :*=* f
* }}}
*
* `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)`
*/
val flexSet = DFS(this, Map()).values
/** The total number of :*= operators where we're on the left. */
val allSink = flexSet.map(_.sinkCard).sum
/** The total number of :=* operators used when we're on the right. */
val allSource = flexSet.map(_.sourceCard).sum
require(
allSink == 0 || allSource == 0,
s"The nodes ${flexSet.map(_.name)} which are inter-connected by :*=* have ${allSink} :*= operators and ${allSource} :=* operators connected to them, making it impossible to determine cardinality inference direction."
)
allSink - allSource
}
/** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. */
protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = {
if (flexibleArityDirection) flexOffset
else if (n.flexibleArityDirection) n.flexOffset
else 0
}
/** For a node which is connected between two nodes, select the one that will influence the direction of the flex
* resolution.
*/
protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = {
val dir = edgeArityDirection(n)
if (dir < 0) l
else if (dir > 0) r
else 1
}
/** Ensure that the same node is not visited twice in resolving `:*=`, etc operators. */
private var starCycleGuard = false
/** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star"
* connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also
* need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct
* edge parameters and later build up correct bundle connections.
*
* [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding
* operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort
* (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N :*= foo` or `N :*=* foo :*=
* bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo :*=* N`
*/
protected[diplomacy] lazy val (
oPortMapping: Seq[(Int, Int)],
iPortMapping: Seq[(Int, Int)],
oStar: Int,
iStar: Int
) = {
try {
if (starCycleGuard) throw StarCycleException()
starCycleGuard = true
// For a given node N...
// Number of foo :=* N
// + Number of bar :=* foo :*=* N
val oStars = oBindings.count { case (_, n, b, _, _) =>
b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) < 0)
}
// Number of N :*= foo
// + Number of N :*=* foo :*= bar
val iStars = iBindings.count { case (_, n, b, _, _) =>
b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) > 0)
}
// 1 for foo := N
// + bar.iStar for bar :*= foo :*=* N
// + foo.iStar for foo :*= N
// + 0 for foo :=* N
val oKnown = oBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, 0, n.iStar)
case BIND_QUERY => n.iStar
case BIND_STAR => 0
}
}.sum
// 1 for N := foo
// + bar.oStar for N :*=* foo :=* bar
// + foo.oStar for N :=* foo
// + 0 for N :*= foo
val iKnown = iBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, n.oStar, 0)
case BIND_QUERY => n.oStar
case BIND_STAR => 0
}
}.sum
// Resolve star depends on the node subclass to implement the algorithm for this.
val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars)
// Cumulative list of resolved outward binding range starting points
val oSum = oBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar)
case BIND_QUERY => n.iStar
case BIND_STAR => oStar
}
}.scanLeft(0)(_ + _)
// Cumulative list of resolved inward binding range starting points
val iSum = iBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar)
case BIND_QUERY => n.oStar
case BIND_STAR => iStar
}
}.scanLeft(0)(_ + _)
// Create ranges for each binding based on the running sums and return
// those along with resolved values for the star operations.
(oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar)
} catch {
case c: StarCycleException => throw c.copy(loop = context +: c.loop)
}
}
/** Sequence of inward ports.
*
* This should be called after all star bindings are resolved.
*
* Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding.
* `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this
* connection was made in the source code.
*/
protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] =
oBindings.flatMap { case (i, n, _, p, s) =>
// for each binding operator in this node, look at what it connects to
val (start, end) = n.iPortMapping(i)
(start until end).map { j => (j, n, p, s) }
}
/** Sequence of outward ports.
*
* This should be called after all star bindings are resolved.
*
* `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of
* outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection
* was made in the source code.
*/
protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] =
iBindings.flatMap { case (i, n, _, p, s) =>
// query this port index range of this node in the other side of node.
val (start, end) = n.oPortMapping(i)
(start until end).map { j => (j, n, p, s) }
}
// Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree
// Thus, there must exist an Eulerian path and the below algorithms terminate
@scala.annotation.tailrec
private def oTrace(
tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)
): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match {
case (i, n, p, s) => n.iForward(i) match {
case None => (i, n, p, s)
case Some((j, m)) => oTrace((j, m, p, s))
}
}
@scala.annotation.tailrec
private def iTrace(
tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)
): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match {
case (i, n, p, s) => n.oForward(i) match {
case None => (i, n, p, s)
case Some((j, m)) => iTrace((j, m, p, s))
}
}
/** Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved.
*
* Each Port is a tuple of:
* - Numeric index of this binding in the [[InwardNode]] on the other end.
* - [[InwardNode]] on the other end of this binding.
* - A view of [[Parameters]] where the binding occurred.
* - [[SourceInfo]] for source-level error reporting.
*/
lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace)
/** Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved.
*
* Each Port is a tuple of:
* - numeric index of this binding in [[OutwardNode]] on the other end.
* - [[OutwardNode]] on the other end of this binding.
* - a view of [[Parameters]] where the binding occurred.
* - [[SourceInfo]] for source-level error reporting.
*/
lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace)
private var oParamsCycleGuard = false
protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) }
protected[diplomacy] lazy val doParams: Seq[DO] = {
try {
if (oParamsCycleGuard) throw DownwardCycleException()
oParamsCycleGuard = true
val o = mapParamsD(oPorts.size, diParams)
require(
o.size == oPorts.size,
s"""Diplomacy has detected a problem with your graph:
|At the following node, the number of outward ports should equal the number of produced outward parameters.
|$context
|$connectedPortsInfo
|Downstreamed inward parameters: [${diParams.mkString(",")}]
|Produced outward parameters: [${o.mkString(",")}]
|""".stripMargin
)
o.map(outer.mixO(_, this))
} catch {
case c: DownwardCycleException => throw c.copy(loop = context +: c.loop)
}
}
private var iParamsCycleGuard = false
protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) }
protected[diplomacy] lazy val uiParams: Seq[UI] = {
try {
if (iParamsCycleGuard) throw UpwardCycleException()
iParamsCycleGuard = true
val i = mapParamsU(iPorts.size, uoParams)
require(
i.size == iPorts.size,
s"""Diplomacy has detected a problem with your graph:
|At the following node, the number of inward ports should equal the number of produced inward parameters.
|$context
|$connectedPortsInfo
|Upstreamed outward parameters: [${uoParams.mkString(",")}]
|Produced inward parameters: [${i.mkString(",")}]
|""".stripMargin
)
i.map(inner.mixI(_, this))
} catch {
case c: UpwardCycleException => throw c.copy(loop = context +: c.loop)
}
}
/** Outward edge parameters. */
protected[diplomacy] lazy val edgesOut: Seq[EO] =
(oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) }
/** Inward edge parameters. */
protected[diplomacy] lazy val edgesIn: Seq[EI] =
(iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) }
/** A tuple of the input edge parameters and output edge parameters for the edges bound to this node.
*
* If you need to access to the edges of a foreign Node, use this method (in/out create bundles).
*/
lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut)
/** Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. */
protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e =>
val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out")
// TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue,
// In the future, we should add an option to decide whether allowing unconnected in the LazyModule
x := DontCare
x
}
/** Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. */
protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e =>
val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In")
// TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue,
// In the future, we should add an option to decide whether allowing unconnected in the LazyModule
x := DontCare
x
}
private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) =>
Dangle(
source = HalfEdge(serial, i),
sink = HalfEdge(n.serial, j),
flipped = false,
name = wirePrefix + "out",
dataOpt = None
)
}
private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) =>
Dangle(
source = HalfEdge(n.serial, j),
sink = HalfEdge(serial, i),
flipped = true,
name = wirePrefix + "in",
dataOpt = None
)
}
/** Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. */
protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) =>
d.copy(dataOpt = Some(bundleOut(i)))
}
/** Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. */
protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) =>
d.copy(dataOpt = Some(bundleIn(i)))
}
private[diplomacy] var instantiated = false
/** Gather Bundle and edge parameters of outward ports.
*
* Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within
* [[LazyModuleImp]] code or after its instantiation has completed.
*/
def out: Seq[(BO, EO)] = {
require(
instantiated,
s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun"
)
bundleOut.zip(edgesOut)
}
/** Gather Bundle and edge parameters of inward ports.
*
* Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within
* [[LazyModuleImp]] code or after its instantiation has completed.
*/
def in: Seq[(BI, EI)] = {
require(
instantiated,
s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun"
)
bundleIn.zip(edgesIn)
}
/** Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires,
* instantiate monitors on all input ports if appropriate, and return all the dangles of this node.
*/
protected[diplomacy] def instantiate(): Seq[Dangle] = {
instantiated = true
if (!circuitIdentity) {
(iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) }
}
danglesOut ++ danglesIn
}
protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn
/** Connects the outward part of a node with the inward part of this node. */
protected[diplomacy] def bind(
h: OutwardNode[DI, UI, BI],
binding: NodeBinding
)(
implicit p: Parameters,
sourceInfo: SourceInfo
): Unit = {
val x = this // x := y
val y = h
sourceLine(sourceInfo, " at ", "")
val i = x.iPushed
val o = y.oPushed
y.oPush(
i,
x,
binding match {
case BIND_ONCE => BIND_ONCE
case BIND_FLEX => BIND_FLEX
case BIND_STAR => BIND_QUERY
case BIND_QUERY => BIND_STAR
}
)
x.iPush(o, y, binding)
}
/* Metadata for printing the node graph. */
def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) =>
val re = inner.render(e)
(n, re.copy(flipped = re.flipped != p(RenderFlipped)))
}
/** Metadata for printing the node graph */
def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) }
}
| module IntSyncSyncCrossingSink_n1x1_23( // @[Crossing.scala:96:9]
input auto_in_sync_0, // @[LazyModuleImp.scala:107:25]
output auto_out_0 // @[LazyModuleImp.scala:107:25]
);
wire auto_in_sync_0_0 = auto_in_sync_0; // @[Crossing.scala:96:9]
wire childClock = 1'h0; // @[LazyModuleImp.scala:155:31]
wire childReset = 1'h0; // @[LazyModuleImp.scala:158:31]
wire _childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25]
wire nodeIn_sync_0 = auto_in_sync_0_0; // @[Crossing.scala:96:9]
wire nodeOut_0; // @[MixedNode.scala:542:17]
wire auto_out_0_0; // @[Crossing.scala:96:9]
assign nodeOut_0 = nodeIn_sync_0; // @[MixedNode.scala:542:17, :551:17]
assign auto_out_0_0 = nodeOut_0; // @[Crossing.scala:96:9]
assign auto_out_0 = auto_out_0_0; // @[Crossing.scala:96:9]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File Transposer.scala:
package gemmini
import chisel3._
import chisel3.util._
import Util._
trait Transposer[T <: Data] extends Module {
def dim: Int
def dataType: T
val io = IO(new Bundle {
val inRow = Flipped(Decoupled(Vec(dim, dataType)))
val outCol = Decoupled(Vec(dim, dataType))
})
}
class PipelinedTransposer[T <: Data](val dim: Int, val dataType: T) extends Transposer[T] {
require(isPow2(dim))
val regArray = Seq.fill(dim, dim)(Reg(dataType))
val regArrayT = regArray.transpose
val sMoveUp :: sMoveLeft :: Nil = Enum(2)
val state = RegInit(sMoveUp)
val leftCounter = RegInit(0.U(log2Ceil(dim+1).W)) //(io.inRow.fire && state === sMoveLeft, dim+1)
val upCounter = RegInit(0.U(log2Ceil(dim+1).W)) //Counter(io.inRow.fire && state === sMoveUp, dim+1)
io.outCol.valid := 0.U
io.inRow.ready := 0.U
switch(state) {
is(sMoveUp) {
io.inRow.ready := upCounter <= dim.U
io.outCol.valid := leftCounter > 0.U
when(io.inRow.fire) {
upCounter := upCounter + 1.U
}
when(upCounter === (dim-1).U) {
state := sMoveLeft
leftCounter := 0.U
}
when(io.outCol.fire) {
leftCounter := leftCounter - 1.U
}
}
is(sMoveLeft) {
io.inRow.ready := leftCounter <= dim.U // TODO: this is naive
io.outCol.valid := upCounter > 0.U
when(leftCounter === (dim-1).U) {
state := sMoveUp
}
when(io.inRow.fire) {
leftCounter := leftCounter + 1.U
upCounter := 0.U
}
when(io.outCol.fire) {
upCounter := upCounter - 1.U
}
}
}
// Propagate input from bottom row to top row systolically in the move up phase
// TODO: need to iterate over columns to connect Chisel values of type T
// Should be able to operate directly on the Vec, but Seq and Vec don't mix (try Array?)
for (colIdx <- 0 until dim) {
regArray.foldRight(io.inRow.bits(colIdx)) {
case (regRow, prevReg) =>
when (state === sMoveUp) {
regRow(colIdx) := prevReg
}
regRow(colIdx)
}
}
// Propagate input from right side to left side systolically in the move left phase
for (rowIdx <- 0 until dim) {
regArrayT.foldRight(io.inRow.bits(rowIdx)) {
case (regCol, prevReg) =>
when (state === sMoveLeft) {
regCol(rowIdx) := prevReg
}
regCol(rowIdx)
}
}
// Pull from the left side or the top side based on the state
for (idx <- 0 until dim) {
when (state === sMoveUp) {
io.outCol.bits(idx) := regArray(0)(idx)
}.elsewhen(state === sMoveLeft) {
io.outCol.bits(idx) := regArrayT(0)(idx)
}.otherwise {
io.outCol.bits(idx) := DontCare
}
}
}
class AlwaysOutTransposer[T <: Data](val dim: Int, val dataType: T) extends Transposer[T] {
require(isPow2(dim))
val LEFT_DIR = 0.U(1.W)
val UP_DIR = 1.U(1.W)
class PE extends Module {
val io = IO(new Bundle {
val inR = Input(dataType)
val inD = Input(dataType)
val outL = Output(dataType)
val outU = Output(dataType)
val dir = Input(UInt(1.W))
val en = Input(Bool())
})
val reg = RegEnable(Mux(io.dir === LEFT_DIR, io.inR, io.inD), io.en)
io.outU := reg
io.outL := reg
}
val pes = Seq.fill(dim,dim)(Module(new PE))
val counter = RegInit(0.U((log2Ceil(dim) max 1).W)) // TODO replace this with a standard Chisel counter
val dir = RegInit(LEFT_DIR)
// Wire up horizontal signals
for (row <- 0 until dim; col <- 0 until dim) {
val right_in = if (col == dim-1) io.inRow.bits(row) else pes(row)(col+1).io.outL
pes(row)(col).io.inR := right_in
}
// Wire up vertical signals
for (row <- 0 until dim; col <- 0 until dim) {
val down_in = if (row == dim-1) io.inRow.bits(col) else pes(row+1)(col).io.outU
pes(row)(col).io.inD := down_in
}
// Wire up global signals
pes.flatten.foreach(_.io.dir := dir)
pes.flatten.foreach(_.io.en := io.inRow.fire)
io.outCol.valid := true.B
io.inRow.ready := true.B
val left_out = VecInit(pes.transpose.head.map(_.io.outL))
val up_out = VecInit(pes.head.map(_.io.outU))
io.outCol.bits := Mux(dir === LEFT_DIR, left_out, up_out)
when (io.inRow.fire) {
counter := wrappingAdd(counter, 1.U, dim)
}
when (counter === (dim-1).U && io.inRow.fire) {
dir := ~dir
}
}
class NaiveTransposer[T <: Data](val dim: Int, val dataType: T) extends Transposer[T] {
val regArray = Seq.fill(dim, dim)(Reg(dataType))
val regArrayT = regArray.transpose
// state = 0 => filling regArray row-wise, state = 1 => draining regArray column-wise
val state = RegInit(0.U(1.W))
val countInc = io.inRow.fire || io.outCol.fire
val (countValue, countWrap) = Counter(countInc, dim)
io.inRow.ready := state === 0.U
io.outCol.valid := state === 1.U
for (i <- 0 until dim) {
for (j <- 0 until dim) {
when(countValue === i.U && io.inRow.fire) {
regArray(i)(j) := io.inRow.bits(j)
}
}
}
for (i <- 0 until dim) {
io.outCol.bits(i) := 0.U
for (j <- 0 until dim) {
when(countValue === j.U) {
io.outCol.bits(i) := regArrayT(j)(i)
}
}
}
when (io.inRow.fire && countWrap) {
state := 1.U
}
when (io.outCol.fire && countWrap) {
state := 0.U
}
assert(!(state === 0.U) || !io.outCol.fire)
assert(!(state === 1.U) || !io.inRow.fire)
}
| module PE_29( // @[Transposer.scala:100:9]
input clock, // @[Transposer.scala:100:9]
input reset, // @[Transposer.scala:100:9]
input [7:0] io_inR, // @[Transposer.scala:101:16]
input [7:0] io_inD, // @[Transposer.scala:101:16]
output [7:0] io_outL, // @[Transposer.scala:101:16]
output [7:0] io_outU, // @[Transposer.scala:101:16]
input io_dir, // @[Transposer.scala:101:16]
input io_en // @[Transposer.scala:101:16]
);
wire [7:0] io_inR_0 = io_inR; // @[Transposer.scala:100:9]
wire [7:0] io_inD_0 = io_inD; // @[Transposer.scala:100:9]
wire io_dir_0 = io_dir; // @[Transposer.scala:100:9]
wire io_en_0 = io_en; // @[Transposer.scala:100:9]
wire [7:0] io_outL_0; // @[Transposer.scala:100:9]
wire [7:0] io_outU_0; // @[Transposer.scala:100:9]
wire _reg_T = ~io_dir_0; // @[Transposer.scala:100:9, :110:36]
wire [7:0] _reg_T_1 = _reg_T ? io_inR_0 : io_inD_0; // @[Transposer.scala:100:9, :110:{28,36}]
reg [7:0] reg_0; // @[Transposer.scala:110:24]
assign io_outL_0 = reg_0; // @[Transposer.scala:100:9, :110:24]
assign io_outU_0 = reg_0; // @[Transposer.scala:100:9, :110:24]
always @(posedge clock) begin // @[Transposer.scala:100:9]
if (io_en_0) // @[Transposer.scala:100:9]
reg_0 <= _reg_T_1; // @[Transposer.scala:110:{24,28}]
always @(posedge)
assign io_outL = io_outL_0; // @[Transposer.scala:100:9]
assign io_outU = io_outU_0; // @[Transposer.scala:100:9]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File Monitor.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceLine
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import freechips.rocketchip.diplomacy.EnableMonitors
import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode}
import freechips.rocketchip.util.PlusArg
case class TLMonitorArgs(edge: TLEdge)
abstract class TLMonitorBase(args: TLMonitorArgs) extends Module
{
val io = IO(new Bundle {
val in = Input(new TLBundle(args.edge.bundle))
})
def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit
legalize(io.in, args.edge, reset)
}
object TLMonitor {
def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = {
if (enable) {
EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) }
} else { node }
}
}
class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args)
{
require (args.edge.params(TLMonitorStrictMode) || (! args.edge.params(TestplanTestType).formal))
val cover_prop_class = PropertyClass.Default
//Like assert but can flip to being an assumption for formal verification
def monAssert(cond: Bool, message: String): Unit =
if (monitorDir == MonitorDirection.Monitor) {
assert(cond, message)
} else {
Property(monitorDir, cond, message, PropertyClass.Default)
}
def assume(cond: Bool, message: String): Unit =
if (monitorDir == MonitorDirection.Monitor) {
assert(cond, message)
} else {
Property(monitorDir.flip, cond, message, PropertyClass.Default)
}
def extra = {
args.edge.sourceInfo match {
case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)"
case _ => ""
}
}
def visible(address: UInt, source: UInt, edge: TLEdge) =
edge.client.clients.map { c =>
!c.sourceId.contains(source) ||
c.visibility.map(_.contains(address)).reduce(_ || _)
}.reduce(_ && _)
def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = {
//switch this flag to turn on diplomacy in error messages
def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n"
monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra)
// Reuse these subexpressions to save some firrtl lines
val source_ok = edge.client.contains(bundle.source)
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val mask = edge.full_mask(bundle)
monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility")
//The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B
//TODO: check for acquireT?
when (bundle.opcode === TLMessages.AcquireBlock) {
monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra)
monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra)
monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra)
monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra)
}
when (bundle.opcode === TLMessages.AcquirePerm) {
monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra)
monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra)
monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra)
monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra)
monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra)
}
when (bundle.opcode === TLMessages.Get) {
monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra)
monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra)
monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra)
}
when (bundle.opcode === TLMessages.PutFullData) {
monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra)
monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.PutPartialData) {
monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra)
monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.ArithmeticData) {
monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra)
monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.LogicalData) {
monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra)
monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.Hint) {
monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra)
monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra)
}
}
def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = {
monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra)
monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility")
// Reuse these subexpressions to save some firrtl lines
val address_ok = edge.manager.containsSafe(edge.address(bundle))
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val mask = edge.full_mask(bundle)
val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source
when (bundle.opcode === TLMessages.Probe) {
assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra)
assume (address_ok, "'B' channel Probe carries unmanaged address" + extra)
assume (legal_source, "'B' channel Probe carries source that is not first source" + extra)
assume (is_aligned, "'B' channel Probe address not aligned to size" + extra)
assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra)
assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra)
assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra)
}
when (bundle.opcode === TLMessages.Get) {
monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra)
monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra)
}
when (bundle.opcode === TLMessages.PutFullData) {
monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra)
monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.PutPartialData) {
monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra)
monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.ArithmeticData) {
monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra)
monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra)
monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.LogicalData) {
monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra)
monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra)
monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.Hint) {
monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra)
monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra)
monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra)
}
}
def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = {
monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra)
val source_ok = edge.client.contains(bundle.source)
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val address_ok = edge.manager.containsSafe(edge.address(bundle))
monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility")
when (bundle.opcode === TLMessages.ProbeAck) {
monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra)
monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra)
}
when (bundle.opcode === TLMessages.ProbeAckData) {
monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra)
}
when (bundle.opcode === TLMessages.Release) {
monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra)
monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra)
monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra)
}
when (bundle.opcode === TLMessages.ReleaseData) {
monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra)
monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra)
}
when (bundle.opcode === TLMessages.AccessAck) {
monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra)
monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra)
}
when (bundle.opcode === TLMessages.AccessAckData) {
monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra)
}
when (bundle.opcode === TLMessages.HintAck) {
monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra)
monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra)
}
}
def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = {
assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra)
val source_ok = edge.client.contains(bundle.source)
val sink_ok = bundle.sink < edge.manager.endSinkId.U
val deny_put_ok = edge.manager.mayDenyPut.B
val deny_get_ok = edge.manager.mayDenyGet.B
when (bundle.opcode === TLMessages.ReleaseAck) {
assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra)
assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra)
assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra)
}
when (bundle.opcode === TLMessages.Grant) {
assume (source_ok, "'D' channel Grant carries invalid source ID" + extra)
assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra)
assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra)
assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra)
assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel Grant is denied" + extra)
}
when (bundle.opcode === TLMessages.GrantData) {
assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra)
assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra)
assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra)
assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra)
assume (!bundle.denied || bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra)
assume (deny_get_ok || !bundle.denied, "'D' channel GrantData is denied" + extra)
}
when (bundle.opcode === TLMessages.AccessAck) {
assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel AccessAck is denied" + extra)
}
when (bundle.opcode === TLMessages.AccessAckData) {
assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra)
assume (!bundle.denied || bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra)
assume (deny_get_ok || !bundle.denied, "'D' channel AccessAckData is denied" + extra)
}
when (bundle.opcode === TLMessages.HintAck) {
assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel HintAck is denied" + extra)
}
}
def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = {
val sink_ok = bundle.sink < edge.manager.endSinkId.U
monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra)
}
def legalizeFormat(bundle: TLBundle, edge: TLEdge) = {
when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) }
when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) }
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) }
when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) }
when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) }
} else {
monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra)
monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra)
monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra)
}
}
def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = {
val a_first = edge.first(a.bits, a.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (a.valid && !a_first) {
monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra)
monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra)
monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra)
monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra)
monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra)
}
when (a.fire && a_first) {
opcode := a.bits.opcode
param := a.bits.param
size := a.bits.size
source := a.bits.source
address := a.bits.address
}
}
def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = {
val b_first = edge.first(b.bits, b.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (b.valid && !b_first) {
monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra)
monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra)
monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra)
monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra)
monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra)
}
when (b.fire && b_first) {
opcode := b.bits.opcode
param := b.bits.param
size := b.bits.size
source := b.bits.source
address := b.bits.address
}
}
def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = {
// Symbolic variable
val sym_source = Wire(UInt(edge.client.endSourceId.W))
// TODO: Connect sym_source to a fixed value for simulation and to a
// free wire in formal
sym_source := 0.U
// Type casting Int to UInt
val maxSourceId = Wire(UInt(edge.client.endSourceId.W))
maxSourceId := edge.client.endSourceId.U
// Delayed verison of sym_source
val sym_source_d = Reg(UInt(edge.client.endSourceId.W))
sym_source_d := sym_source
// These will be constraints for FV setup
Property(
MonitorDirection.Monitor,
(sym_source === sym_source_d),
"sym_source should remain stable",
PropertyClass.Default)
Property(
MonitorDirection.Monitor,
(sym_source <= maxSourceId),
"sym_source should take legal value",
PropertyClass.Default)
val my_resp_pend = RegInit(false.B)
val my_opcode = Reg(UInt())
val my_size = Reg(UInt())
val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire)
val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire)
val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source)
val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source)
val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat)
val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend)
when (my_set_resp_pend) {
my_resp_pend := true.B
} .elsewhen (my_clr_resp_pend) {
my_resp_pend := false.B
}
when (my_a_first_beat) {
my_opcode := bundle.a.bits.opcode
my_size := bundle.a.bits.size
}
val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size)
val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode)
val my_resp_opcode_legal = Wire(Bool())
when ((my_resp_opcode === TLMessages.Get) || (my_resp_opcode === TLMessages.ArithmeticData) ||
(my_resp_opcode === TLMessages.LogicalData)) {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData)
} .elsewhen ((my_resp_opcode === TLMessages.PutFullData) || (my_resp_opcode === TLMessages.PutPartialData)) {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck)
} .otherwise {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck)
}
monAssert (IfThen(my_resp_pend, !my_a_first_beat),
"Request message should not be sent with a source ID, for which a response message" +
"is already pending (not received until current cycle) for a prior request message" +
"with the same source ID" + extra)
assume (IfThen(my_clr_resp_pend, (my_set_resp_pend || my_resp_pend)),
"Response message should be accepted with a source ID only if a request message with the" +
"same source ID has been accepted or is being accepted in the current cycle" + extra)
assume (IfThen(my_d_first_beat, (my_a_first_beat || my_resp_pend)),
"Response message should be sent with a source ID only if a request message with the" +
"same source ID has been accepted or is being sent in the current cycle" + extra)
assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)),
"If d_valid is 1, then d_size should be same as a_size of the corresponding request" +
"message" + extra)
assume (IfThen(my_d_first_beat, my_resp_opcode_legal),
"If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" +
"request message" + extra)
}
def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = {
val c_first = edge.first(c.bits, c.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (c.valid && !c_first) {
monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra)
monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra)
monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra)
monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra)
monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra)
}
when (c.fire && c_first) {
opcode := c.bits.opcode
param := c.bits.param
size := c.bits.size
source := c.bits.source
address := c.bits.address
}
}
def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = {
val d_first = edge.first(d.bits, d.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val sink = Reg(UInt())
val denied = Reg(Bool())
when (d.valid && !d_first) {
assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra)
assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra)
assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra)
assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra)
assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra)
assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra)
}
when (d.fire && d_first) {
opcode := d.bits.opcode
param := d.bits.param
size := d.bits.size
source := d.bits.source
sink := d.bits.sink
denied := d.bits.denied
}
}
def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = {
legalizeMultibeatA(bundle.a, edge)
legalizeMultibeatD(bundle.d, edge)
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
legalizeMultibeatB(bundle.b, edge)
legalizeMultibeatC(bundle.c, edge)
}
}
//This is left in for almond which doesn't adhere to the tilelink protocol
@deprecated("Use legalizeADSource instead if possible","")
def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = {
val inflight = RegInit(0.U(edge.client.endSourceId.W))
val a_first = edge.first(bundle.a.bits, bundle.a.fire)
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
val a_set = WireInit(0.U(edge.client.endSourceId.W))
when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) {
a_set := UIntToOH(bundle.a.bits.source)
assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra)
}
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
assume((a_set | inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra)
}
if (edge.manager.minLatency > 0) {
assume(a_set =/= d_clr || !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra)
}
inflight := (inflight | a_set) & ~d_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
assert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = {
val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset)
val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything
val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size)
val log_a_size_bus_size = log2Ceil(a_size_bus_size)
def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits
val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error
inflight.suggestName("inflight")
val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
inflight_opcodes.suggestName("inflight_opcodes")
val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
inflight_sizes.suggestName("inflight_sizes")
val a_first = edge.first(bundle.a.bits, bundle.a.fire)
a_first.suggestName("a_first")
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
d_first.suggestName("d_first")
val a_set = WireInit(0.U(edge.client.endSourceId.W))
val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
a_set.suggestName("a_set")
a_set_wo_ready.suggestName("a_set_wo_ready")
val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
a_opcodes_set.suggestName("a_opcodes_set")
val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
a_sizes_set.suggestName("a_sizes_set")
val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W))
a_opcode_lookup.suggestName("a_opcode_lookup")
a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U
val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W))
a_size_lookup.suggestName("a_size_lookup")
a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U
val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant))
val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant))
val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W))
a_opcodes_set_interm.suggestName("a_opcodes_set_interm")
val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W))
a_sizes_set_interm.suggestName("a_sizes_set_interm")
when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) {
a_set_wo_ready := UIntToOH(bundle.a.bits.source)
}
when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) {
a_set := UIntToOH(bundle.a.bits.source)
a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) | 1.U
a_sizes_set_interm := (bundle.a.bits.size << 1.U) | 1.U
a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U)
a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U)
monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra)
}
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
d_clr.suggestName("d_clr")
d_clr_wo_ready.suggestName("d_clr_wo_ready")
val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
d_opcodes_clr.suggestName("d_opcodes_clr")
val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
d_sizes_clr.suggestName("d_sizes_clr")
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr_wo_ready := UIntToOH(bundle.d.bits.source)
}
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U)
d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U)
}
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source)
assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra)
when (same_cycle_resp) {
assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) ||
(bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra)
assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra)
} .otherwise {
assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) ||
(bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra)
assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra)
}
}
when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) {
assume((!bundle.d.ready) || bundle.a.ready, "ready check")
}
if (edge.manager.minLatency > 0) {
assume(a_set_wo_ready =/= d_clr_wo_ready || !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra)
}
inflight := (inflight | a_set) & ~d_clr
inflight_opcodes := (inflight_opcodes | a_opcodes_set) & ~d_opcodes_clr
inflight_sizes := (inflight_sizes | a_sizes_set) & ~d_sizes_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = {
val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset)
val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything
val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size)
val log_c_size_bus_size = log2Ceil(c_size_bus_size)
def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits
val inflight = RegInit(0.U((2 max edge.client.endSourceId).W))
val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
inflight.suggestName("inflight")
inflight_opcodes.suggestName("inflight_opcodes")
inflight_sizes.suggestName("inflight_sizes")
val c_first = edge.first(bundle.c.bits, bundle.c.fire)
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
c_first.suggestName("c_first")
d_first.suggestName("d_first")
val c_set = WireInit(0.U(edge.client.endSourceId.W))
val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
c_set.suggestName("c_set")
c_set_wo_ready.suggestName("c_set_wo_ready")
c_opcodes_set.suggestName("c_opcodes_set")
c_sizes_set.suggestName("c_sizes_set")
val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W))
val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W))
c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U
c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U
c_opcode_lookup.suggestName("c_opcode_lookup")
c_size_lookup.suggestName("c_size_lookup")
val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W))
val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W))
c_opcodes_set_interm.suggestName("c_opcodes_set_interm")
c_sizes_set_interm.suggestName("c_sizes_set_interm")
when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) {
c_set_wo_ready := UIntToOH(bundle.c.bits.source)
}
when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) {
c_set := UIntToOH(bundle.c.bits.source)
c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) | 1.U
c_sizes_set_interm := (bundle.c.bits.size << 1.U) | 1.U
c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U)
c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U)
monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra)
}
val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck || bundle.c.bits.opcode === TLMessages.ProbeAckData
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
d_clr.suggestName("d_clr")
d_clr_wo_ready.suggestName("d_clr_wo_ready")
d_opcodes_clr.suggestName("d_opcodes_clr")
d_sizes_clr.suggestName("d_sizes_clr")
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
d_clr_wo_ready := UIntToOH(bundle.d.bits.source)
}
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U)
d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U)
}
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source)
assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra)
when (same_cycle_resp) {
assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra)
} .otherwise {
assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra)
}
}
when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) {
assume((!bundle.d.ready) || bundle.c.ready, "ready check")
}
if (edge.manager.minLatency > 0) {
when (c_set_wo_ready.orR) {
assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra)
}
}
inflight := (inflight | c_set) & ~d_clr
inflight_opcodes := (inflight_opcodes | c_opcodes_set) & ~d_opcodes_clr
inflight_sizes := (inflight_sizes | c_sizes_set) & ~d_sizes_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.c.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = {
val inflight = RegInit(0.U(edge.manager.endSinkId.W))
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
val e_first = true.B
val d_set = WireInit(0.U(edge.manager.endSinkId.W))
when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) {
d_set := UIntToOH(bundle.d.bits.sink)
assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra)
}
val e_clr = WireInit(0.U(edge.manager.endSinkId.W))
when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) {
e_clr := UIntToOH(bundle.e.bits.sink)
monAssert((d_set | inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra)
}
// edge.client.minLatency applies to BC, not DE
inflight := (inflight | d_set) & ~e_clr
}
def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = {
val sourceBits = log2Ceil(edge.client.endSourceId)
val tooBig = 14 // >16kB worth of flight information gets to be too much
if (sourceBits > tooBig) {
println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked")
} else {
if (args.edge.params(TestplanTestType).simulation) {
if (args.edge.params(TLMonitorStrictMode)) {
legalizeADSource(bundle, edge)
legalizeCDSource(bundle, edge)
} else {
legalizeADSourceOld(bundle, edge)
}
}
if (args.edge.params(TestplanTestType).formal) {
legalizeADSourceFormal(bundle, edge)
}
}
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
// legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize...
val sinkBits = log2Ceil(edge.manager.endSinkId)
if (sinkBits > tooBig) {
println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked")
} else {
legalizeDESink(bundle, edge)
}
}
}
def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = {
legalizeFormat (bundle, edge)
legalizeMultibeat (bundle, edge)
legalizeUnique (bundle, edge)
}
}
File Misc.scala:
// See LICENSE.Berkeley for license details.
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util._
import chisel3.util.random.LFSR
import org.chipsalliance.cde.config.Parameters
import scala.math._
class ParameterizedBundle(implicit p: Parameters) extends Bundle
trait Clocked extends Bundle {
val clock = Clock()
val reset = Bool()
}
object DecoupledHelper {
def apply(rvs: Bool*) = new DecoupledHelper(rvs)
}
class DecoupledHelper(val rvs: Seq[Bool]) {
def fire(exclude: Bool, includes: Bool*) = {
require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!")
(rvs.filter(_ ne exclude) ++ includes).reduce(_ && _)
}
def fire() = {
rvs.reduce(_ && _)
}
}
object MuxT {
def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2))
def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3))
def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4))
}
/** Creates a cascade of n MuxTs to search for a key value. */
object MuxTLookup {
def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = {
var res = default
for ((k, v) <- mapping.reverse)
res = MuxT(k === key, v, res)
res
}
def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = {
var res = default
for ((k, v) <- mapping.reverse)
res = MuxT(k === key, v, res)
res
}
}
object ValidMux {
def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = {
apply(v1 +: v2.toSeq)
}
def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = {
val out = Wire(Valid(valids.head.bits.cloneType))
out.valid := valids.map(_.valid).reduce(_ || _)
out.bits := MuxCase(valids.head.bits,
valids.map(v => (v.valid -> v.bits)))
out
}
}
object Str
{
def apply(s: String): UInt = {
var i = BigInt(0)
require(s.forall(validChar _))
for (c <- s)
i = (i << 8) | c
i.U((s.length*8).W)
}
def apply(x: Char): UInt = {
require(validChar(x))
x.U(8.W)
}
def apply(x: UInt): UInt = apply(x, 10)
def apply(x: UInt, radix: Int): UInt = {
val rad = radix.U
val w = x.getWidth
require(w > 0)
var q = x
var s = digit(q % rad)
for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {
q = q / rad
s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s)
}
s
}
def apply(x: SInt): UInt = apply(x, 10)
def apply(x: SInt, radix: Int): UInt = {
val neg = x < 0.S
val abs = x.abs.asUInt
if (radix != 10) {
Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix))
} else {
val rad = radix.U
val w = abs.getWidth
require(w > 0)
var q = abs
var s = digit(q % rad)
var needSign = neg
for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {
q = q / rad
val placeSpace = q === 0.U
val space = Mux(needSign, Str('-'), Str(' '))
needSign = needSign && !placeSpace
s = Cat(Mux(placeSpace, space, digit(q % rad)), s)
}
Cat(Mux(needSign, Str('-'), Str(' ')), s)
}
}
private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0)
private def validChar(x: Char) = x == (x & 0xFF)
}
object Split
{
def apply(x: UInt, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n0), x.extract(n0-1,0))
}
def apply(x: UInt, n1: Int, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))
}
def apply(x: UInt, n2: Int, n1: Int, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))
}
}
object Random
{
def apply(mod: Int, random: UInt): UInt = {
if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0)
else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod))
}
def apply(mod: Int): UInt = apply(mod, randomizer)
def oneHot(mod: Int, random: UInt): UInt = {
if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0))
else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt
}
def oneHot(mod: Int): UInt = oneHot(mod, randomizer)
private def randomizer = LFSR(16)
private def partition(value: UInt, slices: Int) =
Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U)
}
object Majority {
def apply(in: Set[Bool]): Bool = {
val n = (in.size >> 1) + 1
val clauses = in.subsets(n).map(_.reduce(_ && _))
clauses.reduce(_ || _)
}
def apply(in: Seq[Bool]): Bool = apply(in.toSet)
def apply(in: UInt): Bool = apply(in.asBools.toSet)
}
object PopCountAtLeast {
private def two(x: UInt): (Bool, Bool) = x.getWidth match {
case 1 => (x.asBool, false.B)
case n =>
val half = x.getWidth / 2
val (leftOne, leftTwo) = two(x(half - 1, 0))
val (rightOne, rightTwo) = two(x(x.getWidth - 1, half))
(leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne))
}
def apply(x: UInt, n: Int): Bool = n match {
case 0 => true.B
case 1 => x.orR
case 2 => two(x)._2
case 3 => PopCount(x) >= n.U
}
}
// This gets used everywhere, so make the smallest circuit possible ...
// Given an address and size, create a mask of beatBytes size
// eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111
// groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01
object MaskGen {
def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = {
require (groupBy >= 1 && beatBytes >= groupBy)
require (isPow2(beatBytes) && isPow2(groupBy))
val lgBytes = log2Ceil(beatBytes)
val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U
def helper(i: Int): Seq[(Bool, Bool)] = {
if (i == 0) {
Seq((lgSize >= lgBytes.asUInt, true.B))
} else {
val sub = helper(i-1)
val size = sizeOH(lgBytes - i)
val bit = addr_lo(lgBytes - i)
val nbit = !bit
Seq.tabulate (1 << i) { j =>
val (sub_acc, sub_eq) = sub(j/2)
val eq = sub_eq && (if (j % 2 == 1) bit else nbit)
val acc = sub_acc || (size && eq)
(acc, eq)
}
}
}
if (groupBy == beatBytes) 1.U else
Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse)
}
}
File PlusArg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.experimental._
import chisel3.util.HasBlackBoxResource
@deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05")
case class PlusArgInfo(default: BigInt, docstring: String)
/** Case class for PlusArg information
*
* @tparam A scala type of the PlusArg value
* @param default optional default value
* @param docstring text to include in the help
* @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT)
*/
private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String)
/** Typeclass for converting a type to a doctype string
* @tparam A some type
*/
trait Doctypeable[A] {
/** Return the doctype string for some option */
def toDoctype(a: Option[A]): String
}
/** Object containing implementations of the Doctypeable typeclass */
object Doctypes {
/** Converts an Int => "INT" */
implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" }
/** Converts a BigInt => "INT" */
implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" }
/** Converts a String => "STRING" */
implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" }
}
class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map(
"FORMAT" -> StringParam(format),
"DEFAULT" -> IntParam(default),
"WIDTH" -> IntParam(width)
)) with HasBlackBoxResource {
val io = IO(new Bundle {
val out = Output(UInt(width.W))
})
addResource("/vsrc/plusarg_reader.v")
}
/* This wrapper class has no outputs, making it clear it is a simulation-only construct */
class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module {
val io = IO(new Bundle {
val count = Input(UInt(width.W))
})
val max = Module(new plusarg_reader(format, default, docstring, width)).io.out
when (max > 0.U) {
assert (io.count < max, s"Timeout exceeded: $docstring")
}
}
import Doctypes._
object PlusArg
{
/** PlusArg("foo") will return 42.U if the simulation is run with +foo=42
* Do not use this as an initial register value. The value is set in an
* initial block and thus accessing it from another initial is racey.
* Add a docstring to document the arg, which can be dumped in an elaboration
* pass.
*/
def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = {
PlusArgArtefacts.append(name, Some(default), docstring)
Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out
}
/** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert
* to kill the simulation when count exceeds the specified integer argument.
* Default 0 will never assert.
*/
def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = {
PlusArgArtefacts.append(name, Some(default), docstring)
Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count
}
}
object PlusArgArtefacts {
private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty
/* Add a new PlusArg */
@deprecated(
"Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08",
"Rocket Chip 2020.05"
)
def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring)
/** Add a new PlusArg
*
* @tparam A scala type of the PlusArg value
* @param name name for the PlusArg
* @param default optional default value
* @param docstring text to include in the help
*/
def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit =
artefacts = artefacts ++
Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default)))
/* From plus args, generate help text */
private def serializeHelp_cHeader(tab: String = ""): String = artefacts
.map{ case(arg, info) =>
s"""|$tab+$arg=${info.doctype}\\n\\
|$tab${" "*20}${info.docstring}\\n\\
|""".stripMargin ++ info.default.map{ case default =>
s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("")
}.toSeq.mkString("\\n\\\n") ++ "\""
/* From plus args, generate a char array of their names */
private def serializeArray_cHeader(tab: String = ""): String = {
val prettyTab = tab + " " * 44 // Length of 'static const ...'
s"${tab}static const char * verilog_plusargs [] = {\\\n" ++
artefacts
.map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" }
.mkString("")++
s"${prettyTab}0};"
}
/* Generate C code to be included in emulator.cc that helps with
* argument parsing based on available Verilog PlusArgs */
def serialize_cHeader(): String =
s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\
|${serializeHelp_cHeader(" "*7)}
|${serializeArray_cHeader()}
|""".stripMargin
}
File package.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip
import chisel3._
import chisel3.util._
import scala.math.min
import scala.collection.{immutable, mutable}
package object util {
implicit class UnzippableOption[S, T](val x: Option[(S, T)]) {
def unzip = (x.map(_._1), x.map(_._2))
}
implicit class UIntIsOneOf(private val x: UInt) extends AnyVal {
def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR
def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq)
}
implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal {
/** Like Vec.apply(idx), but tolerates indices of mismatched width */
def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0))
}
implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal {
def apply(idx: UInt): T = {
if (x.size <= 1) {
x.head
} else if (!isPow2(x.size)) {
// For non-power-of-2 seqs, reflect elements to simplify decoder
(x ++ x.takeRight(x.size & -x.size)).toSeq(idx)
} else {
// Ignore MSBs of idx
val truncIdx =
if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx
else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0)
x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) }
}
}
def extract(idx: UInt): T = VecInit(x).extract(idx)
def asUInt: UInt = Cat(x.map(_.asUInt).reverse)
def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n)
def rotate(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n)
def rotateRight(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
}
// allow bitwise ops on Seq[Bool] just like UInt
implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal {
def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b }
def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b }
def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b }
def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x
def >> (n: Int): Seq[Bool] = x drop n
def unary_~ : Seq[Bool] = x.map(!_)
def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_)
def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_)
def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_)
private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B)
}
implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal {
def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable))
def getElements: Seq[Element] = x match {
case e: Element => Seq(e)
case a: Aggregate => a.getElements.flatMap(_.getElements)
}
}
/** Any Data subtype that has a Bool member named valid. */
type DataCanBeValid = Data { val valid: Bool }
implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal {
def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable)
}
implicit class StringToAugmentedString(private val x: String) extends AnyVal {
/** converts from camel case to to underscores, also removing all spaces */
def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") {
case (acc, c) if c.isUpper => acc + "_" + c.toLower
case (acc, c) if c == ' ' => acc
case (acc, c) => acc + c
}
/** converts spaces or underscores to hyphens, also lowering case */
def kebab: String = x.toLowerCase map {
case ' ' => '-'
case '_' => '-'
case c => c
}
def named(name: Option[String]): String = {
x + name.map("_named_" + _ ).getOrElse("_with_no_name")
}
def named(name: String): String = named(Some(name))
}
implicit def uintToBitPat(x: UInt): BitPat = BitPat(x)
implicit def wcToUInt(c: WideCounter): UInt = c.value
implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal {
def sextTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x)
}
def padTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(0.U((n - x.getWidth).W), x)
}
// shifts left by n if n >= 0, or right by -n if n < 0
def << (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << n(w-1, 0)
Mux(n(w), shifted >> (1 << w), shifted)
}
// shifts right by n if n >= 0, or left by -n if n < 0
def >> (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << (1 << w) >> n(w-1, 0)
Mux(n(w), shifted, shifted >> (1 << w))
}
// Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts
def extract(hi: Int, lo: Int): UInt = {
require(hi >= lo-1)
if (hi == lo-1) 0.U
else x(hi, lo)
}
// Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts
def extractOption(hi: Int, lo: Int): Option[UInt] = {
require(hi >= lo-1)
if (hi == lo-1) None
else Some(x(hi, lo))
}
// like x & ~y, but first truncate or zero-extend y to x's width
def andNot(y: UInt): UInt = x & ~(y | (x & 0.U))
def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n)
def rotateRight(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r))
}
}
def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n))
def rotateLeft(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r))
}
}
// compute (this + y) % n, given (this < n) and (y < n)
def addWrap(y: UInt, n: Int): UInt = {
val z = x +& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0)
}
// compute (this - y) % n, given (this < n) and (y < n)
def subWrap(y: UInt, n: Int): UInt = {
val z = x -& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0)
}
def grouped(width: Int): Seq[UInt] =
(0 until x.getWidth by width).map(base => x(base + width - 1, base))
def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds
def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x)
// Like >=, but prevents x-prop for ('x >= 0)
def >== (y: UInt): Bool = x >= y || y === 0.U
}
implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal {
def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y)
def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y)
}
implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal {
def toInt: Int = if (x) 1 else 0
// this one's snagged from scalaz
def option[T](z: => T): Option[T] = if (x) Some(z) else None
}
implicit class IntToAugmentedInt(private val x: Int) extends AnyVal {
// exact log2
def log2: Int = {
require(isPow2(x))
log2Ceil(x)
}
}
def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x)
def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x))
def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0)
def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1)
def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None
// Fill 1s from low bits to high bits
def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth)
def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0))
helper(1, x)(width-1, 0)
}
// Fill 1s form high bits to low bits
def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth)
def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x >> s))
helper(1, x)(width-1, 0)
}
def OptimizationBarrier[T <: Data](in: T): T = {
val barrier = Module(new Module {
val io = IO(new Bundle {
val x = Input(chiselTypeOf(in))
val y = Output(chiselTypeOf(in))
})
io.y := io.x
override def desiredName = s"OptimizationBarrier_${in.typeName}"
})
barrier.io.x := in
barrier.io.y
}
/** Similar to Seq.groupBy except this returns a Seq instead of a Map
* Useful for deterministic code generation
*/
def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = {
val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]]
for (x <- xs) {
val key = f(x)
val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A])
l += x
}
map.view.map({ case (k, vs) => k -> vs.toList }).toList
}
def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match {
case 1 => List.fill(n)(in.head)
case x if x == n => in
case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in")
}
// HeterogeneousBag moved to standalond diplomacy
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts)
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag
}
File Bundles.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import freechips.rocketchip.util._
import scala.collection.immutable.ListMap
import chisel3.util.Decoupled
import chisel3.util.DecoupledIO
import chisel3.reflect.DataMirror
abstract class TLBundleBase(val params: TLBundleParameters) extends Bundle
// common combos in lazy policy:
// Put + Acquire
// Release + AccessAck
object TLMessages
{
// A B C D E
def PutFullData = 0.U // . . => AccessAck
def PutPartialData = 1.U // . . => AccessAck
def ArithmeticData = 2.U // . . => AccessAckData
def LogicalData = 3.U // . . => AccessAckData
def Get = 4.U // . . => AccessAckData
def Hint = 5.U // . . => HintAck
def AcquireBlock = 6.U // . => Grant[Data]
def AcquirePerm = 7.U // . => Grant[Data]
def Probe = 6.U // . => ProbeAck[Data]
def AccessAck = 0.U // . .
def AccessAckData = 1.U // . .
def HintAck = 2.U // . .
def ProbeAck = 4.U // .
def ProbeAckData = 5.U // .
def Release = 6.U // . => ReleaseAck
def ReleaseData = 7.U // . => ReleaseAck
def Grant = 4.U // . => GrantAck
def GrantData = 5.U // . => GrantAck
def ReleaseAck = 6.U // .
def GrantAck = 0.U // .
def isA(x: UInt) = x <= AcquirePerm
def isB(x: UInt) = x <= Probe
def isC(x: UInt) = x <= ReleaseData
def isD(x: UInt) = x <= ReleaseAck
def adResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant, Grant)
def bcResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, ProbeAck, ProbeAck)
def a = Seq( ("PutFullData",TLPermissions.PermMsgReserved),
("PutPartialData",TLPermissions.PermMsgReserved),
("ArithmeticData",TLAtomics.ArithMsg),
("LogicalData",TLAtomics.LogicMsg),
("Get",TLPermissions.PermMsgReserved),
("Hint",TLHints.HintsMsg),
("AcquireBlock",TLPermissions.PermMsgGrow),
("AcquirePerm",TLPermissions.PermMsgGrow))
def b = Seq( ("PutFullData",TLPermissions.PermMsgReserved),
("PutPartialData",TLPermissions.PermMsgReserved),
("ArithmeticData",TLAtomics.ArithMsg),
("LogicalData",TLAtomics.LogicMsg),
("Get",TLPermissions.PermMsgReserved),
("Hint",TLHints.HintsMsg),
("Probe",TLPermissions.PermMsgCap))
def c = Seq( ("AccessAck",TLPermissions.PermMsgReserved),
("AccessAckData",TLPermissions.PermMsgReserved),
("HintAck",TLPermissions.PermMsgReserved),
("Invalid Opcode",TLPermissions.PermMsgReserved),
("ProbeAck",TLPermissions.PermMsgReport),
("ProbeAckData",TLPermissions.PermMsgReport),
("Release",TLPermissions.PermMsgReport),
("ReleaseData",TLPermissions.PermMsgReport))
def d = Seq( ("AccessAck",TLPermissions.PermMsgReserved),
("AccessAckData",TLPermissions.PermMsgReserved),
("HintAck",TLPermissions.PermMsgReserved),
("Invalid Opcode",TLPermissions.PermMsgReserved),
("Grant",TLPermissions.PermMsgCap),
("GrantData",TLPermissions.PermMsgCap),
("ReleaseAck",TLPermissions.PermMsgReserved))
}
/**
* The three primary TileLink permissions are:
* (T)runk: the agent is (or is on inwards path to) the global point of serialization.
* (B)ranch: the agent is on an outwards path to
* (N)one:
* These permissions are permuted by transfer operations in various ways.
* Operations can cap permissions, request for them to be grown or shrunk,
* or for a report on their current status.
*/
object TLPermissions
{
val aWidth = 2
val bdWidth = 2
val cWidth = 3
// Cap types (Grant = new permissions, Probe = permisions <= target)
def toT = 0.U(bdWidth.W)
def toB = 1.U(bdWidth.W)
def toN = 2.U(bdWidth.W)
def isCap(x: UInt) = x <= toN
// Grow types (Acquire = permissions >= target)
def NtoB = 0.U(aWidth.W)
def NtoT = 1.U(aWidth.W)
def BtoT = 2.U(aWidth.W)
def isGrow(x: UInt) = x <= BtoT
// Shrink types (ProbeAck, Release)
def TtoB = 0.U(cWidth.W)
def TtoN = 1.U(cWidth.W)
def BtoN = 2.U(cWidth.W)
def isShrink(x: UInt) = x <= BtoN
// Report types (ProbeAck, Release)
def TtoT = 3.U(cWidth.W)
def BtoB = 4.U(cWidth.W)
def NtoN = 5.U(cWidth.W)
def isReport(x: UInt) = x <= NtoN
def PermMsgGrow:Seq[String] = Seq("Grow NtoB", "Grow NtoT", "Grow BtoT")
def PermMsgCap:Seq[String] = Seq("Cap toT", "Cap toB", "Cap toN")
def PermMsgReport:Seq[String] = Seq("Shrink TtoB", "Shrink TtoN", "Shrink BtoN", "Report TotT", "Report BtoB", "Report NtoN")
def PermMsgReserved:Seq[String] = Seq("Reserved")
}
object TLAtomics
{
val width = 3
// Arithmetic types
def MIN = 0.U(width.W)
def MAX = 1.U(width.W)
def MINU = 2.U(width.W)
def MAXU = 3.U(width.W)
def ADD = 4.U(width.W)
def isArithmetic(x: UInt) = x <= ADD
// Logical types
def XOR = 0.U(width.W)
def OR = 1.U(width.W)
def AND = 2.U(width.W)
def SWAP = 3.U(width.W)
def isLogical(x: UInt) = x <= SWAP
def ArithMsg:Seq[String] = Seq("MIN", "MAX", "MINU", "MAXU", "ADD")
def LogicMsg:Seq[String] = Seq("XOR", "OR", "AND", "SWAP")
}
object TLHints
{
val width = 1
def PREFETCH_READ = 0.U(width.W)
def PREFETCH_WRITE = 1.U(width.W)
def isHints(x: UInt) = x <= PREFETCH_WRITE
def HintsMsg:Seq[String] = Seq("PrefetchRead", "PrefetchWrite")
}
sealed trait TLChannel extends TLBundleBase {
val channelName: String
}
sealed trait TLDataChannel extends TLChannel
sealed trait TLAddrChannel extends TLDataChannel
final class TLBundleA(params: TLBundleParameters)
extends TLBundleBase(params) with TLAddrChannel
{
override def typeName = s"TLBundleA_${params.shortName}"
val channelName = "'A' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(List(TLAtomics.width, TLPermissions.aWidth, TLHints.width).max.W) // amo_opcode || grow perms || hint
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // from
val address = UInt(params.addressBits.W) // to
val user = BundleMap(params.requestFields)
val echo = BundleMap(params.echoFields)
// variable fields during multibeat:
val mask = UInt((params.dataBits/8).W)
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleB(params: TLBundleParameters)
extends TLBundleBase(params) with TLAddrChannel
{
override def typeName = s"TLBundleB_${params.shortName}"
val channelName = "'B' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(TLPermissions.bdWidth.W) // cap perms
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // to
val address = UInt(params.addressBits.W) // from
// variable fields during multibeat:
val mask = UInt((params.dataBits/8).W)
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleC(params: TLBundleParameters)
extends TLBundleBase(params) with TLAddrChannel
{
override def typeName = s"TLBundleC_${params.shortName}"
val channelName = "'C' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(TLPermissions.cWidth.W) // shrink or report perms
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // from
val address = UInt(params.addressBits.W) // to
val user = BundleMap(params.requestFields)
val echo = BundleMap(params.echoFields)
// variable fields during multibeat:
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleD(params: TLBundleParameters)
extends TLBundleBase(params) with TLDataChannel
{
override def typeName = s"TLBundleD_${params.shortName}"
val channelName = "'D' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(TLPermissions.bdWidth.W) // cap perms
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // to
val sink = UInt(params.sinkBits.W) // from
val denied = Bool() // implies corrupt iff *Data
val user = BundleMap(params.responseFields)
val echo = BundleMap(params.echoFields)
// variable fields during multibeat:
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleE(params: TLBundleParameters)
extends TLBundleBase(params) with TLChannel
{
override def typeName = s"TLBundleE_${params.shortName}"
val channelName = "'E' channel"
val sink = UInt(params.sinkBits.W) // to
}
class TLBundle(val params: TLBundleParameters) extends Record
{
// Emulate a Bundle with elements abcde or ad depending on params.hasBCE
private val optA = Some (Decoupled(new TLBundleA(params)))
private val optB = params.hasBCE.option(Flipped(Decoupled(new TLBundleB(params))))
private val optC = params.hasBCE.option(Decoupled(new TLBundleC(params)))
private val optD = Some (Flipped(Decoupled(new TLBundleD(params))))
private val optE = params.hasBCE.option(Decoupled(new TLBundleE(params)))
def a: DecoupledIO[TLBundleA] = optA.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleA(params)))))
def b: DecoupledIO[TLBundleB] = optB.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleB(params)))))
def c: DecoupledIO[TLBundleC] = optC.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleC(params)))))
def d: DecoupledIO[TLBundleD] = optD.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleD(params)))))
def e: DecoupledIO[TLBundleE] = optE.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleE(params)))))
val elements =
if (params.hasBCE) ListMap("e" -> e, "d" -> d, "c" -> c, "b" -> b, "a" -> a)
else ListMap("d" -> d, "a" -> a)
def tieoff(): Unit = {
DataMirror.specifiedDirectionOf(a.ready) match {
case SpecifiedDirection.Input =>
a.ready := false.B
c.ready := false.B
e.ready := false.B
b.valid := false.B
d.valid := false.B
case SpecifiedDirection.Output =>
a.valid := false.B
c.valid := false.B
e.valid := false.B
b.ready := false.B
d.ready := false.B
case _ =>
}
}
}
object TLBundle
{
def apply(params: TLBundleParameters) = new TLBundle(params)
}
class TLAsyncBundleBase(val params: TLAsyncBundleParameters) extends Bundle
class TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params)
{
val a = new AsyncBundle(new TLBundleA(params.base), params.async)
val b = Flipped(new AsyncBundle(new TLBundleB(params.base), params.async))
val c = new AsyncBundle(new TLBundleC(params.base), params.async)
val d = Flipped(new AsyncBundle(new TLBundleD(params.base), params.async))
val e = new AsyncBundle(new TLBundleE(params.base), params.async)
}
class TLRationalBundle(params: TLBundleParameters) extends TLBundleBase(params)
{
val a = RationalIO(new TLBundleA(params))
val b = Flipped(RationalIO(new TLBundleB(params)))
val c = RationalIO(new TLBundleC(params))
val d = Flipped(RationalIO(new TLBundleD(params)))
val e = RationalIO(new TLBundleE(params))
}
class TLCreditedBundle(params: TLBundleParameters) extends TLBundleBase(params)
{
val a = CreditedIO(new TLBundleA(params))
val b = Flipped(CreditedIO(new TLBundleB(params)))
val c = CreditedIO(new TLBundleC(params))
val d = Flipped(CreditedIO(new TLBundleD(params)))
val e = CreditedIO(new TLBundleE(params))
}
File Parameters.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.diplomacy
import chisel3._
import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor}
import freechips.rocketchip.util.ShiftQueue
/** Options for describing the attributes of memory regions */
object RegionType {
// Define the 'more relaxed than' ordering
val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS)
sealed trait T extends Ordered[T] {
def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this)
}
case object CACHED extends T // an intermediate agent may have cached a copy of the region for you
case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided
case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible
case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached
case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects
case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed
case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively
}
// A non-empty half-open range; [start, end)
case class IdRange(start: Int, end: Int) extends Ordered[IdRange]
{
require (start >= 0, s"Ids cannot be negative, but got: $start.")
require (start <= end, "Id ranges cannot be negative.")
def compare(x: IdRange) = {
val primary = (this.start - x.start).signum
val secondary = (x.end - this.end).signum
if (primary != 0) primary else secondary
}
def overlaps(x: IdRange) = start < x.end && x.start < end
def contains(x: IdRange) = start <= x.start && x.end <= end
def contains(x: Int) = start <= x && x < end
def contains(x: UInt) =
if (size == 0) {
false.B
} else if (size == 1) { // simple comparison
x === start.U
} else {
// find index of largest different bit
val largestDeltaBit = log2Floor(start ^ (end-1))
val smallestCommonBit = largestDeltaBit + 1 // may not exist in x
val uncommonMask = (1 << smallestCommonBit) - 1
val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0)
// the prefix must match exactly (note: may shift ALL bits away)
(x >> smallestCommonBit) === (start >> smallestCommonBit).U &&
// firrtl constant prop range analysis can eliminate these two:
(start & uncommonMask).U <= uncommonBits &&
uncommonBits <= ((end-1) & uncommonMask).U
}
def shift(x: Int) = IdRange(start+x, end+x)
def size = end - start
def isEmpty = end == start
def range = start until end
}
object IdRange
{
def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else {
val ranges = s.sorted
(ranges.tail zip ranges.init) find { case (a, b) => a overlaps b }
}
}
// An potentially empty inclusive range of 2-powers [min, max] (in bytes)
case class TransferSizes(min: Int, max: Int)
{
def this(x: Int) = this(x, x)
require (min <= max, s"Min transfer $min > max transfer $max")
require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)")
require (max == 0 || isPow2(max), s"TransferSizes must be a power of 2, got: $max")
require (min == 0 || isPow2(min), s"TransferSizes must be a power of 2, got: $min")
require (max == 0 || min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)")
def none = min == 0
def contains(x: Int) = isPow2(x) && min <= x && x <= max
def containsLg(x: Int) = contains(1 << x)
def containsLg(x: UInt) =
if (none) false.B
else if (min == max) { log2Ceil(min).U === x }
else { log2Ceil(min).U <= x && x <= log2Ceil(max).U }
def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max)
def intersect(x: TransferSizes) =
if (x.max < min || max < x.min) TransferSizes.none
else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max))
// Not a union, because the result may contain sizes contained by neither term
// NOT TO BE CONFUSED WITH COVERPOINTS
def mincover(x: TransferSizes) = {
if (none) {
x
} else if (x.none) {
this
} else {
TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max))
}
}
override def toString() = "TransferSizes[%d, %d]".format(min, max)
}
object TransferSizes {
def apply(x: Int) = new TransferSizes(x)
val none = new TransferSizes(0)
def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _)
def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _)
implicit def asBool(x: TransferSizes) = !x.none
}
// AddressSets specify the address space managed by the manager
// Base is the base address, and mask are the bits consumed by the manager
// e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff
// e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ...
case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet]
{
// Forbid misaligned base address (and empty sets)
require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}")
require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous
// We do allow negative mask (=> ignore all high bits)
def contains(x: BigInt) = ((x ^ base) & ~mask) == 0
def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S
// turn x into an address contained in this set
def legalize(x: UInt): UInt = base.U | (mask.U & x)
// overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1)
def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0
// contains iff bitwise: x.mask => mask && contains(x.base)
def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0
// The number of bytes to which the manager must be aligned
def alignment = ((mask + 1) & ~mask)
// Is this a contiguous memory range
def contiguous = alignment == mask+1
def finite = mask >= 0
def max = { require (finite, "Max cannot be calculated on infinite mask"); base | mask }
// Widen the match function to ignore all bits in imask
def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask)
// Return an AddressSet that only contains the addresses both sets contain
def intersect(x: AddressSet): Option[AddressSet] = {
if (!overlaps(x)) {
None
} else {
val r_mask = mask & x.mask
val r_base = base | x.base
Some(AddressSet(r_base, r_mask))
}
}
def subtract(x: AddressSet): Seq[AddressSet] = {
intersect(x) match {
case None => Seq(this)
case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit =>
val nmask = (mask & (bit-1)) | remove.mask
val nbase = (remove.base ^ bit) & ~nmask
AddressSet(nbase, nmask)
}
}
}
// AddressSets have one natural Ordering (the containment order, if contiguous)
def compare(x: AddressSet) = {
val primary = (this.base - x.base).signum // smallest address first
val secondary = (x.mask - this.mask).signum // largest mask first
if (primary != 0) primary else secondary
}
// We always want to see things in hex
override def toString() = {
if (mask >= 0) {
"AddressSet(0x%x, 0x%x)".format(base, mask)
} else {
"AddressSet(0x%x, ~0x%x)".format(base, ~mask)
}
}
def toRanges = {
require (finite, "Ranges cannot be calculated on infinite mask")
val size = alignment
val fragments = mask & ~(size-1)
val bits = bitIndexes(fragments)
(BigInt(0) until (BigInt(1) << bits.size)).map { i =>
val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) }
AddressRange(off, size)
}
}
}
object AddressSet
{
val everything = AddressSet(0, -1)
def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = {
if (size == 0) tail.reverse else {
val maxBaseAlignment = base & (-base) // 0 for infinite (LSB)
val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size
val step =
if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment)
maxSizeAlignment else maxBaseAlignment
misaligned(base+step, size-step, AddressSet(base, step-1) +: tail)
}
}
def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = {
// Pair terms up by ignoring 'bit'
seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) =>
if (seq.size == 1) {
seq.head // singleton -> unaffected
} else {
key.copy(mask = key.mask | bit) // pair - widen mask by bit
}
}.toList
}
def unify(seq: Seq[AddressSet]): Seq[AddressSet] = {
val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _)
AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted
}
def enumerateMask(mask: BigInt): Seq[BigInt] = {
def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] =
if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail)
helper(0, Nil)
}
def enumerateBits(mask: BigInt): Seq[BigInt] = {
def helper(x: BigInt): Seq[BigInt] = {
if (x == 0) {
Nil
} else {
val bit = x & (-x)
bit +: helper(x & ~bit)
}
}
helper(mask)
}
}
case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean)
{
require (depth >= 0, "Buffer depth must be >= 0")
def isDefined = depth > 0
def latency = if (isDefined && !flow) 1 else 0
def apply[T <: Data](x: DecoupledIO[T]) =
if (isDefined) Queue(x, depth, flow=flow, pipe=pipe)
else x
def irrevocable[T <: Data](x: ReadyValidIO[T]) =
if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe)
else x
def sq[T <: Data](x: DecoupledIO[T]) =
if (!isDefined) x else {
val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe))
sq.io.enq <> x
sq.io.deq
}
override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "")
}
object BufferParams
{
implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false)
val default = BufferParams(2)
val none = BufferParams(0)
val flow = BufferParams(1, true, false)
val pipe = BufferParams(1, false, true)
}
case class TriStateValue(value: Boolean, set: Boolean)
{
def update(orig: Boolean) = if (set) value else orig
}
object TriStateValue
{
implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true)
def unset = TriStateValue(false, false)
}
trait DirectedBuffers[T] {
def copyIn(x: BufferParams): T
def copyOut(x: BufferParams): T
def copyInOut(x: BufferParams): T
}
trait IdMapEntry {
def name: String
def from: IdRange
def to: IdRange
def isCache: Boolean
def requestFifo: Boolean
def maxTransactionsInFlight: Option[Int]
def pretty(fmt: String) =
if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5
fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "")
} else {
fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "")
}
}
abstract class IdMap[T <: IdMapEntry] {
protected val fmt: String
val mapping: Seq[T]
def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n")
}
File Edges.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.util._
class TLEdge(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdgeParameters(client, manager, params, sourceInfo)
{
def isAligned(address: UInt, lgSize: UInt): Bool = {
if (maxLgSize == 0) true.B else {
val mask = UIntToOH1(lgSize, maxLgSize)
(address & mask) === 0.U
}
}
def mask(address: UInt, lgSize: UInt): UInt =
MaskGen(address, lgSize, manager.beatBytes)
def staticHasData(bundle: TLChannel): Option[Boolean] = {
bundle match {
case _:TLBundleA => {
// Do there exist A messages with Data?
val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial
// Do there exist A messages without Data?
val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint
// Statically optimize the case where hasData is a constant
if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None
}
case _:TLBundleB => {
// Do there exist B messages with Data?
val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial
// Do there exist B messages without Data?
val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint
// Statically optimize the case where hasData is a constant
if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None
}
case _:TLBundleC => {
// Do there eixst C messages with Data?
val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe
// Do there exist C messages without Data?
val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe
if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None
}
case _:TLBundleD => {
// Do there eixst D messages with Data?
val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB
// Do there exist D messages without Data?
val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT
if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None
}
case _:TLBundleE => Some(false)
}
}
def isRequest(x: TLChannel): Bool = {
x match {
case a: TLBundleA => true.B
case b: TLBundleB => true.B
case c: TLBundleC => c.opcode(2) && c.opcode(1)
// opcode === TLMessages.Release ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(2) && !d.opcode(1)
// opcode === TLMessages.Grant ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
}
def isResponse(x: TLChannel): Bool = {
x match {
case a: TLBundleA => false.B
case b: TLBundleB => false.B
case c: TLBundleC => !c.opcode(2) || !c.opcode(1)
// opcode =/= TLMessages.Release &&
// opcode =/= TLMessages.ReleaseData
case d: TLBundleD => true.B // Grant isResponse + isRequest
case e: TLBundleE => true.B
}
}
def hasData(x: TLChannel): Bool = {
val opdata = x match {
case a: TLBundleA => !a.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case b: TLBundleB => !b.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case c: TLBundleC => c.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.ProbeAckData ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
staticHasData(x).map(_.B).getOrElse(opdata)
}
def opcode(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.opcode
case b: TLBundleB => b.opcode
case c: TLBundleC => c.opcode
case d: TLBundleD => d.opcode
}
}
def param(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.param
case b: TLBundleB => b.param
case c: TLBundleC => c.param
case d: TLBundleD => d.param
}
}
def size(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.size
case b: TLBundleB => b.size
case c: TLBundleC => c.size
case d: TLBundleD => d.size
}
}
def data(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.data
case b: TLBundleB => b.data
case c: TLBundleC => c.data
case d: TLBundleD => d.data
}
}
def corrupt(x: TLDataChannel): Bool = {
x match {
case a: TLBundleA => a.corrupt
case b: TLBundleB => b.corrupt
case c: TLBundleC => c.corrupt
case d: TLBundleD => d.corrupt
}
}
def mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.mask
case b: TLBundleB => b.mask
case c: TLBundleC => mask(c.address, c.size)
}
}
def full_mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => mask(a.address, a.size)
case b: TLBundleB => mask(b.address, b.size)
case c: TLBundleC => mask(c.address, c.size)
}
}
def address(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.address
case b: TLBundleB => b.address
case c: TLBundleC => c.address
}
}
def source(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.source
case b: TLBundleB => b.source
case c: TLBundleC => c.source
case d: TLBundleD => d.source
}
}
def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes)
def addr_lo(x: UInt): UInt =
if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0)
def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x))
def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x))
def numBeats(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 1.U
case bundle: TLDataChannel => {
val hasData = this.hasData(bundle)
val size = this.size(bundle)
val cutoff = log2Ceil(manager.beatBytes)
val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U
val decode = UIntToOH(size, maxLgSize+1) >> cutoff
Mux(hasData, decode | small.asUInt, 1.U)
}
}
}
def numBeats1(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 0.U
case bundle: TLDataChannel => {
if (maxLgSize == 0) {
0.U
} else {
val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes)
Mux(hasData(bundle), decode, 0.U)
}
}
}
}
def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val beats1 = numBeats1(bits)
val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W))
val counter1 = counter - 1.U
val first = counter === 0.U
val last = counter === 1.U || beats1 === 0.U
val done = last && fire
val count = (beats1 & ~counter1)
when (fire) {
counter := Mux(first, beats1, counter1)
}
(first, last, done, count)
}
def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1
def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire)
def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid)
def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2
def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire)
def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid)
def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3
def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire)
def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid)
def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3)
}
def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire)
def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid)
def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4)
}
def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire)
def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid)
def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes))
}
def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire)
def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid)
// Does the request need T permissions to be executed?
def needT(a: TLBundleA): Bool = {
val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLPermissions.NtoB -> false.B,
TLPermissions.NtoT -> true.B,
TLPermissions.BtoT -> true.B))
MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array(
TLMessages.PutFullData -> true.B,
TLMessages.PutPartialData -> true.B,
TLMessages.ArithmeticData -> true.B,
TLMessages.LogicalData -> true.B,
TLMessages.Get -> false.B,
TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLHints.PREFETCH_READ -> false.B,
TLHints.PREFETCH_WRITE -> true.B)),
TLMessages.AcquireBlock -> acq_needT,
TLMessages.AcquirePerm -> acq_needT))
}
// This is a very expensive circuit; use only if you really mean it!
def inFlight(x: TLBundle): (UInt, UInt) = {
val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W))
val bce = manager.anySupportAcquireB && client.anySupportProbe
val (a_first, a_last, _) = firstlast(x.a)
val (b_first, b_last, _) = firstlast(x.b)
val (c_first, c_last, _) = firstlast(x.c)
val (d_first, d_last, _) = firstlast(x.d)
val (e_first, e_last, _) = firstlast(x.e)
val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits))
val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits))
val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits))
val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits))
val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits))
val a_inc = x.a.fire && a_first && a_request
val b_inc = x.b.fire && b_first && b_request
val c_inc = x.c.fire && c_first && c_request
val d_inc = x.d.fire && d_first && d_request
val e_inc = x.e.fire && e_first && e_request
val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil))
val a_dec = x.a.fire && a_last && a_response
val b_dec = x.b.fire && b_last && b_response
val c_dec = x.c.fire && c_last && c_response
val d_dec = x.d.fire && d_last && d_response
val e_dec = x.e.fire && e_last && e_response
val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil))
val next_flight = flight + PopCount(inc) - PopCount(dec)
flight := next_flight
(flight, next_flight)
}
def prettySourceMapping(context: String): String = {
s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n"
}
}
class TLEdgeOut(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
// Transfers
def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquireBlock
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquirePerm
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.Release
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ReleaseData
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) =
Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B)
def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAck
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions, data)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAckData
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B)
def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink)
def GrantAck(toSink: UInt): TLBundleE = {
val e = Wire(new TLBundleE(bundle))
e.sink := toSink
e
}
// Accesses
def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsGetFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Get
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutFullFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutFullData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, mask, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutPartialFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutPartialData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = {
require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsArithmeticFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.ArithmeticData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsLogicalFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.LogicalData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = {
require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsHintFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Hint
a.param := param
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data)
def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAckData
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size)
def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.HintAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
}
class TLEdgeIn(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = {
val todo = x.filter(!_.isEmpty)
val heads = todo.map(_.head)
val tails = todo.map(_.tail)
if (todo.isEmpty) Nil else { heads +: myTranspose(tails) }
}
// Transfers
def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = {
require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}")
val legal = client.supportsProbe(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Probe
b.param := capPermissions
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.Grant
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.GrantData
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B)
def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.ReleaseAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
// Accesses
def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = {
require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsGet(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Get
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsPutFull(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutFullData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, mask, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsPutPartial(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutPartialData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsArithmetic(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.ArithmeticData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsLogical(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.LogicalData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = {
require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsHint(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Hint
b.param := param
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size)
def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied)
def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data)
def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAckData
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B)
def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied)
def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B)
def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.HintAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
}
| module TLMonitor_22( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14]
input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_source, // @[Monitor.scala:20:14]
input [13:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14]
input io_in_a_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input [7:0] io_in_d_bits_source, // @[Monitor.scala:20:14]
input io_in_d_bits_corrupt // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7]
wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7]
wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7]
wire [7:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7]
wire [13:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7]
wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7]
wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7]
wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7]
wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7]
wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7]
wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7]
wire [7:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7]
wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7]
wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7]
wire sink_ok = 1'h0; // @[Monitor.scala:309:31]
wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35]
wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36]
wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25]
wire c_first_done = 1'h0; // @[Edges.scala:233:22]
wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47]
wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95]
wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71]
wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44]
wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36]
wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51]
wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40]
wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55]
wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88]
wire [8:0] c_first_beats1_decode = 9'h0; // @[Edges.scala:220:59]
wire [8:0] c_first_beats1 = 9'h0; // @[Edges.scala:221:14]
wire [8:0] _c_first_count_T = 9'h0; // @[Edges.scala:234:27]
wire [8:0] c_first_count = 9'h0; // @[Edges.scala:234:25]
wire [8:0] _c_first_counter_T = 9'h0; // @[Edges.scala:236:21]
wire io_in_d_bits_denied = 1'h1; // @[Monitor.scala:36:7]
wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_17 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_21 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_23 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_27 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_29 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_33 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_35 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_53 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_55 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_59 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_61 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_65 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_67 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_71 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_73 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_77 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_79 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_83 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_85 = 1'h1; // @[Parameters.scala:57:20]
wire c_first = 1'h1; // @[Edges.scala:231:25]
wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire c_first_last = 1'h1; // @[Edges.scala:232:33]
wire [8:0] c_first_counter1 = 9'h1FF; // @[Edges.scala:230:28]
wire [9:0] _c_first_counter1_T = 10'h3FF; // @[Edges.scala:230:28]
wire [1:0] io_in_d_bits_param = 2'h0; // @[Monitor.scala:36:7]
wire [63:0] io_in_d_bits_data = 64'h0; // @[Monitor.scala:36:7]
wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [13:0] _c_first_WIRE_bits_address = 14'h0; // @[Bundles.scala:265:74]
wire [13:0] _c_first_WIRE_1_bits_address = 14'h0; // @[Bundles.scala:265:61]
wire [13:0] _c_first_WIRE_2_bits_address = 14'h0; // @[Bundles.scala:265:74]
wire [13:0] _c_first_WIRE_3_bits_address = 14'h0; // @[Bundles.scala:265:61]
wire [13:0] _c_set_wo_ready_WIRE_bits_address = 14'h0; // @[Bundles.scala:265:74]
wire [13:0] _c_set_wo_ready_WIRE_1_bits_address = 14'h0; // @[Bundles.scala:265:61]
wire [13:0] _c_set_WIRE_bits_address = 14'h0; // @[Bundles.scala:265:74]
wire [13:0] _c_set_WIRE_1_bits_address = 14'h0; // @[Bundles.scala:265:61]
wire [13:0] _c_opcodes_set_interm_WIRE_bits_address = 14'h0; // @[Bundles.scala:265:74]
wire [13:0] _c_opcodes_set_interm_WIRE_1_bits_address = 14'h0; // @[Bundles.scala:265:61]
wire [13:0] _c_sizes_set_interm_WIRE_bits_address = 14'h0; // @[Bundles.scala:265:74]
wire [13:0] _c_sizes_set_interm_WIRE_1_bits_address = 14'h0; // @[Bundles.scala:265:61]
wire [13:0] _c_opcodes_set_WIRE_bits_address = 14'h0; // @[Bundles.scala:265:74]
wire [13:0] _c_opcodes_set_WIRE_1_bits_address = 14'h0; // @[Bundles.scala:265:61]
wire [13:0] _c_sizes_set_WIRE_bits_address = 14'h0; // @[Bundles.scala:265:74]
wire [13:0] _c_sizes_set_WIRE_1_bits_address = 14'h0; // @[Bundles.scala:265:61]
wire [13:0] _c_probe_ack_WIRE_bits_address = 14'h0; // @[Bundles.scala:265:74]
wire [13:0] _c_probe_ack_WIRE_1_bits_address = 14'h0; // @[Bundles.scala:265:61]
wire [13:0] _c_probe_ack_WIRE_2_bits_address = 14'h0; // @[Bundles.scala:265:74]
wire [13:0] _c_probe_ack_WIRE_3_bits_address = 14'h0; // @[Bundles.scala:265:61]
wire [13:0] _same_cycle_resp_WIRE_bits_address = 14'h0; // @[Bundles.scala:265:74]
wire [13:0] _same_cycle_resp_WIRE_1_bits_address = 14'h0; // @[Bundles.scala:265:61]
wire [13:0] _same_cycle_resp_WIRE_2_bits_address = 14'h0; // @[Bundles.scala:265:74]
wire [13:0] _same_cycle_resp_WIRE_3_bits_address = 14'h0; // @[Bundles.scala:265:61]
wire [13:0] _same_cycle_resp_WIRE_4_bits_address = 14'h0; // @[Bundles.scala:265:74]
wire [13:0] _same_cycle_resp_WIRE_5_bits_address = 14'h0; // @[Bundles.scala:265:61]
wire [7:0] _c_first_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _c_first_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _c_first_WIRE_2_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _c_first_WIRE_3_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _c_set_wo_ready_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _c_set_wo_ready_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _c_set_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _c_set_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _c_opcodes_set_interm_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _c_opcodes_set_interm_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _c_sizes_set_interm_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _c_sizes_set_interm_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _c_opcodes_set_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _c_opcodes_set_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _c_sizes_set_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _c_sizes_set_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _c_probe_ack_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _c_probe_ack_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _c_probe_ack_WIRE_2_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _c_probe_ack_WIRE_3_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _same_cycle_resp_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _same_cycle_resp_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _same_cycle_resp_WIRE_2_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _same_cycle_resp_WIRE_3_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _same_cycle_resp_WIRE_4_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _same_cycle_resp_WIRE_5_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_first_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_first_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_first_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_first_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40]
wire [3:0] _c_set_wo_ready_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_set_wo_ready_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53]
wire [3:0] _c_sizes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_sizes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_opcodes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_sizes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_sizes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_probe_ack_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_probe_ack_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_probe_ack_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_probe_ack_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_4_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_5_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57]
wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57]
wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57]
wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57]
wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57]
wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57]
wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57]
wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57]
wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51]
wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51]
wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51]
wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51]
wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [2051:0] _c_sizes_set_T_1 = 2052'h0; // @[Monitor.scala:768:52]
wire [10:0] _c_opcodes_set_T = 11'h0; // @[Monitor.scala:767:79]
wire [10:0] _c_sizes_set_T = 11'h0; // @[Monitor.scala:768:77]
wire [2050:0] _c_opcodes_set_T_1 = 2051'h0; // @[Monitor.scala:767:54]
wire [4:0] _c_sizes_set_interm_T_1 = 5'h1; // @[Monitor.scala:766:59]
wire [4:0] c_sizes_set_interm = 5'h0; // @[Monitor.scala:755:40]
wire [4:0] _c_sizes_set_interm_T = 5'h0; // @[Monitor.scala:766:51]
wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61]
wire [255:0] _c_set_wo_ready_T = 256'h1; // @[OneHot.scala:58:35]
wire [255:0] _c_set_T = 256'h1; // @[OneHot.scala:58:35]
wire [1031:0] c_sizes_set = 1032'h0; // @[Monitor.scala:741:34]
wire [515:0] c_opcodes_set = 516'h0; // @[Monitor.scala:740:34]
wire [128:0] c_set = 129'h0; // @[Monitor.scala:738:34]
wire [128:0] c_set_wo_ready = 129'h0; // @[Monitor.scala:739:34]
wire [11:0] _c_first_beats1_decode_T_2 = 12'h0; // @[package.scala:243:46]
wire [11:0] _c_first_beats1_decode_T_1 = 12'hFFF; // @[package.scala:243:76]
wire [26:0] _c_first_beats1_decode_T = 27'hFFF; // @[package.scala:243:71]
wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42]
wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42]
wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42]
wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123]
wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48]
wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123]
wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48]
wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117]
wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48]
wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119]
wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48]
wire [3:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34]
wire [7:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_36 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_37 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_38 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_39 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_40 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_41 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_42 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_43 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_44 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_45 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_46 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_47 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_48 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_49 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_50 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_51 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_52 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_53 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_54 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_55 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_56 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_57 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_58 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_59 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_60 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_61 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_62 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_63 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_64 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_65 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_uncommonBits_T_6 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_uncommonBits_T_7 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_uncommonBits_T_8 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_uncommonBits_T_9 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_uncommonBits_T_10 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_uncommonBits_T_11 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire _source_ok_T = io_in_a_bits_source_0 == 8'h30; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] _source_ok_T_1 = io_in_a_bits_source_0[7:2]; // @[Monitor.scala:36:7]
wire [5:0] _source_ok_T_7 = io_in_a_bits_source_0[7:2]; // @[Monitor.scala:36:7]
wire [5:0] _source_ok_T_13 = io_in_a_bits_source_0[7:2]; // @[Monitor.scala:36:7]
wire [5:0] _source_ok_T_19 = io_in_a_bits_source_0[7:2]; // @[Monitor.scala:36:7]
wire _source_ok_T_2 = _source_ok_T_1 == 6'h8; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_4 = _source_ok_T_2; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_6 = _source_ok_T_4; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_8 = _source_ok_T_7 == 6'h9; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_10 = _source_ok_T_8; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_12 = _source_ok_T_10; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_2 = _source_ok_T_12; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_14 = _source_ok_T_13 == 6'hA; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_16 = _source_ok_T_14; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_18 = _source_ok_T_16; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_3 = _source_ok_T_18; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_20 = _source_ok_T_19 == 6'hB; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_22 = _source_ok_T_20; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_24 = _source_ok_T_22; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_4 = _source_ok_T_24; // @[Parameters.scala:1138:31]
wire [3:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[3:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] _source_ok_T_25 = io_in_a_bits_source_0[7:4]; // @[Monitor.scala:36:7]
wire [3:0] _source_ok_T_31 = io_in_a_bits_source_0[7:4]; // @[Monitor.scala:36:7]
wire _source_ok_T_26 = _source_ok_T_25 == 4'h1; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_28 = _source_ok_T_26; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_30 = _source_ok_T_28; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_5 = _source_ok_T_30; // @[Parameters.scala:1138:31]
wire [3:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[3:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_32 = _source_ok_T_31 == 4'h0; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_34 = _source_ok_T_32; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_36 = _source_ok_T_34; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_6 = _source_ok_T_36; // @[Parameters.scala:1138:31]
wire _source_ok_T_37 = io_in_a_bits_source_0 == 8'h40; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_7 = _source_ok_T_37; // @[Parameters.scala:1138:31]
wire _source_ok_T_38 = io_in_a_bits_source_0 == 8'h41; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_8 = _source_ok_T_38; // @[Parameters.scala:1138:31]
wire _source_ok_T_39 = io_in_a_bits_source_0 == 8'h42; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_9 = _source_ok_T_39; // @[Parameters.scala:1138:31]
wire _source_ok_T_40 = io_in_a_bits_source_0 == 8'h80; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_10 = _source_ok_T_40; // @[Parameters.scala:1138:31]
wire _source_ok_T_41 = _source_ok_WIRE_0 | _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_42 = _source_ok_T_41 | _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_43 = _source_ok_T_42 | _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_44 = _source_ok_T_43 | _source_ok_WIRE_4; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_45 = _source_ok_T_44 | _source_ok_WIRE_5; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_46 = _source_ok_T_45 | _source_ok_WIRE_6; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_47 = _source_ok_T_46 | _source_ok_WIRE_7; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_48 = _source_ok_T_47 | _source_ok_WIRE_8; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_49 = _source_ok_T_48 | _source_ok_WIRE_9; // @[Parameters.scala:1138:31, :1139:46]
wire source_ok = _source_ok_T_49 | _source_ok_WIRE_10; // @[Parameters.scala:1138:31, :1139:46]
wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71]
wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71]
assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71]
wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71]
assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71]
wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71]
wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}]
wire [13:0] _is_aligned_T = {2'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46]
wire is_aligned = _is_aligned_T == 14'h0; // @[Edges.scala:21:{16,24}]
wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12]
wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}]
wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27]
wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 4'h2; // @[Misc.scala:206:21]
wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26]
wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}]
wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}]
wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26]
wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26]
wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26]
wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20]
wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}]
wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}]
wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}]
wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}]
wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10]
wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10]
wire [1:0] uncommonBits = _uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_4 = _uncommonBits_T_4[3:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_5 = _uncommonBits_T_5[3:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_6 = _uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_7 = _uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_9 = _uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_10 = _uncommonBits_T_10[3:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_11 = _uncommonBits_T_11[3:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_12 = _uncommonBits_T_12[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_13 = _uncommonBits_T_13[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_14 = _uncommonBits_T_14[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_16 = _uncommonBits_T_16[3:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_17 = _uncommonBits_T_17[3:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_18 = _uncommonBits_T_18[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_19 = _uncommonBits_T_19[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_20 = _uncommonBits_T_20[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_21 = _uncommonBits_T_21[1:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_22 = _uncommonBits_T_22[3:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_23 = _uncommonBits_T_23[3:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_24 = _uncommonBits_T_24[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_25 = _uncommonBits_T_25[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_26 = _uncommonBits_T_26[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_27 = _uncommonBits_T_27[1:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_28 = _uncommonBits_T_28[3:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_29 = _uncommonBits_T_29[3:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_30 = _uncommonBits_T_30[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_31 = _uncommonBits_T_31[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_32 = _uncommonBits_T_32[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_33 = _uncommonBits_T_33[1:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_34 = _uncommonBits_T_34[3:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_35 = _uncommonBits_T_35[3:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_36 = _uncommonBits_T_36[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_37 = _uncommonBits_T_37[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_38 = _uncommonBits_T_38[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_39 = _uncommonBits_T_39[1:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_40 = _uncommonBits_T_40[3:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_41 = _uncommonBits_T_41[3:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_42 = _uncommonBits_T_42[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_43 = _uncommonBits_T_43[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_44 = _uncommonBits_T_44[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_45 = _uncommonBits_T_45[1:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_46 = _uncommonBits_T_46[3:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_47 = _uncommonBits_T_47[3:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_48 = _uncommonBits_T_48[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_49 = _uncommonBits_T_49[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_50 = _uncommonBits_T_50[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_51 = _uncommonBits_T_51[1:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_52 = _uncommonBits_T_52[3:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_53 = _uncommonBits_T_53[3:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_54 = _uncommonBits_T_54[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_55 = _uncommonBits_T_55[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_56 = _uncommonBits_T_56[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_57 = _uncommonBits_T_57[1:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_58 = _uncommonBits_T_58[3:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_59 = _uncommonBits_T_59[3:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_60 = _uncommonBits_T_60[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_61 = _uncommonBits_T_61[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_62 = _uncommonBits_T_62[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_63 = _uncommonBits_T_63[1:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_64 = _uncommonBits_T_64[3:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_65 = _uncommonBits_T_65[3:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_50 = io_in_d_bits_source_0 == 8'h30; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_0 = _source_ok_T_50; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] _source_ok_T_51 = io_in_d_bits_source_0[7:2]; // @[Monitor.scala:36:7]
wire [5:0] _source_ok_T_57 = io_in_d_bits_source_0[7:2]; // @[Monitor.scala:36:7]
wire [5:0] _source_ok_T_63 = io_in_d_bits_source_0[7:2]; // @[Monitor.scala:36:7]
wire [5:0] _source_ok_T_69 = io_in_d_bits_source_0[7:2]; // @[Monitor.scala:36:7]
wire _source_ok_T_52 = _source_ok_T_51 == 6'h8; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_54 = _source_ok_T_52; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_56 = _source_ok_T_54; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_1 = _source_ok_T_56; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_58 = _source_ok_T_57 == 6'h9; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_60 = _source_ok_T_58; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_62 = _source_ok_T_60; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_2 = _source_ok_T_62; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_8 = _source_ok_uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_64 = _source_ok_T_63 == 6'hA; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_66 = _source_ok_T_64; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_68 = _source_ok_T_66; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_3 = _source_ok_T_68; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_9 = _source_ok_uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_70 = _source_ok_T_69 == 6'hB; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_72 = _source_ok_T_70; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_74 = _source_ok_T_72; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_4 = _source_ok_T_74; // @[Parameters.scala:1138:31]
wire [3:0] source_ok_uncommonBits_10 = _source_ok_uncommonBits_T_10[3:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] _source_ok_T_75 = io_in_d_bits_source_0[7:4]; // @[Monitor.scala:36:7]
wire [3:0] _source_ok_T_81 = io_in_d_bits_source_0[7:4]; // @[Monitor.scala:36:7]
wire _source_ok_T_76 = _source_ok_T_75 == 4'h1; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_78 = _source_ok_T_76; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_80 = _source_ok_T_78; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_5 = _source_ok_T_80; // @[Parameters.scala:1138:31]
wire [3:0] source_ok_uncommonBits_11 = _source_ok_uncommonBits_T_11[3:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_82 = _source_ok_T_81 == 4'h0; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_84 = _source_ok_T_82; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_86 = _source_ok_T_84; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_6 = _source_ok_T_86; // @[Parameters.scala:1138:31]
wire _source_ok_T_87 = io_in_d_bits_source_0 == 8'h40; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_7 = _source_ok_T_87; // @[Parameters.scala:1138:31]
wire _source_ok_T_88 = io_in_d_bits_source_0 == 8'h41; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_8 = _source_ok_T_88; // @[Parameters.scala:1138:31]
wire _source_ok_T_89 = io_in_d_bits_source_0 == 8'h42; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_9 = _source_ok_T_89; // @[Parameters.scala:1138:31]
wire _source_ok_T_90 = io_in_d_bits_source_0 == 8'h80; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_10 = _source_ok_T_90; // @[Parameters.scala:1138:31]
wire _source_ok_T_91 = _source_ok_WIRE_1_0 | _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_92 = _source_ok_T_91 | _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_93 = _source_ok_T_92 | _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_94 = _source_ok_T_93 | _source_ok_WIRE_1_4; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_95 = _source_ok_T_94 | _source_ok_WIRE_1_5; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_96 = _source_ok_T_95 | _source_ok_WIRE_1_6; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_97 = _source_ok_T_96 | _source_ok_WIRE_1_7; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_98 = _source_ok_T_97 | _source_ok_WIRE_1_8; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_99 = _source_ok_T_98 | _source_ok_WIRE_1_9; // @[Parameters.scala:1138:31, :1139:46]
wire source_ok_1 = _source_ok_T_99 | _source_ok_WIRE_1_10; // @[Parameters.scala:1138:31, :1139:46]
wire _T_1282 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35]
wire _a_first_T; // @[Decoupled.scala:51:35]
assign _a_first_T = _T_1282; // @[Decoupled.scala:51:35]
wire _a_first_T_1; // @[Decoupled.scala:51:35]
assign _a_first_T_1 = _T_1282; // @[Decoupled.scala:51:35]
wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [8:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46]
wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}]
wire [8:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [8:0] a_first_counter; // @[Edges.scala:229:27]
wire [9:0] _a_first_counter1_T = {1'h0, a_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] a_first_counter1 = _a_first_counter1_T[8:0]; // @[Edges.scala:230:28]
wire a_first = a_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T = a_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_1 = a_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35]
wire [8:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [8:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [2:0] param; // @[Monitor.scala:388:22]
reg [3:0] size; // @[Monitor.scala:389:22]
reg [7:0] source; // @[Monitor.scala:390:22]
reg [13:0] address; // @[Monitor.scala:391:22]
wire _T_1355 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35]
wire _d_first_T; // @[Decoupled.scala:51:35]
assign _d_first_T = _T_1355; // @[Decoupled.scala:51:35]
wire _d_first_T_1; // @[Decoupled.scala:51:35]
assign _d_first_T_1 = _T_1355; // @[Decoupled.scala:51:35]
wire _d_first_T_2; // @[Decoupled.scala:51:35]
assign _d_first_T_2 = _T_1355; // @[Decoupled.scala:51:35]
wire [26:0] _GEN_0 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71]
assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71]
wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [8:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46]
wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire [8:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [8:0] d_first_counter; // @[Edges.scala:229:27]
wire [9:0] _d_first_counter1_T = {1'h0, d_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] d_first_counter1 = _d_first_counter1_T[8:0]; // @[Edges.scala:230:28]
wire d_first = d_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T = d_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_1 = d_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35]
wire [8:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [8:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [3:0] size_1; // @[Monitor.scala:540:22]
reg [7:0] source_1; // @[Monitor.scala:541:22]
reg [128:0] inflight; // @[Monitor.scala:614:27]
reg [515:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [1031:0] inflight_sizes; // @[Monitor.scala:618:33]
wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [8:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46]
wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}]
wire [8:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [8:0] a_first_counter_1; // @[Edges.scala:229:27]
wire [9:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] a_first_counter1_1 = _a_first_counter1_T_1[8:0]; // @[Edges.scala:230:28]
wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T_2 = a_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_3 = a_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35]
wire [8:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [8:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [8:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46]
wire [8:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [8:0] d_first_counter_1; // @[Edges.scala:229:27]
wire [9:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] d_first_counter1_1 = _d_first_counter1_T_1[8:0]; // @[Edges.scala:230:28]
wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_2 = d_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_3 = d_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35]
wire [8:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [8:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [128:0] a_set; // @[Monitor.scala:626:34]
wire [128:0] a_set_wo_ready; // @[Monitor.scala:627:34]
wire [515:0] a_opcodes_set; // @[Monitor.scala:630:33]
wire [1031:0] a_sizes_set; // @[Monitor.scala:632:31]
wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35]
wire [10:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69]
wire [10:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69]
assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69]
wire [10:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101]
assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101]
wire [10:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69]
assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69]
wire [10:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101]
assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101]
wire [515:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}]
wire [515:0] _a_opcode_lookup_T_6 = {512'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}]
wire [515:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[515:1]}; // @[Monitor.scala:637:{97,152}]
assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}]
wire [7:0] a_size_lookup; // @[Monitor.scala:639:33]
wire [10:0] _GEN_2 = {io_in_d_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :641:65]
wire [10:0] _a_size_lookup_T; // @[Monitor.scala:641:65]
assign _a_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65]
wire [10:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99]
assign _d_sizes_clr_T_4 = _GEN_2; // @[Monitor.scala:641:65, :681:99]
wire [10:0] _c_size_lookup_T; // @[Monitor.scala:750:67]
assign _c_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65, :750:67]
wire [10:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99]
assign _d_sizes_clr_T_10 = _GEN_2; // @[Monitor.scala:641:65, :791:99]
wire [1031:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}]
wire [1031:0] _a_size_lookup_T_6 = {1024'h0, _a_size_lookup_T_1[7:0]}; // @[Monitor.scala:641:{40,91}]
wire [1031:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[1031:1]}; // @[Monitor.scala:641:{91,144}]
assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}]
wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40]
wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38]
wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44]
wire [255:0] _GEN_3 = 256'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35]
wire [255:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35]
assign _a_set_wo_ready_T = _GEN_3; // @[OneHot.scala:58:35]
wire [255:0] _a_set_T; // @[OneHot.scala:58:35]
assign _a_set_T = _GEN_3; // @[OneHot.scala:58:35]
assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[128:0] : 129'h0; // @[OneHot.scala:58:35]
wire _T_1208 = _T_1282 & a_first_1; // @[Decoupled.scala:51:35]
assign a_set = _T_1208 ? _a_set_T[128:0] : 129'h0; // @[OneHot.scala:58:35]
wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53]
wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}]
assign a_opcodes_set_interm = _T_1208 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}]
wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51]
wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}]
assign a_sizes_set_interm = _T_1208 ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}]
wire [10:0] _a_opcodes_set_T = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79]
wire [2050:0] _a_opcodes_set_T_1 = {2047'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}]
assign a_opcodes_set = _T_1208 ? _a_opcodes_set_T_1[515:0] : 516'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}]
wire [10:0] _a_sizes_set_T = {io_in_a_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :660:77]
wire [2051:0] _a_sizes_set_T_1 = {2047'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}]
assign a_sizes_set = _T_1208 ? _a_sizes_set_T_1[1031:0] : 1032'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}]
wire [128:0] d_clr; // @[Monitor.scala:664:34]
wire [128:0] d_clr_wo_ready; // @[Monitor.scala:665:34]
wire [515:0] d_opcodes_clr; // @[Monitor.scala:668:33]
wire [1031:0] d_sizes_clr; // @[Monitor.scala:670:31]
wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46]
wire d_release_ack; // @[Monitor.scala:673:46]
assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46]
wire d_release_ack_1; // @[Monitor.scala:783:46]
assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46]
wire _T_1254 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26]
wire [255:0] _GEN_5 = 256'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35]
wire [255:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35]
wire [255:0] _d_clr_T; // @[OneHot.scala:58:35]
assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35]
wire [255:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35]
wire [255:0] _d_clr_T_1; // @[OneHot.scala:58:35]
assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35]
assign d_clr_wo_ready = _T_1254 & ~d_release_ack ? _d_clr_wo_ready_T[128:0] : 129'h0; // @[OneHot.scala:58:35]
wire _T_1223 = _T_1355 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35]
assign d_clr = _T_1223 ? _d_clr_T[128:0] : 129'h0; // @[OneHot.scala:58:35]
wire [2062:0] _d_opcodes_clr_T_5 = 2063'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}]
assign d_opcodes_clr = _T_1223 ? _d_opcodes_clr_T_5[515:0] : 516'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}]
wire [2062:0] _d_sizes_clr_T_5 = 2063'hFF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}]
assign d_sizes_clr = _T_1223 ? _d_sizes_clr_T_5[1031:0] : 1032'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}]
wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}]
wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113]
wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}]
wire [128:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27]
wire [128:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38]
wire [128:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}]
wire [515:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43]
wire [515:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62]
wire [515:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}]
wire [1031:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39]
wire [1031:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56]
wire [1031:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26]
wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26]
reg [128:0] inflight_1; // @[Monitor.scala:726:35]
wire [128:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35]
reg [515:0] inflight_opcodes_1; // @[Monitor.scala:727:35]
wire [515:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43]
reg [1031:0] inflight_sizes_1; // @[Monitor.scala:728:35]
wire [1031:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41]
wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}]
wire [8:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:3]; // @[package.scala:243:46]
wire [8:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [8:0] d_first_counter_2; // @[Edges.scala:229:27]
wire [9:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] d_first_counter1_2 = _d_first_counter1_T_2[8:0]; // @[Edges.scala:230:28]
wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_4 = d_first_counter_2 == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_5 = d_first_beats1_2 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35]
wire [8:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27]
wire [8:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35]
wire [7:0] c_size_lookup; // @[Monitor.scala:748:35]
wire [515:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}]
wire [515:0] _c_opcode_lookup_T_6 = {512'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}]
wire [515:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[515:1]}; // @[Monitor.scala:749:{97,152}]
assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}]
wire [1031:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}]
wire [1031:0] _c_size_lookup_T_6 = {1024'h0, _c_size_lookup_T_1[7:0]}; // @[Monitor.scala:750:{42,93}]
wire [1031:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[1031:1]}; // @[Monitor.scala:750:{93,146}]
assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}]
wire [128:0] d_clr_1; // @[Monitor.scala:774:34]
wire [128:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34]
wire [515:0] d_opcodes_clr_1; // @[Monitor.scala:776:34]
wire [1031:0] d_sizes_clr_1; // @[Monitor.scala:777:34]
wire _T_1326 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26]
assign d_clr_wo_ready_1 = _T_1326 & d_release_ack_1 ? _d_clr_wo_ready_T_1[128:0] : 129'h0; // @[OneHot.scala:58:35]
wire _T_1308 = _T_1355 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35]
assign d_clr_1 = _T_1308 ? _d_clr_T_1[128:0] : 129'h0; // @[OneHot.scala:58:35]
wire [2062:0] _d_opcodes_clr_T_11 = 2063'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}]
assign d_opcodes_clr_1 = _T_1308 ? _d_opcodes_clr_T_11[515:0] : 516'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}]
wire [2062:0] _d_sizes_clr_T_11 = 2063'hFF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}]
assign d_sizes_clr_1 = _T_1308 ? _d_sizes_clr_T_11[1031:0] : 1032'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}]
wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 8'h0; // @[Monitor.scala:36:7, :795:113]
wire [128:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46]
wire [128:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}]
wire [515:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62]
wire [515:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}]
wire [1031:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58]
wire [1031:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27] |
Generate the Verilog code corresponding to the following Chisel files.
File Tilelink.scala:
package constellation.protocol
import chisel3._
import chisel3.util._
import constellation.channel._
import constellation.noc._
import constellation.soc.{CanAttachToGlobalNoC}
import org.chipsalliance.cde.config._
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.util._
import freechips.rocketchip.tilelink._
import scala.collection.immutable.{ListMap}
trait TLFieldHelper {
def getBodyFields(b: TLChannel): Seq[Data] = b match {
case b: TLBundleA => Seq(b.mask, b.data, b.corrupt)
case b: TLBundleB => Seq(b.mask, b.data, b.corrupt)
case b: TLBundleC => Seq( b.data, b.corrupt)
case b: TLBundleD => Seq( b.data, b.corrupt)
case b: TLBundleE => Seq()
}
def getConstFields(b: TLChannel): Seq[Data] = b match {
case b: TLBundleA => Seq(b.opcode, b.param, b.size, b.source, b.address, b.user, b.echo )
case b: TLBundleB => Seq(b.opcode, b.param, b.size, b.source, b.address )
case b: TLBundleC => Seq(b.opcode, b.param, b.size, b.source, b.address, b.user, b.echo )
case b: TLBundleD => Seq(b.opcode, b.param, b.size, b.source, b.user, b.echo, b.sink, b.denied)
case b: TLBundleE => Seq( b.sink )
}
def minTLPayloadWidth(b: TLChannel): Int = Seq(getBodyFields(b), getConstFields(b)).map(_.map(_.getWidth).sum).max
def minTLPayloadWidth(bs: Seq[TLChannel]): Int = bs.map(b => minTLPayloadWidth(b)).max
def minTLPayloadWidth(b: TLBundle): Int = minTLPayloadWidth(Seq(b.a, b.b, b.c, b.d, b.e).map(_.bits))
}
class TLMasterToNoC(
edgeIn: TLEdge, edgesOut: Seq[TLEdge],
sourceStart: Int, sourceSize: Int,
wideBundle: TLBundleParameters,
slaveToEgressOffset: Int => Int,
flitWidth: Int
)(implicit p: Parameters) extends Module {
val io = IO(new Bundle {
val tilelink = Flipped(new TLBundle(wideBundle))
val flits = new Bundle {
val a = Decoupled(new IngressFlit(flitWidth))
val b = Flipped(Decoupled(new EgressFlit(flitWidth)))
val c = Decoupled(new IngressFlit(flitWidth))
val d = Flipped(Decoupled(new EgressFlit(flitWidth)))
val e = Decoupled(new IngressFlit(flitWidth))
}
})
val a = Module(new TLAToNoC(edgeIn, edgesOut, wideBundle, (i) => slaveToEgressOffset(i) + 0, sourceStart))
val b = Module(new TLBFromNoC(edgeIn, wideBundle, sourceSize))
val c = Module(new TLCToNoC(edgeIn, edgesOut, wideBundle, (i) => slaveToEgressOffset(i) + 1, sourceStart))
val d = Module(new TLDFromNoC(edgeIn, wideBundle, sourceSize))
val e = Module(new TLEToNoC(edgeIn, edgesOut, wideBundle, (i) => slaveToEgressOffset(i) + 2))
a.io.protocol <> io.tilelink.a
io.tilelink.b <> b.io.protocol
c.io.protocol <> io.tilelink.c
io.tilelink.d <> d.io.protocol
e.io.protocol <> io.tilelink.e
io.flits.a <> a.io.flit
b.io.flit <> io.flits.b
io.flits.c <> c.io.flit
d.io.flit <> io.flits.d
io.flits.e <> e.io.flit
}
class TLMasterACDToNoC(
edgeIn: TLEdge, edgesOut: Seq[TLEdge],
sourceStart: Int, sourceSize: Int,
wideBundle: TLBundleParameters,
slaveToEgressOffset: Int => Int,
flitWidth: Int
)(implicit p: Parameters) extends Module {
val io = IO(new Bundle {
val tilelink = Flipped(new TLBundle(wideBundle))
val flits = new Bundle {
val a = Decoupled(new IngressFlit(flitWidth))
val c = Decoupled(new IngressFlit(flitWidth))
val d = Flipped(Decoupled(new EgressFlit(flitWidth)))
}
})
io.tilelink := DontCare
val a = Module(new TLAToNoC(edgeIn, edgesOut, wideBundle, (i) => slaveToEgressOffset(i) + 0, sourceStart))
val c = Module(new TLCToNoC(edgeIn, edgesOut, wideBundle, (i) => slaveToEgressOffset(i) + 1, sourceStart))
val d = Module(new TLDFromNoC(edgeIn, wideBundle, sourceSize))
a.io.protocol <> io.tilelink.a
c.io.protocol <> io.tilelink.c
io.tilelink.d <> d.io.protocol
io.flits.a <> a.io.flit
io.flits.c <> c.io.flit
d.io.flit <> io.flits.d
}
class TLMasterBEToNoC(
edgeIn: TLEdge, edgesOut: Seq[TLEdge],
sourceStart: Int, sourceSize: Int,
wideBundle: TLBundleParameters,
slaveToEgressOffset: Int => Int,
flitWidth: Int
)(implicit p: Parameters) extends Module {
val io = IO(new Bundle {
val tilelink = Flipped(new TLBundle(wideBundle))
val flits = new Bundle {
val b = Flipped(Decoupled(new EgressFlit(flitWidth)))
val e = Decoupled(new IngressFlit(flitWidth))
}
})
io.tilelink := DontCare
val b = Module(new TLBFromNoC(edgeIn, wideBundle, sourceSize))
val e = Module(new TLEToNoC(edgeIn, edgesOut, wideBundle, (i) => slaveToEgressOffset(i) + 0))
io.tilelink.b <> b.io.protocol
e.io.protocol <> io.tilelink.e
b.io.flit <> io.flits.b
io.flits.e <> e.io.flit
}
class TLSlaveToNoC(
edgeOut: TLEdge, edgesIn: Seq[TLEdge],
sourceStart: Int, sourceSize: Int,
wideBundle: TLBundleParameters,
masterToEgressOffset: Int => Int,
flitWidth: Int
)(implicit p: Parameters) extends Module {
val io = IO(new Bundle {
val tilelink = new TLBundle(wideBundle)
val flits = new Bundle {
val a = Flipped(Decoupled(new EgressFlit(flitWidth)))
val b = Decoupled(new IngressFlit(flitWidth))
val c = Flipped(Decoupled(new EgressFlit(flitWidth)))
val d = Decoupled(new IngressFlit(flitWidth))
val e = Flipped(Decoupled(new EgressFlit(flitWidth)))
}
})
val a = Module(new TLAFromNoC(edgeOut, wideBundle))
val b = Module(new TLBToNoC(edgeOut, edgesIn, wideBundle, (i) => masterToEgressOffset(i) + 0))
val c = Module(new TLCFromNoC(edgeOut, wideBundle))
val d = Module(new TLDToNoC(edgeOut, edgesIn, wideBundle, (i) => masterToEgressOffset(i) + 1, sourceStart))
val e = Module(new TLEFromNoC(edgeOut, wideBundle, sourceSize))
io.tilelink.a <> a.io.protocol
b.io.protocol <> io.tilelink.b
io.tilelink.c <> c.io.protocol
d.io.protocol <> io.tilelink.d
io.tilelink.e <> e.io.protocol
a.io.flit <> io.flits.a
io.flits.b <> b.io.flit
c.io.flit <> io.flits.c
io.flits.d <> d.io.flit
e.io.flit <> io.flits.e
}
class TLSlaveACDToNoC(
edgeOut: TLEdge, edgesIn: Seq[TLEdge],
sourceStart: Int, sourceSize: Int,
wideBundle: TLBundleParameters,
masterToEgressOffset: Int => Int,
flitWidth: Int
)(implicit p: Parameters) extends Module {
val io = IO(new Bundle {
val tilelink = new TLBundle(wideBundle)
val flits = new Bundle {
val a = Flipped(Decoupled(new EgressFlit(flitWidth)))
val c = Flipped(Decoupled(new EgressFlit(flitWidth)))
val d = Decoupled(new IngressFlit(flitWidth))
}
})
io.tilelink := DontCare
val a = Module(new TLAFromNoC(edgeOut, wideBundle))
val c = Module(new TLCFromNoC(edgeOut, wideBundle))
val d = Module(new TLDToNoC(edgeOut, edgesIn, wideBundle, (i) => masterToEgressOffset(i) + 0, sourceStart))
io.tilelink.a <> a.io.protocol
io.tilelink.c <> c.io.protocol
d.io.protocol <> io.tilelink.d
a.io.flit <> io.flits.a
c.io.flit <> io.flits.c
io.flits.d <> d.io.flit
}
class TLSlaveBEToNoC(
edgeOut: TLEdge, edgesIn: Seq[TLEdge],
sourceStart: Int, sourceSize: Int,
wideBundle: TLBundleParameters,
masterToEgressOffset: Int => Int,
flitWidth: Int
)(implicit p: Parameters) extends Module {
val io = IO(new Bundle {
val tilelink = new TLBundle(wideBundle)
val flits = new Bundle {
val b = Decoupled(new IngressFlit(flitWidth))
val e = Flipped(Decoupled(new EgressFlit(flitWidth)))
}
})
io.tilelink := DontCare
val b = Module(new TLBToNoC(edgeOut, edgesIn, wideBundle, (i) => masterToEgressOffset(i) + 0))
val e = Module(new TLEFromNoC(edgeOut, wideBundle, sourceSize))
b.io.protocol <> io.tilelink.b
io.tilelink.e <> e.io.protocol
io.flits.b <> b.io.flit
e.io.flit <> io.flits.e
}
class TileLinkInterconnectInterface(edgesIn: Seq[TLEdge], edgesOut: Seq[TLEdge])(implicit val p: Parameters) extends Bundle {
val in = MixedVec(edgesIn.map { e => Flipped(new TLBundle(e.bundle)) })
val out = MixedVec(edgesOut.map { e => new TLBundle(e.bundle) })
}
trait TileLinkProtocolParams extends ProtocolParams with TLFieldHelper {
def edgesIn: Seq[TLEdge]
def edgesOut: Seq[TLEdge]
def edgeInNodes: Seq[Int]
def edgeOutNodes: Seq[Int]
require(edgesIn.size == edgeInNodes.size && edgesOut.size == edgeOutNodes.size)
def wideBundle = TLBundleParameters.union(edgesIn.map(_.bundle) ++ edgesOut.map(_.bundle))
def genBundle = new TLBundle(wideBundle)
def inputIdRanges = TLXbar.mapInputIds(edgesIn.map(_.client))
def outputIdRanges = TLXbar.mapOutputIds(edgesOut.map(_.manager))
val vNetBlocking = (blocker: Int, blockee: Int) => blocker < blockee
def genIO()(implicit p: Parameters): Data = new TileLinkInterconnectInterface(edgesIn, edgesOut)
}
object TLConnect {
def apply[T <: TLBundleBase](l: DecoupledIO[T], r: DecoupledIO[T]) = {
l.valid := r.valid
r.ready := l.ready
l.bits.squeezeAll.waiveAll :<>= r.bits.squeezeAll.waiveAll
}
}
// BEGIN: TileLinkProtocolParams
case class TileLinkABCDEProtocolParams(
edgesIn: Seq[TLEdge],
edgesOut: Seq[TLEdge],
edgeInNodes: Seq[Int],
edgeOutNodes: Seq[Int]
) extends TileLinkProtocolParams {
// END: TileLinkProtocolParams
val minPayloadWidth = minTLPayloadWidth(new TLBundle(wideBundle))
val ingressNodes = (edgeInNodes.map(u => Seq.fill(3) (u)) ++ edgeOutNodes.map(u => Seq.fill (2) {u})).flatten
val egressNodes = (edgeInNodes.map(u => Seq.fill(2) (u)) ++ edgeOutNodes.map(u => Seq.fill (3) {u})).flatten
val nVirtualNetworks = 5
val flows = edgesIn.zipWithIndex.map { case (edgeIn, ii) => edgesOut.zipWithIndex.map { case (edgeOut, oi) =>
val reachable = edgeIn.client.clients.exists { c => edgeOut.manager.managers.exists { m =>
c.visibility.exists { ca => m.address.exists { ma =>
ca.overlaps(ma)
}}
}}
val probe = edgeIn.client.anySupportProbe && edgeOut.manager.managers.exists(_.regionType >= RegionType.TRACKED)
val release = edgeIn.client.anySupportProbe && edgeOut.manager.anySupportAcquireB
( (if (reachable) Some(FlowParams(ii * 3 + 0 , oi * 3 + 0 + edgesIn.size * 2, 4)) else None) ++ // A
(if (probe ) Some(FlowParams(oi * 2 + 0 + edgesIn.size * 3, ii * 2 + 0 , 3)) else None) ++ // B
(if (release ) Some(FlowParams(ii * 3 + 1 , oi * 3 + 1 + edgesIn.size * 2, 2)) else None) ++ // C
(if (reachable) Some(FlowParams(oi * 2 + 1 + edgesIn.size * 3, ii * 2 + 1 , 1)) else None) ++ // D
(if (release ) Some(FlowParams(ii * 3 + 2 , oi * 3 + 2 + edgesIn.size * 2, 0)) else None)) // E
}}.flatten.flatten
def interface(terminals: NoCTerminalIO,
ingressOffset: Int, egressOffset: Int, protocol: Data)(implicit p: Parameters) = {
val ingresses = terminals.ingress
val egresses = terminals.egress
protocol match { case protocol: TileLinkInterconnectInterface => {
edgesIn.zipWithIndex.map { case (e,i) =>
val nif_master = Module(new TLMasterToNoC(
e, edgesOut, inputIdRanges(i).start, inputIdRanges(i).size,
wideBundle,
(s) => s * 3 + edgesIn.size * 2 + egressOffset,
minPayloadWidth
))
nif_master.io.tilelink := DontCare
nif_master.io.tilelink.a.valid := false.B
nif_master.io.tilelink.c.valid := false.B
nif_master.io.tilelink.e.valid := false.B
TLConnect(nif_master.io.tilelink.a, protocol.in(i).a)
TLConnect(protocol.in(i).d, nif_master.io.tilelink.d)
if (protocol.in(i).params.hasBCE) {
TLConnect(protocol.in(i).b, nif_master.io.tilelink.b)
TLConnect(nif_master.io.tilelink.c, protocol.in(i).c)
TLConnect(nif_master.io.tilelink.e, protocol.in(i).e)
}
ingresses(i * 3 + 0).flit <> nif_master.io.flits.a
ingresses(i * 3 + 1).flit <> nif_master.io.flits.c
ingresses(i * 3 + 2).flit <> nif_master.io.flits.e
nif_master.io.flits.b <> egresses(i * 2 + 0).flit
nif_master.io.flits.d <> egresses(i * 2 + 1).flit
}
edgesOut.zipWithIndex.map { case (e,i) =>
val nif_slave = Module(new TLSlaveToNoC(
e, edgesIn, outputIdRanges(i).start, outputIdRanges(i).size,
wideBundle,
(s) => s * 2 + egressOffset,
minPayloadWidth
))
nif_slave.io.tilelink := DontCare
nif_slave.io.tilelink.b.valid := false.B
nif_slave.io.tilelink.d.valid := false.B
TLConnect(protocol.out(i).a, nif_slave.io.tilelink.a)
TLConnect(nif_slave.io.tilelink.d, protocol.out(i).d)
if (protocol.out(i).params.hasBCE) {
TLConnect(nif_slave.io.tilelink.b, protocol.out(i).b)
TLConnect(protocol.out(i).c, nif_slave.io.tilelink.c)
TLConnect(protocol.out(i).e, nif_slave.io.tilelink.e)
}
ingresses(i * 2 + 0 + edgesIn.size * 3).flit <> nif_slave.io.flits.b
ingresses(i * 2 + 1 + edgesIn.size * 3).flit <> nif_slave.io.flits.d
nif_slave.io.flits.a <> egresses(i * 3 + 0 + edgesIn.size * 2).flit
nif_slave.io.flits.c <> egresses(i * 3 + 1 + edgesIn.size * 2).flit
nif_slave.io.flits.e <> egresses(i * 3 + 2 + edgesIn.size * 2).flit
}
} }
}
}
case class TileLinkACDProtocolParams(
edgesIn: Seq[TLEdge],
edgesOut: Seq[TLEdge],
edgeInNodes: Seq[Int],
edgeOutNodes: Seq[Int]) extends TileLinkProtocolParams {
val minPayloadWidth = minTLPayloadWidth(Seq(genBundle.a, genBundle.c, genBundle.d).map(_.bits))
val ingressNodes = (edgeInNodes.map(u => Seq.fill(2) (u)) ++ edgeOutNodes.map(u => Seq.fill (1) {u})).flatten
val egressNodes = (edgeInNodes.map(u => Seq.fill(1) (u)) ++ edgeOutNodes.map(u => Seq.fill (2) {u})).flatten
val nVirtualNetworks = 3
val flows = edgesIn.zipWithIndex.map { case (edgeIn, ii) => edgesOut.zipWithIndex.map { case (edgeOut, oi) =>
val reachable = edgeIn.client.clients.exists { c => edgeOut.manager.managers.exists { m =>
c.visibility.exists { ca => m.address.exists { ma =>
ca.overlaps(ma)
}}
}}
val release = edgeIn.client.anySupportProbe && edgeOut.manager.anySupportAcquireB
( (if (reachable) Some(FlowParams(ii * 2 + 0 , oi * 2 + 0 + edgesIn.size * 1, 2)) else None) ++ // A
(if (release ) Some(FlowParams(ii * 2 + 1 , oi * 2 + 1 + edgesIn.size * 1, 1)) else None) ++ // C
(if (reachable) Some(FlowParams(oi * 1 + 0 + edgesIn.size * 2, ii * 1 + 0 , 0)) else None)) // D
}}.flatten.flatten
def interface(terminals: NoCTerminalIO,
ingressOffset: Int, egressOffset: Int, protocol: Data)(implicit p: Parameters) = {
val ingresses = terminals.ingress
val egresses = terminals.egress
protocol match { case protocol: TileLinkInterconnectInterface => {
protocol := DontCare
edgesIn.zipWithIndex.map { case (e,i) =>
val nif_master_acd = Module(new TLMasterACDToNoC(
e, edgesOut, inputIdRanges(i).start, inputIdRanges(i).size,
wideBundle,
(s) => s * 2 + edgesIn.size * 1 + egressOffset,
minPayloadWidth
))
nif_master_acd.io.tilelink := DontCare
nif_master_acd.io.tilelink.a.valid := false.B
nif_master_acd.io.tilelink.c.valid := false.B
nif_master_acd.io.tilelink.e.valid := false.B
TLConnect(nif_master_acd.io.tilelink.a, protocol.in(i).a)
TLConnect(protocol.in(i).d, nif_master_acd.io.tilelink.d)
if (protocol.in(i).params.hasBCE) {
TLConnect(nif_master_acd.io.tilelink.c, protocol.in(i).c)
}
ingresses(i * 2 + 0).flit <> nif_master_acd.io.flits.a
ingresses(i * 2 + 1).flit <> nif_master_acd.io.flits.c
nif_master_acd.io.flits.d <> egresses(i * 1 + 0).flit
}
edgesOut.zipWithIndex.map { case (e,i) =>
val nif_slave_acd = Module(new TLSlaveACDToNoC(
e, edgesIn, outputIdRanges(i).start, outputIdRanges(i).size,
wideBundle,
(s) => s * 1 + egressOffset,
minPayloadWidth
))
nif_slave_acd.io.tilelink := DontCare
nif_slave_acd.io.tilelink.b.valid := false.B
nif_slave_acd.io.tilelink.d.valid := false.B
TLConnect(protocol.out(i).a, nif_slave_acd.io.tilelink.a)
TLConnect(nif_slave_acd.io.tilelink.d, protocol.out(i).d)
if (protocol.out(i).params.hasBCE) {
TLConnect(protocol.out(i).c, nif_slave_acd.io.tilelink.c)
}
ingresses(i * 1 + 0 + edgesIn.size * 2).flit <> nif_slave_acd.io.flits.d
nif_slave_acd.io.flits.a <> egresses(i * 2 + 0 + edgesIn.size * 1).flit
nif_slave_acd.io.flits.c <> egresses(i * 2 + 1 + edgesIn.size * 1).flit
}
}}
}
}
case class TileLinkBEProtocolParams(
edgesIn: Seq[TLEdge],
edgesOut: Seq[TLEdge],
edgeInNodes: Seq[Int],
edgeOutNodes: Seq[Int]) extends TileLinkProtocolParams {
val minPayloadWidth = minTLPayloadWidth(Seq(genBundle.b, genBundle.e).map(_.bits))
val ingressNodes = (edgeInNodes.map(u => Seq.fill(1) (u)) ++ edgeOutNodes.map(u => Seq.fill (1) {u})).flatten
val egressNodes = (edgeInNodes.map(u => Seq.fill(1) (u)) ++ edgeOutNodes.map(u => Seq.fill (1) {u})).flatten
val nVirtualNetworks = 2
val flows = edgesIn.zipWithIndex.map { case (edgeIn, ii) => edgesOut.zipWithIndex.map { case (edgeOut, oi) =>
val probe = edgeIn.client.anySupportProbe && edgeOut.manager.managers.exists(_.regionType >= RegionType.TRACKED)
val release = edgeIn.client.anySupportProbe && edgeOut.manager.anySupportAcquireB
( (if (probe ) Some(FlowParams(oi * 1 + 0 + edgesIn.size * 1, ii * 1 + 0 , 1)) else None) ++ // B
(if (release ) Some(FlowParams(ii * 1 + 0 , oi * 1 + 0 + edgesIn.size * 1, 0)) else None)) // E
}}.flatten.flatten
def interface(terminals: NoCTerminalIO,
ingressOffset: Int, egressOffset: Int, protocol: Data)(implicit p: Parameters) = {
val ingresses = terminals.ingress
val egresses = terminals.egress
protocol match { case protocol: TileLinkInterconnectInterface => {
protocol := DontCare
edgesIn.zipWithIndex.map { case (e,i) =>
val nif_master_be = Module(new TLMasterBEToNoC(
e, edgesOut, inputIdRanges(i).start, inputIdRanges(i).size,
wideBundle,
(s) => s * 1 + edgesIn.size * 1 + egressOffset,
minPayloadWidth
))
nif_master_be.io.tilelink := DontCare
nif_master_be.io.tilelink.a.valid := false.B
nif_master_be.io.tilelink.c.valid := false.B
nif_master_be.io.tilelink.e.valid := false.B
if (protocol.in(i).params.hasBCE) {
TLConnect(protocol.in(i).b, nif_master_be.io.tilelink.b)
TLConnect(nif_master_be.io.tilelink.e, protocol.in(i).e)
}
ingresses(i * 1 + 0).flit <> nif_master_be.io.flits.e
nif_master_be.io.flits.b <> egresses(i * 1 + 0).flit
}
edgesOut.zipWithIndex.map { case (e,i) =>
val nif_slave_be = Module(new TLSlaveBEToNoC(
e, edgesIn, outputIdRanges(i).start, outputIdRanges(i).size,
wideBundle,
(s) => s * 1 + egressOffset,
minPayloadWidth
))
nif_slave_be.io.tilelink := DontCare
nif_slave_be.io.tilelink.b.valid := false.B
nif_slave_be.io.tilelink.d.valid := false.B
if (protocol.out(i).params.hasBCE) {
TLConnect(protocol.out(i).e, nif_slave_be.io.tilelink.e)
TLConnect(nif_slave_be.io.tilelink.b, protocol.out(i).b)
}
ingresses(i * 1 + 0 + edgesIn.size * 1).flit <> nif_slave_be.io.flits.b
nif_slave_be.io.flits.e <> egresses(i * 1 + 0 + edgesIn.size * 1).flit
}
}}
}
}
abstract class TLNoCLike(implicit p: Parameters) extends LazyModule {
val node = new TLNexusNode(
clientFn = { seq =>
seq(0).v1copy(
echoFields = BundleField.union(seq.flatMap(_.echoFields)),
requestFields = BundleField.union(seq.flatMap(_.requestFields)),
responseKeys = seq.flatMap(_.responseKeys).distinct,
minLatency = seq.map(_.minLatency).min,
clients = (TLXbar.mapInputIds(seq) zip seq) flatMap { case (range, port) =>
port.clients map { client => client.v1copy(
sourceId = client.sourceId.shift(range.start)
)}
}
)
},
managerFn = { seq =>
val fifoIdFactory = TLXbar.relabeler()
seq(0).v1copy(
responseFields = BundleField.union(seq.flatMap(_.responseFields)),
requestKeys = seq.flatMap(_.requestKeys).distinct,
minLatency = seq.map(_.minLatency).min,
endSinkId = TLXbar.mapOutputIds(seq).map(_.end).max,
managers = seq.flatMap { port =>
require (port.beatBytes == seq(0).beatBytes,
s"TLNoC (data widths don't match: ${port.managers.map(_.name)} has ${port.beatBytes}B vs ${seq(0).managers.map(_.name)} has ${seq(0).beatBytes}B")
// TileLink NoC does not preserve FIFO-ness, masters to this NoC should instantiate FIFOFixers
port.managers map { manager => manager.v1copy(fifoId = None) }
}
)
}
)
}
abstract class TLNoCModuleImp(outer: LazyModule) extends LazyModuleImp(outer) {
val edgesIn: Seq[TLEdge]
val edgesOut: Seq[TLEdge]
val nodeMapping: DiplomaticNetworkNodeMapping
val nocName: String
lazy val inNames = nodeMapping.genUniqueName(edgesIn.map(_.master.masters.map(_.name)))
lazy val outNames = nodeMapping.genUniqueName(edgesOut.map(_.slave.slaves.map(_.name)))
lazy val edgeInNodes = nodeMapping.getNodesIn(inNames)
lazy val edgeOutNodes = nodeMapping.getNodesOut(outNames)
def printNodeMappings() {
println(s"Constellation: TLNoC $nocName inwards mapping:")
for ((n, i) <- inNames zip edgeInNodes) {
val node = i.map(_.toString).getOrElse("X")
println(s" $node <- $n")
}
println(s"Constellation: TLNoC $nocName outwards mapping:")
for ((n, i) <- outNames zip edgeOutNodes) {
val node = i.map(_.toString).getOrElse("X")
println(s" $node <- $n")
}
}
}
trait TLNoCParams
// Instantiates a private TLNoC. Replaces the TLXbar
// BEGIN: TLNoCParams
case class SimpleTLNoCParams(
nodeMappings: DiplomaticNetworkNodeMapping,
nocParams: NoCParams = NoCParams(),
) extends TLNoCParams
class TLNoC(params: SimpleTLNoCParams, name: String = "test", inlineNoC: Boolean = false)(implicit p: Parameters) extends TLNoCLike {
// END: TLNoCParams
override def shouldBeInlined = inlineNoC
lazy val module = new TLNoCModuleImp(this) {
val (io_in, edgesIn) = node.in.unzip
val (io_out, edgesOut) = node.out.unzip
val nodeMapping = params.nodeMappings
val nocName = name
printNodeMappings()
val protocolParams = TileLinkABCDEProtocolParams(
edgesIn = edgesIn,
edgesOut = edgesOut,
edgeInNodes = edgeInNodes.flatten,
edgeOutNodes = edgeOutNodes.flatten
)
val noc = Module(new ProtocolNoC(ProtocolNoCParams(
params.nocParams.copy(hasCtrl = false, nocName=name, inlineNoC = inlineNoC),
Seq(protocolParams),
inlineNoC = inlineNoC
)))
noc.io.protocol(0) match {
case protocol: TileLinkInterconnectInterface => {
(protocol.in zip io_in).foreach { case (l,r) => l <> r }
(io_out zip protocol.out).foreach { case (l,r) => l <> r }
}
}
}
}
case class SplitACDxBETLNoCParams(
nodeMappings: DiplomaticNetworkNodeMapping,
acdNoCParams: NoCParams = NoCParams(),
beNoCParams: NoCParams = NoCParams(),
beDivision: Int = 2
) extends TLNoCParams
class TLSplitACDxBENoC(params: SplitACDxBETLNoCParams, name: String = "test", inlineNoC: Boolean = false)(implicit p: Parameters) extends TLNoCLike {
override def shouldBeInlined = inlineNoC
lazy val module = new TLNoCModuleImp(this) {
val (io_in, edgesIn) = node.in.unzip
val (io_out, edgesOut) = node.out.unzip
val nodeMapping = params.nodeMappings
val nocName = name
printNodeMappings()
val acdProtocolParams = TileLinkACDProtocolParams(
edgesIn = edgesIn,
edgesOut = edgesOut,
edgeInNodes = edgeInNodes.flatten,
edgeOutNodes = edgeOutNodes.flatten
)
val beProtocolParams = TileLinkBEProtocolParams(
edgesIn = edgesIn,
edgesOut = edgesOut,
edgeInNodes = edgeInNodes.flatten,
edgeOutNodes = edgeOutNodes.flatten
)
val acd_noc = Module(new ProtocolNoC(ProtocolNoCParams(
params.acdNoCParams.copy(hasCtrl = false, nocName=s"${name}_acd", inlineNoC = inlineNoC),
Seq(acdProtocolParams),
inlineNoC = inlineNoC
)))
val be_noc = Module(new ProtocolNoC(ProtocolNoCParams(
params.beNoCParams.copy(hasCtrl = false, nocName=s"${name}_be", inlineNoC = inlineNoC),
Seq(beProtocolParams),
widthDivision = params.beDivision,
inlineNoC = inlineNoC
)))
acd_noc.io.protocol(0) match { case protocol: TileLinkInterconnectInterface => {
(protocol.in zip io_in).foreach { case (l,r) =>
l := DontCare
l.a <> r.a
l.c <> r.c
l.d <> r.d
}
(io_out zip protocol.out).foreach { case (l,r) =>
r := DontCare
l.a <> r.a
l.c <> r.c
l.d <> r.d
}
}}
be_noc.io.protocol(0) match { case protocol: TileLinkInterconnectInterface => {
(protocol.in zip io_in).foreach { case (l,r) =>
l := DontCare
l.b <> r.b
l.e <> r.e
}
(io_out zip protocol.out).foreach { case (l,r) =>
r := DontCare
l.b <> r.b
l.e <> r.e
}
}}
}
}
case class GlobalTLNoCParams(
nodeMappings: DiplomaticNetworkNodeMapping
) extends TLNoCParams
// Maps this interconnect onto a global NoC
class TLGlobalNoC(params: GlobalTLNoCParams, name: String = "test")(implicit p: Parameters) extends TLNoCLike {
lazy val module = new TLNoCModuleImp(this) with CanAttachToGlobalNoC {
val (io_in, edgesIn) = node.in.unzip
val (io_out, edgesOut) = node.out.unzip
val nodeMapping = params.nodeMappings
val nocName = name
val protocolParams = TileLinkABCDEProtocolParams(
edgesIn = edgesIn,
edgesOut = edgesOut,
edgeInNodes = edgeInNodes.flatten,
edgeOutNodes = edgeOutNodes.flatten
)
printNodeMappings()
val io_global = IO(Flipped(protocolParams.genIO()))
io_global match {
case protocol: TileLinkInterconnectInterface => {
(protocol.in zip io_in).foreach { case (l,r) => l <> r }
(io_out zip protocol.out).foreach { case (l,r) => l <> r }
}
}
}
}
| module TLMasterToNoC_1( // @[Tilelink.scala:37:7]
input clock, // @[Tilelink.scala:37:7]
input reset, // @[Tilelink.scala:37:7]
output io_tilelink_a_ready, // @[Tilelink.scala:44:14]
input io_tilelink_a_valid, // @[Tilelink.scala:44:14]
input [2:0] io_tilelink_a_bits_opcode, // @[Tilelink.scala:44:14]
input [2:0] io_tilelink_a_bits_param, // @[Tilelink.scala:44:14]
input [3:0] io_tilelink_a_bits_size, // @[Tilelink.scala:44:14]
input [5:0] io_tilelink_a_bits_source, // @[Tilelink.scala:44:14]
input [31:0] io_tilelink_a_bits_address, // @[Tilelink.scala:44:14]
input [7:0] io_tilelink_a_bits_mask, // @[Tilelink.scala:44:14]
input [63:0] io_tilelink_a_bits_data, // @[Tilelink.scala:44:14]
input io_tilelink_a_bits_corrupt, // @[Tilelink.scala:44:14]
input io_tilelink_b_ready, // @[Tilelink.scala:44:14]
output io_tilelink_b_valid, // @[Tilelink.scala:44:14]
output [2:0] io_tilelink_b_bits_opcode, // @[Tilelink.scala:44:14]
output [1:0] io_tilelink_b_bits_param, // @[Tilelink.scala:44:14]
output [3:0] io_tilelink_b_bits_size, // @[Tilelink.scala:44:14]
output [5:0] io_tilelink_b_bits_source, // @[Tilelink.scala:44:14]
output [31:0] io_tilelink_b_bits_address, // @[Tilelink.scala:44:14]
output [7:0] io_tilelink_b_bits_mask, // @[Tilelink.scala:44:14]
output [63:0] io_tilelink_b_bits_data, // @[Tilelink.scala:44:14]
output io_tilelink_b_bits_corrupt, // @[Tilelink.scala:44:14]
output io_tilelink_c_ready, // @[Tilelink.scala:44:14]
input io_tilelink_c_valid, // @[Tilelink.scala:44:14]
input [2:0] io_tilelink_c_bits_opcode, // @[Tilelink.scala:44:14]
input [2:0] io_tilelink_c_bits_param, // @[Tilelink.scala:44:14]
input [3:0] io_tilelink_c_bits_size, // @[Tilelink.scala:44:14]
input [5:0] io_tilelink_c_bits_source, // @[Tilelink.scala:44:14]
input [31:0] io_tilelink_c_bits_address, // @[Tilelink.scala:44:14]
input [63:0] io_tilelink_c_bits_data, // @[Tilelink.scala:44:14]
input io_tilelink_c_bits_corrupt, // @[Tilelink.scala:44:14]
input io_tilelink_d_ready, // @[Tilelink.scala:44:14]
output io_tilelink_d_valid, // @[Tilelink.scala:44:14]
output [2:0] io_tilelink_d_bits_opcode, // @[Tilelink.scala:44:14]
output [1:0] io_tilelink_d_bits_param, // @[Tilelink.scala:44:14]
output [3:0] io_tilelink_d_bits_size, // @[Tilelink.scala:44:14]
output [5:0] io_tilelink_d_bits_source, // @[Tilelink.scala:44:14]
output [4:0] io_tilelink_d_bits_sink, // @[Tilelink.scala:44:14]
output io_tilelink_d_bits_denied, // @[Tilelink.scala:44:14]
output [63:0] io_tilelink_d_bits_data, // @[Tilelink.scala:44:14]
output io_tilelink_d_bits_corrupt, // @[Tilelink.scala:44:14]
output io_tilelink_e_ready, // @[Tilelink.scala:44:14]
input io_tilelink_e_valid, // @[Tilelink.scala:44:14]
input [4:0] io_tilelink_e_bits_sink, // @[Tilelink.scala:44:14]
input io_flits_a_ready, // @[Tilelink.scala:44:14]
output io_flits_a_valid, // @[Tilelink.scala:44:14]
output io_flits_a_bits_head, // @[Tilelink.scala:44:14]
output io_flits_a_bits_tail, // @[Tilelink.scala:44:14]
output [72:0] io_flits_a_bits_payload, // @[Tilelink.scala:44:14]
output [4:0] io_flits_a_bits_egress_id, // @[Tilelink.scala:44:14]
output io_flits_b_ready, // @[Tilelink.scala:44:14]
input io_flits_b_valid, // @[Tilelink.scala:44:14]
input io_flits_b_bits_head, // @[Tilelink.scala:44:14]
input io_flits_b_bits_tail, // @[Tilelink.scala:44:14]
input [72:0] io_flits_b_bits_payload, // @[Tilelink.scala:44:14]
input io_flits_c_ready, // @[Tilelink.scala:44:14]
output io_flits_c_valid, // @[Tilelink.scala:44:14]
output io_flits_c_bits_head, // @[Tilelink.scala:44:14]
output io_flits_c_bits_tail, // @[Tilelink.scala:44:14]
output [72:0] io_flits_c_bits_payload, // @[Tilelink.scala:44:14]
output [4:0] io_flits_c_bits_egress_id, // @[Tilelink.scala:44:14]
output io_flits_d_ready, // @[Tilelink.scala:44:14]
input io_flits_d_valid, // @[Tilelink.scala:44:14]
input io_flits_d_bits_head, // @[Tilelink.scala:44:14]
input io_flits_d_bits_tail, // @[Tilelink.scala:44:14]
input [72:0] io_flits_d_bits_payload, // @[Tilelink.scala:44:14]
input io_flits_e_ready, // @[Tilelink.scala:44:14]
output io_flits_e_valid, // @[Tilelink.scala:44:14]
output io_flits_e_bits_head, // @[Tilelink.scala:44:14]
output [72:0] io_flits_e_bits_payload, // @[Tilelink.scala:44:14]
output [5:0] io_flits_e_bits_egress_id // @[Tilelink.scala:44:14]
);
wire [4:0] _e_io_flit_bits_payload; // @[Tilelink.scala:58:17]
wire [64:0] _c_io_flit_bits_payload; // @[Tilelink.scala:56:17]
TLAToNoC_1 a ( // @[Tilelink.scala:54:17]
.clock (clock),
.reset (reset),
.io_protocol_ready (io_tilelink_a_ready),
.io_protocol_valid (io_tilelink_a_valid),
.io_protocol_bits_opcode (io_tilelink_a_bits_opcode),
.io_protocol_bits_param (io_tilelink_a_bits_param),
.io_protocol_bits_size (io_tilelink_a_bits_size),
.io_protocol_bits_source (io_tilelink_a_bits_source),
.io_protocol_bits_address (io_tilelink_a_bits_address),
.io_protocol_bits_mask (io_tilelink_a_bits_mask),
.io_protocol_bits_data (io_tilelink_a_bits_data),
.io_protocol_bits_corrupt (io_tilelink_a_bits_corrupt),
.io_flit_ready (io_flits_a_ready),
.io_flit_valid (io_flits_a_valid),
.io_flit_bits_head (io_flits_a_bits_head),
.io_flit_bits_tail (io_flits_a_bits_tail),
.io_flit_bits_payload (io_flits_a_bits_payload),
.io_flit_bits_egress_id (io_flits_a_bits_egress_id)
); // @[Tilelink.scala:54:17]
TLBFromNoC_1 b ( // @[Tilelink.scala:55:17]
.clock (clock),
.reset (reset),
.io_protocol_ready (io_tilelink_b_ready),
.io_protocol_valid (io_tilelink_b_valid),
.io_protocol_bits_opcode (io_tilelink_b_bits_opcode),
.io_protocol_bits_param (io_tilelink_b_bits_param),
.io_protocol_bits_size (io_tilelink_b_bits_size),
.io_protocol_bits_source (io_tilelink_b_bits_source),
.io_protocol_bits_address (io_tilelink_b_bits_address),
.io_protocol_bits_mask (io_tilelink_b_bits_mask),
.io_protocol_bits_data (io_tilelink_b_bits_data),
.io_protocol_bits_corrupt (io_tilelink_b_bits_corrupt),
.io_flit_ready (io_flits_b_ready),
.io_flit_valid (io_flits_b_valid),
.io_flit_bits_head (io_flits_b_bits_head),
.io_flit_bits_tail (io_flits_b_bits_tail),
.io_flit_bits_payload (io_flits_b_bits_payload)
); // @[Tilelink.scala:55:17]
TLCToNoC_1 c ( // @[Tilelink.scala:56:17]
.clock (clock),
.reset (reset),
.io_protocol_ready (io_tilelink_c_ready),
.io_protocol_valid (io_tilelink_c_valid),
.io_protocol_bits_opcode (io_tilelink_c_bits_opcode),
.io_protocol_bits_param (io_tilelink_c_bits_param),
.io_protocol_bits_size (io_tilelink_c_bits_size),
.io_protocol_bits_source (io_tilelink_c_bits_source),
.io_protocol_bits_address (io_tilelink_c_bits_address),
.io_protocol_bits_data (io_tilelink_c_bits_data),
.io_protocol_bits_corrupt (io_tilelink_c_bits_corrupt),
.io_flit_ready (io_flits_c_ready),
.io_flit_valid (io_flits_c_valid),
.io_flit_bits_head (io_flits_c_bits_head),
.io_flit_bits_tail (io_flits_c_bits_tail),
.io_flit_bits_payload (_c_io_flit_bits_payload),
.io_flit_bits_egress_id (io_flits_c_bits_egress_id)
); // @[Tilelink.scala:56:17]
TLDFromNoC_1 d ( // @[Tilelink.scala:57:17]
.clock (clock),
.reset (reset),
.io_protocol_ready (io_tilelink_d_ready),
.io_protocol_valid (io_tilelink_d_valid),
.io_protocol_bits_opcode (io_tilelink_d_bits_opcode),
.io_protocol_bits_param (io_tilelink_d_bits_param),
.io_protocol_bits_size (io_tilelink_d_bits_size),
.io_protocol_bits_source (io_tilelink_d_bits_source),
.io_protocol_bits_sink (io_tilelink_d_bits_sink),
.io_protocol_bits_denied (io_tilelink_d_bits_denied),
.io_protocol_bits_data (io_tilelink_d_bits_data),
.io_protocol_bits_corrupt (io_tilelink_d_bits_corrupt),
.io_flit_ready (io_flits_d_ready),
.io_flit_valid (io_flits_d_valid),
.io_flit_bits_head (io_flits_d_bits_head),
.io_flit_bits_tail (io_flits_d_bits_tail),
.io_flit_bits_payload (io_flits_d_bits_payload[64:0]) // @[Tilelink.scala:68:14]
); // @[Tilelink.scala:57:17]
TLEToNoC e ( // @[Tilelink.scala:58:17]
.clock (clock),
.reset (reset),
.io_protocol_ready (io_tilelink_e_ready),
.io_protocol_valid (io_tilelink_e_valid),
.io_protocol_bits_sink (io_tilelink_e_bits_sink),
.io_flit_ready (io_flits_e_ready),
.io_flit_valid (io_flits_e_valid),
.io_flit_bits_head (io_flits_e_bits_head),
.io_flit_bits_payload (_e_io_flit_bits_payload),
.io_flit_bits_egress_id (io_flits_e_bits_egress_id)
); // @[Tilelink.scala:58:17]
assign io_flits_c_bits_payload = {8'h0, _c_io_flit_bits_payload}; // @[Tilelink.scala:37:7, :56:17, :67:14]
assign io_flits_e_bits_payload = {68'h0, _e_io_flit_bits_payload}; // @[Tilelink.scala:37:7, :58:17, :69:14]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File Monitor.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceLine
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import freechips.rocketchip.diplomacy.EnableMonitors
import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode}
import freechips.rocketchip.util.PlusArg
case class TLMonitorArgs(edge: TLEdge)
abstract class TLMonitorBase(args: TLMonitorArgs) extends Module
{
val io = IO(new Bundle {
val in = Input(new TLBundle(args.edge.bundle))
})
def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit
legalize(io.in, args.edge, reset)
}
object TLMonitor {
def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = {
if (enable) {
EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) }
} else { node }
}
}
class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args)
{
require (args.edge.params(TLMonitorStrictMode) || (! args.edge.params(TestplanTestType).formal))
val cover_prop_class = PropertyClass.Default
//Like assert but can flip to being an assumption for formal verification
def monAssert(cond: Bool, message: String): Unit =
if (monitorDir == MonitorDirection.Monitor) {
assert(cond, message)
} else {
Property(monitorDir, cond, message, PropertyClass.Default)
}
def assume(cond: Bool, message: String): Unit =
if (monitorDir == MonitorDirection.Monitor) {
assert(cond, message)
} else {
Property(monitorDir.flip, cond, message, PropertyClass.Default)
}
def extra = {
args.edge.sourceInfo match {
case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)"
case _ => ""
}
}
def visible(address: UInt, source: UInt, edge: TLEdge) =
edge.client.clients.map { c =>
!c.sourceId.contains(source) ||
c.visibility.map(_.contains(address)).reduce(_ || _)
}.reduce(_ && _)
def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = {
//switch this flag to turn on diplomacy in error messages
def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n"
monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra)
// Reuse these subexpressions to save some firrtl lines
val source_ok = edge.client.contains(bundle.source)
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val mask = edge.full_mask(bundle)
monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility")
//The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B
//TODO: check for acquireT?
when (bundle.opcode === TLMessages.AcquireBlock) {
monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra)
monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra)
monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra)
monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra)
}
when (bundle.opcode === TLMessages.AcquirePerm) {
monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra)
monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra)
monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra)
monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra)
monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra)
}
when (bundle.opcode === TLMessages.Get) {
monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra)
monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra)
monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra)
}
when (bundle.opcode === TLMessages.PutFullData) {
monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra)
monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.PutPartialData) {
monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra)
monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.ArithmeticData) {
monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra)
monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.LogicalData) {
monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra)
monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.Hint) {
monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra)
monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra)
}
}
def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = {
monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra)
monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility")
// Reuse these subexpressions to save some firrtl lines
val address_ok = edge.manager.containsSafe(edge.address(bundle))
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val mask = edge.full_mask(bundle)
val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source
when (bundle.opcode === TLMessages.Probe) {
assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra)
assume (address_ok, "'B' channel Probe carries unmanaged address" + extra)
assume (legal_source, "'B' channel Probe carries source that is not first source" + extra)
assume (is_aligned, "'B' channel Probe address not aligned to size" + extra)
assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra)
assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra)
assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra)
}
when (bundle.opcode === TLMessages.Get) {
monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra)
monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra)
}
when (bundle.opcode === TLMessages.PutFullData) {
monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra)
monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.PutPartialData) {
monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra)
monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.ArithmeticData) {
monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra)
monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra)
monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.LogicalData) {
monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra)
monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra)
monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.Hint) {
monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra)
monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra)
monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra)
}
}
def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = {
monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra)
val source_ok = edge.client.contains(bundle.source)
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val address_ok = edge.manager.containsSafe(edge.address(bundle))
monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility")
when (bundle.opcode === TLMessages.ProbeAck) {
monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra)
monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra)
}
when (bundle.opcode === TLMessages.ProbeAckData) {
monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra)
}
when (bundle.opcode === TLMessages.Release) {
monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra)
monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra)
monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra)
}
when (bundle.opcode === TLMessages.ReleaseData) {
monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra)
monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra)
}
when (bundle.opcode === TLMessages.AccessAck) {
monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra)
monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra)
}
when (bundle.opcode === TLMessages.AccessAckData) {
monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra)
}
when (bundle.opcode === TLMessages.HintAck) {
monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra)
monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra)
}
}
def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = {
assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra)
val source_ok = edge.client.contains(bundle.source)
val sink_ok = bundle.sink < edge.manager.endSinkId.U
val deny_put_ok = edge.manager.mayDenyPut.B
val deny_get_ok = edge.manager.mayDenyGet.B
when (bundle.opcode === TLMessages.ReleaseAck) {
assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra)
assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra)
assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra)
}
when (bundle.opcode === TLMessages.Grant) {
assume (source_ok, "'D' channel Grant carries invalid source ID" + extra)
assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra)
assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra)
assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra)
assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel Grant is denied" + extra)
}
when (bundle.opcode === TLMessages.GrantData) {
assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra)
assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra)
assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra)
assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra)
assume (!bundle.denied || bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra)
assume (deny_get_ok || !bundle.denied, "'D' channel GrantData is denied" + extra)
}
when (bundle.opcode === TLMessages.AccessAck) {
assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel AccessAck is denied" + extra)
}
when (bundle.opcode === TLMessages.AccessAckData) {
assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra)
assume (!bundle.denied || bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra)
assume (deny_get_ok || !bundle.denied, "'D' channel AccessAckData is denied" + extra)
}
when (bundle.opcode === TLMessages.HintAck) {
assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel HintAck is denied" + extra)
}
}
def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = {
val sink_ok = bundle.sink < edge.manager.endSinkId.U
monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra)
}
def legalizeFormat(bundle: TLBundle, edge: TLEdge) = {
when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) }
when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) }
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) }
when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) }
when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) }
} else {
monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra)
monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra)
monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra)
}
}
def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = {
val a_first = edge.first(a.bits, a.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (a.valid && !a_first) {
monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra)
monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra)
monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra)
monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra)
monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra)
}
when (a.fire && a_first) {
opcode := a.bits.opcode
param := a.bits.param
size := a.bits.size
source := a.bits.source
address := a.bits.address
}
}
def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = {
val b_first = edge.first(b.bits, b.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (b.valid && !b_first) {
monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra)
monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra)
monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra)
monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra)
monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra)
}
when (b.fire && b_first) {
opcode := b.bits.opcode
param := b.bits.param
size := b.bits.size
source := b.bits.source
address := b.bits.address
}
}
def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = {
// Symbolic variable
val sym_source = Wire(UInt(edge.client.endSourceId.W))
// TODO: Connect sym_source to a fixed value for simulation and to a
// free wire in formal
sym_source := 0.U
// Type casting Int to UInt
val maxSourceId = Wire(UInt(edge.client.endSourceId.W))
maxSourceId := edge.client.endSourceId.U
// Delayed verison of sym_source
val sym_source_d = Reg(UInt(edge.client.endSourceId.W))
sym_source_d := sym_source
// These will be constraints for FV setup
Property(
MonitorDirection.Monitor,
(sym_source === sym_source_d),
"sym_source should remain stable",
PropertyClass.Default)
Property(
MonitorDirection.Monitor,
(sym_source <= maxSourceId),
"sym_source should take legal value",
PropertyClass.Default)
val my_resp_pend = RegInit(false.B)
val my_opcode = Reg(UInt())
val my_size = Reg(UInt())
val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire)
val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire)
val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source)
val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source)
val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat)
val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend)
when (my_set_resp_pend) {
my_resp_pend := true.B
} .elsewhen (my_clr_resp_pend) {
my_resp_pend := false.B
}
when (my_a_first_beat) {
my_opcode := bundle.a.bits.opcode
my_size := bundle.a.bits.size
}
val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size)
val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode)
val my_resp_opcode_legal = Wire(Bool())
when ((my_resp_opcode === TLMessages.Get) || (my_resp_opcode === TLMessages.ArithmeticData) ||
(my_resp_opcode === TLMessages.LogicalData)) {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData)
} .elsewhen ((my_resp_opcode === TLMessages.PutFullData) || (my_resp_opcode === TLMessages.PutPartialData)) {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck)
} .otherwise {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck)
}
monAssert (IfThen(my_resp_pend, !my_a_first_beat),
"Request message should not be sent with a source ID, for which a response message" +
"is already pending (not received until current cycle) for a prior request message" +
"with the same source ID" + extra)
assume (IfThen(my_clr_resp_pend, (my_set_resp_pend || my_resp_pend)),
"Response message should be accepted with a source ID only if a request message with the" +
"same source ID has been accepted or is being accepted in the current cycle" + extra)
assume (IfThen(my_d_first_beat, (my_a_first_beat || my_resp_pend)),
"Response message should be sent with a source ID only if a request message with the" +
"same source ID has been accepted or is being sent in the current cycle" + extra)
assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)),
"If d_valid is 1, then d_size should be same as a_size of the corresponding request" +
"message" + extra)
assume (IfThen(my_d_first_beat, my_resp_opcode_legal),
"If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" +
"request message" + extra)
}
def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = {
val c_first = edge.first(c.bits, c.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (c.valid && !c_first) {
monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra)
monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra)
monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra)
monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra)
monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra)
}
when (c.fire && c_first) {
opcode := c.bits.opcode
param := c.bits.param
size := c.bits.size
source := c.bits.source
address := c.bits.address
}
}
def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = {
val d_first = edge.first(d.bits, d.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val sink = Reg(UInt())
val denied = Reg(Bool())
when (d.valid && !d_first) {
assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra)
assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra)
assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra)
assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra)
assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra)
assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra)
}
when (d.fire && d_first) {
opcode := d.bits.opcode
param := d.bits.param
size := d.bits.size
source := d.bits.source
sink := d.bits.sink
denied := d.bits.denied
}
}
def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = {
legalizeMultibeatA(bundle.a, edge)
legalizeMultibeatD(bundle.d, edge)
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
legalizeMultibeatB(bundle.b, edge)
legalizeMultibeatC(bundle.c, edge)
}
}
//This is left in for almond which doesn't adhere to the tilelink protocol
@deprecated("Use legalizeADSource instead if possible","")
def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = {
val inflight = RegInit(0.U(edge.client.endSourceId.W))
val a_first = edge.first(bundle.a.bits, bundle.a.fire)
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
val a_set = WireInit(0.U(edge.client.endSourceId.W))
when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) {
a_set := UIntToOH(bundle.a.bits.source)
assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra)
}
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
assume((a_set | inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra)
}
if (edge.manager.minLatency > 0) {
assume(a_set =/= d_clr || !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra)
}
inflight := (inflight | a_set) & ~d_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
assert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = {
val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset)
val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything
val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size)
val log_a_size_bus_size = log2Ceil(a_size_bus_size)
def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits
val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error
inflight.suggestName("inflight")
val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
inflight_opcodes.suggestName("inflight_opcodes")
val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
inflight_sizes.suggestName("inflight_sizes")
val a_first = edge.first(bundle.a.bits, bundle.a.fire)
a_first.suggestName("a_first")
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
d_first.suggestName("d_first")
val a_set = WireInit(0.U(edge.client.endSourceId.W))
val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
a_set.suggestName("a_set")
a_set_wo_ready.suggestName("a_set_wo_ready")
val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
a_opcodes_set.suggestName("a_opcodes_set")
val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
a_sizes_set.suggestName("a_sizes_set")
val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W))
a_opcode_lookup.suggestName("a_opcode_lookup")
a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U
val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W))
a_size_lookup.suggestName("a_size_lookup")
a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U
val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant))
val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant))
val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W))
a_opcodes_set_interm.suggestName("a_opcodes_set_interm")
val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W))
a_sizes_set_interm.suggestName("a_sizes_set_interm")
when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) {
a_set_wo_ready := UIntToOH(bundle.a.bits.source)
}
when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) {
a_set := UIntToOH(bundle.a.bits.source)
a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) | 1.U
a_sizes_set_interm := (bundle.a.bits.size << 1.U) | 1.U
a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U)
a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U)
monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra)
}
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
d_clr.suggestName("d_clr")
d_clr_wo_ready.suggestName("d_clr_wo_ready")
val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
d_opcodes_clr.suggestName("d_opcodes_clr")
val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
d_sizes_clr.suggestName("d_sizes_clr")
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr_wo_ready := UIntToOH(bundle.d.bits.source)
}
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U)
d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U)
}
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source)
assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra)
when (same_cycle_resp) {
assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) ||
(bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra)
assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra)
} .otherwise {
assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) ||
(bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra)
assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra)
}
}
when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) {
assume((!bundle.d.ready) || bundle.a.ready, "ready check")
}
if (edge.manager.minLatency > 0) {
assume(a_set_wo_ready =/= d_clr_wo_ready || !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra)
}
inflight := (inflight | a_set) & ~d_clr
inflight_opcodes := (inflight_opcodes | a_opcodes_set) & ~d_opcodes_clr
inflight_sizes := (inflight_sizes | a_sizes_set) & ~d_sizes_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = {
val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset)
val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything
val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size)
val log_c_size_bus_size = log2Ceil(c_size_bus_size)
def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits
val inflight = RegInit(0.U((2 max edge.client.endSourceId).W))
val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
inflight.suggestName("inflight")
inflight_opcodes.suggestName("inflight_opcodes")
inflight_sizes.suggestName("inflight_sizes")
val c_first = edge.first(bundle.c.bits, bundle.c.fire)
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
c_first.suggestName("c_first")
d_first.suggestName("d_first")
val c_set = WireInit(0.U(edge.client.endSourceId.W))
val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
c_set.suggestName("c_set")
c_set_wo_ready.suggestName("c_set_wo_ready")
c_opcodes_set.suggestName("c_opcodes_set")
c_sizes_set.suggestName("c_sizes_set")
val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W))
val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W))
c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U
c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U
c_opcode_lookup.suggestName("c_opcode_lookup")
c_size_lookup.suggestName("c_size_lookup")
val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W))
val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W))
c_opcodes_set_interm.suggestName("c_opcodes_set_interm")
c_sizes_set_interm.suggestName("c_sizes_set_interm")
when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) {
c_set_wo_ready := UIntToOH(bundle.c.bits.source)
}
when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) {
c_set := UIntToOH(bundle.c.bits.source)
c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) | 1.U
c_sizes_set_interm := (bundle.c.bits.size << 1.U) | 1.U
c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U)
c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U)
monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra)
}
val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck || bundle.c.bits.opcode === TLMessages.ProbeAckData
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
d_clr.suggestName("d_clr")
d_clr_wo_ready.suggestName("d_clr_wo_ready")
d_opcodes_clr.suggestName("d_opcodes_clr")
d_sizes_clr.suggestName("d_sizes_clr")
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
d_clr_wo_ready := UIntToOH(bundle.d.bits.source)
}
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U)
d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U)
}
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source)
assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra)
when (same_cycle_resp) {
assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra)
} .otherwise {
assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra)
}
}
when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) {
assume((!bundle.d.ready) || bundle.c.ready, "ready check")
}
if (edge.manager.minLatency > 0) {
when (c_set_wo_ready.orR) {
assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra)
}
}
inflight := (inflight | c_set) & ~d_clr
inflight_opcodes := (inflight_opcodes | c_opcodes_set) & ~d_opcodes_clr
inflight_sizes := (inflight_sizes | c_sizes_set) & ~d_sizes_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.c.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = {
val inflight = RegInit(0.U(edge.manager.endSinkId.W))
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
val e_first = true.B
val d_set = WireInit(0.U(edge.manager.endSinkId.W))
when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) {
d_set := UIntToOH(bundle.d.bits.sink)
assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra)
}
val e_clr = WireInit(0.U(edge.manager.endSinkId.W))
when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) {
e_clr := UIntToOH(bundle.e.bits.sink)
monAssert((d_set | inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra)
}
// edge.client.minLatency applies to BC, not DE
inflight := (inflight | d_set) & ~e_clr
}
def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = {
val sourceBits = log2Ceil(edge.client.endSourceId)
val tooBig = 14 // >16kB worth of flight information gets to be too much
if (sourceBits > tooBig) {
println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked")
} else {
if (args.edge.params(TestplanTestType).simulation) {
if (args.edge.params(TLMonitorStrictMode)) {
legalizeADSource(bundle, edge)
legalizeCDSource(bundle, edge)
} else {
legalizeADSourceOld(bundle, edge)
}
}
if (args.edge.params(TestplanTestType).formal) {
legalizeADSourceFormal(bundle, edge)
}
}
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
// legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize...
val sinkBits = log2Ceil(edge.manager.endSinkId)
if (sinkBits > tooBig) {
println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked")
} else {
legalizeDESink(bundle, edge)
}
}
}
def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = {
legalizeFormat (bundle, edge)
legalizeMultibeat (bundle, edge)
legalizeUnique (bundle, edge)
}
}
File PlusArg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.experimental._
import chisel3.util.HasBlackBoxResource
@deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05")
case class PlusArgInfo(default: BigInt, docstring: String)
/** Case class for PlusArg information
*
* @tparam A scala type of the PlusArg value
* @param default optional default value
* @param docstring text to include in the help
* @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT)
*/
private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String)
/** Typeclass for converting a type to a doctype string
* @tparam A some type
*/
trait Doctypeable[A] {
/** Return the doctype string for some option */
def toDoctype(a: Option[A]): String
}
/** Object containing implementations of the Doctypeable typeclass */
object Doctypes {
/** Converts an Int => "INT" */
implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" }
/** Converts a BigInt => "INT" */
implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" }
/** Converts a String => "STRING" */
implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" }
}
class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map(
"FORMAT" -> StringParam(format),
"DEFAULT" -> IntParam(default),
"WIDTH" -> IntParam(width)
)) with HasBlackBoxResource {
val io = IO(new Bundle {
val out = Output(UInt(width.W))
})
addResource("/vsrc/plusarg_reader.v")
}
/* This wrapper class has no outputs, making it clear it is a simulation-only construct */
class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module {
val io = IO(new Bundle {
val count = Input(UInt(width.W))
})
val max = Module(new plusarg_reader(format, default, docstring, width)).io.out
when (max > 0.U) {
assert (io.count < max, s"Timeout exceeded: $docstring")
}
}
import Doctypes._
object PlusArg
{
/** PlusArg("foo") will return 42.U if the simulation is run with +foo=42
* Do not use this as an initial register value. The value is set in an
* initial block and thus accessing it from another initial is racey.
* Add a docstring to document the arg, which can be dumped in an elaboration
* pass.
*/
def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = {
PlusArgArtefacts.append(name, Some(default), docstring)
Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out
}
/** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert
* to kill the simulation when count exceeds the specified integer argument.
* Default 0 will never assert.
*/
def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = {
PlusArgArtefacts.append(name, Some(default), docstring)
Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count
}
}
object PlusArgArtefacts {
private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty
/* Add a new PlusArg */
@deprecated(
"Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08",
"Rocket Chip 2020.05"
)
def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring)
/** Add a new PlusArg
*
* @tparam A scala type of the PlusArg value
* @param name name for the PlusArg
* @param default optional default value
* @param docstring text to include in the help
*/
def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit =
artefacts = artefacts ++
Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default)))
/* From plus args, generate help text */
private def serializeHelp_cHeader(tab: String = ""): String = artefacts
.map{ case(arg, info) =>
s"""|$tab+$arg=${info.doctype}\\n\\
|$tab${" "*20}${info.docstring}\\n\\
|""".stripMargin ++ info.default.map{ case default =>
s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("")
}.toSeq.mkString("\\n\\\n") ++ "\""
/* From plus args, generate a char array of their names */
private def serializeArray_cHeader(tab: String = ""): String = {
val prettyTab = tab + " " * 44 // Length of 'static const ...'
s"${tab}static const char * verilog_plusargs [] = {\\\n" ++
artefacts
.map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" }
.mkString("")++
s"${prettyTab}0};"
}
/* Generate C code to be included in emulator.cc that helps with
* argument parsing based on available Verilog PlusArgs */
def serialize_cHeader(): String =
s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\
|${serializeHelp_cHeader(" "*7)}
|${serializeArray_cHeader()}
|""".stripMargin
}
File package.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip
import chisel3._
import chisel3.util._
import scala.math.min
import scala.collection.{immutable, mutable}
package object util {
implicit class UnzippableOption[S, T](val x: Option[(S, T)]) {
def unzip = (x.map(_._1), x.map(_._2))
}
implicit class UIntIsOneOf(private val x: UInt) extends AnyVal {
def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR
def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq)
}
implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal {
/** Like Vec.apply(idx), but tolerates indices of mismatched width */
def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0))
}
implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal {
def apply(idx: UInt): T = {
if (x.size <= 1) {
x.head
} else if (!isPow2(x.size)) {
// For non-power-of-2 seqs, reflect elements to simplify decoder
(x ++ x.takeRight(x.size & -x.size)).toSeq(idx)
} else {
// Ignore MSBs of idx
val truncIdx =
if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx
else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0)
x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) }
}
}
def extract(idx: UInt): T = VecInit(x).extract(idx)
def asUInt: UInt = Cat(x.map(_.asUInt).reverse)
def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n)
def rotate(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n)
def rotateRight(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
}
// allow bitwise ops on Seq[Bool] just like UInt
implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal {
def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b }
def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b }
def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b }
def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x
def >> (n: Int): Seq[Bool] = x drop n
def unary_~ : Seq[Bool] = x.map(!_)
def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_)
def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_)
def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_)
private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B)
}
implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal {
def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable))
def getElements: Seq[Element] = x match {
case e: Element => Seq(e)
case a: Aggregate => a.getElements.flatMap(_.getElements)
}
}
/** Any Data subtype that has a Bool member named valid. */
type DataCanBeValid = Data { val valid: Bool }
implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal {
def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable)
}
implicit class StringToAugmentedString(private val x: String) extends AnyVal {
/** converts from camel case to to underscores, also removing all spaces */
def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") {
case (acc, c) if c.isUpper => acc + "_" + c.toLower
case (acc, c) if c == ' ' => acc
case (acc, c) => acc + c
}
/** converts spaces or underscores to hyphens, also lowering case */
def kebab: String = x.toLowerCase map {
case ' ' => '-'
case '_' => '-'
case c => c
}
def named(name: Option[String]): String = {
x + name.map("_named_" + _ ).getOrElse("_with_no_name")
}
def named(name: String): String = named(Some(name))
}
implicit def uintToBitPat(x: UInt): BitPat = BitPat(x)
implicit def wcToUInt(c: WideCounter): UInt = c.value
implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal {
def sextTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x)
}
def padTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(0.U((n - x.getWidth).W), x)
}
// shifts left by n if n >= 0, or right by -n if n < 0
def << (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << n(w-1, 0)
Mux(n(w), shifted >> (1 << w), shifted)
}
// shifts right by n if n >= 0, or left by -n if n < 0
def >> (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << (1 << w) >> n(w-1, 0)
Mux(n(w), shifted, shifted >> (1 << w))
}
// Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts
def extract(hi: Int, lo: Int): UInt = {
require(hi >= lo-1)
if (hi == lo-1) 0.U
else x(hi, lo)
}
// Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts
def extractOption(hi: Int, lo: Int): Option[UInt] = {
require(hi >= lo-1)
if (hi == lo-1) None
else Some(x(hi, lo))
}
// like x & ~y, but first truncate or zero-extend y to x's width
def andNot(y: UInt): UInt = x & ~(y | (x & 0.U))
def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n)
def rotateRight(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r))
}
}
def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n))
def rotateLeft(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r))
}
}
// compute (this + y) % n, given (this < n) and (y < n)
def addWrap(y: UInt, n: Int): UInt = {
val z = x +& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0)
}
// compute (this - y) % n, given (this < n) and (y < n)
def subWrap(y: UInt, n: Int): UInt = {
val z = x -& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0)
}
def grouped(width: Int): Seq[UInt] =
(0 until x.getWidth by width).map(base => x(base + width - 1, base))
def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds
def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x)
// Like >=, but prevents x-prop for ('x >= 0)
def >== (y: UInt): Bool = x >= y || y === 0.U
}
implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal {
def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y)
def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y)
}
implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal {
def toInt: Int = if (x) 1 else 0
// this one's snagged from scalaz
def option[T](z: => T): Option[T] = if (x) Some(z) else None
}
implicit class IntToAugmentedInt(private val x: Int) extends AnyVal {
// exact log2
def log2: Int = {
require(isPow2(x))
log2Ceil(x)
}
}
def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x)
def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x))
def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0)
def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1)
def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None
// Fill 1s from low bits to high bits
def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth)
def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0))
helper(1, x)(width-1, 0)
}
// Fill 1s form high bits to low bits
def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth)
def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x >> s))
helper(1, x)(width-1, 0)
}
def OptimizationBarrier[T <: Data](in: T): T = {
val barrier = Module(new Module {
val io = IO(new Bundle {
val x = Input(chiselTypeOf(in))
val y = Output(chiselTypeOf(in))
})
io.y := io.x
override def desiredName = s"OptimizationBarrier_${in.typeName}"
})
barrier.io.x := in
barrier.io.y
}
/** Similar to Seq.groupBy except this returns a Seq instead of a Map
* Useful for deterministic code generation
*/
def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = {
val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]]
for (x <- xs) {
val key = f(x)
val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A])
l += x
}
map.view.map({ case (k, vs) => k -> vs.toList }).toList
}
def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match {
case 1 => List.fill(n)(in.head)
case x if x == n => in
case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in")
}
// HeterogeneousBag moved to standalond diplomacy
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts)
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag
}
File Edges.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.util._
class TLEdge(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdgeParameters(client, manager, params, sourceInfo)
{
def isAligned(address: UInt, lgSize: UInt): Bool = {
if (maxLgSize == 0) true.B else {
val mask = UIntToOH1(lgSize, maxLgSize)
(address & mask) === 0.U
}
}
def mask(address: UInt, lgSize: UInt): UInt =
MaskGen(address, lgSize, manager.beatBytes)
def staticHasData(bundle: TLChannel): Option[Boolean] = {
bundle match {
case _:TLBundleA => {
// Do there exist A messages with Data?
val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial
// Do there exist A messages without Data?
val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint
// Statically optimize the case where hasData is a constant
if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None
}
case _:TLBundleB => {
// Do there exist B messages with Data?
val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial
// Do there exist B messages without Data?
val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint
// Statically optimize the case where hasData is a constant
if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None
}
case _:TLBundleC => {
// Do there eixst C messages with Data?
val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe
// Do there exist C messages without Data?
val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe
if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None
}
case _:TLBundleD => {
// Do there eixst D messages with Data?
val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB
// Do there exist D messages without Data?
val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT
if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None
}
case _:TLBundleE => Some(false)
}
}
def isRequest(x: TLChannel): Bool = {
x match {
case a: TLBundleA => true.B
case b: TLBundleB => true.B
case c: TLBundleC => c.opcode(2) && c.opcode(1)
// opcode === TLMessages.Release ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(2) && !d.opcode(1)
// opcode === TLMessages.Grant ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
}
def isResponse(x: TLChannel): Bool = {
x match {
case a: TLBundleA => false.B
case b: TLBundleB => false.B
case c: TLBundleC => !c.opcode(2) || !c.opcode(1)
// opcode =/= TLMessages.Release &&
// opcode =/= TLMessages.ReleaseData
case d: TLBundleD => true.B // Grant isResponse + isRequest
case e: TLBundleE => true.B
}
}
def hasData(x: TLChannel): Bool = {
val opdata = x match {
case a: TLBundleA => !a.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case b: TLBundleB => !b.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case c: TLBundleC => c.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.ProbeAckData ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
staticHasData(x).map(_.B).getOrElse(opdata)
}
def opcode(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.opcode
case b: TLBundleB => b.opcode
case c: TLBundleC => c.opcode
case d: TLBundleD => d.opcode
}
}
def param(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.param
case b: TLBundleB => b.param
case c: TLBundleC => c.param
case d: TLBundleD => d.param
}
}
def size(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.size
case b: TLBundleB => b.size
case c: TLBundleC => c.size
case d: TLBundleD => d.size
}
}
def data(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.data
case b: TLBundleB => b.data
case c: TLBundleC => c.data
case d: TLBundleD => d.data
}
}
def corrupt(x: TLDataChannel): Bool = {
x match {
case a: TLBundleA => a.corrupt
case b: TLBundleB => b.corrupt
case c: TLBundleC => c.corrupt
case d: TLBundleD => d.corrupt
}
}
def mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.mask
case b: TLBundleB => b.mask
case c: TLBundleC => mask(c.address, c.size)
}
}
def full_mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => mask(a.address, a.size)
case b: TLBundleB => mask(b.address, b.size)
case c: TLBundleC => mask(c.address, c.size)
}
}
def address(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.address
case b: TLBundleB => b.address
case c: TLBundleC => c.address
}
}
def source(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.source
case b: TLBundleB => b.source
case c: TLBundleC => c.source
case d: TLBundleD => d.source
}
}
def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes)
def addr_lo(x: UInt): UInt =
if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0)
def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x))
def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x))
def numBeats(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 1.U
case bundle: TLDataChannel => {
val hasData = this.hasData(bundle)
val size = this.size(bundle)
val cutoff = log2Ceil(manager.beatBytes)
val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U
val decode = UIntToOH(size, maxLgSize+1) >> cutoff
Mux(hasData, decode | small.asUInt, 1.U)
}
}
}
def numBeats1(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 0.U
case bundle: TLDataChannel => {
if (maxLgSize == 0) {
0.U
} else {
val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes)
Mux(hasData(bundle), decode, 0.U)
}
}
}
}
def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val beats1 = numBeats1(bits)
val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W))
val counter1 = counter - 1.U
val first = counter === 0.U
val last = counter === 1.U || beats1 === 0.U
val done = last && fire
val count = (beats1 & ~counter1)
when (fire) {
counter := Mux(first, beats1, counter1)
}
(first, last, done, count)
}
def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1
def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire)
def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid)
def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2
def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire)
def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid)
def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3
def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire)
def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid)
def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3)
}
def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire)
def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid)
def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4)
}
def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire)
def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid)
def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes))
}
def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire)
def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid)
// Does the request need T permissions to be executed?
def needT(a: TLBundleA): Bool = {
val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLPermissions.NtoB -> false.B,
TLPermissions.NtoT -> true.B,
TLPermissions.BtoT -> true.B))
MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array(
TLMessages.PutFullData -> true.B,
TLMessages.PutPartialData -> true.B,
TLMessages.ArithmeticData -> true.B,
TLMessages.LogicalData -> true.B,
TLMessages.Get -> false.B,
TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLHints.PREFETCH_READ -> false.B,
TLHints.PREFETCH_WRITE -> true.B)),
TLMessages.AcquireBlock -> acq_needT,
TLMessages.AcquirePerm -> acq_needT))
}
// This is a very expensive circuit; use only if you really mean it!
def inFlight(x: TLBundle): (UInt, UInt) = {
val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W))
val bce = manager.anySupportAcquireB && client.anySupportProbe
val (a_first, a_last, _) = firstlast(x.a)
val (b_first, b_last, _) = firstlast(x.b)
val (c_first, c_last, _) = firstlast(x.c)
val (d_first, d_last, _) = firstlast(x.d)
val (e_first, e_last, _) = firstlast(x.e)
val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits))
val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits))
val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits))
val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits))
val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits))
val a_inc = x.a.fire && a_first && a_request
val b_inc = x.b.fire && b_first && b_request
val c_inc = x.c.fire && c_first && c_request
val d_inc = x.d.fire && d_first && d_request
val e_inc = x.e.fire && e_first && e_request
val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil))
val a_dec = x.a.fire && a_last && a_response
val b_dec = x.b.fire && b_last && b_response
val c_dec = x.c.fire && c_last && c_response
val d_dec = x.d.fire && d_last && d_response
val e_dec = x.e.fire && e_last && e_response
val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil))
val next_flight = flight + PopCount(inc) - PopCount(dec)
flight := next_flight
(flight, next_flight)
}
def prettySourceMapping(context: String): String = {
s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n"
}
}
class TLEdgeOut(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
// Transfers
def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquireBlock
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquirePerm
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.Release
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ReleaseData
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) =
Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B)
def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAck
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions, data)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAckData
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B)
def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink)
def GrantAck(toSink: UInt): TLBundleE = {
val e = Wire(new TLBundleE(bundle))
e.sink := toSink
e
}
// Accesses
def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsGetFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Get
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutFullFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutFullData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, mask, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutPartialFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutPartialData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = {
require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsArithmeticFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.ArithmeticData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsLogicalFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.LogicalData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = {
require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsHintFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Hint
a.param := param
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data)
def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAckData
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size)
def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.HintAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
}
class TLEdgeIn(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = {
val todo = x.filter(!_.isEmpty)
val heads = todo.map(_.head)
val tails = todo.map(_.tail)
if (todo.isEmpty) Nil else { heads +: myTranspose(tails) }
}
// Transfers
def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = {
require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}")
val legal = client.supportsProbe(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Probe
b.param := capPermissions
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.Grant
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.GrantData
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B)
def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.ReleaseAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
// Accesses
def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = {
require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsGet(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Get
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsPutFull(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutFullData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, mask, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsPutPartial(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutPartialData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsArithmetic(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.ArithmeticData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsLogical(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.LogicalData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = {
require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsHint(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Hint
b.param := param
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size)
def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied)
def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data)
def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAckData
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B)
def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied)
def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B)
def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.HintAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
}
| module TLMonitor_23( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [28:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14]
input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input io_in_d_bits_sink, // @[Monitor.scala:20:14]
input io_in_d_bits_denied, // @[Monitor.scala:20:14]
input io_in_d_bits_corrupt // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire _a_first_T_1 = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35]
reg [8:0] a_first_counter; // @[Edges.scala:229:27]
reg [28:0] address; // @[Monitor.scala:391:22]
reg [8:0] d_first_counter; // @[Edges.scala:229:27]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [1:0] param_1; // @[Monitor.scala:539:22]
reg [3:0] size_1; // @[Monitor.scala:540:22]
reg sink; // @[Monitor.scala:542:22]
reg denied; // @[Monitor.scala:543:22]
reg [1:0] inflight; // @[Monitor.scala:614:27]
reg [3:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [7:0] inflight_sizes; // @[Monitor.scala:618:33]
reg [8:0] a_first_counter_1; // @[Edges.scala:229:27]
wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25]
reg [8:0] d_first_counter_1; // @[Edges.scala:229:27]
wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire a_set = _a_first_T_1 & a_first_1; // @[Decoupled.scala:51:35]
wire _GEN = io_in_d_valid & d_first_1; // @[Monitor.scala:674:26]
wire _GEN_0 = io_in_d_bits_opcode != 3'h6; // @[Monitor.scala:36:7, :673:46, :674:74]
wire d_clr = _GEN & _GEN_0; // @[Monitor.scala:673:46, :674:{26,71,74}]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
reg [1:0] inflight_1; // @[Monitor.scala:726:35]
reg [7:0] inflight_sizes_1; // @[Monitor.scala:728:35]
reg [8:0] d_first_counter_2; // @[Edges.scala:229:27]
wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire d_clr_1 = io_in_d_valid & d_first_2 & io_in_d_bits_opcode == 3'h6; // @[Monitor.scala:36:7, :673:46, :784:26, :788:70]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27] |
Generate the Verilog code corresponding to the following Chisel files.
File RegMapper.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.regmapper
import chisel3._
import chisel3.experimental.SourceInfo
import chisel3.util._
import freechips.rocketchip.diplomacy.AddressDecoder
import freechips.rocketchip.util.{BundleFieldBase, BundleMap, MuxSeq, ReduceOthers, property}
// A bus agnostic register interface to a register-based device
case class RegMapperParams(indexBits: Int, maskBits: Int, extraFields: Seq[BundleFieldBase] = Nil)
class RegMapperInput(val params: RegMapperParams) extends Bundle
{
val read = Bool()
val index = UInt((params.indexBits).W)
val data = UInt((params.maskBits*8).W)
val mask = UInt((params.maskBits).W)
val extra = BundleMap(params.extraFields)
}
class RegMapperOutput(val params: RegMapperParams) extends Bundle
{
val read = Bool()
val data = UInt((params.maskBits*8).W)
val extra = BundleMap(params.extraFields)
}
object RegMapper
{
// Create a generic register-based device
def apply(bytes: Int, concurrency: Int, undefZero: Boolean, in: DecoupledIO[RegMapperInput], mapping: RegField.Map*)(implicit sourceInfo: SourceInfo) = {
// Filter out zero-width fields
val bytemap = mapping.toList.map { case (offset, fields) => (offset, fields.filter(_.width != 0)) }
// Negative addresses are bad
bytemap.foreach { byte => require (byte._1 >= 0) }
// Transform all fields into bit offsets Seq[(bit, field)]
val bitmap = bytemap.map { case (byte, fields) =>
val bits = fields.scanLeft(byte * 8)(_ + _.width).init
bits zip fields
}.flatten.sortBy(_._1)
// Detect overlaps
(bitmap.init zip bitmap.tail) foreach { case ((lbit, lfield), (rbit, rfield)) =>
require (lbit + lfield.width <= rbit, s"Register map overlaps at bit ${rbit}.")
}
// Group those fields into bus words Map[word, List[(bit, field)]]
val wordmap = bitmap.groupBy(_._1 / (8*bytes))
// Make sure registers fit
val inParams = in.bits.params
val inBits = inParams.indexBits
assert (wordmap.keySet.max < (1 << inBits), "Register map does not fit in device")
val out = Wire(Decoupled(new RegMapperOutput(inParams)))
val front = Wire(Decoupled(new RegMapperInput(inParams)))
front.bits := in.bits
// Must this device pipeline the control channel?
val pipelined = wordmap.values.map(_.map(_._2.pipelined)).flatten.reduce(_ || _)
val depth = concurrency
require (depth >= 0)
require (!pipelined || depth > 0, "Register-based device with request/response handshaking needs concurrency > 0")
val back = if (depth > 0) {
val front_q = Module(new Queue(new RegMapperInput(inParams), depth) {
override def desiredName = s"Queue${depth}_${front.bits.typeName}_i${inParams.indexBits}_m${inParams.maskBits}"
})
front_q.io.enq <> front
front_q.io.deq
} else front
// Convert to and from Bits
def toBits(x: Int, tail: List[Boolean] = List.empty): List[Boolean] =
if (x == 0) tail.reverse else toBits(x >> 1, ((x & 1) == 1) :: tail)
def ofBits(bits: List[Boolean]) = bits.foldRight(0){ case (x,y) => (if (x) 1 else 0) | y << 1 }
// Find the minimal mask that can decide the register map
val mask = AddressDecoder(wordmap.keySet.toList)
val maskMatch = ~mask.U(inBits.W)
val maskFilter = toBits(mask)
val maskBits = maskFilter.filter(x => x).size
// Calculate size and indexes into the register map
val regSize = 1 << maskBits
def regIndexI(x: Int) = ofBits((maskFilter zip toBits(x)).filter(_._1).map(_._2))
def regIndexU(x: UInt) = if (maskBits == 0) 0.U else
Cat((maskFilter zip x.asBools).filter(_._1).map(_._2).reverse)
val findex = front.bits.index & maskMatch
val bindex = back .bits.index & maskMatch
// Protection flag for undefined registers
val iRightReg = Array.fill(regSize) { true.B }
val oRightReg = Array.fill(regSize) { true.B }
// Transform the wordmap into minimal decoded indexes, Seq[(index, bit, field)]
val flat = wordmap.toList.map { case (word, fields) =>
val index = regIndexI(word)
if (undefZero) {
val uint = (word & ~mask).U(inBits.W)
iRightReg(index) = findex === uint
oRightReg(index) = bindex === uint
}
// Confirm that no field spans a word boundary
fields foreach { case (bit, field) =>
val off = bit - 8*bytes*word
// println(s"Reg ${word}: [${off}, ${off+field.width})")
require (off + field.width <= bytes * 8, s"Field at word ${word}*(${bytes}B) has bits [${off}, ${off+field.width}), which exceeds word limit.")
}
// println("mapping 0x%x -> 0x%x for 0x%x/%d".format(word, index, mask, maskBits))
fields.map { case (bit, field) => (index, bit-8*bytes*word, field) }
}.flatten
// Forward declaration of all flow control signals
val rivalid = Wire(Vec(flat.size, Bool()))
val wivalid = Wire(Vec(flat.size, Bool()))
val roready = Wire(Vec(flat.size, Bool()))
val woready = Wire(Vec(flat.size, Bool()))
// Per-register list of all control signals needed for data to flow
val rifire = Array.fill(regSize) { Nil:List[(Bool, Bool)] }
val wifire = Array.fill(regSize) { Nil:List[(Bool, Bool)] }
val rofire = Array.fill(regSize) { Nil:List[(Bool, Bool)] }
val wofire = Array.fill(regSize) { Nil:List[(Bool, Bool)] }
// The output values for each register
val dataOut = Array.fill(regSize) { 0.U }
// Which bits are touched?
val frontMask = FillInterleaved(8, front.bits.mask)
val backMask = FillInterleaved(8, back .bits.mask)
// Connect the fields
for (i <- 0 until flat.size) {
val (reg, low, field) = flat(i)
val high = low + field.width - 1
// Confirm that no register is too big
require (high < 8*bytes)
val rimask = frontMask(high, low).orR
val wimask = frontMask(high, low).andR
val romask = backMask(high, low).orR
val womask = backMask(high, low).andR
val data = if (field.write.combinational) back.bits.data else front.bits.data
val f_rivalid = rivalid(i) && rimask
val f_roready = roready(i) && romask
val f_wivalid = wivalid(i) && wimask
val f_woready = woready(i) && womask
val (f_riready, f_rovalid, f_data) = field.read.fn(f_rivalid, f_roready)
val (f_wiready, f_wovalid) = field.write.fn(f_wivalid, f_woready, data(high, low))
// cover reads and writes to register
val fname = field.desc.map{_.name}.getOrElse("")
val fdesc = field.desc.map{_.desc + ":"}.getOrElse("")
val facct = field.desc.map{_.access}.getOrElse("")
if((facct == RegFieldAccessType.R) || (facct == RegFieldAccessType.RW)) {
property.cover(f_rivalid && f_riready, fname + "_Reg_read_start", fdesc + " RegField Read Request Initiate")
property.cover(f_rovalid && f_roready, fname + "_Reg_read_out", fdesc + " RegField Read Request Complete")
}
if((facct == RegFieldAccessType.W) || (facct == RegFieldAccessType.RW)) {
property.cover(f_wivalid && f_wiready, fname + "_Reg_write_start", fdesc + " RegField Write Request Initiate")
property.cover(f_wovalid && f_woready, fname + "_Reg_write_out", fdesc + " RegField Write Request Complete")
}
def litOR(x: Bool, y: Bool) = if (x.isLit && x.litValue == 1) true.B else x || y
// Add this field to the ready-valid signals for the register
rifire(reg) = (rivalid(i), litOR(f_riready, !rimask)) +: rifire(reg)
wifire(reg) = (wivalid(i), litOR(f_wiready, !wimask)) +: wifire(reg)
rofire(reg) = (roready(i), litOR(f_rovalid, !romask)) +: rofire(reg)
wofire(reg) = (woready(i), litOR(f_wovalid, !womask)) +: wofire(reg)
// ... this loop iterates from smallest to largest bit offset
val prepend = if (low == 0) { f_data } else { Cat(f_data, dataOut(reg) | 0.U(low.W)) }
dataOut(reg) = (prepend | 0.U((high+1).W))(high, 0)
}
// Which register is touched?
val iindex = regIndexU(front.bits.index)
val oindex = regIndexU(back .bits.index)
val frontSel = UIntToOH(iindex).asBools
val backSel = UIntToOH(oindex).asBools
// Compute: is the selected register ready? ... and cross-connect all ready-valids
def mux(index: UInt, valid: Bool, select: Seq[Bool], guard: Seq[Bool], flow: Seq[Seq[(Bool, Bool)]]): Bool =
MuxSeq(index, true.B, ((select zip guard) zip flow).map { case ((s, g), f) =>
val out = Wire(Bool())
ReduceOthers((out, valid && s && g) +: f)
out || !g
})
// Include the per-register one-hot selected criteria
val rifireMux = mux(iindex, in.valid && front.ready && front.bits.read, frontSel, iRightReg, rifire)
val wifireMux = mux(iindex, in.valid && front.ready && !front.bits.read, frontSel, iRightReg, wifire)
val rofireMux = mux(oindex, back.valid && out.ready && back .bits.read, backSel, oRightReg, rofire)
val wofireMux = mux(oindex, back.valid && out.ready && !back .bits.read, backSel, oRightReg, wofire)
val iready = Mux(front.bits.read, rifireMux, wifireMux)
val oready = Mux(back .bits.read, rofireMux, wofireMux)
// Connect the pipeline
in.ready := front.ready && iready
front.valid := in.valid && iready
back.ready := out.ready && oready
out.valid := back.valid && oready
out.bits.read := back.bits.read
out.bits.data := Mux(MuxSeq(oindex, true.B, oRightReg),
MuxSeq(oindex, 0.U, dataOut),
0.U)
out.bits.extra := back.bits.extra
out
}
}
| module Queue1_RegMapperInput_i9_m8_2( // @[RegMapper.scala:71:32]
input clock, // @[RegMapper.scala:71:32]
input reset, // @[RegMapper.scala:71:32]
output io_enq_ready, // @[Decoupled.scala:255:14]
input io_enq_valid, // @[Decoupled.scala:255:14]
input io_enq_bits_read, // @[Decoupled.scala:255:14]
input [8:0] io_enq_bits_index, // @[Decoupled.scala:255:14]
input [63:0] io_enq_bits_data, // @[Decoupled.scala:255:14]
input [7:0] io_enq_bits_mask, // @[Decoupled.scala:255:14]
input [6:0] io_enq_bits_extra_tlrr_extra_source, // @[Decoupled.scala:255:14]
input [2:0] io_enq_bits_extra_tlrr_extra_size, // @[Decoupled.scala:255:14]
input io_deq_ready, // @[Decoupled.scala:255:14]
output io_deq_valid, // @[Decoupled.scala:255:14]
output io_deq_bits_read, // @[Decoupled.scala:255:14]
output [8:0] io_deq_bits_index, // @[Decoupled.scala:255:14]
output [63:0] io_deq_bits_data, // @[Decoupled.scala:255:14]
output [7:0] io_deq_bits_mask, // @[Decoupled.scala:255:14]
output [6:0] io_deq_bits_extra_tlrr_extra_source, // @[Decoupled.scala:255:14]
output [2:0] io_deq_bits_extra_tlrr_extra_size // @[Decoupled.scala:255:14]
);
wire io_enq_valid_0 = io_enq_valid; // @[RegMapper.scala:71:32]
wire io_enq_bits_read_0 = io_enq_bits_read; // @[RegMapper.scala:71:32]
wire [8:0] io_enq_bits_index_0 = io_enq_bits_index; // @[RegMapper.scala:71:32]
wire [63:0] io_enq_bits_data_0 = io_enq_bits_data; // @[RegMapper.scala:71:32]
wire [7:0] io_enq_bits_mask_0 = io_enq_bits_mask; // @[RegMapper.scala:71:32]
wire [6:0] io_enq_bits_extra_tlrr_extra_source_0 = io_enq_bits_extra_tlrr_extra_source; // @[RegMapper.scala:71:32]
wire [2:0] io_enq_bits_extra_tlrr_extra_size_0 = io_enq_bits_extra_tlrr_extra_size; // @[RegMapper.scala:71:32]
wire io_deq_ready_0 = io_deq_ready; // @[RegMapper.scala:71:32]
wire ptr_match = 1'h1; // @[Decoupled.scala:260:33]
wire [1:0] _ptr_diff_T = 2'h0; // @[Decoupled.scala:309:32]
wire enq_ptr_value = 1'h0; // @[Counter.scala:61:73]
wire deq_ptr_value = 1'h0; // @[Counter.scala:61:73]
wire _io_enq_ready_T; // @[Decoupled.scala:286:19]
wire _io_deq_bits_WIRE = 1'h0; // @[Decoupled.scala:293:23]
wire ptr_diff = 1'h0; // @[Decoupled.scala:309:32]
wire _io_deq_valid_T; // @[Decoupled.scala:285:19]
wire _io_count_T_2; // @[Decoupled.scala:312:62]
wire io_enq_ready_0; // @[RegMapper.scala:71:32]
wire [6:0] io_deq_bits_extra_tlrr_extra_source_0; // @[RegMapper.scala:71:32]
wire [2:0] io_deq_bits_extra_tlrr_extra_size_0; // @[RegMapper.scala:71:32]
wire io_deq_bits_read_0; // @[RegMapper.scala:71:32]
wire [8:0] io_deq_bits_index_0; // @[RegMapper.scala:71:32]
wire [63:0] io_deq_bits_data_0; // @[RegMapper.scala:71:32]
wire [7:0] io_deq_bits_mask_0; // @[RegMapper.scala:71:32]
wire io_deq_valid_0; // @[RegMapper.scala:71:32]
wire io_count; // @[RegMapper.scala:71:32]
reg [91:0] ram; // @[Decoupled.scala:256:91]
assign io_deq_bits_read_0 = ram[0]; // @[Decoupled.scala:256:91]
assign io_deq_bits_index_0 = ram[9:1]; // @[Decoupled.scala:256:91]
assign io_deq_bits_data_0 = ram[73:10]; // @[Decoupled.scala:256:91]
assign io_deq_bits_mask_0 = ram[81:74]; // @[Decoupled.scala:256:91]
assign io_deq_bits_extra_tlrr_extra_source_0 = ram[88:82]; // @[Decoupled.scala:256:91]
assign io_deq_bits_extra_tlrr_extra_size_0 = ram[91:89]; // @[Decoupled.scala:256:91]
reg maybe_full; // @[Decoupled.scala:259:27]
wire full = maybe_full; // @[Decoupled.scala:259:27, :262:24]
wire _io_count_T = maybe_full; // @[Decoupled.scala:259:27, :312:32]
wire _empty_T = ~maybe_full; // @[Decoupled.scala:259:27, :261:28]
wire empty = _empty_T; // @[Decoupled.scala:261:{25,28}]
wire _do_enq_T = io_enq_ready_0 & io_enq_valid_0; // @[Decoupled.scala:51:35]
wire do_enq = _do_enq_T; // @[Decoupled.scala:51:35, :263:27]
wire _do_deq_T = io_deq_ready_0 & io_deq_valid_0; // @[Decoupled.scala:51:35]
wire do_deq = _do_deq_T; // @[Decoupled.scala:51:35, :264:27]
assign _io_deq_valid_T = ~empty; // @[Decoupled.scala:261:25, :285:19]
assign io_deq_valid_0 = _io_deq_valid_T; // @[Decoupled.scala:285:19]
assign _io_enq_ready_T = ~full; // @[Decoupled.scala:262:24, :286:19]
assign io_enq_ready_0 = _io_enq_ready_T; // @[Decoupled.scala:286:19]
wire _io_count_T_1 = _io_count_T; // @[Decoupled.scala:312:{20,32}]
assign _io_count_T_2 = _io_count_T_1; // @[Decoupled.scala:312:{20,62}]
assign io_count = _io_count_T_2; // @[Decoupled.scala:312:62]
always @(posedge clock) begin // @[RegMapper.scala:71:32]
if (do_enq) // @[Decoupled.scala:263:27]
ram <= {io_enq_bits_extra_tlrr_extra_size_0, io_enq_bits_extra_tlrr_extra_source_0, io_enq_bits_mask_0, io_enq_bits_data_0, io_enq_bits_index_0, io_enq_bits_read_0}; // @[Decoupled.scala:256:91]
if (reset) // @[RegMapper.scala:71:32]
maybe_full <= 1'h0; // @[Decoupled.scala:259:27]
else if (~(do_enq == do_deq)) // @[Decoupled.scala:259:27, :263:27, :264:27, :276:{15,27}, :277:16]
maybe_full <= do_enq; // @[Decoupled.scala:259:27, :263:27]
always @(posedge)
assign io_enq_ready = io_enq_ready_0; // @[RegMapper.scala:71:32]
assign io_deq_valid = io_deq_valid_0; // @[RegMapper.scala:71:32]
assign io_deq_bits_read = io_deq_bits_read_0; // @[RegMapper.scala:71:32]
assign io_deq_bits_index = io_deq_bits_index_0; // @[RegMapper.scala:71:32]
assign io_deq_bits_data = io_deq_bits_data_0; // @[RegMapper.scala:71:32]
assign io_deq_bits_mask = io_deq_bits_mask_0; // @[RegMapper.scala:71:32]
assign io_deq_bits_extra_tlrr_extra_source = io_deq_bits_extra_tlrr_extra_source_0; // @[RegMapper.scala:71:32]
assign io_deq_bits_extra_tlrr_extra_size = io_deq_bits_extra_tlrr_extra_size_0; // @[RegMapper.scala:71:32]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File DescribedSRAM.scala:
// See LICENSE.Berkeley for license details.
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3.{Data, SyncReadMem, Vec}
import chisel3.util.log2Ceil
object DescribedSRAM {
def apply[T <: Data](
name: String,
desc: String,
size: BigInt, // depth
data: T
): SyncReadMem[T] = {
val mem = SyncReadMem(size, data)
mem.suggestName(name)
val granWidth = data match {
case v: Vec[_] => v.head.getWidth
case d => d.getWidth
}
val uid = 0
Annotated.srams(
component = mem,
name = name,
address_width = log2Ceil(size),
data_width = data.getWidth,
depth = size,
description = desc,
write_mask_granularity = granWidth
)
mem
}
}
| module cc_dir( // @[DescribedSRAM.scala:17:26]
input [9:0] RW0_addr,
input RW0_en,
input RW0_clk,
input RW0_wmode,
input [191:0] RW0_wdata,
output [191:0] RW0_rdata,
input [7:0] RW0_wmask
);
cc_dir_ext cc_dir_ext ( // @[DescribedSRAM.scala:17:26]
.RW0_addr (RW0_addr),
.RW0_en (RW0_en),
.RW0_clk (RW0_clk),
.RW0_wmode (RW0_wmode),
.RW0_wdata (RW0_wdata),
.RW0_rdata (RW0_rdata),
.RW0_wmask (RW0_wmask)
); // @[DescribedSRAM.scala:17:26]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File BankBinder.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import org.chipsalliance.diplomacy.lazymodule._
import freechips.rocketchip.diplomacy.{AddressSet, TransferSizes}
case class BankBinderNode(mask: BigInt)(implicit valName: ValName) extends TLCustomNode
{
private val bit = mask & -mask
val maxXfer = TransferSizes(1, if (bit == 0 || bit > 4096) 4096 else bit.toInt)
val ids = AddressSet.enumerateMask(mask)
def resolveStar(iKnown: Int, oKnown: Int, iStars: Int, oStars: Int): (Int, Int) = {
val ports = ids.size
val oStar = if (oStars == 0) 0 else (ports - oKnown) / oStars
val iStar = if (iStars == 0) 0 else (ports - iKnown) / iStars
require (ports == iKnown + iStar*iStars, s"${name} must have ${ports} inputs, but has ${iKnown} + ${iStar}*${iStars} (at ${lazyModule.line})")
require (ports == oKnown + oStar*oStars, s"${name} must have ${ports} outputs, but has ${oKnown} + ${oStar}*${oStars} (at ${lazyModule.line})")
(iStar, oStar)
}
def mapParamsD(n: Int, p: Seq[TLMasterPortParameters]): Seq[TLMasterPortParameters] =
(p zip ids) map { case (cp, id) => cp.v1copy(clients = cp.clients.map { c => c.v1copy(
visibility = c.visibility.flatMap { a => a.intersect(AddressSet(id, ~mask))},
supportsProbe = c.supports.probe intersect maxXfer,
supportsArithmetic = c.supports.arithmetic intersect maxXfer,
supportsLogical = c.supports.logical intersect maxXfer,
supportsGet = c.supports.get intersect maxXfer,
supportsPutFull = c.supports.putFull intersect maxXfer,
supportsPutPartial = c.supports.putPartial intersect maxXfer,
supportsHint = c.supports.hint intersect maxXfer)})}
def mapParamsU(n: Int, p: Seq[TLSlavePortParameters]): Seq[TLSlavePortParameters] =
(p zip ids) map { case (mp, id) => mp.v1copy(managers = mp.managers.flatMap { m =>
val addresses = m.address.flatMap(a => a.intersect(AddressSet(id, ~mask)))
if (addresses.nonEmpty)
Some(m.v1copy(
address = addresses,
supportsAcquireT = m.supportsAcquireT intersect maxXfer,
supportsAcquireB = m.supportsAcquireB intersect maxXfer,
supportsArithmetic = m.supportsArithmetic intersect maxXfer,
supportsLogical = m.supportsLogical intersect maxXfer,
supportsGet = m.supportsGet intersect maxXfer,
supportsPutFull = m.supportsPutFull intersect maxXfer,
supportsPutPartial = m.supportsPutPartial intersect maxXfer,
supportsHint = m.supportsHint intersect maxXfer))
else None
})}
}
/* A BankBinder is used to divide contiguous memory regions into banks, suitable for a cache */
class BankBinder(mask: BigInt)(implicit p: Parameters) extends LazyModule
{
val node = BankBinderNode(mask)
lazy val module = new Impl
class Impl extends LazyModuleImp(this) {
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
out <> in
}
}
}
object BankBinder
{
def apply(mask: BigInt)(implicit p: Parameters): TLNode = {
val binder = LazyModule(new BankBinder(mask))
binder.node
}
def apply(nBanks: Int, granularity: Int)(implicit p: Parameters): TLNode = {
if (nBanks > 0) apply(granularity * (nBanks-1))
else TLTempNode()
}
}
File Buffer.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import org.chipsalliance.diplomacy.lazymodule._
import freechips.rocketchip.diplomacy.BufferParams
class TLBufferNode (
a: BufferParams,
b: BufferParams,
c: BufferParams,
d: BufferParams,
e: BufferParams)(implicit valName: ValName) extends TLAdapterNode(
clientFn = { p => p.v1copy(minLatency = p.minLatency + b.latency + c.latency) },
managerFn = { p => p.v1copy(minLatency = p.minLatency + a.latency + d.latency) }
) {
override lazy val nodedebugstring = s"a:${a.toString}, b:${b.toString}, c:${c.toString}, d:${d.toString}, e:${e.toString}"
override def circuitIdentity = List(a,b,c,d,e).forall(_ == BufferParams.none)
}
class TLBuffer(
a: BufferParams,
b: BufferParams,
c: BufferParams,
d: BufferParams,
e: BufferParams)(implicit p: Parameters) extends LazyModule
{
def this(ace: BufferParams, bd: BufferParams)(implicit p: Parameters) = this(ace, bd, ace, bd, ace)
def this(abcde: BufferParams)(implicit p: Parameters) = this(abcde, abcde)
def this()(implicit p: Parameters) = this(BufferParams.default)
val node = new TLBufferNode(a, b, c, d, e)
lazy val module = new Impl
class Impl extends LazyModuleImp(this) {
def headBundle = node.out.head._2.bundle
override def desiredName = (Seq("TLBuffer") ++ node.out.headOption.map(_._2.bundle.shortName)).mkString("_")
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
out.a <> a(in .a)
in .d <> d(out.d)
if (edgeOut.manager.anySupportAcquireB && edgeOut.client.anySupportProbe) {
in .b <> b(out.b)
out.c <> c(in .c)
out.e <> e(in .e)
} else {
in.b.valid := false.B
in.c.ready := true.B
in.e.ready := true.B
out.b.ready := true.B
out.c.valid := false.B
out.e.valid := false.B
}
}
}
}
object TLBuffer
{
def apply() (implicit p: Parameters): TLNode = apply(BufferParams.default)
def apply(abcde: BufferParams) (implicit p: Parameters): TLNode = apply(abcde, abcde)
def apply(ace: BufferParams, bd: BufferParams)(implicit p: Parameters): TLNode = apply(ace, bd, ace, bd, ace)
def apply(
a: BufferParams,
b: BufferParams,
c: BufferParams,
d: BufferParams,
e: BufferParams)(implicit p: Parameters): TLNode =
{
val buffer = LazyModule(new TLBuffer(a, b, c, d, e))
buffer.node
}
def chain(depth: Int, name: Option[String] = None)(implicit p: Parameters): Seq[TLNode] = {
val buffers = Seq.fill(depth) { LazyModule(new TLBuffer()) }
name.foreach { n => buffers.zipWithIndex.foreach { case (b, i) => b.suggestName(s"${n}_${i}") } }
buffers.map(_.node)
}
def chainNode(depth: Int, name: Option[String] = None)(implicit p: Parameters): TLNode = {
chain(depth, name)
.reduceLeftOption(_ :*=* _)
.getOrElse(TLNameNode("no_buffer"))
}
}
File Filter.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy.lazymodule._
import freechips.rocketchip.diplomacy.{AddressSet, RegionType, TransferSizes}
class TLFilter(
mfilter: TLFilter.ManagerFilter = TLFilter.mIdentity,
cfilter: TLFilter.ClientFilter = TLFilter.cIdentity
)(implicit p: Parameters) extends LazyModule
{
val node = new TLAdapterNode(
clientFn = { cp => cp.v1copy(clients = cp.clients.flatMap { c =>
val out = cfilter(c)
out.map { o => // Confirm the filter only REMOVES capability
require (c.sourceId.contains(o.sourceId))
require (c.supports.probe.contains(o.supports.probe))
require (c.supports.arithmetic.contains(o.supports.arithmetic))
require (c.supports.logical.contains(o.supports.logical))
require (c.supports.get.contains(o.supports.get))
require (c.supports.putFull.contains(o.supports.putFull))
require (c.supports.putPartial.contains(o.supports.putPartial))
require (c.supports.hint.contains(o.supports.hint))
require (!c.requestFifo || o.requestFifo)
}
out
})},
managerFn = { mp =>
val managers = mp.managers.flatMap { m =>
val out = mfilter(m)
out.map { o => // Confirm the filter only REMOVES capability
o.address.foreach { a => require (m.address.map(_.contains(a)).reduce(_||_)) }
require (o.regionType <= m.regionType)
// we allow executable to be changed both ways
require (m.supportsAcquireT.contains(o.supportsAcquireT))
require (m.supportsAcquireB.contains(o.supportsAcquireB))
require (m.supportsArithmetic.contains(o.supportsArithmetic))
require (m.supportsLogical.contains(o.supportsLogical))
require (m.supportsGet.contains(o.supportsGet))
require (m.supportsPutFull.contains(o.supportsPutFull))
require (m.supportsPutPartial.contains(o.supportsPutPartial))
require (m.supportsHint.contains(o.supportsHint))
require (!o.fifoId.isDefined || m.fifoId == o.fifoId)
}
out
}
mp.v1copy(managers = managers,
endSinkId = if (managers.exists(_.supportsAcquireB)) mp.endSinkId else 0)
}
) {
override def circuitIdentity = true
}
lazy val module = new Impl
class Impl extends LazyModuleImp(this) {
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
out <> in
// In case the inner interface removes Acquire, tie-off the channels
if (!edgeIn.manager.anySupportAcquireB) {
in.b.valid := false.B
in.c.ready := true.B
in.e.ready := true.B
out.b.ready := true.B
out.c.valid := false.B
out.e.valid := false.B
}
}
}
}
object TLFilter
{
type ManagerFilter = TLSlaveParameters => Option[TLSlaveParameters]
type ClientFilter = TLMasterParameters => Option[TLMasterParameters]
// preserve manager visibility
def mIdentity: ManagerFilter = { m => Some(m) }
// preserve client visibility
def cIdentity: ClientFilter = { c => Some(c) }
// make only the intersected address sets visible
def mSelectIntersect(select: AddressSet): ManagerFilter = { m =>
val filtered = m.address.map(_.intersect(select)).flatten
val alignment = select.alignment /* alignment 0 means 'select' selected everything */
transferSizeHelper(m, filtered, alignment)
}
// make everything except the intersected address sets visible
def mSubtract(excepts: Seq[AddressSet]): ManagerFilter = { m =>
val filtered = excepts.foldLeft(m.address) { (a,e) => a.flatMap(_.subtract(e)) }
val alignment: BigInt = if (filtered.isEmpty) 0 else filtered.map(_.alignment).min
transferSizeHelper(m, filtered, alignment)
}
def mSubtract(except: AddressSet): ManagerFilter = { m =>
mSubtract(Seq(except))(m)
}
// adjust supported transfer sizes based on filtered intersection
private def transferSizeHelper(m: TLSlaveParameters, filtered: Seq[AddressSet], alignment: BigInt): Option[TLSlaveParameters] = {
val maxTransfer = 1 << 30
val capTransfer = if (alignment == 0 || alignment > maxTransfer) maxTransfer else alignment.toInt
val cap = TransferSizes(1, capTransfer)
if (filtered.isEmpty) { None } else {
Some(m.v1copy(
address = filtered,
supportsAcquireT = m.supportsAcquireT .intersect(cap),
supportsAcquireB = m.supportsAcquireB .intersect(cap),
supportsArithmetic = m.supportsArithmetic.intersect(cap),
supportsLogical = m.supportsLogical .intersect(cap),
supportsGet = m.supportsGet .intersect(cap),
supportsPutFull = m.supportsPutFull .intersect(cap),
supportsPutPartial = m.supportsPutPartial.intersect(cap),
supportsHint = m.supportsHint .intersect(cap)))
}
}
// hide any fully contained address sets
def mHideContained(containedBy: AddressSet): ManagerFilter = { m =>
val filtered = m.address.filterNot(containedBy.contains(_))
if (filtered.isEmpty) None else Some(m.v1copy(address = filtered))
}
// hide all cacheable managers
def mHideCacheable: ManagerFilter = { m =>
if (m.supportsAcquireB) None else Some(m)
}
// make visible only cacheable managers
def mSelectCacheable: ManagerFilter = { m =>
if (m.supportsAcquireB) Some(m) else None
}
// cacheable managers cannot be acquired from
def mMaskCacheable: ManagerFilter = { m =>
if (m.supportsAcquireB) {
Some(m.v1copy(
regionType = RegionType.UNCACHED,
supportsAcquireB = TransferSizes.none,
supportsAcquireT = TransferSizes.none,
alwaysGrantsT = false))
} else { Some(m) }
}
// only cacheable managers are visible, but cannot be acquired from
def mSelectAndMaskCacheable: ManagerFilter = { m =>
if (m.supportsAcquireB) {
Some(m.v1copy(
regionType = RegionType.UNCACHED,
supportsAcquireB = TransferSizes.none,
supportsAcquireT = TransferSizes.none,
alwaysGrantsT = false))
} else { None }
}
// hide all caching clients
def cHideCaching: ClientFilter = { c =>
if (c.supports.probe) None else Some(c)
}
// onyl caching clients are visible
def cSelectCaching: ClientFilter = { c =>
if (c.supports.probe) Some(c) else None
}
// removes resources from managers
def mResourceRemover: ManagerFilter = { m =>
Some(m.v2copy(resources=Nil))
}
// default application applies neither type of filter unless overridden
def apply(
mfilter: ManagerFilter = TLFilter.mIdentity,
cfilter: ClientFilter = TLFilter.cIdentity
)(implicit p: Parameters): TLNode =
{
val filter = LazyModule(new TLFilter(mfilter, cfilter))
filter.node
}
}
File package.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip
import chisel3._
import chisel3.util._
import scala.math.min
import scala.collection.{immutable, mutable}
package object util {
implicit class UnzippableOption[S, T](val x: Option[(S, T)]) {
def unzip = (x.map(_._1), x.map(_._2))
}
implicit class UIntIsOneOf(private val x: UInt) extends AnyVal {
def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR
def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq)
}
implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal {
/** Like Vec.apply(idx), but tolerates indices of mismatched width */
def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0))
}
implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal {
def apply(idx: UInt): T = {
if (x.size <= 1) {
x.head
} else if (!isPow2(x.size)) {
// For non-power-of-2 seqs, reflect elements to simplify decoder
(x ++ x.takeRight(x.size & -x.size)).toSeq(idx)
} else {
// Ignore MSBs of idx
val truncIdx =
if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx
else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0)
x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) }
}
}
def extract(idx: UInt): T = VecInit(x).extract(idx)
def asUInt: UInt = Cat(x.map(_.asUInt).reverse)
def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n)
def rotate(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n)
def rotateRight(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
}
// allow bitwise ops on Seq[Bool] just like UInt
implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal {
def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b }
def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b }
def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b }
def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x
def >> (n: Int): Seq[Bool] = x drop n
def unary_~ : Seq[Bool] = x.map(!_)
def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_)
def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_)
def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_)
private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B)
}
implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal {
def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable))
def getElements: Seq[Element] = x match {
case e: Element => Seq(e)
case a: Aggregate => a.getElements.flatMap(_.getElements)
}
}
/** Any Data subtype that has a Bool member named valid. */
type DataCanBeValid = Data { val valid: Bool }
implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal {
def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable)
}
implicit class StringToAugmentedString(private val x: String) extends AnyVal {
/** converts from camel case to to underscores, also removing all spaces */
def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") {
case (acc, c) if c.isUpper => acc + "_" + c.toLower
case (acc, c) if c == ' ' => acc
case (acc, c) => acc + c
}
/** converts spaces or underscores to hyphens, also lowering case */
def kebab: String = x.toLowerCase map {
case ' ' => '-'
case '_' => '-'
case c => c
}
def named(name: Option[String]): String = {
x + name.map("_named_" + _ ).getOrElse("_with_no_name")
}
def named(name: String): String = named(Some(name))
}
implicit def uintToBitPat(x: UInt): BitPat = BitPat(x)
implicit def wcToUInt(c: WideCounter): UInt = c.value
implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal {
def sextTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x)
}
def padTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(0.U((n - x.getWidth).W), x)
}
// shifts left by n if n >= 0, or right by -n if n < 0
def << (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << n(w-1, 0)
Mux(n(w), shifted >> (1 << w), shifted)
}
// shifts right by n if n >= 0, or left by -n if n < 0
def >> (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << (1 << w) >> n(w-1, 0)
Mux(n(w), shifted, shifted >> (1 << w))
}
// Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts
def extract(hi: Int, lo: Int): UInt = {
require(hi >= lo-1)
if (hi == lo-1) 0.U
else x(hi, lo)
}
// Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts
def extractOption(hi: Int, lo: Int): Option[UInt] = {
require(hi >= lo-1)
if (hi == lo-1) None
else Some(x(hi, lo))
}
// like x & ~y, but first truncate or zero-extend y to x's width
def andNot(y: UInt): UInt = x & ~(y | (x & 0.U))
def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n)
def rotateRight(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r))
}
}
def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n))
def rotateLeft(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r))
}
}
// compute (this + y) % n, given (this < n) and (y < n)
def addWrap(y: UInt, n: Int): UInt = {
val z = x +& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0)
}
// compute (this - y) % n, given (this < n) and (y < n)
def subWrap(y: UInt, n: Int): UInt = {
val z = x -& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0)
}
def grouped(width: Int): Seq[UInt] =
(0 until x.getWidth by width).map(base => x(base + width - 1, base))
def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds
def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x)
// Like >=, but prevents x-prop for ('x >= 0)
def >== (y: UInt): Bool = x >= y || y === 0.U
}
implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal {
def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y)
def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y)
}
implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal {
def toInt: Int = if (x) 1 else 0
// this one's snagged from scalaz
def option[T](z: => T): Option[T] = if (x) Some(z) else None
}
implicit class IntToAugmentedInt(private val x: Int) extends AnyVal {
// exact log2
def log2: Int = {
require(isPow2(x))
log2Ceil(x)
}
}
def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x)
def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x))
def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0)
def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1)
def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None
// Fill 1s from low bits to high bits
def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth)
def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0))
helper(1, x)(width-1, 0)
}
// Fill 1s form high bits to low bits
def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth)
def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x >> s))
helper(1, x)(width-1, 0)
}
def OptimizationBarrier[T <: Data](in: T): T = {
val barrier = Module(new Module {
val io = IO(new Bundle {
val x = Input(chiselTypeOf(in))
val y = Output(chiselTypeOf(in))
})
io.y := io.x
override def desiredName = s"OptimizationBarrier_${in.typeName}"
})
barrier.io.x := in
barrier.io.y
}
/** Similar to Seq.groupBy except this returns a Seq instead of a Map
* Useful for deterministic code generation
*/
def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = {
val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]]
for (x <- xs) {
val key = f(x)
val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A])
l += x
}
map.view.map({ case (k, vs) => k -> vs.toList }).toList
}
def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match {
case 1 => List.fill(n)(in.head)
case x if x == n => in
case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in")
}
// HeterogeneousBag moved to standalond diplomacy
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts)
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag
}
File ClockDomain.scala:
package freechips.rocketchip.prci
import chisel3._
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy.lazymodule._
abstract class Domain(implicit p: Parameters) extends LazyModule with HasDomainCrossing
{
def clockBundle: ClockBundle
lazy val module = new Impl
class Impl extends LazyRawModuleImp(this) {
childClock := clockBundle.clock
childReset := clockBundle.reset
override def provideImplicitClockToLazyChildren = true
// these are just for backwards compatibility with external devices
// that were manually wiring themselves to the domain's clock/reset input:
val clock = IO(Output(chiselTypeOf(clockBundle.clock)))
val reset = IO(Output(chiselTypeOf(clockBundle.reset)))
clock := clockBundle.clock
reset := clockBundle.reset
}
}
abstract class ClockDomain(implicit p: Parameters) extends Domain with HasClockDomainCrossing
class ClockSinkDomain(val clockSinkParams: ClockSinkParameters)(implicit p: Parameters) extends ClockDomain
{
def this(take: Option[ClockParameters] = None, name: Option[String] = None)(implicit p: Parameters) = this(ClockSinkParameters(take = take, name = name))
val clockNode = ClockSinkNode(Seq(clockSinkParams))
def clockBundle = clockNode.in.head._1
override lazy val desiredName = (clockSinkParams.name.toSeq :+ "ClockSinkDomain").mkString
}
class ClockSourceDomain(val clockSourceParams: ClockSourceParameters)(implicit p: Parameters) extends ClockDomain
{
def this(give: Option[ClockParameters] = None, name: Option[String] = None)(implicit p: Parameters) = this(ClockSourceParameters(give = give, name = name))
val clockNode = ClockSourceNode(Seq(clockSourceParams))
def clockBundle = clockNode.out.head._1
override lazy val desiredName = (clockSourceParams.name.toSeq :+ "ClockSourceDomain").mkString
}
abstract class ResetDomain(implicit p: Parameters) extends Domain with HasResetDomainCrossing
File Jbar.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy.lazymodule._
import freechips.rocketchip.diplomacy.AddressSet
class TLJbar(policy: TLArbiter.Policy = TLArbiter.roundRobin)(implicit p: Parameters) extends LazyModule
{
val node: TLJunctionNode = new TLJunctionNode(
clientFn = { seq =>
Seq.fill(node.dRatio)(seq(0).v1copy(
minLatency = seq.map(_.minLatency).min,
clients = (TLXbar.mapInputIds(seq) zip seq) flatMap { case (range, port) =>
port.clients map { client => client.v1copy(
sourceId = client.sourceId.shift(range.start)
)}
}
))
},
managerFn = { seq =>
val fifoIdFactory = TLXbar.relabeler()
Seq.fill(node.uRatio)(seq(0).v1copy(
minLatency = seq.map(_.minLatency).min,
endSinkId = TLXbar.mapOutputIds(seq).map(_.end).max,
managers = seq.flatMap { port =>
require (port.beatBytes == seq(0).beatBytes,
s"Xbar data widths don't match: ${port.managers.map(_.name)} has ${port.beatBytes}B vs ${seq(0).managers.map(_.name)} has ${seq(0).beatBytes}B")
val fifoIdMapper = fifoIdFactory()
port.managers map { manager => manager.v1copy(
fifoId = manager.fifoId.map(fifoIdMapper(_))
)}
}
))
}) {
override def circuitIdentity = uRatio == 1 && dRatio == 1
}
lazy val module = new Impl
class Impl extends LazyModuleImp(this) {
node.inoutGrouped.foreach { case (in, out) => TLXbar.circuit(policy, in, out) }
}
}
object TLJbar
{
def apply(policy: TLArbiter.Policy = TLArbiter.roundRobin)(implicit p: Parameters) = {
val jbar = LazyModule(new TLJbar(policy))
jbar.node
}
}
// Synthesizable unit tests
import freechips.rocketchip.unittest._
class TLJbarTestImp(nClients: Int, nManagers: Int, txns: Int)(implicit p: Parameters) extends LazyModule {
val jbar = LazyModule(new TLJbar)
val fuzzers = Seq.fill(nClients) {
val fuzzer = LazyModule(new TLFuzzer(txns))
jbar.node :*= TLXbar() := TLDelayer(0.1) := fuzzer.node
fuzzer
}
for (n <- 0 until nManagers) {
TLRAM(AddressSet(0x0+0x400*n, 0x3ff)) := TLFragmenter(4, 256) := TLDelayer(0.1) := jbar.node
}
lazy val module = new Impl
class Impl extends LazyModuleImp(this) with UnitTestModule {
io.finished := fuzzers.map(_.module.io.finished).reduce(_ && _)
}
}
class TLJbarTest(nClients: Int, nManagers: Int, txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) {
val dut = Module(LazyModule(new TLJbarTestImp(nClients, nManagers, txns)).module)
io.finished := dut.io.finished
dut.io.start := io.start
}
File ClockGroup.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.prci
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import org.chipsalliance.diplomacy.lazymodule._
import org.chipsalliance.diplomacy.nodes._
import freechips.rocketchip.resources.FixedClockResource
case class ClockGroupingNode(groupName: String)(implicit valName: ValName)
extends MixedNexusNode(ClockGroupImp, ClockImp)(
dFn = { _ => ClockSourceParameters() },
uFn = { seq => ClockGroupSinkParameters(name = groupName, members = seq) })
{
override def circuitIdentity = outputs.size == 1
}
class ClockGroup(groupName: String)(implicit p: Parameters) extends LazyModule
{
val node = ClockGroupingNode(groupName)
lazy val module = new Impl
class Impl extends LazyRawModuleImp(this) {
val (in, _) = node.in(0)
val (out, _) = node.out.unzip
require (node.in.size == 1)
require (in.member.size == out.size)
(in.member.data zip out) foreach { case (i, o) => o := i }
}
}
object ClockGroup
{
def apply()(implicit p: Parameters, valName: ValName) = LazyModule(new ClockGroup(valName.name)).node
}
case class ClockGroupAggregateNode(groupName: String)(implicit valName: ValName)
extends NexusNode(ClockGroupImp)(
dFn = { _ => ClockGroupSourceParameters() },
uFn = { seq => ClockGroupSinkParameters(name = groupName, members = seq.flatMap(_.members))})
{
override def circuitIdentity = outputs.size == 1
}
class ClockGroupAggregator(groupName: String)(implicit p: Parameters) extends LazyModule
{
val node = ClockGroupAggregateNode(groupName)
override lazy val desiredName = s"ClockGroupAggregator_$groupName"
lazy val module = new Impl
class Impl extends LazyRawModuleImp(this) {
val (in, _) = node.in.unzip
val (out, _) = node.out.unzip
val outputs = out.flatMap(_.member.data)
require (node.in.size == 1, s"Aggregator for groupName: ${groupName} had ${node.in.size} inward edges instead of 1")
require (in.head.member.size == outputs.size)
in.head.member.data.zip(outputs).foreach { case (i, o) => o := i }
}
}
object ClockGroupAggregator
{
def apply()(implicit p: Parameters, valName: ValName) = LazyModule(new ClockGroupAggregator(valName.name)).node
}
class SimpleClockGroupSource(numSources: Int = 1)(implicit p: Parameters) extends LazyModule
{
val node = ClockGroupSourceNode(List.fill(numSources) { ClockGroupSourceParameters() })
lazy val module = new Impl
class Impl extends LazyModuleImp(this) {
val (out, _) = node.out.unzip
out.map { out: ClockGroupBundle =>
out.member.data.foreach { o =>
o.clock := clock; o.reset := reset }
}
}
}
object SimpleClockGroupSource
{
def apply(num: Int = 1)(implicit p: Parameters, valName: ValName) = LazyModule(new SimpleClockGroupSource(num)).node
}
case class FixedClockBroadcastNode(fixedClockOpt: Option[ClockParameters])(implicit valName: ValName)
extends NexusNode(ClockImp)(
dFn = { seq => fixedClockOpt.map(_ => ClockSourceParameters(give = fixedClockOpt)).orElse(seq.headOption).getOrElse(ClockSourceParameters()) },
uFn = { seq => fixedClockOpt.map(_ => ClockSinkParameters(take = fixedClockOpt)).orElse(seq.headOption).getOrElse(ClockSinkParameters()) },
inputRequiresOutput = false) {
def fixedClockResources(name: String, prefix: String = "soc/"): Seq[Option[FixedClockResource]] = Seq(fixedClockOpt.map(t => new FixedClockResource(name, t.freqMHz, prefix)))
}
class FixedClockBroadcast(fixedClockOpt: Option[ClockParameters])(implicit p: Parameters) extends LazyModule
{
val node = new FixedClockBroadcastNode(fixedClockOpt) {
override def circuitIdentity = outputs.size == 1
}
lazy val module = new Impl
class Impl extends LazyRawModuleImp(this) {
val (in, _) = node.in(0)
val (out, _) = node.out.unzip
override def desiredName = s"FixedClockBroadcast_${out.size}"
require (node.in.size == 1, "FixedClockBroadcast can only broadcast a single clock")
out.foreach { _ := in }
}
}
object FixedClockBroadcast
{
def apply(fixedClockOpt: Option[ClockParameters] = None)(implicit p: Parameters, valName: ValName) = LazyModule(new FixedClockBroadcast(fixedClockOpt)).node
}
case class PRCIClockGroupNode()(implicit valName: ValName)
extends NexusNode(ClockGroupImp)(
dFn = { _ => ClockGroupSourceParameters() },
uFn = { _ => ClockGroupSinkParameters("prci", Nil) },
outputRequiresInput = false)
File WidthWidget.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy.lazymodule._
import freechips.rocketchip.diplomacy.AddressSet
import freechips.rocketchip.util.{Repeater, UIntToOH1}
// innBeatBytes => the new client-facing bus width
class TLWidthWidget(innerBeatBytes: Int)(implicit p: Parameters) extends LazyModule
{
private def noChangeRequired(manager: TLManagerPortParameters) = manager.beatBytes == innerBeatBytes
val node = new TLAdapterNode(
clientFn = { case c => c },
managerFn = { case m => m.v1copy(beatBytes = innerBeatBytes) }){
override def circuitIdentity = edges.out.map(_.manager).forall(noChangeRequired)
}
override lazy val desiredName = s"TLWidthWidget$innerBeatBytes"
lazy val module = new Impl
class Impl extends LazyModuleImp(this) {
def merge[T <: TLDataChannel](edgeIn: TLEdge, in: DecoupledIO[T], edgeOut: TLEdge, out: DecoupledIO[T]) = {
val inBytes = edgeIn.manager.beatBytes
val outBytes = edgeOut.manager.beatBytes
val ratio = outBytes / inBytes
val keepBits = log2Ceil(outBytes)
val dropBits = log2Ceil(inBytes)
val countBits = log2Ceil(ratio)
val size = edgeIn.size(in.bits)
val hasData = edgeIn.hasData(in.bits)
val limit = UIntToOH1(size, keepBits) >> dropBits
val count = RegInit(0.U(countBits.W))
val first = count === 0.U
val last = count === limit || !hasData
val enable = Seq.tabulate(ratio) { i => !((count ^ i.U) & limit).orR }
val corrupt_reg = RegInit(false.B)
val corrupt_in = edgeIn.corrupt(in.bits)
val corrupt_out = corrupt_in || corrupt_reg
when (in.fire) {
count := count + 1.U
corrupt_reg := corrupt_out
when (last) {
count := 0.U
corrupt_reg := false.B
}
}
def helper(idata: UInt): UInt = {
// rdata is X until the first time a multi-beat write occurs.
// Prevent the X from leaking outside by jamming the mux control until
// the first time rdata is written (and hence no longer X).
val rdata_written_once = RegInit(false.B)
val masked_enable = enable.map(_ || !rdata_written_once)
val odata = Seq.fill(ratio) { WireInit(idata) }
val rdata = Reg(Vec(ratio-1, chiselTypeOf(idata)))
val pdata = rdata :+ idata
val mdata = (masked_enable zip (odata zip pdata)) map { case (e, (o, p)) => Mux(e, o, p) }
when (in.fire && !last) {
rdata_written_once := true.B
(rdata zip mdata) foreach { case (r, m) => r := m }
}
Cat(mdata.reverse)
}
in.ready := out.ready || !last
out.valid := in.valid && last
out.bits := in.bits
// Don't put down hardware if we never carry data
edgeOut.data(out.bits) := (if (edgeIn.staticHasData(in.bits) == Some(false)) 0.U else helper(edgeIn.data(in.bits)))
edgeOut.corrupt(out.bits) := corrupt_out
(out.bits, in.bits) match {
case (o: TLBundleA, i: TLBundleA) => o.mask := edgeOut.mask(o.address, o.size) & Mux(hasData, helper(i.mask), ~0.U(outBytes.W))
case (o: TLBundleB, i: TLBundleB) => o.mask := edgeOut.mask(o.address, o.size) & Mux(hasData, helper(i.mask), ~0.U(outBytes.W))
case (o: TLBundleC, i: TLBundleC) => ()
case (o: TLBundleD, i: TLBundleD) => ()
case _ => require(false, "Impossible bundle combination in WidthWidget")
}
}
def split[T <: TLDataChannel](edgeIn: TLEdge, in: DecoupledIO[T], edgeOut: TLEdge, out: DecoupledIO[T], sourceMap: UInt => UInt) = {
val inBytes = edgeIn.manager.beatBytes
val outBytes = edgeOut.manager.beatBytes
val ratio = inBytes / outBytes
val keepBits = log2Ceil(inBytes)
val dropBits = log2Ceil(outBytes)
val countBits = log2Ceil(ratio)
val size = edgeIn.size(in.bits)
val hasData = edgeIn.hasData(in.bits)
val limit = UIntToOH1(size, keepBits) >> dropBits
val count = RegInit(0.U(countBits.W))
val first = count === 0.U
val last = count === limit || !hasData
when (out.fire) {
count := count + 1.U
when (last) { count := 0.U }
}
// For sub-beat transfer, extract which part matters
val sel = in.bits match {
case a: TLBundleA => a.address(keepBits-1, dropBits)
case b: TLBundleB => b.address(keepBits-1, dropBits)
case c: TLBundleC => c.address(keepBits-1, dropBits)
case d: TLBundleD => {
val sel = sourceMap(d.source)
val hold = Mux(first, sel, RegEnable(sel, first)) // a_first is not for whole xfer
hold & ~limit // if more than one a_first/xfer, the address must be aligned anyway
}
}
val index = sel | count
def helper(idata: UInt, width: Int): UInt = {
val mux = VecInit.tabulate(ratio) { i => idata((i+1)*outBytes*width-1, i*outBytes*width) }
mux(index)
}
out.bits := in.bits
out.valid := in.valid
in.ready := out.ready
// Don't put down hardware if we never carry data
edgeOut.data(out.bits) := (if (edgeIn.staticHasData(in.bits) == Some(false)) 0.U else helper(edgeIn.data(in.bits), 8))
(out.bits, in.bits) match {
case (o: TLBundleA, i: TLBundleA) => o.mask := helper(i.mask, 1)
case (o: TLBundleB, i: TLBundleB) => o.mask := helper(i.mask, 1)
case (o: TLBundleC, i: TLBundleC) => () // replicating corrupt to all beats is ok
case (o: TLBundleD, i: TLBundleD) => ()
case _ => require(false, "Impossbile bundle combination in WidthWidget")
}
// Repeat the input if we're not last
!last
}
def splice[T <: TLDataChannel](edgeIn: TLEdge, in: DecoupledIO[T], edgeOut: TLEdge, out: DecoupledIO[T], sourceMap: UInt => UInt) = {
if (edgeIn.manager.beatBytes == edgeOut.manager.beatBytes) {
// nothing to do; pass it through
out.bits := in.bits
out.valid := in.valid
in.ready := out.ready
} else if (edgeIn.manager.beatBytes > edgeOut.manager.beatBytes) {
// split input to output
val repeat = Wire(Bool())
val repeated = Repeater(in, repeat)
val cated = Wire(chiselTypeOf(repeated))
cated <> repeated
edgeIn.data(cated.bits) := Cat(
edgeIn.data(repeated.bits)(edgeIn.manager.beatBytes*8-1, edgeOut.manager.beatBytes*8),
edgeIn.data(in.bits)(edgeOut.manager.beatBytes*8-1, 0))
repeat := split(edgeIn, cated, edgeOut, out, sourceMap)
} else {
// merge input to output
merge(edgeIn, in, edgeOut, out)
}
}
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
// If the master is narrower than the slave, the D channel must be narrowed.
// This is tricky, because the D channel has no address data.
// Thus, you don't know which part of a sub-beat transfer to extract.
// To fix this, we record the relevant address bits for all sources.
// The assumption is that this sort of situation happens only where
// you connect a narrow master to the system bus, so there are few sources.
def sourceMap(source_bits: UInt) = {
val source = if (edgeIn.client.endSourceId == 1) 0.U(0.W) else source_bits
require (edgeOut.manager.beatBytes > edgeIn.manager.beatBytes)
val keepBits = log2Ceil(edgeOut.manager.beatBytes)
val dropBits = log2Ceil(edgeIn.manager.beatBytes)
val sources = Reg(Vec(edgeIn.client.endSourceId, UInt((keepBits-dropBits).W)))
val a_sel = in.a.bits.address(keepBits-1, dropBits)
when (in.a.fire) {
if (edgeIn.client.endSourceId == 1) { // avoid extraction-index-width warning
sources(0) := a_sel
} else {
sources(in.a.bits.source) := a_sel
}
}
// depopulate unused source registers:
edgeIn.client.unusedSources.foreach { id => sources(id) := 0.U }
val bypass = in.a.valid && in.a.bits.source === source
if (edgeIn.manager.minLatency > 0) sources(source)
else Mux(bypass, a_sel, sources(source))
}
splice(edgeIn, in.a, edgeOut, out.a, sourceMap)
splice(edgeOut, out.d, edgeIn, in.d, sourceMap)
if (edgeOut.manager.anySupportAcquireB && edgeIn.client.anySupportProbe) {
splice(edgeOut, out.b, edgeIn, in.b, sourceMap)
splice(edgeIn, in.c, edgeOut, out.c, sourceMap)
out.e.valid := in.e.valid
out.e.bits := in.e.bits
in.e.ready := out.e.ready
} else {
in.b.valid := false.B
in.c.ready := true.B
in.e.ready := true.B
out.b.ready := true.B
out.c.valid := false.B
out.e.valid := false.B
}
}
}
}
object TLWidthWidget
{
def apply(innerBeatBytes: Int)(implicit p: Parameters): TLNode =
{
val widget = LazyModule(new TLWidthWidget(innerBeatBytes))
widget.node
}
def apply(wrapper: TLBusWrapper)(implicit p: Parameters): TLNode = apply(wrapper.beatBytes)
}
// Synthesizable unit tests
import freechips.rocketchip.unittest._
class TLRAMWidthWidget(first: Int, second: Int, txns: Int)(implicit p: Parameters) extends LazyModule {
val fuzz = LazyModule(new TLFuzzer(txns))
val model = LazyModule(new TLRAMModel("WidthWidget"))
val ram = LazyModule(new TLRAM(AddressSet(0x0, 0x3ff)))
(ram.node
:= TLDelayer(0.1)
:= TLFragmenter(4, 256)
:= TLWidthWidget(second)
:= TLWidthWidget(first)
:= TLDelayer(0.1)
:= model.node
:= fuzz.node)
lazy val module = new Impl
class Impl extends LazyModuleImp(this) with UnitTestModule {
io.finished := fuzz.module.io.finished
}
}
class TLRAMWidthWidgetTest(little: Int, big: Int, txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) {
val dut = Module(LazyModule(new TLRAMWidthWidget(little,big,txns)).module)
dut.io.start := DontCare
io.finished := dut.io.finished
}
File LazyModuleImp.scala:
package org.chipsalliance.diplomacy.lazymodule
import chisel3.{withClockAndReset, Module, RawModule, Reset, _}
import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo}
import firrtl.passes.InlineAnnotation
import org.chipsalliance.cde.config.Parameters
import org.chipsalliance.diplomacy.nodes.Dangle
import scala.collection.immutable.SortedMap
/** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]].
*
* This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy.
*/
sealed trait LazyModuleImpLike extends RawModule {
/** [[LazyModule]] that contains this instance. */
val wrapper: LazyModule
/** IOs that will be automatically "punched" for this instance. */
val auto: AutoBundle
/** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */
protected[diplomacy] val dangles: Seq[Dangle]
// [[wrapper.module]] had better not be accessed while LazyModules are still being built!
require(
LazyModule.scope.isEmpty,
s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}"
)
/** Set module name. Defaults to the containing LazyModule's desiredName. */
override def desiredName: String = wrapper.desiredName
suggestName(wrapper.suggestedName)
/** [[Parameters]] for chisel [[Module]]s. */
implicit val p: Parameters = wrapper.p
/** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and
* submodules.
*/
protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = {
// 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]],
// 2. return [[Dangle]]s from each module.
val childDangles = wrapper.children.reverse.flatMap { c =>
implicit val sourceInfo: SourceInfo = c.info
c.cloneProto.map { cp =>
// If the child is a clone, then recursively set cloneProto of its children as well
def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = {
require(bases.size == clones.size)
(bases.zip(clones)).map { case (l, r) =>
require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}")
l.cloneProto = Some(r)
assignCloneProtos(l.children, r.children)
}
}
assignCloneProtos(c.children, cp.children)
// Clone the child module as a record, and get its [[AutoBundle]]
val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName)
val clonedAuto = clone("auto").asInstanceOf[AutoBundle]
// Get the empty [[Dangle]]'s of the cloned child
val rawDangles = c.cloneDangles()
require(rawDangles.size == clonedAuto.elements.size)
// Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s
val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) }
dangles
}.getOrElse {
// For non-clones, instantiate the child module
val mod = try {
Module(c.module)
} catch {
case e: ChiselException => {
println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}")
throw e
}
}
mod.dangles
}
}
// Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]].
// This will result in a sequence of [[Dangle]] from these [[BaseNode]]s.
val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate())
// Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]]
val allDangles = nodeDangles ++ childDangles
// Group [[allDangles]] by their [[source]].
val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*)
// For each [[source]] set of [[Dangle]]s of size 2, ensure that these
// can be connected as a source-sink pair (have opposite flipped value).
// Make the connection and mark them as [[done]].
val done = Set() ++ pairing.values.filter(_.size == 2).map {
case Seq(a, b) =>
require(a.flipped != b.flipped)
// @todo <> in chisel3 makes directionless connection.
if (a.flipped) {
a.data <> b.data
} else {
b.data <> a.data
}
a.source
case _ => None
}
// Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module.
val forward = allDangles.filter(d => !done(d.source))
// Generate [[AutoBundle]] IO from [[forward]].
val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*))
// Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]]
val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) =>
if (d.flipped) {
d.data <> io
} else {
io <> d.data
}
d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name)
}
// Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]].
wrapper.inModuleBody.reverse.foreach {
_()
}
if (wrapper.shouldBeInlined) {
chisel3.experimental.annotate(new ChiselAnnotation {
def toFirrtl = InlineAnnotation(toNamed)
})
}
// Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]].
(auto, dangles)
}
}
/** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike {
/** Instantiate hardware of this `Module`. */
val (auto, dangles) = instantiate()
}
/** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike {
// These wires are the default clock+reset for all LazyModule children.
// It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the
// [[LazyRawModuleImp]] children.
// Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly.
/** drive clock explicitly. */
val childClock: Clock = Wire(Clock())
/** drive reset explicitly. */
val childReset: Reset = Wire(Reset())
// the default is that these are disabled
childClock := false.B.asClock
childReset := chisel3.DontCare
def provideImplicitClockToLazyChildren: Boolean = false
val (auto, dangles) =
if (provideImplicitClockToLazyChildren) {
withClockAndReset(childClock, childReset) { instantiate() }
} else {
instantiate()
}
}
File Parameters.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.diplomacy
import chisel3._
import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor}
import freechips.rocketchip.util.ShiftQueue
/** Options for describing the attributes of memory regions */
object RegionType {
// Define the 'more relaxed than' ordering
val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS)
sealed trait T extends Ordered[T] {
def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this)
}
case object CACHED extends T // an intermediate agent may have cached a copy of the region for you
case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided
case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible
case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached
case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects
case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed
case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively
}
// A non-empty half-open range; [start, end)
case class IdRange(start: Int, end: Int) extends Ordered[IdRange]
{
require (start >= 0, s"Ids cannot be negative, but got: $start.")
require (start <= end, "Id ranges cannot be negative.")
def compare(x: IdRange) = {
val primary = (this.start - x.start).signum
val secondary = (x.end - this.end).signum
if (primary != 0) primary else secondary
}
def overlaps(x: IdRange) = start < x.end && x.start < end
def contains(x: IdRange) = start <= x.start && x.end <= end
def contains(x: Int) = start <= x && x < end
def contains(x: UInt) =
if (size == 0) {
false.B
} else if (size == 1) { // simple comparison
x === start.U
} else {
// find index of largest different bit
val largestDeltaBit = log2Floor(start ^ (end-1))
val smallestCommonBit = largestDeltaBit + 1 // may not exist in x
val uncommonMask = (1 << smallestCommonBit) - 1
val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0)
// the prefix must match exactly (note: may shift ALL bits away)
(x >> smallestCommonBit) === (start >> smallestCommonBit).U &&
// firrtl constant prop range analysis can eliminate these two:
(start & uncommonMask).U <= uncommonBits &&
uncommonBits <= ((end-1) & uncommonMask).U
}
def shift(x: Int) = IdRange(start+x, end+x)
def size = end - start
def isEmpty = end == start
def range = start until end
}
object IdRange
{
def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else {
val ranges = s.sorted
(ranges.tail zip ranges.init) find { case (a, b) => a overlaps b }
}
}
// An potentially empty inclusive range of 2-powers [min, max] (in bytes)
case class TransferSizes(min: Int, max: Int)
{
def this(x: Int) = this(x, x)
require (min <= max, s"Min transfer $min > max transfer $max")
require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)")
require (max == 0 || isPow2(max), s"TransferSizes must be a power of 2, got: $max")
require (min == 0 || isPow2(min), s"TransferSizes must be a power of 2, got: $min")
require (max == 0 || min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)")
def none = min == 0
def contains(x: Int) = isPow2(x) && min <= x && x <= max
def containsLg(x: Int) = contains(1 << x)
def containsLg(x: UInt) =
if (none) false.B
else if (min == max) { log2Ceil(min).U === x }
else { log2Ceil(min).U <= x && x <= log2Ceil(max).U }
def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max)
def intersect(x: TransferSizes) =
if (x.max < min || max < x.min) TransferSizes.none
else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max))
// Not a union, because the result may contain sizes contained by neither term
// NOT TO BE CONFUSED WITH COVERPOINTS
def mincover(x: TransferSizes) = {
if (none) {
x
} else if (x.none) {
this
} else {
TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max))
}
}
override def toString() = "TransferSizes[%d, %d]".format(min, max)
}
object TransferSizes {
def apply(x: Int) = new TransferSizes(x)
val none = new TransferSizes(0)
def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _)
def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _)
implicit def asBool(x: TransferSizes) = !x.none
}
// AddressSets specify the address space managed by the manager
// Base is the base address, and mask are the bits consumed by the manager
// e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff
// e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ...
case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet]
{
// Forbid misaligned base address (and empty sets)
require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}")
require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous
// We do allow negative mask (=> ignore all high bits)
def contains(x: BigInt) = ((x ^ base) & ~mask) == 0
def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S
// turn x into an address contained in this set
def legalize(x: UInt): UInt = base.U | (mask.U & x)
// overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1)
def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0
// contains iff bitwise: x.mask => mask && contains(x.base)
def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0
// The number of bytes to which the manager must be aligned
def alignment = ((mask + 1) & ~mask)
// Is this a contiguous memory range
def contiguous = alignment == mask+1
def finite = mask >= 0
def max = { require (finite, "Max cannot be calculated on infinite mask"); base | mask }
// Widen the match function to ignore all bits in imask
def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask)
// Return an AddressSet that only contains the addresses both sets contain
def intersect(x: AddressSet): Option[AddressSet] = {
if (!overlaps(x)) {
None
} else {
val r_mask = mask & x.mask
val r_base = base | x.base
Some(AddressSet(r_base, r_mask))
}
}
def subtract(x: AddressSet): Seq[AddressSet] = {
intersect(x) match {
case None => Seq(this)
case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit =>
val nmask = (mask & (bit-1)) | remove.mask
val nbase = (remove.base ^ bit) & ~nmask
AddressSet(nbase, nmask)
}
}
}
// AddressSets have one natural Ordering (the containment order, if contiguous)
def compare(x: AddressSet) = {
val primary = (this.base - x.base).signum // smallest address first
val secondary = (x.mask - this.mask).signum // largest mask first
if (primary != 0) primary else secondary
}
// We always want to see things in hex
override def toString() = {
if (mask >= 0) {
"AddressSet(0x%x, 0x%x)".format(base, mask)
} else {
"AddressSet(0x%x, ~0x%x)".format(base, ~mask)
}
}
def toRanges = {
require (finite, "Ranges cannot be calculated on infinite mask")
val size = alignment
val fragments = mask & ~(size-1)
val bits = bitIndexes(fragments)
(BigInt(0) until (BigInt(1) << bits.size)).map { i =>
val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) }
AddressRange(off, size)
}
}
}
object AddressSet
{
val everything = AddressSet(0, -1)
def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = {
if (size == 0) tail.reverse else {
val maxBaseAlignment = base & (-base) // 0 for infinite (LSB)
val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size
val step =
if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment)
maxSizeAlignment else maxBaseAlignment
misaligned(base+step, size-step, AddressSet(base, step-1) +: tail)
}
}
def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = {
// Pair terms up by ignoring 'bit'
seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) =>
if (seq.size == 1) {
seq.head // singleton -> unaffected
} else {
key.copy(mask = key.mask | bit) // pair - widen mask by bit
}
}.toList
}
def unify(seq: Seq[AddressSet]): Seq[AddressSet] = {
val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _)
AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted
}
def enumerateMask(mask: BigInt): Seq[BigInt] = {
def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] =
if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail)
helper(0, Nil)
}
def enumerateBits(mask: BigInt): Seq[BigInt] = {
def helper(x: BigInt): Seq[BigInt] = {
if (x == 0) {
Nil
} else {
val bit = x & (-x)
bit +: helper(x & ~bit)
}
}
helper(mask)
}
}
case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean)
{
require (depth >= 0, "Buffer depth must be >= 0")
def isDefined = depth > 0
def latency = if (isDefined && !flow) 1 else 0
def apply[T <: Data](x: DecoupledIO[T]) =
if (isDefined) Queue(x, depth, flow=flow, pipe=pipe)
else x
def irrevocable[T <: Data](x: ReadyValidIO[T]) =
if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe)
else x
def sq[T <: Data](x: DecoupledIO[T]) =
if (!isDefined) x else {
val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe))
sq.io.enq <> x
sq.io.deq
}
override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "")
}
object BufferParams
{
implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false)
val default = BufferParams(2)
val none = BufferParams(0)
val flow = BufferParams(1, true, false)
val pipe = BufferParams(1, false, true)
}
case class TriStateValue(value: Boolean, set: Boolean)
{
def update(orig: Boolean) = if (set) value else orig
}
object TriStateValue
{
implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true)
def unset = TriStateValue(false, false)
}
trait DirectedBuffers[T] {
def copyIn(x: BufferParams): T
def copyOut(x: BufferParams): T
def copyInOut(x: BufferParams): T
}
trait IdMapEntry {
def name: String
def from: IdRange
def to: IdRange
def isCache: Boolean
def requestFifo: Boolean
def maxTransactionsInFlight: Option[Int]
def pretty(fmt: String) =
if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5
fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "")
} else {
fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "")
}
}
abstract class IdMap[T <: IdMapEntry] {
protected val fmt: String
val mapping: Seq[T]
def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n")
}
File Configs.scala:
/*
* Copyright 2019 SiFive, Inc.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You should have received a copy of LICENSE.Apache2 along with
* this software. If not, you may obtain a copy at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
package freechips.rocketchip.subsystem
import org.chipsalliance.cde.config._
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.tile._
import freechips.rocketchip.rocket._
import freechips.rocketchip.tilelink._
import sifive.blocks.inclusivecache._
import freechips.rocketchip.devices.tilelink._
import freechips.rocketchip.util._
import sifive.blocks.inclusivecache.InclusiveCacheParameters
case class InclusiveCacheParams(
ways: Int,
sets: Int,
writeBytes: Int, // backing store update granularity
portFactor: Int, // numSubBanks = (widest TL port * portFactor) / writeBytes
memCycles: Int, // # of L2 clock cycles for a memory round-trip (50ns @ 800MHz)
physicalFilter: Option[PhysicalFilterParams] = None,
hintsSkipProbe: Boolean = false, // do hints probe the same client
bankedControl: Boolean = false, // bank the cache ctrl with the cache banks
ctrlAddr: Option[Int] = Some(InclusiveCacheParameters.L2ControlAddress),
// Interior/Exterior refer to placement either inside the Scheduler or outside it
// Inner/Outer refer to buffers on the front (towards cores) or back (towards DDR) of the L2
bufInnerInterior: InclusiveCachePortParameters = InclusiveCachePortParameters.fullC,
bufInnerExterior: InclusiveCachePortParameters = InclusiveCachePortParameters.flowAD,
bufOuterInterior: InclusiveCachePortParameters = InclusiveCachePortParameters.full,
bufOuterExterior: InclusiveCachePortParameters = InclusiveCachePortParameters.none)
case object InclusiveCacheKey extends Field[InclusiveCacheParams]
class WithInclusiveCache(
nWays: Int = 8,
capacityKB: Int = 512,
outerLatencyCycles: Int = 40,
subBankingFactor: Int = 4,
hintsSkipProbe: Boolean = false,
bankedControl: Boolean = false,
ctrlAddr: Option[Int] = Some(InclusiveCacheParameters.L2ControlAddress),
writeBytes: Int = 8
) extends Config((site, here, up) => {
case InclusiveCacheKey => InclusiveCacheParams(
sets = (capacityKB * 1024)/(site(CacheBlockBytes) * nWays * up(SubsystemBankedCoherenceKey, site).nBanks),
ways = nWays,
memCycles = outerLatencyCycles,
writeBytes = writeBytes,
portFactor = subBankingFactor,
hintsSkipProbe = hintsSkipProbe,
bankedControl = bankedControl,
ctrlAddr = ctrlAddr)
case SubsystemBankedCoherenceKey => up(SubsystemBankedCoherenceKey, site).copy(coherenceManager = { context =>
implicit val p = context.p
val sbus = context.tlBusWrapperLocationMap(SBUS)
val cbus = context.tlBusWrapperLocationMap.lift(CBUS).getOrElse(sbus)
val InclusiveCacheParams(
ways,
sets,
writeBytes,
portFactor,
memCycles,
physicalFilter,
hintsSkipProbe,
bankedControl,
ctrlAddr,
bufInnerInterior,
bufInnerExterior,
bufOuterInterior,
bufOuterExterior) = p(InclusiveCacheKey)
val l2Ctrl = ctrlAddr.map { addr =>
InclusiveCacheControlParameters(
address = addr,
beatBytes = cbus.beatBytes,
bankedControl = bankedControl)
}
val l2 = LazyModule(new InclusiveCache(
CacheParameters(
level = 2,
ways = ways,
sets = sets,
blockBytes = sbus.blockBytes,
beatBytes = sbus.beatBytes,
hintsSkipProbe = hintsSkipProbe),
InclusiveCacheMicroParameters(
writeBytes = writeBytes,
portFactor = portFactor,
memCycles = memCycles,
innerBuf = bufInnerInterior,
outerBuf = bufOuterInterior),
l2Ctrl))
def skipMMIO(x: TLClientParameters) = {
val dcacheMMIO =
x.requestFifo &&
x.sourceId.start % 2 == 1 && // 1 => dcache issues acquires from another master
x.nodePath.last.name == "dcache.node"
if (dcacheMMIO) None else Some(x)
}
val filter = LazyModule(new TLFilter(cfilter = skipMMIO))
val l2_inner_buffer = bufInnerExterior()
val l2_outer_buffer = bufOuterExterior()
val cork = LazyModule(new TLCacheCork)
val lastLevelNode = cork.node
l2_inner_buffer.suggestName("InclusiveCache_inner_TLBuffer")
l2_outer_buffer.suggestName("InclusiveCache_outer_TLBuffer")
l2_inner_buffer.node :*= filter.node
l2.node :*= l2_inner_buffer.node
l2_outer_buffer.node :*= l2.node
/* PhysicalFilters need to be on the TL-C side of a CacheCork to prevent Acquire.NtoB -> Grant.toT */
physicalFilter match {
case None => lastLevelNode :*= l2_outer_buffer.node
case Some(fp) => {
val physicalFilter = LazyModule(new PhysicalFilter(fp.copy(controlBeatBytes = cbus.beatBytes)))
lastLevelNode :*= physicalFilter.node :*= l2_outer_buffer.node
physicalFilter.controlNode := cbus.coupleTo("physical_filter") {
TLBuffer(1) := TLFragmenter(cbus, Some("LLCPhysicalFilter")) := _
}
}
}
l2.ctrls.foreach {
_.ctrlnode := cbus.coupleTo("l2_ctrl") { TLBuffer(1) := TLFragmenter(cbus, Some("LLCCtrl")) := _ }
}
ElaborationArtefacts.add("l2.json", l2.module.json)
(filter.node, lastLevelNode, None)
})
})
File MixedNode.scala:
package org.chipsalliance.diplomacy.nodes
import chisel3.{Data, DontCare, Wire}
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.{Field, Parameters}
import org.chipsalliance.diplomacy.ValName
import org.chipsalliance.diplomacy.sourceLine
/** One side metadata of a [[Dangle]].
*
* Describes one side of an edge going into or out of a [[BaseNode]].
*
* @param serial
* the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to.
* @param index
* the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to.
*/
case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] {
import scala.math.Ordered.orderingToOrdered
def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that))
}
/** [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]]
* connects.
*
* [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] ,
* [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]].
*
* @param source
* the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within
* that [[BaseNode]].
* @param sink
* sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that
* [[BaseNode]].
* @param flipped
* flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to
* `danglesIn`.
* @param dataOpt
* actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module
*/
case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) {
def data = dataOpt.get
}
/** [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often
* derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually
* implement the protocol.
*/
case class Edges[EI, EO](in: Seq[EI], out: Seq[EO])
/** A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. */
case object MonitorsEnabled extends Field[Boolean](true)
/** When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented.
*
* For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but
* [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink
* nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the
* [[LazyModule]].
*/
case object RenderFlipped extends Field[Boolean](false)
/** The sealed node class in the package, all node are derived from it.
*
* @param inner
* Sink interface implementation.
* @param outer
* Source interface implementation.
* @param valName
* val name of this node.
* @tparam DI
* Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters
* describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected
* [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port
* parameters.
* @tparam UI
* Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing
* the protocol parameters of a sink. For an [[InwardNode]], it is determined itself.
* @tparam EI
* Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers
* specified for a sink according to protocol.
* @tparam BI
* Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface.
* It should extends from [[chisel3.Data]], which represents the real hardware.
* @tparam DO
* Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters
* describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself.
* @tparam UO
* Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing
* the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]].
* Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters.
* @tparam EO
* Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers
* specified for a source according to protocol.
* @tparam BO
* Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source
* interface. It should extends from [[chisel3.Data]], which represents the real hardware.
*
* @note
* Call Graph of [[MixedNode]]
* - line `─`: source is process by a function and generate pass to others
* - Arrow `→`: target of arrow is generated by source
*
* {{{
* (from the other node)
* ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐
* ↓ │
* (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │
* [[InwardNode.accPI]] │ │ │
* │ │ (based on protocol) │
* │ │ [[MixedNode.inner.edgeI]] │
* │ │ ↓ │
* ↓ │ │ │
* (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │
* [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │
* │ │ ↑ │ │ │
* │ │ │ [[OutwardNode.doParams]] │ │
* │ │ │ (from the other node) │ │
* │ │ │ │ │ │
* │ │ │ │ │ │
* │ │ │ └────────┬──────────────┤ │
* │ │ │ │ │ │
* │ │ │ │ (based on protocol) │
* │ │ │ │ [[MixedNode.inner.edgeI]] │
* │ │ │ │ │ │
* │ │ (from the other node) │ ↓ │
* │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │
* │ ↑ ↑ │ │ ↓ │
* │ │ │ │ │ [[MixedNode.in]] │
* │ │ │ │ ↓ ↑ │
* │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │
* ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │
* │ │ │ [[MixedNode.bundleOut]]─┐ │ │
* │ │ │ ↑ ↓ │ │
* │ │ │ │ [[MixedNode.out]] │ │
* │ ↓ ↓ │ ↑ │ │
* │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │
* │ │ (from the other node) ↑ │ │
* │ │ │ │ │ │
* │ │ │ [[MixedNode.outer.edgeO]] │ │
* │ │ │ (based on protocol) │ │
* │ │ │ │ │ │
* │ │ │ ┌────────────────────────────────────────┤ │ │
* │ │ │ │ │ │ │
* │ │ │ │ │ │ │
* │ │ │ │ │ │ │
* (immobilize after elaboration)│ ↓ │ │ │ │
* [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │
* ↑ (inward port from [[OutwardNode]]) │ │ │ │
* │ ┌─────────────────────────────────────────┤ │ │ │
* │ │ │ │ │ │
* │ │ │ │ │ │
* [[OutwardNode.accPO]] │ ↓ │ │ │
* (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │
* │ ↑ │ │
* │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │
* └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘
* }}}
*/
abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data](
val inner: InwardNodeImp[DI, UI, EI, BI],
val outer: OutwardNodeImp[DO, UO, EO, BO]
)(
implicit valName: ValName)
extends BaseNode
with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO]
with InwardNode[DI, UI, BI]
with OutwardNode[DO, UO, BO] {
// Generate a [[NodeHandle]] with inward and outward node are both this node.
val inward = this
val outward = this
/** Debug info of nodes binding. */
def bindingInfo: String = s"""$iBindingInfo
|$oBindingInfo
|""".stripMargin
/** Debug info of ports connecting. */
def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}]
|${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}]
|""".stripMargin
/** Debug info of parameters propagations. */
def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}]
|${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}]
|${diParams.size} downstream inward parameters: [${diParams.mkString(",")}]
|${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}]
|""".stripMargin
/** For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and
* [[MixedNode.iPortMapping]].
*
* Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward
* stars and outward stars.
*
* This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type
* of node.
*
* @param iKnown
* Number of known-size ([[BIND_ONCE]]) input bindings.
* @param oKnown
* Number of known-size ([[BIND_ONCE]]) output bindings.
* @param iStar
* Number of unknown size ([[BIND_STAR]]) input bindings.
* @param oStar
* Number of unknown size ([[BIND_STAR]]) output bindings.
* @return
* A Tuple of the resolved number of input and output connections.
*/
protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int)
/** Function to generate downward-flowing outward params from the downward-flowing input params and the current output
* ports.
*
* @param n
* The size of the output sequence to generate.
* @param p
* Sequence of downward-flowing input parameters of this node.
* @return
* A `n`-sized sequence of downward-flowing output edge parameters.
*/
protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO]
/** Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]].
*
* @param n
* Size of the output sequence.
* @param p
* Upward-flowing output edge parameters.
* @return
* A n-sized sequence of upward-flowing input edge parameters.
*/
protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI]
/** @return
* The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with
* [[BIND_STAR]].
*/
protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR)
/** @return
* The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of
* output bindings bound with [[BIND_STAR]].
*/
protected[diplomacy] lazy val sourceCard: Int =
iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR)
/** @return list of nodes involved in flex bindings with this node. */
protected[diplomacy] lazy val flexes: Seq[BaseNode] =
oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2)
/** Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin
* greedily taking up the remaining connections.
*
* @return
* A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return
* value is not relevant.
*/
protected[diplomacy] lazy val flexOffset: Int = {
/** Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex
* operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a
* connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of
* each node in the current set and decide whether they should be added to the set or not.
*
* @return
* the mapping of [[BaseNode]] indexed by their serial numbers.
*/
def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = {
if (visited.contains(v.serial) || !v.flexibleArityDirection) {
visited
} else {
v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum))
}
}
/** Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node.
*
* @example
* {{{
* a :*=* b :*=* c
* d :*=* b
* e :*=* f
* }}}
*
* `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)`
*/
val flexSet = DFS(this, Map()).values
/** The total number of :*= operators where we're on the left. */
val allSink = flexSet.map(_.sinkCard).sum
/** The total number of :=* operators used when we're on the right. */
val allSource = flexSet.map(_.sourceCard).sum
require(
allSink == 0 || allSource == 0,
s"The nodes ${flexSet.map(_.name)} which are inter-connected by :*=* have ${allSink} :*= operators and ${allSource} :=* operators connected to them, making it impossible to determine cardinality inference direction."
)
allSink - allSource
}
/** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. */
protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = {
if (flexibleArityDirection) flexOffset
else if (n.flexibleArityDirection) n.flexOffset
else 0
}
/** For a node which is connected between two nodes, select the one that will influence the direction of the flex
* resolution.
*/
protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = {
val dir = edgeArityDirection(n)
if (dir < 0) l
else if (dir > 0) r
else 1
}
/** Ensure that the same node is not visited twice in resolving `:*=`, etc operators. */
private var starCycleGuard = false
/** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star"
* connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also
* need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct
* edge parameters and later build up correct bundle connections.
*
* [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding
* operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort
* (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N :*= foo` or `N :*=* foo :*=
* bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo :*=* N`
*/
protected[diplomacy] lazy val (
oPortMapping: Seq[(Int, Int)],
iPortMapping: Seq[(Int, Int)],
oStar: Int,
iStar: Int
) = {
try {
if (starCycleGuard) throw StarCycleException()
starCycleGuard = true
// For a given node N...
// Number of foo :=* N
// + Number of bar :=* foo :*=* N
val oStars = oBindings.count { case (_, n, b, _, _) =>
b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) < 0)
}
// Number of N :*= foo
// + Number of N :*=* foo :*= bar
val iStars = iBindings.count { case (_, n, b, _, _) =>
b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) > 0)
}
// 1 for foo := N
// + bar.iStar for bar :*= foo :*=* N
// + foo.iStar for foo :*= N
// + 0 for foo :=* N
val oKnown = oBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, 0, n.iStar)
case BIND_QUERY => n.iStar
case BIND_STAR => 0
}
}.sum
// 1 for N := foo
// + bar.oStar for N :*=* foo :=* bar
// + foo.oStar for N :=* foo
// + 0 for N :*= foo
val iKnown = iBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, n.oStar, 0)
case BIND_QUERY => n.oStar
case BIND_STAR => 0
}
}.sum
// Resolve star depends on the node subclass to implement the algorithm for this.
val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars)
// Cumulative list of resolved outward binding range starting points
val oSum = oBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar)
case BIND_QUERY => n.iStar
case BIND_STAR => oStar
}
}.scanLeft(0)(_ + _)
// Cumulative list of resolved inward binding range starting points
val iSum = iBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar)
case BIND_QUERY => n.oStar
case BIND_STAR => iStar
}
}.scanLeft(0)(_ + _)
// Create ranges for each binding based on the running sums and return
// those along with resolved values for the star operations.
(oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar)
} catch {
case c: StarCycleException => throw c.copy(loop = context +: c.loop)
}
}
/** Sequence of inward ports.
*
* This should be called after all star bindings are resolved.
*
* Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding.
* `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this
* connection was made in the source code.
*/
protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] =
oBindings.flatMap { case (i, n, _, p, s) =>
// for each binding operator in this node, look at what it connects to
val (start, end) = n.iPortMapping(i)
(start until end).map { j => (j, n, p, s) }
}
/** Sequence of outward ports.
*
* This should be called after all star bindings are resolved.
*
* `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of
* outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection
* was made in the source code.
*/
protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] =
iBindings.flatMap { case (i, n, _, p, s) =>
// query this port index range of this node in the other side of node.
val (start, end) = n.oPortMapping(i)
(start until end).map { j => (j, n, p, s) }
}
// Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree
// Thus, there must exist an Eulerian path and the below algorithms terminate
@scala.annotation.tailrec
private def oTrace(
tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)
): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match {
case (i, n, p, s) => n.iForward(i) match {
case None => (i, n, p, s)
case Some((j, m)) => oTrace((j, m, p, s))
}
}
@scala.annotation.tailrec
private def iTrace(
tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)
): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match {
case (i, n, p, s) => n.oForward(i) match {
case None => (i, n, p, s)
case Some((j, m)) => iTrace((j, m, p, s))
}
}
/** Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved.
*
* Each Port is a tuple of:
* - Numeric index of this binding in the [[InwardNode]] on the other end.
* - [[InwardNode]] on the other end of this binding.
* - A view of [[Parameters]] where the binding occurred.
* - [[SourceInfo]] for source-level error reporting.
*/
lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace)
/** Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved.
*
* Each Port is a tuple of:
* - numeric index of this binding in [[OutwardNode]] on the other end.
* - [[OutwardNode]] on the other end of this binding.
* - a view of [[Parameters]] where the binding occurred.
* - [[SourceInfo]] for source-level error reporting.
*/
lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace)
private var oParamsCycleGuard = false
protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) }
protected[diplomacy] lazy val doParams: Seq[DO] = {
try {
if (oParamsCycleGuard) throw DownwardCycleException()
oParamsCycleGuard = true
val o = mapParamsD(oPorts.size, diParams)
require(
o.size == oPorts.size,
s"""Diplomacy has detected a problem with your graph:
|At the following node, the number of outward ports should equal the number of produced outward parameters.
|$context
|$connectedPortsInfo
|Downstreamed inward parameters: [${diParams.mkString(",")}]
|Produced outward parameters: [${o.mkString(",")}]
|""".stripMargin
)
o.map(outer.mixO(_, this))
} catch {
case c: DownwardCycleException => throw c.copy(loop = context +: c.loop)
}
}
private var iParamsCycleGuard = false
protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) }
protected[diplomacy] lazy val uiParams: Seq[UI] = {
try {
if (iParamsCycleGuard) throw UpwardCycleException()
iParamsCycleGuard = true
val i = mapParamsU(iPorts.size, uoParams)
require(
i.size == iPorts.size,
s"""Diplomacy has detected a problem with your graph:
|At the following node, the number of inward ports should equal the number of produced inward parameters.
|$context
|$connectedPortsInfo
|Upstreamed outward parameters: [${uoParams.mkString(",")}]
|Produced inward parameters: [${i.mkString(",")}]
|""".stripMargin
)
i.map(inner.mixI(_, this))
} catch {
case c: UpwardCycleException => throw c.copy(loop = context +: c.loop)
}
}
/** Outward edge parameters. */
protected[diplomacy] lazy val edgesOut: Seq[EO] =
(oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) }
/** Inward edge parameters. */
protected[diplomacy] lazy val edgesIn: Seq[EI] =
(iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) }
/** A tuple of the input edge parameters and output edge parameters for the edges bound to this node.
*
* If you need to access to the edges of a foreign Node, use this method (in/out create bundles).
*/
lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut)
/** Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. */
protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e =>
val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out")
// TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue,
// In the future, we should add an option to decide whether allowing unconnected in the LazyModule
x := DontCare
x
}
/** Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. */
protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e =>
val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In")
// TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue,
// In the future, we should add an option to decide whether allowing unconnected in the LazyModule
x := DontCare
x
}
private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) =>
Dangle(
source = HalfEdge(serial, i),
sink = HalfEdge(n.serial, j),
flipped = false,
name = wirePrefix + "out",
dataOpt = None
)
}
private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) =>
Dangle(
source = HalfEdge(n.serial, j),
sink = HalfEdge(serial, i),
flipped = true,
name = wirePrefix + "in",
dataOpt = None
)
}
/** Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. */
protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) =>
d.copy(dataOpt = Some(bundleOut(i)))
}
/** Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. */
protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) =>
d.copy(dataOpt = Some(bundleIn(i)))
}
private[diplomacy] var instantiated = false
/** Gather Bundle and edge parameters of outward ports.
*
* Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within
* [[LazyModuleImp]] code or after its instantiation has completed.
*/
def out: Seq[(BO, EO)] = {
require(
instantiated,
s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun"
)
bundleOut.zip(edgesOut)
}
/** Gather Bundle and edge parameters of inward ports.
*
* Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within
* [[LazyModuleImp]] code or after its instantiation has completed.
*/
def in: Seq[(BI, EI)] = {
require(
instantiated,
s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun"
)
bundleIn.zip(edgesIn)
}
/** Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires,
* instantiate monitors on all input ports if appropriate, and return all the dangles of this node.
*/
protected[diplomacy] def instantiate(): Seq[Dangle] = {
instantiated = true
if (!circuitIdentity) {
(iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) }
}
danglesOut ++ danglesIn
}
protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn
/** Connects the outward part of a node with the inward part of this node. */
protected[diplomacy] def bind(
h: OutwardNode[DI, UI, BI],
binding: NodeBinding
)(
implicit p: Parameters,
sourceInfo: SourceInfo
): Unit = {
val x = this // x := y
val y = h
sourceLine(sourceInfo, " at ", "")
val i = x.iPushed
val o = y.oPushed
y.oPush(
i,
x,
binding match {
case BIND_ONCE => BIND_ONCE
case BIND_FLEX => BIND_FLEX
case BIND_STAR => BIND_QUERY
case BIND_QUERY => BIND_STAR
}
)
x.iPush(o, y, binding)
}
/* Metadata for printing the node graph. */
def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) =>
val re = inner.render(e)
(n, re.copy(flipped = re.flipped != p(RenderFlipped)))
}
/** Metadata for printing the node graph */
def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) }
}
File Edges.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.util._
class TLEdge(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdgeParameters(client, manager, params, sourceInfo)
{
def isAligned(address: UInt, lgSize: UInt): Bool = {
if (maxLgSize == 0) true.B else {
val mask = UIntToOH1(lgSize, maxLgSize)
(address & mask) === 0.U
}
}
def mask(address: UInt, lgSize: UInt): UInt =
MaskGen(address, lgSize, manager.beatBytes)
def staticHasData(bundle: TLChannel): Option[Boolean] = {
bundle match {
case _:TLBundleA => {
// Do there exist A messages with Data?
val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial
// Do there exist A messages without Data?
val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint
// Statically optimize the case where hasData is a constant
if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None
}
case _:TLBundleB => {
// Do there exist B messages with Data?
val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial
// Do there exist B messages without Data?
val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint
// Statically optimize the case where hasData is a constant
if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None
}
case _:TLBundleC => {
// Do there eixst C messages with Data?
val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe
// Do there exist C messages without Data?
val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe
if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None
}
case _:TLBundleD => {
// Do there eixst D messages with Data?
val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB
// Do there exist D messages without Data?
val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT
if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None
}
case _:TLBundleE => Some(false)
}
}
def isRequest(x: TLChannel): Bool = {
x match {
case a: TLBundleA => true.B
case b: TLBundleB => true.B
case c: TLBundleC => c.opcode(2) && c.opcode(1)
// opcode === TLMessages.Release ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(2) && !d.opcode(1)
// opcode === TLMessages.Grant ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
}
def isResponse(x: TLChannel): Bool = {
x match {
case a: TLBundleA => false.B
case b: TLBundleB => false.B
case c: TLBundleC => !c.opcode(2) || !c.opcode(1)
// opcode =/= TLMessages.Release &&
// opcode =/= TLMessages.ReleaseData
case d: TLBundleD => true.B // Grant isResponse + isRequest
case e: TLBundleE => true.B
}
}
def hasData(x: TLChannel): Bool = {
val opdata = x match {
case a: TLBundleA => !a.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case b: TLBundleB => !b.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case c: TLBundleC => c.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.ProbeAckData ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
staticHasData(x).map(_.B).getOrElse(opdata)
}
def opcode(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.opcode
case b: TLBundleB => b.opcode
case c: TLBundleC => c.opcode
case d: TLBundleD => d.opcode
}
}
def param(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.param
case b: TLBundleB => b.param
case c: TLBundleC => c.param
case d: TLBundleD => d.param
}
}
def size(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.size
case b: TLBundleB => b.size
case c: TLBundleC => c.size
case d: TLBundleD => d.size
}
}
def data(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.data
case b: TLBundleB => b.data
case c: TLBundleC => c.data
case d: TLBundleD => d.data
}
}
def corrupt(x: TLDataChannel): Bool = {
x match {
case a: TLBundleA => a.corrupt
case b: TLBundleB => b.corrupt
case c: TLBundleC => c.corrupt
case d: TLBundleD => d.corrupt
}
}
def mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.mask
case b: TLBundleB => b.mask
case c: TLBundleC => mask(c.address, c.size)
}
}
def full_mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => mask(a.address, a.size)
case b: TLBundleB => mask(b.address, b.size)
case c: TLBundleC => mask(c.address, c.size)
}
}
def address(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.address
case b: TLBundleB => b.address
case c: TLBundleC => c.address
}
}
def source(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.source
case b: TLBundleB => b.source
case c: TLBundleC => c.source
case d: TLBundleD => d.source
}
}
def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes)
def addr_lo(x: UInt): UInt =
if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0)
def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x))
def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x))
def numBeats(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 1.U
case bundle: TLDataChannel => {
val hasData = this.hasData(bundle)
val size = this.size(bundle)
val cutoff = log2Ceil(manager.beatBytes)
val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U
val decode = UIntToOH(size, maxLgSize+1) >> cutoff
Mux(hasData, decode | small.asUInt, 1.U)
}
}
}
def numBeats1(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 0.U
case bundle: TLDataChannel => {
if (maxLgSize == 0) {
0.U
} else {
val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes)
Mux(hasData(bundle), decode, 0.U)
}
}
}
}
def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val beats1 = numBeats1(bits)
val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W))
val counter1 = counter - 1.U
val first = counter === 0.U
val last = counter === 1.U || beats1 === 0.U
val done = last && fire
val count = (beats1 & ~counter1)
when (fire) {
counter := Mux(first, beats1, counter1)
}
(first, last, done, count)
}
def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1
def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire)
def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid)
def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2
def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire)
def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid)
def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3
def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire)
def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid)
def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3)
}
def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire)
def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid)
def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4)
}
def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire)
def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid)
def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes))
}
def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire)
def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid)
// Does the request need T permissions to be executed?
def needT(a: TLBundleA): Bool = {
val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLPermissions.NtoB -> false.B,
TLPermissions.NtoT -> true.B,
TLPermissions.BtoT -> true.B))
MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array(
TLMessages.PutFullData -> true.B,
TLMessages.PutPartialData -> true.B,
TLMessages.ArithmeticData -> true.B,
TLMessages.LogicalData -> true.B,
TLMessages.Get -> false.B,
TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLHints.PREFETCH_READ -> false.B,
TLHints.PREFETCH_WRITE -> true.B)),
TLMessages.AcquireBlock -> acq_needT,
TLMessages.AcquirePerm -> acq_needT))
}
// This is a very expensive circuit; use only if you really mean it!
def inFlight(x: TLBundle): (UInt, UInt) = {
val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W))
val bce = manager.anySupportAcquireB && client.anySupportProbe
val (a_first, a_last, _) = firstlast(x.a)
val (b_first, b_last, _) = firstlast(x.b)
val (c_first, c_last, _) = firstlast(x.c)
val (d_first, d_last, _) = firstlast(x.d)
val (e_first, e_last, _) = firstlast(x.e)
val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits))
val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits))
val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits))
val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits))
val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits))
val a_inc = x.a.fire && a_first && a_request
val b_inc = x.b.fire && b_first && b_request
val c_inc = x.c.fire && c_first && c_request
val d_inc = x.d.fire && d_first && d_request
val e_inc = x.e.fire && e_first && e_request
val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil))
val a_dec = x.a.fire && a_last && a_response
val b_dec = x.b.fire && b_last && b_response
val c_dec = x.c.fire && c_last && c_response
val d_dec = x.d.fire && d_last && d_response
val e_dec = x.e.fire && e_last && e_response
val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil))
val next_flight = flight + PopCount(inc) - PopCount(dec)
flight := next_flight
(flight, next_flight)
}
def prettySourceMapping(context: String): String = {
s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n"
}
}
class TLEdgeOut(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
// Transfers
def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquireBlock
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquirePerm
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.Release
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ReleaseData
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) =
Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B)
def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAck
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions, data)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAckData
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B)
def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink)
def GrantAck(toSink: UInt): TLBundleE = {
val e = Wire(new TLBundleE(bundle))
e.sink := toSink
e
}
// Accesses
def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsGetFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Get
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutFullFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutFullData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, mask, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutPartialFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutPartialData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = {
require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsArithmeticFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.ArithmeticData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsLogicalFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.LogicalData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = {
require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsHintFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Hint
a.param := param
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data)
def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAckData
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size)
def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.HintAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
}
class TLEdgeIn(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = {
val todo = x.filter(!_.isEmpty)
val heads = todo.map(_.head)
val tails = todo.map(_.tail)
if (todo.isEmpty) Nil else { heads +: myTranspose(tails) }
}
// Transfers
def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = {
require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}")
val legal = client.supportsProbe(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Probe
b.param := capPermissions
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.Grant
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.GrantData
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B)
def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.ReleaseAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
// Accesses
def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = {
require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsGet(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Get
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsPutFull(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutFullData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, mask, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsPutPartial(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutPartialData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsArithmetic(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.ArithmeticData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsLogical(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.LogicalData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = {
require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsHint(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Hint
b.param := param
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size)
def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied)
def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data)
def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAckData
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B)
def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied)
def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B)
def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.HintAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
}
File Xbar.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy.lazymodule._
import freechips.rocketchip.diplomacy.{AddressDecoder, AddressSet, RegionType, IdRange, TriStateValue}
import freechips.rocketchip.util.BundleField
// Trades off slave port proximity against routing resource cost
object ForceFanout
{
def apply[T](
a: TriStateValue = TriStateValue.unset,
b: TriStateValue = TriStateValue.unset,
c: TriStateValue = TriStateValue.unset,
d: TriStateValue = TriStateValue.unset,
e: TriStateValue = TriStateValue.unset)(body: Parameters => T)(implicit p: Parameters) =
{
body(p.alterPartial {
case ForceFanoutKey => p(ForceFanoutKey) match {
case ForceFanoutParams(pa, pb, pc, pd, pe) =>
ForceFanoutParams(a.update(pa), b.update(pb), c.update(pc), d.update(pd), e.update(pe))
}
})
}
}
private case class ForceFanoutParams(a: Boolean, b: Boolean, c: Boolean, d: Boolean, e: Boolean)
private case object ForceFanoutKey extends Field(ForceFanoutParams(false, false, false, false, false))
class TLXbar(policy: TLArbiter.Policy = TLArbiter.roundRobin, nameSuffix: Option[String] = None)(implicit p: Parameters) extends LazyModule
{
val node = new TLNexusNode(
clientFn = { seq =>
seq(0).v1copy(
echoFields = BundleField.union(seq.flatMap(_.echoFields)),
requestFields = BundleField.union(seq.flatMap(_.requestFields)),
responseKeys = seq.flatMap(_.responseKeys).distinct,
minLatency = seq.map(_.minLatency).min,
clients = (TLXbar.mapInputIds(seq) zip seq) flatMap { case (range, port) =>
port.clients map { client => client.v1copy(
sourceId = client.sourceId.shift(range.start)
)}
}
)
},
managerFn = { seq =>
val fifoIdFactory = TLXbar.relabeler()
seq(0).v1copy(
responseFields = BundleField.union(seq.flatMap(_.responseFields)),
requestKeys = seq.flatMap(_.requestKeys).distinct,
minLatency = seq.map(_.minLatency).min,
endSinkId = TLXbar.mapOutputIds(seq).map(_.end).max,
managers = seq.flatMap { port =>
require (port.beatBytes == seq(0).beatBytes,
s"Xbar ($name with parent $parent) data widths don't match: ${port.managers.map(_.name)} has ${port.beatBytes}B vs ${seq(0).managers.map(_.name)} has ${seq(0).beatBytes}B")
val fifoIdMapper = fifoIdFactory()
port.managers map { manager => manager.v1copy(
fifoId = manager.fifoId.map(fifoIdMapper(_))
)}
}
)
}
){
override def circuitIdentity = outputs.size == 1 && inputs.size == 1
}
lazy val module = new Impl
class Impl extends LazyModuleImp(this) {
if ((node.in.size * node.out.size) > (8*32)) {
println (s"!!! WARNING !!!")
println (s" Your TLXbar ($name with parent $parent) is very large, with ${node.in.size} Masters and ${node.out.size} Slaves.")
println (s"!!! WARNING !!!")
}
val wide_bundle = TLBundleParameters.union((node.in ++ node.out).map(_._2.bundle))
override def desiredName = (Seq("TLXbar") ++ nameSuffix ++ Seq(s"i${node.in.size}_o${node.out.size}_${wide_bundle.shortName}")).mkString("_")
TLXbar.circuit(policy, node.in, node.out)
}
}
object TLXbar
{
def mapInputIds(ports: Seq[TLMasterPortParameters]) = assignRanges(ports.map(_.endSourceId))
def mapOutputIds(ports: Seq[TLSlavePortParameters]) = assignRanges(ports.map(_.endSinkId))
def assignRanges(sizes: Seq[Int]) = {
val pow2Sizes = sizes.map { z => if (z == 0) 0 else 1 << log2Ceil(z) }
val tuples = pow2Sizes.zipWithIndex.sortBy(_._1) // record old index, then sort by increasing size
val starts = tuples.scanRight(0)(_._1 + _).tail // suffix-sum of the sizes = the start positions
val ranges = (tuples zip starts) map { case ((sz, i), st) =>
(if (sz == 0) IdRange(0, 0) else IdRange(st, st + sz), i)
}
ranges.sortBy(_._2).map(_._1) // Restore orignal order
}
def relabeler() = {
var idFactory = 0
() => {
val fifoMap = scala.collection.mutable.HashMap.empty[Int, Int]
(x: Int) => {
if (fifoMap.contains(x)) fifoMap(x) else {
val out = idFactory
idFactory = idFactory + 1
fifoMap += (x -> out)
out
}
}
}
}
def circuit(policy: TLArbiter.Policy, seqIn: Seq[(TLBundle, TLEdge)], seqOut: Seq[(TLBundle, TLEdge)]) {
val (io_in, edgesIn) = seqIn.unzip
val (io_out, edgesOut) = seqOut.unzip
// Not every master need connect to every slave on every channel; determine which connections are necessary
val reachableIO = edgesIn.map { cp => edgesOut.map { mp =>
cp.client.clients.exists { c => mp.manager.managers.exists { m =>
c.visibility.exists { ca => m.address.exists { ma =>
ca.overlaps(ma)}}}}
}.toVector}.toVector
val probeIO = (edgesIn zip reachableIO).map { case (cp, reachableO) =>
(edgesOut zip reachableO).map { case (mp, reachable) =>
reachable && cp.client.anySupportProbe && mp.manager.managers.exists(_.regionType >= RegionType.TRACKED)
}.toVector}.toVector
val releaseIO = (edgesIn zip reachableIO).map { case (cp, reachableO) =>
(edgesOut zip reachableO).map { case (mp, reachable) =>
reachable && cp.client.anySupportProbe && mp.manager.anySupportAcquireB
}.toVector}.toVector
val connectAIO = reachableIO
val connectBIO = probeIO
val connectCIO = releaseIO
val connectDIO = reachableIO
val connectEIO = releaseIO
def transpose[T](x: Seq[Seq[T]]) = if (x.isEmpty) Nil else Vector.tabulate(x(0).size) { i => Vector.tabulate(x.size) { j => x(j)(i) } }
val connectAOI = transpose(connectAIO)
val connectBOI = transpose(connectBIO)
val connectCOI = transpose(connectCIO)
val connectDOI = transpose(connectDIO)
val connectEOI = transpose(connectEIO)
// Grab the port ID mapping
val inputIdRanges = TLXbar.mapInputIds(edgesIn.map(_.client))
val outputIdRanges = TLXbar.mapOutputIds(edgesOut.map(_.manager))
// We need an intermediate size of bundle with the widest possible identifiers
val wide_bundle = TLBundleParameters.union(io_in.map(_.params) ++ io_out.map(_.params))
// Handle size = 1 gracefully (Chisel3 empty range is broken)
def trim(id: UInt, size: Int): UInt = if (size <= 1) 0.U else id(log2Ceil(size)-1, 0)
// Transform input bundle sources (sinks use global namespace on both sides)
val in = Wire(Vec(io_in.size, TLBundle(wide_bundle)))
for (i <- 0 until in.size) {
val r = inputIdRanges(i)
if (connectAIO(i).exists(x=>x)) {
in(i).a.bits.user := DontCare
in(i).a.squeezeAll.waiveAll :<>= io_in(i).a.squeezeAll.waiveAll
in(i).a.bits.source := io_in(i).a.bits.source | r.start.U
} else {
in(i).a := DontCare
io_in(i).a := DontCare
in(i).a.valid := false.B
io_in(i).a.ready := true.B
}
if (connectBIO(i).exists(x=>x)) {
io_in(i).b.squeezeAll :<>= in(i).b.squeezeAll
io_in(i).b.bits.source := trim(in(i).b.bits.source, r.size)
} else {
in(i).b := DontCare
io_in(i).b := DontCare
in(i).b.ready := true.B
io_in(i).b.valid := false.B
}
if (connectCIO(i).exists(x=>x)) {
in(i).c.bits.user := DontCare
in(i).c.squeezeAll.waiveAll :<>= io_in(i).c.squeezeAll.waiveAll
in(i).c.bits.source := io_in(i).c.bits.source | r.start.U
} else {
in(i).c := DontCare
io_in(i).c := DontCare
in(i).c.valid := false.B
io_in(i).c.ready := true.B
}
if (connectDIO(i).exists(x=>x)) {
io_in(i).d.squeezeAll.waiveAll :<>= in(i).d.squeezeAll.waiveAll
io_in(i).d.bits.source := trim(in(i).d.bits.source, r.size)
} else {
in(i).d := DontCare
io_in(i).d := DontCare
in(i).d.ready := true.B
io_in(i).d.valid := false.B
}
if (connectEIO(i).exists(x=>x)) {
in(i).e.squeezeAll :<>= io_in(i).e.squeezeAll
} else {
in(i).e := DontCare
io_in(i).e := DontCare
in(i).e.valid := false.B
io_in(i).e.ready := true.B
}
}
// Transform output bundle sinks (sources use global namespace on both sides)
val out = Wire(Vec(io_out.size, TLBundle(wide_bundle)))
for (o <- 0 until out.size) {
val r = outputIdRanges(o)
if (connectAOI(o).exists(x=>x)) {
out(o).a.bits.user := DontCare
io_out(o).a.squeezeAll.waiveAll :<>= out(o).a.squeezeAll.waiveAll
} else {
out(o).a := DontCare
io_out(o).a := DontCare
out(o).a.ready := true.B
io_out(o).a.valid := false.B
}
if (connectBOI(o).exists(x=>x)) {
out(o).b.squeezeAll :<>= io_out(o).b.squeezeAll
} else {
out(o).b := DontCare
io_out(o).b := DontCare
out(o).b.valid := false.B
io_out(o).b.ready := true.B
}
if (connectCOI(o).exists(x=>x)) {
out(o).c.bits.user := DontCare
io_out(o).c.squeezeAll.waiveAll :<>= out(o).c.squeezeAll.waiveAll
} else {
out(o).c := DontCare
io_out(o).c := DontCare
out(o).c.ready := true.B
io_out(o).c.valid := false.B
}
if (connectDOI(o).exists(x=>x)) {
out(o).d.squeezeAll :<>= io_out(o).d.squeezeAll
out(o).d.bits.sink := io_out(o).d.bits.sink | r.start.U
} else {
out(o).d := DontCare
io_out(o).d := DontCare
out(o).d.valid := false.B
io_out(o).d.ready := true.B
}
if (connectEOI(o).exists(x=>x)) {
io_out(o).e.squeezeAll :<>= out(o).e.squeezeAll
io_out(o).e.bits.sink := trim(out(o).e.bits.sink, r.size)
} else {
out(o).e := DontCare
io_out(o).e := DontCare
out(o).e.ready := true.B
io_out(o).e.valid := false.B
}
}
// Filter a list to only those elements selected
def filter[T](data: Seq[T], mask: Seq[Boolean]) = (data zip mask).filter(_._2).map(_._1)
// Based on input=>output connectivity, create per-input minimal address decode circuits
val requiredAC = (connectAIO ++ connectCIO).distinct
val outputPortFns: Map[Vector[Boolean], Seq[UInt => Bool]] = requiredAC.map { connectO =>
val port_addrs = edgesOut.map(_.manager.managers.flatMap(_.address))
val routingMask = AddressDecoder(filter(port_addrs, connectO))
val route_addrs = port_addrs.map(seq => AddressSet.unify(seq.map(_.widen(~routingMask)).distinct))
// Print the address mapping
if (false) {
println("Xbar mapping:")
route_addrs.foreach { p =>
print(" ")
p.foreach { a => print(s" ${a}") }
println("")
}
println("--")
}
(connectO, route_addrs.map(seq => (addr: UInt) => seq.map(_.contains(addr)).reduce(_ || _)))
}.toMap
// Print the ID mapping
if (false) {
println(s"XBar mapping:")
(edgesIn zip inputIdRanges).zipWithIndex.foreach { case ((edge, id), i) =>
println(s"\t$i assigned ${id} for ${edge.client.clients.map(_.name).mkString(", ")}")
}
println("")
}
val addressA = (in zip edgesIn) map { case (i, e) => e.address(i.a.bits) }
val addressC = (in zip edgesIn) map { case (i, e) => e.address(i.c.bits) }
def unique(x: Vector[Boolean]): Bool = (x.filter(x=>x).size <= 1).B
val requestAIO = (connectAIO zip addressA) map { case (c, i) => outputPortFns(c).map { o => unique(c) || o(i) } }
val requestCIO = (connectCIO zip addressC) map { case (c, i) => outputPortFns(c).map { o => unique(c) || o(i) } }
val requestBOI = out.map { o => inputIdRanges.map { i => i.contains(o.b.bits.source) } }
val requestDOI = out.map { o => inputIdRanges.map { i => i.contains(o.d.bits.source) } }
val requestEIO = in.map { i => outputIdRanges.map { o => o.contains(i.e.bits.sink) } }
val beatsAI = (in zip edgesIn) map { case (i, e) => e.numBeats1(i.a.bits) }
val beatsBO = (out zip edgesOut) map { case (o, e) => e.numBeats1(o.b.bits) }
val beatsCI = (in zip edgesIn) map { case (i, e) => e.numBeats1(i.c.bits) }
val beatsDO = (out zip edgesOut) map { case (o, e) => e.numBeats1(o.d.bits) }
val beatsEI = (in zip edgesIn) map { case (i, e) => e.numBeats1(i.e.bits) }
// Fanout the input sources to the output sinks
val portsAOI = transpose((in zip requestAIO) map { case (i, r) => TLXbar.fanout(i.a, r, edgesOut.map(_.params(ForceFanoutKey).a)) })
val portsBIO = transpose((out zip requestBOI) map { case (o, r) => TLXbar.fanout(o.b, r, edgesIn .map(_.params(ForceFanoutKey).b)) })
val portsCOI = transpose((in zip requestCIO) map { case (i, r) => TLXbar.fanout(i.c, r, edgesOut.map(_.params(ForceFanoutKey).c)) })
val portsDIO = transpose((out zip requestDOI) map { case (o, r) => TLXbar.fanout(o.d, r, edgesIn .map(_.params(ForceFanoutKey).d)) })
val portsEOI = transpose((in zip requestEIO) map { case (i, r) => TLXbar.fanout(i.e, r, edgesOut.map(_.params(ForceFanoutKey).e)) })
// Arbitrate amongst the sources
for (o <- 0 until out.size) {
TLArbiter(policy)(out(o).a, filter(beatsAI zip portsAOI(o), connectAOI(o)):_*)
TLArbiter(policy)(out(o).c, filter(beatsCI zip portsCOI(o), connectCOI(o)):_*)
TLArbiter(policy)(out(o).e, filter(beatsEI zip portsEOI(o), connectEOI(o)):_*)
filter(portsAOI(o), connectAOI(o).map(!_)) foreach { r => r.ready := false.B }
filter(portsCOI(o), connectCOI(o).map(!_)) foreach { r => r.ready := false.B }
filter(portsEOI(o), connectEOI(o).map(!_)) foreach { r => r.ready := false.B }
}
for (i <- 0 until in.size) {
TLArbiter(policy)(in(i).b, filter(beatsBO zip portsBIO(i), connectBIO(i)):_*)
TLArbiter(policy)(in(i).d, filter(beatsDO zip portsDIO(i), connectDIO(i)):_*)
filter(portsBIO(i), connectBIO(i).map(!_)) foreach { r => r.ready := false.B }
filter(portsDIO(i), connectDIO(i).map(!_)) foreach { r => r.ready := false.B }
}
}
def apply(policy: TLArbiter.Policy = TLArbiter.roundRobin, nameSuffix: Option[String] = None)(implicit p: Parameters): TLNode =
{
val xbar = LazyModule(new TLXbar(policy, nameSuffix))
xbar.node
}
// Replicate an input port to each output port
def fanout[T <: TLChannel](input: DecoupledIO[T], select: Seq[Bool], force: Seq[Boolean] = Nil): Seq[DecoupledIO[T]] = {
val filtered = Wire(Vec(select.size, chiselTypeOf(input)))
for (i <- 0 until select.size) {
filtered(i).bits := (if (force.lift(i).getOrElse(false)) IdentityModule(input.bits) else input.bits)
filtered(i).valid := input.valid && (select(i) || (select.size == 1).B)
}
input.ready := Mux1H(select, filtered.map(_.ready))
filtered
}
}
// Synthesizable unit tests
import freechips.rocketchip.unittest._
class TLRAMXbar(nManagers: Int, txns: Int)(implicit p: Parameters) extends LazyModule {
val fuzz = LazyModule(new TLFuzzer(txns))
val model = LazyModule(new TLRAMModel("Xbar"))
val xbar = LazyModule(new TLXbar)
xbar.node := TLDelayer(0.1) := model.node := fuzz.node
(0 until nManagers) foreach { n =>
val ram = LazyModule(new TLRAM(AddressSet(0x0+0x400*n, 0x3ff)))
ram.node := TLFragmenter(4, 256) := TLDelayer(0.1) := xbar.node
}
lazy val module = new Impl
class Impl extends LazyModuleImp(this) with UnitTestModule {
io.finished := fuzz.module.io.finished
}
}
class TLRAMXbarTest(nManagers: Int, txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) {
val dut = Module(LazyModule(new TLRAMXbar(nManagers,txns)).module)
dut.io.start := io.start
io.finished := dut.io.finished
}
class TLMulticlientXbar(nManagers: Int, nClients: Int, txns: Int)(implicit p: Parameters) extends LazyModule {
val xbar = LazyModule(new TLXbar)
val fuzzers = (0 until nClients) map { n =>
val fuzz = LazyModule(new TLFuzzer(txns))
xbar.node := TLDelayer(0.1) := fuzz.node
fuzz
}
(0 until nManagers) foreach { n =>
val ram = LazyModule(new TLRAM(AddressSet(0x0+0x400*n, 0x3ff)))
ram.node := TLFragmenter(4, 256) := TLDelayer(0.1) := xbar.node
}
lazy val module = new Impl
class Impl extends LazyModuleImp(this) with UnitTestModule {
io.finished := fuzzers.last.module.io.finished
}
}
class TLMulticlientXbarTest(nManagers: Int, nClients: Int, txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) {
val dut = Module(LazyModule(new TLMulticlientXbar(nManagers, nClients, txns)).module)
dut.io.start := io.start
io.finished := dut.io.finished
}
| module CoherenceManagerWrapper( // @[ClockDomain.scala:14:9]
input auto_coupler_to_bus_named_mbus_bus_xing_out_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_coupler_to_bus_named_mbus_bus_xing_out_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [5:0] auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_coupler_to_bus_named_mbus_bus_xing_out_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_coupler_to_bus_named_mbus_bus_xing_out_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_param, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [5:0] auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_source, // @[LazyModuleImp.scala:107:25]
input auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_denied, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_coherent_jbar_anon_in_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_coherent_jbar_anon_in_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_coherent_jbar_anon_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_coherent_jbar_anon_in_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_coherent_jbar_anon_in_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_coherent_jbar_anon_in_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_coherent_jbar_anon_in_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_coherent_jbar_anon_in_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [255:0] auto_coherent_jbar_anon_in_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_coherent_jbar_anon_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_coherent_jbar_anon_in_b_ready, // @[LazyModuleImp.scala:107:25]
output auto_coherent_jbar_anon_in_b_valid, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_coherent_jbar_anon_in_b_bits_param, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_coherent_jbar_anon_in_b_bits_address, // @[LazyModuleImp.scala:107:25]
output auto_coherent_jbar_anon_in_c_ready, // @[LazyModuleImp.scala:107:25]
input auto_coherent_jbar_anon_in_c_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_coherent_jbar_anon_in_c_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_coherent_jbar_anon_in_c_bits_param, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_coherent_jbar_anon_in_c_bits_size, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_coherent_jbar_anon_in_c_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_coherent_jbar_anon_in_c_bits_address, // @[LazyModuleImp.scala:107:25]
input [255:0] auto_coherent_jbar_anon_in_c_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_coherent_jbar_anon_in_c_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_coherent_jbar_anon_in_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_coherent_jbar_anon_in_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_coherent_jbar_anon_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_coherent_jbar_anon_in_d_bits_param, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_coherent_jbar_anon_in_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_coherent_jbar_anon_in_d_bits_source, // @[LazyModuleImp.scala:107:25]
output [4:0] auto_coherent_jbar_anon_in_d_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_coherent_jbar_anon_in_d_bits_denied, // @[LazyModuleImp.scala:107:25]
output [255:0] auto_coherent_jbar_anon_in_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_coherent_jbar_anon_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_coherent_jbar_anon_in_e_valid, // @[LazyModuleImp.scala:107:25]
input [4:0] auto_coherent_jbar_anon_in_e_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_l2_ctrls_ctrl_in_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_l2_ctrls_ctrl_in_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_l2_ctrls_ctrl_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_l2_ctrls_ctrl_in_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_l2_ctrls_ctrl_in_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [12:0] auto_l2_ctrls_ctrl_in_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [25:0] auto_l2_ctrls_ctrl_in_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_l2_ctrls_ctrl_in_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_l2_ctrls_ctrl_in_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_l2_ctrls_ctrl_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_l2_ctrls_ctrl_in_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_l2_ctrls_ctrl_in_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_l2_ctrls_ctrl_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_l2_ctrls_ctrl_in_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [12:0] auto_l2_ctrls_ctrl_in_d_bits_source, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_l2_ctrls_ctrl_in_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_coh_clock_groups_in_member_coh_0_clock, // @[LazyModuleImp.scala:107:25]
input auto_coh_clock_groups_in_member_coh_0_reset // @[LazyModuleImp.scala:107:25]
);
wire coupler_to_bus_named_mbus_widget_auto_anon_out_d_valid; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_mbus_widget_auto_anon_out_d_ready; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_mbus_widget_auto_anon_out_d_bits_corrupt; // @[WidthWidget.scala:27:9]
wire [63:0] coupler_to_bus_named_mbus_widget_auto_anon_out_d_bits_data; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_mbus_widget_auto_anon_out_d_bits_denied; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_mbus_widget_auto_anon_out_d_bits_sink; // @[WidthWidget.scala:27:9]
wire [5:0] coupler_to_bus_named_mbus_widget_auto_anon_out_d_bits_source; // @[WidthWidget.scala:27:9]
wire [2:0] coupler_to_bus_named_mbus_widget_auto_anon_out_d_bits_size; // @[WidthWidget.scala:27:9]
wire [1:0] coupler_to_bus_named_mbus_widget_auto_anon_out_d_bits_param; // @[WidthWidget.scala:27:9]
wire [2:0] coupler_to_bus_named_mbus_widget_auto_anon_out_d_bits_opcode; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_mbus_widget_auto_anon_out_a_valid; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_mbus_widget_auto_anon_out_a_ready; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_mbus_widget_auto_anon_out_a_bits_corrupt; // @[WidthWidget.scala:27:9]
wire [63:0] coupler_to_bus_named_mbus_widget_auto_anon_out_a_bits_data; // @[WidthWidget.scala:27:9]
wire [7:0] coupler_to_bus_named_mbus_widget_auto_anon_out_a_bits_mask; // @[WidthWidget.scala:27:9]
wire [31:0] coupler_to_bus_named_mbus_widget_auto_anon_out_a_bits_address; // @[WidthWidget.scala:27:9]
wire [5:0] coupler_to_bus_named_mbus_widget_auto_anon_out_a_bits_source; // @[WidthWidget.scala:27:9]
wire [2:0] coupler_to_bus_named_mbus_widget_auto_anon_out_a_bits_size; // @[WidthWidget.scala:27:9]
wire [2:0] coupler_to_bus_named_mbus_widget_auto_anon_out_a_bits_param; // @[WidthWidget.scala:27:9]
wire [2:0] coupler_to_bus_named_mbus_widget_auto_anon_out_a_bits_opcode; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_mbus_auto_widget_anon_in_d_ready; // @[LazyModuleImp.scala:138:7]
wire coupler_to_bus_named_mbus_auto_widget_anon_in_a_valid; // @[LazyModuleImp.scala:138:7]
wire coupler_to_bus_named_mbus_auto_widget_anon_in_a_bits_corrupt; // @[LazyModuleImp.scala:138:7]
wire [63:0] coupler_to_bus_named_mbus_auto_widget_anon_in_a_bits_data; // @[LazyModuleImp.scala:138:7]
wire [7:0] coupler_to_bus_named_mbus_auto_widget_anon_in_a_bits_mask; // @[LazyModuleImp.scala:138:7]
wire [31:0] coupler_to_bus_named_mbus_auto_widget_anon_in_a_bits_address; // @[LazyModuleImp.scala:138:7]
wire [5:0] coupler_to_bus_named_mbus_auto_widget_anon_in_a_bits_source; // @[LazyModuleImp.scala:138:7]
wire [2:0] coupler_to_bus_named_mbus_auto_widget_anon_in_a_bits_size; // @[LazyModuleImp.scala:138:7]
wire [2:0] coupler_to_bus_named_mbus_auto_widget_anon_in_a_bits_param; // @[LazyModuleImp.scala:138:7]
wire [2:0] coupler_to_bus_named_mbus_auto_widget_anon_in_a_bits_opcode; // @[LazyModuleImp.scala:138:7]
wire [4:0] coherent_jbar_out_0_e_bits_sink; // @[Xbar.scala:216:19]
wire [4:0] coherent_jbar_out_0_d_bits_sink; // @[Xbar.scala:216:19]
wire [7:0] coherent_jbar_in_0_d_bits_source; // @[Xbar.scala:159:18]
wire [7:0] coherent_jbar_in_0_c_bits_source; // @[Xbar.scala:159:18]
wire [7:0] coherent_jbar_in_0_a_bits_source; // @[Xbar.scala:159:18]
wire InclusiveCache_outer_TLBuffer_auto_out_d_valid; // @[Buffer.scala:40:9]
wire InclusiveCache_outer_TLBuffer_auto_out_d_bits_corrupt; // @[Buffer.scala:40:9]
wire [63:0] InclusiveCache_outer_TLBuffer_auto_out_d_bits_data; // @[Buffer.scala:40:9]
wire InclusiveCache_outer_TLBuffer_auto_out_d_bits_denied; // @[Buffer.scala:40:9]
wire [2:0] InclusiveCache_outer_TLBuffer_auto_out_d_bits_sink; // @[Buffer.scala:40:9]
wire [4:0] InclusiveCache_outer_TLBuffer_auto_out_d_bits_source; // @[Buffer.scala:40:9]
wire [2:0] InclusiveCache_outer_TLBuffer_auto_out_d_bits_size; // @[Buffer.scala:40:9]
wire [1:0] InclusiveCache_outer_TLBuffer_auto_out_d_bits_param; // @[Buffer.scala:40:9]
wire [2:0] InclusiveCache_outer_TLBuffer_auto_out_d_bits_opcode; // @[Buffer.scala:40:9]
wire InclusiveCache_outer_TLBuffer_auto_out_c_ready; // @[Buffer.scala:40:9]
wire InclusiveCache_outer_TLBuffer_auto_out_a_ready; // @[Buffer.scala:40:9]
wire InclusiveCache_outer_TLBuffer_auto_in_e_valid; // @[Buffer.scala:40:9]
wire [2:0] InclusiveCache_outer_TLBuffer_auto_in_e_bits_sink; // @[Buffer.scala:40:9]
wire InclusiveCache_outer_TLBuffer_auto_in_d_ready; // @[Buffer.scala:40:9]
wire InclusiveCache_outer_TLBuffer_auto_in_c_valid; // @[Buffer.scala:40:9]
wire InclusiveCache_outer_TLBuffer_auto_in_c_bits_corrupt; // @[Buffer.scala:40:9]
wire [63:0] InclusiveCache_outer_TLBuffer_auto_in_c_bits_data; // @[Buffer.scala:40:9]
wire [31:0] InclusiveCache_outer_TLBuffer_auto_in_c_bits_address; // @[Buffer.scala:40:9]
wire [4:0] InclusiveCache_outer_TLBuffer_auto_in_c_bits_source; // @[Buffer.scala:40:9]
wire [2:0] InclusiveCache_outer_TLBuffer_auto_in_c_bits_size; // @[Buffer.scala:40:9]
wire [2:0] InclusiveCache_outer_TLBuffer_auto_in_c_bits_param; // @[Buffer.scala:40:9]
wire [2:0] InclusiveCache_outer_TLBuffer_auto_in_c_bits_opcode; // @[Buffer.scala:40:9]
wire InclusiveCache_outer_TLBuffer_auto_in_a_valid; // @[Buffer.scala:40:9]
wire InclusiveCache_outer_TLBuffer_auto_in_a_bits_corrupt; // @[Buffer.scala:40:9]
wire [63:0] InclusiveCache_outer_TLBuffer_auto_in_a_bits_data; // @[Buffer.scala:40:9]
wire [7:0] InclusiveCache_outer_TLBuffer_auto_in_a_bits_mask; // @[Buffer.scala:40:9]
wire [31:0] InclusiveCache_outer_TLBuffer_auto_in_a_bits_address; // @[Buffer.scala:40:9]
wire [4:0] InclusiveCache_outer_TLBuffer_auto_in_a_bits_source; // @[Buffer.scala:40:9]
wire [2:0] InclusiveCache_outer_TLBuffer_auto_in_a_bits_size; // @[Buffer.scala:40:9]
wire [2:0] InclusiveCache_outer_TLBuffer_auto_in_a_bits_param; // @[Buffer.scala:40:9]
wire [2:0] InclusiveCache_outer_TLBuffer_auto_in_a_bits_opcode; // @[Buffer.scala:40:9]
wire filter_auto_anon_out_d_valid; // @[Filter.scala:60:9]
wire filter_auto_anon_out_d_bits_corrupt; // @[Filter.scala:60:9]
wire [255:0] filter_auto_anon_out_d_bits_data; // @[Filter.scala:60:9]
wire filter_auto_anon_out_d_bits_denied; // @[Filter.scala:60:9]
wire [4:0] filter_auto_anon_out_d_bits_sink; // @[Filter.scala:60:9]
wire [7:0] filter_auto_anon_out_d_bits_source; // @[Filter.scala:60:9]
wire [2:0] filter_auto_anon_out_d_bits_size; // @[Filter.scala:60:9]
wire [1:0] filter_auto_anon_out_d_bits_param; // @[Filter.scala:60:9]
wire [2:0] filter_auto_anon_out_d_bits_opcode; // @[Filter.scala:60:9]
wire filter_auto_anon_out_c_ready; // @[Filter.scala:60:9]
wire filter_auto_anon_out_b_valid; // @[Filter.scala:60:9]
wire [31:0] filter_auto_anon_out_b_bits_address; // @[Filter.scala:60:9]
wire [1:0] filter_auto_anon_out_b_bits_param; // @[Filter.scala:60:9]
wire filter_auto_anon_out_a_ready; // @[Filter.scala:60:9]
wire filter_auto_anon_in_e_valid; // @[Filter.scala:60:9]
wire [4:0] filter_auto_anon_in_e_bits_sink; // @[Filter.scala:60:9]
wire filter_auto_anon_in_d_valid; // @[Filter.scala:60:9]
wire filter_auto_anon_in_d_ready; // @[Filter.scala:60:9]
wire filter_auto_anon_in_d_bits_corrupt; // @[Filter.scala:60:9]
wire [255:0] filter_auto_anon_in_d_bits_data; // @[Filter.scala:60:9]
wire filter_auto_anon_in_d_bits_denied; // @[Filter.scala:60:9]
wire [4:0] filter_auto_anon_in_d_bits_sink; // @[Filter.scala:60:9]
wire [7:0] filter_auto_anon_in_d_bits_source; // @[Filter.scala:60:9]
wire [2:0] filter_auto_anon_in_d_bits_size; // @[Filter.scala:60:9]
wire [1:0] filter_auto_anon_in_d_bits_param; // @[Filter.scala:60:9]
wire [2:0] filter_auto_anon_in_d_bits_opcode; // @[Filter.scala:60:9]
wire filter_auto_anon_in_c_valid; // @[Filter.scala:60:9]
wire filter_auto_anon_in_c_ready; // @[Filter.scala:60:9]
wire filter_auto_anon_in_c_bits_corrupt; // @[Filter.scala:60:9]
wire [255:0] filter_auto_anon_in_c_bits_data; // @[Filter.scala:60:9]
wire [31:0] filter_auto_anon_in_c_bits_address; // @[Filter.scala:60:9]
wire [7:0] filter_auto_anon_in_c_bits_source; // @[Filter.scala:60:9]
wire [2:0] filter_auto_anon_in_c_bits_size; // @[Filter.scala:60:9]
wire [2:0] filter_auto_anon_in_c_bits_param; // @[Filter.scala:60:9]
wire [2:0] filter_auto_anon_in_c_bits_opcode; // @[Filter.scala:60:9]
wire filter_auto_anon_in_b_valid; // @[Filter.scala:60:9]
wire filter_auto_anon_in_b_ready; // @[Filter.scala:60:9]
wire [31:0] filter_auto_anon_in_b_bits_address; // @[Filter.scala:60:9]
wire [1:0] filter_auto_anon_in_b_bits_param; // @[Filter.scala:60:9]
wire filter_auto_anon_in_a_valid; // @[Filter.scala:60:9]
wire filter_auto_anon_in_a_ready; // @[Filter.scala:60:9]
wire filter_auto_anon_in_a_bits_corrupt; // @[Filter.scala:60:9]
wire [255:0] filter_auto_anon_in_a_bits_data; // @[Filter.scala:60:9]
wire [31:0] filter_auto_anon_in_a_bits_mask; // @[Filter.scala:60:9]
wire [31:0] filter_auto_anon_in_a_bits_address; // @[Filter.scala:60:9]
wire [7:0] filter_auto_anon_in_a_bits_source; // @[Filter.scala:60:9]
wire [2:0] filter_auto_anon_in_a_bits_size; // @[Filter.scala:60:9]
wire [2:0] filter_auto_anon_in_a_bits_param; // @[Filter.scala:60:9]
wire [2:0] filter_auto_anon_in_a_bits_opcode; // @[Filter.scala:60:9]
wire fixedClockNode_auto_anon_out_reset; // @[ClockGroup.scala:104:9]
wire fixedClockNode_auto_anon_out_clock; // @[ClockGroup.scala:104:9]
wire clockGroup_auto_out_reset; // @[ClockGroup.scala:24:9]
wire clockGroup_auto_out_clock; // @[ClockGroup.scala:24:9]
wire coh_clock_groups_auto_out_member_coh_0_reset; // @[ClockGroup.scala:53:9]
wire coh_clock_groups_auto_out_member_coh_0_clock; // @[ClockGroup.scala:53:9]
wire _binder_auto_in_a_ready; // @[BankBinder.scala:71:28]
wire _binder_auto_in_d_valid; // @[BankBinder.scala:71:28]
wire [2:0] _binder_auto_in_d_bits_opcode; // @[BankBinder.scala:71:28]
wire [1:0] _binder_auto_in_d_bits_param; // @[BankBinder.scala:71:28]
wire [2:0] _binder_auto_in_d_bits_size; // @[BankBinder.scala:71:28]
wire [5:0] _binder_auto_in_d_bits_source; // @[BankBinder.scala:71:28]
wire _binder_auto_in_d_bits_sink; // @[BankBinder.scala:71:28]
wire _binder_auto_in_d_bits_denied; // @[BankBinder.scala:71:28]
wire [63:0] _binder_auto_in_d_bits_data; // @[BankBinder.scala:71:28]
wire _binder_auto_in_d_bits_corrupt; // @[BankBinder.scala:71:28]
wire _cork_auto_out_a_valid; // @[Configs.scala:120:26]
wire [2:0] _cork_auto_out_a_bits_opcode; // @[Configs.scala:120:26]
wire [2:0] _cork_auto_out_a_bits_param; // @[Configs.scala:120:26]
wire [2:0] _cork_auto_out_a_bits_size; // @[Configs.scala:120:26]
wire [5:0] _cork_auto_out_a_bits_source; // @[Configs.scala:120:26]
wire [31:0] _cork_auto_out_a_bits_address; // @[Configs.scala:120:26]
wire [7:0] _cork_auto_out_a_bits_mask; // @[Configs.scala:120:26]
wire [63:0] _cork_auto_out_a_bits_data; // @[Configs.scala:120:26]
wire _cork_auto_out_a_bits_corrupt; // @[Configs.scala:120:26]
wire _cork_auto_out_d_ready; // @[Configs.scala:120:26]
wire _InclusiveCache_inner_TLBuffer_auto_out_a_valid; // @[Parameters.scala:56:69]
wire [2:0] _InclusiveCache_inner_TLBuffer_auto_out_a_bits_opcode; // @[Parameters.scala:56:69]
wire [2:0] _InclusiveCache_inner_TLBuffer_auto_out_a_bits_param; // @[Parameters.scala:56:69]
wire [2:0] _InclusiveCache_inner_TLBuffer_auto_out_a_bits_size; // @[Parameters.scala:56:69]
wire [7:0] _InclusiveCache_inner_TLBuffer_auto_out_a_bits_source; // @[Parameters.scala:56:69]
wire [31:0] _InclusiveCache_inner_TLBuffer_auto_out_a_bits_address; // @[Parameters.scala:56:69]
wire [31:0] _InclusiveCache_inner_TLBuffer_auto_out_a_bits_mask; // @[Parameters.scala:56:69]
wire [255:0] _InclusiveCache_inner_TLBuffer_auto_out_a_bits_data; // @[Parameters.scala:56:69]
wire _InclusiveCache_inner_TLBuffer_auto_out_a_bits_corrupt; // @[Parameters.scala:56:69]
wire _InclusiveCache_inner_TLBuffer_auto_out_b_ready; // @[Parameters.scala:56:69]
wire _InclusiveCache_inner_TLBuffer_auto_out_c_valid; // @[Parameters.scala:56:69]
wire [2:0] _InclusiveCache_inner_TLBuffer_auto_out_c_bits_opcode; // @[Parameters.scala:56:69]
wire [2:0] _InclusiveCache_inner_TLBuffer_auto_out_c_bits_param; // @[Parameters.scala:56:69]
wire [2:0] _InclusiveCache_inner_TLBuffer_auto_out_c_bits_size; // @[Parameters.scala:56:69]
wire [7:0] _InclusiveCache_inner_TLBuffer_auto_out_c_bits_source; // @[Parameters.scala:56:69]
wire [31:0] _InclusiveCache_inner_TLBuffer_auto_out_c_bits_address; // @[Parameters.scala:56:69]
wire [255:0] _InclusiveCache_inner_TLBuffer_auto_out_c_bits_data; // @[Parameters.scala:56:69]
wire _InclusiveCache_inner_TLBuffer_auto_out_c_bits_corrupt; // @[Parameters.scala:56:69]
wire _InclusiveCache_inner_TLBuffer_auto_out_d_ready; // @[Parameters.scala:56:69]
wire _InclusiveCache_inner_TLBuffer_auto_out_e_valid; // @[Parameters.scala:56:69]
wire [4:0] _InclusiveCache_inner_TLBuffer_auto_out_e_bits_sink; // @[Parameters.scala:56:69]
wire _l2_auto_in_a_ready; // @[Configs.scala:93:24]
wire _l2_auto_in_b_valid; // @[Configs.scala:93:24]
wire [1:0] _l2_auto_in_b_bits_param; // @[Configs.scala:93:24]
wire [31:0] _l2_auto_in_b_bits_address; // @[Configs.scala:93:24]
wire _l2_auto_in_c_ready; // @[Configs.scala:93:24]
wire _l2_auto_in_d_valid; // @[Configs.scala:93:24]
wire [2:0] _l2_auto_in_d_bits_opcode; // @[Configs.scala:93:24]
wire [1:0] _l2_auto_in_d_bits_param; // @[Configs.scala:93:24]
wire [2:0] _l2_auto_in_d_bits_size; // @[Configs.scala:93:24]
wire [7:0] _l2_auto_in_d_bits_source; // @[Configs.scala:93:24]
wire [4:0] _l2_auto_in_d_bits_sink; // @[Configs.scala:93:24]
wire _l2_auto_in_d_bits_denied; // @[Configs.scala:93:24]
wire [255:0] _l2_auto_in_d_bits_data; // @[Configs.scala:93:24]
wire _l2_auto_in_d_bits_corrupt; // @[Configs.scala:93:24]
wire auto_coupler_to_bus_named_mbus_bus_xing_out_a_ready_0 = auto_coupler_to_bus_named_mbus_bus_xing_out_a_ready; // @[ClockDomain.scala:14:9]
wire auto_coupler_to_bus_named_mbus_bus_xing_out_d_valid_0 = auto_coupler_to_bus_named_mbus_bus_xing_out_d_valid; // @[ClockDomain.scala:14:9]
wire [2:0] auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_opcode_0 = auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_opcode; // @[ClockDomain.scala:14:9]
wire [1:0] auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_param_0 = auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_param; // @[ClockDomain.scala:14:9]
wire [2:0] auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_size_0 = auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_size; // @[ClockDomain.scala:14:9]
wire [5:0] auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_source_0 = auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_source; // @[ClockDomain.scala:14:9]
wire auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_sink_0 = auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_sink; // @[ClockDomain.scala:14:9]
wire auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_denied_0 = auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_denied; // @[ClockDomain.scala:14:9]
wire [63:0] auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_data_0 = auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_data; // @[ClockDomain.scala:14:9]
wire auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_corrupt_0 = auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_corrupt; // @[ClockDomain.scala:14:9]
wire auto_coherent_jbar_anon_in_a_valid_0 = auto_coherent_jbar_anon_in_a_valid; // @[ClockDomain.scala:14:9]
wire [2:0] auto_coherent_jbar_anon_in_a_bits_opcode_0 = auto_coherent_jbar_anon_in_a_bits_opcode; // @[ClockDomain.scala:14:9]
wire [2:0] auto_coherent_jbar_anon_in_a_bits_param_0 = auto_coherent_jbar_anon_in_a_bits_param; // @[ClockDomain.scala:14:9]
wire [2:0] auto_coherent_jbar_anon_in_a_bits_size_0 = auto_coherent_jbar_anon_in_a_bits_size; // @[ClockDomain.scala:14:9]
wire [7:0] auto_coherent_jbar_anon_in_a_bits_source_0 = auto_coherent_jbar_anon_in_a_bits_source; // @[ClockDomain.scala:14:9]
wire [31:0] auto_coherent_jbar_anon_in_a_bits_address_0 = auto_coherent_jbar_anon_in_a_bits_address; // @[ClockDomain.scala:14:9]
wire [31:0] auto_coherent_jbar_anon_in_a_bits_mask_0 = auto_coherent_jbar_anon_in_a_bits_mask; // @[ClockDomain.scala:14:9]
wire [255:0] auto_coherent_jbar_anon_in_a_bits_data_0 = auto_coherent_jbar_anon_in_a_bits_data; // @[ClockDomain.scala:14:9]
wire auto_coherent_jbar_anon_in_a_bits_corrupt_0 = auto_coherent_jbar_anon_in_a_bits_corrupt; // @[ClockDomain.scala:14:9]
wire auto_coherent_jbar_anon_in_b_ready_0 = auto_coherent_jbar_anon_in_b_ready; // @[ClockDomain.scala:14:9]
wire auto_coherent_jbar_anon_in_c_valid_0 = auto_coherent_jbar_anon_in_c_valid; // @[ClockDomain.scala:14:9]
wire [2:0] auto_coherent_jbar_anon_in_c_bits_opcode_0 = auto_coherent_jbar_anon_in_c_bits_opcode; // @[ClockDomain.scala:14:9]
wire [2:0] auto_coherent_jbar_anon_in_c_bits_param_0 = auto_coherent_jbar_anon_in_c_bits_param; // @[ClockDomain.scala:14:9]
wire [2:0] auto_coherent_jbar_anon_in_c_bits_size_0 = auto_coherent_jbar_anon_in_c_bits_size; // @[ClockDomain.scala:14:9]
wire [7:0] auto_coherent_jbar_anon_in_c_bits_source_0 = auto_coherent_jbar_anon_in_c_bits_source; // @[ClockDomain.scala:14:9]
wire [31:0] auto_coherent_jbar_anon_in_c_bits_address_0 = auto_coherent_jbar_anon_in_c_bits_address; // @[ClockDomain.scala:14:9]
wire [255:0] auto_coherent_jbar_anon_in_c_bits_data_0 = auto_coherent_jbar_anon_in_c_bits_data; // @[ClockDomain.scala:14:9]
wire auto_coherent_jbar_anon_in_c_bits_corrupt_0 = auto_coherent_jbar_anon_in_c_bits_corrupt; // @[ClockDomain.scala:14:9]
wire auto_coherent_jbar_anon_in_d_ready_0 = auto_coherent_jbar_anon_in_d_ready; // @[ClockDomain.scala:14:9]
wire auto_coherent_jbar_anon_in_e_valid_0 = auto_coherent_jbar_anon_in_e_valid; // @[ClockDomain.scala:14:9]
wire [4:0] auto_coherent_jbar_anon_in_e_bits_sink_0 = auto_coherent_jbar_anon_in_e_bits_sink; // @[ClockDomain.scala:14:9]
wire auto_l2_ctrls_ctrl_in_a_valid_0 = auto_l2_ctrls_ctrl_in_a_valid; // @[ClockDomain.scala:14:9]
wire [2:0] auto_l2_ctrls_ctrl_in_a_bits_opcode_0 = auto_l2_ctrls_ctrl_in_a_bits_opcode; // @[ClockDomain.scala:14:9]
wire [2:0] auto_l2_ctrls_ctrl_in_a_bits_param_0 = auto_l2_ctrls_ctrl_in_a_bits_param; // @[ClockDomain.scala:14:9]
wire [1:0] auto_l2_ctrls_ctrl_in_a_bits_size_0 = auto_l2_ctrls_ctrl_in_a_bits_size; // @[ClockDomain.scala:14:9]
wire [12:0] auto_l2_ctrls_ctrl_in_a_bits_source_0 = auto_l2_ctrls_ctrl_in_a_bits_source; // @[ClockDomain.scala:14:9]
wire [25:0] auto_l2_ctrls_ctrl_in_a_bits_address_0 = auto_l2_ctrls_ctrl_in_a_bits_address; // @[ClockDomain.scala:14:9]
wire [7:0] auto_l2_ctrls_ctrl_in_a_bits_mask_0 = auto_l2_ctrls_ctrl_in_a_bits_mask; // @[ClockDomain.scala:14:9]
wire [63:0] auto_l2_ctrls_ctrl_in_a_bits_data_0 = auto_l2_ctrls_ctrl_in_a_bits_data; // @[ClockDomain.scala:14:9]
wire auto_l2_ctrls_ctrl_in_a_bits_corrupt_0 = auto_l2_ctrls_ctrl_in_a_bits_corrupt; // @[ClockDomain.scala:14:9]
wire auto_l2_ctrls_ctrl_in_d_ready_0 = auto_l2_ctrls_ctrl_in_d_ready; // @[ClockDomain.scala:14:9]
wire auto_coh_clock_groups_in_member_coh_0_clock_0 = auto_coh_clock_groups_in_member_coh_0_clock; // @[ClockDomain.scala:14:9]
wire auto_coh_clock_groups_in_member_coh_0_reset_0 = auto_coh_clock_groups_in_member_coh_0_reset; // @[ClockDomain.scala:14:9]
wire [2:0] auto_coherent_jbar_anon_in_b_bits_opcode = 3'h6; // @[ClockDomain.scala:14:9]
wire [2:0] auto_coherent_jbar_anon_in_b_bits_size = 3'h6; // @[ClockDomain.scala:14:9]
wire [2:0] filter_auto_anon_in_b_bits_opcode = 3'h6; // @[Filter.scala:60:9]
wire [2:0] filter_auto_anon_in_b_bits_size = 3'h6; // @[Filter.scala:60:9]
wire [2:0] filter_auto_anon_out_b_bits_opcode = 3'h6; // @[Filter.scala:60:9]
wire [2:0] filter_auto_anon_out_b_bits_size = 3'h6; // @[Filter.scala:60:9]
wire [2:0] filter_anonOut_b_bits_opcode = 3'h6; // @[MixedNode.scala:542:17]
wire [2:0] filter_anonOut_b_bits_size = 3'h6; // @[MixedNode.scala:542:17]
wire [2:0] filter_anonIn_b_bits_opcode = 3'h6; // @[MixedNode.scala:551:17]
wire [2:0] filter_anonIn_b_bits_size = 3'h6; // @[MixedNode.scala:551:17]
wire [2:0] coherent_jbar_auto_anon_in_b_bits_opcode = 3'h6; // @[Jbar.scala:44:9]
wire [2:0] coherent_jbar_auto_anon_in_b_bits_size = 3'h6; // @[Jbar.scala:44:9]
wire [2:0] coherent_jbar_auto_anon_out_b_bits_opcode = 3'h6; // @[Jbar.scala:44:9]
wire [2:0] coherent_jbar_auto_anon_out_b_bits_size = 3'h6; // @[Jbar.scala:44:9]
wire [2:0] coherent_jbar_anonOut_b_bits_opcode = 3'h6; // @[MixedNode.scala:542:17]
wire [2:0] coherent_jbar_anonOut_b_bits_size = 3'h6; // @[MixedNode.scala:542:17]
wire [2:0] coherent_jbar_anonIn_b_bits_opcode = 3'h6; // @[MixedNode.scala:551:17]
wire [2:0] coherent_jbar_anonIn_b_bits_size = 3'h6; // @[MixedNode.scala:551:17]
wire [2:0] coherent_jbar_in_0_b_bits_opcode = 3'h6; // @[Xbar.scala:159:18]
wire [2:0] coherent_jbar_in_0_b_bits_size = 3'h6; // @[Xbar.scala:159:18]
wire [2:0] coherent_jbar_out_0_b_bits_opcode = 3'h6; // @[Xbar.scala:216:19]
wire [2:0] coherent_jbar_out_0_b_bits_size = 3'h6; // @[Xbar.scala:216:19]
wire [2:0] coherent_jbar_portsBIO_filtered_0_bits_opcode = 3'h6; // @[Xbar.scala:352:24]
wire [2:0] coherent_jbar_portsBIO_filtered_0_bits_size = 3'h6; // @[Xbar.scala:352:24]
wire [7:0] auto_coherent_jbar_anon_in_b_bits_source = 8'h40; // @[ClockDomain.scala:14:9]
wire [7:0] filter_auto_anon_in_b_bits_source = 8'h40; // @[Filter.scala:60:9]
wire [7:0] filter_auto_anon_out_b_bits_source = 8'h40; // @[Filter.scala:60:9]
wire [7:0] filter_anonOut_b_bits_source = 8'h40; // @[MixedNode.scala:542:17]
wire [7:0] filter_anonIn_b_bits_source = 8'h40; // @[MixedNode.scala:551:17]
wire [7:0] coherent_jbar_auto_anon_in_b_bits_source = 8'h40; // @[Jbar.scala:44:9]
wire [7:0] coherent_jbar_auto_anon_out_b_bits_source = 8'h40; // @[Jbar.scala:44:9]
wire [7:0] coherent_jbar_anonOut_b_bits_source = 8'h40; // @[MixedNode.scala:542:17]
wire [7:0] coherent_jbar_anonIn_b_bits_source = 8'h40; // @[MixedNode.scala:551:17]
wire [7:0] coherent_jbar_in_0_b_bits_source = 8'h40; // @[Xbar.scala:159:18]
wire [7:0] coherent_jbar__anonIn_b_bits_source_T = 8'h40; // @[Xbar.scala:156:69]
wire [7:0] coherent_jbar_out_0_b_bits_source = 8'h40; // @[Xbar.scala:216:19]
wire [7:0] coherent_jbar__requestBOI_uncommonBits_T = 8'h40; // @[Parameters.scala:52:29]
wire [7:0] coherent_jbar_requestBOI_uncommonBits = 8'h40; // @[Parameters.scala:52:56]
wire [7:0] coherent_jbar_portsBIO_filtered_0_bits_source = 8'h40; // @[Xbar.scala:352:24]
wire [31:0] auto_coherent_jbar_anon_in_b_bits_mask = 32'hFFFFFFFF; // @[ClockDomain.scala:14:9]
wire [31:0] filter_auto_anon_in_b_bits_mask = 32'hFFFFFFFF; // @[Filter.scala:60:9]
wire [31:0] filter_auto_anon_out_b_bits_mask = 32'hFFFFFFFF; // @[Filter.scala:60:9]
wire [31:0] filter_anonOut_b_bits_mask = 32'hFFFFFFFF; // @[MixedNode.scala:542:17]
wire [31:0] filter_anonIn_b_bits_mask = 32'hFFFFFFFF; // @[MixedNode.scala:551:17]
wire [31:0] coherent_jbar_auto_anon_in_b_bits_mask = 32'hFFFFFFFF; // @[Jbar.scala:44:9]
wire [31:0] coherent_jbar_auto_anon_out_b_bits_mask = 32'hFFFFFFFF; // @[Jbar.scala:44:9]
wire [31:0] coherent_jbar_anonOut_b_bits_mask = 32'hFFFFFFFF; // @[MixedNode.scala:542:17]
wire [31:0] coherent_jbar_anonIn_b_bits_mask = 32'hFFFFFFFF; // @[MixedNode.scala:551:17]
wire [31:0] coherent_jbar_in_0_b_bits_mask = 32'hFFFFFFFF; // @[Xbar.scala:159:18]
wire [31:0] coherent_jbar_out_0_b_bits_mask = 32'hFFFFFFFF; // @[Xbar.scala:216:19]
wire [31:0] coherent_jbar_portsBIO_filtered_0_bits_mask = 32'hFFFFFFFF; // @[Xbar.scala:352:24]
wire [255:0] auto_coherent_jbar_anon_in_b_bits_data = 256'h0; // @[ClockDomain.scala:14:9]
wire [255:0] filter_auto_anon_in_b_bits_data = 256'h0; // @[Filter.scala:60:9]
wire [255:0] filter_auto_anon_out_b_bits_data = 256'h0; // @[Filter.scala:60:9]
wire [255:0] filter_anonOut_b_bits_data = 256'h0; // @[MixedNode.scala:542:17]
wire [255:0] filter_anonIn_b_bits_data = 256'h0; // @[MixedNode.scala:551:17]
wire [255:0] coherent_jbar_auto_anon_in_b_bits_data = 256'h0; // @[Jbar.scala:44:9]
wire [255:0] coherent_jbar_auto_anon_out_b_bits_data = 256'h0; // @[Jbar.scala:44:9]
wire [255:0] coherent_jbar_anonOut_b_bits_data = 256'h0; // @[MixedNode.scala:542:17]
wire [255:0] coherent_jbar_anonIn_b_bits_data = 256'h0; // @[MixedNode.scala:551:17]
wire [255:0] coherent_jbar_in_0_b_bits_data = 256'h0; // @[Xbar.scala:159:18]
wire [255:0] coherent_jbar_out_0_b_bits_data = 256'h0; // @[Xbar.scala:216:19]
wire [255:0] coherent_jbar_portsBIO_filtered_0_bits_data = 256'h0; // @[Xbar.scala:352:24]
wire auto_coherent_jbar_anon_in_b_bits_corrupt = 1'h0; // @[ClockDomain.scala:14:9]
wire auto_l2_ctrls_ctrl_in_d_bits_sink = 1'h0; // @[ClockDomain.scala:14:9]
wire auto_l2_ctrls_ctrl_in_d_bits_denied = 1'h0; // @[ClockDomain.scala:14:9]
wire auto_l2_ctrls_ctrl_in_d_bits_corrupt = 1'h0; // @[ClockDomain.scala:14:9]
wire _childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25]
wire coh_clock_groups_childClock = 1'h0; // @[LazyModuleImp.scala:155:31]
wire coh_clock_groups_childReset = 1'h0; // @[LazyModuleImp.scala:158:31]
wire coh_clock_groups__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25]
wire clockGroup_childClock = 1'h0; // @[LazyModuleImp.scala:155:31]
wire clockGroup_childReset = 1'h0; // @[LazyModuleImp.scala:158:31]
wire clockGroup__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25]
wire fixedClockNode_childClock = 1'h0; // @[LazyModuleImp.scala:155:31]
wire fixedClockNode_childReset = 1'h0; // @[LazyModuleImp.scala:158:31]
wire fixedClockNode__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25]
wire broadcast_childClock = 1'h0; // @[LazyModuleImp.scala:155:31]
wire broadcast_childReset = 1'h0; // @[LazyModuleImp.scala:158:31]
wire broadcast__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25]
wire filter_auto_anon_in_b_bits_corrupt = 1'h0; // @[Filter.scala:60:9]
wire filter_auto_anon_out_b_bits_corrupt = 1'h0; // @[Filter.scala:60:9]
wire filter_anonOut_b_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17]
wire filter_anonIn_b_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17]
wire InclusiveCache_outer_TLBuffer_auto_in_b_valid = 1'h0; // @[Buffer.scala:40:9]
wire InclusiveCache_outer_TLBuffer_auto_in_b_bits_corrupt = 1'h0; // @[Buffer.scala:40:9]
wire InclusiveCache_outer_TLBuffer_auto_out_b_valid = 1'h0; // @[Buffer.scala:40:9]
wire InclusiveCache_outer_TLBuffer_auto_out_b_bits_corrupt = 1'h0; // @[Buffer.scala:40:9]
wire InclusiveCache_outer_TLBuffer_nodeOut_b_valid = 1'h0; // @[MixedNode.scala:542:17]
wire InclusiveCache_outer_TLBuffer_nodeOut_b_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17]
wire InclusiveCache_outer_TLBuffer_nodeIn_b_valid = 1'h0; // @[MixedNode.scala:551:17]
wire InclusiveCache_outer_TLBuffer_nodeIn_b_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17]
wire coherent_jbar_auto_anon_in_b_bits_corrupt = 1'h0; // @[Jbar.scala:44:9]
wire coherent_jbar_auto_anon_out_b_bits_corrupt = 1'h0; // @[Jbar.scala:44:9]
wire coherent_jbar_anonOut_b_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17]
wire coherent_jbar_anonIn_b_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17]
wire coherent_jbar_in_0_b_bits_corrupt = 1'h0; // @[Xbar.scala:159:18]
wire coherent_jbar_out_0_b_bits_corrupt = 1'h0; // @[Xbar.scala:216:19]
wire coherent_jbar__requestBOI_T = 1'h0; // @[Parameters.scala:54:10]
wire coherent_jbar__requestDOI_T = 1'h0; // @[Parameters.scala:54:10]
wire coherent_jbar__requestEIO_T = 1'h0; // @[Parameters.scala:54:10]
wire coherent_jbar_beatsBO_opdata = 1'h0; // @[Edges.scala:97:28]
wire coherent_jbar_beatsBO_0 = 1'h0; // @[Edges.scala:221:14]
wire coherent_jbar_portsBIO_filtered_0_bits_corrupt = 1'h0; // @[Xbar.scala:352:24]
wire auto_coherent_jbar_anon_in_e_ready = 1'h1; // @[ClockDomain.scala:14:9]
wire filter_auto_anon_in_e_ready = 1'h1; // @[Filter.scala:60:9]
wire filter_auto_anon_out_e_ready = 1'h1; // @[Filter.scala:60:9]
wire filter_anonOut_e_ready = 1'h1; // @[MixedNode.scala:542:17]
wire filter_anonIn_e_ready = 1'h1; // @[MixedNode.scala:551:17]
wire InclusiveCache_outer_TLBuffer_auto_in_b_ready = 1'h1; // @[Buffer.scala:40:9]
wire InclusiveCache_outer_TLBuffer_auto_in_e_ready = 1'h1; // @[Buffer.scala:40:9]
wire InclusiveCache_outer_TLBuffer_auto_out_b_ready = 1'h1; // @[Buffer.scala:40:9]
wire InclusiveCache_outer_TLBuffer_auto_out_e_ready = 1'h1; // @[Buffer.scala:40:9]
wire InclusiveCache_outer_TLBuffer_nodeOut_b_ready = 1'h1; // @[MixedNode.scala:542:17]
wire InclusiveCache_outer_TLBuffer_nodeOut_e_ready = 1'h1; // @[MixedNode.scala:542:17]
wire InclusiveCache_outer_TLBuffer_nodeIn_b_ready = 1'h1; // @[MixedNode.scala:551:17]
wire InclusiveCache_outer_TLBuffer_nodeIn_e_ready = 1'h1; // @[MixedNode.scala:551:17]
wire coherent_jbar_auto_anon_in_e_ready = 1'h1; // @[Jbar.scala:44:9]
wire coherent_jbar_auto_anon_out_e_ready = 1'h1; // @[Jbar.scala:44:9]
wire coherent_jbar_anonOut_e_ready = 1'h1; // @[MixedNode.scala:542:17]
wire coherent_jbar_anonIn_e_ready = 1'h1; // @[MixedNode.scala:551:17]
wire coherent_jbar_in_0_e_ready = 1'h1; // @[Xbar.scala:159:18]
wire coherent_jbar_out_0_e_ready = 1'h1; // @[Xbar.scala:216:19]
wire coherent_jbar__requestAIO_T_4 = 1'h1; // @[Parameters.scala:137:59]
wire coherent_jbar_requestAIO_0_0 = 1'h1; // @[Xbar.scala:307:107]
wire coherent_jbar__requestCIO_T_4 = 1'h1; // @[Parameters.scala:137:59]
wire coherent_jbar_requestCIO_0_0 = 1'h1; // @[Xbar.scala:308:107]
wire coherent_jbar__requestBOI_T_1 = 1'h1; // @[Parameters.scala:54:32]
wire coherent_jbar__requestBOI_T_2 = 1'h1; // @[Parameters.scala:56:32]
wire coherent_jbar__requestBOI_T_3 = 1'h1; // @[Parameters.scala:54:67]
wire coherent_jbar__requestBOI_T_4 = 1'h1; // @[Parameters.scala:57:20]
wire coherent_jbar_requestBOI_0_0 = 1'h1; // @[Parameters.scala:56:48]
wire coherent_jbar__requestDOI_T_1 = 1'h1; // @[Parameters.scala:54:32]
wire coherent_jbar__requestDOI_T_2 = 1'h1; // @[Parameters.scala:56:32]
wire coherent_jbar__requestDOI_T_3 = 1'h1; // @[Parameters.scala:54:67]
wire coherent_jbar__requestDOI_T_4 = 1'h1; // @[Parameters.scala:57:20]
wire coherent_jbar_requestDOI_0_0 = 1'h1; // @[Parameters.scala:56:48]
wire coherent_jbar__requestEIO_T_1 = 1'h1; // @[Parameters.scala:54:32]
wire coherent_jbar__requestEIO_T_2 = 1'h1; // @[Parameters.scala:56:32]
wire coherent_jbar__requestEIO_T_3 = 1'h1; // @[Parameters.scala:54:67]
wire coherent_jbar__requestEIO_T_4 = 1'h1; // @[Parameters.scala:57:20]
wire coherent_jbar_requestEIO_0_0 = 1'h1; // @[Parameters.scala:56:48]
wire coherent_jbar_beatsBO_decode = 1'h1; // @[Edges.scala:220:59]
wire coherent_jbar__beatsBO_opdata_T = 1'h1; // @[Edges.scala:97:37]
wire coherent_jbar__portsAOI_filtered_0_valid_T = 1'h1; // @[Xbar.scala:355:54]
wire coherent_jbar__portsBIO_filtered_0_valid_T = 1'h1; // @[Xbar.scala:355:54]
wire coherent_jbar__portsCOI_filtered_0_valid_T = 1'h1; // @[Xbar.scala:355:54]
wire coherent_jbar__portsDIO_filtered_0_valid_T = 1'h1; // @[Xbar.scala:355:54]
wire coherent_jbar_portsEOI_filtered_0_ready = 1'h1; // @[Xbar.scala:352:24]
wire coherent_jbar__portsEOI_filtered_0_valid_T = 1'h1; // @[Xbar.scala:355:54]
wire [1:0] auto_l2_ctrls_ctrl_in_d_bits_param = 2'h0; // @[ClockDomain.scala:14:9]
wire [1:0] InclusiveCache_outer_TLBuffer_auto_in_b_bits_param = 2'h0; // @[Buffer.scala:40:9]
wire [1:0] InclusiveCache_outer_TLBuffer_auto_out_b_bits_param = 2'h0; // @[Buffer.scala:40:9]
wire [1:0] InclusiveCache_outer_TLBuffer_nodeOut_b_bits_param = 2'h0; // @[MixedNode.scala:542:17]
wire [1:0] InclusiveCache_outer_TLBuffer_nodeIn_b_bits_param = 2'h0; // @[MixedNode.scala:551:17]
wire [5:0] coherent_jbar__beatsBO_decode_T_2 = 6'h3F; // @[package.scala:243:46]
wire [5:0] coherent_jbar__beatsBO_decode_T_1 = 6'h0; // @[package.scala:243:76]
wire [12:0] coherent_jbar__beatsBO_decode_T = 13'hFC0; // @[package.scala:243:71]
wire [2:0] InclusiveCache_outer_TLBuffer_auto_in_b_bits_opcode = 3'h0; // @[Buffer.scala:40:9]
wire [2:0] InclusiveCache_outer_TLBuffer_auto_in_b_bits_size = 3'h0; // @[Buffer.scala:40:9]
wire [2:0] InclusiveCache_outer_TLBuffer_auto_out_b_bits_opcode = 3'h0; // @[Buffer.scala:40:9]
wire [2:0] InclusiveCache_outer_TLBuffer_auto_out_b_bits_size = 3'h0; // @[Buffer.scala:40:9]
wire [2:0] InclusiveCache_outer_TLBuffer_nodeOut_b_bits_opcode = 3'h0; // @[MixedNode.scala:542:17]
wire [2:0] InclusiveCache_outer_TLBuffer_nodeOut_b_bits_size = 3'h0; // @[MixedNode.scala:542:17]
wire [2:0] InclusiveCache_outer_TLBuffer_nodeIn_b_bits_opcode = 3'h0; // @[MixedNode.scala:551:17]
wire [2:0] InclusiveCache_outer_TLBuffer_nodeIn_b_bits_size = 3'h0; // @[MixedNode.scala:551:17]
wire [4:0] InclusiveCache_outer_TLBuffer_auto_in_b_bits_source = 5'h0; // @[Buffer.scala:40:9]
wire [4:0] InclusiveCache_outer_TLBuffer_auto_out_b_bits_source = 5'h0; // @[Buffer.scala:40:9]
wire [4:0] InclusiveCache_outer_TLBuffer_nodeOut_b_bits_source = 5'h0; // @[MixedNode.scala:542:17]
wire [4:0] InclusiveCache_outer_TLBuffer_nodeIn_b_bits_source = 5'h0; // @[MixedNode.scala:551:17]
wire [31:0] InclusiveCache_outer_TLBuffer_auto_in_b_bits_address = 32'h0; // @[Buffer.scala:40:9]
wire [31:0] InclusiveCache_outer_TLBuffer_auto_out_b_bits_address = 32'h0; // @[Buffer.scala:40:9]
wire [31:0] InclusiveCache_outer_TLBuffer_nodeOut_b_bits_address = 32'h0; // @[MixedNode.scala:542:17]
wire [31:0] InclusiveCache_outer_TLBuffer_nodeIn_b_bits_address = 32'h0; // @[MixedNode.scala:551:17]
wire [7:0] InclusiveCache_outer_TLBuffer_auto_in_b_bits_mask = 8'h0; // @[Buffer.scala:40:9]
wire [7:0] InclusiveCache_outer_TLBuffer_auto_out_b_bits_mask = 8'h0; // @[Buffer.scala:40:9]
wire [7:0] InclusiveCache_outer_TLBuffer_nodeOut_b_bits_mask = 8'h0; // @[MixedNode.scala:542:17]
wire [7:0] InclusiveCache_outer_TLBuffer_nodeIn_b_bits_mask = 8'h0; // @[MixedNode.scala:551:17]
wire [63:0] InclusiveCache_outer_TLBuffer_auto_in_b_bits_data = 64'h0; // @[Buffer.scala:40:9]
wire [63:0] InclusiveCache_outer_TLBuffer_auto_out_b_bits_data = 64'h0; // @[Buffer.scala:40:9]
wire [63:0] InclusiveCache_outer_TLBuffer_nodeOut_b_bits_data = 64'h0; // @[MixedNode.scala:542:17]
wire [63:0] InclusiveCache_outer_TLBuffer_nodeIn_b_bits_data = 64'h0; // @[MixedNode.scala:551:17]
wire [32:0] coherent_jbar__requestAIO_T_2 = 33'h0; // @[Parameters.scala:137:46]
wire [32:0] coherent_jbar__requestAIO_T_3 = 33'h0; // @[Parameters.scala:137:46]
wire [32:0] coherent_jbar__requestCIO_T_2 = 33'h0; // @[Parameters.scala:137:46]
wire [32:0] coherent_jbar__requestCIO_T_3 = 33'h0; // @[Parameters.scala:137:46]
wire coupler_to_bus_named_mbus_auto_bus_xing_out_a_ready = auto_coupler_to_bus_named_mbus_bus_xing_out_a_ready_0; // @[ClockDomain.scala:14:9]
wire coupler_to_bus_named_mbus_auto_bus_xing_out_a_valid; // @[LazyModuleImp.scala:138:7]
wire [2:0] coupler_to_bus_named_mbus_auto_bus_xing_out_a_bits_opcode; // @[LazyModuleImp.scala:138:7]
wire [2:0] coupler_to_bus_named_mbus_auto_bus_xing_out_a_bits_param; // @[LazyModuleImp.scala:138:7]
wire [2:0] coupler_to_bus_named_mbus_auto_bus_xing_out_a_bits_size; // @[LazyModuleImp.scala:138:7]
wire [5:0] coupler_to_bus_named_mbus_auto_bus_xing_out_a_bits_source; // @[LazyModuleImp.scala:138:7]
wire [31:0] coupler_to_bus_named_mbus_auto_bus_xing_out_a_bits_address; // @[LazyModuleImp.scala:138:7]
wire [7:0] coupler_to_bus_named_mbus_auto_bus_xing_out_a_bits_mask; // @[LazyModuleImp.scala:138:7]
wire [63:0] coupler_to_bus_named_mbus_auto_bus_xing_out_a_bits_data; // @[LazyModuleImp.scala:138:7]
wire coupler_to_bus_named_mbus_auto_bus_xing_out_a_bits_corrupt; // @[LazyModuleImp.scala:138:7]
wire coupler_to_bus_named_mbus_auto_bus_xing_out_d_ready; // @[LazyModuleImp.scala:138:7]
wire coupler_to_bus_named_mbus_auto_bus_xing_out_d_valid = auto_coupler_to_bus_named_mbus_bus_xing_out_d_valid_0; // @[ClockDomain.scala:14:9]
wire [2:0] coupler_to_bus_named_mbus_auto_bus_xing_out_d_bits_opcode = auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_opcode_0; // @[ClockDomain.scala:14:9]
wire [1:0] coupler_to_bus_named_mbus_auto_bus_xing_out_d_bits_param = auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_param_0; // @[ClockDomain.scala:14:9]
wire [2:0] coupler_to_bus_named_mbus_auto_bus_xing_out_d_bits_size = auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_size_0; // @[ClockDomain.scala:14:9]
wire [5:0] coupler_to_bus_named_mbus_auto_bus_xing_out_d_bits_source = auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_source_0; // @[ClockDomain.scala:14:9]
wire coupler_to_bus_named_mbus_auto_bus_xing_out_d_bits_sink = auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_sink_0; // @[ClockDomain.scala:14:9]
wire coupler_to_bus_named_mbus_auto_bus_xing_out_d_bits_denied = auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_denied_0; // @[ClockDomain.scala:14:9]
wire [63:0] coupler_to_bus_named_mbus_auto_bus_xing_out_d_bits_data = auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_data_0; // @[ClockDomain.scala:14:9]
wire coherent_jbar_auto_anon_in_a_ready; // @[Jbar.scala:44:9]
wire coupler_to_bus_named_mbus_auto_bus_xing_out_d_bits_corrupt = auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_corrupt_0; // @[ClockDomain.scala:14:9]
wire coherent_jbar_auto_anon_in_a_valid = auto_coherent_jbar_anon_in_a_valid_0; // @[Jbar.scala:44:9]
wire [2:0] coherent_jbar_auto_anon_in_a_bits_opcode = auto_coherent_jbar_anon_in_a_bits_opcode_0; // @[Jbar.scala:44:9]
wire [2:0] coherent_jbar_auto_anon_in_a_bits_param = auto_coherent_jbar_anon_in_a_bits_param_0; // @[Jbar.scala:44:9]
wire [2:0] coherent_jbar_auto_anon_in_a_bits_size = auto_coherent_jbar_anon_in_a_bits_size_0; // @[Jbar.scala:44:9]
wire [7:0] coherent_jbar_auto_anon_in_a_bits_source = auto_coherent_jbar_anon_in_a_bits_source_0; // @[Jbar.scala:44:9]
wire [31:0] coherent_jbar_auto_anon_in_a_bits_address = auto_coherent_jbar_anon_in_a_bits_address_0; // @[Jbar.scala:44:9]
wire [31:0] coherent_jbar_auto_anon_in_a_bits_mask = auto_coherent_jbar_anon_in_a_bits_mask_0; // @[Jbar.scala:44:9]
wire [255:0] coherent_jbar_auto_anon_in_a_bits_data = auto_coherent_jbar_anon_in_a_bits_data_0; // @[Jbar.scala:44:9]
wire coherent_jbar_auto_anon_in_a_bits_corrupt = auto_coherent_jbar_anon_in_a_bits_corrupt_0; // @[Jbar.scala:44:9]
wire coherent_jbar_auto_anon_in_b_ready = auto_coherent_jbar_anon_in_b_ready_0; // @[Jbar.scala:44:9]
wire coherent_jbar_auto_anon_in_b_valid; // @[Jbar.scala:44:9]
wire [1:0] coherent_jbar_auto_anon_in_b_bits_param; // @[Jbar.scala:44:9]
wire [31:0] coherent_jbar_auto_anon_in_b_bits_address; // @[Jbar.scala:44:9]
wire coherent_jbar_auto_anon_in_c_ready; // @[Jbar.scala:44:9]
wire coherent_jbar_auto_anon_in_c_valid = auto_coherent_jbar_anon_in_c_valid_0; // @[Jbar.scala:44:9]
wire [2:0] coherent_jbar_auto_anon_in_c_bits_opcode = auto_coherent_jbar_anon_in_c_bits_opcode_0; // @[Jbar.scala:44:9]
wire [2:0] coherent_jbar_auto_anon_in_c_bits_param = auto_coherent_jbar_anon_in_c_bits_param_0; // @[Jbar.scala:44:9]
wire [2:0] coherent_jbar_auto_anon_in_c_bits_size = auto_coherent_jbar_anon_in_c_bits_size_0; // @[Jbar.scala:44:9]
wire [7:0] coherent_jbar_auto_anon_in_c_bits_source = auto_coherent_jbar_anon_in_c_bits_source_0; // @[Jbar.scala:44:9]
wire [31:0] coherent_jbar_auto_anon_in_c_bits_address = auto_coherent_jbar_anon_in_c_bits_address_0; // @[Jbar.scala:44:9]
wire [255:0] coherent_jbar_auto_anon_in_c_bits_data = auto_coherent_jbar_anon_in_c_bits_data_0; // @[Jbar.scala:44:9]
wire coherent_jbar_auto_anon_in_c_bits_corrupt = auto_coherent_jbar_anon_in_c_bits_corrupt_0; // @[Jbar.scala:44:9]
wire coherent_jbar_auto_anon_in_d_ready = auto_coherent_jbar_anon_in_d_ready_0; // @[Jbar.scala:44:9]
wire coherent_jbar_auto_anon_in_d_valid; // @[Jbar.scala:44:9]
wire [2:0] coherent_jbar_auto_anon_in_d_bits_opcode; // @[Jbar.scala:44:9]
wire [1:0] coherent_jbar_auto_anon_in_d_bits_param; // @[Jbar.scala:44:9]
wire [2:0] coherent_jbar_auto_anon_in_d_bits_size; // @[Jbar.scala:44:9]
wire [7:0] coherent_jbar_auto_anon_in_d_bits_source; // @[Jbar.scala:44:9]
wire [4:0] coherent_jbar_auto_anon_in_d_bits_sink; // @[Jbar.scala:44:9]
wire coherent_jbar_auto_anon_in_d_bits_denied; // @[Jbar.scala:44:9]
wire [255:0] coherent_jbar_auto_anon_in_d_bits_data; // @[Jbar.scala:44:9]
wire coherent_jbar_auto_anon_in_d_bits_corrupt; // @[Jbar.scala:44:9]
wire coherent_jbar_auto_anon_in_e_valid = auto_coherent_jbar_anon_in_e_valid_0; // @[Jbar.scala:44:9]
wire [4:0] coherent_jbar_auto_anon_in_e_bits_sink = auto_coherent_jbar_anon_in_e_bits_sink_0; // @[Jbar.scala:44:9]
wire coh_clock_groups_auto_in_member_coh_0_clock = auto_coh_clock_groups_in_member_coh_0_clock_0; // @[ClockGroup.scala:53:9]
wire coh_clock_groups_auto_in_member_coh_0_reset = auto_coh_clock_groups_in_member_coh_0_reset_0; // @[ClockGroup.scala:53:9]
wire [2:0] auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_opcode_0; // @[ClockDomain.scala:14:9]
wire [2:0] auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_param_0; // @[ClockDomain.scala:14:9]
wire [2:0] auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_size_0; // @[ClockDomain.scala:14:9]
wire [5:0] auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_source_0; // @[ClockDomain.scala:14:9]
wire [31:0] auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_address_0; // @[ClockDomain.scala:14:9]
wire [7:0] auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_mask_0; // @[ClockDomain.scala:14:9]
wire [63:0] auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_data_0; // @[ClockDomain.scala:14:9]
wire auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_corrupt_0; // @[ClockDomain.scala:14:9]
wire auto_coupler_to_bus_named_mbus_bus_xing_out_a_valid_0; // @[ClockDomain.scala:14:9]
wire auto_coupler_to_bus_named_mbus_bus_xing_out_d_ready_0; // @[ClockDomain.scala:14:9]
wire auto_coherent_jbar_anon_in_a_ready_0; // @[ClockDomain.scala:14:9]
wire [1:0] auto_coherent_jbar_anon_in_b_bits_param_0; // @[ClockDomain.scala:14:9]
wire [31:0] auto_coherent_jbar_anon_in_b_bits_address_0; // @[ClockDomain.scala:14:9]
wire auto_coherent_jbar_anon_in_b_valid_0; // @[ClockDomain.scala:14:9]
wire auto_coherent_jbar_anon_in_c_ready_0; // @[ClockDomain.scala:14:9]
wire [2:0] auto_coherent_jbar_anon_in_d_bits_opcode_0; // @[ClockDomain.scala:14:9]
wire [1:0] auto_coherent_jbar_anon_in_d_bits_param_0; // @[ClockDomain.scala:14:9]
wire [2:0] auto_coherent_jbar_anon_in_d_bits_size_0; // @[ClockDomain.scala:14:9]
wire [7:0] auto_coherent_jbar_anon_in_d_bits_source_0; // @[ClockDomain.scala:14:9]
wire [4:0] auto_coherent_jbar_anon_in_d_bits_sink_0; // @[ClockDomain.scala:14:9]
wire auto_coherent_jbar_anon_in_d_bits_denied_0; // @[ClockDomain.scala:14:9]
wire [255:0] auto_coherent_jbar_anon_in_d_bits_data_0; // @[ClockDomain.scala:14:9]
wire auto_coherent_jbar_anon_in_d_bits_corrupt_0; // @[ClockDomain.scala:14:9]
wire auto_coherent_jbar_anon_in_d_valid_0; // @[ClockDomain.scala:14:9]
wire auto_l2_ctrls_ctrl_in_a_ready_0; // @[ClockDomain.scala:14:9]
wire [2:0] auto_l2_ctrls_ctrl_in_d_bits_opcode_0; // @[ClockDomain.scala:14:9]
wire [1:0] auto_l2_ctrls_ctrl_in_d_bits_size_0; // @[ClockDomain.scala:14:9]
wire [12:0] auto_l2_ctrls_ctrl_in_d_bits_source_0; // @[ClockDomain.scala:14:9]
wire [63:0] auto_l2_ctrls_ctrl_in_d_bits_data_0; // @[ClockDomain.scala:14:9]
wire auto_l2_ctrls_ctrl_in_d_valid_0; // @[ClockDomain.scala:14:9]
wire clockSinkNodeIn_clock; // @[MixedNode.scala:551:17]
wire clockSinkNodeIn_reset; // @[MixedNode.scala:551:17]
wire childClock; // @[LazyModuleImp.scala:155:31]
wire childReset; // @[LazyModuleImp.scala:158:31]
wire coh_clock_groups_nodeIn_member_coh_0_clock = coh_clock_groups_auto_in_member_coh_0_clock; // @[ClockGroup.scala:53:9]
wire coh_clock_groups_nodeOut_member_coh_0_clock; // @[MixedNode.scala:542:17]
wire coh_clock_groups_nodeIn_member_coh_0_reset = coh_clock_groups_auto_in_member_coh_0_reset; // @[ClockGroup.scala:53:9]
wire coh_clock_groups_nodeOut_member_coh_0_reset; // @[MixedNode.scala:542:17]
wire clockGroup_auto_in_member_coh_0_clock = coh_clock_groups_auto_out_member_coh_0_clock; // @[ClockGroup.scala:24:9, :53:9]
wire clockGroup_auto_in_member_coh_0_reset = coh_clock_groups_auto_out_member_coh_0_reset; // @[ClockGroup.scala:24:9, :53:9]
assign coh_clock_groups_auto_out_member_coh_0_clock = coh_clock_groups_nodeOut_member_coh_0_clock; // @[ClockGroup.scala:53:9]
assign coh_clock_groups_auto_out_member_coh_0_reset = coh_clock_groups_nodeOut_member_coh_0_reset; // @[ClockGroup.scala:53:9]
assign coh_clock_groups_nodeOut_member_coh_0_clock = coh_clock_groups_nodeIn_member_coh_0_clock; // @[MixedNode.scala:542:17, :551:17]
assign coh_clock_groups_nodeOut_member_coh_0_reset = coh_clock_groups_nodeIn_member_coh_0_reset; // @[MixedNode.scala:542:17, :551:17]
wire clockGroup_nodeIn_member_coh_0_clock = clockGroup_auto_in_member_coh_0_clock; // @[ClockGroup.scala:24:9]
wire clockGroup_nodeOut_clock; // @[MixedNode.scala:542:17]
wire clockGroup_nodeIn_member_coh_0_reset = clockGroup_auto_in_member_coh_0_reset; // @[ClockGroup.scala:24:9]
wire clockGroup_nodeOut_reset; // @[MixedNode.scala:542:17]
wire fixedClockNode_auto_anon_in_clock = clockGroup_auto_out_clock; // @[ClockGroup.scala:24:9, :104:9]
wire fixedClockNode_auto_anon_in_reset = clockGroup_auto_out_reset; // @[ClockGroup.scala:24:9, :104:9]
assign clockGroup_auto_out_clock = clockGroup_nodeOut_clock; // @[ClockGroup.scala:24:9]
assign clockGroup_auto_out_reset = clockGroup_nodeOut_reset; // @[ClockGroup.scala:24:9]
assign clockGroup_nodeOut_clock = clockGroup_nodeIn_member_coh_0_clock; // @[MixedNode.scala:542:17, :551:17]
assign clockGroup_nodeOut_reset = clockGroup_nodeIn_member_coh_0_reset; // @[MixedNode.scala:542:17, :551:17]
wire fixedClockNode_anonIn_clock = fixedClockNode_auto_anon_in_clock; // @[ClockGroup.scala:104:9]
wire fixedClockNode_anonOut_clock; // @[MixedNode.scala:542:17]
wire fixedClockNode_anonIn_reset = fixedClockNode_auto_anon_in_reset; // @[ClockGroup.scala:104:9]
wire fixedClockNode_anonOut_reset; // @[MixedNode.scala:542:17]
assign clockSinkNodeIn_clock = fixedClockNode_auto_anon_out_clock; // @[ClockGroup.scala:104:9]
assign clockSinkNodeIn_reset = fixedClockNode_auto_anon_out_reset; // @[ClockGroup.scala:104:9]
assign fixedClockNode_auto_anon_out_clock = fixedClockNode_anonOut_clock; // @[ClockGroup.scala:104:9]
assign fixedClockNode_auto_anon_out_reset = fixedClockNode_anonOut_reset; // @[ClockGroup.scala:104:9]
assign fixedClockNode_anonOut_clock = fixedClockNode_anonIn_clock; // @[MixedNode.scala:542:17, :551:17]
assign fixedClockNode_anonOut_reset = fixedClockNode_anonIn_reset; // @[MixedNode.scala:542:17, :551:17]
wire filter_anonIn_a_ready; // @[MixedNode.scala:551:17]
wire coherent_jbar_auto_anon_out_a_ready = filter_auto_anon_in_a_ready; // @[Jbar.scala:44:9]
wire coherent_jbar_auto_anon_out_a_valid; // @[Jbar.scala:44:9]
wire filter_anonIn_a_valid = filter_auto_anon_in_a_valid; // @[Filter.scala:60:9]
wire [2:0] coherent_jbar_auto_anon_out_a_bits_opcode; // @[Jbar.scala:44:9]
wire [2:0] filter_anonIn_a_bits_opcode = filter_auto_anon_in_a_bits_opcode; // @[Filter.scala:60:9]
wire [2:0] coherent_jbar_auto_anon_out_a_bits_param; // @[Jbar.scala:44:9]
wire [2:0] filter_anonIn_a_bits_param = filter_auto_anon_in_a_bits_param; // @[Filter.scala:60:9]
wire [2:0] coherent_jbar_auto_anon_out_a_bits_size; // @[Jbar.scala:44:9]
wire [2:0] filter_anonIn_a_bits_size = filter_auto_anon_in_a_bits_size; // @[Filter.scala:60:9]
wire [7:0] coherent_jbar_auto_anon_out_a_bits_source; // @[Jbar.scala:44:9]
wire [7:0] filter_anonIn_a_bits_source = filter_auto_anon_in_a_bits_source; // @[Filter.scala:60:9]
wire [31:0] coherent_jbar_auto_anon_out_a_bits_address; // @[Jbar.scala:44:9]
wire [31:0] filter_anonIn_a_bits_address = filter_auto_anon_in_a_bits_address; // @[Filter.scala:60:9]
wire [31:0] coherent_jbar_auto_anon_out_a_bits_mask; // @[Jbar.scala:44:9]
wire [31:0] filter_anonIn_a_bits_mask = filter_auto_anon_in_a_bits_mask; // @[Filter.scala:60:9]
wire [255:0] coherent_jbar_auto_anon_out_a_bits_data; // @[Jbar.scala:44:9]
wire [255:0] filter_anonIn_a_bits_data = filter_auto_anon_in_a_bits_data; // @[Filter.scala:60:9]
wire coherent_jbar_auto_anon_out_a_bits_corrupt; // @[Jbar.scala:44:9]
wire filter_anonIn_a_bits_corrupt = filter_auto_anon_in_a_bits_corrupt; // @[Filter.scala:60:9]
wire coherent_jbar_auto_anon_out_b_ready; // @[Jbar.scala:44:9]
wire filter_anonIn_b_ready = filter_auto_anon_in_b_ready; // @[Filter.scala:60:9]
wire filter_anonIn_b_valid; // @[MixedNode.scala:551:17]
wire coherent_jbar_auto_anon_out_b_valid = filter_auto_anon_in_b_valid; // @[Jbar.scala:44:9]
wire [1:0] filter_anonIn_b_bits_param; // @[MixedNode.scala:551:17]
wire [1:0] coherent_jbar_auto_anon_out_b_bits_param = filter_auto_anon_in_b_bits_param; // @[Jbar.scala:44:9]
wire [31:0] filter_anonIn_b_bits_address; // @[MixedNode.scala:551:17]
wire [31:0] coherent_jbar_auto_anon_out_b_bits_address = filter_auto_anon_in_b_bits_address; // @[Jbar.scala:44:9]
wire filter_anonIn_c_ready; // @[MixedNode.scala:551:17]
wire coherent_jbar_auto_anon_out_c_ready = filter_auto_anon_in_c_ready; // @[Jbar.scala:44:9]
wire coherent_jbar_auto_anon_out_c_valid; // @[Jbar.scala:44:9]
wire filter_anonIn_c_valid = filter_auto_anon_in_c_valid; // @[Filter.scala:60:9]
wire [2:0] coherent_jbar_auto_anon_out_c_bits_opcode; // @[Jbar.scala:44:9]
wire [2:0] filter_anonIn_c_bits_opcode = filter_auto_anon_in_c_bits_opcode; // @[Filter.scala:60:9]
wire [2:0] coherent_jbar_auto_anon_out_c_bits_param; // @[Jbar.scala:44:9]
wire [2:0] filter_anonIn_c_bits_param = filter_auto_anon_in_c_bits_param; // @[Filter.scala:60:9]
wire [2:0] coherent_jbar_auto_anon_out_c_bits_size; // @[Jbar.scala:44:9]
wire [2:0] filter_anonIn_c_bits_size = filter_auto_anon_in_c_bits_size; // @[Filter.scala:60:9]
wire [7:0] coherent_jbar_auto_anon_out_c_bits_source; // @[Jbar.scala:44:9]
wire [7:0] filter_anonIn_c_bits_source = filter_auto_anon_in_c_bits_source; // @[Filter.scala:60:9]
wire [31:0] coherent_jbar_auto_anon_out_c_bits_address; // @[Jbar.scala:44:9]
wire [31:0] filter_anonIn_c_bits_address = filter_auto_anon_in_c_bits_address; // @[Filter.scala:60:9]
wire [255:0] coherent_jbar_auto_anon_out_c_bits_data; // @[Jbar.scala:44:9]
wire [255:0] filter_anonIn_c_bits_data = filter_auto_anon_in_c_bits_data; // @[Filter.scala:60:9]
wire coherent_jbar_auto_anon_out_c_bits_corrupt; // @[Jbar.scala:44:9]
wire filter_anonIn_c_bits_corrupt = filter_auto_anon_in_c_bits_corrupt; // @[Filter.scala:60:9]
wire coherent_jbar_auto_anon_out_d_ready; // @[Jbar.scala:44:9]
wire filter_anonIn_d_ready = filter_auto_anon_in_d_ready; // @[Filter.scala:60:9]
wire filter_anonIn_d_valid; // @[MixedNode.scala:551:17]
wire [2:0] filter_anonIn_d_bits_opcode; // @[MixedNode.scala:551:17]
wire coherent_jbar_auto_anon_out_d_valid = filter_auto_anon_in_d_valid; // @[Jbar.scala:44:9]
wire [1:0] filter_anonIn_d_bits_param; // @[MixedNode.scala:551:17]
wire [2:0] coherent_jbar_auto_anon_out_d_bits_opcode = filter_auto_anon_in_d_bits_opcode; // @[Jbar.scala:44:9]
wire [2:0] filter_anonIn_d_bits_size; // @[MixedNode.scala:551:17]
wire [1:0] coherent_jbar_auto_anon_out_d_bits_param = filter_auto_anon_in_d_bits_param; // @[Jbar.scala:44:9]
wire [7:0] filter_anonIn_d_bits_source; // @[MixedNode.scala:551:17]
wire [2:0] coherent_jbar_auto_anon_out_d_bits_size = filter_auto_anon_in_d_bits_size; // @[Jbar.scala:44:9]
wire [4:0] filter_anonIn_d_bits_sink; // @[MixedNode.scala:551:17]
wire [7:0] coherent_jbar_auto_anon_out_d_bits_source = filter_auto_anon_in_d_bits_source; // @[Jbar.scala:44:9]
wire filter_anonIn_d_bits_denied; // @[MixedNode.scala:551:17]
wire [4:0] coherent_jbar_auto_anon_out_d_bits_sink = filter_auto_anon_in_d_bits_sink; // @[Jbar.scala:44:9]
wire [255:0] filter_anonIn_d_bits_data; // @[MixedNode.scala:551:17]
wire coherent_jbar_auto_anon_out_d_bits_denied = filter_auto_anon_in_d_bits_denied; // @[Jbar.scala:44:9]
wire filter_anonIn_d_bits_corrupt; // @[MixedNode.scala:551:17]
wire [255:0] coherent_jbar_auto_anon_out_d_bits_data = filter_auto_anon_in_d_bits_data; // @[Jbar.scala:44:9]
wire coherent_jbar_auto_anon_out_d_bits_corrupt = filter_auto_anon_in_d_bits_corrupt; // @[Jbar.scala:44:9]
wire coherent_jbar_auto_anon_out_e_valid; // @[Jbar.scala:44:9]
wire filter_anonIn_e_valid = filter_auto_anon_in_e_valid; // @[Filter.scala:60:9]
wire [4:0] coherent_jbar_auto_anon_out_e_bits_sink; // @[Jbar.scala:44:9]
wire [4:0] filter_anonIn_e_bits_sink = filter_auto_anon_in_e_bits_sink; // @[Filter.scala:60:9]
wire filter_anonOut_a_ready = filter_auto_anon_out_a_ready; // @[Filter.scala:60:9]
wire filter_anonOut_a_valid; // @[MixedNode.scala:542:17]
wire [2:0] filter_anonOut_a_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] filter_anonOut_a_bits_param; // @[MixedNode.scala:542:17]
wire [2:0] filter_anonOut_a_bits_size; // @[MixedNode.scala:542:17]
wire [7:0] filter_anonOut_a_bits_source; // @[MixedNode.scala:542:17]
wire [31:0] filter_anonOut_a_bits_address; // @[MixedNode.scala:542:17]
wire [31:0] filter_anonOut_a_bits_mask; // @[MixedNode.scala:542:17]
wire [255:0] filter_anonOut_a_bits_data; // @[MixedNode.scala:542:17]
wire filter_anonOut_a_bits_corrupt; // @[MixedNode.scala:542:17]
wire filter_anonOut_b_ready; // @[MixedNode.scala:542:17]
wire filter_anonOut_b_valid = filter_auto_anon_out_b_valid; // @[Filter.scala:60:9]
wire [1:0] filter_anonOut_b_bits_param = filter_auto_anon_out_b_bits_param; // @[Filter.scala:60:9]
wire [31:0] filter_anonOut_b_bits_address = filter_auto_anon_out_b_bits_address; // @[Filter.scala:60:9]
wire filter_anonOut_c_ready = filter_auto_anon_out_c_ready; // @[Filter.scala:60:9]
wire filter_anonOut_c_valid; // @[MixedNode.scala:542:17]
wire [2:0] filter_anonOut_c_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] filter_anonOut_c_bits_param; // @[MixedNode.scala:542:17]
wire [2:0] filter_anonOut_c_bits_size; // @[MixedNode.scala:542:17]
wire [7:0] filter_anonOut_c_bits_source; // @[MixedNode.scala:542:17]
wire [31:0] filter_anonOut_c_bits_address; // @[MixedNode.scala:542:17]
wire [255:0] filter_anonOut_c_bits_data; // @[MixedNode.scala:542:17]
wire filter_anonOut_c_bits_corrupt; // @[MixedNode.scala:542:17]
wire filter_anonOut_d_ready; // @[MixedNode.scala:542:17]
wire filter_anonOut_d_valid = filter_auto_anon_out_d_valid; // @[Filter.scala:60:9]
wire [2:0] filter_anonOut_d_bits_opcode = filter_auto_anon_out_d_bits_opcode; // @[Filter.scala:60:9]
wire [1:0] filter_anonOut_d_bits_param = filter_auto_anon_out_d_bits_param; // @[Filter.scala:60:9]
wire [2:0] filter_anonOut_d_bits_size = filter_auto_anon_out_d_bits_size; // @[Filter.scala:60:9]
wire [7:0] filter_anonOut_d_bits_source = filter_auto_anon_out_d_bits_source; // @[Filter.scala:60:9]
wire [4:0] filter_anonOut_d_bits_sink = filter_auto_anon_out_d_bits_sink; // @[Filter.scala:60:9]
wire filter_anonOut_d_bits_denied = filter_auto_anon_out_d_bits_denied; // @[Filter.scala:60:9]
wire [255:0] filter_anonOut_d_bits_data = filter_auto_anon_out_d_bits_data; // @[Filter.scala:60:9]
wire filter_anonOut_d_bits_corrupt = filter_auto_anon_out_d_bits_corrupt; // @[Filter.scala:60:9]
wire filter_anonOut_e_valid; // @[MixedNode.scala:542:17]
wire [4:0] filter_anonOut_e_bits_sink; // @[MixedNode.scala:542:17]
wire [2:0] filter_auto_anon_out_a_bits_opcode; // @[Filter.scala:60:9]
wire [2:0] filter_auto_anon_out_a_bits_param; // @[Filter.scala:60:9]
wire [2:0] filter_auto_anon_out_a_bits_size; // @[Filter.scala:60:9]
wire [7:0] filter_auto_anon_out_a_bits_source; // @[Filter.scala:60:9]
wire [31:0] filter_auto_anon_out_a_bits_address; // @[Filter.scala:60:9]
wire [31:0] filter_auto_anon_out_a_bits_mask; // @[Filter.scala:60:9]
wire [255:0] filter_auto_anon_out_a_bits_data; // @[Filter.scala:60:9]
wire filter_auto_anon_out_a_bits_corrupt; // @[Filter.scala:60:9]
wire filter_auto_anon_out_a_valid; // @[Filter.scala:60:9]
wire filter_auto_anon_out_b_ready; // @[Filter.scala:60:9]
wire [2:0] filter_auto_anon_out_c_bits_opcode; // @[Filter.scala:60:9]
wire [2:0] filter_auto_anon_out_c_bits_param; // @[Filter.scala:60:9]
wire [2:0] filter_auto_anon_out_c_bits_size; // @[Filter.scala:60:9]
wire [7:0] filter_auto_anon_out_c_bits_source; // @[Filter.scala:60:9]
wire [31:0] filter_auto_anon_out_c_bits_address; // @[Filter.scala:60:9]
wire [255:0] filter_auto_anon_out_c_bits_data; // @[Filter.scala:60:9]
wire filter_auto_anon_out_c_bits_corrupt; // @[Filter.scala:60:9]
wire filter_auto_anon_out_c_valid; // @[Filter.scala:60:9]
wire filter_auto_anon_out_d_ready; // @[Filter.scala:60:9]
wire [4:0] filter_auto_anon_out_e_bits_sink; // @[Filter.scala:60:9]
wire filter_auto_anon_out_e_valid; // @[Filter.scala:60:9]
assign filter_anonIn_a_ready = filter_anonOut_a_ready; // @[MixedNode.scala:542:17, :551:17]
assign filter_auto_anon_out_a_valid = filter_anonOut_a_valid; // @[Filter.scala:60:9]
assign filter_auto_anon_out_a_bits_opcode = filter_anonOut_a_bits_opcode; // @[Filter.scala:60:9]
assign filter_auto_anon_out_a_bits_param = filter_anonOut_a_bits_param; // @[Filter.scala:60:9]
assign filter_auto_anon_out_a_bits_size = filter_anonOut_a_bits_size; // @[Filter.scala:60:9]
assign filter_auto_anon_out_a_bits_source = filter_anonOut_a_bits_source; // @[Filter.scala:60:9]
assign filter_auto_anon_out_a_bits_address = filter_anonOut_a_bits_address; // @[Filter.scala:60:9]
assign filter_auto_anon_out_a_bits_mask = filter_anonOut_a_bits_mask; // @[Filter.scala:60:9]
assign filter_auto_anon_out_a_bits_data = filter_anonOut_a_bits_data; // @[Filter.scala:60:9]
assign filter_auto_anon_out_a_bits_corrupt = filter_anonOut_a_bits_corrupt; // @[Filter.scala:60:9]
assign filter_auto_anon_out_b_ready = filter_anonOut_b_ready; // @[Filter.scala:60:9]
assign filter_anonIn_b_valid = filter_anonOut_b_valid; // @[MixedNode.scala:542:17, :551:17]
assign filter_anonIn_b_bits_param = filter_anonOut_b_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign filter_anonIn_b_bits_address = filter_anonOut_b_bits_address; // @[MixedNode.scala:542:17, :551:17]
assign filter_anonIn_c_ready = filter_anonOut_c_ready; // @[MixedNode.scala:542:17, :551:17]
assign filter_auto_anon_out_c_valid = filter_anonOut_c_valid; // @[Filter.scala:60:9]
assign filter_auto_anon_out_c_bits_opcode = filter_anonOut_c_bits_opcode; // @[Filter.scala:60:9]
assign filter_auto_anon_out_c_bits_param = filter_anonOut_c_bits_param; // @[Filter.scala:60:9]
assign filter_auto_anon_out_c_bits_size = filter_anonOut_c_bits_size; // @[Filter.scala:60:9]
assign filter_auto_anon_out_c_bits_source = filter_anonOut_c_bits_source; // @[Filter.scala:60:9]
assign filter_auto_anon_out_c_bits_address = filter_anonOut_c_bits_address; // @[Filter.scala:60:9]
assign filter_auto_anon_out_c_bits_data = filter_anonOut_c_bits_data; // @[Filter.scala:60:9]
assign filter_auto_anon_out_c_bits_corrupt = filter_anonOut_c_bits_corrupt; // @[Filter.scala:60:9]
assign filter_auto_anon_out_d_ready = filter_anonOut_d_ready; // @[Filter.scala:60:9]
assign filter_anonIn_d_valid = filter_anonOut_d_valid; // @[MixedNode.scala:542:17, :551:17]
assign filter_anonIn_d_bits_opcode = filter_anonOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign filter_anonIn_d_bits_param = filter_anonOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign filter_anonIn_d_bits_size = filter_anonOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign filter_anonIn_d_bits_source = filter_anonOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign filter_anonIn_d_bits_sink = filter_anonOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17]
assign filter_anonIn_d_bits_denied = filter_anonOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17]
assign filter_anonIn_d_bits_data = filter_anonOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign filter_anonIn_d_bits_corrupt = filter_anonOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign filter_auto_anon_out_e_valid = filter_anonOut_e_valid; // @[Filter.scala:60:9]
assign filter_auto_anon_out_e_bits_sink = filter_anonOut_e_bits_sink; // @[Filter.scala:60:9]
assign filter_auto_anon_in_a_ready = filter_anonIn_a_ready; // @[Filter.scala:60:9]
assign filter_anonOut_a_valid = filter_anonIn_a_valid; // @[MixedNode.scala:542:17, :551:17]
assign filter_anonOut_a_bits_opcode = filter_anonIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign filter_anonOut_a_bits_param = filter_anonIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign filter_anonOut_a_bits_size = filter_anonIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign filter_anonOut_a_bits_source = filter_anonIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign filter_anonOut_a_bits_address = filter_anonIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17]
assign filter_anonOut_a_bits_mask = filter_anonIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17]
assign filter_anonOut_a_bits_data = filter_anonIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign filter_anonOut_a_bits_corrupt = filter_anonIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign filter_anonOut_b_ready = filter_anonIn_b_ready; // @[MixedNode.scala:542:17, :551:17]
assign filter_auto_anon_in_b_valid = filter_anonIn_b_valid; // @[Filter.scala:60:9]
assign filter_auto_anon_in_b_bits_param = filter_anonIn_b_bits_param; // @[Filter.scala:60:9]
assign filter_auto_anon_in_b_bits_address = filter_anonIn_b_bits_address; // @[Filter.scala:60:9]
assign filter_auto_anon_in_c_ready = filter_anonIn_c_ready; // @[Filter.scala:60:9]
assign filter_anonOut_c_valid = filter_anonIn_c_valid; // @[MixedNode.scala:542:17, :551:17]
assign filter_anonOut_c_bits_opcode = filter_anonIn_c_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign filter_anonOut_c_bits_param = filter_anonIn_c_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign filter_anonOut_c_bits_size = filter_anonIn_c_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign filter_anonOut_c_bits_source = filter_anonIn_c_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign filter_anonOut_c_bits_address = filter_anonIn_c_bits_address; // @[MixedNode.scala:542:17, :551:17]
assign filter_anonOut_c_bits_data = filter_anonIn_c_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign filter_anonOut_c_bits_corrupt = filter_anonIn_c_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign filter_anonOut_d_ready = filter_anonIn_d_ready; // @[MixedNode.scala:542:17, :551:17]
assign filter_auto_anon_in_d_valid = filter_anonIn_d_valid; // @[Filter.scala:60:9]
assign filter_auto_anon_in_d_bits_opcode = filter_anonIn_d_bits_opcode; // @[Filter.scala:60:9]
assign filter_auto_anon_in_d_bits_param = filter_anonIn_d_bits_param; // @[Filter.scala:60:9]
assign filter_auto_anon_in_d_bits_size = filter_anonIn_d_bits_size; // @[Filter.scala:60:9]
assign filter_auto_anon_in_d_bits_source = filter_anonIn_d_bits_source; // @[Filter.scala:60:9]
assign filter_auto_anon_in_d_bits_sink = filter_anonIn_d_bits_sink; // @[Filter.scala:60:9]
assign filter_auto_anon_in_d_bits_denied = filter_anonIn_d_bits_denied; // @[Filter.scala:60:9]
assign filter_auto_anon_in_d_bits_data = filter_anonIn_d_bits_data; // @[Filter.scala:60:9]
assign filter_auto_anon_in_d_bits_corrupt = filter_anonIn_d_bits_corrupt; // @[Filter.scala:60:9]
assign filter_anonOut_e_valid = filter_anonIn_e_valid; // @[MixedNode.scala:542:17, :551:17]
assign filter_anonOut_e_bits_sink = filter_anonIn_e_bits_sink; // @[MixedNode.scala:542:17, :551:17]
wire InclusiveCache_outer_TLBuffer_nodeIn_a_ready; // @[MixedNode.scala:551:17]
wire InclusiveCache_outer_TLBuffer_nodeIn_a_valid = InclusiveCache_outer_TLBuffer_auto_in_a_valid; // @[Buffer.scala:40:9]
wire [2:0] InclusiveCache_outer_TLBuffer_nodeIn_a_bits_opcode = InclusiveCache_outer_TLBuffer_auto_in_a_bits_opcode; // @[Buffer.scala:40:9]
wire [2:0] InclusiveCache_outer_TLBuffer_nodeIn_a_bits_param = InclusiveCache_outer_TLBuffer_auto_in_a_bits_param; // @[Buffer.scala:40:9]
wire [2:0] InclusiveCache_outer_TLBuffer_nodeIn_a_bits_size = InclusiveCache_outer_TLBuffer_auto_in_a_bits_size; // @[Buffer.scala:40:9]
wire [4:0] InclusiveCache_outer_TLBuffer_nodeIn_a_bits_source = InclusiveCache_outer_TLBuffer_auto_in_a_bits_source; // @[Buffer.scala:40:9]
wire [31:0] InclusiveCache_outer_TLBuffer_nodeIn_a_bits_address = InclusiveCache_outer_TLBuffer_auto_in_a_bits_address; // @[Buffer.scala:40:9]
wire [7:0] InclusiveCache_outer_TLBuffer_nodeIn_a_bits_mask = InclusiveCache_outer_TLBuffer_auto_in_a_bits_mask; // @[Buffer.scala:40:9]
wire [63:0] InclusiveCache_outer_TLBuffer_nodeIn_a_bits_data = InclusiveCache_outer_TLBuffer_auto_in_a_bits_data; // @[Buffer.scala:40:9]
wire InclusiveCache_outer_TLBuffer_nodeIn_a_bits_corrupt = InclusiveCache_outer_TLBuffer_auto_in_a_bits_corrupt; // @[Buffer.scala:40:9]
wire InclusiveCache_outer_TLBuffer_nodeIn_c_ready; // @[MixedNode.scala:551:17]
wire InclusiveCache_outer_TLBuffer_nodeIn_c_valid = InclusiveCache_outer_TLBuffer_auto_in_c_valid; // @[Buffer.scala:40:9]
wire [2:0] InclusiveCache_outer_TLBuffer_nodeIn_c_bits_opcode = InclusiveCache_outer_TLBuffer_auto_in_c_bits_opcode; // @[Buffer.scala:40:9]
wire [2:0] InclusiveCache_outer_TLBuffer_nodeIn_c_bits_param = InclusiveCache_outer_TLBuffer_auto_in_c_bits_param; // @[Buffer.scala:40:9]
wire [2:0] InclusiveCache_outer_TLBuffer_nodeIn_c_bits_size = InclusiveCache_outer_TLBuffer_auto_in_c_bits_size; // @[Buffer.scala:40:9]
wire [4:0] InclusiveCache_outer_TLBuffer_nodeIn_c_bits_source = InclusiveCache_outer_TLBuffer_auto_in_c_bits_source; // @[Buffer.scala:40:9]
wire [31:0] InclusiveCache_outer_TLBuffer_nodeIn_c_bits_address = InclusiveCache_outer_TLBuffer_auto_in_c_bits_address; // @[Buffer.scala:40:9]
wire [63:0] InclusiveCache_outer_TLBuffer_nodeIn_c_bits_data = InclusiveCache_outer_TLBuffer_auto_in_c_bits_data; // @[Buffer.scala:40:9]
wire InclusiveCache_outer_TLBuffer_nodeIn_c_bits_corrupt = InclusiveCache_outer_TLBuffer_auto_in_c_bits_corrupt; // @[Buffer.scala:40:9]
wire InclusiveCache_outer_TLBuffer_nodeIn_d_ready = InclusiveCache_outer_TLBuffer_auto_in_d_ready; // @[Buffer.scala:40:9]
wire InclusiveCache_outer_TLBuffer_nodeIn_d_valid; // @[MixedNode.scala:551:17]
wire [2:0] InclusiveCache_outer_TLBuffer_nodeIn_d_bits_opcode; // @[MixedNode.scala:551:17]
wire [1:0] InclusiveCache_outer_TLBuffer_nodeIn_d_bits_param; // @[MixedNode.scala:551:17]
wire [2:0] InclusiveCache_outer_TLBuffer_nodeIn_d_bits_size; // @[MixedNode.scala:551:17]
wire [4:0] InclusiveCache_outer_TLBuffer_nodeIn_d_bits_source; // @[MixedNode.scala:551:17]
wire [2:0] InclusiveCache_outer_TLBuffer_nodeIn_d_bits_sink; // @[MixedNode.scala:551:17]
wire InclusiveCache_outer_TLBuffer_nodeIn_d_bits_denied; // @[MixedNode.scala:551:17]
wire [63:0] InclusiveCache_outer_TLBuffer_nodeIn_d_bits_data; // @[MixedNode.scala:551:17]
wire InclusiveCache_outer_TLBuffer_nodeIn_d_bits_corrupt; // @[MixedNode.scala:551:17]
wire InclusiveCache_outer_TLBuffer_nodeIn_e_valid = InclusiveCache_outer_TLBuffer_auto_in_e_valid; // @[Buffer.scala:40:9]
wire [2:0] InclusiveCache_outer_TLBuffer_nodeIn_e_bits_sink = InclusiveCache_outer_TLBuffer_auto_in_e_bits_sink; // @[Buffer.scala:40:9]
wire InclusiveCache_outer_TLBuffer_nodeOut_a_ready = InclusiveCache_outer_TLBuffer_auto_out_a_ready; // @[Buffer.scala:40:9]
wire InclusiveCache_outer_TLBuffer_nodeOut_a_valid; // @[MixedNode.scala:542:17]
wire [2:0] InclusiveCache_outer_TLBuffer_nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] InclusiveCache_outer_TLBuffer_nodeOut_a_bits_param; // @[MixedNode.scala:542:17]
wire [2:0] InclusiveCache_outer_TLBuffer_nodeOut_a_bits_size; // @[MixedNode.scala:542:17]
wire [4:0] InclusiveCache_outer_TLBuffer_nodeOut_a_bits_source; // @[MixedNode.scala:542:17]
wire [31:0] InclusiveCache_outer_TLBuffer_nodeOut_a_bits_address; // @[MixedNode.scala:542:17]
wire [7:0] InclusiveCache_outer_TLBuffer_nodeOut_a_bits_mask; // @[MixedNode.scala:542:17]
wire [63:0] InclusiveCache_outer_TLBuffer_nodeOut_a_bits_data; // @[MixedNode.scala:542:17]
wire InclusiveCache_outer_TLBuffer_nodeOut_a_bits_corrupt; // @[MixedNode.scala:542:17]
wire InclusiveCache_outer_TLBuffer_nodeOut_c_ready = InclusiveCache_outer_TLBuffer_auto_out_c_ready; // @[Buffer.scala:40:9]
wire InclusiveCache_outer_TLBuffer_nodeOut_c_valid; // @[MixedNode.scala:542:17]
wire [2:0] InclusiveCache_outer_TLBuffer_nodeOut_c_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] InclusiveCache_outer_TLBuffer_nodeOut_c_bits_param; // @[MixedNode.scala:542:17]
wire [2:0] InclusiveCache_outer_TLBuffer_nodeOut_c_bits_size; // @[MixedNode.scala:542:17]
wire [4:0] InclusiveCache_outer_TLBuffer_nodeOut_c_bits_source; // @[MixedNode.scala:542:17]
wire [31:0] InclusiveCache_outer_TLBuffer_nodeOut_c_bits_address; // @[MixedNode.scala:542:17]
wire [63:0] InclusiveCache_outer_TLBuffer_nodeOut_c_bits_data; // @[MixedNode.scala:542:17]
wire InclusiveCache_outer_TLBuffer_nodeOut_c_bits_corrupt; // @[MixedNode.scala:542:17]
wire InclusiveCache_outer_TLBuffer_nodeOut_d_ready; // @[MixedNode.scala:542:17]
wire InclusiveCache_outer_TLBuffer_nodeOut_d_valid = InclusiveCache_outer_TLBuffer_auto_out_d_valid; // @[Buffer.scala:40:9]
wire [2:0] InclusiveCache_outer_TLBuffer_nodeOut_d_bits_opcode = InclusiveCache_outer_TLBuffer_auto_out_d_bits_opcode; // @[Buffer.scala:40:9]
wire [1:0] InclusiveCache_outer_TLBuffer_nodeOut_d_bits_param = InclusiveCache_outer_TLBuffer_auto_out_d_bits_param; // @[Buffer.scala:40:9]
wire [2:0] InclusiveCache_outer_TLBuffer_nodeOut_d_bits_size = InclusiveCache_outer_TLBuffer_auto_out_d_bits_size; // @[Buffer.scala:40:9]
wire [4:0] InclusiveCache_outer_TLBuffer_nodeOut_d_bits_source = InclusiveCache_outer_TLBuffer_auto_out_d_bits_source; // @[Buffer.scala:40:9]
wire [2:0] InclusiveCache_outer_TLBuffer_nodeOut_d_bits_sink = InclusiveCache_outer_TLBuffer_auto_out_d_bits_sink; // @[Buffer.scala:40:9]
wire InclusiveCache_outer_TLBuffer_nodeOut_d_bits_denied = InclusiveCache_outer_TLBuffer_auto_out_d_bits_denied; // @[Buffer.scala:40:9]
wire [63:0] InclusiveCache_outer_TLBuffer_nodeOut_d_bits_data = InclusiveCache_outer_TLBuffer_auto_out_d_bits_data; // @[Buffer.scala:40:9]
wire InclusiveCache_outer_TLBuffer_nodeOut_d_bits_corrupt = InclusiveCache_outer_TLBuffer_auto_out_d_bits_corrupt; // @[Buffer.scala:40:9]
wire InclusiveCache_outer_TLBuffer_nodeOut_e_valid; // @[MixedNode.scala:542:17]
wire [2:0] InclusiveCache_outer_TLBuffer_nodeOut_e_bits_sink; // @[MixedNode.scala:542:17]
wire InclusiveCache_outer_TLBuffer_auto_in_a_ready; // @[Buffer.scala:40:9]
wire InclusiveCache_outer_TLBuffer_auto_in_c_ready; // @[Buffer.scala:40:9]
wire [2:0] InclusiveCache_outer_TLBuffer_auto_in_d_bits_opcode; // @[Buffer.scala:40:9]
wire [1:0] InclusiveCache_outer_TLBuffer_auto_in_d_bits_param; // @[Buffer.scala:40:9]
wire [2:0] InclusiveCache_outer_TLBuffer_auto_in_d_bits_size; // @[Buffer.scala:40:9]
wire [4:0] InclusiveCache_outer_TLBuffer_auto_in_d_bits_source; // @[Buffer.scala:40:9]
wire [2:0] InclusiveCache_outer_TLBuffer_auto_in_d_bits_sink; // @[Buffer.scala:40:9]
wire InclusiveCache_outer_TLBuffer_auto_in_d_bits_denied; // @[Buffer.scala:40:9]
wire [63:0] InclusiveCache_outer_TLBuffer_auto_in_d_bits_data; // @[Buffer.scala:40:9]
wire InclusiveCache_outer_TLBuffer_auto_in_d_bits_corrupt; // @[Buffer.scala:40:9]
wire InclusiveCache_outer_TLBuffer_auto_in_d_valid; // @[Buffer.scala:40:9]
wire [2:0] InclusiveCache_outer_TLBuffer_auto_out_a_bits_opcode; // @[Buffer.scala:40:9]
wire [2:0] InclusiveCache_outer_TLBuffer_auto_out_a_bits_param; // @[Buffer.scala:40:9]
wire [2:0] InclusiveCache_outer_TLBuffer_auto_out_a_bits_size; // @[Buffer.scala:40:9]
wire [4:0] InclusiveCache_outer_TLBuffer_auto_out_a_bits_source; // @[Buffer.scala:40:9]
wire [31:0] InclusiveCache_outer_TLBuffer_auto_out_a_bits_address; // @[Buffer.scala:40:9]
wire [7:0] InclusiveCache_outer_TLBuffer_auto_out_a_bits_mask; // @[Buffer.scala:40:9]
wire [63:0] InclusiveCache_outer_TLBuffer_auto_out_a_bits_data; // @[Buffer.scala:40:9]
wire InclusiveCache_outer_TLBuffer_auto_out_a_bits_corrupt; // @[Buffer.scala:40:9]
wire InclusiveCache_outer_TLBuffer_auto_out_a_valid; // @[Buffer.scala:40:9]
wire [2:0] InclusiveCache_outer_TLBuffer_auto_out_c_bits_opcode; // @[Buffer.scala:40:9]
wire [2:0] InclusiveCache_outer_TLBuffer_auto_out_c_bits_param; // @[Buffer.scala:40:9]
wire [2:0] InclusiveCache_outer_TLBuffer_auto_out_c_bits_size; // @[Buffer.scala:40:9]
wire [4:0] InclusiveCache_outer_TLBuffer_auto_out_c_bits_source; // @[Buffer.scala:40:9]
wire [31:0] InclusiveCache_outer_TLBuffer_auto_out_c_bits_address; // @[Buffer.scala:40:9]
wire [63:0] InclusiveCache_outer_TLBuffer_auto_out_c_bits_data; // @[Buffer.scala:40:9]
wire InclusiveCache_outer_TLBuffer_auto_out_c_bits_corrupt; // @[Buffer.scala:40:9]
wire InclusiveCache_outer_TLBuffer_auto_out_c_valid; // @[Buffer.scala:40:9]
wire InclusiveCache_outer_TLBuffer_auto_out_d_ready; // @[Buffer.scala:40:9]
wire [2:0] InclusiveCache_outer_TLBuffer_auto_out_e_bits_sink; // @[Buffer.scala:40:9]
wire InclusiveCache_outer_TLBuffer_auto_out_e_valid; // @[Buffer.scala:40:9]
assign InclusiveCache_outer_TLBuffer_nodeIn_a_ready = InclusiveCache_outer_TLBuffer_nodeOut_a_ready; // @[MixedNode.scala:542:17, :551:17]
assign InclusiveCache_outer_TLBuffer_auto_out_a_valid = InclusiveCache_outer_TLBuffer_nodeOut_a_valid; // @[Buffer.scala:40:9]
assign InclusiveCache_outer_TLBuffer_auto_out_a_bits_opcode = InclusiveCache_outer_TLBuffer_nodeOut_a_bits_opcode; // @[Buffer.scala:40:9]
assign InclusiveCache_outer_TLBuffer_auto_out_a_bits_param = InclusiveCache_outer_TLBuffer_nodeOut_a_bits_param; // @[Buffer.scala:40:9]
assign InclusiveCache_outer_TLBuffer_auto_out_a_bits_size = InclusiveCache_outer_TLBuffer_nodeOut_a_bits_size; // @[Buffer.scala:40:9]
assign InclusiveCache_outer_TLBuffer_auto_out_a_bits_source = InclusiveCache_outer_TLBuffer_nodeOut_a_bits_source; // @[Buffer.scala:40:9]
assign InclusiveCache_outer_TLBuffer_auto_out_a_bits_address = InclusiveCache_outer_TLBuffer_nodeOut_a_bits_address; // @[Buffer.scala:40:9]
assign InclusiveCache_outer_TLBuffer_auto_out_a_bits_mask = InclusiveCache_outer_TLBuffer_nodeOut_a_bits_mask; // @[Buffer.scala:40:9]
assign InclusiveCache_outer_TLBuffer_auto_out_a_bits_data = InclusiveCache_outer_TLBuffer_nodeOut_a_bits_data; // @[Buffer.scala:40:9]
assign InclusiveCache_outer_TLBuffer_auto_out_a_bits_corrupt = InclusiveCache_outer_TLBuffer_nodeOut_a_bits_corrupt; // @[Buffer.scala:40:9]
assign InclusiveCache_outer_TLBuffer_nodeIn_c_ready = InclusiveCache_outer_TLBuffer_nodeOut_c_ready; // @[MixedNode.scala:542:17, :551:17]
assign InclusiveCache_outer_TLBuffer_auto_out_c_valid = InclusiveCache_outer_TLBuffer_nodeOut_c_valid; // @[Buffer.scala:40:9]
assign InclusiveCache_outer_TLBuffer_auto_out_c_bits_opcode = InclusiveCache_outer_TLBuffer_nodeOut_c_bits_opcode; // @[Buffer.scala:40:9]
assign InclusiveCache_outer_TLBuffer_auto_out_c_bits_param = InclusiveCache_outer_TLBuffer_nodeOut_c_bits_param; // @[Buffer.scala:40:9]
assign InclusiveCache_outer_TLBuffer_auto_out_c_bits_size = InclusiveCache_outer_TLBuffer_nodeOut_c_bits_size; // @[Buffer.scala:40:9]
assign InclusiveCache_outer_TLBuffer_auto_out_c_bits_source = InclusiveCache_outer_TLBuffer_nodeOut_c_bits_source; // @[Buffer.scala:40:9]
assign InclusiveCache_outer_TLBuffer_auto_out_c_bits_address = InclusiveCache_outer_TLBuffer_nodeOut_c_bits_address; // @[Buffer.scala:40:9]
assign InclusiveCache_outer_TLBuffer_auto_out_c_bits_data = InclusiveCache_outer_TLBuffer_nodeOut_c_bits_data; // @[Buffer.scala:40:9]
assign InclusiveCache_outer_TLBuffer_auto_out_c_bits_corrupt = InclusiveCache_outer_TLBuffer_nodeOut_c_bits_corrupt; // @[Buffer.scala:40:9]
assign InclusiveCache_outer_TLBuffer_auto_out_d_ready = InclusiveCache_outer_TLBuffer_nodeOut_d_ready; // @[Buffer.scala:40:9]
assign InclusiveCache_outer_TLBuffer_nodeIn_d_valid = InclusiveCache_outer_TLBuffer_nodeOut_d_valid; // @[MixedNode.scala:542:17, :551:17]
assign InclusiveCache_outer_TLBuffer_nodeIn_d_bits_opcode = InclusiveCache_outer_TLBuffer_nodeOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign InclusiveCache_outer_TLBuffer_nodeIn_d_bits_param = InclusiveCache_outer_TLBuffer_nodeOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign InclusiveCache_outer_TLBuffer_nodeIn_d_bits_size = InclusiveCache_outer_TLBuffer_nodeOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign InclusiveCache_outer_TLBuffer_nodeIn_d_bits_source = InclusiveCache_outer_TLBuffer_nodeOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign InclusiveCache_outer_TLBuffer_nodeIn_d_bits_sink = InclusiveCache_outer_TLBuffer_nodeOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17]
assign InclusiveCache_outer_TLBuffer_nodeIn_d_bits_denied = InclusiveCache_outer_TLBuffer_nodeOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17]
assign InclusiveCache_outer_TLBuffer_nodeIn_d_bits_data = InclusiveCache_outer_TLBuffer_nodeOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign InclusiveCache_outer_TLBuffer_nodeIn_d_bits_corrupt = InclusiveCache_outer_TLBuffer_nodeOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign InclusiveCache_outer_TLBuffer_auto_out_e_valid = InclusiveCache_outer_TLBuffer_nodeOut_e_valid; // @[Buffer.scala:40:9]
assign InclusiveCache_outer_TLBuffer_auto_out_e_bits_sink = InclusiveCache_outer_TLBuffer_nodeOut_e_bits_sink; // @[Buffer.scala:40:9]
assign InclusiveCache_outer_TLBuffer_auto_in_a_ready = InclusiveCache_outer_TLBuffer_nodeIn_a_ready; // @[Buffer.scala:40:9]
assign InclusiveCache_outer_TLBuffer_nodeOut_a_valid = InclusiveCache_outer_TLBuffer_nodeIn_a_valid; // @[MixedNode.scala:542:17, :551:17]
assign InclusiveCache_outer_TLBuffer_nodeOut_a_bits_opcode = InclusiveCache_outer_TLBuffer_nodeIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign InclusiveCache_outer_TLBuffer_nodeOut_a_bits_param = InclusiveCache_outer_TLBuffer_nodeIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign InclusiveCache_outer_TLBuffer_nodeOut_a_bits_size = InclusiveCache_outer_TLBuffer_nodeIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign InclusiveCache_outer_TLBuffer_nodeOut_a_bits_source = InclusiveCache_outer_TLBuffer_nodeIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign InclusiveCache_outer_TLBuffer_nodeOut_a_bits_address = InclusiveCache_outer_TLBuffer_nodeIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17]
assign InclusiveCache_outer_TLBuffer_nodeOut_a_bits_mask = InclusiveCache_outer_TLBuffer_nodeIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17]
assign InclusiveCache_outer_TLBuffer_nodeOut_a_bits_data = InclusiveCache_outer_TLBuffer_nodeIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign InclusiveCache_outer_TLBuffer_nodeOut_a_bits_corrupt = InclusiveCache_outer_TLBuffer_nodeIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign InclusiveCache_outer_TLBuffer_auto_in_c_ready = InclusiveCache_outer_TLBuffer_nodeIn_c_ready; // @[Buffer.scala:40:9]
assign InclusiveCache_outer_TLBuffer_nodeOut_c_valid = InclusiveCache_outer_TLBuffer_nodeIn_c_valid; // @[MixedNode.scala:542:17, :551:17]
assign InclusiveCache_outer_TLBuffer_nodeOut_c_bits_opcode = InclusiveCache_outer_TLBuffer_nodeIn_c_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign InclusiveCache_outer_TLBuffer_nodeOut_c_bits_param = InclusiveCache_outer_TLBuffer_nodeIn_c_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign InclusiveCache_outer_TLBuffer_nodeOut_c_bits_size = InclusiveCache_outer_TLBuffer_nodeIn_c_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign InclusiveCache_outer_TLBuffer_nodeOut_c_bits_source = InclusiveCache_outer_TLBuffer_nodeIn_c_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign InclusiveCache_outer_TLBuffer_nodeOut_c_bits_address = InclusiveCache_outer_TLBuffer_nodeIn_c_bits_address; // @[MixedNode.scala:542:17, :551:17]
assign InclusiveCache_outer_TLBuffer_nodeOut_c_bits_data = InclusiveCache_outer_TLBuffer_nodeIn_c_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign InclusiveCache_outer_TLBuffer_nodeOut_c_bits_corrupt = InclusiveCache_outer_TLBuffer_nodeIn_c_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign InclusiveCache_outer_TLBuffer_nodeOut_d_ready = InclusiveCache_outer_TLBuffer_nodeIn_d_ready; // @[MixedNode.scala:542:17, :551:17]
assign InclusiveCache_outer_TLBuffer_auto_in_d_valid = InclusiveCache_outer_TLBuffer_nodeIn_d_valid; // @[Buffer.scala:40:9]
assign InclusiveCache_outer_TLBuffer_auto_in_d_bits_opcode = InclusiveCache_outer_TLBuffer_nodeIn_d_bits_opcode; // @[Buffer.scala:40:9]
assign InclusiveCache_outer_TLBuffer_auto_in_d_bits_param = InclusiveCache_outer_TLBuffer_nodeIn_d_bits_param; // @[Buffer.scala:40:9]
assign InclusiveCache_outer_TLBuffer_auto_in_d_bits_size = InclusiveCache_outer_TLBuffer_nodeIn_d_bits_size; // @[Buffer.scala:40:9]
assign InclusiveCache_outer_TLBuffer_auto_in_d_bits_source = InclusiveCache_outer_TLBuffer_nodeIn_d_bits_source; // @[Buffer.scala:40:9]
assign InclusiveCache_outer_TLBuffer_auto_in_d_bits_sink = InclusiveCache_outer_TLBuffer_nodeIn_d_bits_sink; // @[Buffer.scala:40:9]
assign InclusiveCache_outer_TLBuffer_auto_in_d_bits_denied = InclusiveCache_outer_TLBuffer_nodeIn_d_bits_denied; // @[Buffer.scala:40:9]
assign InclusiveCache_outer_TLBuffer_auto_in_d_bits_data = InclusiveCache_outer_TLBuffer_nodeIn_d_bits_data; // @[Buffer.scala:40:9]
assign InclusiveCache_outer_TLBuffer_auto_in_d_bits_corrupt = InclusiveCache_outer_TLBuffer_nodeIn_d_bits_corrupt; // @[Buffer.scala:40:9]
assign InclusiveCache_outer_TLBuffer_nodeOut_e_valid = InclusiveCache_outer_TLBuffer_nodeIn_e_valid; // @[MixedNode.scala:542:17, :551:17]
assign InclusiveCache_outer_TLBuffer_nodeOut_e_bits_sink = InclusiveCache_outer_TLBuffer_nodeIn_e_bits_sink; // @[MixedNode.scala:542:17, :551:17]
wire coherent_jbar_anonIn_a_ready; // @[MixedNode.scala:551:17]
assign auto_coherent_jbar_anon_in_a_ready_0 = coherent_jbar_auto_anon_in_a_ready; // @[Jbar.scala:44:9]
wire coherent_jbar_anonIn_a_valid = coherent_jbar_auto_anon_in_a_valid; // @[Jbar.scala:44:9]
wire [2:0] coherent_jbar_anonIn_a_bits_opcode = coherent_jbar_auto_anon_in_a_bits_opcode; // @[Jbar.scala:44:9]
wire [2:0] coherent_jbar_anonIn_a_bits_param = coherent_jbar_auto_anon_in_a_bits_param; // @[Jbar.scala:44:9]
wire [2:0] coherent_jbar_anonIn_a_bits_size = coherent_jbar_auto_anon_in_a_bits_size; // @[Jbar.scala:44:9]
wire [7:0] coherent_jbar_anonIn_a_bits_source = coherent_jbar_auto_anon_in_a_bits_source; // @[Jbar.scala:44:9]
wire [31:0] coherent_jbar_anonIn_a_bits_address = coherent_jbar_auto_anon_in_a_bits_address; // @[Jbar.scala:44:9]
wire [31:0] coherent_jbar_anonIn_a_bits_mask = coherent_jbar_auto_anon_in_a_bits_mask; // @[Jbar.scala:44:9]
wire [255:0] coherent_jbar_anonIn_a_bits_data = coherent_jbar_auto_anon_in_a_bits_data; // @[Jbar.scala:44:9]
wire coherent_jbar_anonIn_a_bits_corrupt = coherent_jbar_auto_anon_in_a_bits_corrupt; // @[Jbar.scala:44:9]
wire coherent_jbar_anonIn_b_ready = coherent_jbar_auto_anon_in_b_ready; // @[Jbar.scala:44:9]
wire coherent_jbar_anonIn_b_valid; // @[MixedNode.scala:551:17]
assign auto_coherent_jbar_anon_in_b_valid_0 = coherent_jbar_auto_anon_in_b_valid; // @[Jbar.scala:44:9]
wire [1:0] coherent_jbar_anonIn_b_bits_param; // @[MixedNode.scala:551:17]
assign auto_coherent_jbar_anon_in_b_bits_param_0 = coherent_jbar_auto_anon_in_b_bits_param; // @[Jbar.scala:44:9]
wire [31:0] coherent_jbar_anonIn_b_bits_address; // @[MixedNode.scala:551:17]
assign auto_coherent_jbar_anon_in_b_bits_address_0 = coherent_jbar_auto_anon_in_b_bits_address; // @[Jbar.scala:44:9]
wire coherent_jbar_anonIn_c_ready; // @[MixedNode.scala:551:17]
assign auto_coherent_jbar_anon_in_c_ready_0 = coherent_jbar_auto_anon_in_c_ready; // @[Jbar.scala:44:9]
wire coherent_jbar_anonIn_c_valid = coherent_jbar_auto_anon_in_c_valid; // @[Jbar.scala:44:9]
wire [2:0] coherent_jbar_anonIn_c_bits_opcode = coherent_jbar_auto_anon_in_c_bits_opcode; // @[Jbar.scala:44:9]
wire [2:0] coherent_jbar_anonIn_c_bits_param = coherent_jbar_auto_anon_in_c_bits_param; // @[Jbar.scala:44:9]
wire [2:0] coherent_jbar_anonIn_c_bits_size = coherent_jbar_auto_anon_in_c_bits_size; // @[Jbar.scala:44:9]
wire [7:0] coherent_jbar_anonIn_c_bits_source = coherent_jbar_auto_anon_in_c_bits_source; // @[Jbar.scala:44:9]
wire [31:0] coherent_jbar_anonIn_c_bits_address = coherent_jbar_auto_anon_in_c_bits_address; // @[Jbar.scala:44:9]
wire [255:0] coherent_jbar_anonIn_c_bits_data = coherent_jbar_auto_anon_in_c_bits_data; // @[Jbar.scala:44:9]
wire coherent_jbar_anonIn_c_bits_corrupt = coherent_jbar_auto_anon_in_c_bits_corrupt; // @[Jbar.scala:44:9]
wire coherent_jbar_anonIn_d_ready = coherent_jbar_auto_anon_in_d_ready; // @[Jbar.scala:44:9]
wire coherent_jbar_anonIn_d_valid; // @[MixedNode.scala:551:17]
assign auto_coherent_jbar_anon_in_d_valid_0 = coherent_jbar_auto_anon_in_d_valid; // @[Jbar.scala:44:9]
wire [2:0] coherent_jbar_anonIn_d_bits_opcode; // @[MixedNode.scala:551:17]
assign auto_coherent_jbar_anon_in_d_bits_opcode_0 = coherent_jbar_auto_anon_in_d_bits_opcode; // @[Jbar.scala:44:9]
wire [1:0] coherent_jbar_anonIn_d_bits_param; // @[MixedNode.scala:551:17]
assign auto_coherent_jbar_anon_in_d_bits_param_0 = coherent_jbar_auto_anon_in_d_bits_param; // @[Jbar.scala:44:9]
wire [2:0] coherent_jbar_anonIn_d_bits_size; // @[MixedNode.scala:551:17]
assign auto_coherent_jbar_anon_in_d_bits_size_0 = coherent_jbar_auto_anon_in_d_bits_size; // @[Jbar.scala:44:9]
wire [7:0] coherent_jbar_anonIn_d_bits_source; // @[MixedNode.scala:551:17]
assign auto_coherent_jbar_anon_in_d_bits_source_0 = coherent_jbar_auto_anon_in_d_bits_source; // @[Jbar.scala:44:9]
wire [4:0] coherent_jbar_anonIn_d_bits_sink; // @[MixedNode.scala:551:17]
assign auto_coherent_jbar_anon_in_d_bits_sink_0 = coherent_jbar_auto_anon_in_d_bits_sink; // @[Jbar.scala:44:9]
wire coherent_jbar_anonIn_d_bits_denied; // @[MixedNode.scala:551:17]
assign auto_coherent_jbar_anon_in_d_bits_denied_0 = coherent_jbar_auto_anon_in_d_bits_denied; // @[Jbar.scala:44:9]
wire [255:0] coherent_jbar_anonIn_d_bits_data; // @[MixedNode.scala:551:17]
assign auto_coherent_jbar_anon_in_d_bits_data_0 = coherent_jbar_auto_anon_in_d_bits_data; // @[Jbar.scala:44:9]
wire coherent_jbar_anonIn_d_bits_corrupt; // @[MixedNode.scala:551:17]
assign auto_coherent_jbar_anon_in_d_bits_corrupt_0 = coherent_jbar_auto_anon_in_d_bits_corrupt; // @[Jbar.scala:44:9]
wire coherent_jbar_anonIn_e_valid = coherent_jbar_auto_anon_in_e_valid; // @[Jbar.scala:44:9]
wire [4:0] coherent_jbar_anonIn_e_bits_sink = coherent_jbar_auto_anon_in_e_bits_sink; // @[Jbar.scala:44:9]
wire coherent_jbar_anonOut_a_ready = coherent_jbar_auto_anon_out_a_ready; // @[Jbar.scala:44:9]
wire coherent_jbar_anonOut_a_valid; // @[MixedNode.scala:542:17]
assign filter_auto_anon_in_a_valid = coherent_jbar_auto_anon_out_a_valid; // @[Jbar.scala:44:9]
wire [2:0] coherent_jbar_anonOut_a_bits_opcode; // @[MixedNode.scala:542:17]
assign filter_auto_anon_in_a_bits_opcode = coherent_jbar_auto_anon_out_a_bits_opcode; // @[Jbar.scala:44:9]
wire [2:0] coherent_jbar_anonOut_a_bits_param; // @[MixedNode.scala:542:17]
assign filter_auto_anon_in_a_bits_param = coherent_jbar_auto_anon_out_a_bits_param; // @[Jbar.scala:44:9]
wire [2:0] coherent_jbar_anonOut_a_bits_size; // @[MixedNode.scala:542:17]
assign filter_auto_anon_in_a_bits_size = coherent_jbar_auto_anon_out_a_bits_size; // @[Jbar.scala:44:9]
wire [7:0] coherent_jbar_anonOut_a_bits_source; // @[MixedNode.scala:542:17]
assign filter_auto_anon_in_a_bits_source = coherent_jbar_auto_anon_out_a_bits_source; // @[Jbar.scala:44:9]
wire [31:0] coherent_jbar_anonOut_a_bits_address; // @[MixedNode.scala:542:17]
assign filter_auto_anon_in_a_bits_address = coherent_jbar_auto_anon_out_a_bits_address; // @[Jbar.scala:44:9]
wire [31:0] coherent_jbar_anonOut_a_bits_mask; // @[MixedNode.scala:542:17]
assign filter_auto_anon_in_a_bits_mask = coherent_jbar_auto_anon_out_a_bits_mask; // @[Jbar.scala:44:9]
wire [255:0] coherent_jbar_anonOut_a_bits_data; // @[MixedNode.scala:542:17]
assign filter_auto_anon_in_a_bits_data = coherent_jbar_auto_anon_out_a_bits_data; // @[Jbar.scala:44:9]
wire coherent_jbar_anonOut_a_bits_corrupt; // @[MixedNode.scala:542:17]
assign filter_auto_anon_in_a_bits_corrupt = coherent_jbar_auto_anon_out_a_bits_corrupt; // @[Jbar.scala:44:9]
wire coherent_jbar_anonOut_b_ready; // @[MixedNode.scala:542:17]
assign filter_auto_anon_in_b_ready = coherent_jbar_auto_anon_out_b_ready; // @[Jbar.scala:44:9]
wire coherent_jbar_anonOut_b_valid = coherent_jbar_auto_anon_out_b_valid; // @[Jbar.scala:44:9]
wire [1:0] coherent_jbar_anonOut_b_bits_param = coherent_jbar_auto_anon_out_b_bits_param; // @[Jbar.scala:44:9]
wire [31:0] coherent_jbar_anonOut_b_bits_address = coherent_jbar_auto_anon_out_b_bits_address; // @[Jbar.scala:44:9]
wire coherent_jbar_anonOut_c_ready = coherent_jbar_auto_anon_out_c_ready; // @[Jbar.scala:44:9]
wire coherent_jbar_anonOut_c_valid; // @[MixedNode.scala:542:17]
assign filter_auto_anon_in_c_valid = coherent_jbar_auto_anon_out_c_valid; // @[Jbar.scala:44:9]
wire [2:0] coherent_jbar_anonOut_c_bits_opcode; // @[MixedNode.scala:542:17]
assign filter_auto_anon_in_c_bits_opcode = coherent_jbar_auto_anon_out_c_bits_opcode; // @[Jbar.scala:44:9]
wire [2:0] coherent_jbar_anonOut_c_bits_param; // @[MixedNode.scala:542:17]
assign filter_auto_anon_in_c_bits_param = coherent_jbar_auto_anon_out_c_bits_param; // @[Jbar.scala:44:9]
wire [2:0] coherent_jbar_anonOut_c_bits_size; // @[MixedNode.scala:542:17]
assign filter_auto_anon_in_c_bits_size = coherent_jbar_auto_anon_out_c_bits_size; // @[Jbar.scala:44:9]
wire [7:0] coherent_jbar_anonOut_c_bits_source; // @[MixedNode.scala:542:17]
assign filter_auto_anon_in_c_bits_source = coherent_jbar_auto_anon_out_c_bits_source; // @[Jbar.scala:44:9]
wire [31:0] coherent_jbar_anonOut_c_bits_address; // @[MixedNode.scala:542:17]
assign filter_auto_anon_in_c_bits_address = coherent_jbar_auto_anon_out_c_bits_address; // @[Jbar.scala:44:9]
wire [255:0] coherent_jbar_anonOut_c_bits_data; // @[MixedNode.scala:542:17]
assign filter_auto_anon_in_c_bits_data = coherent_jbar_auto_anon_out_c_bits_data; // @[Jbar.scala:44:9]
wire coherent_jbar_anonOut_c_bits_corrupt; // @[MixedNode.scala:542:17]
assign filter_auto_anon_in_c_bits_corrupt = coherent_jbar_auto_anon_out_c_bits_corrupt; // @[Jbar.scala:44:9]
wire coherent_jbar_anonOut_d_ready; // @[MixedNode.scala:542:17]
assign filter_auto_anon_in_d_ready = coherent_jbar_auto_anon_out_d_ready; // @[Jbar.scala:44:9]
wire coherent_jbar_anonOut_d_valid = coherent_jbar_auto_anon_out_d_valid; // @[Jbar.scala:44:9]
wire [2:0] coherent_jbar_anonOut_d_bits_opcode = coherent_jbar_auto_anon_out_d_bits_opcode; // @[Jbar.scala:44:9]
wire [1:0] coherent_jbar_anonOut_d_bits_param = coherent_jbar_auto_anon_out_d_bits_param; // @[Jbar.scala:44:9]
wire [2:0] coherent_jbar_anonOut_d_bits_size = coherent_jbar_auto_anon_out_d_bits_size; // @[Jbar.scala:44:9]
wire [7:0] coherent_jbar_anonOut_d_bits_source = coherent_jbar_auto_anon_out_d_bits_source; // @[Jbar.scala:44:9]
wire [4:0] coherent_jbar_anonOut_d_bits_sink = coherent_jbar_auto_anon_out_d_bits_sink; // @[Jbar.scala:44:9]
wire coherent_jbar_anonOut_d_bits_denied = coherent_jbar_auto_anon_out_d_bits_denied; // @[Jbar.scala:44:9]
wire [255:0] coherent_jbar_anonOut_d_bits_data = coherent_jbar_auto_anon_out_d_bits_data; // @[Jbar.scala:44:9]
wire coherent_jbar_anonOut_d_bits_corrupt = coherent_jbar_auto_anon_out_d_bits_corrupt; // @[Jbar.scala:44:9]
wire coherent_jbar_anonOut_e_valid; // @[MixedNode.scala:542:17]
assign filter_auto_anon_in_e_valid = coherent_jbar_auto_anon_out_e_valid; // @[Jbar.scala:44:9]
wire [4:0] coherent_jbar_anonOut_e_bits_sink; // @[MixedNode.scala:542:17]
assign filter_auto_anon_in_e_bits_sink = coherent_jbar_auto_anon_out_e_bits_sink; // @[Jbar.scala:44:9]
wire coherent_jbar_out_0_a_ready = coherent_jbar_anonOut_a_ready; // @[Xbar.scala:216:19]
wire coherent_jbar_out_0_a_valid; // @[Xbar.scala:216:19]
assign coherent_jbar_auto_anon_out_a_valid = coherent_jbar_anonOut_a_valid; // @[Jbar.scala:44:9]
wire [2:0] coherent_jbar_out_0_a_bits_opcode; // @[Xbar.scala:216:19]
assign coherent_jbar_auto_anon_out_a_bits_opcode = coherent_jbar_anonOut_a_bits_opcode; // @[Jbar.scala:44:9]
wire [2:0] coherent_jbar_out_0_a_bits_param; // @[Xbar.scala:216:19]
assign coherent_jbar_auto_anon_out_a_bits_param = coherent_jbar_anonOut_a_bits_param; // @[Jbar.scala:44:9]
wire [2:0] coherent_jbar_out_0_a_bits_size; // @[Xbar.scala:216:19]
assign coherent_jbar_auto_anon_out_a_bits_size = coherent_jbar_anonOut_a_bits_size; // @[Jbar.scala:44:9]
wire [7:0] coherent_jbar_out_0_a_bits_source; // @[Xbar.scala:216:19]
assign coherent_jbar_auto_anon_out_a_bits_source = coherent_jbar_anonOut_a_bits_source; // @[Jbar.scala:44:9]
wire [31:0] coherent_jbar_out_0_a_bits_address; // @[Xbar.scala:216:19]
assign coherent_jbar_auto_anon_out_a_bits_address = coherent_jbar_anonOut_a_bits_address; // @[Jbar.scala:44:9]
wire [31:0] coherent_jbar_out_0_a_bits_mask; // @[Xbar.scala:216:19]
assign coherent_jbar_auto_anon_out_a_bits_mask = coherent_jbar_anonOut_a_bits_mask; // @[Jbar.scala:44:9]
wire [255:0] coherent_jbar_out_0_a_bits_data; // @[Xbar.scala:216:19]
assign coherent_jbar_auto_anon_out_a_bits_data = coherent_jbar_anonOut_a_bits_data; // @[Jbar.scala:44:9]
wire coherent_jbar_out_0_a_bits_corrupt; // @[Xbar.scala:216:19]
assign coherent_jbar_auto_anon_out_a_bits_corrupt = coherent_jbar_anonOut_a_bits_corrupt; // @[Jbar.scala:44:9]
wire coherent_jbar_out_0_b_ready; // @[Xbar.scala:216:19]
assign coherent_jbar_auto_anon_out_b_ready = coherent_jbar_anonOut_b_ready; // @[Jbar.scala:44:9]
wire coherent_jbar_out_0_b_valid = coherent_jbar_anonOut_b_valid; // @[Xbar.scala:216:19]
wire [1:0] coherent_jbar_out_0_b_bits_param = coherent_jbar_anonOut_b_bits_param; // @[Xbar.scala:216:19]
wire [31:0] coherent_jbar_out_0_b_bits_address = coherent_jbar_anonOut_b_bits_address; // @[Xbar.scala:216:19]
wire coherent_jbar_out_0_c_ready = coherent_jbar_anonOut_c_ready; // @[Xbar.scala:216:19]
wire coherent_jbar_out_0_c_valid; // @[Xbar.scala:216:19]
assign coherent_jbar_auto_anon_out_c_valid = coherent_jbar_anonOut_c_valid; // @[Jbar.scala:44:9]
wire [2:0] coherent_jbar_out_0_c_bits_opcode; // @[Xbar.scala:216:19]
assign coherent_jbar_auto_anon_out_c_bits_opcode = coherent_jbar_anonOut_c_bits_opcode; // @[Jbar.scala:44:9]
wire [2:0] coherent_jbar_out_0_c_bits_param; // @[Xbar.scala:216:19]
assign coherent_jbar_auto_anon_out_c_bits_param = coherent_jbar_anonOut_c_bits_param; // @[Jbar.scala:44:9]
wire [2:0] coherent_jbar_out_0_c_bits_size; // @[Xbar.scala:216:19]
assign coherent_jbar_auto_anon_out_c_bits_size = coherent_jbar_anonOut_c_bits_size; // @[Jbar.scala:44:9]
wire [7:0] coherent_jbar_out_0_c_bits_source; // @[Xbar.scala:216:19]
assign coherent_jbar_auto_anon_out_c_bits_source = coherent_jbar_anonOut_c_bits_source; // @[Jbar.scala:44:9]
wire [31:0] coherent_jbar_out_0_c_bits_address; // @[Xbar.scala:216:19]
assign coherent_jbar_auto_anon_out_c_bits_address = coherent_jbar_anonOut_c_bits_address; // @[Jbar.scala:44:9]
wire [255:0] coherent_jbar_out_0_c_bits_data; // @[Xbar.scala:216:19]
assign coherent_jbar_auto_anon_out_c_bits_data = coherent_jbar_anonOut_c_bits_data; // @[Jbar.scala:44:9]
wire coherent_jbar_out_0_c_bits_corrupt; // @[Xbar.scala:216:19]
assign coherent_jbar_auto_anon_out_c_bits_corrupt = coherent_jbar_anonOut_c_bits_corrupt; // @[Jbar.scala:44:9]
wire coherent_jbar_out_0_d_ready; // @[Xbar.scala:216:19]
assign coherent_jbar_auto_anon_out_d_ready = coherent_jbar_anonOut_d_ready; // @[Jbar.scala:44:9]
wire coherent_jbar_out_0_d_valid = coherent_jbar_anonOut_d_valid; // @[Xbar.scala:216:19]
wire [2:0] coherent_jbar_out_0_d_bits_opcode = coherent_jbar_anonOut_d_bits_opcode; // @[Xbar.scala:216:19]
wire [1:0] coherent_jbar_out_0_d_bits_param = coherent_jbar_anonOut_d_bits_param; // @[Xbar.scala:216:19]
wire [2:0] coherent_jbar_out_0_d_bits_size = coherent_jbar_anonOut_d_bits_size; // @[Xbar.scala:216:19]
wire [7:0] coherent_jbar_out_0_d_bits_source = coherent_jbar_anonOut_d_bits_source; // @[Xbar.scala:216:19]
wire [4:0] coherent_jbar__out_0_d_bits_sink_T = coherent_jbar_anonOut_d_bits_sink; // @[Xbar.scala:251:53]
wire coherent_jbar_out_0_d_bits_denied = coherent_jbar_anonOut_d_bits_denied; // @[Xbar.scala:216:19]
wire [255:0] coherent_jbar_out_0_d_bits_data = coherent_jbar_anonOut_d_bits_data; // @[Xbar.scala:216:19]
wire coherent_jbar_out_0_d_bits_corrupt = coherent_jbar_anonOut_d_bits_corrupt; // @[Xbar.scala:216:19]
wire coherent_jbar_out_0_e_valid; // @[Xbar.scala:216:19]
assign coherent_jbar_auto_anon_out_e_valid = coherent_jbar_anonOut_e_valid; // @[Jbar.scala:44:9]
wire [4:0] coherent_jbar__anonOut_e_bits_sink_T; // @[Xbar.scala:156:69]
assign coherent_jbar_auto_anon_out_e_bits_sink = coherent_jbar_anonOut_e_bits_sink; // @[Jbar.scala:44:9]
wire coherent_jbar_in_0_a_ready; // @[Xbar.scala:159:18]
assign coherent_jbar_auto_anon_in_a_ready = coherent_jbar_anonIn_a_ready; // @[Jbar.scala:44:9]
wire coherent_jbar_in_0_a_valid = coherent_jbar_anonIn_a_valid; // @[Xbar.scala:159:18]
wire [2:0] coherent_jbar_in_0_a_bits_opcode = coherent_jbar_anonIn_a_bits_opcode; // @[Xbar.scala:159:18]
wire [2:0] coherent_jbar_in_0_a_bits_param = coherent_jbar_anonIn_a_bits_param; // @[Xbar.scala:159:18]
wire [2:0] coherent_jbar_in_0_a_bits_size = coherent_jbar_anonIn_a_bits_size; // @[Xbar.scala:159:18]
wire [7:0] coherent_jbar__in_0_a_bits_source_T = coherent_jbar_anonIn_a_bits_source; // @[Xbar.scala:166:55]
wire [31:0] coherent_jbar_in_0_a_bits_address = coherent_jbar_anonIn_a_bits_address; // @[Xbar.scala:159:18]
wire [31:0] coherent_jbar_in_0_a_bits_mask = coherent_jbar_anonIn_a_bits_mask; // @[Xbar.scala:159:18]
wire [255:0] coherent_jbar_in_0_a_bits_data = coherent_jbar_anonIn_a_bits_data; // @[Xbar.scala:159:18]
wire coherent_jbar_in_0_a_bits_corrupt = coherent_jbar_anonIn_a_bits_corrupt; // @[Xbar.scala:159:18]
wire coherent_jbar_in_0_b_ready = coherent_jbar_anonIn_b_ready; // @[Xbar.scala:159:18]
wire coherent_jbar_in_0_b_valid; // @[Xbar.scala:159:18]
assign coherent_jbar_auto_anon_in_b_valid = coherent_jbar_anonIn_b_valid; // @[Jbar.scala:44:9]
wire [1:0] coherent_jbar_in_0_b_bits_param; // @[Xbar.scala:159:18]
assign coherent_jbar_auto_anon_in_b_bits_param = coherent_jbar_anonIn_b_bits_param; // @[Jbar.scala:44:9]
wire [31:0] coherent_jbar_in_0_b_bits_address; // @[Xbar.scala:159:18]
assign coherent_jbar_auto_anon_in_b_bits_address = coherent_jbar_anonIn_b_bits_address; // @[Jbar.scala:44:9]
wire coherent_jbar_in_0_c_ready; // @[Xbar.scala:159:18]
assign coherent_jbar_auto_anon_in_c_ready = coherent_jbar_anonIn_c_ready; // @[Jbar.scala:44:9]
wire coherent_jbar_in_0_c_valid = coherent_jbar_anonIn_c_valid; // @[Xbar.scala:159:18]
wire [2:0] coherent_jbar_in_0_c_bits_opcode = coherent_jbar_anonIn_c_bits_opcode; // @[Xbar.scala:159:18]
wire [2:0] coherent_jbar_in_0_c_bits_param = coherent_jbar_anonIn_c_bits_param; // @[Xbar.scala:159:18]
wire [2:0] coherent_jbar_in_0_c_bits_size = coherent_jbar_anonIn_c_bits_size; // @[Xbar.scala:159:18]
wire [7:0] coherent_jbar__in_0_c_bits_source_T = coherent_jbar_anonIn_c_bits_source; // @[Xbar.scala:187:55]
wire [31:0] coherent_jbar_in_0_c_bits_address = coherent_jbar_anonIn_c_bits_address; // @[Xbar.scala:159:18]
wire [255:0] coherent_jbar_in_0_c_bits_data = coherent_jbar_anonIn_c_bits_data; // @[Xbar.scala:159:18]
wire coherent_jbar_in_0_c_bits_corrupt = coherent_jbar_anonIn_c_bits_corrupt; // @[Xbar.scala:159:18]
wire coherent_jbar_in_0_d_ready = coherent_jbar_anonIn_d_ready; // @[Xbar.scala:159:18]
wire coherent_jbar_in_0_d_valid; // @[Xbar.scala:159:18]
assign coherent_jbar_auto_anon_in_d_valid = coherent_jbar_anonIn_d_valid; // @[Jbar.scala:44:9]
wire [2:0] coherent_jbar_in_0_d_bits_opcode; // @[Xbar.scala:159:18]
assign coherent_jbar_auto_anon_in_d_bits_opcode = coherent_jbar_anonIn_d_bits_opcode; // @[Jbar.scala:44:9]
wire [1:0] coherent_jbar_in_0_d_bits_param; // @[Xbar.scala:159:18]
assign coherent_jbar_auto_anon_in_d_bits_param = coherent_jbar_anonIn_d_bits_param; // @[Jbar.scala:44:9]
wire [2:0] coherent_jbar_in_0_d_bits_size; // @[Xbar.scala:159:18]
assign coherent_jbar_auto_anon_in_d_bits_size = coherent_jbar_anonIn_d_bits_size; // @[Jbar.scala:44:9]
wire [7:0] coherent_jbar__anonIn_d_bits_source_T; // @[Xbar.scala:156:69]
assign coherent_jbar_auto_anon_in_d_bits_source = coherent_jbar_anonIn_d_bits_source; // @[Jbar.scala:44:9]
wire [4:0] coherent_jbar_in_0_d_bits_sink; // @[Xbar.scala:159:18]
assign coherent_jbar_auto_anon_in_d_bits_sink = coherent_jbar_anonIn_d_bits_sink; // @[Jbar.scala:44:9]
wire coherent_jbar_in_0_d_bits_denied; // @[Xbar.scala:159:18]
assign coherent_jbar_auto_anon_in_d_bits_denied = coherent_jbar_anonIn_d_bits_denied; // @[Jbar.scala:44:9]
wire [255:0] coherent_jbar_in_0_d_bits_data; // @[Xbar.scala:159:18]
assign coherent_jbar_auto_anon_in_d_bits_data = coherent_jbar_anonIn_d_bits_data; // @[Jbar.scala:44:9]
wire coherent_jbar_in_0_d_bits_corrupt; // @[Xbar.scala:159:18]
assign coherent_jbar_auto_anon_in_d_bits_corrupt = coherent_jbar_anonIn_d_bits_corrupt; // @[Jbar.scala:44:9]
wire coherent_jbar_in_0_e_valid = coherent_jbar_anonIn_e_valid; // @[Xbar.scala:159:18]
wire [4:0] coherent_jbar_in_0_e_bits_sink = coherent_jbar_anonIn_e_bits_sink; // @[Xbar.scala:159:18]
wire coherent_jbar_portsAOI_filtered_0_ready; // @[Xbar.scala:352:24]
assign coherent_jbar_anonIn_a_ready = coherent_jbar_in_0_a_ready; // @[Xbar.scala:159:18]
wire coherent_jbar__portsAOI_filtered_0_valid_T_1 = coherent_jbar_in_0_a_valid; // @[Xbar.scala:159:18, :355:40]
wire [2:0] coherent_jbar_portsAOI_filtered_0_bits_opcode = coherent_jbar_in_0_a_bits_opcode; // @[Xbar.scala:159:18, :352:24]
wire [2:0] coherent_jbar_portsAOI_filtered_0_bits_param = coherent_jbar_in_0_a_bits_param; // @[Xbar.scala:159:18, :352:24]
wire [2:0] coherent_jbar_portsAOI_filtered_0_bits_size = coherent_jbar_in_0_a_bits_size; // @[Xbar.scala:159:18, :352:24]
wire [7:0] coherent_jbar_portsAOI_filtered_0_bits_source = coherent_jbar_in_0_a_bits_source; // @[Xbar.scala:159:18, :352:24]
wire [31:0] coherent_jbar__requestAIO_T = coherent_jbar_in_0_a_bits_address; // @[Xbar.scala:159:18]
wire [31:0] coherent_jbar_portsAOI_filtered_0_bits_address = coherent_jbar_in_0_a_bits_address; // @[Xbar.scala:159:18, :352:24]
wire [31:0] coherent_jbar_portsAOI_filtered_0_bits_mask = coherent_jbar_in_0_a_bits_mask; // @[Xbar.scala:159:18, :352:24]
wire [255:0] coherent_jbar_portsAOI_filtered_0_bits_data = coherent_jbar_in_0_a_bits_data; // @[Xbar.scala:159:18, :352:24]
wire coherent_jbar_portsAOI_filtered_0_bits_corrupt = coherent_jbar_in_0_a_bits_corrupt; // @[Xbar.scala:159:18, :352:24]
wire coherent_jbar_portsBIO_filtered_0_ready = coherent_jbar_in_0_b_ready; // @[Xbar.scala:159:18, :352:24]
wire coherent_jbar_portsBIO_filtered_0_valid; // @[Xbar.scala:352:24]
assign coherent_jbar_anonIn_b_valid = coherent_jbar_in_0_b_valid; // @[Xbar.scala:159:18]
wire [1:0] coherent_jbar_portsBIO_filtered_0_bits_param; // @[Xbar.scala:352:24]
assign coherent_jbar_anonIn_b_bits_param = coherent_jbar_in_0_b_bits_param; // @[Xbar.scala:159:18]
wire [31:0] coherent_jbar_portsBIO_filtered_0_bits_address; // @[Xbar.scala:352:24]
assign coherent_jbar_anonIn_b_bits_address = coherent_jbar_in_0_b_bits_address; // @[Xbar.scala:159:18]
wire coherent_jbar_portsCOI_filtered_0_ready; // @[Xbar.scala:352:24]
assign coherent_jbar_anonIn_c_ready = coherent_jbar_in_0_c_ready; // @[Xbar.scala:159:18]
wire coherent_jbar__portsCOI_filtered_0_valid_T_1 = coherent_jbar_in_0_c_valid; // @[Xbar.scala:159:18, :355:40]
wire [2:0] coherent_jbar_portsCOI_filtered_0_bits_opcode = coherent_jbar_in_0_c_bits_opcode; // @[Xbar.scala:159:18, :352:24]
wire [2:0] coherent_jbar_portsCOI_filtered_0_bits_param = coherent_jbar_in_0_c_bits_param; // @[Xbar.scala:159:18, :352:24]
wire [2:0] coherent_jbar_portsCOI_filtered_0_bits_size = coherent_jbar_in_0_c_bits_size; // @[Xbar.scala:159:18, :352:24]
wire [7:0] coherent_jbar_portsCOI_filtered_0_bits_source = coherent_jbar_in_0_c_bits_source; // @[Xbar.scala:159:18, :352:24]
wire [31:0] coherent_jbar__requestCIO_T = coherent_jbar_in_0_c_bits_address; // @[Xbar.scala:159:18]
wire [31:0] coherent_jbar_portsCOI_filtered_0_bits_address = coherent_jbar_in_0_c_bits_address; // @[Xbar.scala:159:18, :352:24]
wire [255:0] coherent_jbar_portsCOI_filtered_0_bits_data = coherent_jbar_in_0_c_bits_data; // @[Xbar.scala:159:18, :352:24]
wire coherent_jbar_portsCOI_filtered_0_bits_corrupt = coherent_jbar_in_0_c_bits_corrupt; // @[Xbar.scala:159:18, :352:24]
wire coherent_jbar_portsDIO_filtered_0_ready = coherent_jbar_in_0_d_ready; // @[Xbar.scala:159:18, :352:24]
wire coherent_jbar_portsDIO_filtered_0_valid; // @[Xbar.scala:352:24]
assign coherent_jbar_anonIn_d_valid = coherent_jbar_in_0_d_valid; // @[Xbar.scala:159:18]
wire [2:0] coherent_jbar_portsDIO_filtered_0_bits_opcode; // @[Xbar.scala:352:24]
assign coherent_jbar_anonIn_d_bits_opcode = coherent_jbar_in_0_d_bits_opcode; // @[Xbar.scala:159:18]
wire [1:0] coherent_jbar_portsDIO_filtered_0_bits_param; // @[Xbar.scala:352:24]
assign coherent_jbar_anonIn_d_bits_param = coherent_jbar_in_0_d_bits_param; // @[Xbar.scala:159:18]
wire [2:0] coherent_jbar_portsDIO_filtered_0_bits_size; // @[Xbar.scala:352:24]
assign coherent_jbar_anonIn_d_bits_size = coherent_jbar_in_0_d_bits_size; // @[Xbar.scala:159:18]
wire [7:0] coherent_jbar_portsDIO_filtered_0_bits_source; // @[Xbar.scala:352:24]
assign coherent_jbar__anonIn_d_bits_source_T = coherent_jbar_in_0_d_bits_source; // @[Xbar.scala:156:69, :159:18]
wire [4:0] coherent_jbar_portsDIO_filtered_0_bits_sink; // @[Xbar.scala:352:24]
assign coherent_jbar_anonIn_d_bits_sink = coherent_jbar_in_0_d_bits_sink; // @[Xbar.scala:159:18]
wire coherent_jbar_portsDIO_filtered_0_bits_denied; // @[Xbar.scala:352:24]
assign coherent_jbar_anonIn_d_bits_denied = coherent_jbar_in_0_d_bits_denied; // @[Xbar.scala:159:18]
wire [255:0] coherent_jbar_portsDIO_filtered_0_bits_data; // @[Xbar.scala:352:24]
assign coherent_jbar_anonIn_d_bits_data = coherent_jbar_in_0_d_bits_data; // @[Xbar.scala:159:18]
wire coherent_jbar_portsDIO_filtered_0_bits_corrupt; // @[Xbar.scala:352:24]
assign coherent_jbar_anonIn_d_bits_corrupt = coherent_jbar_in_0_d_bits_corrupt; // @[Xbar.scala:159:18]
wire coherent_jbar__portsEOI_filtered_0_valid_T_1 = coherent_jbar_in_0_e_valid; // @[Xbar.scala:159:18, :355:40]
wire [4:0] coherent_jbar__requestEIO_uncommonBits_T = coherent_jbar_in_0_e_bits_sink; // @[Xbar.scala:159:18]
wire [4:0] coherent_jbar_portsEOI_filtered_0_bits_sink = coherent_jbar_in_0_e_bits_sink; // @[Xbar.scala:159:18, :352:24]
assign coherent_jbar_in_0_a_bits_source = coherent_jbar__in_0_a_bits_source_T; // @[Xbar.scala:159:18, :166:55]
assign coherent_jbar_in_0_c_bits_source = coherent_jbar__in_0_c_bits_source_T; // @[Xbar.scala:159:18, :187:55]
assign coherent_jbar_anonIn_d_bits_source = coherent_jbar__anonIn_d_bits_source_T; // @[Xbar.scala:156:69]
assign coherent_jbar_portsAOI_filtered_0_ready = coherent_jbar_out_0_a_ready; // @[Xbar.scala:216:19, :352:24]
wire coherent_jbar_portsAOI_filtered_0_valid; // @[Xbar.scala:352:24]
assign coherent_jbar_anonOut_a_valid = coherent_jbar_out_0_a_valid; // @[Xbar.scala:216:19]
assign coherent_jbar_anonOut_a_bits_opcode = coherent_jbar_out_0_a_bits_opcode; // @[Xbar.scala:216:19]
assign coherent_jbar_anonOut_a_bits_param = coherent_jbar_out_0_a_bits_param; // @[Xbar.scala:216:19]
assign coherent_jbar_anonOut_a_bits_size = coherent_jbar_out_0_a_bits_size; // @[Xbar.scala:216:19]
assign coherent_jbar_anonOut_a_bits_source = coherent_jbar_out_0_a_bits_source; // @[Xbar.scala:216:19]
assign coherent_jbar_anonOut_a_bits_address = coherent_jbar_out_0_a_bits_address; // @[Xbar.scala:216:19]
assign coherent_jbar_anonOut_a_bits_mask = coherent_jbar_out_0_a_bits_mask; // @[Xbar.scala:216:19]
assign coherent_jbar_anonOut_a_bits_data = coherent_jbar_out_0_a_bits_data; // @[Xbar.scala:216:19]
assign coherent_jbar_anonOut_a_bits_corrupt = coherent_jbar_out_0_a_bits_corrupt; // @[Xbar.scala:216:19]
assign coherent_jbar_anonOut_b_ready = coherent_jbar_out_0_b_ready; // @[Xbar.scala:216:19]
wire coherent_jbar__portsBIO_filtered_0_valid_T_1 = coherent_jbar_out_0_b_valid; // @[Xbar.scala:216:19, :355:40]
assign coherent_jbar_portsBIO_filtered_0_bits_param = coherent_jbar_out_0_b_bits_param; // @[Xbar.scala:216:19, :352:24]
assign coherent_jbar_portsBIO_filtered_0_bits_address = coherent_jbar_out_0_b_bits_address; // @[Xbar.scala:216:19, :352:24]
assign coherent_jbar_portsCOI_filtered_0_ready = coherent_jbar_out_0_c_ready; // @[Xbar.scala:216:19, :352:24]
wire coherent_jbar_portsCOI_filtered_0_valid; // @[Xbar.scala:352:24]
assign coherent_jbar_anonOut_c_valid = coherent_jbar_out_0_c_valid; // @[Xbar.scala:216:19]
assign coherent_jbar_anonOut_c_bits_opcode = coherent_jbar_out_0_c_bits_opcode; // @[Xbar.scala:216:19]
assign coherent_jbar_anonOut_c_bits_param = coherent_jbar_out_0_c_bits_param; // @[Xbar.scala:216:19]
assign coherent_jbar_anonOut_c_bits_size = coherent_jbar_out_0_c_bits_size; // @[Xbar.scala:216:19]
assign coherent_jbar_anonOut_c_bits_source = coherent_jbar_out_0_c_bits_source; // @[Xbar.scala:216:19]
assign coherent_jbar_anonOut_c_bits_address = coherent_jbar_out_0_c_bits_address; // @[Xbar.scala:216:19]
assign coherent_jbar_anonOut_c_bits_data = coherent_jbar_out_0_c_bits_data; // @[Xbar.scala:216:19]
assign coherent_jbar_anonOut_c_bits_corrupt = coherent_jbar_out_0_c_bits_corrupt; // @[Xbar.scala:216:19]
assign coherent_jbar_anonOut_d_ready = coherent_jbar_out_0_d_ready; // @[Xbar.scala:216:19]
wire coherent_jbar__portsDIO_filtered_0_valid_T_1 = coherent_jbar_out_0_d_valid; // @[Xbar.scala:216:19, :355:40]
assign coherent_jbar_portsDIO_filtered_0_bits_opcode = coherent_jbar_out_0_d_bits_opcode; // @[Xbar.scala:216:19, :352:24]
assign coherent_jbar_portsDIO_filtered_0_bits_param = coherent_jbar_out_0_d_bits_param; // @[Xbar.scala:216:19, :352:24]
assign coherent_jbar_portsDIO_filtered_0_bits_size = coherent_jbar_out_0_d_bits_size; // @[Xbar.scala:216:19, :352:24]
wire [7:0] coherent_jbar__requestDOI_uncommonBits_T = coherent_jbar_out_0_d_bits_source; // @[Xbar.scala:216:19]
assign coherent_jbar_portsDIO_filtered_0_bits_source = coherent_jbar_out_0_d_bits_source; // @[Xbar.scala:216:19, :352:24]
assign coherent_jbar_portsDIO_filtered_0_bits_sink = coherent_jbar_out_0_d_bits_sink; // @[Xbar.scala:216:19, :352:24]
assign coherent_jbar_portsDIO_filtered_0_bits_denied = coherent_jbar_out_0_d_bits_denied; // @[Xbar.scala:216:19, :352:24]
assign coherent_jbar_portsDIO_filtered_0_bits_data = coherent_jbar_out_0_d_bits_data; // @[Xbar.scala:216:19, :352:24]
assign coherent_jbar_portsDIO_filtered_0_bits_corrupt = coherent_jbar_out_0_d_bits_corrupt; // @[Xbar.scala:216:19, :352:24]
wire coherent_jbar_portsEOI_filtered_0_valid; // @[Xbar.scala:352:24]
assign coherent_jbar_anonOut_e_valid = coherent_jbar_out_0_e_valid; // @[Xbar.scala:216:19]
assign coherent_jbar__anonOut_e_bits_sink_T = coherent_jbar_out_0_e_bits_sink; // @[Xbar.scala:156:69, :216:19]
assign coherent_jbar_out_0_d_bits_sink = coherent_jbar__out_0_d_bits_sink_T; // @[Xbar.scala:216:19, :251:53]
assign coherent_jbar_anonOut_e_bits_sink = coherent_jbar__anonOut_e_bits_sink_T; // @[Xbar.scala:156:69]
wire [32:0] coherent_jbar__requestAIO_T_1 = {1'h0, coherent_jbar__requestAIO_T}; // @[Parameters.scala:137:{31,41}]
wire [32:0] coherent_jbar__requestCIO_T_1 = {1'h0, coherent_jbar__requestCIO_T}; // @[Parameters.scala:137:{31,41}]
wire [7:0] coherent_jbar_requestDOI_uncommonBits = coherent_jbar__requestDOI_uncommonBits_T; // @[Parameters.scala:52:{29,56}]
wire [4:0] coherent_jbar_requestEIO_uncommonBits = coherent_jbar__requestEIO_uncommonBits_T; // @[Parameters.scala:52:{29,56}]
wire [12:0] coherent_jbar__beatsAI_decode_T = 13'h3F << coherent_jbar_in_0_a_bits_size; // @[package.scala:243:71]
wire [5:0] coherent_jbar__beatsAI_decode_T_1 = coherent_jbar__beatsAI_decode_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] coherent_jbar__beatsAI_decode_T_2 = ~coherent_jbar__beatsAI_decode_T_1; // @[package.scala:243:{46,76}]
wire coherent_jbar_beatsAI_decode = coherent_jbar__beatsAI_decode_T_2[5]; // @[package.scala:243:46]
wire coherent_jbar__beatsAI_opdata_T = coherent_jbar_in_0_a_bits_opcode[2]; // @[Xbar.scala:159:18]
wire coherent_jbar_beatsAI_opdata = ~coherent_jbar__beatsAI_opdata_T; // @[Edges.scala:92:{28,37}]
wire coherent_jbar_beatsAI_0 = coherent_jbar_beatsAI_opdata & coherent_jbar_beatsAI_decode; // @[Edges.scala:92:28, :220:59, :221:14]
wire [12:0] coherent_jbar__beatsCI_decode_T = 13'h3F << coherent_jbar_in_0_c_bits_size; // @[package.scala:243:71]
wire [5:0] coherent_jbar__beatsCI_decode_T_1 = coherent_jbar__beatsCI_decode_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] coherent_jbar__beatsCI_decode_T_2 = ~coherent_jbar__beatsCI_decode_T_1; // @[package.scala:243:{46,76}]
wire coherent_jbar_beatsCI_decode = coherent_jbar__beatsCI_decode_T_2[5]; // @[package.scala:243:46]
wire coherent_jbar_beatsCI_opdata = coherent_jbar_in_0_c_bits_opcode[0]; // @[Xbar.scala:159:18]
wire coherent_jbar_beatsCI_0 = coherent_jbar_beatsCI_opdata & coherent_jbar_beatsCI_decode; // @[Edges.scala:102:36, :220:59, :221:14]
wire [12:0] coherent_jbar__beatsDO_decode_T = 13'h3F << coherent_jbar_out_0_d_bits_size; // @[package.scala:243:71]
wire [5:0] coherent_jbar__beatsDO_decode_T_1 = coherent_jbar__beatsDO_decode_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] coherent_jbar__beatsDO_decode_T_2 = ~coherent_jbar__beatsDO_decode_T_1; // @[package.scala:243:{46,76}]
wire coherent_jbar_beatsDO_decode = coherent_jbar__beatsDO_decode_T_2[5]; // @[package.scala:243:46]
wire coherent_jbar_beatsDO_opdata = coherent_jbar_out_0_d_bits_opcode[0]; // @[Xbar.scala:216:19]
wire coherent_jbar_beatsDO_0 = coherent_jbar_beatsDO_opdata & coherent_jbar_beatsDO_decode; // @[Edges.scala:106:36, :220:59, :221:14]
assign coherent_jbar_in_0_a_ready = coherent_jbar_portsAOI_filtered_0_ready; // @[Xbar.scala:159:18, :352:24]
assign coherent_jbar_out_0_a_valid = coherent_jbar_portsAOI_filtered_0_valid; // @[Xbar.scala:216:19, :352:24]
assign coherent_jbar_out_0_a_bits_opcode = coherent_jbar_portsAOI_filtered_0_bits_opcode; // @[Xbar.scala:216:19, :352:24]
assign coherent_jbar_out_0_a_bits_param = coherent_jbar_portsAOI_filtered_0_bits_param; // @[Xbar.scala:216:19, :352:24]
assign coherent_jbar_out_0_a_bits_size = coherent_jbar_portsAOI_filtered_0_bits_size; // @[Xbar.scala:216:19, :352:24]
assign coherent_jbar_out_0_a_bits_source = coherent_jbar_portsAOI_filtered_0_bits_source; // @[Xbar.scala:216:19, :352:24]
assign coherent_jbar_out_0_a_bits_address = coherent_jbar_portsAOI_filtered_0_bits_address; // @[Xbar.scala:216:19, :352:24]
assign coherent_jbar_out_0_a_bits_mask = coherent_jbar_portsAOI_filtered_0_bits_mask; // @[Xbar.scala:216:19, :352:24]
assign coherent_jbar_out_0_a_bits_data = coherent_jbar_portsAOI_filtered_0_bits_data; // @[Xbar.scala:216:19, :352:24]
assign coherent_jbar_out_0_a_bits_corrupt = coherent_jbar_portsAOI_filtered_0_bits_corrupt; // @[Xbar.scala:216:19, :352:24]
assign coherent_jbar_portsAOI_filtered_0_valid = coherent_jbar__portsAOI_filtered_0_valid_T_1; // @[Xbar.scala:352:24, :355:40]
assign coherent_jbar_out_0_b_ready = coherent_jbar_portsBIO_filtered_0_ready; // @[Xbar.scala:216:19, :352:24]
assign coherent_jbar_in_0_b_valid = coherent_jbar_portsBIO_filtered_0_valid; // @[Xbar.scala:159:18, :352:24]
assign coherent_jbar_in_0_b_bits_param = coherent_jbar_portsBIO_filtered_0_bits_param; // @[Xbar.scala:159:18, :352:24]
assign coherent_jbar_in_0_b_bits_address = coherent_jbar_portsBIO_filtered_0_bits_address; // @[Xbar.scala:159:18, :352:24]
assign coherent_jbar_portsBIO_filtered_0_valid = coherent_jbar__portsBIO_filtered_0_valid_T_1; // @[Xbar.scala:352:24, :355:40]
assign coherent_jbar_in_0_c_ready = coherent_jbar_portsCOI_filtered_0_ready; // @[Xbar.scala:159:18, :352:24]
assign coherent_jbar_out_0_c_valid = coherent_jbar_portsCOI_filtered_0_valid; // @[Xbar.scala:216:19, :352:24]
assign coherent_jbar_out_0_c_bits_opcode = coherent_jbar_portsCOI_filtered_0_bits_opcode; // @[Xbar.scala:216:19, :352:24]
assign coherent_jbar_out_0_c_bits_param = coherent_jbar_portsCOI_filtered_0_bits_param; // @[Xbar.scala:216:19, :352:24]
assign coherent_jbar_out_0_c_bits_size = coherent_jbar_portsCOI_filtered_0_bits_size; // @[Xbar.scala:216:19, :352:24]
assign coherent_jbar_out_0_c_bits_source = coherent_jbar_portsCOI_filtered_0_bits_source; // @[Xbar.scala:216:19, :352:24]
assign coherent_jbar_out_0_c_bits_address = coherent_jbar_portsCOI_filtered_0_bits_address; // @[Xbar.scala:216:19, :352:24]
assign coherent_jbar_out_0_c_bits_data = coherent_jbar_portsCOI_filtered_0_bits_data; // @[Xbar.scala:216:19, :352:24]
assign coherent_jbar_out_0_c_bits_corrupt = coherent_jbar_portsCOI_filtered_0_bits_corrupt; // @[Xbar.scala:216:19, :352:24]
assign coherent_jbar_portsCOI_filtered_0_valid = coherent_jbar__portsCOI_filtered_0_valid_T_1; // @[Xbar.scala:352:24, :355:40]
assign coherent_jbar_out_0_d_ready = coherent_jbar_portsDIO_filtered_0_ready; // @[Xbar.scala:216:19, :352:24]
assign coherent_jbar_in_0_d_valid = coherent_jbar_portsDIO_filtered_0_valid; // @[Xbar.scala:159:18, :352:24]
assign coherent_jbar_in_0_d_bits_opcode = coherent_jbar_portsDIO_filtered_0_bits_opcode; // @[Xbar.scala:159:18, :352:24]
assign coherent_jbar_in_0_d_bits_param = coherent_jbar_portsDIO_filtered_0_bits_param; // @[Xbar.scala:159:18, :352:24]
assign coherent_jbar_in_0_d_bits_size = coherent_jbar_portsDIO_filtered_0_bits_size; // @[Xbar.scala:159:18, :352:24]
assign coherent_jbar_in_0_d_bits_source = coherent_jbar_portsDIO_filtered_0_bits_source; // @[Xbar.scala:159:18, :352:24]
assign coherent_jbar_in_0_d_bits_sink = coherent_jbar_portsDIO_filtered_0_bits_sink; // @[Xbar.scala:159:18, :352:24]
assign coherent_jbar_in_0_d_bits_denied = coherent_jbar_portsDIO_filtered_0_bits_denied; // @[Xbar.scala:159:18, :352:24]
assign coherent_jbar_in_0_d_bits_data = coherent_jbar_portsDIO_filtered_0_bits_data; // @[Xbar.scala:159:18, :352:24]
assign coherent_jbar_in_0_d_bits_corrupt = coherent_jbar_portsDIO_filtered_0_bits_corrupt; // @[Xbar.scala:159:18, :352:24]
assign coherent_jbar_portsDIO_filtered_0_valid = coherent_jbar__portsDIO_filtered_0_valid_T_1; // @[Xbar.scala:352:24, :355:40]
assign coherent_jbar_out_0_e_valid = coherent_jbar_portsEOI_filtered_0_valid; // @[Xbar.scala:216:19, :352:24]
assign coherent_jbar_out_0_e_bits_sink = coherent_jbar_portsEOI_filtered_0_bits_sink; // @[Xbar.scala:216:19, :352:24]
assign coherent_jbar_portsEOI_filtered_0_valid = coherent_jbar__portsEOI_filtered_0_valid_T_1; // @[Xbar.scala:352:24, :355:40]
wire coupler_to_bus_named_mbus_widget_auto_anon_in_a_ready; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_mbus_widget_auto_anon_in_a_valid = coupler_to_bus_named_mbus_auto_widget_anon_in_a_valid; // @[WidthWidget.scala:27:9]
wire [2:0] coupler_to_bus_named_mbus_widget_auto_anon_in_a_bits_opcode = coupler_to_bus_named_mbus_auto_widget_anon_in_a_bits_opcode; // @[WidthWidget.scala:27:9]
wire [2:0] coupler_to_bus_named_mbus_widget_auto_anon_in_a_bits_param = coupler_to_bus_named_mbus_auto_widget_anon_in_a_bits_param; // @[WidthWidget.scala:27:9]
wire [2:0] coupler_to_bus_named_mbus_widget_auto_anon_in_a_bits_size = coupler_to_bus_named_mbus_auto_widget_anon_in_a_bits_size; // @[WidthWidget.scala:27:9]
wire [5:0] coupler_to_bus_named_mbus_widget_auto_anon_in_a_bits_source = coupler_to_bus_named_mbus_auto_widget_anon_in_a_bits_source; // @[WidthWidget.scala:27:9]
wire [31:0] coupler_to_bus_named_mbus_widget_auto_anon_in_a_bits_address = coupler_to_bus_named_mbus_auto_widget_anon_in_a_bits_address; // @[WidthWidget.scala:27:9]
wire [7:0] coupler_to_bus_named_mbus_widget_auto_anon_in_a_bits_mask = coupler_to_bus_named_mbus_auto_widget_anon_in_a_bits_mask; // @[WidthWidget.scala:27:9]
wire [63:0] coupler_to_bus_named_mbus_widget_auto_anon_in_a_bits_data = coupler_to_bus_named_mbus_auto_widget_anon_in_a_bits_data; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_mbus_widget_auto_anon_in_a_bits_corrupt = coupler_to_bus_named_mbus_auto_widget_anon_in_a_bits_corrupt; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_mbus_widget_auto_anon_in_d_ready = coupler_to_bus_named_mbus_auto_widget_anon_in_d_ready; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_mbus_widget_auto_anon_in_d_valid; // @[WidthWidget.scala:27:9]
wire [2:0] coupler_to_bus_named_mbus_widget_auto_anon_in_d_bits_opcode; // @[WidthWidget.scala:27:9]
wire [1:0] coupler_to_bus_named_mbus_widget_auto_anon_in_d_bits_param; // @[WidthWidget.scala:27:9]
wire [2:0] coupler_to_bus_named_mbus_widget_auto_anon_in_d_bits_size; // @[WidthWidget.scala:27:9]
wire [5:0] coupler_to_bus_named_mbus_widget_auto_anon_in_d_bits_source; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_mbus_widget_auto_anon_in_d_bits_sink; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_mbus_widget_auto_anon_in_d_bits_denied; // @[WidthWidget.scala:27:9]
wire [63:0] coupler_to_bus_named_mbus_widget_auto_anon_in_d_bits_data; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_mbus_widget_auto_anon_in_d_bits_corrupt; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_mbus_bus_xingOut_a_ready = coupler_to_bus_named_mbus_auto_bus_xing_out_a_ready; // @[MixedNode.scala:542:17]
wire coupler_to_bus_named_mbus_bus_xingOut_a_valid; // @[MixedNode.scala:542:17]
assign auto_coupler_to_bus_named_mbus_bus_xing_out_a_valid_0 = coupler_to_bus_named_mbus_auto_bus_xing_out_a_valid; // @[ClockDomain.scala:14:9]
wire [2:0] coupler_to_bus_named_mbus_bus_xingOut_a_bits_opcode; // @[MixedNode.scala:542:17]
assign auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_opcode_0 = coupler_to_bus_named_mbus_auto_bus_xing_out_a_bits_opcode; // @[ClockDomain.scala:14:9]
wire [2:0] coupler_to_bus_named_mbus_bus_xingOut_a_bits_param; // @[MixedNode.scala:542:17]
assign auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_param_0 = coupler_to_bus_named_mbus_auto_bus_xing_out_a_bits_param; // @[ClockDomain.scala:14:9]
wire [2:0] coupler_to_bus_named_mbus_bus_xingOut_a_bits_size; // @[MixedNode.scala:542:17]
assign auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_size_0 = coupler_to_bus_named_mbus_auto_bus_xing_out_a_bits_size; // @[ClockDomain.scala:14:9]
wire [5:0] coupler_to_bus_named_mbus_bus_xingOut_a_bits_source; // @[MixedNode.scala:542:17]
assign auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_source_0 = coupler_to_bus_named_mbus_auto_bus_xing_out_a_bits_source; // @[ClockDomain.scala:14:9]
wire [31:0] coupler_to_bus_named_mbus_bus_xingOut_a_bits_address; // @[MixedNode.scala:542:17]
assign auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_address_0 = coupler_to_bus_named_mbus_auto_bus_xing_out_a_bits_address; // @[ClockDomain.scala:14:9]
wire [7:0] coupler_to_bus_named_mbus_bus_xingOut_a_bits_mask; // @[MixedNode.scala:542:17]
assign auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_mask_0 = coupler_to_bus_named_mbus_auto_bus_xing_out_a_bits_mask; // @[ClockDomain.scala:14:9]
wire [63:0] coupler_to_bus_named_mbus_bus_xingOut_a_bits_data; // @[MixedNode.scala:542:17]
assign auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_data_0 = coupler_to_bus_named_mbus_auto_bus_xing_out_a_bits_data; // @[ClockDomain.scala:14:9]
wire coupler_to_bus_named_mbus_bus_xingOut_a_bits_corrupt; // @[MixedNode.scala:542:17]
assign auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_corrupt_0 = coupler_to_bus_named_mbus_auto_bus_xing_out_a_bits_corrupt; // @[ClockDomain.scala:14:9]
wire coupler_to_bus_named_mbus_bus_xingOut_d_ready; // @[MixedNode.scala:542:17]
assign auto_coupler_to_bus_named_mbus_bus_xing_out_d_ready_0 = coupler_to_bus_named_mbus_auto_bus_xing_out_d_ready; // @[ClockDomain.scala:14:9]
wire coupler_to_bus_named_mbus_bus_xingOut_d_valid = coupler_to_bus_named_mbus_auto_bus_xing_out_d_valid; // @[MixedNode.scala:542:17]
wire [2:0] coupler_to_bus_named_mbus_bus_xingOut_d_bits_opcode = coupler_to_bus_named_mbus_auto_bus_xing_out_d_bits_opcode; // @[MixedNode.scala:542:17]
wire [1:0] coupler_to_bus_named_mbus_bus_xingOut_d_bits_param = coupler_to_bus_named_mbus_auto_bus_xing_out_d_bits_param; // @[MixedNode.scala:542:17]
wire [2:0] coupler_to_bus_named_mbus_bus_xingOut_d_bits_size = coupler_to_bus_named_mbus_auto_bus_xing_out_d_bits_size; // @[MixedNode.scala:542:17]
wire [5:0] coupler_to_bus_named_mbus_bus_xingOut_d_bits_source = coupler_to_bus_named_mbus_auto_bus_xing_out_d_bits_source; // @[MixedNode.scala:542:17]
wire coupler_to_bus_named_mbus_bus_xingOut_d_bits_sink = coupler_to_bus_named_mbus_auto_bus_xing_out_d_bits_sink; // @[MixedNode.scala:542:17]
wire coupler_to_bus_named_mbus_bus_xingOut_d_bits_denied = coupler_to_bus_named_mbus_auto_bus_xing_out_d_bits_denied; // @[MixedNode.scala:542:17]
wire [63:0] coupler_to_bus_named_mbus_bus_xingOut_d_bits_data = coupler_to_bus_named_mbus_auto_bus_xing_out_d_bits_data; // @[MixedNode.scala:542:17]
wire coupler_to_bus_named_mbus_bus_xingOut_d_bits_corrupt = coupler_to_bus_named_mbus_auto_bus_xing_out_d_bits_corrupt; // @[MixedNode.scala:542:17]
wire coupler_to_bus_named_mbus_auto_widget_anon_in_a_ready; // @[LazyModuleImp.scala:138:7]
wire [2:0] coupler_to_bus_named_mbus_auto_widget_anon_in_d_bits_opcode; // @[LazyModuleImp.scala:138:7]
wire [1:0] coupler_to_bus_named_mbus_auto_widget_anon_in_d_bits_param; // @[LazyModuleImp.scala:138:7]
wire [2:0] coupler_to_bus_named_mbus_auto_widget_anon_in_d_bits_size; // @[LazyModuleImp.scala:138:7]
wire [5:0] coupler_to_bus_named_mbus_auto_widget_anon_in_d_bits_source; // @[LazyModuleImp.scala:138:7]
wire coupler_to_bus_named_mbus_auto_widget_anon_in_d_bits_sink; // @[LazyModuleImp.scala:138:7]
wire coupler_to_bus_named_mbus_auto_widget_anon_in_d_bits_denied; // @[LazyModuleImp.scala:138:7]
wire [63:0] coupler_to_bus_named_mbus_auto_widget_anon_in_d_bits_data; // @[LazyModuleImp.scala:138:7]
wire coupler_to_bus_named_mbus_auto_widget_anon_in_d_bits_corrupt; // @[LazyModuleImp.scala:138:7]
wire coupler_to_bus_named_mbus_auto_widget_anon_in_d_valid; // @[LazyModuleImp.scala:138:7]
wire coupler_to_bus_named_mbus_widget_anonIn_a_ready; // @[MixedNode.scala:551:17]
assign coupler_to_bus_named_mbus_auto_widget_anon_in_a_ready = coupler_to_bus_named_mbus_widget_auto_anon_in_a_ready; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_mbus_widget_anonIn_a_valid = coupler_to_bus_named_mbus_widget_auto_anon_in_a_valid; // @[WidthWidget.scala:27:9]
wire [2:0] coupler_to_bus_named_mbus_widget_anonIn_a_bits_opcode = coupler_to_bus_named_mbus_widget_auto_anon_in_a_bits_opcode; // @[WidthWidget.scala:27:9]
wire [2:0] coupler_to_bus_named_mbus_widget_anonIn_a_bits_param = coupler_to_bus_named_mbus_widget_auto_anon_in_a_bits_param; // @[WidthWidget.scala:27:9]
wire [2:0] coupler_to_bus_named_mbus_widget_anonIn_a_bits_size = coupler_to_bus_named_mbus_widget_auto_anon_in_a_bits_size; // @[WidthWidget.scala:27:9]
wire [5:0] coupler_to_bus_named_mbus_widget_anonIn_a_bits_source = coupler_to_bus_named_mbus_widget_auto_anon_in_a_bits_source; // @[WidthWidget.scala:27:9]
wire [31:0] coupler_to_bus_named_mbus_widget_anonIn_a_bits_address = coupler_to_bus_named_mbus_widget_auto_anon_in_a_bits_address; // @[WidthWidget.scala:27:9]
wire [7:0] coupler_to_bus_named_mbus_widget_anonIn_a_bits_mask = coupler_to_bus_named_mbus_widget_auto_anon_in_a_bits_mask; // @[WidthWidget.scala:27:9]
wire [63:0] coupler_to_bus_named_mbus_widget_anonIn_a_bits_data = coupler_to_bus_named_mbus_widget_auto_anon_in_a_bits_data; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_mbus_widget_anonIn_a_bits_corrupt = coupler_to_bus_named_mbus_widget_auto_anon_in_a_bits_corrupt; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_mbus_widget_anonIn_d_ready = coupler_to_bus_named_mbus_widget_auto_anon_in_d_ready; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_mbus_widget_anonIn_d_valid; // @[MixedNode.scala:551:17]
assign coupler_to_bus_named_mbus_auto_widget_anon_in_d_valid = coupler_to_bus_named_mbus_widget_auto_anon_in_d_valid; // @[WidthWidget.scala:27:9]
wire [2:0] coupler_to_bus_named_mbus_widget_anonIn_d_bits_opcode; // @[MixedNode.scala:551:17]
assign coupler_to_bus_named_mbus_auto_widget_anon_in_d_bits_opcode = coupler_to_bus_named_mbus_widget_auto_anon_in_d_bits_opcode; // @[WidthWidget.scala:27:9]
wire [1:0] coupler_to_bus_named_mbus_widget_anonIn_d_bits_param; // @[MixedNode.scala:551:17]
assign coupler_to_bus_named_mbus_auto_widget_anon_in_d_bits_param = coupler_to_bus_named_mbus_widget_auto_anon_in_d_bits_param; // @[WidthWidget.scala:27:9]
wire [2:0] coupler_to_bus_named_mbus_widget_anonIn_d_bits_size; // @[MixedNode.scala:551:17]
assign coupler_to_bus_named_mbus_auto_widget_anon_in_d_bits_size = coupler_to_bus_named_mbus_widget_auto_anon_in_d_bits_size; // @[WidthWidget.scala:27:9]
wire [5:0] coupler_to_bus_named_mbus_widget_anonIn_d_bits_source; // @[MixedNode.scala:551:17]
assign coupler_to_bus_named_mbus_auto_widget_anon_in_d_bits_source = coupler_to_bus_named_mbus_widget_auto_anon_in_d_bits_source; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_mbus_widget_anonIn_d_bits_sink; // @[MixedNode.scala:551:17]
assign coupler_to_bus_named_mbus_auto_widget_anon_in_d_bits_sink = coupler_to_bus_named_mbus_widget_auto_anon_in_d_bits_sink; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_mbus_widget_anonIn_d_bits_denied; // @[MixedNode.scala:551:17]
assign coupler_to_bus_named_mbus_auto_widget_anon_in_d_bits_denied = coupler_to_bus_named_mbus_widget_auto_anon_in_d_bits_denied; // @[WidthWidget.scala:27:9]
wire [63:0] coupler_to_bus_named_mbus_widget_anonIn_d_bits_data; // @[MixedNode.scala:551:17]
assign coupler_to_bus_named_mbus_auto_widget_anon_in_d_bits_data = coupler_to_bus_named_mbus_widget_auto_anon_in_d_bits_data; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_mbus_widget_anonIn_d_bits_corrupt; // @[MixedNode.scala:551:17]
assign coupler_to_bus_named_mbus_auto_widget_anon_in_d_bits_corrupt = coupler_to_bus_named_mbus_widget_auto_anon_in_d_bits_corrupt; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_mbus_bus_xingIn_a_ready; // @[MixedNode.scala:551:17]
wire coupler_to_bus_named_mbus_widget_anonOut_a_ready = coupler_to_bus_named_mbus_widget_auto_anon_out_a_ready; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_mbus_widget_anonOut_a_valid; // @[MixedNode.scala:542:17]
wire [2:0] coupler_to_bus_named_mbus_widget_anonOut_a_bits_opcode; // @[MixedNode.scala:542:17]
wire coupler_to_bus_named_mbus_bus_xingIn_a_valid = coupler_to_bus_named_mbus_widget_auto_anon_out_a_valid; // @[WidthWidget.scala:27:9]
wire [2:0] coupler_to_bus_named_mbus_widget_anonOut_a_bits_param; // @[MixedNode.scala:542:17]
wire [2:0] coupler_to_bus_named_mbus_bus_xingIn_a_bits_opcode = coupler_to_bus_named_mbus_widget_auto_anon_out_a_bits_opcode; // @[WidthWidget.scala:27:9]
wire [2:0] coupler_to_bus_named_mbus_widget_anonOut_a_bits_size; // @[MixedNode.scala:542:17]
wire [2:0] coupler_to_bus_named_mbus_bus_xingIn_a_bits_param = coupler_to_bus_named_mbus_widget_auto_anon_out_a_bits_param; // @[WidthWidget.scala:27:9]
wire [5:0] coupler_to_bus_named_mbus_widget_anonOut_a_bits_source; // @[MixedNode.scala:542:17]
wire [2:0] coupler_to_bus_named_mbus_bus_xingIn_a_bits_size = coupler_to_bus_named_mbus_widget_auto_anon_out_a_bits_size; // @[WidthWidget.scala:27:9]
wire [31:0] coupler_to_bus_named_mbus_widget_anonOut_a_bits_address; // @[MixedNode.scala:542:17]
wire [5:0] coupler_to_bus_named_mbus_bus_xingIn_a_bits_source = coupler_to_bus_named_mbus_widget_auto_anon_out_a_bits_source; // @[WidthWidget.scala:27:9]
wire [7:0] coupler_to_bus_named_mbus_widget_anonOut_a_bits_mask; // @[MixedNode.scala:542:17]
wire [31:0] coupler_to_bus_named_mbus_bus_xingIn_a_bits_address = coupler_to_bus_named_mbus_widget_auto_anon_out_a_bits_address; // @[WidthWidget.scala:27:9]
wire [63:0] coupler_to_bus_named_mbus_widget_anonOut_a_bits_data; // @[MixedNode.scala:542:17]
wire [7:0] coupler_to_bus_named_mbus_bus_xingIn_a_bits_mask = coupler_to_bus_named_mbus_widget_auto_anon_out_a_bits_mask; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_mbus_widget_anonOut_a_bits_corrupt; // @[MixedNode.scala:542:17]
wire [63:0] coupler_to_bus_named_mbus_bus_xingIn_a_bits_data = coupler_to_bus_named_mbus_widget_auto_anon_out_a_bits_data; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_mbus_widget_anonOut_d_ready; // @[MixedNode.scala:542:17]
wire coupler_to_bus_named_mbus_bus_xingIn_a_bits_corrupt = coupler_to_bus_named_mbus_widget_auto_anon_out_a_bits_corrupt; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_mbus_bus_xingIn_d_ready = coupler_to_bus_named_mbus_widget_auto_anon_out_d_ready; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_mbus_bus_xingIn_d_valid; // @[MixedNode.scala:551:17]
wire coupler_to_bus_named_mbus_widget_anonOut_d_valid = coupler_to_bus_named_mbus_widget_auto_anon_out_d_valid; // @[WidthWidget.scala:27:9]
wire [2:0] coupler_to_bus_named_mbus_bus_xingIn_d_bits_opcode; // @[MixedNode.scala:551:17]
wire [2:0] coupler_to_bus_named_mbus_widget_anonOut_d_bits_opcode = coupler_to_bus_named_mbus_widget_auto_anon_out_d_bits_opcode; // @[WidthWidget.scala:27:9]
wire [1:0] coupler_to_bus_named_mbus_bus_xingIn_d_bits_param; // @[MixedNode.scala:551:17]
wire [1:0] coupler_to_bus_named_mbus_widget_anonOut_d_bits_param = coupler_to_bus_named_mbus_widget_auto_anon_out_d_bits_param; // @[WidthWidget.scala:27:9]
wire [2:0] coupler_to_bus_named_mbus_bus_xingIn_d_bits_size; // @[MixedNode.scala:551:17]
wire [2:0] coupler_to_bus_named_mbus_widget_anonOut_d_bits_size = coupler_to_bus_named_mbus_widget_auto_anon_out_d_bits_size; // @[WidthWidget.scala:27:9]
wire [5:0] coupler_to_bus_named_mbus_bus_xingIn_d_bits_source; // @[MixedNode.scala:551:17]
wire [5:0] coupler_to_bus_named_mbus_widget_anonOut_d_bits_source = coupler_to_bus_named_mbus_widget_auto_anon_out_d_bits_source; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_mbus_bus_xingIn_d_bits_sink; // @[MixedNode.scala:551:17]
wire coupler_to_bus_named_mbus_widget_anonOut_d_bits_sink = coupler_to_bus_named_mbus_widget_auto_anon_out_d_bits_sink; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_mbus_bus_xingIn_d_bits_denied; // @[MixedNode.scala:551:17]
wire coupler_to_bus_named_mbus_widget_anonOut_d_bits_denied = coupler_to_bus_named_mbus_widget_auto_anon_out_d_bits_denied; // @[WidthWidget.scala:27:9]
wire [63:0] coupler_to_bus_named_mbus_bus_xingIn_d_bits_data; // @[MixedNode.scala:551:17]
wire [63:0] coupler_to_bus_named_mbus_widget_anonOut_d_bits_data = coupler_to_bus_named_mbus_widget_auto_anon_out_d_bits_data; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_mbus_bus_xingIn_d_bits_corrupt; // @[MixedNode.scala:551:17]
wire coupler_to_bus_named_mbus_widget_anonOut_d_bits_corrupt = coupler_to_bus_named_mbus_widget_auto_anon_out_d_bits_corrupt; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_mbus_widget_anonIn_a_ready = coupler_to_bus_named_mbus_widget_anonOut_a_ready; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_mbus_widget_auto_anon_out_a_valid = coupler_to_bus_named_mbus_widget_anonOut_a_valid; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_mbus_widget_auto_anon_out_a_bits_opcode = coupler_to_bus_named_mbus_widget_anonOut_a_bits_opcode; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_mbus_widget_auto_anon_out_a_bits_param = coupler_to_bus_named_mbus_widget_anonOut_a_bits_param; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_mbus_widget_auto_anon_out_a_bits_size = coupler_to_bus_named_mbus_widget_anonOut_a_bits_size; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_mbus_widget_auto_anon_out_a_bits_source = coupler_to_bus_named_mbus_widget_anonOut_a_bits_source; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_mbus_widget_auto_anon_out_a_bits_address = coupler_to_bus_named_mbus_widget_anonOut_a_bits_address; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_mbus_widget_auto_anon_out_a_bits_mask = coupler_to_bus_named_mbus_widget_anonOut_a_bits_mask; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_mbus_widget_auto_anon_out_a_bits_data = coupler_to_bus_named_mbus_widget_anonOut_a_bits_data; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_mbus_widget_auto_anon_out_a_bits_corrupt = coupler_to_bus_named_mbus_widget_anonOut_a_bits_corrupt; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_mbus_widget_auto_anon_out_d_ready = coupler_to_bus_named_mbus_widget_anonOut_d_ready; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_mbus_widget_anonIn_d_valid = coupler_to_bus_named_mbus_widget_anonOut_d_valid; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_mbus_widget_anonIn_d_bits_opcode = coupler_to_bus_named_mbus_widget_anonOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_mbus_widget_anonIn_d_bits_param = coupler_to_bus_named_mbus_widget_anonOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_mbus_widget_anonIn_d_bits_size = coupler_to_bus_named_mbus_widget_anonOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_mbus_widget_anonIn_d_bits_source = coupler_to_bus_named_mbus_widget_anonOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_mbus_widget_anonIn_d_bits_sink = coupler_to_bus_named_mbus_widget_anonOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_mbus_widget_anonIn_d_bits_denied = coupler_to_bus_named_mbus_widget_anonOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_mbus_widget_anonIn_d_bits_data = coupler_to_bus_named_mbus_widget_anonOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_mbus_widget_anonIn_d_bits_corrupt = coupler_to_bus_named_mbus_widget_anonOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_mbus_widget_auto_anon_in_a_ready = coupler_to_bus_named_mbus_widget_anonIn_a_ready; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_mbus_widget_anonOut_a_valid = coupler_to_bus_named_mbus_widget_anonIn_a_valid; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_mbus_widget_anonOut_a_bits_opcode = coupler_to_bus_named_mbus_widget_anonIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_mbus_widget_anonOut_a_bits_param = coupler_to_bus_named_mbus_widget_anonIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_mbus_widget_anonOut_a_bits_size = coupler_to_bus_named_mbus_widget_anonIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_mbus_widget_anonOut_a_bits_source = coupler_to_bus_named_mbus_widget_anonIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_mbus_widget_anonOut_a_bits_address = coupler_to_bus_named_mbus_widget_anonIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_mbus_widget_anonOut_a_bits_mask = coupler_to_bus_named_mbus_widget_anonIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_mbus_widget_anonOut_a_bits_data = coupler_to_bus_named_mbus_widget_anonIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_mbus_widget_anonOut_a_bits_corrupt = coupler_to_bus_named_mbus_widget_anonIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_mbus_widget_anonOut_d_ready = coupler_to_bus_named_mbus_widget_anonIn_d_ready; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_mbus_widget_auto_anon_in_d_valid = coupler_to_bus_named_mbus_widget_anonIn_d_valid; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_mbus_widget_auto_anon_in_d_bits_opcode = coupler_to_bus_named_mbus_widget_anonIn_d_bits_opcode; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_mbus_widget_auto_anon_in_d_bits_param = coupler_to_bus_named_mbus_widget_anonIn_d_bits_param; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_mbus_widget_auto_anon_in_d_bits_size = coupler_to_bus_named_mbus_widget_anonIn_d_bits_size; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_mbus_widget_auto_anon_in_d_bits_source = coupler_to_bus_named_mbus_widget_anonIn_d_bits_source; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_mbus_widget_auto_anon_in_d_bits_sink = coupler_to_bus_named_mbus_widget_anonIn_d_bits_sink; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_mbus_widget_auto_anon_in_d_bits_denied = coupler_to_bus_named_mbus_widget_anonIn_d_bits_denied; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_mbus_widget_auto_anon_in_d_bits_data = coupler_to_bus_named_mbus_widget_anonIn_d_bits_data; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_mbus_widget_auto_anon_in_d_bits_corrupt = coupler_to_bus_named_mbus_widget_anonIn_d_bits_corrupt; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_mbus_bus_xingIn_a_ready = coupler_to_bus_named_mbus_bus_xingOut_a_ready; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_mbus_auto_bus_xing_out_a_valid = coupler_to_bus_named_mbus_bus_xingOut_a_valid; // @[MixedNode.scala:542:17]
assign coupler_to_bus_named_mbus_auto_bus_xing_out_a_bits_opcode = coupler_to_bus_named_mbus_bus_xingOut_a_bits_opcode; // @[MixedNode.scala:542:17]
assign coupler_to_bus_named_mbus_auto_bus_xing_out_a_bits_param = coupler_to_bus_named_mbus_bus_xingOut_a_bits_param; // @[MixedNode.scala:542:17]
assign coupler_to_bus_named_mbus_auto_bus_xing_out_a_bits_size = coupler_to_bus_named_mbus_bus_xingOut_a_bits_size; // @[MixedNode.scala:542:17]
assign coupler_to_bus_named_mbus_auto_bus_xing_out_a_bits_source = coupler_to_bus_named_mbus_bus_xingOut_a_bits_source; // @[MixedNode.scala:542:17]
assign coupler_to_bus_named_mbus_auto_bus_xing_out_a_bits_address = coupler_to_bus_named_mbus_bus_xingOut_a_bits_address; // @[MixedNode.scala:542:17]
assign coupler_to_bus_named_mbus_auto_bus_xing_out_a_bits_mask = coupler_to_bus_named_mbus_bus_xingOut_a_bits_mask; // @[MixedNode.scala:542:17]
assign coupler_to_bus_named_mbus_auto_bus_xing_out_a_bits_data = coupler_to_bus_named_mbus_bus_xingOut_a_bits_data; // @[MixedNode.scala:542:17]
assign coupler_to_bus_named_mbus_auto_bus_xing_out_a_bits_corrupt = coupler_to_bus_named_mbus_bus_xingOut_a_bits_corrupt; // @[MixedNode.scala:542:17]
assign coupler_to_bus_named_mbus_auto_bus_xing_out_d_ready = coupler_to_bus_named_mbus_bus_xingOut_d_ready; // @[MixedNode.scala:542:17]
assign coupler_to_bus_named_mbus_bus_xingIn_d_valid = coupler_to_bus_named_mbus_bus_xingOut_d_valid; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_mbus_bus_xingIn_d_bits_opcode = coupler_to_bus_named_mbus_bus_xingOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_mbus_bus_xingIn_d_bits_param = coupler_to_bus_named_mbus_bus_xingOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_mbus_bus_xingIn_d_bits_size = coupler_to_bus_named_mbus_bus_xingOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_mbus_bus_xingIn_d_bits_source = coupler_to_bus_named_mbus_bus_xingOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_mbus_bus_xingIn_d_bits_sink = coupler_to_bus_named_mbus_bus_xingOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_mbus_bus_xingIn_d_bits_denied = coupler_to_bus_named_mbus_bus_xingOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_mbus_bus_xingIn_d_bits_data = coupler_to_bus_named_mbus_bus_xingOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_mbus_bus_xingIn_d_bits_corrupt = coupler_to_bus_named_mbus_bus_xingOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_mbus_widget_auto_anon_out_a_ready = coupler_to_bus_named_mbus_bus_xingIn_a_ready; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_mbus_bus_xingOut_a_valid = coupler_to_bus_named_mbus_bus_xingIn_a_valid; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_mbus_bus_xingOut_a_bits_opcode = coupler_to_bus_named_mbus_bus_xingIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_mbus_bus_xingOut_a_bits_param = coupler_to_bus_named_mbus_bus_xingIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_mbus_bus_xingOut_a_bits_size = coupler_to_bus_named_mbus_bus_xingIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_mbus_bus_xingOut_a_bits_source = coupler_to_bus_named_mbus_bus_xingIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_mbus_bus_xingOut_a_bits_address = coupler_to_bus_named_mbus_bus_xingIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_mbus_bus_xingOut_a_bits_mask = coupler_to_bus_named_mbus_bus_xingIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_mbus_bus_xingOut_a_bits_data = coupler_to_bus_named_mbus_bus_xingIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_mbus_bus_xingOut_a_bits_corrupt = coupler_to_bus_named_mbus_bus_xingIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_mbus_bus_xingOut_d_ready = coupler_to_bus_named_mbus_bus_xingIn_d_ready; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_mbus_widget_auto_anon_out_d_valid = coupler_to_bus_named_mbus_bus_xingIn_d_valid; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_mbus_widget_auto_anon_out_d_bits_opcode = coupler_to_bus_named_mbus_bus_xingIn_d_bits_opcode; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_mbus_widget_auto_anon_out_d_bits_param = coupler_to_bus_named_mbus_bus_xingIn_d_bits_param; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_mbus_widget_auto_anon_out_d_bits_size = coupler_to_bus_named_mbus_bus_xingIn_d_bits_size; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_mbus_widget_auto_anon_out_d_bits_source = coupler_to_bus_named_mbus_bus_xingIn_d_bits_source; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_mbus_widget_auto_anon_out_d_bits_sink = coupler_to_bus_named_mbus_bus_xingIn_d_bits_sink; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_mbus_widget_auto_anon_out_d_bits_denied = coupler_to_bus_named_mbus_bus_xingIn_d_bits_denied; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_mbus_widget_auto_anon_out_d_bits_data = coupler_to_bus_named_mbus_bus_xingIn_d_bits_data; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_mbus_widget_auto_anon_out_d_bits_corrupt = coupler_to_bus_named_mbus_bus_xingIn_d_bits_corrupt; // @[WidthWidget.scala:27:9]
assign childClock = clockSinkNodeIn_clock; // @[MixedNode.scala:551:17]
assign childReset = clockSinkNodeIn_reset; // @[MixedNode.scala:551:17]
InclusiveCache l2 ( // @[Configs.scala:93:24]
.clock (childClock), // @[LazyModuleImp.scala:155:31]
.reset (childReset), // @[LazyModuleImp.scala:158:31]
.auto_ctrls_ctrl_in_a_ready (auto_l2_ctrls_ctrl_in_a_ready_0),
.auto_ctrls_ctrl_in_a_valid (auto_l2_ctrls_ctrl_in_a_valid_0), // @[ClockDomain.scala:14:9]
.auto_ctrls_ctrl_in_a_bits_opcode (auto_l2_ctrls_ctrl_in_a_bits_opcode_0), // @[ClockDomain.scala:14:9]
.auto_ctrls_ctrl_in_a_bits_param (auto_l2_ctrls_ctrl_in_a_bits_param_0), // @[ClockDomain.scala:14:9]
.auto_ctrls_ctrl_in_a_bits_size (auto_l2_ctrls_ctrl_in_a_bits_size_0), // @[ClockDomain.scala:14:9]
.auto_ctrls_ctrl_in_a_bits_source (auto_l2_ctrls_ctrl_in_a_bits_source_0), // @[ClockDomain.scala:14:9]
.auto_ctrls_ctrl_in_a_bits_address (auto_l2_ctrls_ctrl_in_a_bits_address_0), // @[ClockDomain.scala:14:9]
.auto_ctrls_ctrl_in_a_bits_mask (auto_l2_ctrls_ctrl_in_a_bits_mask_0), // @[ClockDomain.scala:14:9]
.auto_ctrls_ctrl_in_a_bits_data (auto_l2_ctrls_ctrl_in_a_bits_data_0), // @[ClockDomain.scala:14:9]
.auto_ctrls_ctrl_in_a_bits_corrupt (auto_l2_ctrls_ctrl_in_a_bits_corrupt_0), // @[ClockDomain.scala:14:9]
.auto_ctrls_ctrl_in_d_ready (auto_l2_ctrls_ctrl_in_d_ready_0), // @[ClockDomain.scala:14:9]
.auto_ctrls_ctrl_in_d_valid (auto_l2_ctrls_ctrl_in_d_valid_0),
.auto_ctrls_ctrl_in_d_bits_opcode (auto_l2_ctrls_ctrl_in_d_bits_opcode_0),
.auto_ctrls_ctrl_in_d_bits_size (auto_l2_ctrls_ctrl_in_d_bits_size_0),
.auto_ctrls_ctrl_in_d_bits_source (auto_l2_ctrls_ctrl_in_d_bits_source_0),
.auto_ctrls_ctrl_in_d_bits_data (auto_l2_ctrls_ctrl_in_d_bits_data_0),
.auto_in_a_ready (_l2_auto_in_a_ready),
.auto_in_a_valid (_InclusiveCache_inner_TLBuffer_auto_out_a_valid), // @[Parameters.scala:56:69]
.auto_in_a_bits_opcode (_InclusiveCache_inner_TLBuffer_auto_out_a_bits_opcode), // @[Parameters.scala:56:69]
.auto_in_a_bits_param (_InclusiveCache_inner_TLBuffer_auto_out_a_bits_param), // @[Parameters.scala:56:69]
.auto_in_a_bits_size (_InclusiveCache_inner_TLBuffer_auto_out_a_bits_size), // @[Parameters.scala:56:69]
.auto_in_a_bits_source (_InclusiveCache_inner_TLBuffer_auto_out_a_bits_source), // @[Parameters.scala:56:69]
.auto_in_a_bits_address (_InclusiveCache_inner_TLBuffer_auto_out_a_bits_address), // @[Parameters.scala:56:69]
.auto_in_a_bits_mask (_InclusiveCache_inner_TLBuffer_auto_out_a_bits_mask), // @[Parameters.scala:56:69]
.auto_in_a_bits_data (_InclusiveCache_inner_TLBuffer_auto_out_a_bits_data), // @[Parameters.scala:56:69]
.auto_in_a_bits_corrupt (_InclusiveCache_inner_TLBuffer_auto_out_a_bits_corrupt), // @[Parameters.scala:56:69]
.auto_in_b_ready (_InclusiveCache_inner_TLBuffer_auto_out_b_ready), // @[Parameters.scala:56:69]
.auto_in_b_valid (_l2_auto_in_b_valid),
.auto_in_b_bits_param (_l2_auto_in_b_bits_param),
.auto_in_b_bits_address (_l2_auto_in_b_bits_address),
.auto_in_c_ready (_l2_auto_in_c_ready),
.auto_in_c_valid (_InclusiveCache_inner_TLBuffer_auto_out_c_valid), // @[Parameters.scala:56:69]
.auto_in_c_bits_opcode (_InclusiveCache_inner_TLBuffer_auto_out_c_bits_opcode), // @[Parameters.scala:56:69]
.auto_in_c_bits_param (_InclusiveCache_inner_TLBuffer_auto_out_c_bits_param), // @[Parameters.scala:56:69]
.auto_in_c_bits_size (_InclusiveCache_inner_TLBuffer_auto_out_c_bits_size), // @[Parameters.scala:56:69]
.auto_in_c_bits_source (_InclusiveCache_inner_TLBuffer_auto_out_c_bits_source), // @[Parameters.scala:56:69]
.auto_in_c_bits_address (_InclusiveCache_inner_TLBuffer_auto_out_c_bits_address), // @[Parameters.scala:56:69]
.auto_in_c_bits_data (_InclusiveCache_inner_TLBuffer_auto_out_c_bits_data), // @[Parameters.scala:56:69]
.auto_in_c_bits_corrupt (_InclusiveCache_inner_TLBuffer_auto_out_c_bits_corrupt), // @[Parameters.scala:56:69]
.auto_in_d_ready (_InclusiveCache_inner_TLBuffer_auto_out_d_ready), // @[Parameters.scala:56:69]
.auto_in_d_valid (_l2_auto_in_d_valid),
.auto_in_d_bits_opcode (_l2_auto_in_d_bits_opcode),
.auto_in_d_bits_param (_l2_auto_in_d_bits_param),
.auto_in_d_bits_size (_l2_auto_in_d_bits_size),
.auto_in_d_bits_source (_l2_auto_in_d_bits_source),
.auto_in_d_bits_sink (_l2_auto_in_d_bits_sink),
.auto_in_d_bits_denied (_l2_auto_in_d_bits_denied),
.auto_in_d_bits_data (_l2_auto_in_d_bits_data),
.auto_in_d_bits_corrupt (_l2_auto_in_d_bits_corrupt),
.auto_in_e_valid (_InclusiveCache_inner_TLBuffer_auto_out_e_valid), // @[Parameters.scala:56:69]
.auto_in_e_bits_sink (_InclusiveCache_inner_TLBuffer_auto_out_e_bits_sink), // @[Parameters.scala:56:69]
.auto_out_a_ready (InclusiveCache_outer_TLBuffer_auto_in_a_ready), // @[Buffer.scala:40:9]
.auto_out_a_valid (InclusiveCache_outer_TLBuffer_auto_in_a_valid),
.auto_out_a_bits_opcode (InclusiveCache_outer_TLBuffer_auto_in_a_bits_opcode),
.auto_out_a_bits_param (InclusiveCache_outer_TLBuffer_auto_in_a_bits_param),
.auto_out_a_bits_size (InclusiveCache_outer_TLBuffer_auto_in_a_bits_size),
.auto_out_a_bits_source (InclusiveCache_outer_TLBuffer_auto_in_a_bits_source),
.auto_out_a_bits_address (InclusiveCache_outer_TLBuffer_auto_in_a_bits_address),
.auto_out_a_bits_mask (InclusiveCache_outer_TLBuffer_auto_in_a_bits_mask),
.auto_out_a_bits_data (InclusiveCache_outer_TLBuffer_auto_in_a_bits_data),
.auto_out_a_bits_corrupt (InclusiveCache_outer_TLBuffer_auto_in_a_bits_corrupt),
.auto_out_c_ready (InclusiveCache_outer_TLBuffer_auto_in_c_ready), // @[Buffer.scala:40:9]
.auto_out_c_valid (InclusiveCache_outer_TLBuffer_auto_in_c_valid),
.auto_out_c_bits_opcode (InclusiveCache_outer_TLBuffer_auto_in_c_bits_opcode),
.auto_out_c_bits_param (InclusiveCache_outer_TLBuffer_auto_in_c_bits_param),
.auto_out_c_bits_size (InclusiveCache_outer_TLBuffer_auto_in_c_bits_size),
.auto_out_c_bits_source (InclusiveCache_outer_TLBuffer_auto_in_c_bits_source),
.auto_out_c_bits_address (InclusiveCache_outer_TLBuffer_auto_in_c_bits_address),
.auto_out_c_bits_data (InclusiveCache_outer_TLBuffer_auto_in_c_bits_data),
.auto_out_c_bits_corrupt (InclusiveCache_outer_TLBuffer_auto_in_c_bits_corrupt),
.auto_out_d_ready (InclusiveCache_outer_TLBuffer_auto_in_d_ready),
.auto_out_d_valid (InclusiveCache_outer_TLBuffer_auto_in_d_valid), // @[Buffer.scala:40:9]
.auto_out_d_bits_opcode (InclusiveCache_outer_TLBuffer_auto_in_d_bits_opcode), // @[Buffer.scala:40:9]
.auto_out_d_bits_param (InclusiveCache_outer_TLBuffer_auto_in_d_bits_param), // @[Buffer.scala:40:9]
.auto_out_d_bits_size (InclusiveCache_outer_TLBuffer_auto_in_d_bits_size), // @[Buffer.scala:40:9]
.auto_out_d_bits_source (InclusiveCache_outer_TLBuffer_auto_in_d_bits_source), // @[Buffer.scala:40:9]
.auto_out_d_bits_sink (InclusiveCache_outer_TLBuffer_auto_in_d_bits_sink), // @[Buffer.scala:40:9]
.auto_out_d_bits_denied (InclusiveCache_outer_TLBuffer_auto_in_d_bits_denied), // @[Buffer.scala:40:9]
.auto_out_d_bits_data (InclusiveCache_outer_TLBuffer_auto_in_d_bits_data), // @[Buffer.scala:40:9]
.auto_out_d_bits_corrupt (InclusiveCache_outer_TLBuffer_auto_in_d_bits_corrupt), // @[Buffer.scala:40:9]
.auto_out_e_valid (InclusiveCache_outer_TLBuffer_auto_in_e_valid),
.auto_out_e_bits_sink (InclusiveCache_outer_TLBuffer_auto_in_e_bits_sink)
); // @[Configs.scala:93:24]
TLBuffer_a32d256s8k5z3c InclusiveCache_inner_TLBuffer ( // @[Parameters.scala:56:69]
.clock (childClock), // @[LazyModuleImp.scala:155:31]
.reset (childReset), // @[LazyModuleImp.scala:158:31]
.auto_in_a_ready (filter_auto_anon_out_a_ready),
.auto_in_a_valid (filter_auto_anon_out_a_valid), // @[Filter.scala:60:9]
.auto_in_a_bits_opcode (filter_auto_anon_out_a_bits_opcode), // @[Filter.scala:60:9]
.auto_in_a_bits_param (filter_auto_anon_out_a_bits_param), // @[Filter.scala:60:9]
.auto_in_a_bits_size (filter_auto_anon_out_a_bits_size), // @[Filter.scala:60:9]
.auto_in_a_bits_source (filter_auto_anon_out_a_bits_source), // @[Filter.scala:60:9]
.auto_in_a_bits_address (filter_auto_anon_out_a_bits_address), // @[Filter.scala:60:9]
.auto_in_a_bits_mask (filter_auto_anon_out_a_bits_mask), // @[Filter.scala:60:9]
.auto_in_a_bits_data (filter_auto_anon_out_a_bits_data), // @[Filter.scala:60:9]
.auto_in_a_bits_corrupt (filter_auto_anon_out_a_bits_corrupt), // @[Filter.scala:60:9]
.auto_in_b_ready (filter_auto_anon_out_b_ready), // @[Filter.scala:60:9]
.auto_in_b_valid (filter_auto_anon_out_b_valid),
.auto_in_b_bits_param (filter_auto_anon_out_b_bits_param),
.auto_in_b_bits_address (filter_auto_anon_out_b_bits_address),
.auto_in_c_ready (filter_auto_anon_out_c_ready),
.auto_in_c_valid (filter_auto_anon_out_c_valid), // @[Filter.scala:60:9]
.auto_in_c_bits_opcode (filter_auto_anon_out_c_bits_opcode), // @[Filter.scala:60:9]
.auto_in_c_bits_param (filter_auto_anon_out_c_bits_param), // @[Filter.scala:60:9]
.auto_in_c_bits_size (filter_auto_anon_out_c_bits_size), // @[Filter.scala:60:9]
.auto_in_c_bits_source (filter_auto_anon_out_c_bits_source), // @[Filter.scala:60:9]
.auto_in_c_bits_address (filter_auto_anon_out_c_bits_address), // @[Filter.scala:60:9]
.auto_in_c_bits_data (filter_auto_anon_out_c_bits_data), // @[Filter.scala:60:9]
.auto_in_c_bits_corrupt (filter_auto_anon_out_c_bits_corrupt), // @[Filter.scala:60:9]
.auto_in_d_ready (filter_auto_anon_out_d_ready), // @[Filter.scala:60:9]
.auto_in_d_valid (filter_auto_anon_out_d_valid),
.auto_in_d_bits_opcode (filter_auto_anon_out_d_bits_opcode),
.auto_in_d_bits_param (filter_auto_anon_out_d_bits_param),
.auto_in_d_bits_size (filter_auto_anon_out_d_bits_size),
.auto_in_d_bits_source (filter_auto_anon_out_d_bits_source),
.auto_in_d_bits_sink (filter_auto_anon_out_d_bits_sink),
.auto_in_d_bits_denied (filter_auto_anon_out_d_bits_denied),
.auto_in_d_bits_data (filter_auto_anon_out_d_bits_data),
.auto_in_d_bits_corrupt (filter_auto_anon_out_d_bits_corrupt),
.auto_in_e_valid (filter_auto_anon_out_e_valid), // @[Filter.scala:60:9]
.auto_in_e_bits_sink (filter_auto_anon_out_e_bits_sink), // @[Filter.scala:60:9]
.auto_out_a_ready (_l2_auto_in_a_ready), // @[Configs.scala:93:24]
.auto_out_a_valid (_InclusiveCache_inner_TLBuffer_auto_out_a_valid),
.auto_out_a_bits_opcode (_InclusiveCache_inner_TLBuffer_auto_out_a_bits_opcode),
.auto_out_a_bits_param (_InclusiveCache_inner_TLBuffer_auto_out_a_bits_param),
.auto_out_a_bits_size (_InclusiveCache_inner_TLBuffer_auto_out_a_bits_size),
.auto_out_a_bits_source (_InclusiveCache_inner_TLBuffer_auto_out_a_bits_source),
.auto_out_a_bits_address (_InclusiveCache_inner_TLBuffer_auto_out_a_bits_address),
.auto_out_a_bits_mask (_InclusiveCache_inner_TLBuffer_auto_out_a_bits_mask),
.auto_out_a_bits_data (_InclusiveCache_inner_TLBuffer_auto_out_a_bits_data),
.auto_out_a_bits_corrupt (_InclusiveCache_inner_TLBuffer_auto_out_a_bits_corrupt),
.auto_out_b_ready (_InclusiveCache_inner_TLBuffer_auto_out_b_ready),
.auto_out_b_valid (_l2_auto_in_b_valid), // @[Configs.scala:93:24]
.auto_out_b_bits_param (_l2_auto_in_b_bits_param), // @[Configs.scala:93:24]
.auto_out_b_bits_address (_l2_auto_in_b_bits_address), // @[Configs.scala:93:24]
.auto_out_c_ready (_l2_auto_in_c_ready), // @[Configs.scala:93:24]
.auto_out_c_valid (_InclusiveCache_inner_TLBuffer_auto_out_c_valid),
.auto_out_c_bits_opcode (_InclusiveCache_inner_TLBuffer_auto_out_c_bits_opcode),
.auto_out_c_bits_param (_InclusiveCache_inner_TLBuffer_auto_out_c_bits_param),
.auto_out_c_bits_size (_InclusiveCache_inner_TLBuffer_auto_out_c_bits_size),
.auto_out_c_bits_source (_InclusiveCache_inner_TLBuffer_auto_out_c_bits_source),
.auto_out_c_bits_address (_InclusiveCache_inner_TLBuffer_auto_out_c_bits_address),
.auto_out_c_bits_data (_InclusiveCache_inner_TLBuffer_auto_out_c_bits_data),
.auto_out_c_bits_corrupt (_InclusiveCache_inner_TLBuffer_auto_out_c_bits_corrupt),
.auto_out_d_ready (_InclusiveCache_inner_TLBuffer_auto_out_d_ready),
.auto_out_d_valid (_l2_auto_in_d_valid), // @[Configs.scala:93:24]
.auto_out_d_bits_opcode (_l2_auto_in_d_bits_opcode), // @[Configs.scala:93:24]
.auto_out_d_bits_param (_l2_auto_in_d_bits_param), // @[Configs.scala:93:24]
.auto_out_d_bits_size (_l2_auto_in_d_bits_size), // @[Configs.scala:93:24]
.auto_out_d_bits_source (_l2_auto_in_d_bits_source), // @[Configs.scala:93:24]
.auto_out_d_bits_sink (_l2_auto_in_d_bits_sink), // @[Configs.scala:93:24]
.auto_out_d_bits_denied (_l2_auto_in_d_bits_denied), // @[Configs.scala:93:24]
.auto_out_d_bits_data (_l2_auto_in_d_bits_data), // @[Configs.scala:93:24]
.auto_out_d_bits_corrupt (_l2_auto_in_d_bits_corrupt), // @[Configs.scala:93:24]
.auto_out_e_valid (_InclusiveCache_inner_TLBuffer_auto_out_e_valid),
.auto_out_e_bits_sink (_InclusiveCache_inner_TLBuffer_auto_out_e_bits_sink)
); // @[Parameters.scala:56:69]
TLCacheCork cork ( // @[Configs.scala:120:26]
.clock (childClock), // @[LazyModuleImp.scala:155:31]
.reset (childReset), // @[LazyModuleImp.scala:158:31]
.auto_in_a_ready (InclusiveCache_outer_TLBuffer_auto_out_a_ready),
.auto_in_a_valid (InclusiveCache_outer_TLBuffer_auto_out_a_valid), // @[Buffer.scala:40:9]
.auto_in_a_bits_opcode (InclusiveCache_outer_TLBuffer_auto_out_a_bits_opcode), // @[Buffer.scala:40:9]
.auto_in_a_bits_param (InclusiveCache_outer_TLBuffer_auto_out_a_bits_param), // @[Buffer.scala:40:9]
.auto_in_a_bits_size (InclusiveCache_outer_TLBuffer_auto_out_a_bits_size), // @[Buffer.scala:40:9]
.auto_in_a_bits_source (InclusiveCache_outer_TLBuffer_auto_out_a_bits_source), // @[Buffer.scala:40:9]
.auto_in_a_bits_address (InclusiveCache_outer_TLBuffer_auto_out_a_bits_address), // @[Buffer.scala:40:9]
.auto_in_a_bits_mask (InclusiveCache_outer_TLBuffer_auto_out_a_bits_mask), // @[Buffer.scala:40:9]
.auto_in_a_bits_data (InclusiveCache_outer_TLBuffer_auto_out_a_bits_data), // @[Buffer.scala:40:9]
.auto_in_a_bits_corrupt (InclusiveCache_outer_TLBuffer_auto_out_a_bits_corrupt), // @[Buffer.scala:40:9]
.auto_in_c_ready (InclusiveCache_outer_TLBuffer_auto_out_c_ready),
.auto_in_c_valid (InclusiveCache_outer_TLBuffer_auto_out_c_valid), // @[Buffer.scala:40:9]
.auto_in_c_bits_opcode (InclusiveCache_outer_TLBuffer_auto_out_c_bits_opcode), // @[Buffer.scala:40:9]
.auto_in_c_bits_param (InclusiveCache_outer_TLBuffer_auto_out_c_bits_param), // @[Buffer.scala:40:9]
.auto_in_c_bits_size (InclusiveCache_outer_TLBuffer_auto_out_c_bits_size), // @[Buffer.scala:40:9]
.auto_in_c_bits_source (InclusiveCache_outer_TLBuffer_auto_out_c_bits_source), // @[Buffer.scala:40:9]
.auto_in_c_bits_address (InclusiveCache_outer_TLBuffer_auto_out_c_bits_address), // @[Buffer.scala:40:9]
.auto_in_c_bits_data (InclusiveCache_outer_TLBuffer_auto_out_c_bits_data), // @[Buffer.scala:40:9]
.auto_in_c_bits_corrupt (InclusiveCache_outer_TLBuffer_auto_out_c_bits_corrupt), // @[Buffer.scala:40:9]
.auto_in_d_ready (InclusiveCache_outer_TLBuffer_auto_out_d_ready), // @[Buffer.scala:40:9]
.auto_in_d_valid (InclusiveCache_outer_TLBuffer_auto_out_d_valid),
.auto_in_d_bits_opcode (InclusiveCache_outer_TLBuffer_auto_out_d_bits_opcode),
.auto_in_d_bits_param (InclusiveCache_outer_TLBuffer_auto_out_d_bits_param),
.auto_in_d_bits_size (InclusiveCache_outer_TLBuffer_auto_out_d_bits_size),
.auto_in_d_bits_source (InclusiveCache_outer_TLBuffer_auto_out_d_bits_source),
.auto_in_d_bits_sink (InclusiveCache_outer_TLBuffer_auto_out_d_bits_sink),
.auto_in_d_bits_denied (InclusiveCache_outer_TLBuffer_auto_out_d_bits_denied),
.auto_in_d_bits_data (InclusiveCache_outer_TLBuffer_auto_out_d_bits_data),
.auto_in_d_bits_corrupt (InclusiveCache_outer_TLBuffer_auto_out_d_bits_corrupt),
.auto_in_e_valid (InclusiveCache_outer_TLBuffer_auto_out_e_valid), // @[Buffer.scala:40:9]
.auto_in_e_bits_sink (InclusiveCache_outer_TLBuffer_auto_out_e_bits_sink), // @[Buffer.scala:40:9]
.auto_out_a_ready (_binder_auto_in_a_ready), // @[BankBinder.scala:71:28]
.auto_out_a_valid (_cork_auto_out_a_valid),
.auto_out_a_bits_opcode (_cork_auto_out_a_bits_opcode),
.auto_out_a_bits_param (_cork_auto_out_a_bits_param),
.auto_out_a_bits_size (_cork_auto_out_a_bits_size),
.auto_out_a_bits_source (_cork_auto_out_a_bits_source),
.auto_out_a_bits_address (_cork_auto_out_a_bits_address),
.auto_out_a_bits_mask (_cork_auto_out_a_bits_mask),
.auto_out_a_bits_data (_cork_auto_out_a_bits_data),
.auto_out_a_bits_corrupt (_cork_auto_out_a_bits_corrupt),
.auto_out_d_ready (_cork_auto_out_d_ready),
.auto_out_d_valid (_binder_auto_in_d_valid), // @[BankBinder.scala:71:28]
.auto_out_d_bits_opcode (_binder_auto_in_d_bits_opcode), // @[BankBinder.scala:71:28]
.auto_out_d_bits_param (_binder_auto_in_d_bits_param), // @[BankBinder.scala:71:28]
.auto_out_d_bits_size (_binder_auto_in_d_bits_size), // @[BankBinder.scala:71:28]
.auto_out_d_bits_source (_binder_auto_in_d_bits_source), // @[BankBinder.scala:71:28]
.auto_out_d_bits_sink (_binder_auto_in_d_bits_sink), // @[BankBinder.scala:71:28]
.auto_out_d_bits_denied (_binder_auto_in_d_bits_denied), // @[BankBinder.scala:71:28]
.auto_out_d_bits_data (_binder_auto_in_d_bits_data), // @[BankBinder.scala:71:28]
.auto_out_d_bits_corrupt (_binder_auto_in_d_bits_corrupt) // @[BankBinder.scala:71:28]
); // @[Configs.scala:120:26]
BankBinder binder ( // @[BankBinder.scala:71:28]
.clock (childClock), // @[LazyModuleImp.scala:155:31]
.reset (childReset), // @[LazyModuleImp.scala:158:31]
.auto_in_a_ready (_binder_auto_in_a_ready),
.auto_in_a_valid (_cork_auto_out_a_valid), // @[Configs.scala:120:26]
.auto_in_a_bits_opcode (_cork_auto_out_a_bits_opcode), // @[Configs.scala:120:26]
.auto_in_a_bits_param (_cork_auto_out_a_bits_param), // @[Configs.scala:120:26]
.auto_in_a_bits_size (_cork_auto_out_a_bits_size), // @[Configs.scala:120:26]
.auto_in_a_bits_source (_cork_auto_out_a_bits_source), // @[Configs.scala:120:26]
.auto_in_a_bits_address (_cork_auto_out_a_bits_address), // @[Configs.scala:120:26]
.auto_in_a_bits_mask (_cork_auto_out_a_bits_mask), // @[Configs.scala:120:26]
.auto_in_a_bits_data (_cork_auto_out_a_bits_data), // @[Configs.scala:120:26]
.auto_in_a_bits_corrupt (_cork_auto_out_a_bits_corrupt), // @[Configs.scala:120:26]
.auto_in_d_ready (_cork_auto_out_d_ready), // @[Configs.scala:120:26]
.auto_in_d_valid (_binder_auto_in_d_valid),
.auto_in_d_bits_opcode (_binder_auto_in_d_bits_opcode),
.auto_in_d_bits_param (_binder_auto_in_d_bits_param),
.auto_in_d_bits_size (_binder_auto_in_d_bits_size),
.auto_in_d_bits_source (_binder_auto_in_d_bits_source),
.auto_in_d_bits_sink (_binder_auto_in_d_bits_sink),
.auto_in_d_bits_denied (_binder_auto_in_d_bits_denied),
.auto_in_d_bits_data (_binder_auto_in_d_bits_data),
.auto_in_d_bits_corrupt (_binder_auto_in_d_bits_corrupt),
.auto_out_a_ready (coupler_to_bus_named_mbus_auto_widget_anon_in_a_ready), // @[LazyModuleImp.scala:138:7]
.auto_out_a_valid (coupler_to_bus_named_mbus_auto_widget_anon_in_a_valid),
.auto_out_a_bits_opcode (coupler_to_bus_named_mbus_auto_widget_anon_in_a_bits_opcode),
.auto_out_a_bits_param (coupler_to_bus_named_mbus_auto_widget_anon_in_a_bits_param),
.auto_out_a_bits_size (coupler_to_bus_named_mbus_auto_widget_anon_in_a_bits_size),
.auto_out_a_bits_source (coupler_to_bus_named_mbus_auto_widget_anon_in_a_bits_source),
.auto_out_a_bits_address (coupler_to_bus_named_mbus_auto_widget_anon_in_a_bits_address),
.auto_out_a_bits_mask (coupler_to_bus_named_mbus_auto_widget_anon_in_a_bits_mask),
.auto_out_a_bits_data (coupler_to_bus_named_mbus_auto_widget_anon_in_a_bits_data),
.auto_out_a_bits_corrupt (coupler_to_bus_named_mbus_auto_widget_anon_in_a_bits_corrupt),
.auto_out_d_ready (coupler_to_bus_named_mbus_auto_widget_anon_in_d_ready),
.auto_out_d_valid (coupler_to_bus_named_mbus_auto_widget_anon_in_d_valid), // @[LazyModuleImp.scala:138:7]
.auto_out_d_bits_opcode (coupler_to_bus_named_mbus_auto_widget_anon_in_d_bits_opcode), // @[LazyModuleImp.scala:138:7]
.auto_out_d_bits_param (coupler_to_bus_named_mbus_auto_widget_anon_in_d_bits_param), // @[LazyModuleImp.scala:138:7]
.auto_out_d_bits_size (coupler_to_bus_named_mbus_auto_widget_anon_in_d_bits_size), // @[LazyModuleImp.scala:138:7]
.auto_out_d_bits_source (coupler_to_bus_named_mbus_auto_widget_anon_in_d_bits_source), // @[LazyModuleImp.scala:138:7]
.auto_out_d_bits_sink (coupler_to_bus_named_mbus_auto_widget_anon_in_d_bits_sink), // @[LazyModuleImp.scala:138:7]
.auto_out_d_bits_denied (coupler_to_bus_named_mbus_auto_widget_anon_in_d_bits_denied), // @[LazyModuleImp.scala:138:7]
.auto_out_d_bits_data (coupler_to_bus_named_mbus_auto_widget_anon_in_d_bits_data), // @[LazyModuleImp.scala:138:7]
.auto_out_d_bits_corrupt (coupler_to_bus_named_mbus_auto_widget_anon_in_d_bits_corrupt) // @[LazyModuleImp.scala:138:7]
); // @[BankBinder.scala:71:28]
assign auto_coupler_to_bus_named_mbus_bus_xing_out_a_valid = auto_coupler_to_bus_named_mbus_bus_xing_out_a_valid_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_opcode = auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_opcode_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_param = auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_param_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_size = auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_size_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_source = auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_source_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_address = auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_address_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_mask = auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_mask_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_data = auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_data_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_corrupt = auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_corrupt_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_bus_named_mbus_bus_xing_out_d_ready = auto_coupler_to_bus_named_mbus_bus_xing_out_d_ready_0; // @[ClockDomain.scala:14:9]
assign auto_coherent_jbar_anon_in_a_ready = auto_coherent_jbar_anon_in_a_ready_0; // @[ClockDomain.scala:14:9]
assign auto_coherent_jbar_anon_in_b_valid = auto_coherent_jbar_anon_in_b_valid_0; // @[ClockDomain.scala:14:9]
assign auto_coherent_jbar_anon_in_b_bits_param = auto_coherent_jbar_anon_in_b_bits_param_0; // @[ClockDomain.scala:14:9]
assign auto_coherent_jbar_anon_in_b_bits_address = auto_coherent_jbar_anon_in_b_bits_address_0; // @[ClockDomain.scala:14:9]
assign auto_coherent_jbar_anon_in_c_ready = auto_coherent_jbar_anon_in_c_ready_0; // @[ClockDomain.scala:14:9]
assign auto_coherent_jbar_anon_in_d_valid = auto_coherent_jbar_anon_in_d_valid_0; // @[ClockDomain.scala:14:9]
assign auto_coherent_jbar_anon_in_d_bits_opcode = auto_coherent_jbar_anon_in_d_bits_opcode_0; // @[ClockDomain.scala:14:9]
assign auto_coherent_jbar_anon_in_d_bits_param = auto_coherent_jbar_anon_in_d_bits_param_0; // @[ClockDomain.scala:14:9]
assign auto_coherent_jbar_anon_in_d_bits_size = auto_coherent_jbar_anon_in_d_bits_size_0; // @[ClockDomain.scala:14:9]
assign auto_coherent_jbar_anon_in_d_bits_source = auto_coherent_jbar_anon_in_d_bits_source_0; // @[ClockDomain.scala:14:9]
assign auto_coherent_jbar_anon_in_d_bits_sink = auto_coherent_jbar_anon_in_d_bits_sink_0; // @[ClockDomain.scala:14:9]
assign auto_coherent_jbar_anon_in_d_bits_denied = auto_coherent_jbar_anon_in_d_bits_denied_0; // @[ClockDomain.scala:14:9]
assign auto_coherent_jbar_anon_in_d_bits_data = auto_coherent_jbar_anon_in_d_bits_data_0; // @[ClockDomain.scala:14:9]
assign auto_coherent_jbar_anon_in_d_bits_corrupt = auto_coherent_jbar_anon_in_d_bits_corrupt_0; // @[ClockDomain.scala:14:9]
assign auto_l2_ctrls_ctrl_in_a_ready = auto_l2_ctrls_ctrl_in_a_ready_0; // @[ClockDomain.scala:14:9]
assign auto_l2_ctrls_ctrl_in_d_valid = auto_l2_ctrls_ctrl_in_d_valid_0; // @[ClockDomain.scala:14:9]
assign auto_l2_ctrls_ctrl_in_d_bits_opcode = auto_l2_ctrls_ctrl_in_d_bits_opcode_0; // @[ClockDomain.scala:14:9]
assign auto_l2_ctrls_ctrl_in_d_bits_size = auto_l2_ctrls_ctrl_in_d_bits_size_0; // @[ClockDomain.scala:14:9]
assign auto_l2_ctrls_ctrl_in_d_bits_source = auto_l2_ctrls_ctrl_in_d_bits_source_0; // @[ClockDomain.scala:14:9]
assign auto_l2_ctrls_ctrl_in_d_bits_data = auto_l2_ctrls_ctrl_in_d_bits_data_0; // @[ClockDomain.scala:14:9]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File primitives.scala:
/*============================================================================
This Chisel source file is part of a pre-release version of the HardFloat IEEE
Floating-Point Arithmetic Package, by John R. Hauser (with some contributions
from Yunsup Lee and Andrew Waterman, mainly concerning testing).
Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
University of California. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
package hardfloat
import chisel3._
import chisel3.util._
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
object lowMask
{
def apply(in: UInt, topBound: BigInt, bottomBound: BigInt): UInt =
{
require(topBound != bottomBound)
val numInVals = BigInt(1)<<in.getWidth
if (topBound < bottomBound) {
lowMask(~in, numInVals - 1 - topBound, numInVals - 1 - bottomBound)
} else if (numInVals > 64 /* Empirical */) {
// For simulation performance, we should avoid generating
// exteremely wide shifters, so we divide and conquer.
// Empirically, this does not impact synthesis QoR.
val mid = numInVals / 2
val msb = in(in.getWidth - 1)
val lsbs = in(in.getWidth - 2, 0)
if (mid < topBound) {
if (mid <= bottomBound) {
Mux(msb,
lowMask(lsbs, topBound - mid, bottomBound - mid),
0.U
)
} else {
Mux(msb,
lowMask(lsbs, topBound - mid, 0) ## ((BigInt(1)<<(mid - bottomBound).toInt) - 1).U,
lowMask(lsbs, mid, bottomBound)
)
}
} else {
~Mux(msb, 0.U, ~lowMask(lsbs, topBound, bottomBound))
}
} else {
val shift = (BigInt(-1)<<numInVals.toInt).S>>in
Reverse(
shift(
(numInVals - 1 - bottomBound).toInt,
(numInVals - topBound).toInt
)
)
}
}
}
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
object countLeadingZeros
{
def apply(in: UInt): UInt = PriorityEncoder(in.asBools.reverse)
}
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
object orReduceBy2
{
def apply(in: UInt): UInt =
{
val reducedWidth = (in.getWidth + 1)>>1
val reducedVec = Wire(Vec(reducedWidth, Bool()))
for (ix <- 0 until reducedWidth - 1) {
reducedVec(ix) := in(ix * 2 + 1, ix * 2).orR
}
reducedVec(reducedWidth - 1) :=
in(in.getWidth - 1, (reducedWidth - 1) * 2).orR
reducedVec.asUInt
}
}
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
object orReduceBy4
{
def apply(in: UInt): UInt =
{
val reducedWidth = (in.getWidth + 3)>>2
val reducedVec = Wire(Vec(reducedWidth, Bool()))
for (ix <- 0 until reducedWidth - 1) {
reducedVec(ix) := in(ix * 4 + 3, ix * 4).orR
}
reducedVec(reducedWidth - 1) :=
in(in.getWidth - 1, (reducedWidth - 1) * 4).orR
reducedVec.asUInt
}
}
File RoundAnyRawFNToRecFN.scala:
/*============================================================================
This Chisel source file is part of a pre-release version of the HardFloat IEEE
Floating-Point Arithmetic Package, by John R. Hauser (with some contributions
from Yunsup Lee and Andrew Waterman, mainly concerning testing).
Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
University of California. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
package hardfloat
import chisel3._
import chisel3.util.Fill
import consts._
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
class
RoundAnyRawFNToRecFN(
inExpWidth: Int,
inSigWidth: Int,
outExpWidth: Int,
outSigWidth: Int,
options: Int
)
extends RawModule
{
override def desiredName = s"RoundAnyRawFNToRecFN_ie${inExpWidth}_is${inSigWidth}_oe${outExpWidth}_os${outSigWidth}"
val io = IO(new Bundle {
val invalidExc = Input(Bool()) // overrides 'infiniteExc' and 'in'
val infiniteExc = Input(Bool()) // overrides 'in' except for 'in.sign'
val in = Input(new RawFloat(inExpWidth, inSigWidth))
// (allowed exponent range has limits)
val roundingMode = Input(UInt(3.W))
val detectTininess = Input(UInt(1.W))
val out = Output(Bits((outExpWidth + outSigWidth + 1).W))
val exceptionFlags = Output(Bits(5.W))
})
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val sigMSBitAlwaysZero = ((options & flRoundOpt_sigMSBitAlwaysZero) != 0)
val effectiveInSigWidth =
if (sigMSBitAlwaysZero) inSigWidth else inSigWidth + 1
val neverUnderflows =
((options &
(flRoundOpt_neverUnderflows | flRoundOpt_subnormsAlwaysExact)
) != 0) ||
(inExpWidth < outExpWidth)
val neverOverflows =
((options & flRoundOpt_neverOverflows) != 0) ||
(inExpWidth < outExpWidth)
val outNaNExp = BigInt(7)<<(outExpWidth - 2)
val outInfExp = BigInt(6)<<(outExpWidth - 2)
val outMaxFiniteExp = outInfExp - 1
val outMinNormExp = (BigInt(1)<<(outExpWidth - 1)) + 2
val outMinNonzeroExp = outMinNormExp - outSigWidth + 1
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val roundingMode_near_even = (io.roundingMode === round_near_even)
val roundingMode_minMag = (io.roundingMode === round_minMag)
val roundingMode_min = (io.roundingMode === round_min)
val roundingMode_max = (io.roundingMode === round_max)
val roundingMode_near_maxMag = (io.roundingMode === round_near_maxMag)
val roundingMode_odd = (io.roundingMode === round_odd)
val roundMagUp =
(roundingMode_min && io.in.sign) || (roundingMode_max && ! io.in.sign)
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val sAdjustedExp =
if (inExpWidth < outExpWidth)
(io.in.sExp +&
((BigInt(1)<<outExpWidth) - (BigInt(1)<<inExpWidth)).S
)(outExpWidth, 0).zext
else if (inExpWidth == outExpWidth)
io.in.sExp
else
io.in.sExp +&
((BigInt(1)<<outExpWidth) - (BigInt(1)<<inExpWidth)).S
val adjustedSig =
if (inSigWidth <= outSigWidth + 2)
io.in.sig<<(outSigWidth - inSigWidth + 2)
else
(io.in.sig(inSigWidth, inSigWidth - outSigWidth - 1) ##
io.in.sig(inSigWidth - outSigWidth - 2, 0).orR
)
val doShiftSigDown1 =
if (sigMSBitAlwaysZero) false.B else adjustedSig(outSigWidth + 2)
val common_expOut = Wire(UInt((outExpWidth + 1).W))
val common_fractOut = Wire(UInt((outSigWidth - 1).W))
val common_overflow = Wire(Bool())
val common_totalUnderflow = Wire(Bool())
val common_underflow = Wire(Bool())
val common_inexact = Wire(Bool())
if (
neverOverflows && neverUnderflows
&& (effectiveInSigWidth <= outSigWidth)
) {
//--------------------------------------------------------------------
//--------------------------------------------------------------------
common_expOut := sAdjustedExp(outExpWidth, 0) + doShiftSigDown1
common_fractOut :=
Mux(doShiftSigDown1,
adjustedSig(outSigWidth + 1, 3),
adjustedSig(outSigWidth, 2)
)
common_overflow := false.B
common_totalUnderflow := false.B
common_underflow := false.B
common_inexact := false.B
} else {
//--------------------------------------------------------------------
//--------------------------------------------------------------------
val roundMask =
if (neverUnderflows)
0.U(outSigWidth.W) ## doShiftSigDown1 ## 3.U(2.W)
else
(lowMask(
sAdjustedExp(outExpWidth, 0),
outMinNormExp - outSigWidth - 1,
outMinNormExp
) | doShiftSigDown1) ##
3.U(2.W)
val shiftedRoundMask = 0.U(1.W) ## roundMask>>1
val roundPosMask = ~shiftedRoundMask & roundMask
val roundPosBit = (adjustedSig & roundPosMask).orR
val anyRoundExtra = (adjustedSig & shiftedRoundMask).orR
val anyRound = roundPosBit || anyRoundExtra
val roundIncr =
((roundingMode_near_even || roundingMode_near_maxMag) &&
roundPosBit) ||
(roundMagUp && anyRound)
val roundedSig: Bits =
Mux(roundIncr,
(((adjustedSig | roundMask)>>2) +& 1.U) &
~Mux(roundingMode_near_even && roundPosBit &&
! anyRoundExtra,
roundMask>>1,
0.U((outSigWidth + 2).W)
),
(adjustedSig & ~roundMask)>>2 |
Mux(roundingMode_odd && anyRound, roundPosMask>>1, 0.U)
)
//*** IF SIG WIDTH IS VERY NARROW, NEED TO ACCOUNT FOR ROUND-EVEN ZEROING
//*** M.S. BIT OF SUBNORMAL SIG?
val sRoundedExp = sAdjustedExp +& (roundedSig>>outSigWidth).asUInt.zext
common_expOut := sRoundedExp(outExpWidth, 0)
common_fractOut :=
Mux(doShiftSigDown1,
roundedSig(outSigWidth - 1, 1),
roundedSig(outSigWidth - 2, 0)
)
common_overflow :=
(if (neverOverflows) false.B else
//*** REWRITE BASED ON BEFORE-ROUNDING EXPONENT?:
(sRoundedExp>>(outExpWidth - 1) >= 3.S))
common_totalUnderflow :=
(if (neverUnderflows) false.B else
//*** WOULD BE GOOD ENOUGH TO USE EXPONENT BEFORE ROUNDING?:
(sRoundedExp < outMinNonzeroExp.S))
val unboundedRange_roundPosBit =
Mux(doShiftSigDown1, adjustedSig(2), adjustedSig(1))
val unboundedRange_anyRound =
(doShiftSigDown1 && adjustedSig(2)) || adjustedSig(1, 0).orR
val unboundedRange_roundIncr =
((roundingMode_near_even || roundingMode_near_maxMag) &&
unboundedRange_roundPosBit) ||
(roundMagUp && unboundedRange_anyRound)
val roundCarry =
Mux(doShiftSigDown1,
roundedSig(outSigWidth + 1),
roundedSig(outSigWidth)
)
common_underflow :=
(if (neverUnderflows) false.B else
common_totalUnderflow ||
//*** IF SIG WIDTH IS VERY NARROW, NEED TO ACCOUNT FOR ROUND-EVEN ZEROING
//*** M.S. BIT OF SUBNORMAL SIG?
(anyRound && ((sAdjustedExp>>outExpWidth) <= 0.S) &&
Mux(doShiftSigDown1, roundMask(3), roundMask(2)) &&
! ((io.detectTininess === tininess_afterRounding) &&
! Mux(doShiftSigDown1,
roundMask(4),
roundMask(3)
) &&
roundCarry && roundPosBit &&
unboundedRange_roundIncr)))
common_inexact := common_totalUnderflow || anyRound
}
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val isNaNOut = io.invalidExc || io.in.isNaN
val notNaN_isSpecialInfOut = io.infiniteExc || io.in.isInf
val commonCase = ! isNaNOut && ! notNaN_isSpecialInfOut && ! io.in.isZero
val overflow = commonCase && common_overflow
val underflow = commonCase && common_underflow
val inexact = overflow || (commonCase && common_inexact)
val overflow_roundMagUp =
roundingMode_near_even || roundingMode_near_maxMag || roundMagUp
val pegMinNonzeroMagOut =
commonCase && common_totalUnderflow && (roundMagUp || roundingMode_odd)
val pegMaxFiniteMagOut = overflow && ! overflow_roundMagUp
val notNaN_isInfOut =
notNaN_isSpecialInfOut || (overflow && overflow_roundMagUp)
val signOut = Mux(isNaNOut, false.B, io.in.sign)
val expOut =
(common_expOut &
~Mux(io.in.isZero || common_totalUnderflow,
(BigInt(7)<<(outExpWidth - 2)).U((outExpWidth + 1).W),
0.U
) &
~Mux(pegMinNonzeroMagOut,
~outMinNonzeroExp.U((outExpWidth + 1).W),
0.U
) &
~Mux(pegMaxFiniteMagOut,
(BigInt(1)<<(outExpWidth - 1)).U((outExpWidth + 1).W),
0.U
) &
~Mux(notNaN_isInfOut,
(BigInt(1)<<(outExpWidth - 2)).U((outExpWidth + 1).W),
0.U
)) |
Mux(pegMinNonzeroMagOut,
outMinNonzeroExp.U((outExpWidth + 1).W),
0.U
) |
Mux(pegMaxFiniteMagOut,
outMaxFiniteExp.U((outExpWidth + 1).W),
0.U
) |
Mux(notNaN_isInfOut, outInfExp.U((outExpWidth + 1).W), 0.U) |
Mux(isNaNOut, outNaNExp.U((outExpWidth + 1).W), 0.U)
val fractOut =
Mux(isNaNOut || io.in.isZero || common_totalUnderflow,
Mux(isNaNOut, (BigInt(1)<<(outSigWidth - 2)).U, 0.U),
common_fractOut
) |
Fill(outSigWidth - 1, pegMaxFiniteMagOut)
io.out := signOut ## expOut ## fractOut
io.exceptionFlags :=
io.invalidExc ## io.infiniteExc ## overflow ## underflow ## inexact
}
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
class
RoundRawFNToRecFN(expWidth: Int, sigWidth: Int, options: Int)
extends RawModule
{
override def desiredName = s"RoundRawFNToRecFN_e${expWidth}_s${sigWidth}"
val io = IO(new Bundle {
val invalidExc = Input(Bool()) // overrides 'infiniteExc' and 'in'
val infiniteExc = Input(Bool()) // overrides 'in' except for 'in.sign'
val in = Input(new RawFloat(expWidth, sigWidth + 2))
val roundingMode = Input(UInt(3.W))
val detectTininess = Input(UInt(1.W))
val out = Output(Bits((expWidth + sigWidth + 1).W))
val exceptionFlags = Output(Bits(5.W))
})
val roundAnyRawFNToRecFN =
Module(
new RoundAnyRawFNToRecFN(
expWidth, sigWidth + 2, expWidth, sigWidth, options))
roundAnyRawFNToRecFN.io.invalidExc := io.invalidExc
roundAnyRawFNToRecFN.io.infiniteExc := io.infiniteExc
roundAnyRawFNToRecFN.io.in := io.in
roundAnyRawFNToRecFN.io.roundingMode := io.roundingMode
roundAnyRawFNToRecFN.io.detectTininess := io.detectTininess
io.out := roundAnyRawFNToRecFN.io.out
io.exceptionFlags := roundAnyRawFNToRecFN.io.exceptionFlags
}
| module RoundAnyRawFNToRecFN_ie11_is55_oe11_os53_9( // @[RoundAnyRawFNToRecFN.scala:48:5]
input io_invalidExc, // @[RoundAnyRawFNToRecFN.scala:58:16]
input io_infiniteExc, // @[RoundAnyRawFNToRecFN.scala:58:16]
input io_in_isNaN, // @[RoundAnyRawFNToRecFN.scala:58:16]
input io_in_isInf, // @[RoundAnyRawFNToRecFN.scala:58:16]
input io_in_isZero, // @[RoundAnyRawFNToRecFN.scala:58:16]
input io_in_sign, // @[RoundAnyRawFNToRecFN.scala:58:16]
input [12:0] io_in_sExp, // @[RoundAnyRawFNToRecFN.scala:58:16]
input [55:0] io_in_sig, // @[RoundAnyRawFNToRecFN.scala:58:16]
input [2:0] io_roundingMode, // @[RoundAnyRawFNToRecFN.scala:58:16]
output [64:0] io_out, // @[RoundAnyRawFNToRecFN.scala:58:16]
output [4:0] io_exceptionFlags // @[RoundAnyRawFNToRecFN.scala:58:16]
);
wire io_invalidExc_0 = io_invalidExc; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire io_infiniteExc_0 = io_infiniteExc; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire io_in_isNaN_0 = io_in_isNaN; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire io_in_isInf_0 = io_in_isInf; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire io_in_isZero_0 = io_in_isZero; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire io_in_sign_0 = io_in_sign; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire [12:0] io_in_sExp_0 = io_in_sExp; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire [55:0] io_in_sig_0 = io_in_sig; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire [2:0] io_roundingMode_0 = io_roundingMode; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire [31:0] _roundMask_T_5 = 32'hFFFF; // @[primitives.scala:77:20]
wire [31:0] _roundMask_T_4 = 32'hFFFF0000; // @[primitives.scala:77:20]
wire [31:0] _roundMask_T_10 = 32'hFFFF0000; // @[primitives.scala:77:20]
wire [23:0] _roundMask_T_13 = 24'hFFFF; // @[primitives.scala:77:20]
wire [31:0] _roundMask_T_14 = 32'hFFFF00; // @[primitives.scala:77:20]
wire [31:0] _roundMask_T_15 = 32'hFF00FF; // @[primitives.scala:77:20]
wire [31:0] _roundMask_T_20 = 32'hFF00FF00; // @[primitives.scala:77:20]
wire [27:0] _roundMask_T_23 = 28'hFF00FF; // @[primitives.scala:77:20]
wire [31:0] _roundMask_T_24 = 32'hFF00FF0; // @[primitives.scala:77:20]
wire [31:0] _roundMask_T_25 = 32'hF0F0F0F; // @[primitives.scala:77:20]
wire [31:0] _roundMask_T_30 = 32'hF0F0F0F0; // @[primitives.scala:77:20]
wire [29:0] _roundMask_T_33 = 30'hF0F0F0F; // @[primitives.scala:77:20]
wire [31:0] _roundMask_T_34 = 32'h3C3C3C3C; // @[primitives.scala:77:20]
wire [31:0] _roundMask_T_35 = 32'h33333333; // @[primitives.scala:77:20]
wire [31:0] _roundMask_T_40 = 32'hCCCCCCCC; // @[primitives.scala:77:20]
wire [30:0] _roundMask_T_43 = 31'h33333333; // @[primitives.scala:77:20]
wire [31:0] _roundMask_T_44 = 32'h66666666; // @[primitives.scala:77:20]
wire [31:0] _roundMask_T_45 = 32'h55555555; // @[primitives.scala:77:20]
wire [31:0] _roundMask_T_50 = 32'hAAAAAAAA; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_56 = 16'hFF; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_55 = 16'hFF00; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_61 = 16'hFF00; // @[primitives.scala:77:20]
wire [11:0] _roundMask_T_64 = 12'hFF; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_65 = 16'hFF0; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_66 = 16'hF0F; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_71 = 16'hF0F0; // @[primitives.scala:77:20]
wire [13:0] _roundMask_T_74 = 14'hF0F; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_75 = 16'h3C3C; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_76 = 16'h3333; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_81 = 16'hCCCC; // @[primitives.scala:77:20]
wire [14:0] _roundMask_T_84 = 15'h3333; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_85 = 16'h6666; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_86 = 16'h5555; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_91 = 16'hAAAA; // @[primitives.scala:77:20]
wire [11:0] _expOut_T_4 = 12'hC31; // @[RoundAnyRawFNToRecFN.scala:258:19]
wire io_detectTininess = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire _common_underflow_T_7 = 1'h1; // @[RoundAnyRawFNToRecFN.scala:222:49]
wire [55:0] adjustedSig = io_in_sig_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :114:22]
wire [64:0] _io_out_T_1; // @[RoundAnyRawFNToRecFN.scala:286:33]
wire [4:0] _io_exceptionFlags_T_3; // @[RoundAnyRawFNToRecFN.scala:288:66]
wire [64:0] io_out_0; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire [4:0] io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire roundingMode_near_even = io_roundingMode_0 == 3'h0; // @[RoundAnyRawFNToRecFN.scala:48:5, :90:53]
wire roundingMode_minMag = io_roundingMode_0 == 3'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :91:53]
wire roundingMode_min = io_roundingMode_0 == 3'h2; // @[RoundAnyRawFNToRecFN.scala:48:5, :92:53]
wire roundingMode_max = io_roundingMode_0 == 3'h3; // @[RoundAnyRawFNToRecFN.scala:48:5, :93:53]
wire roundingMode_near_maxMag = io_roundingMode_0 == 3'h4; // @[RoundAnyRawFNToRecFN.scala:48:5, :94:53]
wire roundingMode_odd = io_roundingMode_0 == 3'h6; // @[RoundAnyRawFNToRecFN.scala:48:5, :95:53]
wire _roundMagUp_T = roundingMode_min & io_in_sign_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :92:53, :98:27]
wire _roundMagUp_T_1 = ~io_in_sign_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :98:66]
wire _roundMagUp_T_2 = roundingMode_max & _roundMagUp_T_1; // @[RoundAnyRawFNToRecFN.scala:93:53, :98:{63,66}]
wire roundMagUp = _roundMagUp_T | _roundMagUp_T_2; // @[RoundAnyRawFNToRecFN.scala:98:{27,42,63}]
wire doShiftSigDown1 = adjustedSig[55]; // @[RoundAnyRawFNToRecFN.scala:114:22, :120:57]
wire [11:0] _common_expOut_T; // @[RoundAnyRawFNToRecFN.scala:187:37]
wire [11:0] common_expOut; // @[RoundAnyRawFNToRecFN.scala:122:31]
wire [51:0] _common_fractOut_T_2; // @[RoundAnyRawFNToRecFN.scala:189:16]
wire [51:0] common_fractOut; // @[RoundAnyRawFNToRecFN.scala:123:31]
wire _common_overflow_T_1; // @[RoundAnyRawFNToRecFN.scala:196:50]
wire common_overflow; // @[RoundAnyRawFNToRecFN.scala:124:37]
wire _common_totalUnderflow_T; // @[RoundAnyRawFNToRecFN.scala:200:31]
wire common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:125:37]
wire _common_underflow_T_18; // @[RoundAnyRawFNToRecFN.scala:217:40]
wire common_underflow; // @[RoundAnyRawFNToRecFN.scala:126:37]
wire _common_inexact_T; // @[RoundAnyRawFNToRecFN.scala:230:49]
wire common_inexact; // @[RoundAnyRawFNToRecFN.scala:127:37]
wire [11:0] _roundMask_T = io_in_sExp_0[11:0]; // @[RoundAnyRawFNToRecFN.scala:48:5, :156:37]
wire [11:0] _roundMask_T_1 = ~_roundMask_T; // @[primitives.scala:52:21]
wire roundMask_msb = _roundMask_T_1[11]; // @[primitives.scala:52:21, :58:25]
wire [10:0] roundMask_lsbs = _roundMask_T_1[10:0]; // @[primitives.scala:52:21, :59:26]
wire roundMask_msb_1 = roundMask_lsbs[10]; // @[primitives.scala:58:25, :59:26]
wire [9:0] roundMask_lsbs_1 = roundMask_lsbs[9:0]; // @[primitives.scala:59:26]
wire roundMask_msb_2 = roundMask_lsbs_1[9]; // @[primitives.scala:58:25, :59:26]
wire roundMask_msb_6 = roundMask_lsbs_1[9]; // @[primitives.scala:58:25, :59:26]
wire [8:0] roundMask_lsbs_2 = roundMask_lsbs_1[8:0]; // @[primitives.scala:59:26]
wire [8:0] roundMask_lsbs_6 = roundMask_lsbs_1[8:0]; // @[primitives.scala:59:26]
wire roundMask_msb_3 = roundMask_lsbs_2[8]; // @[primitives.scala:58:25, :59:26]
wire [7:0] roundMask_lsbs_3 = roundMask_lsbs_2[7:0]; // @[primitives.scala:59:26]
wire roundMask_msb_4 = roundMask_lsbs_3[7]; // @[primitives.scala:58:25, :59:26]
wire [6:0] roundMask_lsbs_4 = roundMask_lsbs_3[6:0]; // @[primitives.scala:59:26]
wire roundMask_msb_5 = roundMask_lsbs_4[6]; // @[primitives.scala:58:25, :59:26]
wire [5:0] roundMask_lsbs_5 = roundMask_lsbs_4[5:0]; // @[primitives.scala:59:26]
wire [64:0] roundMask_shift = $signed(65'sh10000000000000000 >>> roundMask_lsbs_5); // @[primitives.scala:59:26, :76:56]
wire [50:0] _roundMask_T_2 = roundMask_shift[63:13]; // @[primitives.scala:76:56, :78:22]
wire [31:0] _roundMask_T_3 = _roundMask_T_2[31:0]; // @[primitives.scala:77:20, :78:22]
wire [15:0] _roundMask_T_6 = _roundMask_T_3[31:16]; // @[primitives.scala:77:20]
wire [31:0] _roundMask_T_7 = {16'h0, _roundMask_T_6}; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_8 = _roundMask_T_3[15:0]; // @[primitives.scala:77:20]
wire [31:0] _roundMask_T_9 = {_roundMask_T_8, 16'h0}; // @[primitives.scala:77:20]
wire [31:0] _roundMask_T_11 = _roundMask_T_9 & 32'hFFFF0000; // @[primitives.scala:77:20]
wire [31:0] _roundMask_T_12 = _roundMask_T_7 | _roundMask_T_11; // @[primitives.scala:77:20]
wire [23:0] _roundMask_T_16 = _roundMask_T_12[31:8]; // @[primitives.scala:77:20]
wire [31:0] _roundMask_T_17 = {8'h0, _roundMask_T_16 & 24'hFF00FF}; // @[primitives.scala:77:20]
wire [23:0] _roundMask_T_18 = _roundMask_T_12[23:0]; // @[primitives.scala:77:20]
wire [31:0] _roundMask_T_19 = {_roundMask_T_18, 8'h0}; // @[primitives.scala:77:20]
wire [31:0] _roundMask_T_21 = _roundMask_T_19 & 32'hFF00FF00; // @[primitives.scala:77:20]
wire [31:0] _roundMask_T_22 = _roundMask_T_17 | _roundMask_T_21; // @[primitives.scala:77:20]
wire [27:0] _roundMask_T_26 = _roundMask_T_22[31:4]; // @[primitives.scala:77:20]
wire [31:0] _roundMask_T_27 = {4'h0, _roundMask_T_26 & 28'hF0F0F0F}; // @[primitives.scala:77:20]
wire [27:0] _roundMask_T_28 = _roundMask_T_22[27:0]; // @[primitives.scala:77:20]
wire [31:0] _roundMask_T_29 = {_roundMask_T_28, 4'h0}; // @[primitives.scala:77:20]
wire [31:0] _roundMask_T_31 = _roundMask_T_29 & 32'hF0F0F0F0; // @[primitives.scala:77:20]
wire [31:0] _roundMask_T_32 = _roundMask_T_27 | _roundMask_T_31; // @[primitives.scala:77:20]
wire [29:0] _roundMask_T_36 = _roundMask_T_32[31:2]; // @[primitives.scala:77:20]
wire [31:0] _roundMask_T_37 = {2'h0, _roundMask_T_36 & 30'h33333333}; // @[primitives.scala:77:20]
wire [29:0] _roundMask_T_38 = _roundMask_T_32[29:0]; // @[primitives.scala:77:20]
wire [31:0] _roundMask_T_39 = {_roundMask_T_38, 2'h0}; // @[primitives.scala:77:20]
wire [31:0] _roundMask_T_41 = _roundMask_T_39 & 32'hCCCCCCCC; // @[primitives.scala:77:20]
wire [31:0] _roundMask_T_42 = _roundMask_T_37 | _roundMask_T_41; // @[primitives.scala:77:20]
wire [30:0] _roundMask_T_46 = _roundMask_T_42[31:1]; // @[primitives.scala:77:20]
wire [31:0] _roundMask_T_47 = {1'h0, _roundMask_T_46 & 31'h55555555}; // @[primitives.scala:77:20]
wire [30:0] _roundMask_T_48 = _roundMask_T_42[30:0]; // @[primitives.scala:77:20]
wire [31:0] _roundMask_T_49 = {_roundMask_T_48, 1'h0}; // @[primitives.scala:77:20]
wire [31:0] _roundMask_T_51 = _roundMask_T_49 & 32'hAAAAAAAA; // @[primitives.scala:77:20]
wire [31:0] _roundMask_T_52 = _roundMask_T_47 | _roundMask_T_51; // @[primitives.scala:77:20]
wire [18:0] _roundMask_T_53 = _roundMask_T_2[50:32]; // @[primitives.scala:77:20, :78:22]
wire [15:0] _roundMask_T_54 = _roundMask_T_53[15:0]; // @[primitives.scala:77:20]
wire [7:0] _roundMask_T_57 = _roundMask_T_54[15:8]; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_58 = {8'h0, _roundMask_T_57}; // @[primitives.scala:77:20]
wire [7:0] _roundMask_T_59 = _roundMask_T_54[7:0]; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_60 = {_roundMask_T_59, 8'h0}; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_62 = _roundMask_T_60 & 16'hFF00; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_63 = _roundMask_T_58 | _roundMask_T_62; // @[primitives.scala:77:20]
wire [11:0] _roundMask_T_67 = _roundMask_T_63[15:4]; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_68 = {4'h0, _roundMask_T_67 & 12'hF0F}; // @[primitives.scala:77:20]
wire [11:0] _roundMask_T_69 = _roundMask_T_63[11:0]; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_70 = {_roundMask_T_69, 4'h0}; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_72 = _roundMask_T_70 & 16'hF0F0; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_73 = _roundMask_T_68 | _roundMask_T_72; // @[primitives.scala:77:20]
wire [13:0] _roundMask_T_77 = _roundMask_T_73[15:2]; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_78 = {2'h0, _roundMask_T_77 & 14'h3333}; // @[primitives.scala:77:20]
wire [13:0] _roundMask_T_79 = _roundMask_T_73[13:0]; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_80 = {_roundMask_T_79, 2'h0}; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_82 = _roundMask_T_80 & 16'hCCCC; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_83 = _roundMask_T_78 | _roundMask_T_82; // @[primitives.scala:77:20]
wire [14:0] _roundMask_T_87 = _roundMask_T_83[15:1]; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_88 = {1'h0, _roundMask_T_87 & 15'h5555}; // @[primitives.scala:77:20]
wire [14:0] _roundMask_T_89 = _roundMask_T_83[14:0]; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_90 = {_roundMask_T_89, 1'h0}; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_92 = _roundMask_T_90 & 16'hAAAA; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_93 = _roundMask_T_88 | _roundMask_T_92; // @[primitives.scala:77:20]
wire [2:0] _roundMask_T_94 = _roundMask_T_53[18:16]; // @[primitives.scala:77:20]
wire [1:0] _roundMask_T_95 = _roundMask_T_94[1:0]; // @[primitives.scala:77:20]
wire _roundMask_T_96 = _roundMask_T_95[0]; // @[primitives.scala:77:20]
wire _roundMask_T_97 = _roundMask_T_95[1]; // @[primitives.scala:77:20]
wire [1:0] _roundMask_T_98 = {_roundMask_T_96, _roundMask_T_97}; // @[primitives.scala:77:20]
wire _roundMask_T_99 = _roundMask_T_94[2]; // @[primitives.scala:77:20]
wire [2:0] _roundMask_T_100 = {_roundMask_T_98, _roundMask_T_99}; // @[primitives.scala:77:20]
wire [18:0] _roundMask_T_101 = {_roundMask_T_93, _roundMask_T_100}; // @[primitives.scala:77:20]
wire [50:0] _roundMask_T_102 = {_roundMask_T_52, _roundMask_T_101}; // @[primitives.scala:77:20]
wire [50:0] _roundMask_T_103 = ~_roundMask_T_102; // @[primitives.scala:73:32, :77:20]
wire [50:0] _roundMask_T_104 = roundMask_msb_5 ? 51'h0 : _roundMask_T_103; // @[primitives.scala:58:25, :73:{21,32}]
wire [50:0] _roundMask_T_105 = ~_roundMask_T_104; // @[primitives.scala:73:{17,21}]
wire [50:0] _roundMask_T_106 = ~_roundMask_T_105; // @[primitives.scala:73:{17,32}]
wire [50:0] _roundMask_T_107 = roundMask_msb_4 ? 51'h0 : _roundMask_T_106; // @[primitives.scala:58:25, :73:{21,32}]
wire [50:0] _roundMask_T_108 = ~_roundMask_T_107; // @[primitives.scala:73:{17,21}]
wire [50:0] _roundMask_T_109 = ~_roundMask_T_108; // @[primitives.scala:73:{17,32}]
wire [50:0] _roundMask_T_110 = roundMask_msb_3 ? 51'h0 : _roundMask_T_109; // @[primitives.scala:58:25, :73:{21,32}]
wire [50:0] _roundMask_T_111 = ~_roundMask_T_110; // @[primitives.scala:73:{17,21}]
wire [50:0] _roundMask_T_112 = ~_roundMask_T_111; // @[primitives.scala:73:{17,32}]
wire [50:0] _roundMask_T_113 = roundMask_msb_2 ? 51'h0 : _roundMask_T_112; // @[primitives.scala:58:25, :73:{21,32}]
wire [50:0] _roundMask_T_114 = ~_roundMask_T_113; // @[primitives.scala:73:{17,21}]
wire [53:0] _roundMask_T_115 = {_roundMask_T_114, 3'h7}; // @[primitives.scala:68:58, :73:17]
wire roundMask_msb_7 = roundMask_lsbs_6[8]; // @[primitives.scala:58:25, :59:26]
wire [7:0] roundMask_lsbs_7 = roundMask_lsbs_6[7:0]; // @[primitives.scala:59:26]
wire roundMask_msb_8 = roundMask_lsbs_7[7]; // @[primitives.scala:58:25, :59:26]
wire [6:0] roundMask_lsbs_8 = roundMask_lsbs_7[6:0]; // @[primitives.scala:59:26]
wire roundMask_msb_9 = roundMask_lsbs_8[6]; // @[primitives.scala:58:25, :59:26]
wire [5:0] roundMask_lsbs_9 = roundMask_lsbs_8[5:0]; // @[primitives.scala:59:26]
wire [64:0] roundMask_shift_1 = $signed(65'sh10000000000000000 >>> roundMask_lsbs_9); // @[primitives.scala:59:26, :76:56]
wire [2:0] _roundMask_T_116 = roundMask_shift_1[2:0]; // @[primitives.scala:76:56, :78:22]
wire [1:0] _roundMask_T_117 = _roundMask_T_116[1:0]; // @[primitives.scala:77:20, :78:22]
wire _roundMask_T_118 = _roundMask_T_117[0]; // @[primitives.scala:77:20]
wire _roundMask_T_119 = _roundMask_T_117[1]; // @[primitives.scala:77:20]
wire [1:0] _roundMask_T_120 = {_roundMask_T_118, _roundMask_T_119}; // @[primitives.scala:77:20]
wire _roundMask_T_121 = _roundMask_T_116[2]; // @[primitives.scala:77:20, :78:22]
wire [2:0] _roundMask_T_122 = {_roundMask_T_120, _roundMask_T_121}; // @[primitives.scala:77:20]
wire [2:0] _roundMask_T_123 = roundMask_msb_9 ? _roundMask_T_122 : 3'h0; // @[primitives.scala:58:25, :62:24, :77:20]
wire [2:0] _roundMask_T_124 = roundMask_msb_8 ? _roundMask_T_123 : 3'h0; // @[primitives.scala:58:25, :62:24]
wire [2:0] _roundMask_T_125 = roundMask_msb_7 ? _roundMask_T_124 : 3'h0; // @[primitives.scala:58:25, :62:24]
wire [2:0] _roundMask_T_126 = roundMask_msb_6 ? _roundMask_T_125 : 3'h0; // @[primitives.scala:58:25, :62:24]
wire [53:0] _roundMask_T_127 = roundMask_msb_1 ? _roundMask_T_115 : {51'h0, _roundMask_T_126}; // @[primitives.scala:58:25, :62:24, :67:24, :68:58]
wire [53:0] _roundMask_T_128 = roundMask_msb ? _roundMask_T_127 : 54'h0; // @[primitives.scala:58:25, :62:24, :67:24]
wire [53:0] _roundMask_T_129 = {_roundMask_T_128[53:1], _roundMask_T_128[0] | doShiftSigDown1}; // @[primitives.scala:62:24]
wire [55:0] roundMask = {_roundMask_T_129, 2'h3}; // @[RoundAnyRawFNToRecFN.scala:159:{23,42}]
wire [56:0] _shiftedRoundMask_T = {1'h0, roundMask}; // @[RoundAnyRawFNToRecFN.scala:159:42, :162:41]
wire [55:0] shiftedRoundMask = _shiftedRoundMask_T[56:1]; // @[RoundAnyRawFNToRecFN.scala:162:{41,53}]
wire [55:0] _roundPosMask_T = ~shiftedRoundMask; // @[RoundAnyRawFNToRecFN.scala:162:53, :163:28]
wire [55:0] roundPosMask = _roundPosMask_T & roundMask; // @[RoundAnyRawFNToRecFN.scala:159:42, :163:{28,46}]
wire [55:0] _roundPosBit_T = adjustedSig & roundPosMask; // @[RoundAnyRawFNToRecFN.scala:114:22, :163:46, :164:40]
wire roundPosBit = |_roundPosBit_T; // @[RoundAnyRawFNToRecFN.scala:164:{40,56}]
wire [55:0] _anyRoundExtra_T = adjustedSig & shiftedRoundMask; // @[RoundAnyRawFNToRecFN.scala:114:22, :162:53, :165:42]
wire anyRoundExtra = |_anyRoundExtra_T; // @[RoundAnyRawFNToRecFN.scala:165:{42,62}]
wire anyRound = roundPosBit | anyRoundExtra; // @[RoundAnyRawFNToRecFN.scala:164:56, :165:62, :166:36]
wire _GEN = roundingMode_near_even | roundingMode_near_maxMag; // @[RoundAnyRawFNToRecFN.scala:90:53, :94:53, :169:38]
wire _roundIncr_T; // @[RoundAnyRawFNToRecFN.scala:169:38]
assign _roundIncr_T = _GEN; // @[RoundAnyRawFNToRecFN.scala:169:38]
wire _unboundedRange_roundIncr_T; // @[RoundAnyRawFNToRecFN.scala:207:38]
assign _unboundedRange_roundIncr_T = _GEN; // @[RoundAnyRawFNToRecFN.scala:169:38, :207:38]
wire _overflow_roundMagUp_T; // @[RoundAnyRawFNToRecFN.scala:243:32]
assign _overflow_roundMagUp_T = _GEN; // @[RoundAnyRawFNToRecFN.scala:169:38, :243:32]
wire _roundIncr_T_1 = _roundIncr_T & roundPosBit; // @[RoundAnyRawFNToRecFN.scala:164:56, :169:{38,67}]
wire _roundIncr_T_2 = roundMagUp & anyRound; // @[RoundAnyRawFNToRecFN.scala:98:42, :166:36, :171:29]
wire roundIncr = _roundIncr_T_1 | _roundIncr_T_2; // @[RoundAnyRawFNToRecFN.scala:169:67, :170:31, :171:29]
wire [55:0] _roundedSig_T = adjustedSig | roundMask; // @[RoundAnyRawFNToRecFN.scala:114:22, :159:42, :174:32]
wire [53:0] _roundedSig_T_1 = _roundedSig_T[55:2]; // @[RoundAnyRawFNToRecFN.scala:174:{32,44}]
wire [54:0] _roundedSig_T_2 = {1'h0, _roundedSig_T_1} + 55'h1; // @[RoundAnyRawFNToRecFN.scala:174:{44,49}]
wire _roundedSig_T_3 = roundingMode_near_even & roundPosBit; // @[RoundAnyRawFNToRecFN.scala:90:53, :164:56, :175:49]
wire _roundedSig_T_4 = ~anyRoundExtra; // @[RoundAnyRawFNToRecFN.scala:165:62, :176:30]
wire _roundedSig_T_5 = _roundedSig_T_3 & _roundedSig_T_4; // @[RoundAnyRawFNToRecFN.scala:175:{49,64}, :176:30]
wire [54:0] _roundedSig_T_6 = roundMask[55:1]; // @[RoundAnyRawFNToRecFN.scala:159:42, :177:35]
wire [54:0] _roundedSig_T_7 = _roundedSig_T_5 ? _roundedSig_T_6 : 55'h0; // @[RoundAnyRawFNToRecFN.scala:175:{25,64}, :177:35]
wire [54:0] _roundedSig_T_8 = ~_roundedSig_T_7; // @[RoundAnyRawFNToRecFN.scala:175:{21,25}]
wire [54:0] _roundedSig_T_9 = _roundedSig_T_2 & _roundedSig_T_8; // @[RoundAnyRawFNToRecFN.scala:174:{49,57}, :175:21]
wire [55:0] _roundedSig_T_10 = ~roundMask; // @[RoundAnyRawFNToRecFN.scala:159:42, :180:32]
wire [55:0] _roundedSig_T_11 = adjustedSig & _roundedSig_T_10; // @[RoundAnyRawFNToRecFN.scala:114:22, :180:{30,32}]
wire [53:0] _roundedSig_T_12 = _roundedSig_T_11[55:2]; // @[RoundAnyRawFNToRecFN.scala:180:{30,43}]
wire _roundedSig_T_13 = roundingMode_odd & anyRound; // @[RoundAnyRawFNToRecFN.scala:95:53, :166:36, :181:42]
wire [54:0] _roundedSig_T_14 = roundPosMask[55:1]; // @[RoundAnyRawFNToRecFN.scala:163:46, :181:67]
wire [54:0] _roundedSig_T_15 = _roundedSig_T_13 ? _roundedSig_T_14 : 55'h0; // @[RoundAnyRawFNToRecFN.scala:181:{24,42,67}]
wire [54:0] _roundedSig_T_16 = {1'h0, _roundedSig_T_12} | _roundedSig_T_15; // @[RoundAnyRawFNToRecFN.scala:180:{43,47}, :181:24]
wire [54:0] roundedSig = roundIncr ? _roundedSig_T_9 : _roundedSig_T_16; // @[RoundAnyRawFNToRecFN.scala:170:31, :173:16, :174:57, :180:47]
wire [1:0] _sRoundedExp_T = roundedSig[54:53]; // @[RoundAnyRawFNToRecFN.scala:173:16, :185:54]
wire [2:0] _sRoundedExp_T_1 = {1'h0, _sRoundedExp_T}; // @[RoundAnyRawFNToRecFN.scala:185:{54,76}]
wire [13:0] sRoundedExp = {io_in_sExp_0[12], io_in_sExp_0} + {{11{_sRoundedExp_T_1[2]}}, _sRoundedExp_T_1}; // @[RoundAnyRawFNToRecFN.scala:48:5, :185:{40,76}]
assign _common_expOut_T = sRoundedExp[11:0]; // @[RoundAnyRawFNToRecFN.scala:185:40, :187:37]
assign common_expOut = _common_expOut_T; // @[RoundAnyRawFNToRecFN.scala:122:31, :187:37]
wire [51:0] _common_fractOut_T = roundedSig[52:1]; // @[RoundAnyRawFNToRecFN.scala:173:16, :190:27]
wire [51:0] _common_fractOut_T_1 = roundedSig[51:0]; // @[RoundAnyRawFNToRecFN.scala:173:16, :191:27]
assign _common_fractOut_T_2 = doShiftSigDown1 ? _common_fractOut_T : _common_fractOut_T_1; // @[RoundAnyRawFNToRecFN.scala:120:57, :189:16, :190:27, :191:27]
assign common_fractOut = _common_fractOut_T_2; // @[RoundAnyRawFNToRecFN.scala:123:31, :189:16]
wire [3:0] _common_overflow_T = sRoundedExp[13:10]; // @[RoundAnyRawFNToRecFN.scala:185:40, :196:30]
assign _common_overflow_T_1 = $signed(_common_overflow_T) > 4'sh2; // @[RoundAnyRawFNToRecFN.scala:196:{30,50}]
assign common_overflow = _common_overflow_T_1; // @[RoundAnyRawFNToRecFN.scala:124:37, :196:50]
assign _common_totalUnderflow_T = $signed(sRoundedExp) < 14'sh3CE; // @[RoundAnyRawFNToRecFN.scala:185:40, :200:31]
assign common_totalUnderflow = _common_totalUnderflow_T; // @[RoundAnyRawFNToRecFN.scala:125:37, :200:31]
wire _unboundedRange_roundPosBit_T = adjustedSig[2]; // @[RoundAnyRawFNToRecFN.scala:114:22, :203:45]
wire _unboundedRange_anyRound_T = adjustedSig[2]; // @[RoundAnyRawFNToRecFN.scala:114:22, :203:45, :205:44]
wire _unboundedRange_roundPosBit_T_1 = adjustedSig[1]; // @[RoundAnyRawFNToRecFN.scala:114:22, :203:61]
wire unboundedRange_roundPosBit = doShiftSigDown1 ? _unboundedRange_roundPosBit_T : _unboundedRange_roundPosBit_T_1; // @[RoundAnyRawFNToRecFN.scala:120:57, :203:{16,45,61}]
wire _unboundedRange_anyRound_T_1 = doShiftSigDown1 & _unboundedRange_anyRound_T; // @[RoundAnyRawFNToRecFN.scala:120:57, :205:{30,44}]
wire [1:0] _unboundedRange_anyRound_T_2 = adjustedSig[1:0]; // @[RoundAnyRawFNToRecFN.scala:114:22, :205:63]
wire _unboundedRange_anyRound_T_3 = |_unboundedRange_anyRound_T_2; // @[RoundAnyRawFNToRecFN.scala:205:{63,70}]
wire unboundedRange_anyRound = _unboundedRange_anyRound_T_1 | _unboundedRange_anyRound_T_3; // @[RoundAnyRawFNToRecFN.scala:205:{30,49,70}]
wire _unboundedRange_roundIncr_T_1 = _unboundedRange_roundIncr_T & unboundedRange_roundPosBit; // @[RoundAnyRawFNToRecFN.scala:203:16, :207:{38,67}]
wire _unboundedRange_roundIncr_T_2 = roundMagUp & unboundedRange_anyRound; // @[RoundAnyRawFNToRecFN.scala:98:42, :205:49, :209:29]
wire unboundedRange_roundIncr = _unboundedRange_roundIncr_T_1 | _unboundedRange_roundIncr_T_2; // @[RoundAnyRawFNToRecFN.scala:207:67, :208:46, :209:29]
wire _roundCarry_T = roundedSig[54]; // @[RoundAnyRawFNToRecFN.scala:173:16, :212:27]
wire _roundCarry_T_1 = roundedSig[53]; // @[RoundAnyRawFNToRecFN.scala:173:16, :213:27]
wire roundCarry = doShiftSigDown1 ? _roundCarry_T : _roundCarry_T_1; // @[RoundAnyRawFNToRecFN.scala:120:57, :211:16, :212:27, :213:27]
wire [1:0] _common_underflow_T = io_in_sExp_0[12:11]; // @[RoundAnyRawFNToRecFN.scala:48:5, :220:49]
wire _common_underflow_T_1 = _common_underflow_T != 2'h1; // @[RoundAnyRawFNToRecFN.scala:220:{49,64}]
wire _common_underflow_T_2 = anyRound & _common_underflow_T_1; // @[RoundAnyRawFNToRecFN.scala:166:36, :220:{32,64}]
wire _common_underflow_T_3 = roundMask[3]; // @[RoundAnyRawFNToRecFN.scala:159:42, :221:57]
wire _common_underflow_T_9 = roundMask[3]; // @[RoundAnyRawFNToRecFN.scala:159:42, :221:57, :225:49]
wire _common_underflow_T_4 = roundMask[2]; // @[RoundAnyRawFNToRecFN.scala:159:42, :221:71]
wire _common_underflow_T_5 = doShiftSigDown1 ? _common_underflow_T_3 : _common_underflow_T_4; // @[RoundAnyRawFNToRecFN.scala:120:57, :221:{30,57,71}]
wire _common_underflow_T_6 = _common_underflow_T_2 & _common_underflow_T_5; // @[RoundAnyRawFNToRecFN.scala:220:{32,72}, :221:30]
wire _common_underflow_T_8 = roundMask[4]; // @[RoundAnyRawFNToRecFN.scala:159:42, :224:49]
wire _common_underflow_T_10 = doShiftSigDown1 ? _common_underflow_T_8 : _common_underflow_T_9; // @[RoundAnyRawFNToRecFN.scala:120:57, :223:39, :224:49, :225:49]
wire _common_underflow_T_11 = ~_common_underflow_T_10; // @[RoundAnyRawFNToRecFN.scala:223:{34,39}]
wire _common_underflow_T_12 = _common_underflow_T_11; // @[RoundAnyRawFNToRecFN.scala:222:77, :223:34]
wire _common_underflow_T_13 = _common_underflow_T_12 & roundCarry; // @[RoundAnyRawFNToRecFN.scala:211:16, :222:77, :226:38]
wire _common_underflow_T_14 = _common_underflow_T_13 & roundPosBit; // @[RoundAnyRawFNToRecFN.scala:164:56, :226:38, :227:45]
wire _common_underflow_T_15 = _common_underflow_T_14 & unboundedRange_roundIncr; // @[RoundAnyRawFNToRecFN.scala:208:46, :227:{45,60}]
wire _common_underflow_T_16 = ~_common_underflow_T_15; // @[RoundAnyRawFNToRecFN.scala:222:27, :227:60]
wire _common_underflow_T_17 = _common_underflow_T_6 & _common_underflow_T_16; // @[RoundAnyRawFNToRecFN.scala:220:72, :221:76, :222:27]
assign _common_underflow_T_18 = common_totalUnderflow | _common_underflow_T_17; // @[RoundAnyRawFNToRecFN.scala:125:37, :217:40, :221:76]
assign common_underflow = _common_underflow_T_18; // @[RoundAnyRawFNToRecFN.scala:126:37, :217:40]
assign _common_inexact_T = common_totalUnderflow | anyRound; // @[RoundAnyRawFNToRecFN.scala:125:37, :166:36, :230:49]
assign common_inexact = _common_inexact_T; // @[RoundAnyRawFNToRecFN.scala:127:37, :230:49]
wire isNaNOut = io_invalidExc_0 | io_in_isNaN_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :235:34]
wire notNaN_isSpecialInfOut = io_infiniteExc_0 | io_in_isInf_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :236:49]
wire _commonCase_T = ~isNaNOut; // @[RoundAnyRawFNToRecFN.scala:235:34, :237:22]
wire _commonCase_T_1 = ~notNaN_isSpecialInfOut; // @[RoundAnyRawFNToRecFN.scala:236:49, :237:36]
wire _commonCase_T_2 = _commonCase_T & _commonCase_T_1; // @[RoundAnyRawFNToRecFN.scala:237:{22,33,36}]
wire _commonCase_T_3 = ~io_in_isZero_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :237:64]
wire commonCase = _commonCase_T_2 & _commonCase_T_3; // @[RoundAnyRawFNToRecFN.scala:237:{33,61,64}]
wire overflow = commonCase & common_overflow; // @[RoundAnyRawFNToRecFN.scala:124:37, :237:61, :238:32]
wire underflow = commonCase & common_underflow; // @[RoundAnyRawFNToRecFN.scala:126:37, :237:61, :239:32]
wire _inexact_T = commonCase & common_inexact; // @[RoundAnyRawFNToRecFN.scala:127:37, :237:61, :240:43]
wire inexact = overflow | _inexact_T; // @[RoundAnyRawFNToRecFN.scala:238:32, :240:{28,43}]
wire overflow_roundMagUp = _overflow_roundMagUp_T | roundMagUp; // @[RoundAnyRawFNToRecFN.scala:98:42, :243:{32,60}]
wire _pegMinNonzeroMagOut_T = commonCase & common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:125:37, :237:61, :245:20]
wire _pegMinNonzeroMagOut_T_1 = roundMagUp | roundingMode_odd; // @[RoundAnyRawFNToRecFN.scala:95:53, :98:42, :245:60]
wire pegMinNonzeroMagOut = _pegMinNonzeroMagOut_T & _pegMinNonzeroMagOut_T_1; // @[RoundAnyRawFNToRecFN.scala:245:{20,45,60}]
wire _pegMaxFiniteMagOut_T = ~overflow_roundMagUp; // @[RoundAnyRawFNToRecFN.scala:243:60, :246:42]
wire pegMaxFiniteMagOut = overflow & _pegMaxFiniteMagOut_T; // @[RoundAnyRawFNToRecFN.scala:238:32, :246:{39,42}]
wire _notNaN_isInfOut_T = overflow & overflow_roundMagUp; // @[RoundAnyRawFNToRecFN.scala:238:32, :243:60, :248:45]
wire notNaN_isInfOut = notNaN_isSpecialInfOut | _notNaN_isInfOut_T; // @[RoundAnyRawFNToRecFN.scala:236:49, :248:{32,45}]
wire signOut = ~isNaNOut & io_in_sign_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :235:34, :250:22]
wire _expOut_T = io_in_isZero_0 | common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:48:5, :125:37, :253:32]
wire [11:0] _expOut_T_1 = _expOut_T ? 12'hE00 : 12'h0; // @[RoundAnyRawFNToRecFN.scala:253:{18,32}]
wire [11:0] _expOut_T_2 = ~_expOut_T_1; // @[RoundAnyRawFNToRecFN.scala:253:{14,18}]
wire [11:0] _expOut_T_3 = common_expOut & _expOut_T_2; // @[RoundAnyRawFNToRecFN.scala:122:31, :252:24, :253:14]
wire [11:0] _expOut_T_5 = pegMinNonzeroMagOut ? 12'hC31 : 12'h0; // @[RoundAnyRawFNToRecFN.scala:245:45, :257:18]
wire [11:0] _expOut_T_6 = ~_expOut_T_5; // @[RoundAnyRawFNToRecFN.scala:257:{14,18}]
wire [11:0] _expOut_T_7 = _expOut_T_3 & _expOut_T_6; // @[RoundAnyRawFNToRecFN.scala:252:24, :256:17, :257:14]
wire [11:0] _expOut_T_8 = {1'h0, pegMaxFiniteMagOut, 10'h0}; // @[RoundAnyRawFNToRecFN.scala:246:39, :261:18]
wire [11:0] _expOut_T_9 = ~_expOut_T_8; // @[RoundAnyRawFNToRecFN.scala:261:{14,18}]
wire [11:0] _expOut_T_10 = _expOut_T_7 & _expOut_T_9; // @[RoundAnyRawFNToRecFN.scala:256:17, :260:17, :261:14]
wire [11:0] _expOut_T_11 = {2'h0, notNaN_isInfOut, 9'h0}; // @[RoundAnyRawFNToRecFN.scala:248:32, :265:18]
wire [11:0] _expOut_T_12 = ~_expOut_T_11; // @[RoundAnyRawFNToRecFN.scala:265:{14,18}]
wire [11:0] _expOut_T_13 = _expOut_T_10 & _expOut_T_12; // @[RoundAnyRawFNToRecFN.scala:260:17, :264:17, :265:14]
wire [11:0] _expOut_T_14 = pegMinNonzeroMagOut ? 12'h3CE : 12'h0; // @[RoundAnyRawFNToRecFN.scala:245:45, :269:16]
wire [11:0] _expOut_T_15 = _expOut_T_13 | _expOut_T_14; // @[RoundAnyRawFNToRecFN.scala:264:17, :268:18, :269:16]
wire [11:0] _expOut_T_16 = pegMaxFiniteMagOut ? 12'hBFF : 12'h0; // @[RoundAnyRawFNToRecFN.scala:246:39, :273:16]
wire [11:0] _expOut_T_17 = _expOut_T_15 | _expOut_T_16; // @[RoundAnyRawFNToRecFN.scala:268:18, :272:15, :273:16]
wire [11:0] _expOut_T_18 = notNaN_isInfOut ? 12'hC00 : 12'h0; // @[RoundAnyRawFNToRecFN.scala:248:32, :277:16]
wire [11:0] _expOut_T_19 = _expOut_T_17 | _expOut_T_18; // @[RoundAnyRawFNToRecFN.scala:272:15, :276:15, :277:16]
wire [11:0] _expOut_T_20 = isNaNOut ? 12'hE00 : 12'h0; // @[RoundAnyRawFNToRecFN.scala:235:34, :278:16]
wire [11:0] expOut = _expOut_T_19 | _expOut_T_20; // @[RoundAnyRawFNToRecFN.scala:276:15, :277:73, :278:16]
wire _fractOut_T = isNaNOut | io_in_isZero_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :235:34, :280:22]
wire _fractOut_T_1 = _fractOut_T | common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:125:37, :280:{22,38}]
wire [51:0] _fractOut_T_2 = {isNaNOut, 51'h0}; // @[RoundAnyRawFNToRecFN.scala:235:34, :281:16]
wire [51:0] _fractOut_T_3 = _fractOut_T_1 ? _fractOut_T_2 : common_fractOut; // @[RoundAnyRawFNToRecFN.scala:123:31, :280:{12,38}, :281:16]
wire [51:0] _fractOut_T_4 = {52{pegMaxFiniteMagOut}}; // @[RoundAnyRawFNToRecFN.scala:246:39, :284:13]
wire [51:0] fractOut = _fractOut_T_3 | _fractOut_T_4; // @[RoundAnyRawFNToRecFN.scala:280:12, :283:11, :284:13]
wire [12:0] _io_out_T = {signOut, expOut}; // @[RoundAnyRawFNToRecFN.scala:250:22, :277:73, :286:23]
assign _io_out_T_1 = {_io_out_T, fractOut}; // @[RoundAnyRawFNToRecFN.scala:283:11, :286:{23,33}]
assign io_out_0 = _io_out_T_1; // @[RoundAnyRawFNToRecFN.scala:48:5, :286:33]
wire [1:0] _io_exceptionFlags_T = {io_invalidExc_0, io_infiniteExc_0}; // @[RoundAnyRawFNToRecFN.scala:48:5, :288:23]
wire [2:0] _io_exceptionFlags_T_1 = {_io_exceptionFlags_T, overflow}; // @[RoundAnyRawFNToRecFN.scala:238:32, :288:{23,41}]
wire [3:0] _io_exceptionFlags_T_2 = {_io_exceptionFlags_T_1, underflow}; // @[RoundAnyRawFNToRecFN.scala:239:32, :288:{41,53}]
assign _io_exceptionFlags_T_3 = {_io_exceptionFlags_T_2, inexact}; // @[RoundAnyRawFNToRecFN.scala:240:28, :288:{53,66}]
assign io_exceptionFlags_0 = _io_exceptionFlags_T_3; // @[RoundAnyRawFNToRecFN.scala:48:5, :288:66]
assign io_out = io_out_0; // @[RoundAnyRawFNToRecFN.scala:48:5]
assign io_exceptionFlags = io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:48:5]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File regfile.scala:
//******************************************************************************
// Copyright (c) 2013 - 2018, The Regents of the University of California (Regents).
// All Rights Reserved. See LICENSE and LICENSE.SiFive for license details.
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
// Register File (Abstract class and Synthesizable RegFile)
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
package boom.v4.exu
import scala.collection.mutable.ArrayBuffer
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.Parameters
import boom.v4.common._
import boom.v4.util._
abstract class RegisterFile[T <: Data](
dType: T,
numRegisters: Int,
numReadPorts: Int,
numWritePorts: Int)
(implicit p: Parameters) extends BoomModule
{
val io = IO(new BoomBundle {
val arb_read_reqs = Vec(numReadPorts, Flipped(Decoupled(UInt(log2Ceil(numRegisters).W))))
val rrd_read_resps = Vec(numReadPorts, Output(dType))
val write_ports = Vec(numWritePorts, Flipped(Valid(new Bundle {
val addr = Output(UInt(maxPregSz.W))
val data = Output(dType)
})))
})
// ensure there is only 1 writer per register (unless to preg0)
if (numWritePorts > 1) {
for (i <- 0 until (numWritePorts - 1)) {
for (j <- (i + 1) until numWritePorts) {
assert(!io.write_ports(i).valid ||
!io.write_ports(j).valid ||
(io.write_ports(i).bits.addr =/= io.write_ports(j).bits.addr),
"[regfile] too many writers a register")
}
}
}
}
class BankedRF[T <: Data](
dType: T,
numBanks: Int,
numLogicalReadPortsPerBank: Int,
numRegisters: Int,
numLogicalReadPorts: Int,
numPhysicalReadPorts: Int,
numWritePorts: Int,
bankedWritePortArray: Seq[Option[Int]],
typeStr: String
)(implicit p: Parameters)
extends RegisterFile(dType, numRegisters, numLogicalReadPorts, numWritePorts)
{
require(isPow2(numBanks))
require(numRegisters % numBanks == 0)
require(bankedWritePortArray.length == numWritePorts)
val numDedicatedWritePorts = bankedWritePortArray.flatten.length
val writePortsPerBank = if (numDedicatedWritePorts == 0) {
numWritePorts
} else {
numWritePorts - numDedicatedWritePorts + 1
}
def bankIdx(i: UInt): UInt = i(log2Ceil(numBanks)-1,0)
val rfs = (0 until numBanks) map { w => Module(new PartiallyPortedRF(
dType,
numRegisters / numBanks,
numLogicalReadPortsPerBank,
numPhysicalReadPorts,
writePortsPerBank,
typeStr + s" Bank ${w}"
)) }
if (numBanks == 1) {
require(numLogicalReadPortsPerBank == numLogicalReadPorts)
io <> rfs(0).io
} else {
val widxs = Array.fill(numBanks)(0)
for (i <- 0 until numWritePorts) {
if (bankedWritePortArray(i) != None) {
val bank = bankedWritePortArray(i).get
val widx = widxs(bank)
rfs(bank).io.write_ports(widx).valid := io.write_ports(i).valid
rfs(bank).io.write_ports(widx).bits.addr := io.write_ports(i).bits.addr >> log2Ceil(numBanks)
rfs(bank).io.write_ports(widx).bits.data := io.write_ports(i).bits.data
assert(!io.write_ports(i).valid || bankIdx(io.write_ports(i).bits.addr) === bank.U)
widxs(bank) = widx + 1
} else {
for (w <- 0 until numBanks) {
val widx = widxs(w)
rfs(w).io.write_ports(widx).valid := io.write_ports(i).valid && bankIdx(io.write_ports(i).bits.addr) === w.U
rfs(w).io.write_ports(widx).bits.addr := io.write_ports(i).bits.addr >> log2Ceil(numBanks)
rfs(w).io.write_ports(widx).bits.data := io.write_ports(i).bits.data
widxs(w) = widx + 1
}
}
}
require(widxs.forall(_ == writePortsPerBank), widxs.mkString(","))
if (numLogicalReadPortsPerBank == numLogicalReadPorts) {
for (i <- 0 until numLogicalReadPorts) {
val bidx = bankIdx(io.arb_read_reqs(i).bits)
for (w <- 0 until numBanks) {
rfs(w).io.arb_read_reqs(i).valid := io.arb_read_reqs(i).valid && bankIdx(io.arb_read_reqs(i).bits) === w.U
rfs(w).io.arb_read_reqs(i).bits := io.arb_read_reqs(i).bits >> log2Ceil(numBanks)
}
val arb_data_sel = UIntToOH(bidx)
val rrd_data_sel = RegNext(arb_data_sel)
io.arb_read_reqs(i).ready := Mux1H(arb_data_sel, rfs.map(_.io.arb_read_reqs(i).ready))
io.rrd_read_resps(i) := Mux1H(rrd_data_sel, rfs.map(_.io.rrd_read_resps(i)))
}
}
}
override def toString: String = rfs.map(_.toString).mkString
}
class PartiallyPortedRF[T <: Data](
dType: T,
numRegisters: Int,
numLogicalReadPorts: Int,
numPhysicalReadPorts: Int,
numWritePorts: Int,
typeStr: String
)(implicit p: Parameters)
extends RegisterFile(dType, numRegisters, numLogicalReadPorts, numWritePorts)
{
val rf = Module(new FullyPortedRF(
dType = dType,
numRegisters = numRegisters,
numReadPorts = numPhysicalReadPorts,
numWritePorts = numWritePorts,
typeStr = "Partially Ported " + typeStr,
))
rf.io.write_ports := io.write_ports
val port_issued = Array.fill(numPhysicalReadPorts) { false.B }
val port_addrs = Array.fill(numPhysicalReadPorts) { 0.U(log2Ceil(numRegisters).W) }
val data_sels = Wire(Vec(numLogicalReadPorts , UInt(numPhysicalReadPorts.W)))
data_sels := DontCare
for (i <- 0 until numLogicalReadPorts) {
var read_issued = false.B
for (j <- 0 until numPhysicalReadPorts) {
val issue_read = WireInit(false.B)
val use_port = WireInit(false.B)
when (!read_issued && !port_issued(j) && io.arb_read_reqs(i).valid) {
issue_read := true.B
use_port := true.B
data_sels(i) := UIntToOH(j.U)
}
val was_port_issued_yet = port_issued(j)
port_issued(j) = use_port || port_issued(j)
port_addrs(j) = port_addrs(j) | Mux(was_port_issued_yet || !use_port, 0.U, io.arb_read_reqs(i).bits)
read_issued = issue_read || read_issued
}
io.arb_read_reqs(i).ready := PopCount(io.arb_read_reqs.take(i).map(_.valid)) < numPhysicalReadPorts.U
assert(!(io.arb_read_reqs(i).fire && !read_issued))
}
for (j <- 0 until numPhysicalReadPorts) {
rf.io.arb_read_reqs(j).valid := port_issued(j)
rf.io.arb_read_reqs(j).bits := port_addrs(j)
assert(rf.io.arb_read_reqs(j).ready)
}
val rrd_data_sels = RegNext(data_sels)
for (i <- 0 until numLogicalReadPorts) {
io.rrd_read_resps(i) := Mux1H(rrd_data_sels(i).asBools, rf.io.rrd_read_resps)
}
override def toString: String = rf.toString
}
class FullyPortedRF[T <: Data](
dType: T,
numRegisters: Int,
numReadPorts: Int,
numWritePorts: Int,
typeStr: String,
)(implicit p: Parameters)
extends RegisterFile(dType, numRegisters, numReadPorts, numWritePorts)
{
val rf_cost = (numReadPorts + numWritePorts) * (numReadPorts + 2*numWritePorts)
override def toString: String = BoomCoreStringPrefix(
"==" + typeStr + " Regfile==",
"Num RF Read Ports : " + numReadPorts,
"Num RF Write Ports : " + numWritePorts,
"RF Cost (R+W)*(R+2W) : " + rf_cost)
io.arb_read_reqs.map(p => p.ready := true.B)
val regfile = Mem(numRegisters, dType)
(0 until numReadPorts) map {p => io.rrd_read_resps(p) := regfile(RegNext(io.arb_read_reqs(p).bits)) }
io.write_ports map { p => when (p.valid) { regfile(p.bits.addr) := p.bits.data }}
}
| module PartiallyPortedRF_2( // @[regfile.scala:128:7]
input clock, // @[regfile.scala:128:7]
input reset, // @[regfile.scala:128:7]
input io_arb_read_reqs_0_valid, // @[regfile.scala:31:14]
input [5:0] io_arb_read_reqs_0_bits, // @[regfile.scala:31:14]
input io_arb_read_reqs_1_valid, // @[regfile.scala:31:14]
input [5:0] io_arb_read_reqs_1_bits, // @[regfile.scala:31:14]
input io_arb_read_reqs_2_valid, // @[regfile.scala:31:14]
input [5:0] io_arb_read_reqs_2_bits, // @[regfile.scala:31:14]
input io_arb_read_reqs_3_valid, // @[regfile.scala:31:14]
input [5:0] io_arb_read_reqs_3_bits, // @[regfile.scala:31:14]
output io_arb_read_reqs_4_ready, // @[regfile.scala:31:14]
input io_arb_read_reqs_4_valid, // @[regfile.scala:31:14]
input [5:0] io_arb_read_reqs_4_bits, // @[regfile.scala:31:14]
output io_arb_read_reqs_5_ready, // @[regfile.scala:31:14]
input io_arb_read_reqs_5_valid, // @[regfile.scala:31:14]
input [5:0] io_arb_read_reqs_5_bits, // @[regfile.scala:31:14]
output io_arb_read_reqs_6_ready, // @[regfile.scala:31:14]
input io_arb_read_reqs_6_valid, // @[regfile.scala:31:14]
input [5:0] io_arb_read_reqs_6_bits, // @[regfile.scala:31:14]
output io_arb_read_reqs_7_ready, // @[regfile.scala:31:14]
input io_arb_read_reqs_7_valid, // @[regfile.scala:31:14]
input [5:0] io_arb_read_reqs_7_bits, // @[regfile.scala:31:14]
output io_arb_read_reqs_8_ready, // @[regfile.scala:31:14]
input io_arb_read_reqs_8_valid, // @[regfile.scala:31:14]
input [5:0] io_arb_read_reqs_8_bits, // @[regfile.scala:31:14]
output io_arb_read_reqs_9_ready, // @[regfile.scala:31:14]
input io_arb_read_reqs_9_valid, // @[regfile.scala:31:14]
input [5:0] io_arb_read_reqs_9_bits, // @[regfile.scala:31:14]
output [63:0] io_rrd_read_resps_0, // @[regfile.scala:31:14]
output [63:0] io_rrd_read_resps_1, // @[regfile.scala:31:14]
output [63:0] io_rrd_read_resps_2, // @[regfile.scala:31:14]
output [63:0] io_rrd_read_resps_3, // @[regfile.scala:31:14]
output [63:0] io_rrd_read_resps_4, // @[regfile.scala:31:14]
output [63:0] io_rrd_read_resps_5, // @[regfile.scala:31:14]
output [63:0] io_rrd_read_resps_6, // @[regfile.scala:31:14]
output [63:0] io_rrd_read_resps_7, // @[regfile.scala:31:14]
output [63:0] io_rrd_read_resps_8, // @[regfile.scala:31:14]
output [63:0] io_rrd_read_resps_9, // @[regfile.scala:31:14]
input io_write_ports_0_valid, // @[regfile.scala:31:14]
input [6:0] io_write_ports_0_bits_addr, // @[regfile.scala:31:14]
input [63:0] io_write_ports_0_bits_data, // @[regfile.scala:31:14]
input io_write_ports_1_valid, // @[regfile.scala:31:14]
input [6:0] io_write_ports_1_bits_addr, // @[regfile.scala:31:14]
input [63:0] io_write_ports_1_bits_data, // @[regfile.scala:31:14]
input io_write_ports_2_valid, // @[regfile.scala:31:14]
input [6:0] io_write_ports_2_bits_addr, // @[regfile.scala:31:14]
input [63:0] io_write_ports_2_bits_data, // @[regfile.scala:31:14]
input io_write_ports_3_valid, // @[regfile.scala:31:14]
input [6:0] io_write_ports_3_bits_addr, // @[regfile.scala:31:14]
input [63:0] io_write_ports_3_bits_data, // @[regfile.scala:31:14]
input io_write_ports_4_valid, // @[regfile.scala:31:14]
input [6:0] io_write_ports_4_bits_addr, // @[regfile.scala:31:14]
input [63:0] io_write_ports_4_bits_data // @[regfile.scala:31:14]
);
wire [63:0] _rf_io_rrd_read_resps_0; // @[regfile.scala:138:18]
wire [63:0] _rf_io_rrd_read_resps_1; // @[regfile.scala:138:18]
wire [63:0] _rf_io_rrd_read_resps_2; // @[regfile.scala:138:18]
wire [63:0] _rf_io_rrd_read_resps_3; // @[regfile.scala:138:18]
wire [63:0] _rf_io_rrd_read_resps_4; // @[regfile.scala:138:18]
wire [63:0] _rf_io_rrd_read_resps_5; // @[regfile.scala:138:18]
wire io_arb_read_reqs_0_valid_0 = io_arb_read_reqs_0_valid; // @[regfile.scala:128:7]
wire [5:0] io_arb_read_reqs_0_bits_0 = io_arb_read_reqs_0_bits; // @[regfile.scala:128:7]
wire io_arb_read_reqs_1_valid_0 = io_arb_read_reqs_1_valid; // @[regfile.scala:128:7]
wire [5:0] io_arb_read_reqs_1_bits_0 = io_arb_read_reqs_1_bits; // @[regfile.scala:128:7]
wire io_arb_read_reqs_2_valid_0 = io_arb_read_reqs_2_valid; // @[regfile.scala:128:7]
wire [5:0] io_arb_read_reqs_2_bits_0 = io_arb_read_reqs_2_bits; // @[regfile.scala:128:7]
wire io_arb_read_reqs_3_valid_0 = io_arb_read_reqs_3_valid; // @[regfile.scala:128:7]
wire [5:0] io_arb_read_reqs_3_bits_0 = io_arb_read_reqs_3_bits; // @[regfile.scala:128:7]
wire io_arb_read_reqs_4_valid_0 = io_arb_read_reqs_4_valid; // @[regfile.scala:128:7]
wire [5:0] io_arb_read_reqs_4_bits_0 = io_arb_read_reqs_4_bits; // @[regfile.scala:128:7]
wire io_arb_read_reqs_5_valid_0 = io_arb_read_reqs_5_valid; // @[regfile.scala:128:7]
wire [5:0] io_arb_read_reqs_5_bits_0 = io_arb_read_reqs_5_bits; // @[regfile.scala:128:7]
wire io_arb_read_reqs_6_valid_0 = io_arb_read_reqs_6_valid; // @[regfile.scala:128:7]
wire [5:0] io_arb_read_reqs_6_bits_0 = io_arb_read_reqs_6_bits; // @[regfile.scala:128:7]
wire io_arb_read_reqs_7_valid_0 = io_arb_read_reqs_7_valid; // @[regfile.scala:128:7]
wire [5:0] io_arb_read_reqs_7_bits_0 = io_arb_read_reqs_7_bits; // @[regfile.scala:128:7]
wire io_arb_read_reqs_8_valid_0 = io_arb_read_reqs_8_valid; // @[regfile.scala:128:7]
wire [5:0] io_arb_read_reqs_8_bits_0 = io_arb_read_reqs_8_bits; // @[regfile.scala:128:7]
wire io_arb_read_reqs_9_valid_0 = io_arb_read_reqs_9_valid; // @[regfile.scala:128:7]
wire [5:0] io_arb_read_reqs_9_bits_0 = io_arb_read_reqs_9_bits; // @[regfile.scala:128:7]
wire io_write_ports_0_valid_0 = io_write_ports_0_valid; // @[regfile.scala:128:7]
wire [6:0] io_write_ports_0_bits_addr_0 = io_write_ports_0_bits_addr; // @[regfile.scala:128:7]
wire [63:0] io_write_ports_0_bits_data_0 = io_write_ports_0_bits_data; // @[regfile.scala:128:7]
wire io_write_ports_1_valid_0 = io_write_ports_1_valid; // @[regfile.scala:128:7]
wire [6:0] io_write_ports_1_bits_addr_0 = io_write_ports_1_bits_addr; // @[regfile.scala:128:7]
wire [63:0] io_write_ports_1_bits_data_0 = io_write_ports_1_bits_data; // @[regfile.scala:128:7]
wire io_write_ports_2_valid_0 = io_write_ports_2_valid; // @[regfile.scala:128:7]
wire [6:0] io_write_ports_2_bits_addr_0 = io_write_ports_2_bits_addr; // @[regfile.scala:128:7]
wire [63:0] io_write_ports_2_bits_data_0 = io_write_ports_2_bits_data; // @[regfile.scala:128:7]
wire io_write_ports_3_valid_0 = io_write_ports_3_valid; // @[regfile.scala:128:7]
wire [6:0] io_write_ports_3_bits_addr_0 = io_write_ports_3_bits_addr; // @[regfile.scala:128:7]
wire [63:0] io_write_ports_3_bits_data_0 = io_write_ports_3_bits_data; // @[regfile.scala:128:7]
wire io_write_ports_4_valid_0 = io_write_ports_4_valid; // @[regfile.scala:128:7]
wire [6:0] io_write_ports_4_bits_addr_0 = io_write_ports_4_bits_addr; // @[regfile.scala:128:7]
wire [63:0] io_write_ports_4_bits_data_0 = io_write_ports_4_bits_data; // @[regfile.scala:128:7]
wire io_arb_read_reqs_0_ready = 1'h1; // @[regfile.scala:128:7]
wire io_arb_read_reqs_1_ready = 1'h1; // @[regfile.scala:128:7]
wire io_arb_read_reqs_2_ready = 1'h1; // @[regfile.scala:128:7]
wire io_arb_read_reqs_3_ready = 1'h1; // @[regfile.scala:128:7]
wire _io_arb_read_reqs_0_ready_T = 1'h1; // @[regfile.scala:167:82]
wire _io_arb_read_reqs_1_ready_T = 1'h1; // @[regfile.scala:167:82]
wire _io_arb_read_reqs_2_ready_T_2 = 1'h1; // @[regfile.scala:167:82]
wire _io_arb_read_reqs_3_ready_T_4 = 1'h1; // @[regfile.scala:167:82]
wire [7:0] _data_sels_0_T_5 = 8'h20; // @[OneHot.scala:58:35]
wire [7:0] _data_sels_1_T_5 = 8'h20; // @[OneHot.scala:58:35]
wire [7:0] _data_sels_2_T_5 = 8'h20; // @[OneHot.scala:58:35]
wire [7:0] _data_sels_3_T_5 = 8'h20; // @[OneHot.scala:58:35]
wire [7:0] _data_sels_4_T_5 = 8'h20; // @[OneHot.scala:58:35]
wire [7:0] _data_sels_5_T_5 = 8'h20; // @[OneHot.scala:58:35]
wire [7:0] _data_sels_6_T_5 = 8'h20; // @[OneHot.scala:58:35]
wire [7:0] _data_sels_7_T_5 = 8'h20; // @[OneHot.scala:58:35]
wire [7:0] _data_sels_8_T_5 = 8'h20; // @[OneHot.scala:58:35]
wire [7:0] _data_sels_9_T_5 = 8'h20; // @[OneHot.scala:58:35]
wire [7:0] _data_sels_0_T_4 = 8'h10; // @[OneHot.scala:58:35]
wire [7:0] _data_sels_1_T_4 = 8'h10; // @[OneHot.scala:58:35]
wire [7:0] _data_sels_2_T_4 = 8'h10; // @[OneHot.scala:58:35]
wire [7:0] _data_sels_3_T_4 = 8'h10; // @[OneHot.scala:58:35]
wire [7:0] _data_sels_4_T_4 = 8'h10; // @[OneHot.scala:58:35]
wire [7:0] _data_sels_5_T_4 = 8'h10; // @[OneHot.scala:58:35]
wire [7:0] _data_sels_6_T_4 = 8'h10; // @[OneHot.scala:58:35]
wire [7:0] _data_sels_7_T_4 = 8'h10; // @[OneHot.scala:58:35]
wire [7:0] _data_sels_8_T_4 = 8'h10; // @[OneHot.scala:58:35]
wire [7:0] _data_sels_9_T_4 = 8'h10; // @[OneHot.scala:58:35]
wire [3:0] _data_sels_0_T_3 = 4'h8; // @[OneHot.scala:58:35]
wire [3:0] _data_sels_1_T_3 = 4'h8; // @[OneHot.scala:58:35]
wire [3:0] _data_sels_2_T_3 = 4'h8; // @[OneHot.scala:58:35]
wire [3:0] _data_sels_3_T_3 = 4'h8; // @[OneHot.scala:58:35]
wire [3:0] _data_sels_4_T_3 = 4'h8; // @[OneHot.scala:58:35]
wire [3:0] _data_sels_5_T_3 = 4'h8; // @[OneHot.scala:58:35]
wire [3:0] _data_sels_6_T_3 = 4'h8; // @[OneHot.scala:58:35]
wire [3:0] _data_sels_7_T_3 = 4'h8; // @[OneHot.scala:58:35]
wire [3:0] _data_sels_8_T_3 = 4'h8; // @[OneHot.scala:58:35]
wire [3:0] _data_sels_9_T_3 = 4'h8; // @[OneHot.scala:58:35]
wire [3:0] _data_sels_0_T_2 = 4'h4; // @[OneHot.scala:58:35]
wire [3:0] _data_sels_1_T_2 = 4'h4; // @[OneHot.scala:58:35]
wire [3:0] _data_sels_2_T_2 = 4'h4; // @[OneHot.scala:58:35]
wire [3:0] _data_sels_3_T_2 = 4'h4; // @[OneHot.scala:58:35]
wire [3:0] _data_sels_4_T_2 = 4'h4; // @[OneHot.scala:58:35]
wire [3:0] _data_sels_5_T_2 = 4'h4; // @[OneHot.scala:58:35]
wire [3:0] _data_sels_6_T_2 = 4'h4; // @[OneHot.scala:58:35]
wire [3:0] _data_sels_7_T_2 = 4'h4; // @[OneHot.scala:58:35]
wire [3:0] _data_sels_8_T_2 = 4'h4; // @[OneHot.scala:58:35]
wire [3:0] _data_sels_9_T_2 = 4'h4; // @[OneHot.scala:58:35]
wire [1:0] _data_sels_0_T_1 = 2'h2; // @[OneHot.scala:58:35]
wire [1:0] _data_sels_1_T_1 = 2'h2; // @[OneHot.scala:58:35]
wire [1:0] _data_sels_2_T_1 = 2'h2; // @[OneHot.scala:58:35]
wire [1:0] _data_sels_3_T_1 = 2'h2; // @[OneHot.scala:58:35]
wire [1:0] _data_sels_4_T_1 = 2'h2; // @[OneHot.scala:58:35]
wire [1:0] _data_sels_5_T_1 = 2'h2; // @[OneHot.scala:58:35]
wire [1:0] _data_sels_6_T_1 = 2'h2; // @[OneHot.scala:58:35]
wire [1:0] _data_sels_7_T_1 = 2'h2; // @[OneHot.scala:58:35]
wire [1:0] _data_sels_8_T_1 = 2'h2; // @[OneHot.scala:58:35]
wire [1:0] _data_sels_9_T_1 = 2'h2; // @[OneHot.scala:58:35]
wire [1:0] _data_sels_0_T = 2'h1; // @[OneHot.scala:58:35]
wire [1:0] _data_sels_1_T = 2'h1; // @[OneHot.scala:58:35]
wire [1:0] _data_sels_2_T = 2'h1; // @[OneHot.scala:58:35]
wire [1:0] _data_sels_3_T = 2'h1; // @[OneHot.scala:58:35]
wire [1:0] _data_sels_4_T = 2'h1; // @[OneHot.scala:58:35]
wire [1:0] _data_sels_5_T = 2'h1; // @[OneHot.scala:58:35]
wire [1:0] _data_sels_6_T = 2'h1; // @[OneHot.scala:58:35]
wire [1:0] _data_sels_7_T = 2'h1; // @[OneHot.scala:58:35]
wire [1:0] _data_sels_8_T = 2'h1; // @[OneHot.scala:58:35]
wire [1:0] _data_sels_9_T = 2'h1; // @[OneHot.scala:58:35]
wire issue_read = io_arb_read_reqs_0_valid_0; // @[regfile.scala:128:7, :155:32]
wire use_port = io_arb_read_reqs_0_valid_0; // @[regfile.scala:128:7, :156:30]
wire _io_arb_read_reqs_4_ready_T_6; // @[regfile.scala:167:82]
wire _io_arb_read_reqs_5_ready_T_8; // @[regfile.scala:167:82]
wire _io_arb_read_reqs_6_ready_T_10; // @[regfile.scala:167:82]
wire _io_arb_read_reqs_7_ready_T_12; // @[regfile.scala:167:82]
wire _io_arb_read_reqs_8_ready_T_14; // @[regfile.scala:167:82]
wire _io_arb_read_reqs_9_ready_T_16; // @[regfile.scala:167:82]
wire [63:0] _io_rrd_read_resps_0_WIRE; // @[Mux.scala:30:73]
wire [63:0] _io_rrd_read_resps_1_WIRE; // @[Mux.scala:30:73]
wire [63:0] _io_rrd_read_resps_2_WIRE; // @[Mux.scala:30:73]
wire [63:0] _io_rrd_read_resps_3_WIRE; // @[Mux.scala:30:73]
wire [63:0] _io_rrd_read_resps_4_WIRE; // @[Mux.scala:30:73]
wire [63:0] _io_rrd_read_resps_5_WIRE; // @[Mux.scala:30:73]
wire [63:0] _io_rrd_read_resps_6_WIRE; // @[Mux.scala:30:73]
wire [63:0] _io_rrd_read_resps_7_WIRE; // @[Mux.scala:30:73]
wire [63:0] _io_rrd_read_resps_8_WIRE; // @[Mux.scala:30:73]
wire [63:0] _io_rrd_read_resps_9_WIRE; // @[Mux.scala:30:73]
wire io_arb_read_reqs_4_ready_0; // @[regfile.scala:128:7]
wire io_arb_read_reqs_5_ready_0; // @[regfile.scala:128:7]
wire io_arb_read_reqs_6_ready_0; // @[regfile.scala:128:7]
wire io_arb_read_reqs_7_ready_0; // @[regfile.scala:128:7]
wire io_arb_read_reqs_8_ready_0; // @[regfile.scala:128:7]
wire io_arb_read_reqs_9_ready_0; // @[regfile.scala:128:7]
wire [63:0] io_rrd_read_resps_0_0; // @[regfile.scala:128:7]
wire [63:0] io_rrd_read_resps_1_0; // @[regfile.scala:128:7]
wire [63:0] io_rrd_read_resps_2_0; // @[regfile.scala:128:7]
wire [63:0] io_rrd_read_resps_3_0; // @[regfile.scala:128:7]
wire [63:0] io_rrd_read_resps_4_0; // @[regfile.scala:128:7]
wire [63:0] io_rrd_read_resps_5_0; // @[regfile.scala:128:7]
wire [63:0] io_rrd_read_resps_6_0; // @[regfile.scala:128:7]
wire [63:0] io_rrd_read_resps_7_0; // @[regfile.scala:128:7]
wire [63:0] io_rrd_read_resps_8_0; // @[regfile.scala:128:7]
wire [63:0] io_rrd_read_resps_9_0; // @[regfile.scala:128:7]
wire [5:0] data_sels_0; // @[regfile.scala:149:25]
wire [5:0] data_sels_1; // @[regfile.scala:149:25]
wire [5:0] data_sels_2; // @[regfile.scala:149:25]
wire [5:0] data_sels_3; // @[regfile.scala:149:25]
wire [5:0] data_sels_4; // @[regfile.scala:149:25]
wire [5:0] data_sels_5; // @[regfile.scala:149:25]
wire [5:0] data_sels_6; // @[regfile.scala:149:25]
wire [5:0] data_sels_7; // @[regfile.scala:149:25]
wire [5:0] data_sels_8; // @[regfile.scala:149:25]
wire [5:0] data_sels_9; // @[regfile.scala:149:25]
wire issue_read_1; // @[regfile.scala:155:32]
wire use_port_1; // @[regfile.scala:156:30]
wire _T_93 = ~issue_read & io_arb_read_reqs_0_valid_0; // @[regfile.scala:128:7, :155:32, :157:{13,45}]
assign issue_read_1 = _T_93; // @[regfile.scala:155:32, :157:45]
assign use_port_1 = _T_93; // @[regfile.scala:156:30, :157:45]
wire _T_99 = issue_read_1 | issue_read; // @[regfile.scala:155:32, :165:32]
wire issue_read_2; // @[regfile.scala:155:32]
wire use_port_2; // @[regfile.scala:156:30]
wire _T_103 = ~_T_99 & io_arb_read_reqs_0_valid_0; // @[regfile.scala:128:7, :157:{13,45}, :165:32]
assign issue_read_2 = _T_103; // @[regfile.scala:155:32, :157:45]
assign use_port_2 = _T_103; // @[regfile.scala:156:30, :157:45]
wire _T_109 = issue_read_2 | _T_99; // @[regfile.scala:155:32, :165:32]
wire issue_read_3; // @[regfile.scala:155:32]
wire use_port_3; // @[regfile.scala:156:30]
wire _T_113 = ~_T_109 & io_arb_read_reqs_0_valid_0; // @[regfile.scala:128:7, :157:{13,45}, :165:32]
assign issue_read_3 = _T_113; // @[regfile.scala:155:32, :157:45]
assign use_port_3 = _T_113; // @[regfile.scala:156:30, :157:45]
wire _T_119 = issue_read_3 | _T_109; // @[regfile.scala:155:32, :165:32]
wire issue_read_4; // @[regfile.scala:155:32]
wire use_port_4; // @[regfile.scala:156:30]
wire _T_123 = ~_T_119 & io_arb_read_reqs_0_valid_0; // @[regfile.scala:128:7, :157:{13,45}, :165:32]
assign issue_read_4 = _T_123; // @[regfile.scala:155:32, :157:45]
assign use_port_4 = _T_123; // @[regfile.scala:156:30, :157:45]
wire _T_129 = issue_read_4 | _T_119; // @[regfile.scala:155:32, :165:32]
wire issue_read_5; // @[regfile.scala:155:32]
wire use_port_5; // @[regfile.scala:156:30]
wire _T_133 = ~_T_129 & io_arb_read_reqs_0_valid_0; // @[regfile.scala:128:7, :157:{13,45}, :165:32]
assign issue_read_5 = _T_133; // @[regfile.scala:155:32, :157:45]
assign use_port_5 = _T_133; // @[regfile.scala:156:30, :157:45]
assign data_sels_0 = _T_133 ? 6'h20 : _T_123 ? 6'h10 : _T_113 ? 6'h8 : _T_103 ? 6'h4 : _T_93 ? 6'h2 : 6'h1; // @[regfile.scala:149:25, :157:{45,75}, :160:22]
wire issue_read_6; // @[regfile.scala:155:32]
wire use_port_6; // @[regfile.scala:156:30]
wire _T_150 = ~use_port & io_arb_read_reqs_1_valid_0; // @[regfile.scala:128:7, :156:30, :157:{29,45}]
assign issue_read_6 = _T_150; // @[regfile.scala:155:32, :157:45]
assign use_port_6 = _T_150; // @[regfile.scala:156:30, :157:45]
wire _T_151 = use_port_6 | use_port; // @[regfile.scala:156:30, :163:33]
wire issue_read_7; // @[regfile.scala:155:32]
wire use_port_7; // @[regfile.scala:156:30]
wire _T_160 = ~issue_read_6 & ~use_port_1 & io_arb_read_reqs_1_valid_0; // @[regfile.scala:128:7, :155:32, :156:30, :157:{13,26,29,45}]
assign issue_read_7 = _T_160; // @[regfile.scala:155:32, :157:{26,45}]
assign use_port_7 = _T_160; // @[regfile.scala:156:30, :157:{26,45}]
wire _T_161 = use_port_7 | use_port_1; // @[regfile.scala:156:30, :163:33]
wire _T_166 = issue_read_7 | issue_read_6; // @[regfile.scala:155:32, :165:32]
wire issue_read_8; // @[regfile.scala:155:32]
wire use_port_8; // @[regfile.scala:156:30]
wire _T_170 = ~_T_166 & ~use_port_2 & io_arb_read_reqs_1_valid_0; // @[regfile.scala:128:7, :156:30, :157:{13,26,29,45}, :165:32]
assign issue_read_8 = _T_170; // @[regfile.scala:155:32, :157:{26,45}]
assign use_port_8 = _T_170; // @[regfile.scala:156:30, :157:{26,45}]
wire _T_171 = use_port_8 | use_port_2; // @[regfile.scala:156:30, :163:33]
wire _T_176 = issue_read_8 | _T_166; // @[regfile.scala:155:32, :165:32]
wire issue_read_9; // @[regfile.scala:155:32]
wire use_port_9; // @[regfile.scala:156:30]
wire _T_180 = ~_T_176 & ~use_port_3 & io_arb_read_reqs_1_valid_0; // @[regfile.scala:128:7, :156:30, :157:{13,26,29,45}, :165:32]
assign issue_read_9 = _T_180; // @[regfile.scala:155:32, :157:{26,45}]
assign use_port_9 = _T_180; // @[regfile.scala:156:30, :157:{26,45}]
wire _T_181 = use_port_9 | use_port_3; // @[regfile.scala:156:30, :163:33]
wire _T_186 = issue_read_9 | _T_176; // @[regfile.scala:155:32, :165:32]
wire issue_read_10; // @[regfile.scala:155:32]
wire use_port_10; // @[regfile.scala:156:30]
wire _T_190 = ~_T_186 & ~use_port_4 & io_arb_read_reqs_1_valid_0; // @[regfile.scala:128:7, :156:30, :157:{13,26,29,45}, :165:32]
assign issue_read_10 = _T_190; // @[regfile.scala:155:32, :157:{26,45}]
assign use_port_10 = _T_190; // @[regfile.scala:156:30, :157:{26,45}]
wire _T_191 = use_port_10 | use_port_4; // @[regfile.scala:156:30, :163:33]
wire _T_196 = issue_read_10 | _T_186; // @[regfile.scala:155:32, :165:32]
wire issue_read_11; // @[regfile.scala:155:32]
wire use_port_11; // @[regfile.scala:156:30]
wire _T_200 = ~_T_196 & ~use_port_5 & io_arb_read_reqs_1_valid_0; // @[regfile.scala:128:7, :156:30, :157:{13,26,29,45}, :165:32]
assign issue_read_11 = _T_200; // @[regfile.scala:155:32, :157:{26,45}]
assign use_port_11 = _T_200; // @[regfile.scala:156:30, :157:{26,45}]
assign data_sels_1 = _T_200 ? 6'h20 : _T_190 ? 6'h10 : _T_180 ? 6'h8 : _T_170 ? 6'h4 : _T_160 ? 6'h2 : 6'h1; // @[regfile.scala:149:25, :157:{26,45,75}, :160:22]
wire _T_201 = use_port_11 | use_port_5; // @[regfile.scala:156:30, :163:33]
wire issue_read_12; // @[regfile.scala:155:32]
wire use_port_12; // @[regfile.scala:156:30]
wire _T_217 = ~_T_151 & io_arb_read_reqs_2_valid_0; // @[regfile.scala:128:7, :157:{29,45}, :163:33]
assign issue_read_12 = _T_217; // @[regfile.scala:155:32, :157:45]
assign use_port_12 = _T_217; // @[regfile.scala:156:30, :157:45]
wire _T_218 = use_port_12 | _T_151; // @[regfile.scala:156:30, :163:33]
wire issue_read_13; // @[regfile.scala:155:32]
wire use_port_13; // @[regfile.scala:156:30]
wire _T_227 = ~issue_read_12 & ~_T_161 & io_arb_read_reqs_2_valid_0; // @[regfile.scala:128:7, :155:32, :157:{13,26,29,45}, :163:33]
assign issue_read_13 = _T_227; // @[regfile.scala:155:32, :157:{26,45}]
assign use_port_13 = _T_227; // @[regfile.scala:156:30, :157:{26,45}]
wire _T_228 = use_port_13 | _T_161; // @[regfile.scala:156:30, :163:33]
wire _T_233 = issue_read_13 | issue_read_12; // @[regfile.scala:155:32, :165:32]
wire issue_read_14; // @[regfile.scala:155:32]
wire use_port_14; // @[regfile.scala:156:30]
wire _T_237 = ~_T_233 & ~_T_171 & io_arb_read_reqs_2_valid_0; // @[regfile.scala:128:7, :157:{13,26,29,45}, :163:33, :165:32]
assign issue_read_14 = _T_237; // @[regfile.scala:155:32, :157:{26,45}]
assign use_port_14 = _T_237; // @[regfile.scala:156:30, :157:{26,45}]
wire _T_238 = use_port_14 | _T_171; // @[regfile.scala:156:30, :163:33]
wire _T_243 = issue_read_14 | _T_233; // @[regfile.scala:155:32, :165:32]
wire issue_read_15; // @[regfile.scala:155:32]
wire use_port_15; // @[regfile.scala:156:30]
wire _T_247 = ~_T_243 & ~_T_181 & io_arb_read_reqs_2_valid_0; // @[regfile.scala:128:7, :157:{13,26,29,45}, :163:33, :165:32]
assign issue_read_15 = _T_247; // @[regfile.scala:155:32, :157:{26,45}]
assign use_port_15 = _T_247; // @[regfile.scala:156:30, :157:{26,45}]
wire _T_248 = use_port_15 | _T_181; // @[regfile.scala:156:30, :163:33]
wire _T_253 = issue_read_15 | _T_243; // @[regfile.scala:155:32, :165:32]
wire issue_read_16; // @[regfile.scala:155:32]
wire use_port_16; // @[regfile.scala:156:30]
wire _T_257 = ~_T_253 & ~_T_191 & io_arb_read_reqs_2_valid_0; // @[regfile.scala:128:7, :157:{13,26,29,45}, :163:33, :165:32]
assign issue_read_16 = _T_257; // @[regfile.scala:155:32, :157:{26,45}]
assign use_port_16 = _T_257; // @[regfile.scala:156:30, :157:{26,45}]
wire _T_258 = use_port_16 | _T_191; // @[regfile.scala:156:30, :163:33]
wire _T_263 = issue_read_16 | _T_253; // @[regfile.scala:155:32, :165:32]
wire issue_read_17; // @[regfile.scala:155:32]
wire use_port_17; // @[regfile.scala:156:30]
wire _T_267 = ~_T_263 & ~_T_201 & io_arb_read_reqs_2_valid_0; // @[regfile.scala:128:7, :157:{13,26,29,45}, :163:33, :165:32]
assign issue_read_17 = _T_267; // @[regfile.scala:155:32, :157:{26,45}]
assign use_port_17 = _T_267; // @[regfile.scala:156:30, :157:{26,45}]
assign data_sels_2 = _T_267 ? 6'h20 : _T_257 ? 6'h10 : _T_247 ? 6'h8 : _T_237 ? 6'h4 : _T_227 ? 6'h2 : 6'h1; // @[regfile.scala:149:25, :157:{26,45,75}, :160:22]
wire _T_268 = use_port_17 | _T_201; // @[regfile.scala:156:30, :163:33]
wire [1:0] _GEN = {1'h0, io_arb_read_reqs_1_valid_0}; // @[regfile.scala:128:7, :167:42]
wire [1:0] _GEN_0 = {1'h0, io_arb_read_reqs_0_valid_0} + _GEN; // @[regfile.scala:128:7, :167:42]
wire [1:0] _io_arb_read_reqs_2_ready_T; // @[regfile.scala:167:42]
assign _io_arb_read_reqs_2_ready_T = _GEN_0; // @[regfile.scala:167:42]
wire [1:0] _io_arb_read_reqs_4_ready_T; // @[regfile.scala:167:42]
assign _io_arb_read_reqs_4_ready_T = _GEN_0; // @[regfile.scala:167:42]
wire [1:0] _io_arb_read_reqs_5_ready_T; // @[regfile.scala:167:42]
assign _io_arb_read_reqs_5_ready_T = _GEN_0; // @[regfile.scala:167:42]
wire [1:0] _io_arb_read_reqs_8_ready_T; // @[regfile.scala:167:42]
assign _io_arb_read_reqs_8_ready_T = _GEN_0; // @[regfile.scala:167:42]
wire [1:0] _io_arb_read_reqs_9_ready_T; // @[regfile.scala:167:42]
assign _io_arb_read_reqs_9_ready_T = _GEN_0; // @[regfile.scala:167:42]
wire [1:0] _io_arb_read_reqs_2_ready_T_1 = _io_arb_read_reqs_2_ready_T; // @[regfile.scala:167:42]
wire issue_read_18; // @[regfile.scala:155:32]
wire use_port_18; // @[regfile.scala:156:30]
wire _T_284 = ~_T_218 & io_arb_read_reqs_3_valid_0; // @[regfile.scala:128:7, :157:{29,45}, :163:33]
assign issue_read_18 = _T_284; // @[regfile.scala:155:32, :157:45]
assign use_port_18 = _T_284; // @[regfile.scala:156:30, :157:45]
wire _T_285 = use_port_18 | _T_218; // @[regfile.scala:156:30, :163:33]
wire issue_read_19; // @[regfile.scala:155:32]
wire use_port_19; // @[regfile.scala:156:30]
wire _T_294 = ~issue_read_18 & ~_T_228 & io_arb_read_reqs_3_valid_0; // @[regfile.scala:128:7, :155:32, :157:{13,26,29,45}, :163:33]
assign issue_read_19 = _T_294; // @[regfile.scala:155:32, :157:{26,45}]
assign use_port_19 = _T_294; // @[regfile.scala:156:30, :157:{26,45}]
wire _T_295 = use_port_19 | _T_228; // @[regfile.scala:156:30, :163:33]
wire _T_300 = issue_read_19 | issue_read_18; // @[regfile.scala:155:32, :165:32]
wire issue_read_20; // @[regfile.scala:155:32]
wire use_port_20; // @[regfile.scala:156:30]
wire _T_304 = ~_T_300 & ~_T_238 & io_arb_read_reqs_3_valid_0; // @[regfile.scala:128:7, :157:{13,26,29,45}, :163:33, :165:32]
assign issue_read_20 = _T_304; // @[regfile.scala:155:32, :157:{26,45}]
assign use_port_20 = _T_304; // @[regfile.scala:156:30, :157:{26,45}]
wire _T_305 = use_port_20 | _T_238; // @[regfile.scala:156:30, :163:33]
wire _T_310 = issue_read_20 | _T_300; // @[regfile.scala:155:32, :165:32]
wire issue_read_21; // @[regfile.scala:155:32]
wire use_port_21; // @[regfile.scala:156:30]
wire _T_314 = ~_T_310 & ~_T_248 & io_arb_read_reqs_3_valid_0; // @[regfile.scala:128:7, :157:{13,26,29,45}, :163:33, :165:32]
assign issue_read_21 = _T_314; // @[regfile.scala:155:32, :157:{26,45}]
assign use_port_21 = _T_314; // @[regfile.scala:156:30, :157:{26,45}]
wire _T_315 = use_port_21 | _T_248; // @[regfile.scala:156:30, :163:33]
wire _T_320 = issue_read_21 | _T_310; // @[regfile.scala:155:32, :165:32]
wire issue_read_22; // @[regfile.scala:155:32]
wire use_port_22; // @[regfile.scala:156:30]
wire _T_324 = ~_T_320 & ~_T_258 & io_arb_read_reqs_3_valid_0; // @[regfile.scala:128:7, :157:{13,26,29,45}, :163:33, :165:32]
assign issue_read_22 = _T_324; // @[regfile.scala:155:32, :157:{26,45}]
assign use_port_22 = _T_324; // @[regfile.scala:156:30, :157:{26,45}]
wire _T_325 = use_port_22 | _T_258; // @[regfile.scala:156:30, :163:33]
wire _T_330 = issue_read_22 | _T_320; // @[regfile.scala:155:32, :165:32]
wire issue_read_23; // @[regfile.scala:155:32]
wire use_port_23; // @[regfile.scala:156:30]
wire _T_334 = ~_T_330 & ~_T_268 & io_arb_read_reqs_3_valid_0; // @[regfile.scala:128:7, :157:{13,26,29,45}, :163:33, :165:32]
assign issue_read_23 = _T_334; // @[regfile.scala:155:32, :157:{26,45}]
assign use_port_23 = _T_334; // @[regfile.scala:156:30, :157:{26,45}]
assign data_sels_3 = _T_334 ? 6'h20 : _T_324 ? 6'h10 : _T_314 ? 6'h8 : _T_304 ? 6'h4 : _T_294 ? 6'h2 : 6'h1; // @[regfile.scala:149:25, :157:{26,45,75}, :160:22]
wire _T_335 = use_port_23 | _T_268; // @[regfile.scala:156:30, :163:33]
wire [1:0] _GEN_1 = {1'h0, io_arb_read_reqs_2_valid_0}; // @[regfile.scala:128:7, :167:42]
wire [1:0] _GEN_2 = _GEN + _GEN_1; // @[regfile.scala:167:42]
wire [1:0] _io_arb_read_reqs_3_ready_T; // @[regfile.scala:167:42]
assign _io_arb_read_reqs_3_ready_T = _GEN_2; // @[regfile.scala:167:42]
wire [1:0] _io_arb_read_reqs_6_ready_T; // @[regfile.scala:167:42]
assign _io_arb_read_reqs_6_ready_T = _GEN_2; // @[regfile.scala:167:42]
wire [1:0] _io_arb_read_reqs_7_ready_T; // @[regfile.scala:167:42]
assign _io_arb_read_reqs_7_ready_T = _GEN_2; // @[regfile.scala:167:42]
wire [1:0] _io_arb_read_reqs_3_ready_T_1 = _io_arb_read_reqs_3_ready_T; // @[regfile.scala:167:42]
wire [2:0] _GEN_3 = {2'h0, io_arb_read_reqs_0_valid_0}; // @[regfile.scala:128:7, :167:42]
wire [2:0] _io_arb_read_reqs_3_ready_T_2 = _GEN_3 + {1'h0, _io_arb_read_reqs_3_ready_T_1}; // @[regfile.scala:167:42]
wire [1:0] _io_arb_read_reqs_3_ready_T_3 = _io_arb_read_reqs_3_ready_T_2[1:0]; // @[regfile.scala:167:42]
wire issue_read_24; // @[regfile.scala:155:32]
wire use_port_24; // @[regfile.scala:156:30]
wire _T_351 = ~_T_285 & io_arb_read_reqs_4_valid_0; // @[regfile.scala:128:7, :157:{29,45}, :163:33]
assign issue_read_24 = _T_351; // @[regfile.scala:155:32, :157:45]
assign use_port_24 = _T_351; // @[regfile.scala:156:30, :157:45]
wire _T_352 = use_port_24 | _T_285; // @[regfile.scala:156:30, :163:33]
wire issue_read_25; // @[regfile.scala:155:32]
wire use_port_25; // @[regfile.scala:156:30]
wire _T_361 = ~issue_read_24 & ~_T_295 & io_arb_read_reqs_4_valid_0; // @[regfile.scala:128:7, :155:32, :157:{13,26,29,45}, :163:33]
assign issue_read_25 = _T_361; // @[regfile.scala:155:32, :157:{26,45}]
assign use_port_25 = _T_361; // @[regfile.scala:156:30, :157:{26,45}]
wire _T_362 = use_port_25 | _T_295; // @[regfile.scala:156:30, :163:33]
wire _T_367 = issue_read_25 | issue_read_24; // @[regfile.scala:155:32, :165:32]
wire issue_read_26; // @[regfile.scala:155:32]
wire use_port_26; // @[regfile.scala:156:30]
wire _T_371 = ~_T_367 & ~_T_305 & io_arb_read_reqs_4_valid_0; // @[regfile.scala:128:7, :157:{13,26,29,45}, :163:33, :165:32]
assign issue_read_26 = _T_371; // @[regfile.scala:155:32, :157:{26,45}]
assign use_port_26 = _T_371; // @[regfile.scala:156:30, :157:{26,45}]
wire _T_372 = use_port_26 | _T_305; // @[regfile.scala:156:30, :163:33]
wire _T_377 = issue_read_26 | _T_367; // @[regfile.scala:155:32, :165:32]
wire issue_read_27; // @[regfile.scala:155:32]
wire use_port_27; // @[regfile.scala:156:30]
wire _T_381 = ~_T_377 & ~_T_315 & io_arb_read_reqs_4_valid_0; // @[regfile.scala:128:7, :157:{13,26,29,45}, :163:33, :165:32]
assign issue_read_27 = _T_381; // @[regfile.scala:155:32, :157:{26,45}]
assign use_port_27 = _T_381; // @[regfile.scala:156:30, :157:{26,45}]
wire _T_382 = use_port_27 | _T_315; // @[regfile.scala:156:30, :163:33]
wire _T_387 = issue_read_27 | _T_377; // @[regfile.scala:155:32, :165:32]
wire issue_read_28; // @[regfile.scala:155:32]
wire use_port_28; // @[regfile.scala:156:30]
wire _T_391 = ~_T_387 & ~_T_325 & io_arb_read_reqs_4_valid_0; // @[regfile.scala:128:7, :157:{13,26,29,45}, :163:33, :165:32]
assign issue_read_28 = _T_391; // @[regfile.scala:155:32, :157:{26,45}]
assign use_port_28 = _T_391; // @[regfile.scala:156:30, :157:{26,45}]
wire _T_392 = use_port_28 | _T_325; // @[regfile.scala:156:30, :163:33]
wire _T_397 = issue_read_28 | _T_387; // @[regfile.scala:155:32, :165:32]
wire issue_read_29; // @[regfile.scala:155:32]
wire use_port_29; // @[regfile.scala:156:30]
wire _T_401 = ~_T_397 & ~_T_335 & io_arb_read_reqs_4_valid_0; // @[regfile.scala:128:7, :157:{13,26,29,45}, :163:33, :165:32]
assign issue_read_29 = _T_401; // @[regfile.scala:155:32, :157:{26,45}]
assign use_port_29 = _T_401; // @[regfile.scala:156:30, :157:{26,45}]
assign data_sels_4 = _T_401 ? 6'h20 : _T_391 ? 6'h10 : _T_381 ? 6'h8 : _T_371 ? 6'h4 : _T_361 ? 6'h2 : 6'h1; // @[regfile.scala:149:25, :157:{26,45,75}, :160:22]
wire _T_402 = use_port_29 | _T_335; // @[regfile.scala:156:30, :163:33]
wire [1:0] _io_arb_read_reqs_4_ready_T_1 = _io_arb_read_reqs_4_ready_T; // @[regfile.scala:167:42]
wire [1:0] _GEN_4 = {1'h0, io_arb_read_reqs_3_valid_0}; // @[regfile.scala:128:7, :167:42]
wire [1:0] _GEN_5 = _GEN_1 + _GEN_4; // @[regfile.scala:167:42]
wire [1:0] _io_arb_read_reqs_4_ready_T_2; // @[regfile.scala:167:42]
assign _io_arb_read_reqs_4_ready_T_2 = _GEN_5; // @[regfile.scala:167:42]
wire [1:0] _io_arb_read_reqs_8_ready_T_2; // @[regfile.scala:167:42]
assign _io_arb_read_reqs_8_ready_T_2 = _GEN_5; // @[regfile.scala:167:42]
wire [1:0] _io_arb_read_reqs_9_ready_T_2; // @[regfile.scala:167:42]
assign _io_arb_read_reqs_9_ready_T_2 = _GEN_5; // @[regfile.scala:167:42]
wire [1:0] _io_arb_read_reqs_4_ready_T_3 = _io_arb_read_reqs_4_ready_T_2; // @[regfile.scala:167:42]
wire [2:0] _io_arb_read_reqs_4_ready_T_4 = {1'h0, _io_arb_read_reqs_4_ready_T_1} + {1'h0, _io_arb_read_reqs_4_ready_T_3}; // @[regfile.scala:167:42]
wire [2:0] _io_arb_read_reqs_4_ready_T_5 = _io_arb_read_reqs_4_ready_T_4; // @[regfile.scala:167:42]
assign _io_arb_read_reqs_4_ready_T_6 = _io_arb_read_reqs_4_ready_T_5[2:1] != 2'h3; // @[regfile.scala:167:{42,82}]
assign io_arb_read_reqs_4_ready_0 = _io_arb_read_reqs_4_ready_T_6; // @[regfile.scala:128:7, :167:82]
wire issue_read_30; // @[regfile.scala:155:32]
wire use_port_30; // @[regfile.scala:156:30]
wire _T_418 = ~_T_352 & io_arb_read_reqs_5_valid_0; // @[regfile.scala:128:7, :157:{29,45}, :163:33]
assign issue_read_30 = _T_418; // @[regfile.scala:155:32, :157:45]
assign use_port_30 = _T_418; // @[regfile.scala:156:30, :157:45]
wire _T_419 = use_port_30 | _T_352; // @[regfile.scala:156:30, :163:33]
wire issue_read_31; // @[regfile.scala:155:32]
wire use_port_31; // @[regfile.scala:156:30]
wire _T_428 = ~issue_read_30 & ~_T_362 & io_arb_read_reqs_5_valid_0; // @[regfile.scala:128:7, :155:32, :157:{13,26,29,45}, :163:33]
assign issue_read_31 = _T_428; // @[regfile.scala:155:32, :157:{26,45}]
assign use_port_31 = _T_428; // @[regfile.scala:156:30, :157:{26,45}]
wire _T_429 = use_port_31 | _T_362; // @[regfile.scala:156:30, :163:33]
wire _T_434 = issue_read_31 | issue_read_30; // @[regfile.scala:155:32, :165:32]
wire issue_read_32; // @[regfile.scala:155:32]
wire use_port_32; // @[regfile.scala:156:30]
wire _T_438 = ~_T_434 & ~_T_372 & io_arb_read_reqs_5_valid_0; // @[regfile.scala:128:7, :157:{13,26,29,45}, :163:33, :165:32]
assign issue_read_32 = _T_438; // @[regfile.scala:155:32, :157:{26,45}]
assign use_port_32 = _T_438; // @[regfile.scala:156:30, :157:{26,45}]
wire _T_439 = use_port_32 | _T_372; // @[regfile.scala:156:30, :163:33]
wire _T_444 = issue_read_32 | _T_434; // @[regfile.scala:155:32, :165:32]
wire issue_read_33; // @[regfile.scala:155:32]
wire use_port_33; // @[regfile.scala:156:30]
wire _T_448 = ~_T_444 & ~_T_382 & io_arb_read_reqs_5_valid_0; // @[regfile.scala:128:7, :157:{13,26,29,45}, :163:33, :165:32]
assign issue_read_33 = _T_448; // @[regfile.scala:155:32, :157:{26,45}]
assign use_port_33 = _T_448; // @[regfile.scala:156:30, :157:{26,45}]
wire _T_449 = use_port_33 | _T_382; // @[regfile.scala:156:30, :163:33]
wire _T_454 = issue_read_33 | _T_444; // @[regfile.scala:155:32, :165:32]
wire issue_read_34; // @[regfile.scala:155:32]
wire use_port_34; // @[regfile.scala:156:30]
wire _T_458 = ~_T_454 & ~_T_392 & io_arb_read_reqs_5_valid_0; // @[regfile.scala:128:7, :157:{13,26,29,45}, :163:33, :165:32]
assign issue_read_34 = _T_458; // @[regfile.scala:155:32, :157:{26,45}]
assign use_port_34 = _T_458; // @[regfile.scala:156:30, :157:{26,45}]
wire _T_459 = use_port_34 | _T_392; // @[regfile.scala:156:30, :163:33]
wire _T_464 = issue_read_34 | _T_454; // @[regfile.scala:155:32, :165:32]
wire issue_read_35; // @[regfile.scala:155:32]
wire use_port_35; // @[regfile.scala:156:30]
wire _T_468 = ~_T_464 & ~_T_402 & io_arb_read_reqs_5_valid_0; // @[regfile.scala:128:7, :157:{13,26,29,45}, :163:33, :165:32]
assign issue_read_35 = _T_468; // @[regfile.scala:155:32, :157:{26,45}]
assign use_port_35 = _T_468; // @[regfile.scala:156:30, :157:{26,45}]
assign data_sels_5 = _T_468 ? 6'h20 : _T_458 ? 6'h10 : _T_448 ? 6'h8 : _T_438 ? 6'h4 : _T_428 ? 6'h2 : 6'h1; // @[regfile.scala:149:25, :157:{26,45,75}, :160:22]
wire _T_469 = use_port_35 | _T_402; // @[regfile.scala:156:30, :163:33]
wire [1:0] _io_arb_read_reqs_5_ready_T_1 = _io_arb_read_reqs_5_ready_T; // @[regfile.scala:167:42]
wire [1:0] _GEN_6 = {1'h0, io_arb_read_reqs_4_valid_0}; // @[regfile.scala:128:7, :167:42]
wire [1:0] _GEN_7 = _GEN_4 + _GEN_6; // @[regfile.scala:167:42]
wire [1:0] _io_arb_read_reqs_5_ready_T_2; // @[regfile.scala:167:42]
assign _io_arb_read_reqs_5_ready_T_2 = _GEN_7; // @[regfile.scala:167:42]
wire [1:0] _io_arb_read_reqs_7_ready_T_4; // @[regfile.scala:167:42]
assign _io_arb_read_reqs_7_ready_T_4 = _GEN_7; // @[regfile.scala:167:42]
wire [1:0] _io_arb_read_reqs_5_ready_T_3 = _io_arb_read_reqs_5_ready_T_2; // @[regfile.scala:167:42]
wire [2:0] _io_arb_read_reqs_5_ready_T_4 = {2'h0, io_arb_read_reqs_2_valid_0} + {1'h0, _io_arb_read_reqs_5_ready_T_3}; // @[regfile.scala:128:7, :167:42]
wire [1:0] _io_arb_read_reqs_5_ready_T_5 = _io_arb_read_reqs_5_ready_T_4[1:0]; // @[regfile.scala:167:42]
wire [2:0] _io_arb_read_reqs_5_ready_T_6 = {1'h0, _io_arb_read_reqs_5_ready_T_1} + {1'h0, _io_arb_read_reqs_5_ready_T_5}; // @[regfile.scala:167:42]
wire [2:0] _io_arb_read_reqs_5_ready_T_7 = _io_arb_read_reqs_5_ready_T_6; // @[regfile.scala:167:42]
assign _io_arb_read_reqs_5_ready_T_8 = _io_arb_read_reqs_5_ready_T_7[2:1] != 2'h3; // @[regfile.scala:167:{42,82}]
assign io_arb_read_reqs_5_ready_0 = _io_arb_read_reqs_5_ready_T_8; // @[regfile.scala:128:7, :167:82]
wire issue_read_36; // @[regfile.scala:155:32]
wire use_port_36; // @[regfile.scala:156:30]
wire _T_485 = ~_T_419 & io_arb_read_reqs_6_valid_0; // @[regfile.scala:128:7, :157:{29,45}, :163:33]
assign issue_read_36 = _T_485; // @[regfile.scala:155:32, :157:45]
assign use_port_36 = _T_485; // @[regfile.scala:156:30, :157:45]
wire _T_486 = use_port_36 | _T_419; // @[regfile.scala:156:30, :163:33]
wire issue_read_37; // @[regfile.scala:155:32]
wire use_port_37; // @[regfile.scala:156:30]
wire _T_495 = ~issue_read_36 & ~_T_429 & io_arb_read_reqs_6_valid_0; // @[regfile.scala:128:7, :155:32, :157:{13,26,29,45}, :163:33]
assign issue_read_37 = _T_495; // @[regfile.scala:155:32, :157:{26,45}]
assign use_port_37 = _T_495; // @[regfile.scala:156:30, :157:{26,45}]
wire _T_496 = use_port_37 | _T_429; // @[regfile.scala:156:30, :163:33]
wire _T_501 = issue_read_37 | issue_read_36; // @[regfile.scala:155:32, :165:32]
wire issue_read_38; // @[regfile.scala:155:32]
wire use_port_38; // @[regfile.scala:156:30]
wire _T_505 = ~_T_501 & ~_T_439 & io_arb_read_reqs_6_valid_0; // @[regfile.scala:128:7, :157:{13,26,29,45}, :163:33, :165:32]
assign issue_read_38 = _T_505; // @[regfile.scala:155:32, :157:{26,45}]
assign use_port_38 = _T_505; // @[regfile.scala:156:30, :157:{26,45}]
wire _T_506 = use_port_38 | _T_439; // @[regfile.scala:156:30, :163:33]
wire _T_511 = issue_read_38 | _T_501; // @[regfile.scala:155:32, :165:32]
wire issue_read_39; // @[regfile.scala:155:32]
wire use_port_39; // @[regfile.scala:156:30]
wire _T_515 = ~_T_511 & ~_T_449 & io_arb_read_reqs_6_valid_0; // @[regfile.scala:128:7, :157:{13,26,29,45}, :163:33, :165:32]
assign issue_read_39 = _T_515; // @[regfile.scala:155:32, :157:{26,45}]
assign use_port_39 = _T_515; // @[regfile.scala:156:30, :157:{26,45}]
wire _T_516 = use_port_39 | _T_449; // @[regfile.scala:156:30, :163:33]
wire _T_521 = issue_read_39 | _T_511; // @[regfile.scala:155:32, :165:32]
wire issue_read_40; // @[regfile.scala:155:32]
wire use_port_40; // @[regfile.scala:156:30]
wire _T_525 = ~_T_521 & ~_T_459 & io_arb_read_reqs_6_valid_0; // @[regfile.scala:128:7, :157:{13,26,29,45}, :163:33, :165:32]
assign issue_read_40 = _T_525; // @[regfile.scala:155:32, :157:{26,45}]
assign use_port_40 = _T_525; // @[regfile.scala:156:30, :157:{26,45}]
wire _T_526 = use_port_40 | _T_459; // @[regfile.scala:156:30, :163:33]
wire _T_531 = issue_read_40 | _T_521; // @[regfile.scala:155:32, :165:32]
wire issue_read_41; // @[regfile.scala:155:32]
wire use_port_41; // @[regfile.scala:156:30]
wire _T_535 = ~_T_531 & ~_T_469 & io_arb_read_reqs_6_valid_0; // @[regfile.scala:128:7, :157:{13,26,29,45}, :163:33, :165:32]
assign issue_read_41 = _T_535; // @[regfile.scala:155:32, :157:{26,45}]
assign use_port_41 = _T_535; // @[regfile.scala:156:30, :157:{26,45}]
assign data_sels_6 = _T_535 ? 6'h20 : _T_525 ? 6'h10 : _T_515 ? 6'h8 : _T_505 ? 6'h4 : _T_495 ? 6'h2 : 6'h1; // @[regfile.scala:149:25, :157:{26,45,75}, :160:22]
wire _T_536 = use_port_41 | _T_469; // @[regfile.scala:156:30, :163:33]
wire [1:0] _io_arb_read_reqs_6_ready_T_1 = _io_arb_read_reqs_6_ready_T; // @[regfile.scala:167:42]
wire [2:0] _io_arb_read_reqs_6_ready_T_2 = _GEN_3 + {1'h0, _io_arb_read_reqs_6_ready_T_1}; // @[regfile.scala:167:42]
wire [1:0] _io_arb_read_reqs_6_ready_T_3 = _io_arb_read_reqs_6_ready_T_2[1:0]; // @[regfile.scala:167:42]
wire [1:0] _GEN_8 = {1'h0, io_arb_read_reqs_5_valid_0}; // @[regfile.scala:128:7, :167:42]
wire [1:0] _GEN_9 = _GEN_6 + _GEN_8; // @[regfile.scala:167:42]
wire [1:0] _io_arb_read_reqs_6_ready_T_4; // @[regfile.scala:167:42]
assign _io_arb_read_reqs_6_ready_T_4 = _GEN_9; // @[regfile.scala:167:42]
wire [1:0] _io_arb_read_reqs_8_ready_T_6; // @[regfile.scala:167:42]
assign _io_arb_read_reqs_8_ready_T_6 = _GEN_9; // @[regfile.scala:167:42]
wire [1:0] _io_arb_read_reqs_9_ready_T_6; // @[regfile.scala:167:42]
assign _io_arb_read_reqs_9_ready_T_6 = _GEN_9; // @[regfile.scala:167:42]
wire [1:0] _io_arb_read_reqs_6_ready_T_5 = _io_arb_read_reqs_6_ready_T_4; // @[regfile.scala:167:42]
wire [2:0] _io_arb_read_reqs_6_ready_T_6 = {2'h0, io_arb_read_reqs_3_valid_0} + {1'h0, _io_arb_read_reqs_6_ready_T_5}; // @[regfile.scala:128:7, :167:42]
wire [1:0] _io_arb_read_reqs_6_ready_T_7 = _io_arb_read_reqs_6_ready_T_6[1:0]; // @[regfile.scala:167:42]
wire [2:0] _io_arb_read_reqs_6_ready_T_8 = {1'h0, _io_arb_read_reqs_6_ready_T_3} + {1'h0, _io_arb_read_reqs_6_ready_T_7}; // @[regfile.scala:167:42]
wire [2:0] _io_arb_read_reqs_6_ready_T_9 = _io_arb_read_reqs_6_ready_T_8; // @[regfile.scala:167:42]
assign _io_arb_read_reqs_6_ready_T_10 = _io_arb_read_reqs_6_ready_T_9[2:1] != 2'h3; // @[regfile.scala:167:{42,82}]
assign io_arb_read_reqs_6_ready_0 = _io_arb_read_reqs_6_ready_T_10; // @[regfile.scala:128:7, :167:82]
wire issue_read_42; // @[regfile.scala:155:32]
wire use_port_42; // @[regfile.scala:156:30]
wire _T_552 = ~_T_486 & io_arb_read_reqs_7_valid_0; // @[regfile.scala:128:7, :157:{29,45}, :163:33]
assign issue_read_42 = _T_552; // @[regfile.scala:155:32, :157:45]
assign use_port_42 = _T_552; // @[regfile.scala:156:30, :157:45]
wire _T_553 = use_port_42 | _T_486; // @[regfile.scala:156:30, :163:33]
wire issue_read_43; // @[regfile.scala:155:32]
wire use_port_43; // @[regfile.scala:156:30]
wire _T_562 = ~issue_read_42 & ~_T_496 & io_arb_read_reqs_7_valid_0; // @[regfile.scala:128:7, :155:32, :157:{13,26,29,45}, :163:33]
assign issue_read_43 = _T_562; // @[regfile.scala:155:32, :157:{26,45}]
assign use_port_43 = _T_562; // @[regfile.scala:156:30, :157:{26,45}]
wire _T_563 = use_port_43 | _T_496; // @[regfile.scala:156:30, :163:33]
wire _T_568 = issue_read_43 | issue_read_42; // @[regfile.scala:155:32, :165:32]
wire issue_read_44; // @[regfile.scala:155:32]
wire use_port_44; // @[regfile.scala:156:30]
wire _T_572 = ~_T_568 & ~_T_506 & io_arb_read_reqs_7_valid_0; // @[regfile.scala:128:7, :157:{13,26,29,45}, :163:33, :165:32]
assign issue_read_44 = _T_572; // @[regfile.scala:155:32, :157:{26,45}]
assign use_port_44 = _T_572; // @[regfile.scala:156:30, :157:{26,45}]
wire _T_573 = use_port_44 | _T_506; // @[regfile.scala:156:30, :163:33]
wire _T_578 = issue_read_44 | _T_568; // @[regfile.scala:155:32, :165:32]
wire issue_read_45; // @[regfile.scala:155:32]
wire use_port_45; // @[regfile.scala:156:30]
wire _T_582 = ~_T_578 & ~_T_516 & io_arb_read_reqs_7_valid_0; // @[regfile.scala:128:7, :157:{13,26,29,45}, :163:33, :165:32]
assign issue_read_45 = _T_582; // @[regfile.scala:155:32, :157:{26,45}]
assign use_port_45 = _T_582; // @[regfile.scala:156:30, :157:{26,45}]
wire _T_583 = use_port_45 | _T_516; // @[regfile.scala:156:30, :163:33]
wire _T_588 = issue_read_45 | _T_578; // @[regfile.scala:155:32, :165:32]
wire issue_read_46; // @[regfile.scala:155:32]
wire use_port_46; // @[regfile.scala:156:30]
wire _T_592 = ~_T_588 & ~_T_526 & io_arb_read_reqs_7_valid_0; // @[regfile.scala:128:7, :157:{13,26,29,45}, :163:33, :165:32]
assign issue_read_46 = _T_592; // @[regfile.scala:155:32, :157:{26,45}]
assign use_port_46 = _T_592; // @[regfile.scala:156:30, :157:{26,45}]
wire _T_593 = use_port_46 | _T_526; // @[regfile.scala:156:30, :163:33]
wire _T_598 = issue_read_46 | _T_588; // @[regfile.scala:155:32, :165:32]
wire issue_read_47; // @[regfile.scala:155:32]
wire use_port_47; // @[regfile.scala:156:30]
wire _T_602 = ~_T_598 & ~_T_536 & io_arb_read_reqs_7_valid_0; // @[regfile.scala:128:7, :157:{13,26,29,45}, :163:33, :165:32]
assign issue_read_47 = _T_602; // @[regfile.scala:155:32, :157:{26,45}]
assign use_port_47 = _T_602; // @[regfile.scala:156:30, :157:{26,45}]
assign data_sels_7 = _T_602 ? 6'h20 : _T_592 ? 6'h10 : _T_582 ? 6'h8 : _T_572 ? 6'h4 : _T_562 ? 6'h2 : 6'h1; // @[regfile.scala:149:25, :157:{26,45,75}, :160:22]
wire _T_603 = use_port_47 | _T_536; // @[regfile.scala:156:30, :163:33]
wire [1:0] _io_arb_read_reqs_7_ready_T_1 = _io_arb_read_reqs_7_ready_T; // @[regfile.scala:167:42]
wire [2:0] _io_arb_read_reqs_7_ready_T_2 = _GEN_3 + {1'h0, _io_arb_read_reqs_7_ready_T_1}; // @[regfile.scala:167:42]
wire [1:0] _io_arb_read_reqs_7_ready_T_3 = _io_arb_read_reqs_7_ready_T_2[1:0]; // @[regfile.scala:167:42]
wire [1:0] _io_arb_read_reqs_7_ready_T_5 = _io_arb_read_reqs_7_ready_T_4; // @[regfile.scala:167:42]
wire [1:0] _GEN_10 = {1'h0, io_arb_read_reqs_6_valid_0}; // @[regfile.scala:128:7, :167:42]
wire [1:0] _io_arb_read_reqs_7_ready_T_6 = _GEN_8 + _GEN_10; // @[regfile.scala:167:42]
wire [1:0] _io_arb_read_reqs_7_ready_T_7 = _io_arb_read_reqs_7_ready_T_6; // @[regfile.scala:167:42]
wire [2:0] _io_arb_read_reqs_7_ready_T_8 = {1'h0, _io_arb_read_reqs_7_ready_T_5} + {1'h0, _io_arb_read_reqs_7_ready_T_7}; // @[regfile.scala:167:42]
wire [2:0] _io_arb_read_reqs_7_ready_T_9 = _io_arb_read_reqs_7_ready_T_8; // @[regfile.scala:167:42]
wire [3:0] _io_arb_read_reqs_7_ready_T_10 = {2'h0, _io_arb_read_reqs_7_ready_T_3} + {1'h0, _io_arb_read_reqs_7_ready_T_9}; // @[regfile.scala:167:42]
wire [2:0] _io_arb_read_reqs_7_ready_T_11 = _io_arb_read_reqs_7_ready_T_10[2:0]; // @[regfile.scala:167:42]
assign _io_arb_read_reqs_7_ready_T_12 = _io_arb_read_reqs_7_ready_T_11[2:1] != 2'h3; // @[regfile.scala:167:{42,82}]
assign io_arb_read_reqs_7_ready_0 = _io_arb_read_reqs_7_ready_T_12; // @[regfile.scala:128:7, :167:82]
wire issue_read_48; // @[regfile.scala:155:32]
wire use_port_48; // @[regfile.scala:156:30]
wire _T_619 = ~_T_553 & io_arb_read_reqs_8_valid_0; // @[regfile.scala:128:7, :157:{29,45}, :163:33]
assign issue_read_48 = _T_619; // @[regfile.scala:155:32, :157:45]
assign use_port_48 = _T_619; // @[regfile.scala:156:30, :157:45]
wire _T_620 = use_port_48 | _T_553; // @[regfile.scala:156:30, :163:33]
wire issue_read_49; // @[regfile.scala:155:32]
wire use_port_49; // @[regfile.scala:156:30]
wire _T_629 = ~issue_read_48 & ~_T_563 & io_arb_read_reqs_8_valid_0; // @[regfile.scala:128:7, :155:32, :157:{13,26,29,45}, :163:33]
assign issue_read_49 = _T_629; // @[regfile.scala:155:32, :157:{26,45}]
assign use_port_49 = _T_629; // @[regfile.scala:156:30, :157:{26,45}]
wire _T_630 = use_port_49 | _T_563; // @[regfile.scala:156:30, :163:33]
wire _T_635 = issue_read_49 | issue_read_48; // @[regfile.scala:155:32, :165:32]
wire issue_read_50; // @[regfile.scala:155:32]
wire use_port_50; // @[regfile.scala:156:30]
wire _T_639 = ~_T_635 & ~_T_573 & io_arb_read_reqs_8_valid_0; // @[regfile.scala:128:7, :157:{13,26,29,45}, :163:33, :165:32]
assign issue_read_50 = _T_639; // @[regfile.scala:155:32, :157:{26,45}]
assign use_port_50 = _T_639; // @[regfile.scala:156:30, :157:{26,45}]
wire _T_640 = use_port_50 | _T_573; // @[regfile.scala:156:30, :163:33]
wire _T_645 = issue_read_50 | _T_635; // @[regfile.scala:155:32, :165:32]
wire issue_read_51; // @[regfile.scala:155:32]
wire use_port_51; // @[regfile.scala:156:30]
wire _T_649 = ~_T_645 & ~_T_583 & io_arb_read_reqs_8_valid_0; // @[regfile.scala:128:7, :157:{13,26,29,45}, :163:33, :165:32]
assign issue_read_51 = _T_649; // @[regfile.scala:155:32, :157:{26,45}]
assign use_port_51 = _T_649; // @[regfile.scala:156:30, :157:{26,45}]
wire _T_650 = use_port_51 | _T_583; // @[regfile.scala:156:30, :163:33]
wire _T_655 = issue_read_51 | _T_645; // @[regfile.scala:155:32, :165:32]
wire issue_read_52; // @[regfile.scala:155:32]
wire use_port_52; // @[regfile.scala:156:30]
wire _T_659 = ~_T_655 & ~_T_593 & io_arb_read_reqs_8_valid_0; // @[regfile.scala:128:7, :157:{13,26,29,45}, :163:33, :165:32]
assign issue_read_52 = _T_659; // @[regfile.scala:155:32, :157:{26,45}]
assign use_port_52 = _T_659; // @[regfile.scala:156:30, :157:{26,45}]
wire _T_660 = use_port_52 | _T_593; // @[regfile.scala:156:30, :163:33]
wire _T_665 = issue_read_52 | _T_655; // @[regfile.scala:155:32, :165:32]
wire issue_read_53; // @[regfile.scala:155:32]
wire use_port_53; // @[regfile.scala:156:30]
wire _T_669 = ~_T_665 & ~_T_603 & io_arb_read_reqs_8_valid_0; // @[regfile.scala:128:7, :157:{13,26,29,45}, :163:33, :165:32]
assign issue_read_53 = _T_669; // @[regfile.scala:155:32, :157:{26,45}]
assign use_port_53 = _T_669; // @[regfile.scala:156:30, :157:{26,45}]
assign data_sels_8 = _T_669 ? 6'h20 : _T_659 ? 6'h10 : _T_649 ? 6'h8 : _T_639 ? 6'h4 : _T_629 ? 6'h2 : 6'h1; // @[regfile.scala:149:25, :157:{26,45,75}, :160:22]
wire _T_670 = use_port_53 | _T_603; // @[regfile.scala:156:30, :163:33]
wire [1:0] _io_arb_read_reqs_8_ready_T_1 = _io_arb_read_reqs_8_ready_T; // @[regfile.scala:167:42]
wire [1:0] _io_arb_read_reqs_8_ready_T_3 = _io_arb_read_reqs_8_ready_T_2; // @[regfile.scala:167:42]
wire [2:0] _io_arb_read_reqs_8_ready_T_4 = {1'h0, _io_arb_read_reqs_8_ready_T_1} + {1'h0, _io_arb_read_reqs_8_ready_T_3}; // @[regfile.scala:167:42]
wire [2:0] _io_arb_read_reqs_8_ready_T_5 = _io_arb_read_reqs_8_ready_T_4; // @[regfile.scala:167:42]
wire [1:0] _io_arb_read_reqs_8_ready_T_7 = _io_arb_read_reqs_8_ready_T_6; // @[regfile.scala:167:42]
wire [1:0] _GEN_11 = {1'h0, io_arb_read_reqs_7_valid_0}; // @[regfile.scala:128:7, :167:42]
wire [1:0] _io_arb_read_reqs_8_ready_T_8 = _GEN_10 + _GEN_11; // @[regfile.scala:167:42]
wire [1:0] _io_arb_read_reqs_8_ready_T_9 = _io_arb_read_reqs_8_ready_T_8; // @[regfile.scala:167:42]
wire [2:0] _io_arb_read_reqs_8_ready_T_10 = {1'h0, _io_arb_read_reqs_8_ready_T_7} + {1'h0, _io_arb_read_reqs_8_ready_T_9}; // @[regfile.scala:167:42]
wire [2:0] _io_arb_read_reqs_8_ready_T_11 = _io_arb_read_reqs_8_ready_T_10; // @[regfile.scala:167:42]
wire [3:0] _io_arb_read_reqs_8_ready_T_12 = {1'h0, _io_arb_read_reqs_8_ready_T_5} + {1'h0, _io_arb_read_reqs_8_ready_T_11}; // @[regfile.scala:167:42]
wire [3:0] _io_arb_read_reqs_8_ready_T_13 = _io_arb_read_reqs_8_ready_T_12; // @[regfile.scala:167:42]
assign _io_arb_read_reqs_8_ready_T_14 = _io_arb_read_reqs_8_ready_T_13 < 4'h6; // @[regfile.scala:167:{42,82}]
assign io_arb_read_reqs_8_ready_0 = _io_arb_read_reqs_8_ready_T_14; // @[regfile.scala:128:7, :167:82]
wire issue_read_54; // @[regfile.scala:155:32]
wire use_port_54; // @[regfile.scala:156:30]
wire _T_686 = ~_T_620 & io_arb_read_reqs_9_valid_0; // @[regfile.scala:128:7, :157:{29,45}, :163:33]
assign issue_read_54 = _T_686; // @[regfile.scala:155:32, :157:45]
assign use_port_54 = _T_686; // @[regfile.scala:156:30, :157:45]
wire issue_read_55; // @[regfile.scala:155:32]
wire use_port_55; // @[regfile.scala:156:30]
wire _T_696 = ~issue_read_54 & ~_T_630 & io_arb_read_reqs_9_valid_0; // @[regfile.scala:128:7, :155:32, :157:{13,26,29,45}, :163:33]
assign issue_read_55 = _T_696; // @[regfile.scala:155:32, :157:{26,45}]
assign use_port_55 = _T_696; // @[regfile.scala:156:30, :157:{26,45}]
wire _T_702 = issue_read_55 | issue_read_54; // @[regfile.scala:155:32, :165:32]
wire issue_read_56; // @[regfile.scala:155:32]
wire use_port_56; // @[regfile.scala:156:30]
wire _T_706 = ~_T_702 & ~_T_640 & io_arb_read_reqs_9_valid_0; // @[regfile.scala:128:7, :157:{13,26,29,45}, :163:33, :165:32]
assign issue_read_56 = _T_706; // @[regfile.scala:155:32, :157:{26,45}]
assign use_port_56 = _T_706; // @[regfile.scala:156:30, :157:{26,45}]
wire _T_712 = issue_read_56 | _T_702; // @[regfile.scala:155:32, :165:32]
wire issue_read_57; // @[regfile.scala:155:32]
wire use_port_57; // @[regfile.scala:156:30]
wire _T_716 = ~_T_712 & ~_T_650 & io_arb_read_reqs_9_valid_0; // @[regfile.scala:128:7, :157:{13,26,29,45}, :163:33, :165:32]
assign issue_read_57 = _T_716; // @[regfile.scala:155:32, :157:{26,45}]
assign use_port_57 = _T_716; // @[regfile.scala:156:30, :157:{26,45}]
wire _T_722 = issue_read_57 | _T_712; // @[regfile.scala:155:32, :165:32]
wire issue_read_58; // @[regfile.scala:155:32]
wire use_port_58; // @[regfile.scala:156:30]
wire _T_726 = ~_T_722 & ~_T_660 & io_arb_read_reqs_9_valid_0; // @[regfile.scala:128:7, :157:{13,26,29,45}, :163:33, :165:32]
assign issue_read_58 = _T_726; // @[regfile.scala:155:32, :157:{26,45}]
assign use_port_58 = _T_726; // @[regfile.scala:156:30, :157:{26,45}]
wire _T_732 = issue_read_58 | _T_722; // @[regfile.scala:155:32, :165:32]
wire issue_read_59; // @[regfile.scala:155:32]
wire use_port_59; // @[regfile.scala:156:30]
wire _T_736 = ~_T_732 & ~_T_670 & io_arb_read_reqs_9_valid_0; // @[regfile.scala:128:7, :157:{13,26,29,45}, :163:33, :165:32]
assign issue_read_59 = _T_736; // @[regfile.scala:155:32, :157:{26,45}]
assign use_port_59 = _T_736; // @[regfile.scala:156:30, :157:{26,45}]
assign data_sels_9 = _T_736 ? 6'h20 : _T_726 ? 6'h10 : _T_716 ? 6'h8 : _T_706 ? 6'h4 : _T_696 ? 6'h2 : 6'h1; // @[regfile.scala:149:25, :157:{26,45,75}, :160:22]
wire [1:0] _io_arb_read_reqs_9_ready_T_1 = _io_arb_read_reqs_9_ready_T; // @[regfile.scala:167:42]
wire [1:0] _io_arb_read_reqs_9_ready_T_3 = _io_arb_read_reqs_9_ready_T_2; // @[regfile.scala:167:42]
wire [2:0] _io_arb_read_reqs_9_ready_T_4 = {1'h0, _io_arb_read_reqs_9_ready_T_1} + {1'h0, _io_arb_read_reqs_9_ready_T_3}; // @[regfile.scala:167:42]
wire [2:0] _io_arb_read_reqs_9_ready_T_5 = _io_arb_read_reqs_9_ready_T_4; // @[regfile.scala:167:42]
wire [1:0] _io_arb_read_reqs_9_ready_T_7 = _io_arb_read_reqs_9_ready_T_6; // @[regfile.scala:167:42]
wire [1:0] _io_arb_read_reqs_9_ready_T_8 = _GEN_11 + {1'h0, io_arb_read_reqs_8_valid_0}; // @[regfile.scala:128:7, :167:42]
wire [1:0] _io_arb_read_reqs_9_ready_T_9 = _io_arb_read_reqs_9_ready_T_8; // @[regfile.scala:167:42]
wire [2:0] _io_arb_read_reqs_9_ready_T_10 = {2'h0, io_arb_read_reqs_6_valid_0} + {1'h0, _io_arb_read_reqs_9_ready_T_9}; // @[regfile.scala:128:7, :167:42]
wire [1:0] _io_arb_read_reqs_9_ready_T_11 = _io_arb_read_reqs_9_ready_T_10[1:0]; // @[regfile.scala:167:42]
wire [2:0] _io_arb_read_reqs_9_ready_T_12 = {1'h0, _io_arb_read_reqs_9_ready_T_7} + {1'h0, _io_arb_read_reqs_9_ready_T_11}; // @[regfile.scala:167:42]
wire [2:0] _io_arb_read_reqs_9_ready_T_13 = _io_arb_read_reqs_9_ready_T_12; // @[regfile.scala:167:42]
wire [3:0] _io_arb_read_reqs_9_ready_T_14 = {1'h0, _io_arb_read_reqs_9_ready_T_5} + {1'h0, _io_arb_read_reqs_9_ready_T_13}; // @[regfile.scala:167:42]
wire [3:0] _io_arb_read_reqs_9_ready_T_15 = _io_arb_read_reqs_9_ready_T_14; // @[regfile.scala:167:42]
assign _io_arb_read_reqs_9_ready_T_16 = _io_arb_read_reqs_9_ready_T_15 < 4'h6; // @[regfile.scala:167:{42,82}]
assign io_arb_read_reqs_9_ready_0 = _io_arb_read_reqs_9_ready_T_16; // @[regfile.scala:128:7, :167:82] |
Generate the Verilog code corresponding to the following Chisel files.
File PMA.scala:
// See LICENSE.SiFive for license details.
// See LICENSE.Berkeley for license details.
package freechips.rocketchip.rocket
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config._
import freechips.rocketchip.devices.debug.DebugModuleKey
import freechips.rocketchip.diplomacy.RegionType
import freechips.rocketchip.subsystem.CacheBlockBytes
import freechips.rocketchip.tile.{CoreModule, CoreBundle}
import freechips.rocketchip.tilelink.{TLSlavePortParameters, TLManagerParameters}
class PMAChecker(manager: TLSlavePortParameters)(implicit p: Parameters) extends CoreModule()(p) {
val io = IO(new Bundle {
val paddr = Input(UInt())
val resp = Output(new Bundle {
val cacheable = Bool()
val r = Bool()
val w = Bool()
val pp = Bool()
val al = Bool()
val aa = Bool()
val x = Bool()
val eff = Bool()
})
})
// PMA
// check exist a slave can consume this address.
val legal_address = manager.findSafe(io.paddr).reduce(_||_)
// check utility to help check SoC property.
def fastCheck(member: TLManagerParameters => Boolean) =
legal_address && manager.fastProperty(io.paddr, member, (b:Boolean) => b.B)
io.resp.cacheable := fastCheck(_.supportsAcquireB)
io.resp.r := fastCheck(_.supportsGet)
io.resp.w := fastCheck(_.supportsPutFull)
io.resp.pp := fastCheck(_.supportsPutPartial)
io.resp.al := fastCheck(_.supportsLogical)
io.resp.aa := fastCheck(_.supportsArithmetic)
io.resp.x := fastCheck(_.executable)
io.resp.eff := fastCheck(Seq(RegionType.PUT_EFFECTS, RegionType.GET_EFFECTS) contains _.regionType)
}
File Parameters.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.diplomacy
import chisel3._
import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor}
import freechips.rocketchip.util.ShiftQueue
/** Options for describing the attributes of memory regions */
object RegionType {
// Define the 'more relaxed than' ordering
val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS)
sealed trait T extends Ordered[T] {
def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this)
}
case object CACHED extends T // an intermediate agent may have cached a copy of the region for you
case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided
case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible
case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached
case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects
case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed
case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively
}
// A non-empty half-open range; [start, end)
case class IdRange(start: Int, end: Int) extends Ordered[IdRange]
{
require (start >= 0, s"Ids cannot be negative, but got: $start.")
require (start <= end, "Id ranges cannot be negative.")
def compare(x: IdRange) = {
val primary = (this.start - x.start).signum
val secondary = (x.end - this.end).signum
if (primary != 0) primary else secondary
}
def overlaps(x: IdRange) = start < x.end && x.start < end
def contains(x: IdRange) = start <= x.start && x.end <= end
def contains(x: Int) = start <= x && x < end
def contains(x: UInt) =
if (size == 0) {
false.B
} else if (size == 1) { // simple comparison
x === start.U
} else {
// find index of largest different bit
val largestDeltaBit = log2Floor(start ^ (end-1))
val smallestCommonBit = largestDeltaBit + 1 // may not exist in x
val uncommonMask = (1 << smallestCommonBit) - 1
val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0)
// the prefix must match exactly (note: may shift ALL bits away)
(x >> smallestCommonBit) === (start >> smallestCommonBit).U &&
// firrtl constant prop range analysis can eliminate these two:
(start & uncommonMask).U <= uncommonBits &&
uncommonBits <= ((end-1) & uncommonMask).U
}
def shift(x: Int) = IdRange(start+x, end+x)
def size = end - start
def isEmpty = end == start
def range = start until end
}
object IdRange
{
def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else {
val ranges = s.sorted
(ranges.tail zip ranges.init) find { case (a, b) => a overlaps b }
}
}
// An potentially empty inclusive range of 2-powers [min, max] (in bytes)
case class TransferSizes(min: Int, max: Int)
{
def this(x: Int) = this(x, x)
require (min <= max, s"Min transfer $min > max transfer $max")
require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)")
require (max == 0 || isPow2(max), s"TransferSizes must be a power of 2, got: $max")
require (min == 0 || isPow2(min), s"TransferSizes must be a power of 2, got: $min")
require (max == 0 || min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)")
def none = min == 0
def contains(x: Int) = isPow2(x) && min <= x && x <= max
def containsLg(x: Int) = contains(1 << x)
def containsLg(x: UInt) =
if (none) false.B
else if (min == max) { log2Ceil(min).U === x }
else { log2Ceil(min).U <= x && x <= log2Ceil(max).U }
def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max)
def intersect(x: TransferSizes) =
if (x.max < min || max < x.min) TransferSizes.none
else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max))
// Not a union, because the result may contain sizes contained by neither term
// NOT TO BE CONFUSED WITH COVERPOINTS
def mincover(x: TransferSizes) = {
if (none) {
x
} else if (x.none) {
this
} else {
TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max))
}
}
override def toString() = "TransferSizes[%d, %d]".format(min, max)
}
object TransferSizes {
def apply(x: Int) = new TransferSizes(x)
val none = new TransferSizes(0)
def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _)
def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _)
implicit def asBool(x: TransferSizes) = !x.none
}
// AddressSets specify the address space managed by the manager
// Base is the base address, and mask are the bits consumed by the manager
// e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff
// e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ...
case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet]
{
// Forbid misaligned base address (and empty sets)
require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}")
require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous
// We do allow negative mask (=> ignore all high bits)
def contains(x: BigInt) = ((x ^ base) & ~mask) == 0
def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S
// turn x into an address contained in this set
def legalize(x: UInt): UInt = base.U | (mask.U & x)
// overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1)
def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0
// contains iff bitwise: x.mask => mask && contains(x.base)
def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0
// The number of bytes to which the manager must be aligned
def alignment = ((mask + 1) & ~mask)
// Is this a contiguous memory range
def contiguous = alignment == mask+1
def finite = mask >= 0
def max = { require (finite, "Max cannot be calculated on infinite mask"); base | mask }
// Widen the match function to ignore all bits in imask
def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask)
// Return an AddressSet that only contains the addresses both sets contain
def intersect(x: AddressSet): Option[AddressSet] = {
if (!overlaps(x)) {
None
} else {
val r_mask = mask & x.mask
val r_base = base | x.base
Some(AddressSet(r_base, r_mask))
}
}
def subtract(x: AddressSet): Seq[AddressSet] = {
intersect(x) match {
case None => Seq(this)
case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit =>
val nmask = (mask & (bit-1)) | remove.mask
val nbase = (remove.base ^ bit) & ~nmask
AddressSet(nbase, nmask)
}
}
}
// AddressSets have one natural Ordering (the containment order, if contiguous)
def compare(x: AddressSet) = {
val primary = (this.base - x.base).signum // smallest address first
val secondary = (x.mask - this.mask).signum // largest mask first
if (primary != 0) primary else secondary
}
// We always want to see things in hex
override def toString() = {
if (mask >= 0) {
"AddressSet(0x%x, 0x%x)".format(base, mask)
} else {
"AddressSet(0x%x, ~0x%x)".format(base, ~mask)
}
}
def toRanges = {
require (finite, "Ranges cannot be calculated on infinite mask")
val size = alignment
val fragments = mask & ~(size-1)
val bits = bitIndexes(fragments)
(BigInt(0) until (BigInt(1) << bits.size)).map { i =>
val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) }
AddressRange(off, size)
}
}
}
object AddressSet
{
val everything = AddressSet(0, -1)
def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = {
if (size == 0) tail.reverse else {
val maxBaseAlignment = base & (-base) // 0 for infinite (LSB)
val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size
val step =
if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment)
maxSizeAlignment else maxBaseAlignment
misaligned(base+step, size-step, AddressSet(base, step-1) +: tail)
}
}
def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = {
// Pair terms up by ignoring 'bit'
seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) =>
if (seq.size == 1) {
seq.head // singleton -> unaffected
} else {
key.copy(mask = key.mask | bit) // pair - widen mask by bit
}
}.toList
}
def unify(seq: Seq[AddressSet]): Seq[AddressSet] = {
val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _)
AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted
}
def enumerateMask(mask: BigInt): Seq[BigInt] = {
def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] =
if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail)
helper(0, Nil)
}
def enumerateBits(mask: BigInt): Seq[BigInt] = {
def helper(x: BigInt): Seq[BigInt] = {
if (x == 0) {
Nil
} else {
val bit = x & (-x)
bit +: helper(x & ~bit)
}
}
helper(mask)
}
}
case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean)
{
require (depth >= 0, "Buffer depth must be >= 0")
def isDefined = depth > 0
def latency = if (isDefined && !flow) 1 else 0
def apply[T <: Data](x: DecoupledIO[T]) =
if (isDefined) Queue(x, depth, flow=flow, pipe=pipe)
else x
def irrevocable[T <: Data](x: ReadyValidIO[T]) =
if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe)
else x
def sq[T <: Data](x: DecoupledIO[T]) =
if (!isDefined) x else {
val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe))
sq.io.enq <> x
sq.io.deq
}
override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "")
}
object BufferParams
{
implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false)
val default = BufferParams(2)
val none = BufferParams(0)
val flow = BufferParams(1, true, false)
val pipe = BufferParams(1, false, true)
}
case class TriStateValue(value: Boolean, set: Boolean)
{
def update(orig: Boolean) = if (set) value else orig
}
object TriStateValue
{
implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true)
def unset = TriStateValue(false, false)
}
trait DirectedBuffers[T] {
def copyIn(x: BufferParams): T
def copyOut(x: BufferParams): T
def copyInOut(x: BufferParams): T
}
trait IdMapEntry {
def name: String
def from: IdRange
def to: IdRange
def isCache: Boolean
def requestFifo: Boolean
def maxTransactionsInFlight: Option[Int]
def pretty(fmt: String) =
if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5
fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "")
} else {
fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "")
}
}
abstract class IdMap[T <: IdMapEntry] {
protected val fmt: String
val mapping: Seq[T]
def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n")
}
| module PMAChecker( // @[PMA.scala:18:7]
input clock, // @[PMA.scala:18:7]
input reset, // @[PMA.scala:18:7]
input [48:0] io_paddr, // @[PMA.scala:19:14]
output io_resp_cacheable, // @[PMA.scala:19:14]
output io_resp_r, // @[PMA.scala:19:14]
output io_resp_w, // @[PMA.scala:19:14]
output io_resp_pp, // @[PMA.scala:19:14]
output io_resp_al, // @[PMA.scala:19:14]
output io_resp_aa, // @[PMA.scala:19:14]
output io_resp_x, // @[PMA.scala:19:14]
output io_resp_eff // @[PMA.scala:19:14]
);
wire [48:0] io_paddr_0 = io_paddr; // @[PMA.scala:18:7]
wire [49:0] _io_resp_r_T_2 = 50'h0; // @[Parameters.scala:137:46]
wire [49:0] _io_resp_r_T_3 = 50'h0; // @[Parameters.scala:137:46]
wire _io_resp_r_T_4 = 1'h1; // @[Parameters.scala:137:59]
wire _io_resp_cacheable_T_28 = 1'h0; // @[Mux.scala:30:73]
wire _io_resp_w_T_47 = 1'h0; // @[Mux.scala:30:73]
wire _io_resp_pp_T_47 = 1'h0; // @[Mux.scala:30:73]
wire _io_resp_al_T_47 = 1'h0; // @[Mux.scala:30:73]
wire _io_resp_aa_T_47 = 1'h0; // @[Mux.scala:30:73]
wire _io_resp_x_T_65 = 1'h0; // @[Mux.scala:30:73]
wire _io_resp_eff_T_59 = 1'h0; // @[Mux.scala:30:73]
wire [48:0] _legal_address_T = io_paddr_0; // @[PMA.scala:18:7]
wire [48:0] _io_resp_cacheable_T = io_paddr_0; // @[PMA.scala:18:7]
wire _io_resp_cacheable_T_31; // @[PMA.scala:39:19]
wire [48:0] _io_resp_r_T = io_paddr_0; // @[PMA.scala:18:7]
wire [48:0] _io_resp_w_T = io_paddr_0; // @[PMA.scala:18:7]
wire [48:0] _io_resp_pp_T = io_paddr_0; // @[PMA.scala:18:7]
wire [48:0] _io_resp_al_T = io_paddr_0; // @[PMA.scala:18:7]
wire [48:0] _io_resp_aa_T = io_paddr_0; // @[PMA.scala:18:7]
wire [48:0] _io_resp_x_T = io_paddr_0; // @[PMA.scala:18:7]
wire [48:0] _io_resp_eff_T = io_paddr_0; // @[PMA.scala:18:7]
wire _io_resp_r_T_5; // @[PMA.scala:39:19]
wire _io_resp_w_T_49; // @[PMA.scala:39:19]
wire _io_resp_pp_T_49; // @[PMA.scala:39:19]
wire _io_resp_al_T_49; // @[PMA.scala:39:19]
wire _io_resp_aa_T_49; // @[PMA.scala:39:19]
wire _io_resp_x_T_67; // @[PMA.scala:39:19]
wire _io_resp_eff_T_61; // @[PMA.scala:39:19]
wire io_resp_cacheable_0; // @[PMA.scala:18:7]
wire io_resp_r_0; // @[PMA.scala:18:7]
wire io_resp_w_0; // @[PMA.scala:18:7]
wire io_resp_pp_0; // @[PMA.scala:18:7]
wire io_resp_al_0; // @[PMA.scala:18:7]
wire io_resp_aa_0; // @[PMA.scala:18:7]
wire io_resp_x_0; // @[PMA.scala:18:7]
wire io_resp_eff_0; // @[PMA.scala:18:7]
wire [49:0] _legal_address_T_1 = {1'h0, _legal_address_T}; // @[Parameters.scala:137:{31,41}]
wire [49:0] _legal_address_T_2 = _legal_address_T_1 & 50'h3FFFFFFFFF000; // @[Parameters.scala:137:{41,46}]
wire [49:0] _legal_address_T_3 = _legal_address_T_2; // @[Parameters.scala:137:46]
wire _legal_address_T_4 = _legal_address_T_3 == 50'h0; // @[Parameters.scala:137:{46,59}]
wire _legal_address_WIRE_0 = _legal_address_T_4; // @[Parameters.scala:612:40]
wire [48:0] _GEN = {io_paddr_0[48:13], io_paddr_0[12:0] ^ 13'h1000}; // @[PMA.scala:18:7]
wire [48:0] _legal_address_T_5; // @[Parameters.scala:137:31]
assign _legal_address_T_5 = _GEN; // @[Parameters.scala:137:31]
wire [48:0] _io_resp_x_T_29; // @[Parameters.scala:137:31]
assign _io_resp_x_T_29 = _GEN; // @[Parameters.scala:137:31]
wire [49:0] _legal_address_T_6 = {1'h0, _legal_address_T_5}; // @[Parameters.scala:137:{31,41}]
wire [49:0] _legal_address_T_7 = _legal_address_T_6 & 50'h3FFFFFFFFF000; // @[Parameters.scala:137:{41,46}]
wire [49:0] _legal_address_T_8 = _legal_address_T_7; // @[Parameters.scala:137:46]
wire _legal_address_T_9 = _legal_address_T_8 == 50'h0; // @[Parameters.scala:137:{46,59}]
wire _legal_address_WIRE_1 = _legal_address_T_9; // @[Parameters.scala:612:40]
wire [48:0] _GEN_0 = {io_paddr_0[48:14], io_paddr_0[13:0] ^ 14'h3000}; // @[PMA.scala:18:7]
wire [48:0] _legal_address_T_10; // @[Parameters.scala:137:31]
assign _legal_address_T_10 = _GEN_0; // @[Parameters.scala:137:31]
wire [48:0] _io_resp_x_T_5; // @[Parameters.scala:137:31]
assign _io_resp_x_T_5 = _GEN_0; // @[Parameters.scala:137:31]
wire [48:0] _io_resp_eff_T_35; // @[Parameters.scala:137:31]
assign _io_resp_eff_T_35 = _GEN_0; // @[Parameters.scala:137:31]
wire [49:0] _legal_address_T_11 = {1'h0, _legal_address_T_10}; // @[Parameters.scala:137:{31,41}]
wire [49:0] _legal_address_T_12 = _legal_address_T_11 & 50'h3FFFFFFFFF000; // @[Parameters.scala:137:{41,46}]
wire [49:0] _legal_address_T_13 = _legal_address_T_12; // @[Parameters.scala:137:46]
wire _legal_address_T_14 = _legal_address_T_13 == 50'h0; // @[Parameters.scala:137:{46,59}]
wire _legal_address_WIRE_2 = _legal_address_T_14; // @[Parameters.scala:612:40]
wire [48:0] _GEN_1 = {io_paddr_0[48:17], io_paddr_0[16:0] ^ 17'h10000}; // @[PMA.scala:18:7]
wire [48:0] _legal_address_T_15; // @[Parameters.scala:137:31]
assign _legal_address_T_15 = _GEN_1; // @[Parameters.scala:137:31]
wire [48:0] _io_resp_cacheable_T_5; // @[Parameters.scala:137:31]
assign _io_resp_cacheable_T_5 = _GEN_1; // @[Parameters.scala:137:31]
wire [48:0] _io_resp_w_T_41; // @[Parameters.scala:137:31]
assign _io_resp_w_T_41 = _GEN_1; // @[Parameters.scala:137:31]
wire [48:0] _io_resp_pp_T_41; // @[Parameters.scala:137:31]
assign _io_resp_pp_T_41 = _GEN_1; // @[Parameters.scala:137:31]
wire [48:0] _io_resp_al_T_41; // @[Parameters.scala:137:31]
assign _io_resp_al_T_41 = _GEN_1; // @[Parameters.scala:137:31]
wire [48:0] _io_resp_aa_T_41; // @[Parameters.scala:137:31]
assign _io_resp_aa_T_41 = _GEN_1; // @[Parameters.scala:137:31]
wire [48:0] _io_resp_x_T_10; // @[Parameters.scala:137:31]
assign _io_resp_x_T_10 = _GEN_1; // @[Parameters.scala:137:31]
wire [48:0] _io_resp_eff_T_40; // @[Parameters.scala:137:31]
assign _io_resp_eff_T_40 = _GEN_1; // @[Parameters.scala:137:31]
wire [49:0] _legal_address_T_16 = {1'h0, _legal_address_T_15}; // @[Parameters.scala:137:{31,41}]
wire [49:0] _legal_address_T_17 = _legal_address_T_16 & 50'h3FFFFFFFF0000; // @[Parameters.scala:137:{41,46}]
wire [49:0] _legal_address_T_18 = _legal_address_T_17; // @[Parameters.scala:137:46]
wire _legal_address_T_19 = _legal_address_T_18 == 50'h0; // @[Parameters.scala:137:{46,59}]
wire _legal_address_WIRE_3 = _legal_address_T_19; // @[Parameters.scala:612:40]
wire [48:0] _GEN_2 = {io_paddr_0[48:21], io_paddr_0[20:0] ^ 21'h100000}; // @[PMA.scala:18:7]
wire [48:0] _legal_address_T_20; // @[Parameters.scala:137:31]
assign _legal_address_T_20 = _GEN_2; // @[Parameters.scala:137:31]
wire [48:0] _io_resp_w_T_5; // @[Parameters.scala:137:31]
assign _io_resp_w_T_5 = _GEN_2; // @[Parameters.scala:137:31]
wire [48:0] _io_resp_pp_T_5; // @[Parameters.scala:137:31]
assign _io_resp_pp_T_5 = _GEN_2; // @[Parameters.scala:137:31]
wire [48:0] _io_resp_al_T_5; // @[Parameters.scala:137:31]
assign _io_resp_al_T_5 = _GEN_2; // @[Parameters.scala:137:31]
wire [48:0] _io_resp_aa_T_5; // @[Parameters.scala:137:31]
assign _io_resp_aa_T_5 = _GEN_2; // @[Parameters.scala:137:31]
wire [48:0] _io_resp_x_T_34; // @[Parameters.scala:137:31]
assign _io_resp_x_T_34 = _GEN_2; // @[Parameters.scala:137:31]
wire [48:0] _io_resp_eff_T_5; // @[Parameters.scala:137:31]
assign _io_resp_eff_T_5 = _GEN_2; // @[Parameters.scala:137:31]
wire [49:0] _legal_address_T_21 = {1'h0, _legal_address_T_20}; // @[Parameters.scala:137:{31,41}]
wire [49:0] _legal_address_T_22 = _legal_address_T_21 & 50'h3FFFFFFFFF000; // @[Parameters.scala:137:{41,46}]
wire [49:0] _legal_address_T_23 = _legal_address_T_22; // @[Parameters.scala:137:46]
wire _legal_address_T_24 = _legal_address_T_23 == 50'h0; // @[Parameters.scala:137:{46,59}]
wire _legal_address_WIRE_4 = _legal_address_T_24; // @[Parameters.scala:612:40]
wire [48:0] _legal_address_T_25 = {io_paddr_0[48:21], io_paddr_0[20:0] ^ 21'h110000}; // @[PMA.scala:18:7]
wire [49:0] _legal_address_T_26 = {1'h0, _legal_address_T_25}; // @[Parameters.scala:137:{31,41}]
wire [49:0] _legal_address_T_27 = _legal_address_T_26 & 50'h3FFFFFFFFF000; // @[Parameters.scala:137:{41,46}]
wire [49:0] _legal_address_T_28 = _legal_address_T_27; // @[Parameters.scala:137:46]
wire _legal_address_T_29 = _legal_address_T_28 == 50'h0; // @[Parameters.scala:137:{46,59}]
wire _legal_address_WIRE_5 = _legal_address_T_29; // @[Parameters.scala:612:40]
wire [48:0] _GEN_3 = {io_paddr_0[48:26], io_paddr_0[25:0] ^ 26'h2000000}; // @[PMA.scala:18:7]
wire [48:0] _legal_address_T_30; // @[Parameters.scala:137:31]
assign _legal_address_T_30 = _GEN_3; // @[Parameters.scala:137:31]
wire [48:0] _io_resp_x_T_39; // @[Parameters.scala:137:31]
assign _io_resp_x_T_39 = _GEN_3; // @[Parameters.scala:137:31]
wire [48:0] _io_resp_eff_T_10; // @[Parameters.scala:137:31]
assign _io_resp_eff_T_10 = _GEN_3; // @[Parameters.scala:137:31]
wire [49:0] _legal_address_T_31 = {1'h0, _legal_address_T_30}; // @[Parameters.scala:137:{31,41}]
wire [49:0] _legal_address_T_32 = _legal_address_T_31 & 50'h3FFFFFFFF0000; // @[Parameters.scala:137:{41,46}]
wire [49:0] _legal_address_T_33 = _legal_address_T_32; // @[Parameters.scala:137:46]
wire _legal_address_T_34 = _legal_address_T_33 == 50'h0; // @[Parameters.scala:137:{46,59}]
wire _legal_address_WIRE_6 = _legal_address_T_34; // @[Parameters.scala:612:40]
wire [48:0] _GEN_4 = {io_paddr_0[48:26], io_paddr_0[25:0] ^ 26'h2010000}; // @[PMA.scala:18:7]
wire [48:0] _legal_address_T_35; // @[Parameters.scala:137:31]
assign _legal_address_T_35 = _GEN_4; // @[Parameters.scala:137:31]
wire [48:0] _io_resp_w_T_10; // @[Parameters.scala:137:31]
assign _io_resp_w_T_10 = _GEN_4; // @[Parameters.scala:137:31]
wire [48:0] _io_resp_pp_T_10; // @[Parameters.scala:137:31]
assign _io_resp_pp_T_10 = _GEN_4; // @[Parameters.scala:137:31]
wire [48:0] _io_resp_al_T_10; // @[Parameters.scala:137:31]
assign _io_resp_al_T_10 = _GEN_4; // @[Parameters.scala:137:31]
wire [48:0] _io_resp_aa_T_10; // @[Parameters.scala:137:31]
assign _io_resp_aa_T_10 = _GEN_4; // @[Parameters.scala:137:31]
wire [48:0] _io_resp_x_T_44; // @[Parameters.scala:137:31]
assign _io_resp_x_T_44 = _GEN_4; // @[Parameters.scala:137:31]
wire [48:0] _io_resp_eff_T_15; // @[Parameters.scala:137:31]
assign _io_resp_eff_T_15 = _GEN_4; // @[Parameters.scala:137:31]
wire [49:0] _legal_address_T_36 = {1'h0, _legal_address_T_35}; // @[Parameters.scala:137:{31,41}]
wire [49:0] _legal_address_T_37 = _legal_address_T_36 & 50'h3FFFFFFFFF000; // @[Parameters.scala:137:{41,46}]
wire [49:0] _legal_address_T_38 = _legal_address_T_37; // @[Parameters.scala:137:46]
wire _legal_address_T_39 = _legal_address_T_38 == 50'h0; // @[Parameters.scala:137:{46,59}]
wire _legal_address_WIRE_7 = _legal_address_T_39; // @[Parameters.scala:612:40]
wire [48:0] _GEN_5 = {io_paddr_0[48:28], io_paddr_0[27:0] ^ 28'h8000000}; // @[PMA.scala:18:7]
wire [48:0] _legal_address_T_40; // @[Parameters.scala:137:31]
assign _legal_address_T_40 = _GEN_5; // @[Parameters.scala:137:31]
wire [48:0] _io_resp_cacheable_T_17; // @[Parameters.scala:137:31]
assign _io_resp_cacheable_T_17 = _GEN_5; // @[Parameters.scala:137:31]
wire [48:0] _io_resp_w_T_15; // @[Parameters.scala:137:31]
assign _io_resp_w_T_15 = _GEN_5; // @[Parameters.scala:137:31]
wire [48:0] _io_resp_w_T_20; // @[Parameters.scala:137:31]
assign _io_resp_w_T_20 = _GEN_5; // @[Parameters.scala:137:31]
wire [48:0] _io_resp_pp_T_15; // @[Parameters.scala:137:31]
assign _io_resp_pp_T_15 = _GEN_5; // @[Parameters.scala:137:31]
wire [48:0] _io_resp_pp_T_20; // @[Parameters.scala:137:31]
assign _io_resp_pp_T_20 = _GEN_5; // @[Parameters.scala:137:31]
wire [48:0] _io_resp_al_T_15; // @[Parameters.scala:137:31]
assign _io_resp_al_T_15 = _GEN_5; // @[Parameters.scala:137:31]
wire [48:0] _io_resp_al_T_20; // @[Parameters.scala:137:31]
assign _io_resp_al_T_20 = _GEN_5; // @[Parameters.scala:137:31]
wire [48:0] _io_resp_aa_T_15; // @[Parameters.scala:137:31]
assign _io_resp_aa_T_15 = _GEN_5; // @[Parameters.scala:137:31]
wire [48:0] _io_resp_aa_T_20; // @[Parameters.scala:137:31]
assign _io_resp_aa_T_20 = _GEN_5; // @[Parameters.scala:137:31]
wire [48:0] _io_resp_x_T_15; // @[Parameters.scala:137:31]
assign _io_resp_x_T_15 = _GEN_5; // @[Parameters.scala:137:31]
wire [48:0] _io_resp_eff_T_45; // @[Parameters.scala:137:31]
assign _io_resp_eff_T_45 = _GEN_5; // @[Parameters.scala:137:31]
wire [49:0] _legal_address_T_41 = {1'h0, _legal_address_T_40}; // @[Parameters.scala:137:{31,41}]
wire [49:0] _legal_address_T_42 = _legal_address_T_41 & 50'h3FFFFFFFF0000; // @[Parameters.scala:137:{41,46}]
wire [49:0] _legal_address_T_43 = _legal_address_T_42; // @[Parameters.scala:137:46]
wire _legal_address_T_44 = _legal_address_T_43 == 50'h0; // @[Parameters.scala:137:{46,59}]
wire _legal_address_WIRE_8 = _legal_address_T_44; // @[Parameters.scala:612:40]
wire [48:0] _GEN_6 = {io_paddr_0[48:28], io_paddr_0[27:0] ^ 28'hC000000}; // @[PMA.scala:18:7]
wire [48:0] _legal_address_T_45; // @[Parameters.scala:137:31]
assign _legal_address_T_45 = _GEN_6; // @[Parameters.scala:137:31]
wire [48:0] _io_resp_cacheable_T_10; // @[Parameters.scala:137:31]
assign _io_resp_cacheable_T_10 = _GEN_6; // @[Parameters.scala:137:31]
wire [48:0] _io_resp_x_T_49; // @[Parameters.scala:137:31]
assign _io_resp_x_T_49 = _GEN_6; // @[Parameters.scala:137:31]
wire [48:0] _io_resp_eff_T_20; // @[Parameters.scala:137:31]
assign _io_resp_eff_T_20 = _GEN_6; // @[Parameters.scala:137:31]
wire [49:0] _legal_address_T_46 = {1'h0, _legal_address_T_45}; // @[Parameters.scala:137:{31,41}]
wire [49:0] _legal_address_T_47 = _legal_address_T_46 & 50'h3FFFFFC000000; // @[Parameters.scala:137:{41,46}]
wire [49:0] _legal_address_T_48 = _legal_address_T_47; // @[Parameters.scala:137:46]
wire _legal_address_T_49 = _legal_address_T_48 == 50'h0; // @[Parameters.scala:137:{46,59}]
wire _legal_address_WIRE_9 = _legal_address_T_49; // @[Parameters.scala:612:40]
wire [48:0] _legal_address_T_50 = {io_paddr_0[48:29], io_paddr_0[28:0] ^ 29'h10020000}; // @[PMA.scala:18:7]
wire [49:0] _legal_address_T_51 = {1'h0, _legal_address_T_50}; // @[Parameters.scala:137:{31,41}]
wire [49:0] _legal_address_T_52 = _legal_address_T_51 & 50'h3FFFFFFFFF000; // @[Parameters.scala:137:{41,46}]
wire [49:0] _legal_address_T_53 = _legal_address_T_52; // @[Parameters.scala:137:46]
wire _legal_address_T_54 = _legal_address_T_53 == 50'h0; // @[Parameters.scala:137:{46,59}]
wire _legal_address_WIRE_10 = _legal_address_T_54; // @[Parameters.scala:612:40]
wire [48:0] _GEN_7 = {io_paddr_0[48:32], io_paddr_0[31:0] ^ 32'h80000000}; // @[PMA.scala:18:7]
wire [48:0] _legal_address_T_55; // @[Parameters.scala:137:31]
assign _legal_address_T_55 = _GEN_7; // @[Parameters.scala:137:31]
wire [48:0] _io_resp_cacheable_T_22; // @[Parameters.scala:137:31]
assign _io_resp_cacheable_T_22 = _GEN_7; // @[Parameters.scala:137:31]
wire [48:0] _io_resp_w_T_30; // @[Parameters.scala:137:31]
assign _io_resp_w_T_30 = _GEN_7; // @[Parameters.scala:137:31]
wire [48:0] _io_resp_pp_T_30; // @[Parameters.scala:137:31]
assign _io_resp_pp_T_30 = _GEN_7; // @[Parameters.scala:137:31]
wire [48:0] _io_resp_al_T_30; // @[Parameters.scala:137:31]
assign _io_resp_al_T_30 = _GEN_7; // @[Parameters.scala:137:31]
wire [48:0] _io_resp_aa_T_30; // @[Parameters.scala:137:31]
assign _io_resp_aa_T_30 = _GEN_7; // @[Parameters.scala:137:31]
wire [48:0] _io_resp_x_T_20; // @[Parameters.scala:137:31]
assign _io_resp_x_T_20 = _GEN_7; // @[Parameters.scala:137:31]
wire [48:0] _io_resp_eff_T_50; // @[Parameters.scala:137:31]
assign _io_resp_eff_T_50 = _GEN_7; // @[Parameters.scala:137:31]
wire [49:0] _legal_address_T_56 = {1'h0, _legal_address_T_55}; // @[Parameters.scala:137:{31,41}]
wire [49:0] _legal_address_T_57 = _legal_address_T_56 & 50'h3FFFFF0000000; // @[Parameters.scala:137:{41,46}]
wire [49:0] _legal_address_T_58 = _legal_address_T_57; // @[Parameters.scala:137:46]
wire _legal_address_T_59 = _legal_address_T_58 == 50'h0; // @[Parameters.scala:137:{46,59}]
wire _legal_address_WIRE_11 = _legal_address_T_59; // @[Parameters.scala:612:40]
wire _legal_address_T_60 = _legal_address_WIRE_0 | _legal_address_WIRE_1; // @[Parameters.scala:612:40]
wire _legal_address_T_61 = _legal_address_T_60 | _legal_address_WIRE_2; // @[Parameters.scala:612:40]
wire _legal_address_T_62 = _legal_address_T_61 | _legal_address_WIRE_3; // @[Parameters.scala:612:40]
wire _legal_address_T_63 = _legal_address_T_62 | _legal_address_WIRE_4; // @[Parameters.scala:612:40]
wire _legal_address_T_64 = _legal_address_T_63 | _legal_address_WIRE_5; // @[Parameters.scala:612:40]
wire _legal_address_T_65 = _legal_address_T_64 | _legal_address_WIRE_6; // @[Parameters.scala:612:40]
wire _legal_address_T_66 = _legal_address_T_65 | _legal_address_WIRE_7; // @[Parameters.scala:612:40]
wire _legal_address_T_67 = _legal_address_T_66 | _legal_address_WIRE_8; // @[Parameters.scala:612:40]
wire _legal_address_T_68 = _legal_address_T_67 | _legal_address_WIRE_9; // @[Parameters.scala:612:40]
wire _legal_address_T_69 = _legal_address_T_68 | _legal_address_WIRE_10; // @[Parameters.scala:612:40]
wire legal_address = _legal_address_T_69 | _legal_address_WIRE_11; // @[Parameters.scala:612:40]
assign _io_resp_r_T_5 = legal_address; // @[PMA.scala:36:58, :39:19]
wire [49:0] _io_resp_cacheable_T_1 = {1'h0, _io_resp_cacheable_T}; // @[Parameters.scala:137:{31,41}]
wire [49:0] _io_resp_cacheable_T_2 = _io_resp_cacheable_T_1 & 50'h8C000000; // @[Parameters.scala:137:{41,46}]
wire [49:0] _io_resp_cacheable_T_3 = _io_resp_cacheable_T_2; // @[Parameters.scala:137:46]
wire _io_resp_cacheable_T_4 = _io_resp_cacheable_T_3 == 50'h0; // @[Parameters.scala:137:{46,59}]
wire [49:0] _io_resp_cacheable_T_6 = {1'h0, _io_resp_cacheable_T_5}; // @[Parameters.scala:137:{31,41}]
wire [49:0] _io_resp_cacheable_T_7 = _io_resp_cacheable_T_6 & 50'h8C011000; // @[Parameters.scala:137:{41,46}]
wire [49:0] _io_resp_cacheable_T_8 = _io_resp_cacheable_T_7; // @[Parameters.scala:137:46]
wire _io_resp_cacheable_T_9 = _io_resp_cacheable_T_8 == 50'h0; // @[Parameters.scala:137:{46,59}]
wire [49:0] _io_resp_cacheable_T_11 = {1'h0, _io_resp_cacheable_T_10}; // @[Parameters.scala:137:{31,41}]
wire [49:0] _io_resp_cacheable_T_12 = _io_resp_cacheable_T_11 & 50'h8C000000; // @[Parameters.scala:137:{41,46}]
wire [49:0] _io_resp_cacheable_T_13 = _io_resp_cacheable_T_12; // @[Parameters.scala:137:46]
wire _io_resp_cacheable_T_14 = _io_resp_cacheable_T_13 == 50'h0; // @[Parameters.scala:137:{46,59}]
wire _io_resp_cacheable_T_15 = _io_resp_cacheable_T_4 | _io_resp_cacheable_T_9; // @[Parameters.scala:629:89]
wire _io_resp_cacheable_T_16 = _io_resp_cacheable_T_15 | _io_resp_cacheable_T_14; // @[Parameters.scala:629:89]
wire [49:0] _io_resp_cacheable_T_18 = {1'h0, _io_resp_cacheable_T_17}; // @[Parameters.scala:137:{31,41}]
wire [49:0] _io_resp_cacheable_T_19 = _io_resp_cacheable_T_18 & 50'h8C010000; // @[Parameters.scala:137:{41,46}]
wire [49:0] _io_resp_cacheable_T_20 = _io_resp_cacheable_T_19; // @[Parameters.scala:137:46]
wire _io_resp_cacheable_T_21 = _io_resp_cacheable_T_20 == 50'h0; // @[Parameters.scala:137:{46,59}]
wire [49:0] _io_resp_cacheable_T_23 = {1'h0, _io_resp_cacheable_T_22}; // @[Parameters.scala:137:{31,41}]
wire [49:0] _io_resp_cacheable_T_24 = _io_resp_cacheable_T_23 & 50'h80000000; // @[Parameters.scala:137:{41,46}]
wire [49:0] _io_resp_cacheable_T_25 = _io_resp_cacheable_T_24; // @[Parameters.scala:137:46]
wire _io_resp_cacheable_T_26 = _io_resp_cacheable_T_25 == 50'h0; // @[Parameters.scala:137:{46,59}]
wire _io_resp_cacheable_T_27 = _io_resp_cacheable_T_21 | _io_resp_cacheable_T_26; // @[Parameters.scala:629:89]
wire _io_resp_cacheable_T_29 = _io_resp_cacheable_T_27; // @[Mux.scala:30:73]
wire _io_resp_cacheable_T_30 = _io_resp_cacheable_T_29; // @[Mux.scala:30:73]
wire _io_resp_cacheable_WIRE = _io_resp_cacheable_T_30; // @[Mux.scala:30:73]
assign _io_resp_cacheable_T_31 = legal_address & _io_resp_cacheable_WIRE; // @[Mux.scala:30:73]
assign io_resp_cacheable_0 = _io_resp_cacheable_T_31; // @[PMA.scala:18:7, :39:19]
wire [49:0] _io_resp_r_T_1 = {1'h0, _io_resp_r_T}; // @[Parameters.scala:137:{31,41}]
assign io_resp_r_0 = _io_resp_r_T_5; // @[PMA.scala:18:7, :39:19]
wire [49:0] _io_resp_w_T_1 = {1'h0, _io_resp_w_T}; // @[Parameters.scala:137:{31,41}]
wire [49:0] _io_resp_w_T_2 = _io_resp_w_T_1 & 50'h98110000; // @[Parameters.scala:137:{41,46}]
wire [49:0] _io_resp_w_T_3 = _io_resp_w_T_2; // @[Parameters.scala:137:46]
wire _io_resp_w_T_4 = _io_resp_w_T_3 == 50'h0; // @[Parameters.scala:137:{46,59}]
wire [49:0] _io_resp_w_T_6 = {1'h0, _io_resp_w_T_5}; // @[Parameters.scala:137:{31,41}]
wire [49:0] _io_resp_w_T_7 = _io_resp_w_T_6 & 50'h9A101000; // @[Parameters.scala:137:{41,46}]
wire [49:0] _io_resp_w_T_8 = _io_resp_w_T_7; // @[Parameters.scala:137:46]
wire _io_resp_w_T_9 = _io_resp_w_T_8 == 50'h0; // @[Parameters.scala:137:{46,59}]
wire [49:0] _io_resp_w_T_11 = {1'h0, _io_resp_w_T_10}; // @[Parameters.scala:137:{31,41}]
wire [49:0] _io_resp_w_T_12 = _io_resp_w_T_11 & 50'h9A111000; // @[Parameters.scala:137:{41,46}]
wire [49:0] _io_resp_w_T_13 = _io_resp_w_T_12; // @[Parameters.scala:137:46]
wire _io_resp_w_T_14 = _io_resp_w_T_13 == 50'h0; // @[Parameters.scala:137:{46,59}]
wire [49:0] _io_resp_w_T_16 = {1'h0, _io_resp_w_T_15}; // @[Parameters.scala:137:{31,41}]
wire [49:0] _io_resp_w_T_17 = _io_resp_w_T_16 & 50'h98000000; // @[Parameters.scala:137:{41,46}]
wire [49:0] _io_resp_w_T_18 = _io_resp_w_T_17; // @[Parameters.scala:137:46]
wire _io_resp_w_T_19 = _io_resp_w_T_18 == 50'h0; // @[Parameters.scala:137:{46,59}]
wire [49:0] _io_resp_w_T_21 = {1'h0, _io_resp_w_T_20}; // @[Parameters.scala:137:{31,41}]
wire [49:0] _io_resp_w_T_22 = _io_resp_w_T_21 & 50'h9A110000; // @[Parameters.scala:137:{41,46}]
wire [49:0] _io_resp_w_T_23 = _io_resp_w_T_22; // @[Parameters.scala:137:46]
wire _io_resp_w_T_24 = _io_resp_w_T_23 == 50'h0; // @[Parameters.scala:137:{46,59}]
wire [48:0] _GEN_8 = {io_paddr_0[48:29], io_paddr_0[28:0] ^ 29'h10000000}; // @[PMA.scala:18:7]
wire [48:0] _io_resp_w_T_25; // @[Parameters.scala:137:31]
assign _io_resp_w_T_25 = _GEN_8; // @[Parameters.scala:137:31]
wire [48:0] _io_resp_pp_T_25; // @[Parameters.scala:137:31]
assign _io_resp_pp_T_25 = _GEN_8; // @[Parameters.scala:137:31]
wire [48:0] _io_resp_al_T_25; // @[Parameters.scala:137:31]
assign _io_resp_al_T_25 = _GEN_8; // @[Parameters.scala:137:31]
wire [48:0] _io_resp_aa_T_25; // @[Parameters.scala:137:31]
assign _io_resp_aa_T_25 = _GEN_8; // @[Parameters.scala:137:31]
wire [48:0] _io_resp_x_T_54; // @[Parameters.scala:137:31]
assign _io_resp_x_T_54 = _GEN_8; // @[Parameters.scala:137:31]
wire [48:0] _io_resp_eff_T_25; // @[Parameters.scala:137:31]
assign _io_resp_eff_T_25 = _GEN_8; // @[Parameters.scala:137:31]
wire [49:0] _io_resp_w_T_26 = {1'h0, _io_resp_w_T_25}; // @[Parameters.scala:137:{31,41}]
wire [49:0] _io_resp_w_T_27 = _io_resp_w_T_26 & 50'h9A111000; // @[Parameters.scala:137:{41,46}]
wire [49:0] _io_resp_w_T_28 = _io_resp_w_T_27; // @[Parameters.scala:137:46]
wire _io_resp_w_T_29 = _io_resp_w_T_28 == 50'h0; // @[Parameters.scala:137:{46,59}]
wire [49:0] _io_resp_w_T_31 = {1'h0, _io_resp_w_T_30}; // @[Parameters.scala:137:{31,41}]
wire [49:0] _io_resp_w_T_32 = _io_resp_w_T_31 & 50'h90000000; // @[Parameters.scala:137:{41,46}]
wire [49:0] _io_resp_w_T_33 = _io_resp_w_T_32; // @[Parameters.scala:137:46]
wire _io_resp_w_T_34 = _io_resp_w_T_33 == 50'h0; // @[Parameters.scala:137:{46,59}]
wire _io_resp_w_T_35 = _io_resp_w_T_4 | _io_resp_w_T_9; // @[Parameters.scala:629:89]
wire _io_resp_w_T_36 = _io_resp_w_T_35 | _io_resp_w_T_14; // @[Parameters.scala:629:89]
wire _io_resp_w_T_37 = _io_resp_w_T_36 | _io_resp_w_T_19; // @[Parameters.scala:629:89]
wire _io_resp_w_T_38 = _io_resp_w_T_37 | _io_resp_w_T_24; // @[Parameters.scala:629:89]
wire _io_resp_w_T_39 = _io_resp_w_T_38 | _io_resp_w_T_29; // @[Parameters.scala:629:89]
wire _io_resp_w_T_40 = _io_resp_w_T_39 | _io_resp_w_T_34; // @[Parameters.scala:629:89]
wire _io_resp_w_T_46 = _io_resp_w_T_40; // @[Mux.scala:30:73]
wire [49:0] _io_resp_w_T_42 = {1'h0, _io_resp_w_T_41}; // @[Parameters.scala:137:{31,41}]
wire [49:0] _io_resp_w_T_43 = _io_resp_w_T_42 & 50'h9A110000; // @[Parameters.scala:137:{41,46}]
wire [49:0] _io_resp_w_T_44 = _io_resp_w_T_43; // @[Parameters.scala:137:46]
wire _io_resp_w_T_45 = _io_resp_w_T_44 == 50'h0; // @[Parameters.scala:137:{46,59}]
wire _io_resp_w_T_48 = _io_resp_w_T_46; // @[Mux.scala:30:73]
wire _io_resp_w_WIRE = _io_resp_w_T_48; // @[Mux.scala:30:73]
assign _io_resp_w_T_49 = legal_address & _io_resp_w_WIRE; // @[Mux.scala:30:73]
assign io_resp_w_0 = _io_resp_w_T_49; // @[PMA.scala:18:7, :39:19]
wire [49:0] _io_resp_pp_T_1 = {1'h0, _io_resp_pp_T}; // @[Parameters.scala:137:{31,41}]
wire [49:0] _io_resp_pp_T_2 = _io_resp_pp_T_1 & 50'h98110000; // @[Parameters.scala:137:{41,46}]
wire [49:0] _io_resp_pp_T_3 = _io_resp_pp_T_2; // @[Parameters.scala:137:46]
wire _io_resp_pp_T_4 = _io_resp_pp_T_3 == 50'h0; // @[Parameters.scala:137:{46,59}]
wire [49:0] _io_resp_pp_T_6 = {1'h0, _io_resp_pp_T_5}; // @[Parameters.scala:137:{31,41}]
wire [49:0] _io_resp_pp_T_7 = _io_resp_pp_T_6 & 50'h9A101000; // @[Parameters.scala:137:{41,46}]
wire [49:0] _io_resp_pp_T_8 = _io_resp_pp_T_7; // @[Parameters.scala:137:46]
wire _io_resp_pp_T_9 = _io_resp_pp_T_8 == 50'h0; // @[Parameters.scala:137:{46,59}]
wire [49:0] _io_resp_pp_T_11 = {1'h0, _io_resp_pp_T_10}; // @[Parameters.scala:137:{31,41}]
wire [49:0] _io_resp_pp_T_12 = _io_resp_pp_T_11 & 50'h9A111000; // @[Parameters.scala:137:{41,46}]
wire [49:0] _io_resp_pp_T_13 = _io_resp_pp_T_12; // @[Parameters.scala:137:46]
wire _io_resp_pp_T_14 = _io_resp_pp_T_13 == 50'h0; // @[Parameters.scala:137:{46,59}]
wire [49:0] _io_resp_pp_T_16 = {1'h0, _io_resp_pp_T_15}; // @[Parameters.scala:137:{31,41}]
wire [49:0] _io_resp_pp_T_17 = _io_resp_pp_T_16 & 50'h98000000; // @[Parameters.scala:137:{41,46}]
wire [49:0] _io_resp_pp_T_18 = _io_resp_pp_T_17; // @[Parameters.scala:137:46]
wire _io_resp_pp_T_19 = _io_resp_pp_T_18 == 50'h0; // @[Parameters.scala:137:{46,59}]
wire [49:0] _io_resp_pp_T_21 = {1'h0, _io_resp_pp_T_20}; // @[Parameters.scala:137:{31,41}]
wire [49:0] _io_resp_pp_T_22 = _io_resp_pp_T_21 & 50'h9A110000; // @[Parameters.scala:137:{41,46}]
wire [49:0] _io_resp_pp_T_23 = _io_resp_pp_T_22; // @[Parameters.scala:137:46]
wire _io_resp_pp_T_24 = _io_resp_pp_T_23 == 50'h0; // @[Parameters.scala:137:{46,59}]
wire [49:0] _io_resp_pp_T_26 = {1'h0, _io_resp_pp_T_25}; // @[Parameters.scala:137:{31,41}]
wire [49:0] _io_resp_pp_T_27 = _io_resp_pp_T_26 & 50'h9A111000; // @[Parameters.scala:137:{41,46}]
wire [49:0] _io_resp_pp_T_28 = _io_resp_pp_T_27; // @[Parameters.scala:137:46]
wire _io_resp_pp_T_29 = _io_resp_pp_T_28 == 50'h0; // @[Parameters.scala:137:{46,59}]
wire [49:0] _io_resp_pp_T_31 = {1'h0, _io_resp_pp_T_30}; // @[Parameters.scala:137:{31,41}]
wire [49:0] _io_resp_pp_T_32 = _io_resp_pp_T_31 & 50'h90000000; // @[Parameters.scala:137:{41,46}]
wire [49:0] _io_resp_pp_T_33 = _io_resp_pp_T_32; // @[Parameters.scala:137:46]
wire _io_resp_pp_T_34 = _io_resp_pp_T_33 == 50'h0; // @[Parameters.scala:137:{46,59}]
wire _io_resp_pp_T_35 = _io_resp_pp_T_4 | _io_resp_pp_T_9; // @[Parameters.scala:629:89]
wire _io_resp_pp_T_36 = _io_resp_pp_T_35 | _io_resp_pp_T_14; // @[Parameters.scala:629:89]
wire _io_resp_pp_T_37 = _io_resp_pp_T_36 | _io_resp_pp_T_19; // @[Parameters.scala:629:89]
wire _io_resp_pp_T_38 = _io_resp_pp_T_37 | _io_resp_pp_T_24; // @[Parameters.scala:629:89]
wire _io_resp_pp_T_39 = _io_resp_pp_T_38 | _io_resp_pp_T_29; // @[Parameters.scala:629:89]
wire _io_resp_pp_T_40 = _io_resp_pp_T_39 | _io_resp_pp_T_34; // @[Parameters.scala:629:89]
wire _io_resp_pp_T_46 = _io_resp_pp_T_40; // @[Mux.scala:30:73]
wire [49:0] _io_resp_pp_T_42 = {1'h0, _io_resp_pp_T_41}; // @[Parameters.scala:137:{31,41}]
wire [49:0] _io_resp_pp_T_43 = _io_resp_pp_T_42 & 50'h9A110000; // @[Parameters.scala:137:{41,46}]
wire [49:0] _io_resp_pp_T_44 = _io_resp_pp_T_43; // @[Parameters.scala:137:46]
wire _io_resp_pp_T_45 = _io_resp_pp_T_44 == 50'h0; // @[Parameters.scala:137:{46,59}]
wire _io_resp_pp_T_48 = _io_resp_pp_T_46; // @[Mux.scala:30:73]
wire _io_resp_pp_WIRE = _io_resp_pp_T_48; // @[Mux.scala:30:73]
assign _io_resp_pp_T_49 = legal_address & _io_resp_pp_WIRE; // @[Mux.scala:30:73]
assign io_resp_pp_0 = _io_resp_pp_T_49; // @[PMA.scala:18:7, :39:19]
wire [49:0] _io_resp_al_T_1 = {1'h0, _io_resp_al_T}; // @[Parameters.scala:137:{31,41}]
wire [49:0] _io_resp_al_T_2 = _io_resp_al_T_1 & 50'h98110000; // @[Parameters.scala:137:{41,46}]
wire [49:0] _io_resp_al_T_3 = _io_resp_al_T_2; // @[Parameters.scala:137:46]
wire _io_resp_al_T_4 = _io_resp_al_T_3 == 50'h0; // @[Parameters.scala:137:{46,59}]
wire [49:0] _io_resp_al_T_6 = {1'h0, _io_resp_al_T_5}; // @[Parameters.scala:137:{31,41}]
wire [49:0] _io_resp_al_T_7 = _io_resp_al_T_6 & 50'h9A101000; // @[Parameters.scala:137:{41,46}]
wire [49:0] _io_resp_al_T_8 = _io_resp_al_T_7; // @[Parameters.scala:137:46]
wire _io_resp_al_T_9 = _io_resp_al_T_8 == 50'h0; // @[Parameters.scala:137:{46,59}]
wire [49:0] _io_resp_al_T_11 = {1'h0, _io_resp_al_T_10}; // @[Parameters.scala:137:{31,41}]
wire [49:0] _io_resp_al_T_12 = _io_resp_al_T_11 & 50'h9A111000; // @[Parameters.scala:137:{41,46}]
wire [49:0] _io_resp_al_T_13 = _io_resp_al_T_12; // @[Parameters.scala:137:46]
wire _io_resp_al_T_14 = _io_resp_al_T_13 == 50'h0; // @[Parameters.scala:137:{46,59}]
wire [49:0] _io_resp_al_T_16 = {1'h0, _io_resp_al_T_15}; // @[Parameters.scala:137:{31,41}]
wire [49:0] _io_resp_al_T_17 = _io_resp_al_T_16 & 50'h98000000; // @[Parameters.scala:137:{41,46}]
wire [49:0] _io_resp_al_T_18 = _io_resp_al_T_17; // @[Parameters.scala:137:46]
wire _io_resp_al_T_19 = _io_resp_al_T_18 == 50'h0; // @[Parameters.scala:137:{46,59}]
wire [49:0] _io_resp_al_T_21 = {1'h0, _io_resp_al_T_20}; // @[Parameters.scala:137:{31,41}]
wire [49:0] _io_resp_al_T_22 = _io_resp_al_T_21 & 50'h9A110000; // @[Parameters.scala:137:{41,46}]
wire [49:0] _io_resp_al_T_23 = _io_resp_al_T_22; // @[Parameters.scala:137:46]
wire _io_resp_al_T_24 = _io_resp_al_T_23 == 50'h0; // @[Parameters.scala:137:{46,59}]
wire [49:0] _io_resp_al_T_26 = {1'h0, _io_resp_al_T_25}; // @[Parameters.scala:137:{31,41}]
wire [49:0] _io_resp_al_T_27 = _io_resp_al_T_26 & 50'h9A111000; // @[Parameters.scala:137:{41,46}]
wire [49:0] _io_resp_al_T_28 = _io_resp_al_T_27; // @[Parameters.scala:137:46]
wire _io_resp_al_T_29 = _io_resp_al_T_28 == 50'h0; // @[Parameters.scala:137:{46,59}]
wire [49:0] _io_resp_al_T_31 = {1'h0, _io_resp_al_T_30}; // @[Parameters.scala:137:{31,41}]
wire [49:0] _io_resp_al_T_32 = _io_resp_al_T_31 & 50'h90000000; // @[Parameters.scala:137:{41,46}]
wire [49:0] _io_resp_al_T_33 = _io_resp_al_T_32; // @[Parameters.scala:137:46]
wire _io_resp_al_T_34 = _io_resp_al_T_33 == 50'h0; // @[Parameters.scala:137:{46,59}]
wire _io_resp_al_T_35 = _io_resp_al_T_4 | _io_resp_al_T_9; // @[Parameters.scala:629:89]
wire _io_resp_al_T_36 = _io_resp_al_T_35 | _io_resp_al_T_14; // @[Parameters.scala:629:89]
wire _io_resp_al_T_37 = _io_resp_al_T_36 | _io_resp_al_T_19; // @[Parameters.scala:629:89]
wire _io_resp_al_T_38 = _io_resp_al_T_37 | _io_resp_al_T_24; // @[Parameters.scala:629:89]
wire _io_resp_al_T_39 = _io_resp_al_T_38 | _io_resp_al_T_29; // @[Parameters.scala:629:89]
wire _io_resp_al_T_40 = _io_resp_al_T_39 | _io_resp_al_T_34; // @[Parameters.scala:629:89]
wire _io_resp_al_T_46 = _io_resp_al_T_40; // @[Mux.scala:30:73]
wire [49:0] _io_resp_al_T_42 = {1'h0, _io_resp_al_T_41}; // @[Parameters.scala:137:{31,41}]
wire [49:0] _io_resp_al_T_43 = _io_resp_al_T_42 & 50'h9A110000; // @[Parameters.scala:137:{41,46}]
wire [49:0] _io_resp_al_T_44 = _io_resp_al_T_43; // @[Parameters.scala:137:46]
wire _io_resp_al_T_45 = _io_resp_al_T_44 == 50'h0; // @[Parameters.scala:137:{46,59}]
wire _io_resp_al_T_48 = _io_resp_al_T_46; // @[Mux.scala:30:73]
wire _io_resp_al_WIRE = _io_resp_al_T_48; // @[Mux.scala:30:73]
assign _io_resp_al_T_49 = legal_address & _io_resp_al_WIRE; // @[Mux.scala:30:73]
assign io_resp_al_0 = _io_resp_al_T_49; // @[PMA.scala:18:7, :39:19]
wire [49:0] _io_resp_aa_T_1 = {1'h0, _io_resp_aa_T}; // @[Parameters.scala:137:{31,41}]
wire [49:0] _io_resp_aa_T_2 = _io_resp_aa_T_1 & 50'h98110000; // @[Parameters.scala:137:{41,46}]
wire [49:0] _io_resp_aa_T_3 = _io_resp_aa_T_2; // @[Parameters.scala:137:46]
wire _io_resp_aa_T_4 = _io_resp_aa_T_3 == 50'h0; // @[Parameters.scala:137:{46,59}]
wire [49:0] _io_resp_aa_T_6 = {1'h0, _io_resp_aa_T_5}; // @[Parameters.scala:137:{31,41}]
wire [49:0] _io_resp_aa_T_7 = _io_resp_aa_T_6 & 50'h9A101000; // @[Parameters.scala:137:{41,46}]
wire [49:0] _io_resp_aa_T_8 = _io_resp_aa_T_7; // @[Parameters.scala:137:46]
wire _io_resp_aa_T_9 = _io_resp_aa_T_8 == 50'h0; // @[Parameters.scala:137:{46,59}]
wire [49:0] _io_resp_aa_T_11 = {1'h0, _io_resp_aa_T_10}; // @[Parameters.scala:137:{31,41}]
wire [49:0] _io_resp_aa_T_12 = _io_resp_aa_T_11 & 50'h9A111000; // @[Parameters.scala:137:{41,46}]
wire [49:0] _io_resp_aa_T_13 = _io_resp_aa_T_12; // @[Parameters.scala:137:46]
wire _io_resp_aa_T_14 = _io_resp_aa_T_13 == 50'h0; // @[Parameters.scala:137:{46,59}]
wire [49:0] _io_resp_aa_T_16 = {1'h0, _io_resp_aa_T_15}; // @[Parameters.scala:137:{31,41}]
wire [49:0] _io_resp_aa_T_17 = _io_resp_aa_T_16 & 50'h98000000; // @[Parameters.scala:137:{41,46}]
wire [49:0] _io_resp_aa_T_18 = _io_resp_aa_T_17; // @[Parameters.scala:137:46]
wire _io_resp_aa_T_19 = _io_resp_aa_T_18 == 50'h0; // @[Parameters.scala:137:{46,59}]
wire [49:0] _io_resp_aa_T_21 = {1'h0, _io_resp_aa_T_20}; // @[Parameters.scala:137:{31,41}]
wire [49:0] _io_resp_aa_T_22 = _io_resp_aa_T_21 & 50'h9A110000; // @[Parameters.scala:137:{41,46}]
wire [49:0] _io_resp_aa_T_23 = _io_resp_aa_T_22; // @[Parameters.scala:137:46]
wire _io_resp_aa_T_24 = _io_resp_aa_T_23 == 50'h0; // @[Parameters.scala:137:{46,59}]
wire [49:0] _io_resp_aa_T_26 = {1'h0, _io_resp_aa_T_25}; // @[Parameters.scala:137:{31,41}]
wire [49:0] _io_resp_aa_T_27 = _io_resp_aa_T_26 & 50'h9A111000; // @[Parameters.scala:137:{41,46}]
wire [49:0] _io_resp_aa_T_28 = _io_resp_aa_T_27; // @[Parameters.scala:137:46]
wire _io_resp_aa_T_29 = _io_resp_aa_T_28 == 50'h0; // @[Parameters.scala:137:{46,59}]
wire [49:0] _io_resp_aa_T_31 = {1'h0, _io_resp_aa_T_30}; // @[Parameters.scala:137:{31,41}]
wire [49:0] _io_resp_aa_T_32 = _io_resp_aa_T_31 & 50'h90000000; // @[Parameters.scala:137:{41,46}]
wire [49:0] _io_resp_aa_T_33 = _io_resp_aa_T_32; // @[Parameters.scala:137:46]
wire _io_resp_aa_T_34 = _io_resp_aa_T_33 == 50'h0; // @[Parameters.scala:137:{46,59}]
wire _io_resp_aa_T_35 = _io_resp_aa_T_4 | _io_resp_aa_T_9; // @[Parameters.scala:629:89]
wire _io_resp_aa_T_36 = _io_resp_aa_T_35 | _io_resp_aa_T_14; // @[Parameters.scala:629:89]
wire _io_resp_aa_T_37 = _io_resp_aa_T_36 | _io_resp_aa_T_19; // @[Parameters.scala:629:89]
wire _io_resp_aa_T_38 = _io_resp_aa_T_37 | _io_resp_aa_T_24; // @[Parameters.scala:629:89]
wire _io_resp_aa_T_39 = _io_resp_aa_T_38 | _io_resp_aa_T_29; // @[Parameters.scala:629:89]
wire _io_resp_aa_T_40 = _io_resp_aa_T_39 | _io_resp_aa_T_34; // @[Parameters.scala:629:89]
wire _io_resp_aa_T_46 = _io_resp_aa_T_40; // @[Mux.scala:30:73]
wire [49:0] _io_resp_aa_T_42 = {1'h0, _io_resp_aa_T_41}; // @[Parameters.scala:137:{31,41}]
wire [49:0] _io_resp_aa_T_43 = _io_resp_aa_T_42 & 50'h9A110000; // @[Parameters.scala:137:{41,46}]
wire [49:0] _io_resp_aa_T_44 = _io_resp_aa_T_43; // @[Parameters.scala:137:46]
wire _io_resp_aa_T_45 = _io_resp_aa_T_44 == 50'h0; // @[Parameters.scala:137:{46,59}]
wire _io_resp_aa_T_48 = _io_resp_aa_T_46; // @[Mux.scala:30:73]
wire _io_resp_aa_WIRE = _io_resp_aa_T_48; // @[Mux.scala:30:73]
assign _io_resp_aa_T_49 = legal_address & _io_resp_aa_WIRE; // @[Mux.scala:30:73]
assign io_resp_aa_0 = _io_resp_aa_T_49; // @[PMA.scala:18:7, :39:19]
wire [49:0] _io_resp_x_T_1 = {1'h0, _io_resp_x_T}; // @[Parameters.scala:137:{31,41}]
wire [49:0] _io_resp_x_T_2 = _io_resp_x_T_1 & 50'h9E113000; // @[Parameters.scala:137:{41,46}]
wire [49:0] _io_resp_x_T_3 = _io_resp_x_T_2; // @[Parameters.scala:137:46]
wire _io_resp_x_T_4 = _io_resp_x_T_3 == 50'h0; // @[Parameters.scala:137:{46,59}]
wire [49:0] _io_resp_x_T_6 = {1'h0, _io_resp_x_T_5}; // @[Parameters.scala:137:{31,41}]
wire [49:0] _io_resp_x_T_7 = _io_resp_x_T_6 & 50'h9E113000; // @[Parameters.scala:137:{41,46}]
wire [49:0] _io_resp_x_T_8 = _io_resp_x_T_7; // @[Parameters.scala:137:46]
wire _io_resp_x_T_9 = _io_resp_x_T_8 == 50'h0; // @[Parameters.scala:137:{46,59}]
wire [49:0] _io_resp_x_T_11 = {1'h0, _io_resp_x_T_10}; // @[Parameters.scala:137:{31,41}]
wire [49:0] _io_resp_x_T_12 = _io_resp_x_T_11 & 50'h9E110000; // @[Parameters.scala:137:{41,46}]
wire [49:0] _io_resp_x_T_13 = _io_resp_x_T_12; // @[Parameters.scala:137:46]
wire _io_resp_x_T_14 = _io_resp_x_T_13 == 50'h0; // @[Parameters.scala:137:{46,59}]
wire [49:0] _io_resp_x_T_16 = {1'h0, _io_resp_x_T_15}; // @[Parameters.scala:137:{31,41}]
wire [49:0] _io_resp_x_T_17 = _io_resp_x_T_16 & 50'h9E110000; // @[Parameters.scala:137:{41,46}]
wire [49:0] _io_resp_x_T_18 = _io_resp_x_T_17; // @[Parameters.scala:137:46]
wire _io_resp_x_T_19 = _io_resp_x_T_18 == 50'h0; // @[Parameters.scala:137:{46,59}]
wire [49:0] _io_resp_x_T_21 = {1'h0, _io_resp_x_T_20}; // @[Parameters.scala:137:{31,41}]
wire [49:0] _io_resp_x_T_22 = _io_resp_x_T_21 & 50'h90000000; // @[Parameters.scala:137:{41,46}]
wire [49:0] _io_resp_x_T_23 = _io_resp_x_T_22; // @[Parameters.scala:137:46]
wire _io_resp_x_T_24 = _io_resp_x_T_23 == 50'h0; // @[Parameters.scala:137:{46,59}]
wire _io_resp_x_T_25 = _io_resp_x_T_4 | _io_resp_x_T_9; // @[Parameters.scala:629:89]
wire _io_resp_x_T_26 = _io_resp_x_T_25 | _io_resp_x_T_14; // @[Parameters.scala:629:89]
wire _io_resp_x_T_27 = _io_resp_x_T_26 | _io_resp_x_T_19; // @[Parameters.scala:629:89]
wire _io_resp_x_T_28 = _io_resp_x_T_27 | _io_resp_x_T_24; // @[Parameters.scala:629:89]
wire _io_resp_x_T_64 = _io_resp_x_T_28; // @[Mux.scala:30:73]
wire [49:0] _io_resp_x_T_30 = {1'h0, _io_resp_x_T_29}; // @[Parameters.scala:137:{31,41}]
wire [49:0] _io_resp_x_T_31 = _io_resp_x_T_30 & 50'h9E113000; // @[Parameters.scala:137:{41,46}]
wire [49:0] _io_resp_x_T_32 = _io_resp_x_T_31; // @[Parameters.scala:137:46]
wire _io_resp_x_T_33 = _io_resp_x_T_32 == 50'h0; // @[Parameters.scala:137:{46,59}]
wire [49:0] _io_resp_x_T_35 = {1'h0, _io_resp_x_T_34}; // @[Parameters.scala:137:{31,41}]
wire [49:0] _io_resp_x_T_36 = _io_resp_x_T_35 & 50'h9E103000; // @[Parameters.scala:137:{41,46}]
wire [49:0] _io_resp_x_T_37 = _io_resp_x_T_36; // @[Parameters.scala:137:46]
wire _io_resp_x_T_38 = _io_resp_x_T_37 == 50'h0; // @[Parameters.scala:137:{46,59}]
wire [49:0] _io_resp_x_T_40 = {1'h0, _io_resp_x_T_39}; // @[Parameters.scala:137:{31,41}]
wire [49:0] _io_resp_x_T_41 = _io_resp_x_T_40 & 50'h9E110000; // @[Parameters.scala:137:{41,46}]
wire [49:0] _io_resp_x_T_42 = _io_resp_x_T_41; // @[Parameters.scala:137:46]
wire _io_resp_x_T_43 = _io_resp_x_T_42 == 50'h0; // @[Parameters.scala:137:{46,59}]
wire [49:0] _io_resp_x_T_45 = {1'h0, _io_resp_x_T_44}; // @[Parameters.scala:137:{31,41}]
wire [49:0] _io_resp_x_T_46 = _io_resp_x_T_45 & 50'h9E113000; // @[Parameters.scala:137:{41,46}]
wire [49:0] _io_resp_x_T_47 = _io_resp_x_T_46; // @[Parameters.scala:137:46]
wire _io_resp_x_T_48 = _io_resp_x_T_47 == 50'h0; // @[Parameters.scala:137:{46,59}]
wire [49:0] _io_resp_x_T_50 = {1'h0, _io_resp_x_T_49}; // @[Parameters.scala:137:{31,41}]
wire [49:0] _io_resp_x_T_51 = _io_resp_x_T_50 & 50'h9C000000; // @[Parameters.scala:137:{41,46}]
wire [49:0] _io_resp_x_T_52 = _io_resp_x_T_51; // @[Parameters.scala:137:46]
wire _io_resp_x_T_53 = _io_resp_x_T_52 == 50'h0; // @[Parameters.scala:137:{46,59}]
wire [49:0] _io_resp_x_T_55 = {1'h0, _io_resp_x_T_54}; // @[Parameters.scala:137:{31,41}]
wire [49:0] _io_resp_x_T_56 = _io_resp_x_T_55 & 50'h9E113000; // @[Parameters.scala:137:{41,46}]
wire [49:0] _io_resp_x_T_57 = _io_resp_x_T_56; // @[Parameters.scala:137:46]
wire _io_resp_x_T_58 = _io_resp_x_T_57 == 50'h0; // @[Parameters.scala:137:{46,59}]
wire _io_resp_x_T_59 = _io_resp_x_T_33 | _io_resp_x_T_38; // @[Parameters.scala:629:89]
wire _io_resp_x_T_60 = _io_resp_x_T_59 | _io_resp_x_T_43; // @[Parameters.scala:629:89]
wire _io_resp_x_T_61 = _io_resp_x_T_60 | _io_resp_x_T_48; // @[Parameters.scala:629:89]
wire _io_resp_x_T_62 = _io_resp_x_T_61 | _io_resp_x_T_53; // @[Parameters.scala:629:89]
wire _io_resp_x_T_63 = _io_resp_x_T_62 | _io_resp_x_T_58; // @[Parameters.scala:629:89]
wire _io_resp_x_T_66 = _io_resp_x_T_64; // @[Mux.scala:30:73]
wire _io_resp_x_WIRE = _io_resp_x_T_66; // @[Mux.scala:30:73]
assign _io_resp_x_T_67 = legal_address & _io_resp_x_WIRE; // @[Mux.scala:30:73]
assign io_resp_x_0 = _io_resp_x_T_67; // @[PMA.scala:18:7, :39:19]
wire [49:0] _io_resp_eff_T_1 = {1'h0, _io_resp_eff_T}; // @[Parameters.scala:137:{31,41}]
wire [49:0] _io_resp_eff_T_2 = _io_resp_eff_T_1 & 50'h9E112000; // @[Parameters.scala:137:{41,46}]
wire [49:0] _io_resp_eff_T_3 = _io_resp_eff_T_2; // @[Parameters.scala:137:46]
wire _io_resp_eff_T_4 = _io_resp_eff_T_3 == 50'h0; // @[Parameters.scala:137:{46,59}]
wire [49:0] _io_resp_eff_T_6 = {1'h0, _io_resp_eff_T_5}; // @[Parameters.scala:137:{31,41}]
wire [49:0] _io_resp_eff_T_7 = _io_resp_eff_T_6 & 50'h9E103000; // @[Parameters.scala:137:{41,46}]
wire [49:0] _io_resp_eff_T_8 = _io_resp_eff_T_7; // @[Parameters.scala:137:46]
wire _io_resp_eff_T_9 = _io_resp_eff_T_8 == 50'h0; // @[Parameters.scala:137:{46,59}]
wire [49:0] _io_resp_eff_T_11 = {1'h0, _io_resp_eff_T_10}; // @[Parameters.scala:137:{31,41}]
wire [49:0] _io_resp_eff_T_12 = _io_resp_eff_T_11 & 50'h9E110000; // @[Parameters.scala:137:{41,46}]
wire [49:0] _io_resp_eff_T_13 = _io_resp_eff_T_12; // @[Parameters.scala:137:46]
wire _io_resp_eff_T_14 = _io_resp_eff_T_13 == 50'h0; // @[Parameters.scala:137:{46,59}]
wire [49:0] _io_resp_eff_T_16 = {1'h0, _io_resp_eff_T_15}; // @[Parameters.scala:137:{31,41}]
wire [49:0] _io_resp_eff_T_17 = _io_resp_eff_T_16 & 50'h9E113000; // @[Parameters.scala:137:{41,46}]
wire [49:0] _io_resp_eff_T_18 = _io_resp_eff_T_17; // @[Parameters.scala:137:46]
wire _io_resp_eff_T_19 = _io_resp_eff_T_18 == 50'h0; // @[Parameters.scala:137:{46,59}]
wire [49:0] _io_resp_eff_T_21 = {1'h0, _io_resp_eff_T_20}; // @[Parameters.scala:137:{31,41}]
wire [49:0] _io_resp_eff_T_22 = _io_resp_eff_T_21 & 50'h9C000000; // @[Parameters.scala:137:{41,46}]
wire [49:0] _io_resp_eff_T_23 = _io_resp_eff_T_22; // @[Parameters.scala:137:46]
wire _io_resp_eff_T_24 = _io_resp_eff_T_23 == 50'h0; // @[Parameters.scala:137:{46,59}]
wire [49:0] _io_resp_eff_T_26 = {1'h0, _io_resp_eff_T_25}; // @[Parameters.scala:137:{31,41}]
wire [49:0] _io_resp_eff_T_27 = _io_resp_eff_T_26 & 50'h9E113000; // @[Parameters.scala:137:{41,46}]
wire [49:0] _io_resp_eff_T_28 = _io_resp_eff_T_27; // @[Parameters.scala:137:46]
wire _io_resp_eff_T_29 = _io_resp_eff_T_28 == 50'h0; // @[Parameters.scala:137:{46,59}]
wire _io_resp_eff_T_30 = _io_resp_eff_T_4 | _io_resp_eff_T_9; // @[Parameters.scala:629:89]
wire _io_resp_eff_T_31 = _io_resp_eff_T_30 | _io_resp_eff_T_14; // @[Parameters.scala:629:89]
wire _io_resp_eff_T_32 = _io_resp_eff_T_31 | _io_resp_eff_T_19; // @[Parameters.scala:629:89]
wire _io_resp_eff_T_33 = _io_resp_eff_T_32 | _io_resp_eff_T_24; // @[Parameters.scala:629:89]
wire _io_resp_eff_T_34 = _io_resp_eff_T_33 | _io_resp_eff_T_29; // @[Parameters.scala:629:89]
wire _io_resp_eff_T_58 = _io_resp_eff_T_34; // @[Mux.scala:30:73]
wire [49:0] _io_resp_eff_T_36 = {1'h0, _io_resp_eff_T_35}; // @[Parameters.scala:137:{31,41}]
wire [49:0] _io_resp_eff_T_37 = _io_resp_eff_T_36 & 50'h9E113000; // @[Parameters.scala:137:{41,46}]
wire [49:0] _io_resp_eff_T_38 = _io_resp_eff_T_37; // @[Parameters.scala:137:46]
wire _io_resp_eff_T_39 = _io_resp_eff_T_38 == 50'h0; // @[Parameters.scala:137:{46,59}]
wire [49:0] _io_resp_eff_T_41 = {1'h0, _io_resp_eff_T_40}; // @[Parameters.scala:137:{31,41}]
wire [49:0] _io_resp_eff_T_42 = _io_resp_eff_T_41 & 50'h9E110000; // @[Parameters.scala:137:{41,46}]
wire [49:0] _io_resp_eff_T_43 = _io_resp_eff_T_42; // @[Parameters.scala:137:46]
wire _io_resp_eff_T_44 = _io_resp_eff_T_43 == 50'h0; // @[Parameters.scala:137:{46,59}]
wire [49:0] _io_resp_eff_T_46 = {1'h0, _io_resp_eff_T_45}; // @[Parameters.scala:137:{31,41}]
wire [49:0] _io_resp_eff_T_47 = _io_resp_eff_T_46 & 50'h9E110000; // @[Parameters.scala:137:{41,46}]
wire [49:0] _io_resp_eff_T_48 = _io_resp_eff_T_47; // @[Parameters.scala:137:46]
wire _io_resp_eff_T_49 = _io_resp_eff_T_48 == 50'h0; // @[Parameters.scala:137:{46,59}]
wire [49:0] _io_resp_eff_T_51 = {1'h0, _io_resp_eff_T_50}; // @[Parameters.scala:137:{31,41}]
wire [49:0] _io_resp_eff_T_52 = _io_resp_eff_T_51 & 50'h90000000; // @[Parameters.scala:137:{41,46}]
wire [49:0] _io_resp_eff_T_53 = _io_resp_eff_T_52; // @[Parameters.scala:137:46]
wire _io_resp_eff_T_54 = _io_resp_eff_T_53 == 50'h0; // @[Parameters.scala:137:{46,59}]
wire _io_resp_eff_T_55 = _io_resp_eff_T_39 | _io_resp_eff_T_44; // @[Parameters.scala:629:89]
wire _io_resp_eff_T_56 = _io_resp_eff_T_55 | _io_resp_eff_T_49; // @[Parameters.scala:629:89]
wire _io_resp_eff_T_57 = _io_resp_eff_T_56 | _io_resp_eff_T_54; // @[Parameters.scala:629:89]
wire _io_resp_eff_T_60 = _io_resp_eff_T_58; // @[Mux.scala:30:73]
wire _io_resp_eff_WIRE = _io_resp_eff_T_60; // @[Mux.scala:30:73]
assign _io_resp_eff_T_61 = legal_address & _io_resp_eff_WIRE; // @[Mux.scala:30:73]
assign io_resp_eff_0 = _io_resp_eff_T_61; // @[PMA.scala:18:7, :39:19]
assign io_resp_cacheable = io_resp_cacheable_0; // @[PMA.scala:18:7]
assign io_resp_r = io_resp_r_0; // @[PMA.scala:18:7]
assign io_resp_w = io_resp_w_0; // @[PMA.scala:18:7]
assign io_resp_pp = io_resp_pp_0; // @[PMA.scala:18:7]
assign io_resp_al = io_resp_al_0; // @[PMA.scala:18:7]
assign io_resp_aa = io_resp_aa_0; // @[PMA.scala:18:7]
assign io_resp_x = io_resp_x_0; // @[PMA.scala:18:7]
assign io_resp_eff = io_resp_eff_0; // @[PMA.scala:18:7]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File Tile.scala:
// See README.md for license details.
package gemmini
import chisel3._
import chisel3.util._
import Util._
/**
* A Tile is a purely combinational 2D array of passThrough PEs.
* a, b, s, and in_propag are broadcast across the entire array and are passed through to the Tile's outputs
* @param width The data width of each PE in bits
* @param rows Number of PEs on each row
* @param columns Number of PEs on each column
*/
class Tile[T <: Data](inputType: T, outputType: T, accType: T, df: Dataflow.Value, tree_reduction: Boolean, max_simultaneous_matmuls: Int, val rows: Int, val columns: Int)(implicit ev: Arithmetic[T]) extends Module {
val io = IO(new Bundle {
val in_a = Input(Vec(rows, inputType))
val in_b = Input(Vec(columns, outputType)) // This is the output of the tile next to it
val in_d = Input(Vec(columns, outputType))
val in_control = Input(Vec(columns, new PEControl(accType)))
val in_id = Input(Vec(columns, UInt(log2Up(max_simultaneous_matmuls).W)))
val in_last = Input(Vec(columns, Bool()))
val out_a = Output(Vec(rows, inputType))
val out_c = Output(Vec(columns, outputType))
val out_b = Output(Vec(columns, outputType))
val out_control = Output(Vec(columns, new PEControl(accType)))
val out_id = Output(Vec(columns, UInt(log2Up(max_simultaneous_matmuls).W)))
val out_last = Output(Vec(columns, Bool()))
val in_valid = Input(Vec(columns, Bool()))
val out_valid = Output(Vec(columns, Bool()))
val bad_dataflow = Output(Bool())
})
import ev._
val tile = Seq.fill(rows, columns)(Module(new PE(inputType, outputType, accType, df, max_simultaneous_matmuls)))
val tileT = tile.transpose
// TODO: abstract hori/vert broadcast, all these connections look the same
// Broadcast 'a' horizontally across the Tile
for (r <- 0 until rows) {
tile(r).foldLeft(io.in_a(r)) {
case (in_a, pe) =>
pe.io.in_a := in_a
pe.io.out_a
}
}
// Broadcast 'b' vertically across the Tile
for (c <- 0 until columns) {
tileT(c).foldLeft(io.in_b(c)) {
case (in_b, pe) =>
pe.io.in_b := (if (tree_reduction) in_b.zero else in_b)
pe.io.out_b
}
}
// Broadcast 'd' vertically across the Tile
for (c <- 0 until columns) {
tileT(c).foldLeft(io.in_d(c)) {
case (in_d, pe) =>
pe.io.in_d := in_d
pe.io.out_c
}
}
// Broadcast 'control' vertically across the Tile
for (c <- 0 until columns) {
tileT(c).foldLeft(io.in_control(c)) {
case (in_ctrl, pe) =>
pe.io.in_control := in_ctrl
pe.io.out_control
}
}
// Broadcast 'garbage' vertically across the Tile
for (c <- 0 until columns) {
tileT(c).foldLeft(io.in_valid(c)) {
case (v, pe) =>
pe.io.in_valid := v
pe.io.out_valid
}
}
// Broadcast 'id' vertically across the Tile
for (c <- 0 until columns) {
tileT(c).foldLeft(io.in_id(c)) {
case (id, pe) =>
pe.io.in_id := id
pe.io.out_id
}
}
// Broadcast 'last' vertically across the Tile
for (c <- 0 until columns) {
tileT(c).foldLeft(io.in_last(c)) {
case (last, pe) =>
pe.io.in_last := last
pe.io.out_last
}
}
// Drive the Tile's bottom IO
for (c <- 0 until columns) {
io.out_c(c) := tile(rows-1)(c).io.out_c
io.out_control(c) := tile(rows-1)(c).io.out_control
io.out_id(c) := tile(rows-1)(c).io.out_id
io.out_last(c) := tile(rows-1)(c).io.out_last
io.out_valid(c) := tile(rows-1)(c).io.out_valid
io.out_b(c) := {
if (tree_reduction) {
val prods = tileT(c).map(_.io.out_b)
accumulateTree(prods :+ io.in_b(c))
} else {
tile(rows - 1)(c).io.out_b
}
}
}
io.bad_dataflow := tile.map(_.map(_.io.bad_dataflow).reduce(_||_)).reduce(_||_)
// Drive the Tile's right IO
for (r <- 0 until rows) {
io.out_a(r) := tile(r)(columns-1).io.out_a
}
}
| module Tile( // @[Tile.scala:16:7]
input clock, // @[Tile.scala:16:7]
input reset, // @[Tile.scala:16:7]
input [7:0] io_in_a_0, // @[Tile.scala:17:14]
input [19:0] io_in_b_0, // @[Tile.scala:17:14]
input [19:0] io_in_d_0, // @[Tile.scala:17:14]
input io_in_control_0_dataflow, // @[Tile.scala:17:14]
input io_in_control_0_propagate, // @[Tile.scala:17:14]
input [4:0] io_in_control_0_shift, // @[Tile.scala:17:14]
input [2:0] io_in_id_0, // @[Tile.scala:17:14]
input io_in_last_0, // @[Tile.scala:17:14]
output [7:0] io_out_a_0, // @[Tile.scala:17:14]
output [19:0] io_out_c_0, // @[Tile.scala:17:14]
output [19:0] io_out_b_0, // @[Tile.scala:17:14]
output io_out_control_0_dataflow, // @[Tile.scala:17:14]
output io_out_control_0_propagate, // @[Tile.scala:17:14]
output [4:0] io_out_control_0_shift, // @[Tile.scala:17:14]
output [2:0] io_out_id_0, // @[Tile.scala:17:14]
output io_out_last_0, // @[Tile.scala:17:14]
input io_in_valid_0, // @[Tile.scala:17:14]
output io_out_valid_0 // @[Tile.scala:17:14]
);
wire [7:0] io_in_a_0_0 = io_in_a_0; // @[Tile.scala:16:7]
wire [19:0] io_in_b_0_0 = io_in_b_0; // @[Tile.scala:16:7]
wire [19:0] io_in_d_0_0 = io_in_d_0; // @[Tile.scala:16:7]
wire io_in_control_0_dataflow_0 = io_in_control_0_dataflow; // @[Tile.scala:16:7]
wire io_in_control_0_propagate_0 = io_in_control_0_propagate; // @[Tile.scala:16:7]
wire [4:0] io_in_control_0_shift_0 = io_in_control_0_shift; // @[Tile.scala:16:7]
wire [2:0] io_in_id_0_0 = io_in_id_0; // @[Tile.scala:16:7]
wire io_in_last_0_0 = io_in_last_0; // @[Tile.scala:16:7]
wire io_in_valid_0_0 = io_in_valid_0; // @[Tile.scala:16:7]
wire io_bad_dataflow = 1'h0; // @[Tile.scala:16:7, :17:14, :42:44]
wire [7:0] io_out_a_0_0; // @[Tile.scala:16:7]
wire [19:0] io_out_c_0_0; // @[Tile.scala:16:7]
wire [19:0] io_out_b_0_0; // @[Tile.scala:16:7]
wire io_out_control_0_dataflow_0; // @[Tile.scala:16:7]
wire io_out_control_0_propagate_0; // @[Tile.scala:16:7]
wire [4:0] io_out_control_0_shift_0; // @[Tile.scala:16:7]
wire [2:0] io_out_id_0_0; // @[Tile.scala:16:7]
wire io_out_last_0_0; // @[Tile.scala:16:7]
wire io_out_valid_0_0; // @[Tile.scala:16:7]
PE_256 tile_0_0 ( // @[Tile.scala:42:44]
.clock (clock),
.reset (reset),
.io_in_a (io_in_a_0_0), // @[Tile.scala:16:7]
.io_in_b (io_in_b_0_0), // @[Tile.scala:16:7]
.io_in_d (io_in_d_0_0), // @[Tile.scala:16:7]
.io_out_a (io_out_a_0_0),
.io_out_b (io_out_b_0_0),
.io_out_c (io_out_c_0_0),
.io_in_control_dataflow (io_in_control_0_dataflow_0), // @[Tile.scala:16:7]
.io_in_control_propagate (io_in_control_0_propagate_0), // @[Tile.scala:16:7]
.io_in_control_shift (io_in_control_0_shift_0), // @[Tile.scala:16:7]
.io_out_control_dataflow (io_out_control_0_dataflow_0),
.io_out_control_propagate (io_out_control_0_propagate_0),
.io_out_control_shift (io_out_control_0_shift_0),
.io_in_id (io_in_id_0_0), // @[Tile.scala:16:7]
.io_out_id (io_out_id_0_0),
.io_in_last (io_in_last_0_0), // @[Tile.scala:16:7]
.io_out_last (io_out_last_0_0),
.io_in_valid (io_in_valid_0_0), // @[Tile.scala:16:7]
.io_out_valid (io_out_valid_0_0)
); // @[Tile.scala:42:44]
assign io_out_a_0 = io_out_a_0_0; // @[Tile.scala:16:7]
assign io_out_c_0 = io_out_c_0_0; // @[Tile.scala:16:7]
assign io_out_b_0 = io_out_b_0_0; // @[Tile.scala:16:7]
assign io_out_control_0_dataflow = io_out_control_0_dataflow_0; // @[Tile.scala:16:7]
assign io_out_control_0_propagate = io_out_control_0_propagate_0; // @[Tile.scala:16:7]
assign io_out_control_0_shift = io_out_control_0_shift_0; // @[Tile.scala:16:7]
assign io_out_id_0 = io_out_id_0_0; // @[Tile.scala:16:7]
assign io_out_last_0 = io_out_last_0_0; // @[Tile.scala:16:7]
assign io_out_valid_0 = io_out_valid_0_0; // @[Tile.scala:16:7]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File Monitor.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceLine
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import freechips.rocketchip.diplomacy.EnableMonitors
import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode}
import freechips.rocketchip.util.PlusArg
case class TLMonitorArgs(edge: TLEdge)
abstract class TLMonitorBase(args: TLMonitorArgs) extends Module
{
val io = IO(new Bundle {
val in = Input(new TLBundle(args.edge.bundle))
})
def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit
legalize(io.in, args.edge, reset)
}
object TLMonitor {
def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = {
if (enable) {
EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) }
} else { node }
}
}
class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args)
{
require (args.edge.params(TLMonitorStrictMode) || (! args.edge.params(TestplanTestType).formal))
val cover_prop_class = PropertyClass.Default
//Like assert but can flip to being an assumption for formal verification
def monAssert(cond: Bool, message: String): Unit =
if (monitorDir == MonitorDirection.Monitor) {
assert(cond, message)
} else {
Property(monitorDir, cond, message, PropertyClass.Default)
}
def assume(cond: Bool, message: String): Unit =
if (monitorDir == MonitorDirection.Monitor) {
assert(cond, message)
} else {
Property(monitorDir.flip, cond, message, PropertyClass.Default)
}
def extra = {
args.edge.sourceInfo match {
case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)"
case _ => ""
}
}
def visible(address: UInt, source: UInt, edge: TLEdge) =
edge.client.clients.map { c =>
!c.sourceId.contains(source) ||
c.visibility.map(_.contains(address)).reduce(_ || _)
}.reduce(_ && _)
def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = {
//switch this flag to turn on diplomacy in error messages
def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n"
monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra)
// Reuse these subexpressions to save some firrtl lines
val source_ok = edge.client.contains(bundle.source)
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val mask = edge.full_mask(bundle)
monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility")
//The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B
//TODO: check for acquireT?
when (bundle.opcode === TLMessages.AcquireBlock) {
monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra)
monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra)
monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra)
monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra)
}
when (bundle.opcode === TLMessages.AcquirePerm) {
monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra)
monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra)
monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra)
monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra)
monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra)
}
when (bundle.opcode === TLMessages.Get) {
monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra)
monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra)
monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra)
}
when (bundle.opcode === TLMessages.PutFullData) {
monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra)
monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.PutPartialData) {
monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra)
monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.ArithmeticData) {
monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra)
monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.LogicalData) {
monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra)
monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.Hint) {
monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra)
monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra)
}
}
def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = {
monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra)
monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility")
// Reuse these subexpressions to save some firrtl lines
val address_ok = edge.manager.containsSafe(edge.address(bundle))
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val mask = edge.full_mask(bundle)
val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source
when (bundle.opcode === TLMessages.Probe) {
assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra)
assume (address_ok, "'B' channel Probe carries unmanaged address" + extra)
assume (legal_source, "'B' channel Probe carries source that is not first source" + extra)
assume (is_aligned, "'B' channel Probe address not aligned to size" + extra)
assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra)
assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra)
assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra)
}
when (bundle.opcode === TLMessages.Get) {
monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra)
monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra)
}
when (bundle.opcode === TLMessages.PutFullData) {
monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra)
monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.PutPartialData) {
monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra)
monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.ArithmeticData) {
monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra)
monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra)
monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.LogicalData) {
monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra)
monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra)
monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.Hint) {
monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra)
monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra)
monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra)
}
}
def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = {
monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra)
val source_ok = edge.client.contains(bundle.source)
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val address_ok = edge.manager.containsSafe(edge.address(bundle))
monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility")
when (bundle.opcode === TLMessages.ProbeAck) {
monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra)
monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra)
}
when (bundle.opcode === TLMessages.ProbeAckData) {
monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra)
}
when (bundle.opcode === TLMessages.Release) {
monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra)
monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra)
monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra)
}
when (bundle.opcode === TLMessages.ReleaseData) {
monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra)
monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra)
}
when (bundle.opcode === TLMessages.AccessAck) {
monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra)
monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra)
}
when (bundle.opcode === TLMessages.AccessAckData) {
monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra)
}
when (bundle.opcode === TLMessages.HintAck) {
monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra)
monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra)
}
}
def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = {
assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra)
val source_ok = edge.client.contains(bundle.source)
val sink_ok = bundle.sink < edge.manager.endSinkId.U
val deny_put_ok = edge.manager.mayDenyPut.B
val deny_get_ok = edge.manager.mayDenyGet.B
when (bundle.opcode === TLMessages.ReleaseAck) {
assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra)
assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra)
assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra)
}
when (bundle.opcode === TLMessages.Grant) {
assume (source_ok, "'D' channel Grant carries invalid source ID" + extra)
assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra)
assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra)
assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra)
assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel Grant is denied" + extra)
}
when (bundle.opcode === TLMessages.GrantData) {
assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra)
assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra)
assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra)
assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra)
assume (!bundle.denied || bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra)
assume (deny_get_ok || !bundle.denied, "'D' channel GrantData is denied" + extra)
}
when (bundle.opcode === TLMessages.AccessAck) {
assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel AccessAck is denied" + extra)
}
when (bundle.opcode === TLMessages.AccessAckData) {
assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra)
assume (!bundle.denied || bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra)
assume (deny_get_ok || !bundle.denied, "'D' channel AccessAckData is denied" + extra)
}
when (bundle.opcode === TLMessages.HintAck) {
assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel HintAck is denied" + extra)
}
}
def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = {
val sink_ok = bundle.sink < edge.manager.endSinkId.U
monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra)
}
def legalizeFormat(bundle: TLBundle, edge: TLEdge) = {
when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) }
when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) }
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) }
when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) }
when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) }
} else {
monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra)
monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra)
monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra)
}
}
def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = {
val a_first = edge.first(a.bits, a.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (a.valid && !a_first) {
monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra)
monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra)
monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra)
monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra)
monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra)
}
when (a.fire && a_first) {
opcode := a.bits.opcode
param := a.bits.param
size := a.bits.size
source := a.bits.source
address := a.bits.address
}
}
def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = {
val b_first = edge.first(b.bits, b.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (b.valid && !b_first) {
monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra)
monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra)
monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra)
monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra)
monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra)
}
when (b.fire && b_first) {
opcode := b.bits.opcode
param := b.bits.param
size := b.bits.size
source := b.bits.source
address := b.bits.address
}
}
def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = {
// Symbolic variable
val sym_source = Wire(UInt(edge.client.endSourceId.W))
// TODO: Connect sym_source to a fixed value for simulation and to a
// free wire in formal
sym_source := 0.U
// Type casting Int to UInt
val maxSourceId = Wire(UInt(edge.client.endSourceId.W))
maxSourceId := edge.client.endSourceId.U
// Delayed verison of sym_source
val sym_source_d = Reg(UInt(edge.client.endSourceId.W))
sym_source_d := sym_source
// These will be constraints for FV setup
Property(
MonitorDirection.Monitor,
(sym_source === sym_source_d),
"sym_source should remain stable",
PropertyClass.Default)
Property(
MonitorDirection.Monitor,
(sym_source <= maxSourceId),
"sym_source should take legal value",
PropertyClass.Default)
val my_resp_pend = RegInit(false.B)
val my_opcode = Reg(UInt())
val my_size = Reg(UInt())
val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire)
val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire)
val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source)
val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source)
val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat)
val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend)
when (my_set_resp_pend) {
my_resp_pend := true.B
} .elsewhen (my_clr_resp_pend) {
my_resp_pend := false.B
}
when (my_a_first_beat) {
my_opcode := bundle.a.bits.opcode
my_size := bundle.a.bits.size
}
val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size)
val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode)
val my_resp_opcode_legal = Wire(Bool())
when ((my_resp_opcode === TLMessages.Get) || (my_resp_opcode === TLMessages.ArithmeticData) ||
(my_resp_opcode === TLMessages.LogicalData)) {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData)
} .elsewhen ((my_resp_opcode === TLMessages.PutFullData) || (my_resp_opcode === TLMessages.PutPartialData)) {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck)
} .otherwise {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck)
}
monAssert (IfThen(my_resp_pend, !my_a_first_beat),
"Request message should not be sent with a source ID, for which a response message" +
"is already pending (not received until current cycle) for a prior request message" +
"with the same source ID" + extra)
assume (IfThen(my_clr_resp_pend, (my_set_resp_pend || my_resp_pend)),
"Response message should be accepted with a source ID only if a request message with the" +
"same source ID has been accepted or is being accepted in the current cycle" + extra)
assume (IfThen(my_d_first_beat, (my_a_first_beat || my_resp_pend)),
"Response message should be sent with a source ID only if a request message with the" +
"same source ID has been accepted or is being sent in the current cycle" + extra)
assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)),
"If d_valid is 1, then d_size should be same as a_size of the corresponding request" +
"message" + extra)
assume (IfThen(my_d_first_beat, my_resp_opcode_legal),
"If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" +
"request message" + extra)
}
def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = {
val c_first = edge.first(c.bits, c.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (c.valid && !c_first) {
monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra)
monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra)
monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra)
monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra)
monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra)
}
when (c.fire && c_first) {
opcode := c.bits.opcode
param := c.bits.param
size := c.bits.size
source := c.bits.source
address := c.bits.address
}
}
def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = {
val d_first = edge.first(d.bits, d.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val sink = Reg(UInt())
val denied = Reg(Bool())
when (d.valid && !d_first) {
assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra)
assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra)
assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra)
assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra)
assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra)
assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra)
}
when (d.fire && d_first) {
opcode := d.bits.opcode
param := d.bits.param
size := d.bits.size
source := d.bits.source
sink := d.bits.sink
denied := d.bits.denied
}
}
def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = {
legalizeMultibeatA(bundle.a, edge)
legalizeMultibeatD(bundle.d, edge)
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
legalizeMultibeatB(bundle.b, edge)
legalizeMultibeatC(bundle.c, edge)
}
}
//This is left in for almond which doesn't adhere to the tilelink protocol
@deprecated("Use legalizeADSource instead if possible","")
def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = {
val inflight = RegInit(0.U(edge.client.endSourceId.W))
val a_first = edge.first(bundle.a.bits, bundle.a.fire)
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
val a_set = WireInit(0.U(edge.client.endSourceId.W))
when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) {
a_set := UIntToOH(bundle.a.bits.source)
assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra)
}
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
assume((a_set | inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra)
}
if (edge.manager.minLatency > 0) {
assume(a_set =/= d_clr || !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra)
}
inflight := (inflight | a_set) & ~d_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
assert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = {
val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset)
val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything
val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size)
val log_a_size_bus_size = log2Ceil(a_size_bus_size)
def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits
val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error
inflight.suggestName("inflight")
val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
inflight_opcodes.suggestName("inflight_opcodes")
val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
inflight_sizes.suggestName("inflight_sizes")
val a_first = edge.first(bundle.a.bits, bundle.a.fire)
a_first.suggestName("a_first")
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
d_first.suggestName("d_first")
val a_set = WireInit(0.U(edge.client.endSourceId.W))
val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
a_set.suggestName("a_set")
a_set_wo_ready.suggestName("a_set_wo_ready")
val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
a_opcodes_set.suggestName("a_opcodes_set")
val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
a_sizes_set.suggestName("a_sizes_set")
val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W))
a_opcode_lookup.suggestName("a_opcode_lookup")
a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U
val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W))
a_size_lookup.suggestName("a_size_lookup")
a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U
val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant))
val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant))
val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W))
a_opcodes_set_interm.suggestName("a_opcodes_set_interm")
val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W))
a_sizes_set_interm.suggestName("a_sizes_set_interm")
when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) {
a_set_wo_ready := UIntToOH(bundle.a.bits.source)
}
when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) {
a_set := UIntToOH(bundle.a.bits.source)
a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) | 1.U
a_sizes_set_interm := (bundle.a.bits.size << 1.U) | 1.U
a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U)
a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U)
monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra)
}
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
d_clr.suggestName("d_clr")
d_clr_wo_ready.suggestName("d_clr_wo_ready")
val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
d_opcodes_clr.suggestName("d_opcodes_clr")
val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
d_sizes_clr.suggestName("d_sizes_clr")
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr_wo_ready := UIntToOH(bundle.d.bits.source)
}
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U)
d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U)
}
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source)
assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra)
when (same_cycle_resp) {
assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) ||
(bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra)
assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra)
} .otherwise {
assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) ||
(bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra)
assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra)
}
}
when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) {
assume((!bundle.d.ready) || bundle.a.ready, "ready check")
}
if (edge.manager.minLatency > 0) {
assume(a_set_wo_ready =/= d_clr_wo_ready || !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra)
}
inflight := (inflight | a_set) & ~d_clr
inflight_opcodes := (inflight_opcodes | a_opcodes_set) & ~d_opcodes_clr
inflight_sizes := (inflight_sizes | a_sizes_set) & ~d_sizes_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = {
val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset)
val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything
val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size)
val log_c_size_bus_size = log2Ceil(c_size_bus_size)
def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits
val inflight = RegInit(0.U((2 max edge.client.endSourceId).W))
val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
inflight.suggestName("inflight")
inflight_opcodes.suggestName("inflight_opcodes")
inflight_sizes.suggestName("inflight_sizes")
val c_first = edge.first(bundle.c.bits, bundle.c.fire)
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
c_first.suggestName("c_first")
d_first.suggestName("d_first")
val c_set = WireInit(0.U(edge.client.endSourceId.W))
val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
c_set.suggestName("c_set")
c_set_wo_ready.suggestName("c_set_wo_ready")
c_opcodes_set.suggestName("c_opcodes_set")
c_sizes_set.suggestName("c_sizes_set")
val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W))
val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W))
c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U
c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U
c_opcode_lookup.suggestName("c_opcode_lookup")
c_size_lookup.suggestName("c_size_lookup")
val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W))
val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W))
c_opcodes_set_interm.suggestName("c_opcodes_set_interm")
c_sizes_set_interm.suggestName("c_sizes_set_interm")
when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) {
c_set_wo_ready := UIntToOH(bundle.c.bits.source)
}
when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) {
c_set := UIntToOH(bundle.c.bits.source)
c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) | 1.U
c_sizes_set_interm := (bundle.c.bits.size << 1.U) | 1.U
c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U)
c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U)
monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra)
}
val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck || bundle.c.bits.opcode === TLMessages.ProbeAckData
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
d_clr.suggestName("d_clr")
d_clr_wo_ready.suggestName("d_clr_wo_ready")
d_opcodes_clr.suggestName("d_opcodes_clr")
d_sizes_clr.suggestName("d_sizes_clr")
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
d_clr_wo_ready := UIntToOH(bundle.d.bits.source)
}
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U)
d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U)
}
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source)
assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra)
when (same_cycle_resp) {
assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra)
} .otherwise {
assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra)
}
}
when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) {
assume((!bundle.d.ready) || bundle.c.ready, "ready check")
}
if (edge.manager.minLatency > 0) {
when (c_set_wo_ready.orR) {
assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra)
}
}
inflight := (inflight | c_set) & ~d_clr
inflight_opcodes := (inflight_opcodes | c_opcodes_set) & ~d_opcodes_clr
inflight_sizes := (inflight_sizes | c_sizes_set) & ~d_sizes_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.c.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = {
val inflight = RegInit(0.U(edge.manager.endSinkId.W))
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
val e_first = true.B
val d_set = WireInit(0.U(edge.manager.endSinkId.W))
when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) {
d_set := UIntToOH(bundle.d.bits.sink)
assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra)
}
val e_clr = WireInit(0.U(edge.manager.endSinkId.W))
when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) {
e_clr := UIntToOH(bundle.e.bits.sink)
monAssert((d_set | inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra)
}
// edge.client.minLatency applies to BC, not DE
inflight := (inflight | d_set) & ~e_clr
}
def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = {
val sourceBits = log2Ceil(edge.client.endSourceId)
val tooBig = 14 // >16kB worth of flight information gets to be too much
if (sourceBits > tooBig) {
println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked")
} else {
if (args.edge.params(TestplanTestType).simulation) {
if (args.edge.params(TLMonitorStrictMode)) {
legalizeADSource(bundle, edge)
legalizeCDSource(bundle, edge)
} else {
legalizeADSourceOld(bundle, edge)
}
}
if (args.edge.params(TestplanTestType).formal) {
legalizeADSourceFormal(bundle, edge)
}
}
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
// legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize...
val sinkBits = log2Ceil(edge.manager.endSinkId)
if (sinkBits > tooBig) {
println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked")
} else {
legalizeDESink(bundle, edge)
}
}
}
def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = {
legalizeFormat (bundle, edge)
legalizeMultibeat (bundle, edge)
legalizeUnique (bundle, edge)
}
}
File Misc.scala:
// See LICENSE.Berkeley for license details.
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util._
import chisel3.util.random.LFSR
import org.chipsalliance.cde.config.Parameters
import scala.math._
class ParameterizedBundle(implicit p: Parameters) extends Bundle
trait Clocked extends Bundle {
val clock = Clock()
val reset = Bool()
}
object DecoupledHelper {
def apply(rvs: Bool*) = new DecoupledHelper(rvs)
}
class DecoupledHelper(val rvs: Seq[Bool]) {
def fire(exclude: Bool, includes: Bool*) = {
require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!")
(rvs.filter(_ ne exclude) ++ includes).reduce(_ && _)
}
def fire() = {
rvs.reduce(_ && _)
}
}
object MuxT {
def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2))
def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3))
def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4))
}
/** Creates a cascade of n MuxTs to search for a key value. */
object MuxTLookup {
def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = {
var res = default
for ((k, v) <- mapping.reverse)
res = MuxT(k === key, v, res)
res
}
def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = {
var res = default
for ((k, v) <- mapping.reverse)
res = MuxT(k === key, v, res)
res
}
}
object ValidMux {
def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = {
apply(v1 +: v2.toSeq)
}
def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = {
val out = Wire(Valid(valids.head.bits.cloneType))
out.valid := valids.map(_.valid).reduce(_ || _)
out.bits := MuxCase(valids.head.bits,
valids.map(v => (v.valid -> v.bits)))
out
}
}
object Str
{
def apply(s: String): UInt = {
var i = BigInt(0)
require(s.forall(validChar _))
for (c <- s)
i = (i << 8) | c
i.U((s.length*8).W)
}
def apply(x: Char): UInt = {
require(validChar(x))
x.U(8.W)
}
def apply(x: UInt): UInt = apply(x, 10)
def apply(x: UInt, radix: Int): UInt = {
val rad = radix.U
val w = x.getWidth
require(w > 0)
var q = x
var s = digit(q % rad)
for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {
q = q / rad
s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s)
}
s
}
def apply(x: SInt): UInt = apply(x, 10)
def apply(x: SInt, radix: Int): UInt = {
val neg = x < 0.S
val abs = x.abs.asUInt
if (radix != 10) {
Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix))
} else {
val rad = radix.U
val w = abs.getWidth
require(w > 0)
var q = abs
var s = digit(q % rad)
var needSign = neg
for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {
q = q / rad
val placeSpace = q === 0.U
val space = Mux(needSign, Str('-'), Str(' '))
needSign = needSign && !placeSpace
s = Cat(Mux(placeSpace, space, digit(q % rad)), s)
}
Cat(Mux(needSign, Str('-'), Str(' ')), s)
}
}
private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0)
private def validChar(x: Char) = x == (x & 0xFF)
}
object Split
{
def apply(x: UInt, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n0), x.extract(n0-1,0))
}
def apply(x: UInt, n1: Int, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))
}
def apply(x: UInt, n2: Int, n1: Int, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))
}
}
object Random
{
def apply(mod: Int, random: UInt): UInt = {
if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0)
else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod))
}
def apply(mod: Int): UInt = apply(mod, randomizer)
def oneHot(mod: Int, random: UInt): UInt = {
if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0))
else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt
}
def oneHot(mod: Int): UInt = oneHot(mod, randomizer)
private def randomizer = LFSR(16)
private def partition(value: UInt, slices: Int) =
Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U)
}
object Majority {
def apply(in: Set[Bool]): Bool = {
val n = (in.size >> 1) + 1
val clauses = in.subsets(n).map(_.reduce(_ && _))
clauses.reduce(_ || _)
}
def apply(in: Seq[Bool]): Bool = apply(in.toSet)
def apply(in: UInt): Bool = apply(in.asBools.toSet)
}
object PopCountAtLeast {
private def two(x: UInt): (Bool, Bool) = x.getWidth match {
case 1 => (x.asBool, false.B)
case n =>
val half = x.getWidth / 2
val (leftOne, leftTwo) = two(x(half - 1, 0))
val (rightOne, rightTwo) = two(x(x.getWidth - 1, half))
(leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne))
}
def apply(x: UInt, n: Int): Bool = n match {
case 0 => true.B
case 1 => x.orR
case 2 => two(x)._2
case 3 => PopCount(x) >= n.U
}
}
// This gets used everywhere, so make the smallest circuit possible ...
// Given an address and size, create a mask of beatBytes size
// eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111
// groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01
object MaskGen {
def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = {
require (groupBy >= 1 && beatBytes >= groupBy)
require (isPow2(beatBytes) && isPow2(groupBy))
val lgBytes = log2Ceil(beatBytes)
val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U
def helper(i: Int): Seq[(Bool, Bool)] = {
if (i == 0) {
Seq((lgSize >= lgBytes.asUInt, true.B))
} else {
val sub = helper(i-1)
val size = sizeOH(lgBytes - i)
val bit = addr_lo(lgBytes - i)
val nbit = !bit
Seq.tabulate (1 << i) { j =>
val (sub_acc, sub_eq) = sub(j/2)
val eq = sub_eq && (if (j % 2 == 1) bit else nbit)
val acc = sub_acc || (size && eq)
(acc, eq)
}
}
}
if (groupBy == beatBytes) 1.U else
Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse)
}
}
File PlusArg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.experimental._
import chisel3.util.HasBlackBoxResource
@deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05")
case class PlusArgInfo(default: BigInt, docstring: String)
/** Case class for PlusArg information
*
* @tparam A scala type of the PlusArg value
* @param default optional default value
* @param docstring text to include in the help
* @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT)
*/
private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String)
/** Typeclass for converting a type to a doctype string
* @tparam A some type
*/
trait Doctypeable[A] {
/** Return the doctype string for some option */
def toDoctype(a: Option[A]): String
}
/** Object containing implementations of the Doctypeable typeclass */
object Doctypes {
/** Converts an Int => "INT" */
implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" }
/** Converts a BigInt => "INT" */
implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" }
/** Converts a String => "STRING" */
implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" }
}
class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map(
"FORMAT" -> StringParam(format),
"DEFAULT" -> IntParam(default),
"WIDTH" -> IntParam(width)
)) with HasBlackBoxResource {
val io = IO(new Bundle {
val out = Output(UInt(width.W))
})
addResource("/vsrc/plusarg_reader.v")
}
/* This wrapper class has no outputs, making it clear it is a simulation-only construct */
class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module {
val io = IO(new Bundle {
val count = Input(UInt(width.W))
})
val max = Module(new plusarg_reader(format, default, docstring, width)).io.out
when (max > 0.U) {
assert (io.count < max, s"Timeout exceeded: $docstring")
}
}
import Doctypes._
object PlusArg
{
/** PlusArg("foo") will return 42.U if the simulation is run with +foo=42
* Do not use this as an initial register value. The value is set in an
* initial block and thus accessing it from another initial is racey.
* Add a docstring to document the arg, which can be dumped in an elaboration
* pass.
*/
def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = {
PlusArgArtefacts.append(name, Some(default), docstring)
Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out
}
/** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert
* to kill the simulation when count exceeds the specified integer argument.
* Default 0 will never assert.
*/
def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = {
PlusArgArtefacts.append(name, Some(default), docstring)
Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count
}
}
object PlusArgArtefacts {
private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty
/* Add a new PlusArg */
@deprecated(
"Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08",
"Rocket Chip 2020.05"
)
def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring)
/** Add a new PlusArg
*
* @tparam A scala type of the PlusArg value
* @param name name for the PlusArg
* @param default optional default value
* @param docstring text to include in the help
*/
def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit =
artefacts = artefacts ++
Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default)))
/* From plus args, generate help text */
private def serializeHelp_cHeader(tab: String = ""): String = artefacts
.map{ case(arg, info) =>
s"""|$tab+$arg=${info.doctype}\\n\\
|$tab${" "*20}${info.docstring}\\n\\
|""".stripMargin ++ info.default.map{ case default =>
s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("")
}.toSeq.mkString("\\n\\\n") ++ "\""
/* From plus args, generate a char array of their names */
private def serializeArray_cHeader(tab: String = ""): String = {
val prettyTab = tab + " " * 44 // Length of 'static const ...'
s"${tab}static const char * verilog_plusargs [] = {\\\n" ++
artefacts
.map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" }
.mkString("")++
s"${prettyTab}0};"
}
/* Generate C code to be included in emulator.cc that helps with
* argument parsing based on available Verilog PlusArgs */
def serialize_cHeader(): String =
s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\
|${serializeHelp_cHeader(" "*7)}
|${serializeArray_cHeader()}
|""".stripMargin
}
File package.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip
import chisel3._
import chisel3.util._
import scala.math.min
import scala.collection.{immutable, mutable}
package object util {
implicit class UnzippableOption[S, T](val x: Option[(S, T)]) {
def unzip = (x.map(_._1), x.map(_._2))
}
implicit class UIntIsOneOf(private val x: UInt) extends AnyVal {
def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR
def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq)
}
implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal {
/** Like Vec.apply(idx), but tolerates indices of mismatched width */
def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0))
}
implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal {
def apply(idx: UInt): T = {
if (x.size <= 1) {
x.head
} else if (!isPow2(x.size)) {
// For non-power-of-2 seqs, reflect elements to simplify decoder
(x ++ x.takeRight(x.size & -x.size)).toSeq(idx)
} else {
// Ignore MSBs of idx
val truncIdx =
if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx
else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0)
x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) }
}
}
def extract(idx: UInt): T = VecInit(x).extract(idx)
def asUInt: UInt = Cat(x.map(_.asUInt).reverse)
def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n)
def rotate(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n)
def rotateRight(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
}
// allow bitwise ops on Seq[Bool] just like UInt
implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal {
def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b }
def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b }
def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b }
def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x
def >> (n: Int): Seq[Bool] = x drop n
def unary_~ : Seq[Bool] = x.map(!_)
def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_)
def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_)
def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_)
private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B)
}
implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal {
def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable))
def getElements: Seq[Element] = x match {
case e: Element => Seq(e)
case a: Aggregate => a.getElements.flatMap(_.getElements)
}
}
/** Any Data subtype that has a Bool member named valid. */
type DataCanBeValid = Data { val valid: Bool }
implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal {
def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable)
}
implicit class StringToAugmentedString(private val x: String) extends AnyVal {
/** converts from camel case to to underscores, also removing all spaces */
def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") {
case (acc, c) if c.isUpper => acc + "_" + c.toLower
case (acc, c) if c == ' ' => acc
case (acc, c) => acc + c
}
/** converts spaces or underscores to hyphens, also lowering case */
def kebab: String = x.toLowerCase map {
case ' ' => '-'
case '_' => '-'
case c => c
}
def named(name: Option[String]): String = {
x + name.map("_named_" + _ ).getOrElse("_with_no_name")
}
def named(name: String): String = named(Some(name))
}
implicit def uintToBitPat(x: UInt): BitPat = BitPat(x)
implicit def wcToUInt(c: WideCounter): UInt = c.value
implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal {
def sextTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x)
}
def padTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(0.U((n - x.getWidth).W), x)
}
// shifts left by n if n >= 0, or right by -n if n < 0
def << (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << n(w-1, 0)
Mux(n(w), shifted >> (1 << w), shifted)
}
// shifts right by n if n >= 0, or left by -n if n < 0
def >> (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << (1 << w) >> n(w-1, 0)
Mux(n(w), shifted, shifted >> (1 << w))
}
// Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts
def extract(hi: Int, lo: Int): UInt = {
require(hi >= lo-1)
if (hi == lo-1) 0.U
else x(hi, lo)
}
// Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts
def extractOption(hi: Int, lo: Int): Option[UInt] = {
require(hi >= lo-1)
if (hi == lo-1) None
else Some(x(hi, lo))
}
// like x & ~y, but first truncate or zero-extend y to x's width
def andNot(y: UInt): UInt = x & ~(y | (x & 0.U))
def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n)
def rotateRight(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r))
}
}
def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n))
def rotateLeft(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r))
}
}
// compute (this + y) % n, given (this < n) and (y < n)
def addWrap(y: UInt, n: Int): UInt = {
val z = x +& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0)
}
// compute (this - y) % n, given (this < n) and (y < n)
def subWrap(y: UInt, n: Int): UInt = {
val z = x -& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0)
}
def grouped(width: Int): Seq[UInt] =
(0 until x.getWidth by width).map(base => x(base + width - 1, base))
def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds
def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x)
// Like >=, but prevents x-prop for ('x >= 0)
def >== (y: UInt): Bool = x >= y || y === 0.U
}
implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal {
def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y)
def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y)
}
implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal {
def toInt: Int = if (x) 1 else 0
// this one's snagged from scalaz
def option[T](z: => T): Option[T] = if (x) Some(z) else None
}
implicit class IntToAugmentedInt(private val x: Int) extends AnyVal {
// exact log2
def log2: Int = {
require(isPow2(x))
log2Ceil(x)
}
}
def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x)
def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x))
def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0)
def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1)
def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None
// Fill 1s from low bits to high bits
def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth)
def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0))
helper(1, x)(width-1, 0)
}
// Fill 1s form high bits to low bits
def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth)
def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x >> s))
helper(1, x)(width-1, 0)
}
def OptimizationBarrier[T <: Data](in: T): T = {
val barrier = Module(new Module {
val io = IO(new Bundle {
val x = Input(chiselTypeOf(in))
val y = Output(chiselTypeOf(in))
})
io.y := io.x
override def desiredName = s"OptimizationBarrier_${in.typeName}"
})
barrier.io.x := in
barrier.io.y
}
/** Similar to Seq.groupBy except this returns a Seq instead of a Map
* Useful for deterministic code generation
*/
def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = {
val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]]
for (x <- xs) {
val key = f(x)
val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A])
l += x
}
map.view.map({ case (k, vs) => k -> vs.toList }).toList
}
def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match {
case 1 => List.fill(n)(in.head)
case x if x == n => in
case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in")
}
// HeterogeneousBag moved to standalond diplomacy
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts)
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag
}
File Bundles.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import freechips.rocketchip.util._
import scala.collection.immutable.ListMap
import chisel3.util.Decoupled
import chisel3.util.DecoupledIO
import chisel3.reflect.DataMirror
abstract class TLBundleBase(val params: TLBundleParameters) extends Bundle
// common combos in lazy policy:
// Put + Acquire
// Release + AccessAck
object TLMessages
{
// A B C D E
def PutFullData = 0.U // . . => AccessAck
def PutPartialData = 1.U // . . => AccessAck
def ArithmeticData = 2.U // . . => AccessAckData
def LogicalData = 3.U // . . => AccessAckData
def Get = 4.U // . . => AccessAckData
def Hint = 5.U // . . => HintAck
def AcquireBlock = 6.U // . => Grant[Data]
def AcquirePerm = 7.U // . => Grant[Data]
def Probe = 6.U // . => ProbeAck[Data]
def AccessAck = 0.U // . .
def AccessAckData = 1.U // . .
def HintAck = 2.U // . .
def ProbeAck = 4.U // .
def ProbeAckData = 5.U // .
def Release = 6.U // . => ReleaseAck
def ReleaseData = 7.U // . => ReleaseAck
def Grant = 4.U // . => GrantAck
def GrantData = 5.U // . => GrantAck
def ReleaseAck = 6.U // .
def GrantAck = 0.U // .
def isA(x: UInt) = x <= AcquirePerm
def isB(x: UInt) = x <= Probe
def isC(x: UInt) = x <= ReleaseData
def isD(x: UInt) = x <= ReleaseAck
def adResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant, Grant)
def bcResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, ProbeAck, ProbeAck)
def a = Seq( ("PutFullData",TLPermissions.PermMsgReserved),
("PutPartialData",TLPermissions.PermMsgReserved),
("ArithmeticData",TLAtomics.ArithMsg),
("LogicalData",TLAtomics.LogicMsg),
("Get",TLPermissions.PermMsgReserved),
("Hint",TLHints.HintsMsg),
("AcquireBlock",TLPermissions.PermMsgGrow),
("AcquirePerm",TLPermissions.PermMsgGrow))
def b = Seq( ("PutFullData",TLPermissions.PermMsgReserved),
("PutPartialData",TLPermissions.PermMsgReserved),
("ArithmeticData",TLAtomics.ArithMsg),
("LogicalData",TLAtomics.LogicMsg),
("Get",TLPermissions.PermMsgReserved),
("Hint",TLHints.HintsMsg),
("Probe",TLPermissions.PermMsgCap))
def c = Seq( ("AccessAck",TLPermissions.PermMsgReserved),
("AccessAckData",TLPermissions.PermMsgReserved),
("HintAck",TLPermissions.PermMsgReserved),
("Invalid Opcode",TLPermissions.PermMsgReserved),
("ProbeAck",TLPermissions.PermMsgReport),
("ProbeAckData",TLPermissions.PermMsgReport),
("Release",TLPermissions.PermMsgReport),
("ReleaseData",TLPermissions.PermMsgReport))
def d = Seq( ("AccessAck",TLPermissions.PermMsgReserved),
("AccessAckData",TLPermissions.PermMsgReserved),
("HintAck",TLPermissions.PermMsgReserved),
("Invalid Opcode",TLPermissions.PermMsgReserved),
("Grant",TLPermissions.PermMsgCap),
("GrantData",TLPermissions.PermMsgCap),
("ReleaseAck",TLPermissions.PermMsgReserved))
}
/**
* The three primary TileLink permissions are:
* (T)runk: the agent is (or is on inwards path to) the global point of serialization.
* (B)ranch: the agent is on an outwards path to
* (N)one:
* These permissions are permuted by transfer operations in various ways.
* Operations can cap permissions, request for them to be grown or shrunk,
* or for a report on their current status.
*/
object TLPermissions
{
val aWidth = 2
val bdWidth = 2
val cWidth = 3
// Cap types (Grant = new permissions, Probe = permisions <= target)
def toT = 0.U(bdWidth.W)
def toB = 1.U(bdWidth.W)
def toN = 2.U(bdWidth.W)
def isCap(x: UInt) = x <= toN
// Grow types (Acquire = permissions >= target)
def NtoB = 0.U(aWidth.W)
def NtoT = 1.U(aWidth.W)
def BtoT = 2.U(aWidth.W)
def isGrow(x: UInt) = x <= BtoT
// Shrink types (ProbeAck, Release)
def TtoB = 0.U(cWidth.W)
def TtoN = 1.U(cWidth.W)
def BtoN = 2.U(cWidth.W)
def isShrink(x: UInt) = x <= BtoN
// Report types (ProbeAck, Release)
def TtoT = 3.U(cWidth.W)
def BtoB = 4.U(cWidth.W)
def NtoN = 5.U(cWidth.W)
def isReport(x: UInt) = x <= NtoN
def PermMsgGrow:Seq[String] = Seq("Grow NtoB", "Grow NtoT", "Grow BtoT")
def PermMsgCap:Seq[String] = Seq("Cap toT", "Cap toB", "Cap toN")
def PermMsgReport:Seq[String] = Seq("Shrink TtoB", "Shrink TtoN", "Shrink BtoN", "Report TotT", "Report BtoB", "Report NtoN")
def PermMsgReserved:Seq[String] = Seq("Reserved")
}
object TLAtomics
{
val width = 3
// Arithmetic types
def MIN = 0.U(width.W)
def MAX = 1.U(width.W)
def MINU = 2.U(width.W)
def MAXU = 3.U(width.W)
def ADD = 4.U(width.W)
def isArithmetic(x: UInt) = x <= ADD
// Logical types
def XOR = 0.U(width.W)
def OR = 1.U(width.W)
def AND = 2.U(width.W)
def SWAP = 3.U(width.W)
def isLogical(x: UInt) = x <= SWAP
def ArithMsg:Seq[String] = Seq("MIN", "MAX", "MINU", "MAXU", "ADD")
def LogicMsg:Seq[String] = Seq("XOR", "OR", "AND", "SWAP")
}
object TLHints
{
val width = 1
def PREFETCH_READ = 0.U(width.W)
def PREFETCH_WRITE = 1.U(width.W)
def isHints(x: UInt) = x <= PREFETCH_WRITE
def HintsMsg:Seq[String] = Seq("PrefetchRead", "PrefetchWrite")
}
sealed trait TLChannel extends TLBundleBase {
val channelName: String
}
sealed trait TLDataChannel extends TLChannel
sealed trait TLAddrChannel extends TLDataChannel
final class TLBundleA(params: TLBundleParameters)
extends TLBundleBase(params) with TLAddrChannel
{
override def typeName = s"TLBundleA_${params.shortName}"
val channelName = "'A' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(List(TLAtomics.width, TLPermissions.aWidth, TLHints.width).max.W) // amo_opcode || grow perms || hint
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // from
val address = UInt(params.addressBits.W) // to
val user = BundleMap(params.requestFields)
val echo = BundleMap(params.echoFields)
// variable fields during multibeat:
val mask = UInt((params.dataBits/8).W)
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleB(params: TLBundleParameters)
extends TLBundleBase(params) with TLAddrChannel
{
override def typeName = s"TLBundleB_${params.shortName}"
val channelName = "'B' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(TLPermissions.bdWidth.W) // cap perms
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // to
val address = UInt(params.addressBits.W) // from
// variable fields during multibeat:
val mask = UInt((params.dataBits/8).W)
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleC(params: TLBundleParameters)
extends TLBundleBase(params) with TLAddrChannel
{
override def typeName = s"TLBundleC_${params.shortName}"
val channelName = "'C' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(TLPermissions.cWidth.W) // shrink or report perms
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // from
val address = UInt(params.addressBits.W) // to
val user = BundleMap(params.requestFields)
val echo = BundleMap(params.echoFields)
// variable fields during multibeat:
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleD(params: TLBundleParameters)
extends TLBundleBase(params) with TLDataChannel
{
override def typeName = s"TLBundleD_${params.shortName}"
val channelName = "'D' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(TLPermissions.bdWidth.W) // cap perms
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // to
val sink = UInt(params.sinkBits.W) // from
val denied = Bool() // implies corrupt iff *Data
val user = BundleMap(params.responseFields)
val echo = BundleMap(params.echoFields)
// variable fields during multibeat:
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleE(params: TLBundleParameters)
extends TLBundleBase(params) with TLChannel
{
override def typeName = s"TLBundleE_${params.shortName}"
val channelName = "'E' channel"
val sink = UInt(params.sinkBits.W) // to
}
class TLBundle(val params: TLBundleParameters) extends Record
{
// Emulate a Bundle with elements abcde or ad depending on params.hasBCE
private val optA = Some (Decoupled(new TLBundleA(params)))
private val optB = params.hasBCE.option(Flipped(Decoupled(new TLBundleB(params))))
private val optC = params.hasBCE.option(Decoupled(new TLBundleC(params)))
private val optD = Some (Flipped(Decoupled(new TLBundleD(params))))
private val optE = params.hasBCE.option(Decoupled(new TLBundleE(params)))
def a: DecoupledIO[TLBundleA] = optA.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleA(params)))))
def b: DecoupledIO[TLBundleB] = optB.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleB(params)))))
def c: DecoupledIO[TLBundleC] = optC.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleC(params)))))
def d: DecoupledIO[TLBundleD] = optD.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleD(params)))))
def e: DecoupledIO[TLBundleE] = optE.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleE(params)))))
val elements =
if (params.hasBCE) ListMap("e" -> e, "d" -> d, "c" -> c, "b" -> b, "a" -> a)
else ListMap("d" -> d, "a" -> a)
def tieoff(): Unit = {
DataMirror.specifiedDirectionOf(a.ready) match {
case SpecifiedDirection.Input =>
a.ready := false.B
c.ready := false.B
e.ready := false.B
b.valid := false.B
d.valid := false.B
case SpecifiedDirection.Output =>
a.valid := false.B
c.valid := false.B
e.valid := false.B
b.ready := false.B
d.ready := false.B
case _ =>
}
}
}
object TLBundle
{
def apply(params: TLBundleParameters) = new TLBundle(params)
}
class TLAsyncBundleBase(val params: TLAsyncBundleParameters) extends Bundle
class TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params)
{
val a = new AsyncBundle(new TLBundleA(params.base), params.async)
val b = Flipped(new AsyncBundle(new TLBundleB(params.base), params.async))
val c = new AsyncBundle(new TLBundleC(params.base), params.async)
val d = Flipped(new AsyncBundle(new TLBundleD(params.base), params.async))
val e = new AsyncBundle(new TLBundleE(params.base), params.async)
}
class TLRationalBundle(params: TLBundleParameters) extends TLBundleBase(params)
{
val a = RationalIO(new TLBundleA(params))
val b = Flipped(RationalIO(new TLBundleB(params)))
val c = RationalIO(new TLBundleC(params))
val d = Flipped(RationalIO(new TLBundleD(params)))
val e = RationalIO(new TLBundleE(params))
}
class TLCreditedBundle(params: TLBundleParameters) extends TLBundleBase(params)
{
val a = CreditedIO(new TLBundleA(params))
val b = Flipped(CreditedIO(new TLBundleB(params)))
val c = CreditedIO(new TLBundleC(params))
val d = Flipped(CreditedIO(new TLBundleD(params)))
val e = CreditedIO(new TLBundleE(params))
}
File Parameters.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy.nodes._
import freechips.rocketchip.diplomacy.{
AddressDecoder, AddressSet, BufferParams, DirectedBuffers, IdMap, IdMapEntry,
IdRange, RegionType, TransferSizes
}
import freechips.rocketchip.resources.{Resource, ResourceAddress, ResourcePermissions}
import freechips.rocketchip.util.{
AsyncQueueParams, BundleField, BundleFieldBase, BundleKeyBase,
CreditedDelay, groupByIntoSeq, RationalDirection, SimpleProduct
}
import scala.math.max
//These transfer sizes describe requests issued from masters on the A channel that will be responded by slaves on the D channel
case class TLMasterToSlaveTransferSizes(
// Supports both Acquire+Release of the following two sizes:
acquireT: TransferSizes = TransferSizes.none,
acquireB: TransferSizes = TransferSizes.none,
arithmetic: TransferSizes = TransferSizes.none,
logical: TransferSizes = TransferSizes.none,
get: TransferSizes = TransferSizes.none,
putFull: TransferSizes = TransferSizes.none,
putPartial: TransferSizes = TransferSizes.none,
hint: TransferSizes = TransferSizes.none)
extends TLCommonTransferSizes {
def intersect(rhs: TLMasterToSlaveTransferSizes) = TLMasterToSlaveTransferSizes(
acquireT = acquireT .intersect(rhs.acquireT),
acquireB = acquireB .intersect(rhs.acquireB),
arithmetic = arithmetic.intersect(rhs.arithmetic),
logical = logical .intersect(rhs.logical),
get = get .intersect(rhs.get),
putFull = putFull .intersect(rhs.putFull),
putPartial = putPartial.intersect(rhs.putPartial),
hint = hint .intersect(rhs.hint))
def mincover(rhs: TLMasterToSlaveTransferSizes) = TLMasterToSlaveTransferSizes(
acquireT = acquireT .mincover(rhs.acquireT),
acquireB = acquireB .mincover(rhs.acquireB),
arithmetic = arithmetic.mincover(rhs.arithmetic),
logical = logical .mincover(rhs.logical),
get = get .mincover(rhs.get),
putFull = putFull .mincover(rhs.putFull),
putPartial = putPartial.mincover(rhs.putPartial),
hint = hint .mincover(rhs.hint))
// Reduce rendering to a simple yes/no per field
override def toString = {
def str(x: TransferSizes, flag: String) = if (x.none) "" else flag
def flags = Vector(
str(acquireT, "T"),
str(acquireB, "B"),
str(arithmetic, "A"),
str(logical, "L"),
str(get, "G"),
str(putFull, "F"),
str(putPartial, "P"),
str(hint, "H"))
flags.mkString
}
// Prints out the actual information in a user readable way
def infoString = {
s"""acquireT = ${acquireT}
|acquireB = ${acquireB}
|arithmetic = ${arithmetic}
|logical = ${logical}
|get = ${get}
|putFull = ${putFull}
|putPartial = ${putPartial}
|hint = ${hint}
|
|""".stripMargin
}
}
object TLMasterToSlaveTransferSizes {
def unknownEmits = TLMasterToSlaveTransferSizes(
acquireT = TransferSizes(1, 4096),
acquireB = TransferSizes(1, 4096),
arithmetic = TransferSizes(1, 4096),
logical = TransferSizes(1, 4096),
get = TransferSizes(1, 4096),
putFull = TransferSizes(1, 4096),
putPartial = TransferSizes(1, 4096),
hint = TransferSizes(1, 4096))
def unknownSupports = TLMasterToSlaveTransferSizes()
}
//These transfer sizes describe requests issued from slaves on the B channel that will be responded by masters on the C channel
case class TLSlaveToMasterTransferSizes(
probe: TransferSizes = TransferSizes.none,
arithmetic: TransferSizes = TransferSizes.none,
logical: TransferSizes = TransferSizes.none,
get: TransferSizes = TransferSizes.none,
putFull: TransferSizes = TransferSizes.none,
putPartial: TransferSizes = TransferSizes.none,
hint: TransferSizes = TransferSizes.none
) extends TLCommonTransferSizes {
def intersect(rhs: TLSlaveToMasterTransferSizes) = TLSlaveToMasterTransferSizes(
probe = probe .intersect(rhs.probe),
arithmetic = arithmetic.intersect(rhs.arithmetic),
logical = logical .intersect(rhs.logical),
get = get .intersect(rhs.get),
putFull = putFull .intersect(rhs.putFull),
putPartial = putPartial.intersect(rhs.putPartial),
hint = hint .intersect(rhs.hint)
)
def mincover(rhs: TLSlaveToMasterTransferSizes) = TLSlaveToMasterTransferSizes(
probe = probe .mincover(rhs.probe),
arithmetic = arithmetic.mincover(rhs.arithmetic),
logical = logical .mincover(rhs.logical),
get = get .mincover(rhs.get),
putFull = putFull .mincover(rhs.putFull),
putPartial = putPartial.mincover(rhs.putPartial),
hint = hint .mincover(rhs.hint)
)
// Reduce rendering to a simple yes/no per field
override def toString = {
def str(x: TransferSizes, flag: String) = if (x.none) "" else flag
def flags = Vector(
str(probe, "P"),
str(arithmetic, "A"),
str(logical, "L"),
str(get, "G"),
str(putFull, "F"),
str(putPartial, "P"),
str(hint, "H"))
flags.mkString
}
// Prints out the actual information in a user readable way
def infoString = {
s"""probe = ${probe}
|arithmetic = ${arithmetic}
|logical = ${logical}
|get = ${get}
|putFull = ${putFull}
|putPartial = ${putPartial}
|hint = ${hint}
|
|""".stripMargin
}
}
object TLSlaveToMasterTransferSizes {
def unknownEmits = TLSlaveToMasterTransferSizes(
arithmetic = TransferSizes(1, 4096),
logical = TransferSizes(1, 4096),
get = TransferSizes(1, 4096),
putFull = TransferSizes(1, 4096),
putPartial = TransferSizes(1, 4096),
hint = TransferSizes(1, 4096),
probe = TransferSizes(1, 4096))
def unknownSupports = TLSlaveToMasterTransferSizes()
}
trait TLCommonTransferSizes {
def arithmetic: TransferSizes
def logical: TransferSizes
def get: TransferSizes
def putFull: TransferSizes
def putPartial: TransferSizes
def hint: TransferSizes
}
class TLSlaveParameters private(
val nodePath: Seq[BaseNode],
val resources: Seq[Resource],
setName: Option[String],
val address: Seq[AddressSet],
val regionType: RegionType.T,
val executable: Boolean,
val fifoId: Option[Int],
val supports: TLMasterToSlaveTransferSizes,
val emits: TLSlaveToMasterTransferSizes,
// By default, slaves are forbidden from issuing 'denied' responses (it prevents Fragmentation)
val alwaysGrantsT: Boolean, // typically only true for CacheCork'd read-write devices; dual: neverReleaseData
// If fifoId=Some, all accesses sent to the same fifoId are executed and ACK'd in FIFO order
// Note: you can only rely on this FIFO behaviour if your TLMasterParameters include requestFifo
val mayDenyGet: Boolean, // applies to: AccessAckData, GrantData
val mayDenyPut: Boolean) // applies to: AccessAck, Grant, HintAck
// ReleaseAck may NEVER be denied
extends SimpleProduct
{
def sortedAddress = address.sorted
override def canEqual(that: Any): Boolean = that.isInstanceOf[TLSlaveParameters]
override def productPrefix = "TLSlaveParameters"
// We intentionally omit nodePath for equality testing / formatting
def productArity: Int = 11
def productElement(n: Int): Any = n match {
case 0 => name
case 1 => address
case 2 => resources
case 3 => regionType
case 4 => executable
case 5 => fifoId
case 6 => supports
case 7 => emits
case 8 => alwaysGrantsT
case 9 => mayDenyGet
case 10 => mayDenyPut
case _ => throw new IndexOutOfBoundsException(n.toString)
}
def supportsAcquireT: TransferSizes = supports.acquireT
def supportsAcquireB: TransferSizes = supports.acquireB
def supportsArithmetic: TransferSizes = supports.arithmetic
def supportsLogical: TransferSizes = supports.logical
def supportsGet: TransferSizes = supports.get
def supportsPutFull: TransferSizes = supports.putFull
def supportsPutPartial: TransferSizes = supports.putPartial
def supportsHint: TransferSizes = supports.hint
require (!address.isEmpty, "Address cannot be empty")
address.foreach { a => require (a.finite, "Address must be finite") }
address.combinations(2).foreach { case Seq(x,y) => require (!x.overlaps(y), s"$x and $y overlap.") }
require (supportsPutFull.contains(supportsPutPartial), s"PutFull($supportsPutFull) < PutPartial($supportsPutPartial)")
require (supportsPutFull.contains(supportsArithmetic), s"PutFull($supportsPutFull) < Arithmetic($supportsArithmetic)")
require (supportsPutFull.contains(supportsLogical), s"PutFull($supportsPutFull) < Logical($supportsLogical)")
require (supportsGet.contains(supportsArithmetic), s"Get($supportsGet) < Arithmetic($supportsArithmetic)")
require (supportsGet.contains(supportsLogical), s"Get($supportsGet) < Logical($supportsLogical)")
require (supportsAcquireB.contains(supportsAcquireT), s"AcquireB($supportsAcquireB) < AcquireT($supportsAcquireT)")
require (!alwaysGrantsT || supportsAcquireT, s"Must supportAcquireT if promising to always grantT")
// Make sure that the regionType agrees with the capabilities
require (!supportsAcquireB || regionType >= RegionType.UNCACHED) // acquire -> uncached, tracked, cached
require (regionType <= RegionType.UNCACHED || supportsAcquireB) // tracked, cached -> acquire
require (regionType != RegionType.UNCACHED || supportsGet) // uncached -> supportsGet
val name = setName.orElse(nodePath.lastOption.map(_.lazyModule.name)).getOrElse("disconnected")
val maxTransfer = List( // Largest supported transfer of all types
supportsAcquireT.max,
supportsAcquireB.max,
supportsArithmetic.max,
supportsLogical.max,
supportsGet.max,
supportsPutFull.max,
supportsPutPartial.max).max
val maxAddress = address.map(_.max).max
val minAlignment = address.map(_.alignment).min
// The device had better not support a transfer larger than its alignment
require (minAlignment >= maxTransfer, s"Bad $address: minAlignment ($minAlignment) must be >= maxTransfer ($maxTransfer)")
def toResource: ResourceAddress = {
ResourceAddress(address, ResourcePermissions(
r = supportsAcquireB || supportsGet,
w = supportsAcquireT || supportsPutFull,
x = executable,
c = supportsAcquireB,
a = supportsArithmetic && supportsLogical))
}
def findTreeViolation() = nodePath.find {
case _: MixedAdapterNode[_, _, _, _, _, _, _, _] => false
case _: SinkNode[_, _, _, _, _] => false
case node => node.inputs.size != 1
}
def isTree = findTreeViolation() == None
def infoString = {
s"""Slave Name = ${name}
|Slave Address = ${address}
|supports = ${supports.infoString}
|
|""".stripMargin
}
def v1copy(
address: Seq[AddressSet] = address,
resources: Seq[Resource] = resources,
regionType: RegionType.T = regionType,
executable: Boolean = executable,
nodePath: Seq[BaseNode] = nodePath,
supportsAcquireT: TransferSizes = supports.acquireT,
supportsAcquireB: TransferSizes = supports.acquireB,
supportsArithmetic: TransferSizes = supports.arithmetic,
supportsLogical: TransferSizes = supports.logical,
supportsGet: TransferSizes = supports.get,
supportsPutFull: TransferSizes = supports.putFull,
supportsPutPartial: TransferSizes = supports.putPartial,
supportsHint: TransferSizes = supports.hint,
mayDenyGet: Boolean = mayDenyGet,
mayDenyPut: Boolean = mayDenyPut,
alwaysGrantsT: Boolean = alwaysGrantsT,
fifoId: Option[Int] = fifoId) =
{
new TLSlaveParameters(
setName = setName,
address = address,
resources = resources,
regionType = regionType,
executable = executable,
nodePath = nodePath,
supports = TLMasterToSlaveTransferSizes(
acquireT = supportsAcquireT,
acquireB = supportsAcquireB,
arithmetic = supportsArithmetic,
logical = supportsLogical,
get = supportsGet,
putFull = supportsPutFull,
putPartial = supportsPutPartial,
hint = supportsHint),
emits = emits,
mayDenyGet = mayDenyGet,
mayDenyPut = mayDenyPut,
alwaysGrantsT = alwaysGrantsT,
fifoId = fifoId)
}
def v2copy(
nodePath: Seq[BaseNode] = nodePath,
resources: Seq[Resource] = resources,
name: Option[String] = setName,
address: Seq[AddressSet] = address,
regionType: RegionType.T = regionType,
executable: Boolean = executable,
fifoId: Option[Int] = fifoId,
supports: TLMasterToSlaveTransferSizes = supports,
emits: TLSlaveToMasterTransferSizes = emits,
alwaysGrantsT: Boolean = alwaysGrantsT,
mayDenyGet: Boolean = mayDenyGet,
mayDenyPut: Boolean = mayDenyPut) =
{
new TLSlaveParameters(
nodePath = nodePath,
resources = resources,
setName = name,
address = address,
regionType = regionType,
executable = executable,
fifoId = fifoId,
supports = supports,
emits = emits,
alwaysGrantsT = alwaysGrantsT,
mayDenyGet = mayDenyGet,
mayDenyPut = mayDenyPut)
}
@deprecated("Use v1copy instead of copy","")
def copy(
address: Seq[AddressSet] = address,
resources: Seq[Resource] = resources,
regionType: RegionType.T = regionType,
executable: Boolean = executable,
nodePath: Seq[BaseNode] = nodePath,
supportsAcquireT: TransferSizes = supports.acquireT,
supportsAcquireB: TransferSizes = supports.acquireB,
supportsArithmetic: TransferSizes = supports.arithmetic,
supportsLogical: TransferSizes = supports.logical,
supportsGet: TransferSizes = supports.get,
supportsPutFull: TransferSizes = supports.putFull,
supportsPutPartial: TransferSizes = supports.putPartial,
supportsHint: TransferSizes = supports.hint,
mayDenyGet: Boolean = mayDenyGet,
mayDenyPut: Boolean = mayDenyPut,
alwaysGrantsT: Boolean = alwaysGrantsT,
fifoId: Option[Int] = fifoId) =
{
v1copy(
address = address,
resources = resources,
regionType = regionType,
executable = executable,
nodePath = nodePath,
supportsAcquireT = supportsAcquireT,
supportsAcquireB = supportsAcquireB,
supportsArithmetic = supportsArithmetic,
supportsLogical = supportsLogical,
supportsGet = supportsGet,
supportsPutFull = supportsPutFull,
supportsPutPartial = supportsPutPartial,
supportsHint = supportsHint,
mayDenyGet = mayDenyGet,
mayDenyPut = mayDenyPut,
alwaysGrantsT = alwaysGrantsT,
fifoId = fifoId)
}
}
object TLSlaveParameters {
def v1(
address: Seq[AddressSet],
resources: Seq[Resource] = Seq(),
regionType: RegionType.T = RegionType.GET_EFFECTS,
executable: Boolean = false,
nodePath: Seq[BaseNode] = Seq(),
supportsAcquireT: TransferSizes = TransferSizes.none,
supportsAcquireB: TransferSizes = TransferSizes.none,
supportsArithmetic: TransferSizes = TransferSizes.none,
supportsLogical: TransferSizes = TransferSizes.none,
supportsGet: TransferSizes = TransferSizes.none,
supportsPutFull: TransferSizes = TransferSizes.none,
supportsPutPartial: TransferSizes = TransferSizes.none,
supportsHint: TransferSizes = TransferSizes.none,
mayDenyGet: Boolean = false,
mayDenyPut: Boolean = false,
alwaysGrantsT: Boolean = false,
fifoId: Option[Int] = None) =
{
new TLSlaveParameters(
setName = None,
address = address,
resources = resources,
regionType = regionType,
executable = executable,
nodePath = nodePath,
supports = TLMasterToSlaveTransferSizes(
acquireT = supportsAcquireT,
acquireB = supportsAcquireB,
arithmetic = supportsArithmetic,
logical = supportsLogical,
get = supportsGet,
putFull = supportsPutFull,
putPartial = supportsPutPartial,
hint = supportsHint),
emits = TLSlaveToMasterTransferSizes.unknownEmits,
mayDenyGet = mayDenyGet,
mayDenyPut = mayDenyPut,
alwaysGrantsT = alwaysGrantsT,
fifoId = fifoId)
}
def v2(
address: Seq[AddressSet],
nodePath: Seq[BaseNode] = Seq(),
resources: Seq[Resource] = Seq(),
name: Option[String] = None,
regionType: RegionType.T = RegionType.GET_EFFECTS,
executable: Boolean = false,
fifoId: Option[Int] = None,
supports: TLMasterToSlaveTransferSizes = TLMasterToSlaveTransferSizes.unknownSupports,
emits: TLSlaveToMasterTransferSizes = TLSlaveToMasterTransferSizes.unknownEmits,
alwaysGrantsT: Boolean = false,
mayDenyGet: Boolean = false,
mayDenyPut: Boolean = false) =
{
new TLSlaveParameters(
nodePath = nodePath,
resources = resources,
setName = name,
address = address,
regionType = regionType,
executable = executable,
fifoId = fifoId,
supports = supports,
emits = emits,
alwaysGrantsT = alwaysGrantsT,
mayDenyGet = mayDenyGet,
mayDenyPut = mayDenyPut)
}
}
object TLManagerParameters {
@deprecated("Use TLSlaveParameters.v1 instead of TLManagerParameters","")
def apply(
address: Seq[AddressSet],
resources: Seq[Resource] = Seq(),
regionType: RegionType.T = RegionType.GET_EFFECTS,
executable: Boolean = false,
nodePath: Seq[BaseNode] = Seq(),
supportsAcquireT: TransferSizes = TransferSizes.none,
supportsAcquireB: TransferSizes = TransferSizes.none,
supportsArithmetic: TransferSizes = TransferSizes.none,
supportsLogical: TransferSizes = TransferSizes.none,
supportsGet: TransferSizes = TransferSizes.none,
supportsPutFull: TransferSizes = TransferSizes.none,
supportsPutPartial: TransferSizes = TransferSizes.none,
supportsHint: TransferSizes = TransferSizes.none,
mayDenyGet: Boolean = false,
mayDenyPut: Boolean = false,
alwaysGrantsT: Boolean = false,
fifoId: Option[Int] = None) =
TLSlaveParameters.v1(
address,
resources,
regionType,
executable,
nodePath,
supportsAcquireT,
supportsAcquireB,
supportsArithmetic,
supportsLogical,
supportsGet,
supportsPutFull,
supportsPutPartial,
supportsHint,
mayDenyGet,
mayDenyPut,
alwaysGrantsT,
fifoId,
)
}
case class TLChannelBeatBytes(a: Option[Int], b: Option[Int], c: Option[Int], d: Option[Int])
{
def members = Seq(a, b, c, d)
members.collect { case Some(beatBytes) =>
require (isPow2(beatBytes), "Data channel width must be a power of 2")
}
}
object TLChannelBeatBytes{
def apply(beatBytes: Int): TLChannelBeatBytes = TLChannelBeatBytes(
Some(beatBytes),
Some(beatBytes),
Some(beatBytes),
Some(beatBytes))
def apply(): TLChannelBeatBytes = TLChannelBeatBytes(
None,
None,
None,
None)
}
class TLSlavePortParameters private(
val slaves: Seq[TLSlaveParameters],
val channelBytes: TLChannelBeatBytes,
val endSinkId: Int,
val minLatency: Int,
val responseFields: Seq[BundleFieldBase],
val requestKeys: Seq[BundleKeyBase]) extends SimpleProduct
{
def sortedSlaves = slaves.sortBy(_.sortedAddress.head)
override def canEqual(that: Any): Boolean = that.isInstanceOf[TLSlavePortParameters]
override def productPrefix = "TLSlavePortParameters"
def productArity: Int = 6
def productElement(n: Int): Any = n match {
case 0 => slaves
case 1 => channelBytes
case 2 => endSinkId
case 3 => minLatency
case 4 => responseFields
case 5 => requestKeys
case _ => throw new IndexOutOfBoundsException(n.toString)
}
require (!slaves.isEmpty, "Slave ports must have slaves")
require (endSinkId >= 0, "Sink ids cannot be negative")
require (minLatency >= 0, "Minimum required latency cannot be negative")
// Using this API implies you cannot handle mixed-width busses
def beatBytes = {
channelBytes.members.foreach { width =>
require (width.isDefined && width == channelBytes.a)
}
channelBytes.a.get
}
// TODO this should be deprecated
def managers = slaves
def requireFifo(policy: TLFIFOFixer.Policy = TLFIFOFixer.allFIFO) = {
val relevant = slaves.filter(m => policy(m))
relevant.foreach { m =>
require(m.fifoId == relevant.head.fifoId, s"${m.name} had fifoId ${m.fifoId}, which was not homogeneous (${slaves.map(s => (s.name, s.fifoId))}) ")
}
}
// Bounds on required sizes
def maxAddress = slaves.map(_.maxAddress).max
def maxTransfer = slaves.map(_.maxTransfer).max
def mayDenyGet = slaves.exists(_.mayDenyGet)
def mayDenyPut = slaves.exists(_.mayDenyPut)
// Diplomatically determined operation sizes emitted by all outward Slaves
// as opposed to emits* which generate circuitry to check which specific addresses
val allEmitClaims = slaves.map(_.emits).reduce( _ intersect _)
// Operation Emitted by at least one outward Slaves
// as opposed to emits* which generate circuitry to check which specific addresses
val anyEmitClaims = slaves.map(_.emits).reduce(_ mincover _)
// Diplomatically determined operation sizes supported by all outward Slaves
// as opposed to supports* which generate circuitry to check which specific addresses
val allSupportClaims = slaves.map(_.supports).reduce( _ intersect _)
val allSupportAcquireT = allSupportClaims.acquireT
val allSupportAcquireB = allSupportClaims.acquireB
val allSupportArithmetic = allSupportClaims.arithmetic
val allSupportLogical = allSupportClaims.logical
val allSupportGet = allSupportClaims.get
val allSupportPutFull = allSupportClaims.putFull
val allSupportPutPartial = allSupportClaims.putPartial
val allSupportHint = allSupportClaims.hint
// Operation supported by at least one outward Slaves
// as opposed to supports* which generate circuitry to check which specific addresses
val anySupportClaims = slaves.map(_.supports).reduce(_ mincover _)
val anySupportAcquireT = !anySupportClaims.acquireT.none
val anySupportAcquireB = !anySupportClaims.acquireB.none
val anySupportArithmetic = !anySupportClaims.arithmetic.none
val anySupportLogical = !anySupportClaims.logical.none
val anySupportGet = !anySupportClaims.get.none
val anySupportPutFull = !anySupportClaims.putFull.none
val anySupportPutPartial = !anySupportClaims.putPartial.none
val anySupportHint = !anySupportClaims.hint.none
// Supporting Acquire means being routable for GrantAck
require ((endSinkId == 0) == !anySupportAcquireB)
// These return Option[TLSlaveParameters] for your convenience
def find(address: BigInt) = slaves.find(_.address.exists(_.contains(address)))
// The safe version will check the entire address
def findSafe(address: UInt) = VecInit(sortedSlaves.map(_.address.map(_.contains(address)).reduce(_ || _)))
// The fast version assumes the address is valid (you probably want fastProperty instead of this function)
def findFast(address: UInt) = {
val routingMask = AddressDecoder(slaves.map(_.address))
VecInit(sortedSlaves.map(_.address.map(_.widen(~routingMask)).distinct.map(_.contains(address)).reduce(_ || _)))
}
// Compute the simplest AddressSets that decide a key
def fastPropertyGroup[K](p: TLSlaveParameters => K): Seq[(K, Seq[AddressSet])] = {
val groups = groupByIntoSeq(sortedSlaves.map(m => (p(m), m.address)))( _._1).map { case (k, vs) =>
k -> vs.flatMap(_._2)
}
val reductionMask = AddressDecoder(groups.map(_._2))
groups.map { case (k, seq) => k -> AddressSet.unify(seq.map(_.widen(~reductionMask)).distinct) }
}
// Select a property
def fastProperty[K, D <: Data](address: UInt, p: TLSlaveParameters => K, d: K => D): D =
Mux1H(fastPropertyGroup(p).map { case (v, a) => (a.map(_.contains(address)).reduce(_||_), d(v)) })
// Note: returns the actual fifoId + 1 or 0 if None
def findFifoIdFast(address: UInt) = fastProperty(address, _.fifoId.map(_+1).getOrElse(0), (i:Int) => i.U)
def hasFifoIdFast(address: UInt) = fastProperty(address, _.fifoId.isDefined, (b:Boolean) => b.B)
// Does this Port manage this ID/address?
def containsSafe(address: UInt) = findSafe(address).reduce(_ || _)
private def addressHelper(
// setting safe to false indicates that all addresses are expected to be legal, which might reduce circuit complexity
safe: Boolean,
// member filters out the sizes being checked based on the opcode being emitted or supported
member: TLSlaveParameters => TransferSizes,
address: UInt,
lgSize: UInt,
// range provides a limit on the sizes that are expected to be evaluated, which might reduce circuit complexity
range: Option[TransferSizes]): Bool = {
// trim reduces circuit complexity by intersecting checked sizes with the range argument
def trim(x: TransferSizes) = range.map(_.intersect(x)).getOrElse(x)
// groupBy returns an unordered map, convert back to Seq and sort the result for determinism
// groupByIntoSeq is turning slaves into trimmed membership sizes
// We are grouping all the slaves by their transfer size where
// if they support the trimmed size then
// member is the type of transfer that you are looking for (What you are trying to filter on)
// When you consider membership, you are trimming the sizes to only the ones that you care about
// you are filtering the slaves based on both whether they support a particular opcode and the size
// Grouping the slaves based on the actual transfer size range they support
// intersecting the range and checking their membership
// FOR SUPPORTCASES instead of returning the list of slaves,
// you are returning a map from transfer size to the set of
// address sets that are supported for that transfer size
// find all the slaves that support a certain type of operation and then group their addresses by the supported size
// for every size there could be multiple address ranges
// safety is a trade off between checking between all possible addresses vs only the addresses
// that are known to have supported sizes
// the trade off is 'checking all addresses is a more expensive circuit but will always give you
// the right answer even if you give it an illegal address'
// the not safe version is a cheaper circuit but if you give it an illegal address then it might produce the wrong answer
// fast presumes address legality
// This groupByIntoSeq deterministically groups all address sets for which a given `member` transfer size applies.
// In the resulting Map of cases, the keys are transfer sizes and the values are all address sets which emit or support that size.
val supportCases = groupByIntoSeq(slaves)(m => trim(member(m))).map { case (k: TransferSizes, vs: Seq[TLSlaveParameters]) =>
k -> vs.flatMap(_.address)
}
// safe produces a circuit that compares against all possible addresses,
// whereas fast presumes that the address is legal but uses an efficient address decoder
val mask = if (safe) ~BigInt(0) else AddressDecoder(supportCases.map(_._2))
// Simplified creates the most concise possible representation of each cases' address sets based on the mask.
val simplified = supportCases.map { case (k, seq) => k -> AddressSet.unify(seq.map(_.widen(~mask)).distinct) }
simplified.map { case (s, a) =>
// s is a size, you are checking for this size either the size of the operation is in s
// We return an or-reduction of all the cases, checking whether any contains both the dynamic size and dynamic address on the wire.
((Some(s) == range).B || s.containsLg(lgSize)) &&
a.map(_.contains(address)).reduce(_||_)
}.foldLeft(false.B)(_||_)
}
def supportsAcquireTSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.acquireT, address, lgSize, range)
def supportsAcquireBSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.acquireB, address, lgSize, range)
def supportsArithmeticSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.arithmetic, address, lgSize, range)
def supportsLogicalSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.logical, address, lgSize, range)
def supportsGetSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.get, address, lgSize, range)
def supportsPutFullSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.putFull, address, lgSize, range)
def supportsPutPartialSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.putPartial, address, lgSize, range)
def supportsHintSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.hint, address, lgSize, range)
def supportsAcquireTFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.acquireT, address, lgSize, range)
def supportsAcquireBFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.acquireB, address, lgSize, range)
def supportsArithmeticFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.arithmetic, address, lgSize, range)
def supportsLogicalFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.logical, address, lgSize, range)
def supportsGetFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.get, address, lgSize, range)
def supportsPutFullFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.putFull, address, lgSize, range)
def supportsPutPartialFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.putPartial, address, lgSize, range)
def supportsHintFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.hint, address, lgSize, range)
def emitsProbeSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.probe, address, lgSize, range)
def emitsArithmeticSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.arithmetic, address, lgSize, range)
def emitsLogicalSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.logical, address, lgSize, range)
def emitsGetSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.get, address, lgSize, range)
def emitsPutFullSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.putFull, address, lgSize, range)
def emitsPutPartialSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.putPartial, address, lgSize, range)
def emitsHintSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.hint, address, lgSize, range)
def findTreeViolation() = slaves.flatMap(_.findTreeViolation()).headOption
def isTree = !slaves.exists(!_.isTree)
def infoString = "Slave Port Beatbytes = " + beatBytes + "\n" + "Slave Port MinLatency = " + minLatency + "\n\n" + slaves.map(_.infoString).mkString
def v1copy(
managers: Seq[TLSlaveParameters] = slaves,
beatBytes: Int = -1,
endSinkId: Int = endSinkId,
minLatency: Int = minLatency,
responseFields: Seq[BundleFieldBase] = responseFields,
requestKeys: Seq[BundleKeyBase] = requestKeys) =
{
new TLSlavePortParameters(
slaves = managers,
channelBytes = if (beatBytes != -1) TLChannelBeatBytes(beatBytes) else channelBytes,
endSinkId = endSinkId,
minLatency = minLatency,
responseFields = responseFields,
requestKeys = requestKeys)
}
def v2copy(
slaves: Seq[TLSlaveParameters] = slaves,
channelBytes: TLChannelBeatBytes = channelBytes,
endSinkId: Int = endSinkId,
minLatency: Int = minLatency,
responseFields: Seq[BundleFieldBase] = responseFields,
requestKeys: Seq[BundleKeyBase] = requestKeys) =
{
new TLSlavePortParameters(
slaves = slaves,
channelBytes = channelBytes,
endSinkId = endSinkId,
minLatency = minLatency,
responseFields = responseFields,
requestKeys = requestKeys)
}
@deprecated("Use v1copy instead of copy","")
def copy(
managers: Seq[TLSlaveParameters] = slaves,
beatBytes: Int = -1,
endSinkId: Int = endSinkId,
minLatency: Int = minLatency,
responseFields: Seq[BundleFieldBase] = responseFields,
requestKeys: Seq[BundleKeyBase] = requestKeys) =
{
v1copy(
managers,
beatBytes,
endSinkId,
minLatency,
responseFields,
requestKeys)
}
}
object TLSlavePortParameters {
def v1(
managers: Seq[TLSlaveParameters],
beatBytes: Int,
endSinkId: Int = 0,
minLatency: Int = 0,
responseFields: Seq[BundleFieldBase] = Nil,
requestKeys: Seq[BundleKeyBase] = Nil) =
{
new TLSlavePortParameters(
slaves = managers,
channelBytes = TLChannelBeatBytes(beatBytes),
endSinkId = endSinkId,
minLatency = minLatency,
responseFields = responseFields,
requestKeys = requestKeys)
}
}
object TLManagerPortParameters {
@deprecated("Use TLSlavePortParameters.v1 instead of TLManagerPortParameters","")
def apply(
managers: Seq[TLSlaveParameters],
beatBytes: Int,
endSinkId: Int = 0,
minLatency: Int = 0,
responseFields: Seq[BundleFieldBase] = Nil,
requestKeys: Seq[BundleKeyBase] = Nil) =
{
TLSlavePortParameters.v1(
managers,
beatBytes,
endSinkId,
minLatency,
responseFields,
requestKeys)
}
}
class TLMasterParameters private(
val nodePath: Seq[BaseNode],
val resources: Seq[Resource],
val name: String,
val visibility: Seq[AddressSet],
val unusedRegionTypes: Set[RegionType.T],
val executesOnly: Boolean,
val requestFifo: Boolean, // only a request, not a requirement. applies to A, not C.
val supports: TLSlaveToMasterTransferSizes,
val emits: TLMasterToSlaveTransferSizes,
val neverReleasesData: Boolean,
val sourceId: IdRange) extends SimpleProduct
{
override def canEqual(that: Any): Boolean = that.isInstanceOf[TLMasterParameters]
override def productPrefix = "TLMasterParameters"
// We intentionally omit nodePath for equality testing / formatting
def productArity: Int = 10
def productElement(n: Int): Any = n match {
case 0 => name
case 1 => sourceId
case 2 => resources
case 3 => visibility
case 4 => unusedRegionTypes
case 5 => executesOnly
case 6 => requestFifo
case 7 => supports
case 8 => emits
case 9 => neverReleasesData
case _ => throw new IndexOutOfBoundsException(n.toString)
}
require (!sourceId.isEmpty)
require (!visibility.isEmpty)
require (supports.putFull.contains(supports.putPartial))
// We only support these operations if we support Probe (ie: we're a cache)
require (supports.probe.contains(supports.arithmetic))
require (supports.probe.contains(supports.logical))
require (supports.probe.contains(supports.get))
require (supports.probe.contains(supports.putFull))
require (supports.probe.contains(supports.putPartial))
require (supports.probe.contains(supports.hint))
visibility.combinations(2).foreach { case Seq(x,y) => require (!x.overlaps(y), s"$x and $y overlap.") }
val maxTransfer = List(
supports.probe.max,
supports.arithmetic.max,
supports.logical.max,
supports.get.max,
supports.putFull.max,
supports.putPartial.max).max
def infoString = {
s"""Master Name = ${name}
|visibility = ${visibility}
|emits = ${emits.infoString}
|sourceId = ${sourceId}
|
|""".stripMargin
}
def v1copy(
name: String = name,
sourceId: IdRange = sourceId,
nodePath: Seq[BaseNode] = nodePath,
requestFifo: Boolean = requestFifo,
visibility: Seq[AddressSet] = visibility,
supportsProbe: TransferSizes = supports.probe,
supportsArithmetic: TransferSizes = supports.arithmetic,
supportsLogical: TransferSizes = supports.logical,
supportsGet: TransferSizes = supports.get,
supportsPutFull: TransferSizes = supports.putFull,
supportsPutPartial: TransferSizes = supports.putPartial,
supportsHint: TransferSizes = supports.hint) =
{
new TLMasterParameters(
nodePath = nodePath,
resources = this.resources,
name = name,
visibility = visibility,
unusedRegionTypes = this.unusedRegionTypes,
executesOnly = this.executesOnly,
requestFifo = requestFifo,
supports = TLSlaveToMasterTransferSizes(
probe = supportsProbe,
arithmetic = supportsArithmetic,
logical = supportsLogical,
get = supportsGet,
putFull = supportsPutFull,
putPartial = supportsPutPartial,
hint = supportsHint),
emits = this.emits,
neverReleasesData = this.neverReleasesData,
sourceId = sourceId)
}
def v2copy(
nodePath: Seq[BaseNode] = nodePath,
resources: Seq[Resource] = resources,
name: String = name,
visibility: Seq[AddressSet] = visibility,
unusedRegionTypes: Set[RegionType.T] = unusedRegionTypes,
executesOnly: Boolean = executesOnly,
requestFifo: Boolean = requestFifo,
supports: TLSlaveToMasterTransferSizes = supports,
emits: TLMasterToSlaveTransferSizes = emits,
neverReleasesData: Boolean = neverReleasesData,
sourceId: IdRange = sourceId) =
{
new TLMasterParameters(
nodePath = nodePath,
resources = resources,
name = name,
visibility = visibility,
unusedRegionTypes = unusedRegionTypes,
executesOnly = executesOnly,
requestFifo = requestFifo,
supports = supports,
emits = emits,
neverReleasesData = neverReleasesData,
sourceId = sourceId)
}
@deprecated("Use v1copy instead of copy","")
def copy(
name: String = name,
sourceId: IdRange = sourceId,
nodePath: Seq[BaseNode] = nodePath,
requestFifo: Boolean = requestFifo,
visibility: Seq[AddressSet] = visibility,
supportsProbe: TransferSizes = supports.probe,
supportsArithmetic: TransferSizes = supports.arithmetic,
supportsLogical: TransferSizes = supports.logical,
supportsGet: TransferSizes = supports.get,
supportsPutFull: TransferSizes = supports.putFull,
supportsPutPartial: TransferSizes = supports.putPartial,
supportsHint: TransferSizes = supports.hint) =
{
v1copy(
name = name,
sourceId = sourceId,
nodePath = nodePath,
requestFifo = requestFifo,
visibility = visibility,
supportsProbe = supportsProbe,
supportsArithmetic = supportsArithmetic,
supportsLogical = supportsLogical,
supportsGet = supportsGet,
supportsPutFull = supportsPutFull,
supportsPutPartial = supportsPutPartial,
supportsHint = supportsHint)
}
}
object TLMasterParameters {
def v1(
name: String,
sourceId: IdRange = IdRange(0,1),
nodePath: Seq[BaseNode] = Seq(),
requestFifo: Boolean = false,
visibility: Seq[AddressSet] = Seq(AddressSet(0, ~0)),
supportsProbe: TransferSizes = TransferSizes.none,
supportsArithmetic: TransferSizes = TransferSizes.none,
supportsLogical: TransferSizes = TransferSizes.none,
supportsGet: TransferSizes = TransferSizes.none,
supportsPutFull: TransferSizes = TransferSizes.none,
supportsPutPartial: TransferSizes = TransferSizes.none,
supportsHint: TransferSizes = TransferSizes.none) =
{
new TLMasterParameters(
nodePath = nodePath,
resources = Nil,
name = name,
visibility = visibility,
unusedRegionTypes = Set(),
executesOnly = false,
requestFifo = requestFifo,
supports = TLSlaveToMasterTransferSizes(
probe = supportsProbe,
arithmetic = supportsArithmetic,
logical = supportsLogical,
get = supportsGet,
putFull = supportsPutFull,
putPartial = supportsPutPartial,
hint = supportsHint),
emits = TLMasterToSlaveTransferSizes.unknownEmits,
neverReleasesData = false,
sourceId = sourceId)
}
def v2(
nodePath: Seq[BaseNode] = Seq(),
resources: Seq[Resource] = Nil,
name: String,
visibility: Seq[AddressSet] = Seq(AddressSet(0, ~0)),
unusedRegionTypes: Set[RegionType.T] = Set(),
executesOnly: Boolean = false,
requestFifo: Boolean = false,
supports: TLSlaveToMasterTransferSizes = TLSlaveToMasterTransferSizes.unknownSupports,
emits: TLMasterToSlaveTransferSizes = TLMasterToSlaveTransferSizes.unknownEmits,
neverReleasesData: Boolean = false,
sourceId: IdRange = IdRange(0,1)) =
{
new TLMasterParameters(
nodePath = nodePath,
resources = resources,
name = name,
visibility = visibility,
unusedRegionTypes = unusedRegionTypes,
executesOnly = executesOnly,
requestFifo = requestFifo,
supports = supports,
emits = emits,
neverReleasesData = neverReleasesData,
sourceId = sourceId)
}
}
object TLClientParameters {
@deprecated("Use TLMasterParameters.v1 instead of TLClientParameters","")
def apply(
name: String,
sourceId: IdRange = IdRange(0,1),
nodePath: Seq[BaseNode] = Seq(),
requestFifo: Boolean = false,
visibility: Seq[AddressSet] = Seq(AddressSet.everything),
supportsProbe: TransferSizes = TransferSizes.none,
supportsArithmetic: TransferSizes = TransferSizes.none,
supportsLogical: TransferSizes = TransferSizes.none,
supportsGet: TransferSizes = TransferSizes.none,
supportsPutFull: TransferSizes = TransferSizes.none,
supportsPutPartial: TransferSizes = TransferSizes.none,
supportsHint: TransferSizes = TransferSizes.none) =
{
TLMasterParameters.v1(
name = name,
sourceId = sourceId,
nodePath = nodePath,
requestFifo = requestFifo,
visibility = visibility,
supportsProbe = supportsProbe,
supportsArithmetic = supportsArithmetic,
supportsLogical = supportsLogical,
supportsGet = supportsGet,
supportsPutFull = supportsPutFull,
supportsPutPartial = supportsPutPartial,
supportsHint = supportsHint)
}
}
class TLMasterPortParameters private(
val masters: Seq[TLMasterParameters],
val channelBytes: TLChannelBeatBytes,
val minLatency: Int,
val echoFields: Seq[BundleFieldBase],
val requestFields: Seq[BundleFieldBase],
val responseKeys: Seq[BundleKeyBase]) extends SimpleProduct
{
override def canEqual(that: Any): Boolean = that.isInstanceOf[TLMasterPortParameters]
override def productPrefix = "TLMasterPortParameters"
def productArity: Int = 6
def productElement(n: Int): Any = n match {
case 0 => masters
case 1 => channelBytes
case 2 => minLatency
case 3 => echoFields
case 4 => requestFields
case 5 => responseKeys
case _ => throw new IndexOutOfBoundsException(n.toString)
}
require (!masters.isEmpty)
require (minLatency >= 0)
def clients = masters
// Require disjoint ranges for Ids
IdRange.overlaps(masters.map(_.sourceId)).foreach { case (x, y) =>
require (!x.overlaps(y), s"TLClientParameters.sourceId ${x} overlaps ${y}")
}
// Bounds on required sizes
def endSourceId = masters.map(_.sourceId.end).max
def maxTransfer = masters.map(_.maxTransfer).max
// The unused sources < endSourceId
def unusedSources: Seq[Int] = {
val usedSources = masters.map(_.sourceId).sortBy(_.start)
((Seq(0) ++ usedSources.map(_.end)) zip usedSources.map(_.start)) flatMap { case (end, start) =>
end until start
}
}
// Diplomatically determined operation sizes emitted by all inward Masters
// as opposed to emits* which generate circuitry to check which specific addresses
val allEmitClaims = masters.map(_.emits).reduce( _ intersect _)
// Diplomatically determined operation sizes Emitted by at least one inward Masters
// as opposed to emits* which generate circuitry to check which specific addresses
val anyEmitClaims = masters.map(_.emits).reduce(_ mincover _)
// Diplomatically determined operation sizes supported by all inward Masters
// as opposed to supports* which generate circuitry to check which specific addresses
val allSupportProbe = masters.map(_.supports.probe) .reduce(_ intersect _)
val allSupportArithmetic = masters.map(_.supports.arithmetic).reduce(_ intersect _)
val allSupportLogical = masters.map(_.supports.logical) .reduce(_ intersect _)
val allSupportGet = masters.map(_.supports.get) .reduce(_ intersect _)
val allSupportPutFull = masters.map(_.supports.putFull) .reduce(_ intersect _)
val allSupportPutPartial = masters.map(_.supports.putPartial).reduce(_ intersect _)
val allSupportHint = masters.map(_.supports.hint) .reduce(_ intersect _)
// Diplomatically determined operation sizes supported by at least one master
// as opposed to supports* which generate circuitry to check which specific addresses
val anySupportProbe = masters.map(!_.supports.probe.none) .reduce(_ || _)
val anySupportArithmetic = masters.map(!_.supports.arithmetic.none).reduce(_ || _)
val anySupportLogical = masters.map(!_.supports.logical.none) .reduce(_ || _)
val anySupportGet = masters.map(!_.supports.get.none) .reduce(_ || _)
val anySupportPutFull = masters.map(!_.supports.putFull.none) .reduce(_ || _)
val anySupportPutPartial = masters.map(!_.supports.putPartial.none).reduce(_ || _)
val anySupportHint = masters.map(!_.supports.hint.none) .reduce(_ || _)
// These return Option[TLMasterParameters] for your convenience
def find(id: Int) = masters.find(_.sourceId.contains(id))
// Synthesizable lookup methods
def find(id: UInt) = VecInit(masters.map(_.sourceId.contains(id)))
def contains(id: UInt) = find(id).reduce(_ || _)
def requestFifo(id: UInt) = Mux1H(find(id), masters.map(c => c.requestFifo.B))
// Available during RTL runtime, checks to see if (id, size) is supported by the master's (client's) diplomatic parameters
private def sourceIdHelper(member: TLMasterParameters => TransferSizes)(id: UInt, lgSize: UInt) = {
val allSame = masters.map(member(_) == member(masters(0))).reduce(_ && _)
// this if statement is a coarse generalization of the groupBy in the sourceIdHelper2 version;
// the case where there is only one group.
if (allSame) member(masters(0)).containsLg(lgSize) else {
// Find the master associated with ID and returns whether that particular master is able to receive transaction of lgSize
Mux1H(find(id), masters.map(member(_).containsLg(lgSize)))
}
}
// Check for support of a given operation at a specific id
val supportsProbe = sourceIdHelper(_.supports.probe) _
val supportsArithmetic = sourceIdHelper(_.supports.arithmetic) _
val supportsLogical = sourceIdHelper(_.supports.logical) _
val supportsGet = sourceIdHelper(_.supports.get) _
val supportsPutFull = sourceIdHelper(_.supports.putFull) _
val supportsPutPartial = sourceIdHelper(_.supports.putPartial) _
val supportsHint = sourceIdHelper(_.supports.hint) _
// TODO: Merge sourceIdHelper2 with sourceIdHelper
private def sourceIdHelper2(
member: TLMasterParameters => TransferSizes,
sourceId: UInt,
lgSize: UInt): Bool = {
// Because sourceIds are uniquely owned by each master, we use them to group the
// cases that have to be checked.
val emitCases = groupByIntoSeq(masters)(m => member(m)).map { case (k, vs) =>
k -> vs.map(_.sourceId)
}
emitCases.map { case (s, a) =>
(s.containsLg(lgSize)) &&
a.map(_.contains(sourceId)).reduce(_||_)
}.foldLeft(false.B)(_||_)
}
// Check for emit of a given operation at a specific id
def emitsAcquireT (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.acquireT, sourceId, lgSize)
def emitsAcquireB (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.acquireB, sourceId, lgSize)
def emitsArithmetic(sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.arithmetic, sourceId, lgSize)
def emitsLogical (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.logical, sourceId, lgSize)
def emitsGet (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.get, sourceId, lgSize)
def emitsPutFull (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.putFull, sourceId, lgSize)
def emitsPutPartial(sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.putPartial, sourceId, lgSize)
def emitsHint (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.hint, sourceId, lgSize)
def infoString = masters.map(_.infoString).mkString
def v1copy(
clients: Seq[TLMasterParameters] = masters,
minLatency: Int = minLatency,
echoFields: Seq[BundleFieldBase] = echoFields,
requestFields: Seq[BundleFieldBase] = requestFields,
responseKeys: Seq[BundleKeyBase] = responseKeys) =
{
new TLMasterPortParameters(
masters = clients,
channelBytes = channelBytes,
minLatency = minLatency,
echoFields = echoFields,
requestFields = requestFields,
responseKeys = responseKeys)
}
def v2copy(
masters: Seq[TLMasterParameters] = masters,
channelBytes: TLChannelBeatBytes = channelBytes,
minLatency: Int = minLatency,
echoFields: Seq[BundleFieldBase] = echoFields,
requestFields: Seq[BundleFieldBase] = requestFields,
responseKeys: Seq[BundleKeyBase] = responseKeys) =
{
new TLMasterPortParameters(
masters = masters,
channelBytes = channelBytes,
minLatency = minLatency,
echoFields = echoFields,
requestFields = requestFields,
responseKeys = responseKeys)
}
@deprecated("Use v1copy instead of copy","")
def copy(
clients: Seq[TLMasterParameters] = masters,
minLatency: Int = minLatency,
echoFields: Seq[BundleFieldBase] = echoFields,
requestFields: Seq[BundleFieldBase] = requestFields,
responseKeys: Seq[BundleKeyBase] = responseKeys) =
{
v1copy(
clients,
minLatency,
echoFields,
requestFields,
responseKeys)
}
}
object TLClientPortParameters {
@deprecated("Use TLMasterPortParameters.v1 instead of TLClientPortParameters","")
def apply(
clients: Seq[TLMasterParameters],
minLatency: Int = 0,
echoFields: Seq[BundleFieldBase] = Nil,
requestFields: Seq[BundleFieldBase] = Nil,
responseKeys: Seq[BundleKeyBase] = Nil) =
{
TLMasterPortParameters.v1(
clients,
minLatency,
echoFields,
requestFields,
responseKeys)
}
}
object TLMasterPortParameters {
def v1(
clients: Seq[TLMasterParameters],
minLatency: Int = 0,
echoFields: Seq[BundleFieldBase] = Nil,
requestFields: Seq[BundleFieldBase] = Nil,
responseKeys: Seq[BundleKeyBase] = Nil) =
{
new TLMasterPortParameters(
masters = clients,
channelBytes = TLChannelBeatBytes(),
minLatency = minLatency,
echoFields = echoFields,
requestFields = requestFields,
responseKeys = responseKeys)
}
def v2(
masters: Seq[TLMasterParameters],
channelBytes: TLChannelBeatBytes = TLChannelBeatBytes(),
minLatency: Int = 0,
echoFields: Seq[BundleFieldBase] = Nil,
requestFields: Seq[BundleFieldBase] = Nil,
responseKeys: Seq[BundleKeyBase] = Nil) =
{
new TLMasterPortParameters(
masters = masters,
channelBytes = channelBytes,
minLatency = minLatency,
echoFields = echoFields,
requestFields = requestFields,
responseKeys = responseKeys)
}
}
case class TLBundleParameters(
addressBits: Int,
dataBits: Int,
sourceBits: Int,
sinkBits: Int,
sizeBits: Int,
echoFields: Seq[BundleFieldBase],
requestFields: Seq[BundleFieldBase],
responseFields: Seq[BundleFieldBase],
hasBCE: Boolean)
{
// Chisel has issues with 0-width wires
require (addressBits >= 1)
require (dataBits >= 8)
require (sourceBits >= 1)
require (sinkBits >= 1)
require (sizeBits >= 1)
require (isPow2(dataBits))
echoFields.foreach { f => require (f.key.isControl, s"${f} is not a legal echo field") }
val addrLoBits = log2Up(dataBits/8)
// Used to uniquify bus IP names
def shortName = s"a${addressBits}d${dataBits}s${sourceBits}k${sinkBits}z${sizeBits}" + (if (hasBCE) "c" else "u")
def union(x: TLBundleParameters) =
TLBundleParameters(
max(addressBits, x.addressBits),
max(dataBits, x.dataBits),
max(sourceBits, x.sourceBits),
max(sinkBits, x.sinkBits),
max(sizeBits, x.sizeBits),
echoFields = BundleField.union(echoFields ++ x.echoFields),
requestFields = BundleField.union(requestFields ++ x.requestFields),
responseFields = BundleField.union(responseFields ++ x.responseFields),
hasBCE || x.hasBCE)
}
object TLBundleParameters
{
val emptyBundleParams = TLBundleParameters(
addressBits = 1,
dataBits = 8,
sourceBits = 1,
sinkBits = 1,
sizeBits = 1,
echoFields = Nil,
requestFields = Nil,
responseFields = Nil,
hasBCE = false)
def union(x: Seq[TLBundleParameters]) = x.foldLeft(emptyBundleParams)((x,y) => x.union(y))
def apply(master: TLMasterPortParameters, slave: TLSlavePortParameters) =
new TLBundleParameters(
addressBits = log2Up(slave.maxAddress + 1),
dataBits = slave.beatBytes * 8,
sourceBits = log2Up(master.endSourceId),
sinkBits = log2Up(slave.endSinkId),
sizeBits = log2Up(log2Ceil(max(master.maxTransfer, slave.maxTransfer))+1),
echoFields = master.echoFields,
requestFields = BundleField.accept(master.requestFields, slave.requestKeys),
responseFields = BundleField.accept(slave.responseFields, master.responseKeys),
hasBCE = master.anySupportProbe && slave.anySupportAcquireB)
}
case class TLEdgeParameters(
master: TLMasterPortParameters,
slave: TLSlavePortParameters,
params: Parameters,
sourceInfo: SourceInfo) extends FormatEdge
{
// legacy names:
def manager = slave
def client = master
val maxTransfer = max(master.maxTransfer, slave.maxTransfer)
val maxLgSize = log2Ceil(maxTransfer)
// Sanity check the link...
require (maxTransfer >= slave.beatBytes, s"Link's max transfer (${maxTransfer}) < ${slave.slaves.map(_.name)}'s beatBytes (${slave.beatBytes})")
def diplomaticClaimsMasterToSlave = master.anyEmitClaims.intersect(slave.anySupportClaims)
val bundle = TLBundleParameters(master, slave)
def formatEdge = master.infoString + "\n" + slave.infoString
}
case class TLCreditedDelay(
a: CreditedDelay,
b: CreditedDelay,
c: CreditedDelay,
d: CreditedDelay,
e: CreditedDelay)
{
def + (that: TLCreditedDelay): TLCreditedDelay = TLCreditedDelay(
a = a + that.a,
b = b + that.b,
c = c + that.c,
d = d + that.d,
e = e + that.e)
override def toString = s"(${a}, ${b}, ${c}, ${d}, ${e})"
}
object TLCreditedDelay {
def apply(delay: CreditedDelay): TLCreditedDelay = apply(delay, delay.flip, delay, delay.flip, delay)
}
case class TLCreditedManagerPortParameters(delay: TLCreditedDelay, base: TLSlavePortParameters) {def infoString = base.infoString}
case class TLCreditedClientPortParameters(delay: TLCreditedDelay, base: TLMasterPortParameters) {def infoString = base.infoString}
case class TLCreditedEdgeParameters(client: TLCreditedClientPortParameters, manager: TLCreditedManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge
{
val delay = client.delay + manager.delay
val bundle = TLBundleParameters(client.base, manager.base)
def formatEdge = client.infoString + "\n" + manager.infoString
}
case class TLAsyncManagerPortParameters(async: AsyncQueueParams, base: TLSlavePortParameters) {def infoString = base.infoString}
case class TLAsyncClientPortParameters(base: TLMasterPortParameters) {def infoString = base.infoString}
case class TLAsyncBundleParameters(async: AsyncQueueParams, base: TLBundleParameters)
case class TLAsyncEdgeParameters(client: TLAsyncClientPortParameters, manager: TLAsyncManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge
{
val bundle = TLAsyncBundleParameters(manager.async, TLBundleParameters(client.base, manager.base))
def formatEdge = client.infoString + "\n" + manager.infoString
}
case class TLRationalManagerPortParameters(direction: RationalDirection, base: TLSlavePortParameters) {def infoString = base.infoString}
case class TLRationalClientPortParameters(base: TLMasterPortParameters) {def infoString = base.infoString}
case class TLRationalEdgeParameters(client: TLRationalClientPortParameters, manager: TLRationalManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge
{
val bundle = TLBundleParameters(client.base, manager.base)
def formatEdge = client.infoString + "\n" + manager.infoString
}
// To be unified, devices must agree on all of these terms
case class ManagerUnificationKey(
resources: Seq[Resource],
regionType: RegionType.T,
executable: Boolean,
supportsAcquireT: TransferSizes,
supportsAcquireB: TransferSizes,
supportsArithmetic: TransferSizes,
supportsLogical: TransferSizes,
supportsGet: TransferSizes,
supportsPutFull: TransferSizes,
supportsPutPartial: TransferSizes,
supportsHint: TransferSizes)
object ManagerUnificationKey
{
def apply(x: TLSlaveParameters): ManagerUnificationKey = ManagerUnificationKey(
resources = x.resources,
regionType = x.regionType,
executable = x.executable,
supportsAcquireT = x.supportsAcquireT,
supportsAcquireB = x.supportsAcquireB,
supportsArithmetic = x.supportsArithmetic,
supportsLogical = x.supportsLogical,
supportsGet = x.supportsGet,
supportsPutFull = x.supportsPutFull,
supportsPutPartial = x.supportsPutPartial,
supportsHint = x.supportsHint)
}
object ManagerUnification
{
def apply(slaves: Seq[TLSlaveParameters]): List[TLSlaveParameters] = {
slaves.groupBy(ManagerUnificationKey.apply).values.map { seq =>
val agree = seq.forall(_.fifoId == seq.head.fifoId)
seq(0).v1copy(
address = AddressSet.unify(seq.flatMap(_.address)),
fifoId = if (agree) seq(0).fifoId else None)
}.toList
}
}
case class TLBufferParams(
a: BufferParams = BufferParams.none,
b: BufferParams = BufferParams.none,
c: BufferParams = BufferParams.none,
d: BufferParams = BufferParams.none,
e: BufferParams = BufferParams.none
) extends DirectedBuffers[TLBufferParams] {
def copyIn(x: BufferParams) = this.copy(b = x, d = x)
def copyOut(x: BufferParams) = this.copy(a = x, c = x, e = x)
def copyInOut(x: BufferParams) = this.copyIn(x).copyOut(x)
}
/** Pretty printing of TL source id maps */
class TLSourceIdMap(tl: TLMasterPortParameters) extends IdMap[TLSourceIdMapEntry] {
private val tlDigits = String.valueOf(tl.endSourceId-1).length()
protected val fmt = s"\t[%${tlDigits}d, %${tlDigits}d) %s%s%s"
private val sorted = tl.masters.sortBy(_.sourceId)
val mapping: Seq[TLSourceIdMapEntry] = sorted.map { case c =>
TLSourceIdMapEntry(c.sourceId, c.name, c.supports.probe, c.requestFifo)
}
}
case class TLSourceIdMapEntry(tlId: IdRange, name: String, isCache: Boolean, requestFifo: Boolean)
extends IdMapEntry
{
val from = tlId
val to = tlId
val maxTransactionsInFlight = Some(tlId.size)
}
File Edges.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.util._
class TLEdge(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdgeParameters(client, manager, params, sourceInfo)
{
def isAligned(address: UInt, lgSize: UInt): Bool = {
if (maxLgSize == 0) true.B else {
val mask = UIntToOH1(lgSize, maxLgSize)
(address & mask) === 0.U
}
}
def mask(address: UInt, lgSize: UInt): UInt =
MaskGen(address, lgSize, manager.beatBytes)
def staticHasData(bundle: TLChannel): Option[Boolean] = {
bundle match {
case _:TLBundleA => {
// Do there exist A messages with Data?
val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial
// Do there exist A messages without Data?
val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint
// Statically optimize the case where hasData is a constant
if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None
}
case _:TLBundleB => {
// Do there exist B messages with Data?
val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial
// Do there exist B messages without Data?
val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint
// Statically optimize the case where hasData is a constant
if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None
}
case _:TLBundleC => {
// Do there eixst C messages with Data?
val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe
// Do there exist C messages without Data?
val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe
if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None
}
case _:TLBundleD => {
// Do there eixst D messages with Data?
val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB
// Do there exist D messages without Data?
val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT
if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None
}
case _:TLBundleE => Some(false)
}
}
def isRequest(x: TLChannel): Bool = {
x match {
case a: TLBundleA => true.B
case b: TLBundleB => true.B
case c: TLBundleC => c.opcode(2) && c.opcode(1)
// opcode === TLMessages.Release ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(2) && !d.opcode(1)
// opcode === TLMessages.Grant ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
}
def isResponse(x: TLChannel): Bool = {
x match {
case a: TLBundleA => false.B
case b: TLBundleB => false.B
case c: TLBundleC => !c.opcode(2) || !c.opcode(1)
// opcode =/= TLMessages.Release &&
// opcode =/= TLMessages.ReleaseData
case d: TLBundleD => true.B // Grant isResponse + isRequest
case e: TLBundleE => true.B
}
}
def hasData(x: TLChannel): Bool = {
val opdata = x match {
case a: TLBundleA => !a.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case b: TLBundleB => !b.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case c: TLBundleC => c.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.ProbeAckData ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
staticHasData(x).map(_.B).getOrElse(opdata)
}
def opcode(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.opcode
case b: TLBundleB => b.opcode
case c: TLBundleC => c.opcode
case d: TLBundleD => d.opcode
}
}
def param(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.param
case b: TLBundleB => b.param
case c: TLBundleC => c.param
case d: TLBundleD => d.param
}
}
def size(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.size
case b: TLBundleB => b.size
case c: TLBundleC => c.size
case d: TLBundleD => d.size
}
}
def data(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.data
case b: TLBundleB => b.data
case c: TLBundleC => c.data
case d: TLBundleD => d.data
}
}
def corrupt(x: TLDataChannel): Bool = {
x match {
case a: TLBundleA => a.corrupt
case b: TLBundleB => b.corrupt
case c: TLBundleC => c.corrupt
case d: TLBundleD => d.corrupt
}
}
def mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.mask
case b: TLBundleB => b.mask
case c: TLBundleC => mask(c.address, c.size)
}
}
def full_mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => mask(a.address, a.size)
case b: TLBundleB => mask(b.address, b.size)
case c: TLBundleC => mask(c.address, c.size)
}
}
def address(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.address
case b: TLBundleB => b.address
case c: TLBundleC => c.address
}
}
def source(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.source
case b: TLBundleB => b.source
case c: TLBundleC => c.source
case d: TLBundleD => d.source
}
}
def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes)
def addr_lo(x: UInt): UInt =
if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0)
def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x))
def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x))
def numBeats(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 1.U
case bundle: TLDataChannel => {
val hasData = this.hasData(bundle)
val size = this.size(bundle)
val cutoff = log2Ceil(manager.beatBytes)
val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U
val decode = UIntToOH(size, maxLgSize+1) >> cutoff
Mux(hasData, decode | small.asUInt, 1.U)
}
}
}
def numBeats1(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 0.U
case bundle: TLDataChannel => {
if (maxLgSize == 0) {
0.U
} else {
val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes)
Mux(hasData(bundle), decode, 0.U)
}
}
}
}
def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val beats1 = numBeats1(bits)
val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W))
val counter1 = counter - 1.U
val first = counter === 0.U
val last = counter === 1.U || beats1 === 0.U
val done = last && fire
val count = (beats1 & ~counter1)
when (fire) {
counter := Mux(first, beats1, counter1)
}
(first, last, done, count)
}
def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1
def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire)
def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid)
def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2
def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire)
def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid)
def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3
def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire)
def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid)
def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3)
}
def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire)
def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid)
def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4)
}
def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire)
def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid)
def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes))
}
def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire)
def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid)
// Does the request need T permissions to be executed?
def needT(a: TLBundleA): Bool = {
val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLPermissions.NtoB -> false.B,
TLPermissions.NtoT -> true.B,
TLPermissions.BtoT -> true.B))
MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array(
TLMessages.PutFullData -> true.B,
TLMessages.PutPartialData -> true.B,
TLMessages.ArithmeticData -> true.B,
TLMessages.LogicalData -> true.B,
TLMessages.Get -> false.B,
TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLHints.PREFETCH_READ -> false.B,
TLHints.PREFETCH_WRITE -> true.B)),
TLMessages.AcquireBlock -> acq_needT,
TLMessages.AcquirePerm -> acq_needT))
}
// This is a very expensive circuit; use only if you really mean it!
def inFlight(x: TLBundle): (UInt, UInt) = {
val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W))
val bce = manager.anySupportAcquireB && client.anySupportProbe
val (a_first, a_last, _) = firstlast(x.a)
val (b_first, b_last, _) = firstlast(x.b)
val (c_first, c_last, _) = firstlast(x.c)
val (d_first, d_last, _) = firstlast(x.d)
val (e_first, e_last, _) = firstlast(x.e)
val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits))
val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits))
val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits))
val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits))
val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits))
val a_inc = x.a.fire && a_first && a_request
val b_inc = x.b.fire && b_first && b_request
val c_inc = x.c.fire && c_first && c_request
val d_inc = x.d.fire && d_first && d_request
val e_inc = x.e.fire && e_first && e_request
val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil))
val a_dec = x.a.fire && a_last && a_response
val b_dec = x.b.fire && b_last && b_response
val c_dec = x.c.fire && c_last && c_response
val d_dec = x.d.fire && d_last && d_response
val e_dec = x.e.fire && e_last && e_response
val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil))
val next_flight = flight + PopCount(inc) - PopCount(dec)
flight := next_flight
(flight, next_flight)
}
def prettySourceMapping(context: String): String = {
s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n"
}
}
class TLEdgeOut(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
// Transfers
def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquireBlock
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquirePerm
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.Release
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ReleaseData
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) =
Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B)
def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAck
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions, data)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAckData
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B)
def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink)
def GrantAck(toSink: UInt): TLBundleE = {
val e = Wire(new TLBundleE(bundle))
e.sink := toSink
e
}
// Accesses
def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsGetFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Get
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutFullFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutFullData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, mask, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutPartialFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutPartialData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = {
require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsArithmeticFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.ArithmeticData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsLogicalFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.LogicalData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = {
require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsHintFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Hint
a.param := param
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data)
def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAckData
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size)
def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.HintAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
}
class TLEdgeIn(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = {
val todo = x.filter(!_.isEmpty)
val heads = todo.map(_.head)
val tails = todo.map(_.tail)
if (todo.isEmpty) Nil else { heads +: myTranspose(tails) }
}
// Transfers
def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = {
require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}")
val legal = client.supportsProbe(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Probe
b.param := capPermissions
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.Grant
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.GrantData
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B)
def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.ReleaseAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
// Accesses
def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = {
require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsGet(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Get
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsPutFull(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutFullData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, mask, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsPutPartial(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutPartialData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsArithmetic(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.ArithmeticData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsLogical(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.LogicalData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = {
require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsHint(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Hint
b.param := param
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size)
def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied)
def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data)
def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAckData
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B)
def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied)
def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B)
def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.HintAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
}
| module TLMonitor_91( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [127:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [31:0] io_in_a_bits_data, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14]
input [1:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input io_in_d_bits_denied, // @[Monitor.scala:20:14]
input io_in_d_bits_corrupt // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7]
wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7]
wire [127:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7]
wire [31:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7]
wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7]
wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7]
wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7]
wire [1:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7]
wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7]
wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7]
wire io_in_a_bits_source = 1'h0; // @[Monitor.scala:36:7]
wire io_in_a_bits_corrupt = 1'h0; // @[Monitor.scala:36:7]
wire io_in_d_bits_source = 1'h0; // @[Monitor.scala:36:7]
wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7]
wire mask_sizeOH_shiftAmount = 1'h0; // @[OneHot.scala:64:49]
wire mask_sub_size = 1'h0; // @[Misc.scala:209:26]
wire _mask_sub_acc_T = 1'h0; // @[Misc.scala:215:38]
wire _mask_sub_acc_T_1 = 1'h0; // @[Misc.scala:215:38]
wire a_first_beats1_decode = 1'h0; // @[Edges.scala:220:59]
wire a_first_beats1 = 1'h0; // @[Edges.scala:221:14]
wire a_first_count = 1'h0; // @[Edges.scala:234:25]
wire d_first_beats1_decode = 1'h0; // @[Edges.scala:220:59]
wire d_first_beats1 = 1'h0; // @[Edges.scala:221:14]
wire d_first_count = 1'h0; // @[Edges.scala:234:25]
wire a_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59]
wire a_first_beats1_1 = 1'h0; // @[Edges.scala:221:14]
wire a_first_count_1 = 1'h0; // @[Edges.scala:234:25]
wire d_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59]
wire d_first_beats1_1 = 1'h0; // @[Edges.scala:221:14]
wire d_first_count_1 = 1'h0; // @[Edges.scala:234:25]
wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35]
wire c_first_beats1_decode = 1'h0; // @[Edges.scala:220:59]
wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36]
wire c_first_beats1 = 1'h0; // @[Edges.scala:221:14]
wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25]
wire c_first_done = 1'h0; // @[Edges.scala:233:22]
wire _c_first_count_T = 1'h0; // @[Edges.scala:234:27]
wire c_first_count = 1'h0; // @[Edges.scala:234:25]
wire _c_first_counter_T = 1'h0; // @[Edges.scala:236:21]
wire d_first_beats1_decode_2 = 1'h0; // @[Edges.scala:220:59]
wire d_first_beats1_2 = 1'h0; // @[Edges.scala:221:14]
wire d_first_count_2 = 1'h0; // @[Edges.scala:234:25]
wire c_set = 1'h0; // @[Monitor.scala:738:34]
wire c_set_wo_ready = 1'h0; // @[Monitor.scala:739:34]
wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47]
wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95]
wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71]
wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44]
wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36]
wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51]
wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40]
wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55]
wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88]
wire _source_ok_T = 1'h1; // @[Parameters.scala:46:9]
wire _source_ok_WIRE_0 = 1'h1; // @[Parameters.scala:1138:31]
wire mask_sub_sub_0_1 = 1'h1; // @[Misc.scala:206:21]
wire mask_sub_0_1 = 1'h1; // @[Misc.scala:215:29]
wire mask_sub_1_1 = 1'h1; // @[Misc.scala:215:29]
wire mask_size = 1'h1; // @[Misc.scala:209:26]
wire mask_acc = 1'h1; // @[Misc.scala:215:29]
wire mask_acc_1 = 1'h1; // @[Misc.scala:215:29]
wire mask_acc_2 = 1'h1; // @[Misc.scala:215:29]
wire mask_acc_3 = 1'h1; // @[Misc.scala:215:29]
wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:46:9]
wire _source_ok_WIRE_1_0 = 1'h1; // @[Parameters.scala:1138:31]
wire sink_ok = 1'h1; // @[Monitor.scala:309:31]
wire _a_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire a_first_last = 1'h1; // @[Edges.scala:232:33]
wire _d_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire d_first_last = 1'h1; // @[Edges.scala:232:33]
wire _a_first_last_T_3 = 1'h1; // @[Edges.scala:232:43]
wire a_first_last_1 = 1'h1; // @[Edges.scala:232:33]
wire _d_first_last_T_3 = 1'h1; // @[Edges.scala:232:43]
wire d_first_last_1 = 1'h1; // @[Edges.scala:232:33]
wire _same_cycle_resp_T_2 = 1'h1; // @[Monitor.scala:684:113]
wire c_first_counter1 = 1'h1; // @[Edges.scala:230:28]
wire c_first = 1'h1; // @[Edges.scala:231:25]
wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire c_first_last = 1'h1; // @[Edges.scala:232:33]
wire _d_first_last_T_5 = 1'h1; // @[Edges.scala:232:43]
wire d_first_last_2 = 1'h1; // @[Edges.scala:232:33]
wire _same_cycle_resp_T_8 = 1'h1; // @[Monitor.scala:795:113]
wire [1:0] is_aligned_mask = 2'h3; // @[package.scala:243:46]
wire [1:0] mask_lo = 2'h3; // @[Misc.scala:222:10]
wire [1:0] mask_hi = 2'h3; // @[Misc.scala:222:10]
wire [1:0] _a_first_beats1_decode_T_2 = 2'h3; // @[package.scala:243:46]
wire [1:0] _a_first_beats1_decode_T_5 = 2'h3; // @[package.scala:243:46]
wire [1:0] _c_first_beats1_decode_T_1 = 2'h3; // @[package.scala:243:76]
wire [1:0] _c_first_counter1_T = 2'h3; // @[Edges.scala:230:28]
wire [1:0] io_in_a_bits_size = 2'h2; // @[Monitor.scala:36:7]
wire [1:0] _mask_sizeOH_T = 2'h2; // @[Misc.scala:202:34]
wire [2:0] io_in_a_bits_param = 3'h0; // @[Monitor.scala:36:7]
wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] c_sizes_set_interm = 3'h0; // @[Monitor.scala:755:40]
wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_T = 3'h0; // @[Monitor.scala:766:51]
wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [3:0] io_in_a_bits_mask = 4'hF; // @[Monitor.scala:36:7]
wire [3:0] mask = 4'hF; // @[Misc.scala:222:10]
wire [31:0] io_in_d_bits_data = 32'h0; // @[Monitor.scala:36:7]
wire [31:0] _c_first_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_first_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_first_WIRE_2_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_first_WIRE_3_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_set_wo_ready_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_set_wo_ready_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_set_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_set_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_opcodes_set_interm_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_opcodes_set_interm_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_sizes_set_interm_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_sizes_set_interm_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_opcodes_set_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_opcodes_set_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_sizes_set_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_sizes_set_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_probe_ack_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_probe_ack_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_probe_ack_WIRE_2_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_probe_ack_WIRE_3_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _same_cycle_resp_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _same_cycle_resp_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _same_cycle_resp_WIRE_2_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _same_cycle_resp_WIRE_3_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _same_cycle_resp_WIRE_4_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _same_cycle_resp_WIRE_5_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [127:0] _c_first_WIRE_bits_address = 128'h0; // @[Bundles.scala:265:74]
wire [127:0] _c_first_WIRE_1_bits_address = 128'h0; // @[Bundles.scala:265:61]
wire [127:0] _c_first_WIRE_2_bits_address = 128'h0; // @[Bundles.scala:265:74]
wire [127:0] _c_first_WIRE_3_bits_address = 128'h0; // @[Bundles.scala:265:61]
wire [127:0] _c_set_wo_ready_WIRE_bits_address = 128'h0; // @[Bundles.scala:265:74]
wire [127:0] _c_set_wo_ready_WIRE_1_bits_address = 128'h0; // @[Bundles.scala:265:61]
wire [127:0] _c_set_WIRE_bits_address = 128'h0; // @[Bundles.scala:265:74]
wire [127:0] _c_set_WIRE_1_bits_address = 128'h0; // @[Bundles.scala:265:61]
wire [127:0] _c_opcodes_set_interm_WIRE_bits_address = 128'h0; // @[Bundles.scala:265:74]
wire [127:0] _c_opcodes_set_interm_WIRE_1_bits_address = 128'h0; // @[Bundles.scala:265:61]
wire [127:0] _c_sizes_set_interm_WIRE_bits_address = 128'h0; // @[Bundles.scala:265:74]
wire [127:0] _c_sizes_set_interm_WIRE_1_bits_address = 128'h0; // @[Bundles.scala:265:61]
wire [127:0] _c_opcodes_set_WIRE_bits_address = 128'h0; // @[Bundles.scala:265:74]
wire [127:0] _c_opcodes_set_WIRE_1_bits_address = 128'h0; // @[Bundles.scala:265:61]
wire [127:0] _c_sizes_set_WIRE_bits_address = 128'h0; // @[Bundles.scala:265:74]
wire [127:0] _c_sizes_set_WIRE_1_bits_address = 128'h0; // @[Bundles.scala:265:61]
wire [127:0] _c_probe_ack_WIRE_bits_address = 128'h0; // @[Bundles.scala:265:74]
wire [127:0] _c_probe_ack_WIRE_1_bits_address = 128'h0; // @[Bundles.scala:265:61]
wire [127:0] _c_probe_ack_WIRE_2_bits_address = 128'h0; // @[Bundles.scala:265:74]
wire [127:0] _c_probe_ack_WIRE_3_bits_address = 128'h0; // @[Bundles.scala:265:61]
wire [127:0] _same_cycle_resp_WIRE_bits_address = 128'h0; // @[Bundles.scala:265:74]
wire [127:0] _same_cycle_resp_WIRE_1_bits_address = 128'h0; // @[Bundles.scala:265:61]
wire [127:0] _same_cycle_resp_WIRE_2_bits_address = 128'h0; // @[Bundles.scala:265:74]
wire [127:0] _same_cycle_resp_WIRE_3_bits_address = 128'h0; // @[Bundles.scala:265:61]
wire [127:0] _same_cycle_resp_WIRE_4_bits_address = 128'h0; // @[Bundles.scala:265:74]
wire [127:0] _same_cycle_resp_WIRE_5_bits_address = 128'h0; // @[Bundles.scala:265:61]
wire [1:0] _is_aligned_mask_T_1 = 2'h0; // @[package.scala:243:76]
wire [1:0] _a_first_beats1_decode_T_1 = 2'h0; // @[package.scala:243:76]
wire [1:0] _a_first_beats1_decode_T_4 = 2'h0; // @[package.scala:243:76]
wire [1:0] _c_first_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_first_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_first_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_first_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_first_beats1_decode_T_2 = 2'h0; // @[package.scala:243:46]
wire [1:0] _c_set_wo_ready_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_set_wo_ready_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_opcodes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_opcodes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_sizes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_sizes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_opcodes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_opcodes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_sizes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_sizes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_probe_ack_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_probe_ack_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_probe_ack_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_probe_ack_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _same_cycle_resp_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _same_cycle_resp_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _same_cycle_resp_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _same_cycle_resp_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _same_cycle_resp_WIRE_4_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _same_cycle_resp_WIRE_5_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [30:0] _d_opcodes_clr_T_5 = 31'hF; // @[Monitor.scala:680:76]
wire [30:0] _d_sizes_clr_T_5 = 31'hF; // @[Monitor.scala:681:74]
wire [30:0] _d_opcodes_clr_T_11 = 31'hF; // @[Monitor.scala:790:76]
wire [30:0] _d_sizes_clr_T_11 = 31'hF; // @[Monitor.scala:791:74]
wire [3:0] _a_opcode_lookup_T = 4'h0; // @[Monitor.scala:637:69]
wire [3:0] _a_size_lookup_T = 4'h0; // @[Monitor.scala:641:65]
wire [3:0] _a_opcodes_set_T = 4'h0; // @[Monitor.scala:659:79]
wire [3:0] _a_sizes_set_T = 4'h0; // @[Monitor.scala:660:77]
wire [3:0] _d_opcodes_clr_T_4 = 4'h0; // @[Monitor.scala:680:101]
wire [3:0] _d_sizes_clr_T_4 = 4'h0; // @[Monitor.scala:681:99]
wire [3:0] c_opcodes_set = 4'h0; // @[Monitor.scala:740:34]
wire [3:0] c_sizes_set = 4'h0; // @[Monitor.scala:741:34]
wire [3:0] _c_opcode_lookup_T = 4'h0; // @[Monitor.scala:749:69]
wire [3:0] _c_size_lookup_T = 4'h0; // @[Monitor.scala:750:67]
wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40]
wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53]
wire [3:0] _c_opcodes_set_T = 4'h0; // @[Monitor.scala:767:79]
wire [3:0] _c_sizes_set_T = 4'h0; // @[Monitor.scala:768:77]
wire [3:0] _d_opcodes_clr_T_10 = 4'h0; // @[Monitor.scala:790:101]
wire [3:0] _d_sizes_clr_T_10 = 4'h0; // @[Monitor.scala:791:99]
wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [1:0] _mask_sizeOH_T_1 = 2'h1; // @[OneHot.scala:65:12]
wire [1:0] _mask_sizeOH_T_2 = 2'h1; // @[OneHot.scala:65:27]
wire [1:0] mask_sizeOH = 2'h1; // @[Misc.scala:202:81]
wire [1:0] _a_set_wo_ready_T = 2'h1; // @[OneHot.scala:58:35]
wire [1:0] _a_set_T = 2'h1; // @[OneHot.scala:58:35]
wire [1:0] _d_clr_wo_ready_T = 2'h1; // @[OneHot.scala:58:35]
wire [1:0] _d_clr_T = 2'h1; // @[OneHot.scala:58:35]
wire [1:0] _c_set_wo_ready_T = 2'h1; // @[OneHot.scala:58:35]
wire [1:0] _c_set_T = 2'h1; // @[OneHot.scala:58:35]
wire [1:0] _d_clr_wo_ready_T_1 = 2'h1; // @[OneHot.scala:58:35]
wire [1:0] _d_clr_T_1 = 2'h1; // @[OneHot.scala:58:35]
wire [17:0] _c_sizes_set_T_1 = 18'h0; // @[Monitor.scala:768:52]
wire [18:0] _c_opcodes_set_T_1 = 19'h0; // @[Monitor.scala:767:54]
wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] _c_sizes_set_interm_T_1 = 3'h1; // @[Monitor.scala:766:59]
wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61]
wire [4:0] _c_first_beats1_decode_T = 5'h3; // @[package.scala:243:71]
wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42]
wire [2:0] _a_sizes_set_interm_T_1 = 3'h5; // @[Monitor.scala:658:59]
wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42]
wire [2:0] _a_sizes_set_interm_T = 3'h4; // @[Monitor.scala:658:51]
wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42]
wire [4:0] _is_aligned_mask_T = 5'hC; // @[package.scala:243:71]
wire [4:0] _a_first_beats1_decode_T = 5'hC; // @[package.scala:243:71]
wire [4:0] _a_first_beats1_decode_T_3 = 5'hC; // @[package.scala:243:71]
wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123]
wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117]
wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48]
wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48]
wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123]
wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119]
wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48]
wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48]
wire [127:0] _is_aligned_T = {126'h0, io_in_a_bits_address_0[1:0]}; // @[Monitor.scala:36:7]
wire is_aligned = _is_aligned_T == 128'h0; // @[Edges.scala:21:{16,24}]
wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26]
wire mask_sub_1_2 = mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_0_2 = mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26]
wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20]
wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T = mask_eq; // @[Misc.scala:214:27, :215:38]
wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_1 = mask_eq_1; // @[Misc.scala:214:27, :215:38]
wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_2 = mask_eq_2; // @[Misc.scala:214:27, :215:38]
wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_3 = mask_eq_3; // @[Misc.scala:214:27, :215:38]
wire _T_607 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35]
wire _a_first_T; // @[Decoupled.scala:51:35]
assign _a_first_T = _T_607; // @[Decoupled.scala:51:35]
wire _a_first_T_1; // @[Decoupled.scala:51:35]
assign _a_first_T_1 = _T_607; // @[Decoupled.scala:51:35]
wire a_first_done = _a_first_T; // @[Decoupled.scala:51:35]
wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}]
reg a_first_counter; // @[Edges.scala:229:27]
wire _a_first_last_T = a_first_counter; // @[Edges.scala:229:27, :232:25]
wire [1:0] _a_first_counter1_T = {1'h0, a_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28]
wire a_first_counter1 = _a_first_counter1_T[0]; // @[Edges.scala:230:28]
wire a_first = ~a_first_counter; // @[Edges.scala:229:27, :231:25]
wire _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27]
wire _a_first_counter_T = ~a_first & a_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [127:0] address; // @[Monitor.scala:391:22]
wire _T_675 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35]
wire _d_first_T; // @[Decoupled.scala:51:35]
assign _d_first_T = _T_675; // @[Decoupled.scala:51:35]
wire _d_first_T_1; // @[Decoupled.scala:51:35]
assign _d_first_T_1 = _T_675; // @[Decoupled.scala:51:35]
wire _d_first_T_2; // @[Decoupled.scala:51:35]
assign _d_first_T_2 = _T_675; // @[Decoupled.scala:51:35]
wire d_first_done = _d_first_T; // @[Decoupled.scala:51:35]
wire [4:0] _GEN = 5'h3 << io_in_d_bits_size_0; // @[package.scala:243:71]
wire [4:0] _d_first_beats1_decode_T; // @[package.scala:243:71]
assign _d_first_beats1_decode_T = _GEN; // @[package.scala:243:71]
wire [4:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71]
wire [4:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_6 = _GEN; // @[package.scala:243:71]
wire [1:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[1:0]; // @[package.scala:243:{71,76}]
wire [1:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
reg d_first_counter; // @[Edges.scala:229:27]
wire _d_first_last_T = d_first_counter; // @[Edges.scala:229:27, :232:25]
wire [1:0] _d_first_counter1_T = {1'h0, d_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28]
wire d_first_counter1 = _d_first_counter1_T[0]; // @[Edges.scala:230:28]
wire d_first = ~d_first_counter; // @[Edges.scala:229:27, :231:25]
wire _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27]
wire _d_first_counter_T = ~d_first & d_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [1:0] param_1; // @[Monitor.scala:539:22]
reg [1:0] size_1; // @[Monitor.scala:540:22]
reg denied; // @[Monitor.scala:543:22]
reg [1:0] inflight; // @[Monitor.scala:614:27]
reg [3:0] inflight_opcodes; // @[Monitor.scala:616:35]
wire [3:0] _a_opcode_lookup_T_1 = inflight_opcodes; // @[Monitor.scala:616:35, :637:44]
reg [3:0] inflight_sizes; // @[Monitor.scala:618:33]
wire [3:0] _a_size_lookup_T_1 = inflight_sizes; // @[Monitor.scala:618:33, :641:40]
wire a_first_done_1 = _a_first_T_1; // @[Decoupled.scala:51:35]
wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}]
reg a_first_counter_1; // @[Edges.scala:229:27]
wire _a_first_last_T_2 = a_first_counter_1; // @[Edges.scala:229:27, :232:25]
wire [1:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28]
wire a_first_counter1_1 = _a_first_counter1_T_1[0]; // @[Edges.scala:230:28]
wire a_first_1 = ~a_first_counter_1; // @[Edges.scala:229:27, :231:25]
wire _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire _a_first_counter_T_1 = ~a_first_1 & a_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21]
wire d_first_done_1 = _d_first_T_1; // @[Decoupled.scala:51:35]
wire [1:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[1:0]; // @[package.scala:243:{71,76}]
wire [1:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
reg d_first_counter_1; // @[Edges.scala:229:27]
wire _d_first_last_T_2 = d_first_counter_1; // @[Edges.scala:229:27, :232:25]
wire [1:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28]
wire d_first_counter1_1 = _d_first_counter1_T_1[0]; // @[Edges.scala:230:28]
wire d_first_1 = ~d_first_counter_1; // @[Edges.scala:229:27, :231:25]
wire _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire _d_first_counter_T_1 = ~d_first_1 & d_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21]
wire a_set; // @[Monitor.scala:626:34]
wire a_set_wo_ready; // @[Monitor.scala:627:34]
wire [3:0] a_opcodes_set; // @[Monitor.scala:630:33]
wire [3:0] a_sizes_set; // @[Monitor.scala:632:31]
wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35]
wire [15:0] _a_opcode_lookup_T_6 = {12'h0, _a_opcode_lookup_T_1}; // @[Monitor.scala:637:{44,97}]
wire [15:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:637:{97,152}]
assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}]
wire [3:0] a_size_lookup; // @[Monitor.scala:639:33]
wire [15:0] _a_size_lookup_T_6 = {12'h0, _a_size_lookup_T_1}; // @[Monitor.scala:637:97, :641:{40,91}]
wire [15:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[15:1]}; // @[Monitor.scala:641:{91,144}]
assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}]
wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40]
wire [2:0] a_sizes_set_interm; // @[Monitor.scala:648:38]
wire _T_537 = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26]
assign a_set_wo_ready = _T_537; // @[Monitor.scala:627:34, :651:26]
wire _same_cycle_resp_T; // @[Monitor.scala:684:44]
assign _same_cycle_resp_T = _T_537; // @[Monitor.scala:651:26, :684:44]
assign a_set = _T_607 & a_first_1; // @[Decoupled.scala:51:35]
wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53]
wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}]
assign a_opcodes_set_interm = a_set ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:626:34, :646:40, :655:70, :657:{28,61}]
assign a_sizes_set_interm = a_set ? 3'h5 : 3'h0; // @[Monitor.scala:626:34, :648:38, :655:70, :658:28]
wire [18:0] _a_opcodes_set_T_1 = {15'h0, a_opcodes_set_interm}; // @[Monitor.scala:646:40, :659:54]
assign a_opcodes_set = a_set ? _a_opcodes_set_T_1[3:0] : 4'h0; // @[Monitor.scala:626:34, :630:33, :655:70, :659:{28,54}]
wire [17:0] _a_sizes_set_T_1 = {15'h0, a_sizes_set_interm}; // @[Monitor.scala:648:38, :659:54, :660:52]
assign a_sizes_set = a_set ? _a_sizes_set_T_1[3:0] : 4'h0; // @[Monitor.scala:626:34, :632:31, :655:70, :660:{28,52}]
wire d_clr; // @[Monitor.scala:664:34]
wire d_clr_wo_ready; // @[Monitor.scala:665:34]
wire [3:0] d_opcodes_clr; // @[Monitor.scala:668:33]
wire [3:0] d_sizes_clr; // @[Monitor.scala:670:31]
wire _GEN_0 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46]
wire d_release_ack; // @[Monitor.scala:673:46]
assign d_release_ack = _GEN_0; // @[Monitor.scala:673:46]
wire d_release_ack_1; // @[Monitor.scala:783:46]
assign d_release_ack_1 = _GEN_0; // @[Monitor.scala:673:46, :783:46]
wire _T_586 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26]
assign d_clr_wo_ready = _T_586 & ~d_release_ack; // @[Monitor.scala:665:34, :673:46, :674:{26,71,74}]
assign d_clr = _T_675 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35]
wire [3:0] _GEN_1 = {4{d_clr}}; // @[Monitor.scala:664:34, :668:33, :678:89, :680:21]
assign d_opcodes_clr = _GEN_1; // @[Monitor.scala:668:33, :678:89, :680:21]
assign d_sizes_clr = _GEN_1; // @[Monitor.scala:668:33, :670:31, :678:89, :680:21]
wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}]
wire same_cycle_resp = _same_cycle_resp_T_1; // @[Monitor.scala:684:{55,88}]
wire [1:0] _inflight_T = {inflight[1], inflight[0] | a_set}; // @[Monitor.scala:614:27, :626:34, :705:27]
wire _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38]
wire [1:0] _inflight_T_2 = {1'h0, _inflight_T[0] & _inflight_T_1}; // @[Monitor.scala:705:{27,36,38}]
wire [3:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43]
wire [3:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62]
wire [3:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}]
wire [3:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39]
wire [3:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56]
wire [3:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26]
wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26]
reg [1:0] inflight_1; // @[Monitor.scala:726:35]
wire [1:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35]
reg [3:0] inflight_opcodes_1; // @[Monitor.scala:727:35]
wire [3:0] _c_opcode_lookup_T_1 = inflight_opcodes_1; // @[Monitor.scala:727:35, :749:44]
wire [3:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43]
reg [3:0] inflight_sizes_1; // @[Monitor.scala:728:35]
wire [3:0] _c_size_lookup_T_1 = inflight_sizes_1; // @[Monitor.scala:728:35, :750:42]
wire [3:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41]
wire d_first_done_2 = _d_first_T_2; // @[Decoupled.scala:51:35]
wire [1:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[1:0]; // @[package.scala:243:{71,76}]
wire [1:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}]
reg d_first_counter_2; // @[Edges.scala:229:27]
wire _d_first_last_T_4 = d_first_counter_2; // @[Edges.scala:229:27, :232:25]
wire [1:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 2'h1; // @[Edges.scala:229:27, :230:28]
wire d_first_counter1_2 = _d_first_counter1_T_2[0]; // @[Edges.scala:230:28]
wire d_first_2 = ~d_first_counter_2; // @[Edges.scala:229:27, :231:25]
wire _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27]
wire _d_first_counter_T_2 = ~d_first_2 & d_first_counter1_2; // @[Edges.scala:230:28, :231:25, :236:21]
wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35]
wire [3:0] c_size_lookup; // @[Monitor.scala:748:35]
wire [15:0] _c_opcode_lookup_T_6 = {12'h0, _c_opcode_lookup_T_1}; // @[Monitor.scala:637:97, :749:{44,97}]
wire [15:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:749:{97,152}]
assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}]
wire [15:0] _c_size_lookup_T_6 = {12'h0, _c_size_lookup_T_1}; // @[Monitor.scala:637:97, :750:{42,93}]
wire [15:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[15:1]}; // @[Monitor.scala:750:{93,146}]
assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}]
wire d_clr_1; // @[Monitor.scala:774:34]
wire d_clr_wo_ready_1; // @[Monitor.scala:775:34]
wire [3:0] d_opcodes_clr_1; // @[Monitor.scala:776:34]
wire [3:0] d_sizes_clr_1; // @[Monitor.scala:777:34]
wire _T_651 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26]
assign d_clr_wo_ready_1 = _T_651 & d_release_ack_1; // @[Monitor.scala:775:34, :783:46, :784:{26,71}]
assign d_clr_1 = _T_675 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35]
wire [3:0] _GEN_2 = {4{d_clr_1}}; // @[Monitor.scala:774:34, :776:34, :788:88, :790:21]
assign d_opcodes_clr_1 = _GEN_2; // @[Monitor.scala:776:34, :788:88, :790:21]
assign d_sizes_clr_1 = _GEN_2; // @[Monitor.scala:776:34, :777:34, :788:88, :790:21]
wire _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46]
wire [1:0] _inflight_T_5 = {1'h0, _inflight_T_3[0] & _inflight_T_4}; // @[Monitor.scala:814:{35,44,46}]
wire [3:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62]
wire [3:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}]
wire [3:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58]
wire [3:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27] |
Generate the Verilog code corresponding to the following Chisel files.
File Monitor.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceLine
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import freechips.rocketchip.diplomacy.EnableMonitors
import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode}
import freechips.rocketchip.util.PlusArg
case class TLMonitorArgs(edge: TLEdge)
abstract class TLMonitorBase(args: TLMonitorArgs) extends Module
{
val io = IO(new Bundle {
val in = Input(new TLBundle(args.edge.bundle))
})
def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit
legalize(io.in, args.edge, reset)
}
object TLMonitor {
def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = {
if (enable) {
EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) }
} else { node }
}
}
class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args)
{
require (args.edge.params(TLMonitorStrictMode) || (! args.edge.params(TestplanTestType).formal))
val cover_prop_class = PropertyClass.Default
//Like assert but can flip to being an assumption for formal verification
def monAssert(cond: Bool, message: String): Unit =
if (monitorDir == MonitorDirection.Monitor) {
assert(cond, message)
} else {
Property(monitorDir, cond, message, PropertyClass.Default)
}
def assume(cond: Bool, message: String): Unit =
if (monitorDir == MonitorDirection.Monitor) {
assert(cond, message)
} else {
Property(monitorDir.flip, cond, message, PropertyClass.Default)
}
def extra = {
args.edge.sourceInfo match {
case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)"
case _ => ""
}
}
def visible(address: UInt, source: UInt, edge: TLEdge) =
edge.client.clients.map { c =>
!c.sourceId.contains(source) ||
c.visibility.map(_.contains(address)).reduce(_ || _)
}.reduce(_ && _)
def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = {
//switch this flag to turn on diplomacy in error messages
def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n"
monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra)
// Reuse these subexpressions to save some firrtl lines
val source_ok = edge.client.contains(bundle.source)
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val mask = edge.full_mask(bundle)
monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility")
//The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B
//TODO: check for acquireT?
when (bundle.opcode === TLMessages.AcquireBlock) {
monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra)
monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra)
monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra)
monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra)
}
when (bundle.opcode === TLMessages.AcquirePerm) {
monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra)
monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra)
monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra)
monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra)
monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra)
}
when (bundle.opcode === TLMessages.Get) {
monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra)
monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra)
monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra)
}
when (bundle.opcode === TLMessages.PutFullData) {
monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra)
monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.PutPartialData) {
monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra)
monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.ArithmeticData) {
monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra)
monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.LogicalData) {
monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra)
monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.Hint) {
monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra)
monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra)
}
}
def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = {
monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra)
monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility")
// Reuse these subexpressions to save some firrtl lines
val address_ok = edge.manager.containsSafe(edge.address(bundle))
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val mask = edge.full_mask(bundle)
val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source
when (bundle.opcode === TLMessages.Probe) {
assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra)
assume (address_ok, "'B' channel Probe carries unmanaged address" + extra)
assume (legal_source, "'B' channel Probe carries source that is not first source" + extra)
assume (is_aligned, "'B' channel Probe address not aligned to size" + extra)
assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra)
assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra)
assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra)
}
when (bundle.opcode === TLMessages.Get) {
monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra)
monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra)
}
when (bundle.opcode === TLMessages.PutFullData) {
monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra)
monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.PutPartialData) {
monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra)
monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.ArithmeticData) {
monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra)
monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra)
monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.LogicalData) {
monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra)
monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra)
monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.Hint) {
monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra)
monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra)
monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra)
}
}
def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = {
monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra)
val source_ok = edge.client.contains(bundle.source)
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val address_ok = edge.manager.containsSafe(edge.address(bundle))
monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility")
when (bundle.opcode === TLMessages.ProbeAck) {
monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra)
monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra)
}
when (bundle.opcode === TLMessages.ProbeAckData) {
monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra)
}
when (bundle.opcode === TLMessages.Release) {
monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra)
monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra)
monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra)
}
when (bundle.opcode === TLMessages.ReleaseData) {
monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra)
monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra)
}
when (bundle.opcode === TLMessages.AccessAck) {
monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra)
monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra)
}
when (bundle.opcode === TLMessages.AccessAckData) {
monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra)
}
when (bundle.opcode === TLMessages.HintAck) {
monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra)
monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra)
}
}
def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = {
assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra)
val source_ok = edge.client.contains(bundle.source)
val sink_ok = bundle.sink < edge.manager.endSinkId.U
val deny_put_ok = edge.manager.mayDenyPut.B
val deny_get_ok = edge.manager.mayDenyGet.B
when (bundle.opcode === TLMessages.ReleaseAck) {
assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra)
assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra)
assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra)
}
when (bundle.opcode === TLMessages.Grant) {
assume (source_ok, "'D' channel Grant carries invalid source ID" + extra)
assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra)
assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra)
assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra)
assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel Grant is denied" + extra)
}
when (bundle.opcode === TLMessages.GrantData) {
assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra)
assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra)
assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra)
assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra)
assume (!bundle.denied || bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra)
assume (deny_get_ok || !bundle.denied, "'D' channel GrantData is denied" + extra)
}
when (bundle.opcode === TLMessages.AccessAck) {
assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel AccessAck is denied" + extra)
}
when (bundle.opcode === TLMessages.AccessAckData) {
assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra)
assume (!bundle.denied || bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra)
assume (deny_get_ok || !bundle.denied, "'D' channel AccessAckData is denied" + extra)
}
when (bundle.opcode === TLMessages.HintAck) {
assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel HintAck is denied" + extra)
}
}
def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = {
val sink_ok = bundle.sink < edge.manager.endSinkId.U
monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra)
}
def legalizeFormat(bundle: TLBundle, edge: TLEdge) = {
when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) }
when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) }
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) }
when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) }
when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) }
} else {
monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra)
monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra)
monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra)
}
}
def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = {
val a_first = edge.first(a.bits, a.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (a.valid && !a_first) {
monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra)
monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra)
monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra)
monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra)
monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra)
}
when (a.fire && a_first) {
opcode := a.bits.opcode
param := a.bits.param
size := a.bits.size
source := a.bits.source
address := a.bits.address
}
}
def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = {
val b_first = edge.first(b.bits, b.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (b.valid && !b_first) {
monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra)
monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra)
monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra)
monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra)
monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra)
}
when (b.fire && b_first) {
opcode := b.bits.opcode
param := b.bits.param
size := b.bits.size
source := b.bits.source
address := b.bits.address
}
}
def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = {
// Symbolic variable
val sym_source = Wire(UInt(edge.client.endSourceId.W))
// TODO: Connect sym_source to a fixed value for simulation and to a
// free wire in formal
sym_source := 0.U
// Type casting Int to UInt
val maxSourceId = Wire(UInt(edge.client.endSourceId.W))
maxSourceId := edge.client.endSourceId.U
// Delayed verison of sym_source
val sym_source_d = Reg(UInt(edge.client.endSourceId.W))
sym_source_d := sym_source
// These will be constraints for FV setup
Property(
MonitorDirection.Monitor,
(sym_source === sym_source_d),
"sym_source should remain stable",
PropertyClass.Default)
Property(
MonitorDirection.Monitor,
(sym_source <= maxSourceId),
"sym_source should take legal value",
PropertyClass.Default)
val my_resp_pend = RegInit(false.B)
val my_opcode = Reg(UInt())
val my_size = Reg(UInt())
val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire)
val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire)
val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source)
val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source)
val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat)
val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend)
when (my_set_resp_pend) {
my_resp_pend := true.B
} .elsewhen (my_clr_resp_pend) {
my_resp_pend := false.B
}
when (my_a_first_beat) {
my_opcode := bundle.a.bits.opcode
my_size := bundle.a.bits.size
}
val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size)
val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode)
val my_resp_opcode_legal = Wire(Bool())
when ((my_resp_opcode === TLMessages.Get) || (my_resp_opcode === TLMessages.ArithmeticData) ||
(my_resp_opcode === TLMessages.LogicalData)) {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData)
} .elsewhen ((my_resp_opcode === TLMessages.PutFullData) || (my_resp_opcode === TLMessages.PutPartialData)) {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck)
} .otherwise {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck)
}
monAssert (IfThen(my_resp_pend, !my_a_first_beat),
"Request message should not be sent with a source ID, for which a response message" +
"is already pending (not received until current cycle) for a prior request message" +
"with the same source ID" + extra)
assume (IfThen(my_clr_resp_pend, (my_set_resp_pend || my_resp_pend)),
"Response message should be accepted with a source ID only if a request message with the" +
"same source ID has been accepted or is being accepted in the current cycle" + extra)
assume (IfThen(my_d_first_beat, (my_a_first_beat || my_resp_pend)),
"Response message should be sent with a source ID only if a request message with the" +
"same source ID has been accepted or is being sent in the current cycle" + extra)
assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)),
"If d_valid is 1, then d_size should be same as a_size of the corresponding request" +
"message" + extra)
assume (IfThen(my_d_first_beat, my_resp_opcode_legal),
"If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" +
"request message" + extra)
}
def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = {
val c_first = edge.first(c.bits, c.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (c.valid && !c_first) {
monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra)
monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra)
monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra)
monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra)
monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra)
}
when (c.fire && c_first) {
opcode := c.bits.opcode
param := c.bits.param
size := c.bits.size
source := c.bits.source
address := c.bits.address
}
}
def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = {
val d_first = edge.first(d.bits, d.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val sink = Reg(UInt())
val denied = Reg(Bool())
when (d.valid && !d_first) {
assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra)
assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra)
assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra)
assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra)
assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra)
assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra)
}
when (d.fire && d_first) {
opcode := d.bits.opcode
param := d.bits.param
size := d.bits.size
source := d.bits.source
sink := d.bits.sink
denied := d.bits.denied
}
}
def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = {
legalizeMultibeatA(bundle.a, edge)
legalizeMultibeatD(bundle.d, edge)
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
legalizeMultibeatB(bundle.b, edge)
legalizeMultibeatC(bundle.c, edge)
}
}
//This is left in for almond which doesn't adhere to the tilelink protocol
@deprecated("Use legalizeADSource instead if possible","")
def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = {
val inflight = RegInit(0.U(edge.client.endSourceId.W))
val a_first = edge.first(bundle.a.bits, bundle.a.fire)
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
val a_set = WireInit(0.U(edge.client.endSourceId.W))
when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) {
a_set := UIntToOH(bundle.a.bits.source)
assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra)
}
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
assume((a_set | inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra)
}
if (edge.manager.minLatency > 0) {
assume(a_set =/= d_clr || !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra)
}
inflight := (inflight | a_set) & ~d_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
assert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = {
val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset)
val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything
val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size)
val log_a_size_bus_size = log2Ceil(a_size_bus_size)
def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits
val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error
inflight.suggestName("inflight")
val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
inflight_opcodes.suggestName("inflight_opcodes")
val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
inflight_sizes.suggestName("inflight_sizes")
val a_first = edge.first(bundle.a.bits, bundle.a.fire)
a_first.suggestName("a_first")
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
d_first.suggestName("d_first")
val a_set = WireInit(0.U(edge.client.endSourceId.W))
val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
a_set.suggestName("a_set")
a_set_wo_ready.suggestName("a_set_wo_ready")
val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
a_opcodes_set.suggestName("a_opcodes_set")
val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
a_sizes_set.suggestName("a_sizes_set")
val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W))
a_opcode_lookup.suggestName("a_opcode_lookup")
a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U
val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W))
a_size_lookup.suggestName("a_size_lookup")
a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U
val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant))
val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant))
val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W))
a_opcodes_set_interm.suggestName("a_opcodes_set_interm")
val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W))
a_sizes_set_interm.suggestName("a_sizes_set_interm")
when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) {
a_set_wo_ready := UIntToOH(bundle.a.bits.source)
}
when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) {
a_set := UIntToOH(bundle.a.bits.source)
a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) | 1.U
a_sizes_set_interm := (bundle.a.bits.size << 1.U) | 1.U
a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U)
a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U)
monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra)
}
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
d_clr.suggestName("d_clr")
d_clr_wo_ready.suggestName("d_clr_wo_ready")
val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
d_opcodes_clr.suggestName("d_opcodes_clr")
val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
d_sizes_clr.suggestName("d_sizes_clr")
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr_wo_ready := UIntToOH(bundle.d.bits.source)
}
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U)
d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U)
}
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source)
assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra)
when (same_cycle_resp) {
assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) ||
(bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra)
assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra)
} .otherwise {
assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) ||
(bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra)
assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra)
}
}
when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) {
assume((!bundle.d.ready) || bundle.a.ready, "ready check")
}
if (edge.manager.minLatency > 0) {
assume(a_set_wo_ready =/= d_clr_wo_ready || !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra)
}
inflight := (inflight | a_set) & ~d_clr
inflight_opcodes := (inflight_opcodes | a_opcodes_set) & ~d_opcodes_clr
inflight_sizes := (inflight_sizes | a_sizes_set) & ~d_sizes_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = {
val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset)
val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything
val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size)
val log_c_size_bus_size = log2Ceil(c_size_bus_size)
def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits
val inflight = RegInit(0.U((2 max edge.client.endSourceId).W))
val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
inflight.suggestName("inflight")
inflight_opcodes.suggestName("inflight_opcodes")
inflight_sizes.suggestName("inflight_sizes")
val c_first = edge.first(bundle.c.bits, bundle.c.fire)
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
c_first.suggestName("c_first")
d_first.suggestName("d_first")
val c_set = WireInit(0.U(edge.client.endSourceId.W))
val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
c_set.suggestName("c_set")
c_set_wo_ready.suggestName("c_set_wo_ready")
c_opcodes_set.suggestName("c_opcodes_set")
c_sizes_set.suggestName("c_sizes_set")
val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W))
val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W))
c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U
c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U
c_opcode_lookup.suggestName("c_opcode_lookup")
c_size_lookup.suggestName("c_size_lookup")
val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W))
val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W))
c_opcodes_set_interm.suggestName("c_opcodes_set_interm")
c_sizes_set_interm.suggestName("c_sizes_set_interm")
when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) {
c_set_wo_ready := UIntToOH(bundle.c.bits.source)
}
when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) {
c_set := UIntToOH(bundle.c.bits.source)
c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) | 1.U
c_sizes_set_interm := (bundle.c.bits.size << 1.U) | 1.U
c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U)
c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U)
monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra)
}
val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck || bundle.c.bits.opcode === TLMessages.ProbeAckData
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
d_clr.suggestName("d_clr")
d_clr_wo_ready.suggestName("d_clr_wo_ready")
d_opcodes_clr.suggestName("d_opcodes_clr")
d_sizes_clr.suggestName("d_sizes_clr")
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
d_clr_wo_ready := UIntToOH(bundle.d.bits.source)
}
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U)
d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U)
}
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source)
assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra)
when (same_cycle_resp) {
assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra)
} .otherwise {
assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra)
}
}
when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) {
assume((!bundle.d.ready) || bundle.c.ready, "ready check")
}
if (edge.manager.minLatency > 0) {
when (c_set_wo_ready.orR) {
assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra)
}
}
inflight := (inflight | c_set) & ~d_clr
inflight_opcodes := (inflight_opcodes | c_opcodes_set) & ~d_opcodes_clr
inflight_sizes := (inflight_sizes | c_sizes_set) & ~d_sizes_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.c.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = {
val inflight = RegInit(0.U(edge.manager.endSinkId.W))
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
val e_first = true.B
val d_set = WireInit(0.U(edge.manager.endSinkId.W))
when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) {
d_set := UIntToOH(bundle.d.bits.sink)
assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra)
}
val e_clr = WireInit(0.U(edge.manager.endSinkId.W))
when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) {
e_clr := UIntToOH(bundle.e.bits.sink)
monAssert((d_set | inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra)
}
// edge.client.minLatency applies to BC, not DE
inflight := (inflight | d_set) & ~e_clr
}
def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = {
val sourceBits = log2Ceil(edge.client.endSourceId)
val tooBig = 14 // >16kB worth of flight information gets to be too much
if (sourceBits > tooBig) {
println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked")
} else {
if (args.edge.params(TestplanTestType).simulation) {
if (args.edge.params(TLMonitorStrictMode)) {
legalizeADSource(bundle, edge)
legalizeCDSource(bundle, edge)
} else {
legalizeADSourceOld(bundle, edge)
}
}
if (args.edge.params(TestplanTestType).formal) {
legalizeADSourceFormal(bundle, edge)
}
}
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
// legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize...
val sinkBits = log2Ceil(edge.manager.endSinkId)
if (sinkBits > tooBig) {
println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked")
} else {
legalizeDESink(bundle, edge)
}
}
}
def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = {
legalizeFormat (bundle, edge)
legalizeMultibeat (bundle, edge)
legalizeUnique (bundle, edge)
}
}
File Misc.scala:
// See LICENSE.Berkeley for license details.
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util._
import chisel3.util.random.LFSR
import org.chipsalliance.cde.config.Parameters
import scala.math._
class ParameterizedBundle(implicit p: Parameters) extends Bundle
trait Clocked extends Bundle {
val clock = Clock()
val reset = Bool()
}
object DecoupledHelper {
def apply(rvs: Bool*) = new DecoupledHelper(rvs)
}
class DecoupledHelper(val rvs: Seq[Bool]) {
def fire(exclude: Bool, includes: Bool*) = {
require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!")
(rvs.filter(_ ne exclude) ++ includes).reduce(_ && _)
}
def fire() = {
rvs.reduce(_ && _)
}
}
object MuxT {
def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2))
def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3))
def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4))
}
/** Creates a cascade of n MuxTs to search for a key value. */
object MuxTLookup {
def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = {
var res = default
for ((k, v) <- mapping.reverse)
res = MuxT(k === key, v, res)
res
}
def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = {
var res = default
for ((k, v) <- mapping.reverse)
res = MuxT(k === key, v, res)
res
}
}
object ValidMux {
def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = {
apply(v1 +: v2.toSeq)
}
def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = {
val out = Wire(Valid(valids.head.bits.cloneType))
out.valid := valids.map(_.valid).reduce(_ || _)
out.bits := MuxCase(valids.head.bits,
valids.map(v => (v.valid -> v.bits)))
out
}
}
object Str
{
def apply(s: String): UInt = {
var i = BigInt(0)
require(s.forall(validChar _))
for (c <- s)
i = (i << 8) | c
i.U((s.length*8).W)
}
def apply(x: Char): UInt = {
require(validChar(x))
x.U(8.W)
}
def apply(x: UInt): UInt = apply(x, 10)
def apply(x: UInt, radix: Int): UInt = {
val rad = radix.U
val w = x.getWidth
require(w > 0)
var q = x
var s = digit(q % rad)
for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {
q = q / rad
s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s)
}
s
}
def apply(x: SInt): UInt = apply(x, 10)
def apply(x: SInt, radix: Int): UInt = {
val neg = x < 0.S
val abs = x.abs.asUInt
if (radix != 10) {
Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix))
} else {
val rad = radix.U
val w = abs.getWidth
require(w > 0)
var q = abs
var s = digit(q % rad)
var needSign = neg
for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {
q = q / rad
val placeSpace = q === 0.U
val space = Mux(needSign, Str('-'), Str(' '))
needSign = needSign && !placeSpace
s = Cat(Mux(placeSpace, space, digit(q % rad)), s)
}
Cat(Mux(needSign, Str('-'), Str(' ')), s)
}
}
private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0)
private def validChar(x: Char) = x == (x & 0xFF)
}
object Split
{
def apply(x: UInt, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n0), x.extract(n0-1,0))
}
def apply(x: UInt, n1: Int, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))
}
def apply(x: UInt, n2: Int, n1: Int, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))
}
}
object Random
{
def apply(mod: Int, random: UInt): UInt = {
if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0)
else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod))
}
def apply(mod: Int): UInt = apply(mod, randomizer)
def oneHot(mod: Int, random: UInt): UInt = {
if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0))
else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt
}
def oneHot(mod: Int): UInt = oneHot(mod, randomizer)
private def randomizer = LFSR(16)
private def partition(value: UInt, slices: Int) =
Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U)
}
object Majority {
def apply(in: Set[Bool]): Bool = {
val n = (in.size >> 1) + 1
val clauses = in.subsets(n).map(_.reduce(_ && _))
clauses.reduce(_ || _)
}
def apply(in: Seq[Bool]): Bool = apply(in.toSet)
def apply(in: UInt): Bool = apply(in.asBools.toSet)
}
object PopCountAtLeast {
private def two(x: UInt): (Bool, Bool) = x.getWidth match {
case 1 => (x.asBool, false.B)
case n =>
val half = x.getWidth / 2
val (leftOne, leftTwo) = two(x(half - 1, 0))
val (rightOne, rightTwo) = two(x(x.getWidth - 1, half))
(leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne))
}
def apply(x: UInt, n: Int): Bool = n match {
case 0 => true.B
case 1 => x.orR
case 2 => two(x)._2
case 3 => PopCount(x) >= n.U
}
}
// This gets used everywhere, so make the smallest circuit possible ...
// Given an address and size, create a mask of beatBytes size
// eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111
// groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01
object MaskGen {
def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = {
require (groupBy >= 1 && beatBytes >= groupBy)
require (isPow2(beatBytes) && isPow2(groupBy))
val lgBytes = log2Ceil(beatBytes)
val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U
def helper(i: Int): Seq[(Bool, Bool)] = {
if (i == 0) {
Seq((lgSize >= lgBytes.asUInt, true.B))
} else {
val sub = helper(i-1)
val size = sizeOH(lgBytes - i)
val bit = addr_lo(lgBytes - i)
val nbit = !bit
Seq.tabulate (1 << i) { j =>
val (sub_acc, sub_eq) = sub(j/2)
val eq = sub_eq && (if (j % 2 == 1) bit else nbit)
val acc = sub_acc || (size && eq)
(acc, eq)
}
}
}
if (groupBy == beatBytes) 1.U else
Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse)
}
}
File PlusArg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.experimental._
import chisel3.util.HasBlackBoxResource
@deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05")
case class PlusArgInfo(default: BigInt, docstring: String)
/** Case class for PlusArg information
*
* @tparam A scala type of the PlusArg value
* @param default optional default value
* @param docstring text to include in the help
* @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT)
*/
private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String)
/** Typeclass for converting a type to a doctype string
* @tparam A some type
*/
trait Doctypeable[A] {
/** Return the doctype string for some option */
def toDoctype(a: Option[A]): String
}
/** Object containing implementations of the Doctypeable typeclass */
object Doctypes {
/** Converts an Int => "INT" */
implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" }
/** Converts a BigInt => "INT" */
implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" }
/** Converts a String => "STRING" */
implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" }
}
class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map(
"FORMAT" -> StringParam(format),
"DEFAULT" -> IntParam(default),
"WIDTH" -> IntParam(width)
)) with HasBlackBoxResource {
val io = IO(new Bundle {
val out = Output(UInt(width.W))
})
addResource("/vsrc/plusarg_reader.v")
}
/* This wrapper class has no outputs, making it clear it is a simulation-only construct */
class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module {
val io = IO(new Bundle {
val count = Input(UInt(width.W))
})
val max = Module(new plusarg_reader(format, default, docstring, width)).io.out
when (max > 0.U) {
assert (io.count < max, s"Timeout exceeded: $docstring")
}
}
import Doctypes._
object PlusArg
{
/** PlusArg("foo") will return 42.U if the simulation is run with +foo=42
* Do not use this as an initial register value. The value is set in an
* initial block and thus accessing it from another initial is racey.
* Add a docstring to document the arg, which can be dumped in an elaboration
* pass.
*/
def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = {
PlusArgArtefacts.append(name, Some(default), docstring)
Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out
}
/** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert
* to kill the simulation when count exceeds the specified integer argument.
* Default 0 will never assert.
*/
def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = {
PlusArgArtefacts.append(name, Some(default), docstring)
Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count
}
}
object PlusArgArtefacts {
private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty
/* Add a new PlusArg */
@deprecated(
"Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08",
"Rocket Chip 2020.05"
)
def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring)
/** Add a new PlusArg
*
* @tparam A scala type of the PlusArg value
* @param name name for the PlusArg
* @param default optional default value
* @param docstring text to include in the help
*/
def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit =
artefacts = artefacts ++
Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default)))
/* From plus args, generate help text */
private def serializeHelp_cHeader(tab: String = ""): String = artefacts
.map{ case(arg, info) =>
s"""|$tab+$arg=${info.doctype}\\n\\
|$tab${" "*20}${info.docstring}\\n\\
|""".stripMargin ++ info.default.map{ case default =>
s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("")
}.toSeq.mkString("\\n\\\n") ++ "\""
/* From plus args, generate a char array of their names */
private def serializeArray_cHeader(tab: String = ""): String = {
val prettyTab = tab + " " * 44 // Length of 'static const ...'
s"${tab}static const char * verilog_plusargs [] = {\\\n" ++
artefacts
.map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" }
.mkString("")++
s"${prettyTab}0};"
}
/* Generate C code to be included in emulator.cc that helps with
* argument parsing based on available Verilog PlusArgs */
def serialize_cHeader(): String =
s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\
|${serializeHelp_cHeader(" "*7)}
|${serializeArray_cHeader()}
|""".stripMargin
}
File package.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip
import chisel3._
import chisel3.util._
import scala.math.min
import scala.collection.{immutable, mutable}
package object util {
implicit class UnzippableOption[S, T](val x: Option[(S, T)]) {
def unzip = (x.map(_._1), x.map(_._2))
}
implicit class UIntIsOneOf(private val x: UInt) extends AnyVal {
def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR
def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq)
}
implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal {
/** Like Vec.apply(idx), but tolerates indices of mismatched width */
def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0))
}
implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal {
def apply(idx: UInt): T = {
if (x.size <= 1) {
x.head
} else if (!isPow2(x.size)) {
// For non-power-of-2 seqs, reflect elements to simplify decoder
(x ++ x.takeRight(x.size & -x.size)).toSeq(idx)
} else {
// Ignore MSBs of idx
val truncIdx =
if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx
else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0)
x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) }
}
}
def extract(idx: UInt): T = VecInit(x).extract(idx)
def asUInt: UInt = Cat(x.map(_.asUInt).reverse)
def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n)
def rotate(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n)
def rotateRight(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
}
// allow bitwise ops on Seq[Bool] just like UInt
implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal {
def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b }
def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b }
def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b }
def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x
def >> (n: Int): Seq[Bool] = x drop n
def unary_~ : Seq[Bool] = x.map(!_)
def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_)
def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_)
def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_)
private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B)
}
implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal {
def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable))
def getElements: Seq[Element] = x match {
case e: Element => Seq(e)
case a: Aggregate => a.getElements.flatMap(_.getElements)
}
}
/** Any Data subtype that has a Bool member named valid. */
type DataCanBeValid = Data { val valid: Bool }
implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal {
def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable)
}
implicit class StringToAugmentedString(private val x: String) extends AnyVal {
/** converts from camel case to to underscores, also removing all spaces */
def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") {
case (acc, c) if c.isUpper => acc + "_" + c.toLower
case (acc, c) if c == ' ' => acc
case (acc, c) => acc + c
}
/** converts spaces or underscores to hyphens, also lowering case */
def kebab: String = x.toLowerCase map {
case ' ' => '-'
case '_' => '-'
case c => c
}
def named(name: Option[String]): String = {
x + name.map("_named_" + _ ).getOrElse("_with_no_name")
}
def named(name: String): String = named(Some(name))
}
implicit def uintToBitPat(x: UInt): BitPat = BitPat(x)
implicit def wcToUInt(c: WideCounter): UInt = c.value
implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal {
def sextTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x)
}
def padTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(0.U((n - x.getWidth).W), x)
}
// shifts left by n if n >= 0, or right by -n if n < 0
def << (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << n(w-1, 0)
Mux(n(w), shifted >> (1 << w), shifted)
}
// shifts right by n if n >= 0, or left by -n if n < 0
def >> (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << (1 << w) >> n(w-1, 0)
Mux(n(w), shifted, shifted >> (1 << w))
}
// Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts
def extract(hi: Int, lo: Int): UInt = {
require(hi >= lo-1)
if (hi == lo-1) 0.U
else x(hi, lo)
}
// Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts
def extractOption(hi: Int, lo: Int): Option[UInt] = {
require(hi >= lo-1)
if (hi == lo-1) None
else Some(x(hi, lo))
}
// like x & ~y, but first truncate or zero-extend y to x's width
def andNot(y: UInt): UInt = x & ~(y | (x & 0.U))
def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n)
def rotateRight(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r))
}
}
def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n))
def rotateLeft(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r))
}
}
// compute (this + y) % n, given (this < n) and (y < n)
def addWrap(y: UInt, n: Int): UInt = {
val z = x +& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0)
}
// compute (this - y) % n, given (this < n) and (y < n)
def subWrap(y: UInt, n: Int): UInt = {
val z = x -& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0)
}
def grouped(width: Int): Seq[UInt] =
(0 until x.getWidth by width).map(base => x(base + width - 1, base))
def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds
def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x)
// Like >=, but prevents x-prop for ('x >= 0)
def >== (y: UInt): Bool = x >= y || y === 0.U
}
implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal {
def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y)
def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y)
}
implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal {
def toInt: Int = if (x) 1 else 0
// this one's snagged from scalaz
def option[T](z: => T): Option[T] = if (x) Some(z) else None
}
implicit class IntToAugmentedInt(private val x: Int) extends AnyVal {
// exact log2
def log2: Int = {
require(isPow2(x))
log2Ceil(x)
}
}
def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x)
def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x))
def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0)
def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1)
def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None
// Fill 1s from low bits to high bits
def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth)
def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0))
helper(1, x)(width-1, 0)
}
// Fill 1s form high bits to low bits
def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth)
def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x >> s))
helper(1, x)(width-1, 0)
}
def OptimizationBarrier[T <: Data](in: T): T = {
val barrier = Module(new Module {
val io = IO(new Bundle {
val x = Input(chiselTypeOf(in))
val y = Output(chiselTypeOf(in))
})
io.y := io.x
override def desiredName = s"OptimizationBarrier_${in.typeName}"
})
barrier.io.x := in
barrier.io.y
}
/** Similar to Seq.groupBy except this returns a Seq instead of a Map
* Useful for deterministic code generation
*/
def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = {
val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]]
for (x <- xs) {
val key = f(x)
val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A])
l += x
}
map.view.map({ case (k, vs) => k -> vs.toList }).toList
}
def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match {
case 1 => List.fill(n)(in.head)
case x if x == n => in
case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in")
}
// HeterogeneousBag moved to standalond diplomacy
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts)
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag
}
File Parameters.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.diplomacy
import chisel3._
import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor}
import freechips.rocketchip.util.ShiftQueue
/** Options for describing the attributes of memory regions */
object RegionType {
// Define the 'more relaxed than' ordering
val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS)
sealed trait T extends Ordered[T] {
def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this)
}
case object CACHED extends T // an intermediate agent may have cached a copy of the region for you
case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided
case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible
case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached
case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects
case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed
case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively
}
// A non-empty half-open range; [start, end)
case class IdRange(start: Int, end: Int) extends Ordered[IdRange]
{
require (start >= 0, s"Ids cannot be negative, but got: $start.")
require (start <= end, "Id ranges cannot be negative.")
def compare(x: IdRange) = {
val primary = (this.start - x.start).signum
val secondary = (x.end - this.end).signum
if (primary != 0) primary else secondary
}
def overlaps(x: IdRange) = start < x.end && x.start < end
def contains(x: IdRange) = start <= x.start && x.end <= end
def contains(x: Int) = start <= x && x < end
def contains(x: UInt) =
if (size == 0) {
false.B
} else if (size == 1) { // simple comparison
x === start.U
} else {
// find index of largest different bit
val largestDeltaBit = log2Floor(start ^ (end-1))
val smallestCommonBit = largestDeltaBit + 1 // may not exist in x
val uncommonMask = (1 << smallestCommonBit) - 1
val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0)
// the prefix must match exactly (note: may shift ALL bits away)
(x >> smallestCommonBit) === (start >> smallestCommonBit).U &&
// firrtl constant prop range analysis can eliminate these two:
(start & uncommonMask).U <= uncommonBits &&
uncommonBits <= ((end-1) & uncommonMask).U
}
def shift(x: Int) = IdRange(start+x, end+x)
def size = end - start
def isEmpty = end == start
def range = start until end
}
object IdRange
{
def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else {
val ranges = s.sorted
(ranges.tail zip ranges.init) find { case (a, b) => a overlaps b }
}
}
// An potentially empty inclusive range of 2-powers [min, max] (in bytes)
case class TransferSizes(min: Int, max: Int)
{
def this(x: Int) = this(x, x)
require (min <= max, s"Min transfer $min > max transfer $max")
require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)")
require (max == 0 || isPow2(max), s"TransferSizes must be a power of 2, got: $max")
require (min == 0 || isPow2(min), s"TransferSizes must be a power of 2, got: $min")
require (max == 0 || min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)")
def none = min == 0
def contains(x: Int) = isPow2(x) && min <= x && x <= max
def containsLg(x: Int) = contains(1 << x)
def containsLg(x: UInt) =
if (none) false.B
else if (min == max) { log2Ceil(min).U === x }
else { log2Ceil(min).U <= x && x <= log2Ceil(max).U }
def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max)
def intersect(x: TransferSizes) =
if (x.max < min || max < x.min) TransferSizes.none
else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max))
// Not a union, because the result may contain sizes contained by neither term
// NOT TO BE CONFUSED WITH COVERPOINTS
def mincover(x: TransferSizes) = {
if (none) {
x
} else if (x.none) {
this
} else {
TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max))
}
}
override def toString() = "TransferSizes[%d, %d]".format(min, max)
}
object TransferSizes {
def apply(x: Int) = new TransferSizes(x)
val none = new TransferSizes(0)
def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _)
def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _)
implicit def asBool(x: TransferSizes) = !x.none
}
// AddressSets specify the address space managed by the manager
// Base is the base address, and mask are the bits consumed by the manager
// e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff
// e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ...
case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet]
{
// Forbid misaligned base address (and empty sets)
require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}")
require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous
// We do allow negative mask (=> ignore all high bits)
def contains(x: BigInt) = ((x ^ base) & ~mask) == 0
def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S
// turn x into an address contained in this set
def legalize(x: UInt): UInt = base.U | (mask.U & x)
// overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1)
def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0
// contains iff bitwise: x.mask => mask && contains(x.base)
def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0
// The number of bytes to which the manager must be aligned
def alignment = ((mask + 1) & ~mask)
// Is this a contiguous memory range
def contiguous = alignment == mask+1
def finite = mask >= 0
def max = { require (finite, "Max cannot be calculated on infinite mask"); base | mask }
// Widen the match function to ignore all bits in imask
def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask)
// Return an AddressSet that only contains the addresses both sets contain
def intersect(x: AddressSet): Option[AddressSet] = {
if (!overlaps(x)) {
None
} else {
val r_mask = mask & x.mask
val r_base = base | x.base
Some(AddressSet(r_base, r_mask))
}
}
def subtract(x: AddressSet): Seq[AddressSet] = {
intersect(x) match {
case None => Seq(this)
case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit =>
val nmask = (mask & (bit-1)) | remove.mask
val nbase = (remove.base ^ bit) & ~nmask
AddressSet(nbase, nmask)
}
}
}
// AddressSets have one natural Ordering (the containment order, if contiguous)
def compare(x: AddressSet) = {
val primary = (this.base - x.base).signum // smallest address first
val secondary = (x.mask - this.mask).signum // largest mask first
if (primary != 0) primary else secondary
}
// We always want to see things in hex
override def toString() = {
if (mask >= 0) {
"AddressSet(0x%x, 0x%x)".format(base, mask)
} else {
"AddressSet(0x%x, ~0x%x)".format(base, ~mask)
}
}
def toRanges = {
require (finite, "Ranges cannot be calculated on infinite mask")
val size = alignment
val fragments = mask & ~(size-1)
val bits = bitIndexes(fragments)
(BigInt(0) until (BigInt(1) << bits.size)).map { i =>
val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) }
AddressRange(off, size)
}
}
}
object AddressSet
{
val everything = AddressSet(0, -1)
def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = {
if (size == 0) tail.reverse else {
val maxBaseAlignment = base & (-base) // 0 for infinite (LSB)
val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size
val step =
if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment)
maxSizeAlignment else maxBaseAlignment
misaligned(base+step, size-step, AddressSet(base, step-1) +: tail)
}
}
def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = {
// Pair terms up by ignoring 'bit'
seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) =>
if (seq.size == 1) {
seq.head // singleton -> unaffected
} else {
key.copy(mask = key.mask | bit) // pair - widen mask by bit
}
}.toList
}
def unify(seq: Seq[AddressSet]): Seq[AddressSet] = {
val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _)
AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted
}
def enumerateMask(mask: BigInt): Seq[BigInt] = {
def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] =
if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail)
helper(0, Nil)
}
def enumerateBits(mask: BigInt): Seq[BigInt] = {
def helper(x: BigInt): Seq[BigInt] = {
if (x == 0) {
Nil
} else {
val bit = x & (-x)
bit +: helper(x & ~bit)
}
}
helper(mask)
}
}
case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean)
{
require (depth >= 0, "Buffer depth must be >= 0")
def isDefined = depth > 0
def latency = if (isDefined && !flow) 1 else 0
def apply[T <: Data](x: DecoupledIO[T]) =
if (isDefined) Queue(x, depth, flow=flow, pipe=pipe)
else x
def irrevocable[T <: Data](x: ReadyValidIO[T]) =
if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe)
else x
def sq[T <: Data](x: DecoupledIO[T]) =
if (!isDefined) x else {
val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe))
sq.io.enq <> x
sq.io.deq
}
override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "")
}
object BufferParams
{
implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false)
val default = BufferParams(2)
val none = BufferParams(0)
val flow = BufferParams(1, true, false)
val pipe = BufferParams(1, false, true)
}
case class TriStateValue(value: Boolean, set: Boolean)
{
def update(orig: Boolean) = if (set) value else orig
}
object TriStateValue
{
implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true)
def unset = TriStateValue(false, false)
}
trait DirectedBuffers[T] {
def copyIn(x: BufferParams): T
def copyOut(x: BufferParams): T
def copyInOut(x: BufferParams): T
}
trait IdMapEntry {
def name: String
def from: IdRange
def to: IdRange
def isCache: Boolean
def requestFifo: Boolean
def maxTransactionsInFlight: Option[Int]
def pretty(fmt: String) =
if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5
fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "")
} else {
fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "")
}
}
abstract class IdMap[T <: IdMapEntry] {
protected val fmt: String
val mapping: Seq[T]
def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n")
}
File Edges.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.util._
class TLEdge(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdgeParameters(client, manager, params, sourceInfo)
{
def isAligned(address: UInt, lgSize: UInt): Bool = {
if (maxLgSize == 0) true.B else {
val mask = UIntToOH1(lgSize, maxLgSize)
(address & mask) === 0.U
}
}
def mask(address: UInt, lgSize: UInt): UInt =
MaskGen(address, lgSize, manager.beatBytes)
def staticHasData(bundle: TLChannel): Option[Boolean] = {
bundle match {
case _:TLBundleA => {
// Do there exist A messages with Data?
val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial
// Do there exist A messages without Data?
val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint
// Statically optimize the case where hasData is a constant
if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None
}
case _:TLBundleB => {
// Do there exist B messages with Data?
val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial
// Do there exist B messages without Data?
val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint
// Statically optimize the case where hasData is a constant
if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None
}
case _:TLBundleC => {
// Do there eixst C messages with Data?
val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe
// Do there exist C messages without Data?
val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe
if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None
}
case _:TLBundleD => {
// Do there eixst D messages with Data?
val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB
// Do there exist D messages without Data?
val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT
if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None
}
case _:TLBundleE => Some(false)
}
}
def isRequest(x: TLChannel): Bool = {
x match {
case a: TLBundleA => true.B
case b: TLBundleB => true.B
case c: TLBundleC => c.opcode(2) && c.opcode(1)
// opcode === TLMessages.Release ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(2) && !d.opcode(1)
// opcode === TLMessages.Grant ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
}
def isResponse(x: TLChannel): Bool = {
x match {
case a: TLBundleA => false.B
case b: TLBundleB => false.B
case c: TLBundleC => !c.opcode(2) || !c.opcode(1)
// opcode =/= TLMessages.Release &&
// opcode =/= TLMessages.ReleaseData
case d: TLBundleD => true.B // Grant isResponse + isRequest
case e: TLBundleE => true.B
}
}
def hasData(x: TLChannel): Bool = {
val opdata = x match {
case a: TLBundleA => !a.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case b: TLBundleB => !b.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case c: TLBundleC => c.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.ProbeAckData ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
staticHasData(x).map(_.B).getOrElse(opdata)
}
def opcode(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.opcode
case b: TLBundleB => b.opcode
case c: TLBundleC => c.opcode
case d: TLBundleD => d.opcode
}
}
def param(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.param
case b: TLBundleB => b.param
case c: TLBundleC => c.param
case d: TLBundleD => d.param
}
}
def size(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.size
case b: TLBundleB => b.size
case c: TLBundleC => c.size
case d: TLBundleD => d.size
}
}
def data(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.data
case b: TLBundleB => b.data
case c: TLBundleC => c.data
case d: TLBundleD => d.data
}
}
def corrupt(x: TLDataChannel): Bool = {
x match {
case a: TLBundleA => a.corrupt
case b: TLBundleB => b.corrupt
case c: TLBundleC => c.corrupt
case d: TLBundleD => d.corrupt
}
}
def mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.mask
case b: TLBundleB => b.mask
case c: TLBundleC => mask(c.address, c.size)
}
}
def full_mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => mask(a.address, a.size)
case b: TLBundleB => mask(b.address, b.size)
case c: TLBundleC => mask(c.address, c.size)
}
}
def address(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.address
case b: TLBundleB => b.address
case c: TLBundleC => c.address
}
}
def source(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.source
case b: TLBundleB => b.source
case c: TLBundleC => c.source
case d: TLBundleD => d.source
}
}
def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes)
def addr_lo(x: UInt): UInt =
if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0)
def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x))
def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x))
def numBeats(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 1.U
case bundle: TLDataChannel => {
val hasData = this.hasData(bundle)
val size = this.size(bundle)
val cutoff = log2Ceil(manager.beatBytes)
val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U
val decode = UIntToOH(size, maxLgSize+1) >> cutoff
Mux(hasData, decode | small.asUInt, 1.U)
}
}
}
def numBeats1(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 0.U
case bundle: TLDataChannel => {
if (maxLgSize == 0) {
0.U
} else {
val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes)
Mux(hasData(bundle), decode, 0.U)
}
}
}
}
def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val beats1 = numBeats1(bits)
val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W))
val counter1 = counter - 1.U
val first = counter === 0.U
val last = counter === 1.U || beats1 === 0.U
val done = last && fire
val count = (beats1 & ~counter1)
when (fire) {
counter := Mux(first, beats1, counter1)
}
(first, last, done, count)
}
def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1
def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire)
def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid)
def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2
def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire)
def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid)
def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3
def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire)
def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid)
def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3)
}
def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire)
def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid)
def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4)
}
def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire)
def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid)
def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes))
}
def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire)
def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid)
// Does the request need T permissions to be executed?
def needT(a: TLBundleA): Bool = {
val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLPermissions.NtoB -> false.B,
TLPermissions.NtoT -> true.B,
TLPermissions.BtoT -> true.B))
MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array(
TLMessages.PutFullData -> true.B,
TLMessages.PutPartialData -> true.B,
TLMessages.ArithmeticData -> true.B,
TLMessages.LogicalData -> true.B,
TLMessages.Get -> false.B,
TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLHints.PREFETCH_READ -> false.B,
TLHints.PREFETCH_WRITE -> true.B)),
TLMessages.AcquireBlock -> acq_needT,
TLMessages.AcquirePerm -> acq_needT))
}
// This is a very expensive circuit; use only if you really mean it!
def inFlight(x: TLBundle): (UInt, UInt) = {
val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W))
val bce = manager.anySupportAcquireB && client.anySupportProbe
val (a_first, a_last, _) = firstlast(x.a)
val (b_first, b_last, _) = firstlast(x.b)
val (c_first, c_last, _) = firstlast(x.c)
val (d_first, d_last, _) = firstlast(x.d)
val (e_first, e_last, _) = firstlast(x.e)
val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits))
val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits))
val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits))
val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits))
val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits))
val a_inc = x.a.fire && a_first && a_request
val b_inc = x.b.fire && b_first && b_request
val c_inc = x.c.fire && c_first && c_request
val d_inc = x.d.fire && d_first && d_request
val e_inc = x.e.fire && e_first && e_request
val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil))
val a_dec = x.a.fire && a_last && a_response
val b_dec = x.b.fire && b_last && b_response
val c_dec = x.c.fire && c_last && c_response
val d_dec = x.d.fire && d_last && d_response
val e_dec = x.e.fire && e_last && e_response
val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil))
val next_flight = flight + PopCount(inc) - PopCount(dec)
flight := next_flight
(flight, next_flight)
}
def prettySourceMapping(context: String): String = {
s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n"
}
}
class TLEdgeOut(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
// Transfers
def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquireBlock
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquirePerm
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.Release
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ReleaseData
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) =
Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B)
def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAck
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions, data)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAckData
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B)
def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink)
def GrantAck(toSink: UInt): TLBundleE = {
val e = Wire(new TLBundleE(bundle))
e.sink := toSink
e
}
// Accesses
def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsGetFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Get
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutFullFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutFullData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, mask, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutPartialFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutPartialData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = {
require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsArithmeticFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.ArithmeticData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsLogicalFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.LogicalData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = {
require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsHintFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Hint
a.param := param
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data)
def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAckData
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size)
def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.HintAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
}
class TLEdgeIn(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = {
val todo = x.filter(!_.isEmpty)
val heads = todo.map(_.head)
val tails = todo.map(_.tail)
if (todo.isEmpty) Nil else { heads +: myTranspose(tails) }
}
// Transfers
def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = {
require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}")
val legal = client.supportsProbe(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Probe
b.param := capPermissions
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.Grant
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.GrantData
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B)
def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.ReleaseAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
// Accesses
def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = {
require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsGet(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Get
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsPutFull(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutFullData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, mask, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsPutPartial(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutPartialData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsArithmetic(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.ArithmeticData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsLogical(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.LogicalData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = {
require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsHint(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Hint
b.param := param
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size)
def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied)
def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data)
def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAckData
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B)
def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied)
def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B)
def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.HintAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
}
| module TLMonitor_41( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input [4:0] io_in_a_bits_source, // @[Monitor.scala:20:14]
input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input io_in_a_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input [4:0] io_in_d_bits_source, // @[Monitor.scala:20:14]
input io_in_d_bits_sink, // @[Monitor.scala:20:14]
input io_in_d_bits_denied, // @[Monitor.scala:20:14]
input io_in_d_bits_corrupt // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire [12:0] _GEN = {10'h0, io_in_a_bits_size}; // @[package.scala:243:71]
wire _a_first_T_1 = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35]
reg [2:0] a_first_counter; // @[Edges.scala:229:27]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [2:0] param; // @[Monitor.scala:388:22]
reg [2:0] size; // @[Monitor.scala:389:22]
reg [4:0] source; // @[Monitor.scala:390:22]
reg [31:0] address; // @[Monitor.scala:391:22]
reg [2:0] d_first_counter; // @[Edges.scala:229:27]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [1:0] param_1; // @[Monitor.scala:539:22]
reg [2:0] size_1; // @[Monitor.scala:540:22]
reg [4:0] source_1; // @[Monitor.scala:541:22]
reg sink; // @[Monitor.scala:542:22]
reg denied; // @[Monitor.scala:543:22]
reg [19:0] inflight; // @[Monitor.scala:614:27]
reg [79:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [79:0] inflight_sizes; // @[Monitor.scala:618:33]
reg [2:0] a_first_counter_1; // @[Edges.scala:229:27]
wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25]
reg [2:0] d_first_counter_1; // @[Edges.scala:229:27]
wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire [31:0] _GEN_0 = {27'h0, io_in_a_bits_source}; // @[OneHot.scala:58:35]
wire _GEN_1 = _a_first_T_1 & a_first_1; // @[Decoupled.scala:51:35]
wire d_release_ack = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala:673:46]
wire _GEN_2 = io_in_d_bits_opcode != 3'h6; // @[Monitor.scala:673:46, :674:74]
wire [31:0] _GEN_3 = {27'h0, io_in_d_bits_source}; // @[OneHot.scala:58:35]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
reg [19:0] inflight_1; // @[Monitor.scala:726:35]
reg [79:0] inflight_sizes_1; // @[Monitor.scala:728:35]
reg [2:0] d_first_counter_2; // @[Edges.scala:229:27]
wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27] |
Generate the Verilog code corresponding to the following Chisel files.
File Decode.scala:
// See LICENSE.Berkeley for license details.
package freechips.rocketchip.rocket
import chisel3._
import chisel3.util.BitPat
import chisel3.util.experimental.decode._
object DecodeLogic
{
// TODO This should be a method on BitPat
private def hasDontCare(bp: BitPat): Boolean = bp.mask.bitCount != bp.width
// Pads BitPats that are safe to pad (no don't cares), errors otherwise
private def padBP(bp: BitPat, width: Int): BitPat = {
if (bp.width == width) bp
else {
require(!hasDontCare(bp), s"Cannot pad '$bp' to '$width' bits because it has don't cares")
val diff = width - bp.width
require(diff > 0, s"Cannot pad '$bp' to '$width' because it is already '${bp.width}' bits wide!")
BitPat(0.U(diff.W)) ## bp
}
}
def apply(addr: UInt, default: BitPat, mapping: Iterable[(BitPat, BitPat)]): UInt =
chisel3.util.experimental.decode.decoder(QMCMinimizer, addr, TruthTable(mapping, default))
def apply(addr: UInt, default: Seq[BitPat], mappingIn: Iterable[(BitPat, Seq[BitPat])]): Seq[UInt] = {
val nElts = default.size
require(mappingIn.forall(_._2.size == nElts),
s"All Seq[BitPat] must be of the same length, got $nElts vs. ${mappingIn.find(_._2.size != nElts).get}"
)
val elementsGrouped = mappingIn.map(_._2).transpose
val elementWidths = elementsGrouped.zip(default).map { case (elts, default) =>
(default :: elts.toList).map(_.getWidth).max
}
val resultWidth = elementWidths.sum
val elementIndices = elementWidths.scan(resultWidth - 1) { case (l, r) => l - r }
// All BitPats that correspond to a given element in the result must have the same width in the
// chisel3 decoder. We will zero pad any BitPats that are too small so long as they dont have
// any don't cares. If there are don't cares, it is an error and the user needs to pad the
// BitPat themselves
val defaultsPadded = default.zip(elementWidths).map { case (bp, w) => padBP(bp, w) }
val mappingInPadded = mappingIn.map { case (in, elts) =>
in -> elts.zip(elementWidths).map { case (bp, w) => padBP(bp, w) }
}
val decoded = apply(addr, defaultsPadded.reduce(_ ## _), mappingInPadded.map { case (in, out) => (in, out.reduce(_ ## _)) })
elementIndices.zip(elementIndices.tail).map { case (msb, lsb) => decoded(msb, lsb + 1) }.toList
}
def apply(addr: UInt, default: Seq[BitPat], mappingIn: List[(UInt, Seq[BitPat])]): Seq[UInt] =
apply(addr, default, mappingIn.map(m => (BitPat(m._1), m._2)).asInstanceOf[Iterable[(BitPat, Seq[BitPat])]])
def apply(addr: UInt, trues: Iterable[UInt], falses: Iterable[UInt]): Bool =
apply(addr, BitPat.dontCare(1), trues.map(BitPat(_) -> BitPat("b1")) ++ falses.map(BitPat(_) -> BitPat("b0"))).asBool
}
File Counters.scala:
// See LICENSE.Berkeley for license details.
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util._
// Produces 0-width value when counting to 1
class ZCounter(val n: Int) {
val value = RegInit(0.U(log2Ceil(n).W))
def inc(): Bool = {
if (n == 1) true.B
else {
val wrap = value === (n-1).U
value := Mux(!isPow2(n).B && wrap, 0.U, value + 1.U)
wrap
}
}
}
object ZCounter {
def apply(n: Int) = new ZCounter(n)
def apply(cond: Bool, n: Int): (UInt, Bool) = {
val c = new ZCounter(n)
var wrap: Bool = null
when (cond) { wrap = c.inc() }
(c.value, cond && wrap)
}
}
object TwoWayCounter {
def apply(up: Bool, down: Bool, max: Int): UInt = {
val cnt = RegInit(0.U(log2Up(max + 1).W))
when (up && !down) { cnt := cnt + 1.U }
when (down && !up) { cnt := cnt - 1.U }
cnt
}
}
// a counter that clock gates most of its MSBs using the LSB carry-out
case class WideCounter(width: Int, inc: UInt = 1.U, reset: Boolean = true, inhibit: Bool = false.B) {
private val isWide = width > (2 * inc.getWidth)
private val smallWidth = if (isWide) inc.getWidth max log2Up(width) else width
private val small = if (reset) RegInit(0.U(smallWidth.W)) else Reg(UInt(smallWidth.W))
private val nextSmall = small +& inc
when (!inhibit) { small := nextSmall }
private val large = if (isWide) {
val r = if (reset) RegInit(0.U((width - smallWidth).W)) else Reg(UInt((width - smallWidth).W))
when (nextSmall(smallWidth) && !inhibit) { r := r + 1.U }
r
} else null
val value = if (isWide) Cat(large, small) else small
lazy val carryOut = {
val lo = (small ^ nextSmall) >> 1
if (!isWide)
lo
else {
val hi = Mux(nextSmall(smallWidth), large ^ (large +& 1.U), 0.U) >> 1
Cat(hi, lo)
}
}
def := (x: UInt) = {
small := x
if (isWide) large := x >> smallWidth
}
}
File package.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip
import chisel3._
import chisel3.util._
import scala.math.min
import scala.collection.{immutable, mutable}
package object util {
implicit class UnzippableOption[S, T](val x: Option[(S, T)]) {
def unzip = (x.map(_._1), x.map(_._2))
}
implicit class UIntIsOneOf(private val x: UInt) extends AnyVal {
def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR
def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq)
}
implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal {
/** Like Vec.apply(idx), but tolerates indices of mismatched width */
def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0))
}
implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal {
def apply(idx: UInt): T = {
if (x.size <= 1) {
x.head
} else if (!isPow2(x.size)) {
// For non-power-of-2 seqs, reflect elements to simplify decoder
(x ++ x.takeRight(x.size & -x.size)).toSeq(idx)
} else {
// Ignore MSBs of idx
val truncIdx =
if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx
else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0)
x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) }
}
}
def extract(idx: UInt): T = VecInit(x).extract(idx)
def asUInt: UInt = Cat(x.map(_.asUInt).reverse)
def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n)
def rotate(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n)
def rotateRight(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
}
// allow bitwise ops on Seq[Bool] just like UInt
implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal {
def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b }
def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b }
def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b }
def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x
def >> (n: Int): Seq[Bool] = x drop n
def unary_~ : Seq[Bool] = x.map(!_)
def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_)
def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_)
def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_)
private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B)
}
implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal {
def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable))
def getElements: Seq[Element] = x match {
case e: Element => Seq(e)
case a: Aggregate => a.getElements.flatMap(_.getElements)
}
}
/** Any Data subtype that has a Bool member named valid. */
type DataCanBeValid = Data { val valid: Bool }
implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal {
def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable)
}
implicit class StringToAugmentedString(private val x: String) extends AnyVal {
/** converts from camel case to to underscores, also removing all spaces */
def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") {
case (acc, c) if c.isUpper => acc + "_" + c.toLower
case (acc, c) if c == ' ' => acc
case (acc, c) => acc + c
}
/** converts spaces or underscores to hyphens, also lowering case */
def kebab: String = x.toLowerCase map {
case ' ' => '-'
case '_' => '-'
case c => c
}
def named(name: Option[String]): String = {
x + name.map("_named_" + _ ).getOrElse("_with_no_name")
}
def named(name: String): String = named(Some(name))
}
implicit def uintToBitPat(x: UInt): BitPat = BitPat(x)
implicit def wcToUInt(c: WideCounter): UInt = c.value
implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal {
def sextTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x)
}
def padTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(0.U((n - x.getWidth).W), x)
}
// shifts left by n if n >= 0, or right by -n if n < 0
def << (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << n(w-1, 0)
Mux(n(w), shifted >> (1 << w), shifted)
}
// shifts right by n if n >= 0, or left by -n if n < 0
def >> (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << (1 << w) >> n(w-1, 0)
Mux(n(w), shifted, shifted >> (1 << w))
}
// Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts
def extract(hi: Int, lo: Int): UInt = {
require(hi >= lo-1)
if (hi == lo-1) 0.U
else x(hi, lo)
}
// Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts
def extractOption(hi: Int, lo: Int): Option[UInt] = {
require(hi >= lo-1)
if (hi == lo-1) None
else Some(x(hi, lo))
}
// like x & ~y, but first truncate or zero-extend y to x's width
def andNot(y: UInt): UInt = x & ~(y | (x & 0.U))
def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n)
def rotateRight(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r))
}
}
def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n))
def rotateLeft(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r))
}
}
// compute (this + y) % n, given (this < n) and (y < n)
def addWrap(y: UInt, n: Int): UInt = {
val z = x +& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0)
}
// compute (this - y) % n, given (this < n) and (y < n)
def subWrap(y: UInt, n: Int): UInt = {
val z = x -& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0)
}
def grouped(width: Int): Seq[UInt] =
(0 until x.getWidth by width).map(base => x(base + width - 1, base))
def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds
def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x)
// Like >=, but prevents x-prop for ('x >= 0)
def >== (y: UInt): Bool = x >= y || y === 0.U
}
implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal {
def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y)
def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y)
}
implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal {
def toInt: Int = if (x) 1 else 0
// this one's snagged from scalaz
def option[T](z: => T): Option[T] = if (x) Some(z) else None
}
implicit class IntToAugmentedInt(private val x: Int) extends AnyVal {
// exact log2
def log2: Int = {
require(isPow2(x))
log2Ceil(x)
}
}
def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x)
def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x))
def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0)
def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1)
def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None
// Fill 1s from low bits to high bits
def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth)
def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0))
helper(1, x)(width-1, 0)
}
// Fill 1s form high bits to low bits
def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth)
def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x >> s))
helper(1, x)(width-1, 0)
}
def OptimizationBarrier[T <: Data](in: T): T = {
val barrier = Module(new Module {
val io = IO(new Bundle {
val x = Input(chiselTypeOf(in))
val y = Output(chiselTypeOf(in))
})
io.y := io.x
override def desiredName = s"OptimizationBarrier_${in.typeName}"
})
barrier.io.x := in
barrier.io.y
}
/** Similar to Seq.groupBy except this returns a Seq instead of a Map
* Useful for deterministic code generation
*/
def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = {
val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]]
for (x <- xs) {
val key = f(x)
val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A])
l += x
}
map.view.map({ case (k, vs) => k -> vs.toList }).toList
}
def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match {
case 1 => List.fill(n)(in.head)
case x if x == n => in
case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in")
}
// HeterogeneousBag moved to standalond diplomacy
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts)
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag
}
File PMP.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.rocket
import chisel3._
import chisel3.util.{Cat, log2Ceil}
import org.chipsalliance.cde.config._
import freechips.rocketchip.tile._
import freechips.rocketchip.util._
class PMPConfig extends Bundle {
val l = Bool()
val res = UInt(2.W)
val a = UInt(2.W)
val x = Bool()
val w = Bool()
val r = Bool()
}
object PMP {
def lgAlign = 2
def apply(reg: PMPReg): PMP = {
val pmp = Wire(new PMP()(reg.p))
pmp.cfg := reg.cfg
pmp.addr := reg.addr
pmp.mask := pmp.computeMask
pmp
}
}
class PMPReg(implicit p: Parameters) extends CoreBundle()(p) {
val cfg = new PMPConfig
val addr = UInt((paddrBits - PMP.lgAlign).W)
def reset(): Unit = {
cfg.a := 0.U
cfg.l := 0.U
}
def readAddr = if (pmpGranularity.log2 == PMP.lgAlign) addr else {
val mask = ((BigInt(1) << (pmpGranularity.log2 - PMP.lgAlign)) - 1).U
Mux(napot, addr | (mask >> 1), ~(~addr | mask))
}
def napot = cfg.a(1)
def torNotNAPOT = cfg.a(0)
def tor = !napot && torNotNAPOT
def cfgLocked = cfg.l
def addrLocked(next: PMPReg) = cfgLocked || next.cfgLocked && next.tor
}
class PMP(implicit p: Parameters) extends PMPReg {
val mask = UInt(paddrBits.W)
import PMP._
def computeMask = {
val base = Cat(addr, cfg.a(0)) | ((pmpGranularity - 1).U >> lgAlign)
Cat(base & ~(base + 1.U), ((1 << lgAlign) - 1).U)
}
private def comparand = ~(~(addr << lgAlign) | (pmpGranularity - 1).U)
private def pow2Match(x: UInt, lgSize: UInt, lgMaxSize: Int) = {
def eval(a: UInt, b: UInt, m: UInt) = ((a ^ b) & ~m) === 0.U
if (lgMaxSize <= pmpGranularity.log2) {
eval(x, comparand, mask)
} else {
// break up the circuit; the MSB part will be CSE'd
val lsbMask = mask | UIntToOH1(lgSize, lgMaxSize)
val msbMatch = eval(x >> lgMaxSize, comparand >> lgMaxSize, mask >> lgMaxSize)
val lsbMatch = eval(x(lgMaxSize-1, 0), comparand(lgMaxSize-1, 0), lsbMask(lgMaxSize-1, 0))
msbMatch && lsbMatch
}
}
private def boundMatch(x: UInt, lsbMask: UInt, lgMaxSize: Int) = {
if (lgMaxSize <= pmpGranularity.log2) {
x < comparand
} else {
// break up the circuit; the MSB part will be CSE'd
val msbsLess = (x >> lgMaxSize) < (comparand >> lgMaxSize)
val msbsEqual = ((x >> lgMaxSize) ^ (comparand >> lgMaxSize)) === 0.U
val lsbsLess = (x(lgMaxSize-1, 0) | lsbMask) < comparand(lgMaxSize-1, 0)
msbsLess || (msbsEqual && lsbsLess)
}
}
private def lowerBoundMatch(x: UInt, lgSize: UInt, lgMaxSize: Int) =
!boundMatch(x, UIntToOH1(lgSize, lgMaxSize), lgMaxSize)
private def upperBoundMatch(x: UInt, lgMaxSize: Int) =
boundMatch(x, 0.U, lgMaxSize)
private def rangeMatch(x: UInt, lgSize: UInt, lgMaxSize: Int, prev: PMP) =
prev.lowerBoundMatch(x, lgSize, lgMaxSize) && upperBoundMatch(x, lgMaxSize)
private def pow2Homogeneous(x: UInt, pgLevel: UInt) = {
val maskHomogeneous = pgLevelMap { idxBits => if (idxBits > paddrBits) false.B else mask(idxBits - 1) } (pgLevel)
maskHomogeneous || (pgLevelMap { idxBits => ((x ^ comparand) >> idxBits) =/= 0.U } (pgLevel))
}
private def pgLevelMap[T](f: Int => T) = (0 until pgLevels).map { i =>
f(pgIdxBits + (pgLevels - 1 - i) * pgLevelBits)
}
private def rangeHomogeneous(x: UInt, pgLevel: UInt, prev: PMP) = {
val beginsAfterLower = !(x < prev.comparand)
val beginsAfterUpper = !(x < comparand)
val pgMask = pgLevelMap { idxBits => (((BigInt(1) << paddrBits) - (BigInt(1) << idxBits)) max 0).U } (pgLevel)
val endsBeforeLower = (x & pgMask) < (prev.comparand & pgMask)
val endsBeforeUpper = (x & pgMask) < (comparand & pgMask)
endsBeforeLower || beginsAfterUpper || (beginsAfterLower && endsBeforeUpper)
}
// returns whether this PMP completely contains, or contains none of, a page
def homogeneous(x: UInt, pgLevel: UInt, prev: PMP): Bool =
Mux(napot, pow2Homogeneous(x, pgLevel), !torNotNAPOT || rangeHomogeneous(x, pgLevel, prev))
// returns whether this matching PMP fully contains the access
def aligned(x: UInt, lgSize: UInt, lgMaxSize: Int, prev: PMP): Bool = if (lgMaxSize <= pmpGranularity.log2) true.B else {
val lsbMask = UIntToOH1(lgSize, lgMaxSize)
val straddlesLowerBound = ((x >> lgMaxSize) ^ (prev.comparand >> lgMaxSize)) === 0.U && (prev.comparand(lgMaxSize-1, 0) & ~x(lgMaxSize-1, 0)) =/= 0.U
val straddlesUpperBound = ((x >> lgMaxSize) ^ (comparand >> lgMaxSize)) === 0.U && (comparand(lgMaxSize-1, 0) & (x(lgMaxSize-1, 0) | lsbMask)) =/= 0.U
val rangeAligned = !(straddlesLowerBound || straddlesUpperBound)
val pow2Aligned = (lsbMask & ~mask(lgMaxSize-1, 0)) === 0.U
Mux(napot, pow2Aligned, rangeAligned)
}
// returns whether this PMP matches at least one byte of the access
def hit(x: UInt, lgSize: UInt, lgMaxSize: Int, prev: PMP): Bool =
Mux(napot, pow2Match(x, lgSize, lgMaxSize), torNotNAPOT && rangeMatch(x, lgSize, lgMaxSize, prev))
}
class PMPHomogeneityChecker(pmps: Seq[PMP])(implicit p: Parameters) {
def apply(addr: UInt, pgLevel: UInt): Bool = {
pmps.foldLeft((true.B, 0.U.asTypeOf(new PMP))) { case ((h, prev), pmp) =>
(h && pmp.homogeneous(addr, pgLevel, prev), pmp)
}._1
}
}
class PMPChecker(lgMaxSize: Int)(implicit val p: Parameters) extends Module
with HasCoreParameters {
override def desiredName = s"PMPChecker_s${lgMaxSize}"
val io = IO(new Bundle {
val prv = Input(UInt(PRV.SZ.W))
val pmp = Input(Vec(nPMPs, new PMP))
val addr = Input(UInt(paddrBits.W))
val size = Input(UInt(log2Ceil(lgMaxSize + 1).W))
val r = Output(Bool())
val w = Output(Bool())
val x = Output(Bool())
})
val default = if (io.pmp.isEmpty) true.B else io.prv > PRV.S.U
val pmp0 = WireInit(0.U.asTypeOf(new PMP))
pmp0.cfg.r := default
pmp0.cfg.w := default
pmp0.cfg.x := default
val res = (io.pmp zip (pmp0 +: io.pmp)).reverse.foldLeft(pmp0) { case (prev, (pmp, prevPMP)) =>
val hit = pmp.hit(io.addr, io.size, lgMaxSize, prevPMP)
val ignore = default && !pmp.cfg.l
val aligned = pmp.aligned(io.addr, io.size, lgMaxSize, prevPMP)
for ((name, idx) <- Seq("no", "TOR", if (pmpGranularity <= 4) "NA4" else "", "NAPOT").zipWithIndex; if name.nonEmpty)
property.cover(pmp.cfg.a === idx.U, s"The cfg access is set to ${name} access ", "Cover PMP access mode setting")
property.cover(pmp.cfg.l === 0x1.U, s"The cfg lock is set to high ", "Cover PMP lock mode setting")
// Not including Write and no Read permission as the combination is reserved
for ((name, idx) <- Seq("no", "RO", "", "RW", "X", "RX", "", "RWX").zipWithIndex; if name.nonEmpty)
property.cover((Cat(pmp.cfg.x, pmp.cfg.w, pmp.cfg.r) === idx.U), s"The permission is set to ${name} access ", "Cover PMP access permission setting")
for ((name, idx) <- Seq("", "TOR", if (pmpGranularity <= 4) "NA4" else "", "NAPOT").zipWithIndex; if name.nonEmpty) {
property.cover(!ignore && hit && aligned && pmp.cfg.a === idx.U, s"The access matches ${name} mode ", "Cover PMP access")
property.cover(pmp.cfg.l && hit && aligned && pmp.cfg.a === idx.U, s"The access matches ${name} mode with lock bit high", "Cover PMP access with lock bit")
}
val cur = WireInit(pmp)
cur.cfg.r := aligned && (pmp.cfg.r || ignore)
cur.cfg.w := aligned && (pmp.cfg.w || ignore)
cur.cfg.x := aligned && (pmp.cfg.x || ignore)
Mux(hit, cur, prev)
}
io.r := res.cfg.r
io.w := res.cfg.w
io.x := res.cfg.x
}
File CSR.scala:
// See LICENSE.SiFive for license details.
// See LICENSE.Berkeley for license details.
package freechips.rocketchip.rocket
import chisel3._
import chisel3.util.{BitPat, Cat, Fill, Mux1H, PopCount, PriorityMux, RegEnable, UIntToOH, Valid, log2Ceil, log2Up}
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.devices.debug.DebugModuleKey
import freechips.rocketchip.tile._
import freechips.rocketchip.util._
import freechips.rocketchip.util.property
import scala.collection.mutable.LinkedHashMap
import Instructions._
import CustomInstructions._
class MStatus extends Bundle {
// not truly part of mstatus, but convenient
val debug = Bool()
val cease = Bool()
val wfi = Bool()
val isa = UInt(32.W)
val dprv = UInt(PRV.SZ.W) // effective prv for data accesses
val dv = Bool() // effective v for data accesses
val prv = UInt(PRV.SZ.W)
val v = Bool()
val sd = Bool()
val zero2 = UInt(23.W)
val mpv = Bool()
val gva = Bool()
val mbe = Bool()
val sbe = Bool()
val sxl = UInt(2.W)
val uxl = UInt(2.W)
val sd_rv32 = Bool()
val zero1 = UInt(8.W)
val tsr = Bool()
val tw = Bool()
val tvm = Bool()
val mxr = Bool()
val sum = Bool()
val mprv = Bool()
val xs = UInt(2.W)
val fs = UInt(2.W)
val mpp = UInt(2.W)
val vs = UInt(2.W)
val spp = UInt(1.W)
val mpie = Bool()
val ube = Bool()
val spie = Bool()
val upie = Bool()
val mie = Bool()
val hie = Bool()
val sie = Bool()
val uie = Bool()
}
class MNStatus extends Bundle {
val mpp = UInt(2.W)
val zero3 = UInt(3.W)
val mpv = Bool()
val zero2 = UInt(3.W)
val mie = Bool()
val zero1 = UInt(3.W)
}
class HStatus extends Bundle {
val zero6 = UInt(30.W)
val vsxl = UInt(2.W)
val zero5 = UInt(9.W)
val vtsr = Bool()
val vtw = Bool()
val vtvm = Bool()
val zero3 = UInt(2.W)
val vgein = UInt(6.W)
val zero2 = UInt(2.W)
val hu = Bool()
val spvp = Bool()
val spv = Bool()
val gva = Bool()
val vsbe = Bool()
val zero1 = UInt(5.W)
}
class DCSR extends Bundle {
val xdebugver = UInt(2.W)
val zero4 = UInt(2.W)
val zero3 = UInt(12.W)
val ebreakm = Bool()
val ebreakh = Bool()
val ebreaks = Bool()
val ebreaku = Bool()
val zero2 = Bool()
val stopcycle = Bool()
val stoptime = Bool()
val cause = UInt(3.W)
val v = Bool()
val zero1 = UInt(2.W)
val step = Bool()
val prv = UInt(PRV.SZ.W)
}
class MIP(implicit p: Parameters) extends CoreBundle()(p)
with HasCoreParameters {
val lip = Vec(coreParams.nLocalInterrupts, Bool())
val zero1 = Bool()
val debug = Bool() // keep in sync with CSR.debugIntCause
val rocc = Bool()
val sgeip = Bool()
val meip = Bool()
val vseip = Bool()
val seip = Bool()
val ueip = Bool()
val mtip = Bool()
val vstip = Bool()
val stip = Bool()
val utip = Bool()
val msip = Bool()
val vssip = Bool()
val ssip = Bool()
val usip = Bool()
}
class Envcfg extends Bundle {
val stce = Bool() // only for menvcfg/henvcfg
val pbmte = Bool() // only for menvcfg/henvcfg
val zero54 = UInt(54.W)
val cbze = Bool()
val cbcfe = Bool()
val cbie = UInt(2.W)
val zero3 = UInt(3.W)
val fiom = Bool()
def write(wdata: UInt) {
val new_envcfg = wdata.asTypeOf(new Envcfg)
fiom := new_envcfg.fiom // only FIOM is writable currently
}
}
class PTBR(implicit p: Parameters) extends CoreBundle()(p) {
def additionalPgLevels = mode.extract(log2Ceil(pgLevels-minPgLevels+1)-1, 0)
def pgLevelsToMode(i: Int) = (xLen, i) match {
case (32, 2) => 1
case (64, x) if x >= 3 && x <= 6 => x + 5
}
val (modeBits, maxASIdBits) = xLen match {
case 32 => (1, 9)
case 64 => (4, 16)
}
require(modeBits + maxASIdBits + maxPAddrBits - pgIdxBits == xLen)
val mode = UInt(modeBits.W)
val asid = UInt(maxASIdBits.W)
val ppn = UInt((maxPAddrBits - pgIdxBits).W)
}
object PRV
{
val SZ = 2
val U = 0
val S = 1
val H = 2
val M = 3
}
object CSR
{
// commands
val SZ = 3
def X = BitPat.dontCare(SZ)
def N = 0.U(SZ.W)
def R = 2.U(SZ.W)
def I = 4.U(SZ.W)
def W = 5.U(SZ.W)
def S = 6.U(SZ.W)
def C = 7.U(SZ.W)
// mask a CSR cmd with a valid bit
def maskCmd(valid: Bool, cmd: UInt): UInt = {
// all commands less than CSR.I are treated by CSRFile as NOPs
cmd & ~Mux(valid, 0.U, CSR.I)
}
val ADDRSZ = 12
def modeLSB: Int = 8
def mode(addr: Int): Int = (addr >> modeLSB) % (1 << PRV.SZ)
def mode(addr: UInt): UInt = addr(modeLSB + PRV.SZ - 1, modeLSB)
def busErrorIntCause = 128
def debugIntCause = 14 // keep in sync with MIP.debug
def debugTriggerCause = {
val res = debugIntCause
require(!(Causes.all contains res))
res
}
def rnmiIntCause = 13 // NMI: Higher numbers = higher priority, must not reuse debugIntCause
def rnmiBEUCause = 12
val firstCtr = CSRs.cycle
val firstCtrH = CSRs.cycleh
val firstHPC = CSRs.hpmcounter3
val firstHPCH = CSRs.hpmcounter3h
val firstHPE = CSRs.mhpmevent3
val firstMHPC = CSRs.mhpmcounter3
val firstMHPCH = CSRs.mhpmcounter3h
val firstHPM = 3
val nCtr = 32
val nHPM = nCtr - firstHPM
val hpmWidth = 40
val maxPMPs = 16
}
class PerfCounterIO(implicit p: Parameters) extends CoreBundle
with HasCoreParameters {
val eventSel = Output(UInt(xLen.W))
val inc = Input(UInt(log2Ceil(1+retireWidth).W))
}
class TracedInstruction(implicit p: Parameters) extends CoreBundle {
val valid = Bool()
val iaddr = UInt(coreMaxAddrBits.W)
val insn = UInt(iLen.W)
val priv = UInt(3.W)
val exception = Bool()
val interrupt = Bool()
val cause = UInt(xLen.W)
val tval = UInt((coreMaxAddrBits max iLen).W)
val wdata = Option.when(traceHasWdata)(UInt((vLen max xLen).W))
}
class TraceAux extends Bundle {
val enable = Bool()
val stall = Bool()
}
class CSRDecodeIO(implicit p: Parameters) extends CoreBundle {
val inst = Input(UInt(iLen.W))
def csr_addr = (inst >> 20)(CSR.ADDRSZ-1, 0)
val fp_illegal = Output(Bool())
val vector_illegal = Output(Bool())
val fp_csr = Output(Bool())
val vector_csr = Output(Bool())
val rocc_illegal = Output(Bool())
val read_illegal = Output(Bool())
val write_illegal = Output(Bool())
val write_flush = Output(Bool())
val system_illegal = Output(Bool())
val virtual_access_illegal = Output(Bool())
val virtual_system_illegal = Output(Bool())
}
class CSRFileIO(hasBeu: Boolean)(implicit p: Parameters) extends CoreBundle
with HasCoreParameters {
val ungated_clock = Input(Clock())
val interrupts = Input(new CoreInterrupts(hasBeu))
val hartid = Input(UInt(hartIdLen.W))
val rw = new Bundle {
val addr = Input(UInt(CSR.ADDRSZ.W))
val cmd = Input(Bits(CSR.SZ.W))
val rdata = Output(Bits(xLen.W))
val wdata = Input(Bits(xLen.W))
}
val decode = Vec(decodeWidth, new CSRDecodeIO)
val csr_stall = Output(Bool()) // stall retire for wfi
val rw_stall = Output(Bool()) // stall rw, rw will have no effect while rw_stall
val eret = Output(Bool())
val singleStep = Output(Bool())
val status = Output(new MStatus())
val hstatus = Output(new HStatus())
val gstatus = Output(new MStatus())
val ptbr = Output(new PTBR())
val hgatp = Output(new PTBR())
val vsatp = Output(new PTBR())
val evec = Output(UInt(vaddrBitsExtended.W))
val exception = Input(Bool())
val retire = Input(UInt(log2Up(1+retireWidth).W))
val cause = Input(UInt(xLen.W))
val pc = Input(UInt(vaddrBitsExtended.W))
val tval = Input(UInt(vaddrBitsExtended.W))
val htval = Input(UInt(((maxSVAddrBits + 1) min xLen).W))
val mhtinst_read_pseudo = Input(Bool())
val gva = Input(Bool())
val time = Output(UInt(xLen.W))
val fcsr_rm = Output(Bits(FPConstants.RM_SZ.W))
val fcsr_flags = Flipped(Valid(Bits(FPConstants.FLAGS_SZ.W)))
val set_fs_dirty = coreParams.haveFSDirty.option(Input(Bool()))
val rocc_interrupt = Input(Bool())
val interrupt = Output(Bool())
val interrupt_cause = Output(UInt(xLen.W))
val bp = Output(Vec(nBreakpoints, new BP))
val pmp = Output(Vec(nPMPs, new PMP))
val counters = Vec(nPerfCounters, new PerfCounterIO)
val csrw_counter = Output(UInt(CSR.nCtr.W))
val inhibit_cycle = Output(Bool())
val inst = Input(Vec(retireWidth, UInt(iLen.W)))
val trace = Output(Vec(retireWidth, new TracedInstruction))
val mcontext = Output(UInt(coreParams.mcontextWidth.W))
val scontext = Output(UInt(coreParams.scontextWidth.W))
val fiom = Output(Bool())
val vector = usingVector.option(new Bundle {
val vconfig = Output(new VConfig())
val vstart = Output(UInt(maxVLMax.log2.W))
val vxrm = Output(UInt(2.W))
val set_vs_dirty = Input(Bool())
val set_vconfig = Flipped(Valid(new VConfig))
val set_vstart = Flipped(Valid(vstart))
val set_vxsat = Input(Bool())
})
}
class VConfig(implicit p: Parameters) extends CoreBundle {
val vl = UInt((maxVLMax.log2 + 1).W)
val vtype = new VType
}
object VType {
def fromUInt(that: UInt, ignore_vill: Boolean = false)(implicit p: Parameters): VType = {
val res = 0.U.asTypeOf(new VType)
val in = that.asTypeOf(res)
val vill = (in.max_vsew.U < in.vsew) || !in.lmul_ok || in.reserved =/= 0.U || in.vill
when (!vill || ignore_vill.B) {
res := in
res.vsew := in.vsew(log2Ceil(1 + in.max_vsew) - 1, 0)
}
res.reserved := 0.U
res.vill := vill
res
}
def computeVL(avl: UInt, vtype: UInt, currentVL: UInt, useCurrentVL: Bool, useMax: Bool, useZero: Bool)(implicit p: Parameters): UInt =
VType.fromUInt(vtype, true).vl(avl, currentVL, useCurrentVL, useMax, useZero)
}
class VType(implicit p: Parameters) extends CoreBundle {
val vill = Bool()
val reserved = UInt((xLen - 9).W)
val vma = Bool()
val vta = Bool()
val vsew = UInt(3.W)
val vlmul_sign = Bool()
val vlmul_mag = UInt(2.W)
def vlmul_signed: SInt = Cat(vlmul_sign, vlmul_mag).asSInt
@deprecated("use vlmul_sign, vlmul_mag, or vlmul_signed", "RVV 0.9")
def vlmul: UInt = vlmul_mag
def max_vsew = log2Ceil(eLen/8)
def max_vlmul = (1 << vlmul_mag.getWidth) - 1
def lmul_ok: Bool = Mux(this.vlmul_sign, this.vlmul_mag =/= 0.U && ~this.vlmul_mag < max_vsew.U - this.vsew, true.B)
def minVLMax: Int = ((maxVLMax / eLen) >> ((1 << vlmul_mag.getWidth) - 1)) max 1
def vlMax: UInt = (maxVLMax.U >> (this.vsew +& Cat(this.vlmul_sign, ~this.vlmul_mag))).andNot((minVLMax-1).U)
def vl(avl: UInt, currentVL: UInt, useCurrentVL: Bool, useMax: Bool, useZero: Bool): UInt = {
val atLeastMaxVLMax = useMax || Mux(useCurrentVL, currentVL >= maxVLMax.U, avl >= maxVLMax.U)
val avl_lsbs = Mux(useCurrentVL, currentVL, avl)(maxVLMax.log2 - 1, 0)
val atLeastVLMax = atLeastMaxVLMax || (avl_lsbs & (-maxVLMax.S >> (this.vsew +& Cat(this.vlmul_sign, ~this.vlmul_mag))).asUInt.andNot((minVLMax-1).U)).orR
val isZero = vill || useZero
Mux(!isZero && atLeastVLMax, vlMax, 0.U) | Mux(!isZero && !atLeastVLMax, avl_lsbs, 0.U)
}
}
class CSRFile(
perfEventSets: EventSets = new EventSets(Seq()),
customCSRs: Seq[CustomCSR] = Nil,
roccCSRs: Seq[CustomCSR] = Nil,
hasBeu: Boolean = false)(implicit p: Parameters)
extends CoreModule()(p)
with HasCoreParameters {
val io = IO(new CSRFileIO(hasBeu) {
val customCSRs = Vec(CSRFile.this.customCSRs.size, new CustomCSRIO)
val roccCSRs = Vec(CSRFile.this.roccCSRs.size, new CustomCSRIO)
})
io.rw_stall := false.B
val reset_mstatus = WireDefault(0.U.asTypeOf(new MStatus()))
reset_mstatus.mpp := PRV.M.U
reset_mstatus.prv := PRV.M.U
reset_mstatus.xs := (if (usingRoCC) 3.U else 0.U)
val reg_mstatus = RegInit(reset_mstatus)
val new_prv = WireDefault(reg_mstatus.prv)
reg_mstatus.prv := legalizePrivilege(new_prv)
val reset_dcsr = WireDefault(0.U.asTypeOf(new DCSR()))
reset_dcsr.xdebugver := 1.U
reset_dcsr.prv := PRV.M.U
val reg_dcsr = RegInit(reset_dcsr)
val (supported_interrupts, delegable_interrupts) = {
val sup = Wire(new MIP)
sup.usip := false.B
sup.ssip := usingSupervisor.B
sup.vssip := usingHypervisor.B
sup.msip := true.B
sup.utip := false.B
sup.stip := usingSupervisor.B
sup.vstip := usingHypervisor.B
sup.mtip := true.B
sup.ueip := false.B
sup.seip := usingSupervisor.B
sup.vseip := usingHypervisor.B
sup.meip := true.B
sup.sgeip := false.B
sup.rocc := usingRoCC.B
sup.debug := false.B
sup.zero1 := false.B
sup.lip foreach { _ := true.B }
val supported_high_interrupts = if (io.interrupts.buserror.nonEmpty && !usingNMI) (BigInt(1) << CSR.busErrorIntCause).U else 0.U
val del = WireDefault(sup)
del.msip := false.B
del.mtip := false.B
del.meip := false.B
(sup.asUInt | supported_high_interrupts, del.asUInt)
}
val delegable_base_exceptions = Seq(
Causes.misaligned_fetch,
Causes.fetch_page_fault,
Causes.breakpoint,
Causes.load_page_fault,
Causes.store_page_fault,
Causes.misaligned_load,
Causes.misaligned_store,
Causes.illegal_instruction,
Causes.user_ecall,
)
val delegable_hypervisor_exceptions = Seq(
Causes.virtual_supervisor_ecall,
Causes.fetch_guest_page_fault,
Causes.load_guest_page_fault,
Causes.virtual_instruction,
Causes.store_guest_page_fault,
)
val delegable_exceptions = (
delegable_base_exceptions
++ (if (usingHypervisor) delegable_hypervisor_exceptions else Seq())
).map(1 << _).sum.U
val hs_delegable_exceptions = Seq(
Causes.misaligned_fetch,
Causes.fetch_access,
Causes.illegal_instruction,
Causes.breakpoint,
Causes.misaligned_load,
Causes.load_access,
Causes.misaligned_store,
Causes.store_access,
Causes.user_ecall,
Causes.fetch_page_fault,
Causes.load_page_fault,
Causes.store_page_fault).map(1 << _).sum.U
val (hs_delegable_interrupts, mideleg_always_hs) = {
val always = WireDefault(0.U.asTypeOf(new MIP()))
always.vssip := usingHypervisor.B
always.vstip := usingHypervisor.B
always.vseip := usingHypervisor.B
val deleg = WireDefault(always)
deleg.lip.foreach { _ := usingHypervisor.B }
(deleg.asUInt, always.asUInt)
}
val reg_debug = RegInit(false.B)
val reg_dpc = Reg(UInt(vaddrBitsExtended.W))
val reg_dscratch0 = Reg(UInt(xLen.W))
val reg_dscratch1 = (p(DebugModuleKey).map(_.nDscratch).getOrElse(1) > 1).option(Reg(UInt(xLen.W)))
val reg_singleStepped = Reg(Bool())
val reg_mcontext = (coreParams.mcontextWidth > 0).option(RegInit(0.U(coreParams.mcontextWidth.W)))
val reg_scontext = (coreParams.scontextWidth > 0).option(RegInit(0.U(coreParams.scontextWidth.W)))
val reg_tselect = Reg(UInt(log2Up(nBreakpoints).W))
val reg_bp = Reg(Vec(1 << log2Up(nBreakpoints), new BP))
val reg_pmp = Reg(Vec(nPMPs, new PMPReg))
val reg_mie = Reg(UInt(xLen.W))
val (reg_mideleg, read_mideleg) = {
val reg = Reg(UInt(xLen.W))
(reg, Mux(usingSupervisor.B, reg & delegable_interrupts | mideleg_always_hs, 0.U))
}
val (reg_medeleg, read_medeleg) = {
val reg = Reg(UInt(xLen.W))
(reg, Mux(usingSupervisor.B, reg & delegable_exceptions, 0.U))
}
val reg_mip = Reg(new MIP)
val reg_mepc = Reg(UInt(vaddrBitsExtended.W))
val reg_mcause = RegInit(0.U(xLen.W))
val reg_mtval = Reg(UInt(vaddrBitsExtended.W))
val reg_mtval2 = Reg(UInt(((maxSVAddrBits + 1) min xLen).W))
val reg_mscratch = Reg(Bits(xLen.W))
val mtvecWidth = paddrBits min xLen
val reg_mtvec = mtvecInit match {
case Some(addr) => RegInit(addr.U(mtvecWidth.W))
case None => Reg(UInt(mtvecWidth.W))
}
val reset_mnstatus = WireDefault(0.U.asTypeOf(new MNStatus()))
reset_mnstatus.mpp := PRV.M.U
val reg_mnscratch = Reg(Bits(xLen.W))
val reg_mnepc = Reg(UInt(vaddrBitsExtended.W))
val reg_mncause = RegInit(0.U(xLen.W))
val reg_mnstatus = RegInit(reset_mnstatus)
val reg_rnmie = RegInit(true.B)
val nmie = reg_rnmie
val reg_menvcfg = RegInit(0.U.asTypeOf(new Envcfg))
val reg_senvcfg = RegInit(0.U.asTypeOf(new Envcfg))
val reg_henvcfg = RegInit(0.U.asTypeOf(new Envcfg))
val delegable_counters = ((BigInt(1) << (nPerfCounters + CSR.firstHPM)) - 1).U
val (reg_mcounteren, read_mcounteren) = {
val reg = Reg(UInt(32.W))
(reg, Mux(usingUser.B, reg & delegable_counters, 0.U))
}
val (reg_scounteren, read_scounteren) = {
val reg = Reg(UInt(32.W))
(reg, Mux(usingSupervisor.B, reg & delegable_counters, 0.U))
}
val (reg_hideleg, read_hideleg) = {
val reg = Reg(UInt(xLen.W))
(reg, Mux(usingHypervisor.B, reg & hs_delegable_interrupts, 0.U))
}
val (reg_hedeleg, read_hedeleg) = {
val reg = Reg(UInt(xLen.W))
(reg, Mux(usingHypervisor.B, reg & hs_delegable_exceptions, 0.U))
}
val hs_delegable_counters = delegable_counters
val (reg_hcounteren, read_hcounteren) = {
val reg = Reg(UInt(32.W))
(reg, Mux(usingHypervisor.B, reg & hs_delegable_counters, 0.U))
}
val reg_hstatus = RegInit(0.U.asTypeOf(new HStatus))
val reg_hgatp = Reg(new PTBR)
val reg_htval = Reg(reg_mtval2.cloneType)
val read_hvip = reg_mip.asUInt & hs_delegable_interrupts
val read_hie = reg_mie & hs_delegable_interrupts
val (reg_vstvec, read_vstvec) = {
val reg = Reg(UInt(vaddrBitsExtended.W))
(reg, formTVec(reg).sextTo(xLen))
}
val reg_vsstatus = Reg(new MStatus)
val reg_vsscratch = Reg(Bits(xLen.W))
val reg_vsepc = Reg(UInt(vaddrBitsExtended.W))
val reg_vscause = Reg(Bits(xLen.W))
val reg_vstval = Reg(UInt(vaddrBitsExtended.W))
val reg_vsatp = Reg(new PTBR)
val reg_sepc = Reg(UInt(vaddrBitsExtended.W))
val reg_scause = Reg(Bits(xLen.W))
val reg_stval = Reg(UInt(vaddrBitsExtended.W))
val reg_sscratch = Reg(Bits(xLen.W))
val reg_stvec = Reg(UInt((if (usingHypervisor) vaddrBitsExtended else vaddrBits).W))
val reg_satp = Reg(new PTBR)
val reg_wfi = withClock(io.ungated_clock) { RegInit(false.B) }
val reg_fflags = Reg(UInt(5.W))
val reg_frm = Reg(UInt(3.W))
val reg_vconfig = usingVector.option(Reg(new VConfig))
val reg_vstart = usingVector.option(Reg(UInt(maxVLMax.log2.W)))
val reg_vxsat = usingVector.option(Reg(Bool()))
val reg_vxrm = usingVector.option(Reg(UInt(io.vector.get.vxrm.getWidth.W)))
val reg_mtinst_read_pseudo = Reg(Bool())
val reg_htinst_read_pseudo = Reg(Bool())
// XLEN=32: 0x00002000
// XLEN=64: 0x00003000
val Seq(read_mtinst, read_htinst) = Seq(reg_mtinst_read_pseudo, reg_htinst_read_pseudo).map(r => Cat(r, (xLen == 32).option(0.U).getOrElse(r), 0.U(12.W)))
val reg_mcountinhibit = RegInit(0.U((CSR.firstHPM + nPerfCounters).W))
io.inhibit_cycle := reg_mcountinhibit(0)
val reg_instret = WideCounter(64, io.retire, inhibit = reg_mcountinhibit(2))
val reg_cycle = if (enableCommitLog) WideCounter(64, io.retire, inhibit = reg_mcountinhibit(0))
else withClock(io.ungated_clock) { WideCounter(64, !io.csr_stall, inhibit = reg_mcountinhibit(0)) }
val reg_hpmevent = io.counters.map(c => RegInit(0.U(xLen.W)))
(io.counters zip reg_hpmevent) foreach { case (c, e) => c.eventSel := e }
val reg_hpmcounter = io.counters.zipWithIndex.map { case (c, i) =>
WideCounter(CSR.hpmWidth, c.inc, reset = false, inhibit = reg_mcountinhibit(CSR.firstHPM+i)) }
val mip = WireDefault(reg_mip)
mip.lip := (io.interrupts.lip: Seq[Bool])
mip.mtip := io.interrupts.mtip
mip.msip := io.interrupts.msip
mip.meip := io.interrupts.meip
// seip is the OR of reg_mip.seip and the actual line from the PLIC
io.interrupts.seip.foreach { mip.seip := reg_mip.seip || _ }
// Simimlar sort of thing would apply if the PLIC had a VSEIP line:
//io.interrupts.vseip.foreach { mip.vseip := reg_mip.vseip || _ }
mip.rocc := io.rocc_interrupt
val read_mip = mip.asUInt & supported_interrupts
val read_hip = read_mip & hs_delegable_interrupts
val high_interrupts = (if (usingNMI) 0.U else io.interrupts.buserror.map(_ << CSR.busErrorIntCause).getOrElse(0.U))
val pending_interrupts = high_interrupts | (read_mip & reg_mie)
val d_interrupts = io.interrupts.debug << CSR.debugIntCause
val (nmi_interrupts, nmiFlag) = io.interrupts.nmi.map(nmi =>
(((nmi.rnmi && reg_rnmie) << CSR.rnmiIntCause) |
io.interrupts.buserror.map(_ << CSR.rnmiBEUCause).getOrElse(0.U),
!io.interrupts.debug && nmi.rnmi && reg_rnmie)).getOrElse(0.U, false.B)
val m_interrupts = Mux(nmie && (reg_mstatus.prv <= PRV.S.U || reg_mstatus.mie), ~(~pending_interrupts | read_mideleg), 0.U)
val s_interrupts = Mux(nmie && (reg_mstatus.v || reg_mstatus.prv < PRV.S.U || (reg_mstatus.prv === PRV.S.U && reg_mstatus.sie)), pending_interrupts & read_mideleg & ~read_hideleg, 0.U)
val vs_interrupts = Mux(nmie && (reg_mstatus.v && (reg_mstatus.prv < PRV.S.U || reg_mstatus.prv === PRV.S.U && reg_vsstatus.sie)), pending_interrupts & read_hideleg, 0.U)
val (anyInterrupt, whichInterrupt) = chooseInterrupt(Seq(vs_interrupts, s_interrupts, m_interrupts, nmi_interrupts, d_interrupts))
val interruptMSB = BigInt(1) << (xLen-1)
val interruptCause = interruptMSB.U + (nmiFlag << (xLen-2)) + whichInterrupt
io.interrupt := (anyInterrupt && !io.singleStep || reg_singleStepped) && !(reg_debug || io.status.cease)
io.interrupt_cause := interruptCause
io.bp := reg_bp take nBreakpoints
io.mcontext := reg_mcontext.getOrElse(0.U)
io.scontext := reg_scontext.getOrElse(0.U)
io.fiom := (reg_mstatus.prv < PRV.M.U && reg_menvcfg.fiom) || (reg_mstatus.prv < PRV.S.U && reg_senvcfg.fiom) || (reg_mstatus.v && reg_henvcfg.fiom)
io.pmp := reg_pmp.map(PMP(_))
val isaMaskString =
(if (usingMulDiv) "M" else "") +
(if (usingAtomics) "A" else "") +
(if (fLen >= 32) "F" else "") +
(if (fLen >= 64) "D" else "") +
(if (coreParams.hasV) "V" else "") +
(if (usingCompressed) "C" else "")
val isaString = (if (coreParams.useRVE) "E" else "I") +
isaMaskString +
(if (customIsaExt.isDefined || usingRoCC) "X" else "") +
(if (usingSupervisor) "S" else "") +
(if (usingHypervisor) "H" else "") +
(if (usingUser) "U" else "")
val isaMax = (BigInt(log2Ceil(xLen) - 4) << (xLen-2)) | isaStringToMask(isaString)
val reg_misa = RegInit(isaMax.U)
val read_mstatus = io.status.asUInt.extract(xLen-1,0)
val read_mtvec = formTVec(reg_mtvec).padTo(xLen)
val read_stvec = formTVec(reg_stvec).sextTo(xLen)
val read_mapping = LinkedHashMap[Int,Bits](
CSRs.tselect -> reg_tselect,
CSRs.tdata1 -> reg_bp(reg_tselect).control.asUInt,
CSRs.tdata2 -> reg_bp(reg_tselect).address.sextTo(xLen),
CSRs.tdata3 -> reg_bp(reg_tselect).textra.asUInt,
CSRs.misa -> reg_misa,
CSRs.mstatus -> read_mstatus,
CSRs.mtvec -> read_mtvec,
CSRs.mip -> read_mip,
CSRs.mie -> reg_mie,
CSRs.mscratch -> reg_mscratch,
CSRs.mepc -> readEPC(reg_mepc).sextTo(xLen),
CSRs.mtval -> reg_mtval.sextTo(xLen),
CSRs.mcause -> reg_mcause,
CSRs.mhartid -> io.hartid)
val debug_csrs = if (!usingDebug) LinkedHashMap() else LinkedHashMap[Int,Bits](
CSRs.dcsr -> reg_dcsr.asUInt,
CSRs.dpc -> readEPC(reg_dpc).sextTo(xLen),
CSRs.dscratch0 -> reg_dscratch0.asUInt) ++
reg_dscratch1.map(r => CSRs.dscratch1 -> r)
val read_mnstatus = WireInit(0.U.asTypeOf(new MNStatus()))
read_mnstatus.mpp := reg_mnstatus.mpp
read_mnstatus.mpv := reg_mnstatus.mpv
read_mnstatus.mie := reg_rnmie
val nmi_csrs = if (!usingNMI) LinkedHashMap() else LinkedHashMap[Int,Bits](
CustomCSRs.mnscratch -> reg_mnscratch,
CustomCSRs.mnepc -> readEPC(reg_mnepc).sextTo(xLen),
CustomCSRs.mncause -> reg_mncause,
CustomCSRs.mnstatus -> read_mnstatus.asUInt)
val context_csrs = LinkedHashMap[Int,Bits]() ++
reg_mcontext.map(r => CSRs.mcontext -> r) ++
reg_scontext.map(r => CSRs.scontext -> r)
val read_fcsr = Cat(reg_frm, reg_fflags)
val fp_csrs = LinkedHashMap[Int,Bits]() ++
usingFPU.option(CSRs.fflags -> reg_fflags) ++
usingFPU.option(CSRs.frm -> reg_frm) ++
(usingFPU || usingVector).option(CSRs.fcsr -> read_fcsr)
val read_vcsr = Cat(reg_vxrm.getOrElse(0.U), reg_vxsat.getOrElse(0.U))
val vector_csrs = if (!usingVector) LinkedHashMap() else LinkedHashMap[Int,Bits](
CSRs.vxsat -> reg_vxsat.get,
CSRs.vxrm -> reg_vxrm.get,
CSRs.vcsr -> read_vcsr,
CSRs.vstart -> reg_vstart.get,
CSRs.vtype -> reg_vconfig.get.vtype.asUInt,
CSRs.vl -> reg_vconfig.get.vl,
CSRs.vlenb -> (vLen / 8).U)
read_mapping ++= debug_csrs
read_mapping ++= nmi_csrs
read_mapping ++= context_csrs
read_mapping ++= fp_csrs
read_mapping ++= vector_csrs
if (coreParams.haveBasicCounters) {
read_mapping += CSRs.mcountinhibit -> reg_mcountinhibit
read_mapping += CSRs.mcycle -> reg_cycle
read_mapping += CSRs.minstret -> reg_instret
for (((e, c), i) <- (reg_hpmevent.padTo(CSR.nHPM, 0.U)
zip reg_hpmcounter.map(x => x: UInt).padTo(CSR.nHPM, 0.U)).zipWithIndex) {
read_mapping += (i + CSR.firstHPE) -> e // mhpmeventN
read_mapping += (i + CSR.firstMHPC) -> c // mhpmcounterN
read_mapping += (i + CSR.firstHPC) -> c // hpmcounterN
if (xLen == 32) {
read_mapping += (i + CSR.firstMHPCH) -> (c >> 32) // mhpmcounterNh
read_mapping += (i + CSR.firstHPCH) -> (c >> 32) // hpmcounterNh
}
}
if (usingUser) {
read_mapping += CSRs.mcounteren -> read_mcounteren
}
read_mapping += CSRs.cycle -> reg_cycle
read_mapping += CSRs.instret -> reg_instret
if (xLen == 32) {
read_mapping += CSRs.mcycleh -> (reg_cycle >> 32)
read_mapping += CSRs.minstreth -> (reg_instret >> 32)
read_mapping += CSRs.cycleh -> (reg_cycle >> 32)
read_mapping += CSRs.instreth -> (reg_instret >> 32)
}
}
if (usingUser) {
read_mapping += CSRs.menvcfg -> reg_menvcfg.asUInt
if (xLen == 32)
read_mapping += CSRs.menvcfgh -> (reg_menvcfg.asUInt >> 32)
}
val sie_mask = {
val sgeip_mask = WireInit(0.U.asTypeOf(new MIP))
sgeip_mask.sgeip := true.B
read_mideleg & ~(hs_delegable_interrupts | sgeip_mask.asUInt)
}
if (usingSupervisor) {
val read_sie = reg_mie & sie_mask
val read_sip = read_mip & sie_mask
val read_sstatus = WireDefault(0.U.asTypeOf(new MStatus))
read_sstatus.sd := io.status.sd
read_sstatus.uxl := io.status.uxl
read_sstatus.sd_rv32 := io.status.sd_rv32
read_sstatus.mxr := io.status.mxr
read_sstatus.sum := io.status.sum
read_sstatus.xs := io.status.xs
read_sstatus.fs := io.status.fs
read_sstatus.vs := io.status.vs
read_sstatus.spp := io.status.spp
read_sstatus.spie := io.status.spie
read_sstatus.sie := io.status.sie
read_mapping += CSRs.sstatus -> (read_sstatus.asUInt)(xLen-1,0)
read_mapping += CSRs.sip -> read_sip.asUInt
read_mapping += CSRs.sie -> read_sie.asUInt
read_mapping += CSRs.sscratch -> reg_sscratch
read_mapping += CSRs.scause -> reg_scause
read_mapping += CSRs.stval -> reg_stval.sextTo(xLen)
read_mapping += CSRs.satp -> reg_satp.asUInt
read_mapping += CSRs.sepc -> readEPC(reg_sepc).sextTo(xLen)
read_mapping += CSRs.stvec -> read_stvec
read_mapping += CSRs.scounteren -> read_scounteren
read_mapping += CSRs.mideleg -> read_mideleg
read_mapping += CSRs.medeleg -> read_medeleg
read_mapping += CSRs.senvcfg -> reg_senvcfg.asUInt
}
val pmpCfgPerCSR = xLen / new PMPConfig().getWidth
def pmpCfgIndex(i: Int) = (xLen / 32) * (i / pmpCfgPerCSR)
if (reg_pmp.nonEmpty) {
require(reg_pmp.size <= CSR.maxPMPs)
val read_pmp = reg_pmp.padTo(CSR.maxPMPs, 0.U.asTypeOf(new PMP))
for (i <- 0 until read_pmp.size by pmpCfgPerCSR)
read_mapping += (CSRs.pmpcfg0 + pmpCfgIndex(i)) -> read_pmp.map(_.cfg).slice(i, i + pmpCfgPerCSR).asUInt
for ((pmp, i) <- read_pmp.zipWithIndex)
read_mapping += (CSRs.pmpaddr0 + i) -> pmp.readAddr
}
// implementation-defined CSRs
def generateCustomCSR(csr: CustomCSR, csr_io: CustomCSRIO) = {
require(csr.mask >= 0 && csr.mask.bitLength <= xLen)
require(!read_mapping.contains(csr.id))
val reg = csr.init.map(init => RegInit(init.U(xLen.W))).getOrElse(Reg(UInt(xLen.W)))
val read = io.rw.cmd =/= CSR.N && io.rw.addr === csr.id.U
csr_io.ren := read
when (read && csr_io.stall) { io.rw_stall := true.B }
read_mapping += csr.id -> reg
reg
}
val reg_custom = customCSRs.zip(io.customCSRs).map(t => generateCustomCSR(t._1, t._2))
val reg_rocc = roccCSRs.zip(io.roccCSRs).map(t => generateCustomCSR(t._1, t._2))
if (usingHypervisor) {
read_mapping += CSRs.mtinst -> read_mtinst
read_mapping += CSRs.mtval2 -> reg_mtval2
val read_hstatus = io.hstatus.asUInt.extract(xLen-1,0)
read_mapping += CSRs.hstatus -> read_hstatus
read_mapping += CSRs.hedeleg -> read_hedeleg
read_mapping += CSRs.hideleg -> read_hideleg
read_mapping += CSRs.hcounteren-> read_hcounteren
read_mapping += CSRs.hgatp -> reg_hgatp.asUInt
read_mapping += CSRs.hip -> read_hip
read_mapping += CSRs.hie -> read_hie
read_mapping += CSRs.hvip -> read_hvip
read_mapping += CSRs.hgeie -> 0.U
read_mapping += CSRs.hgeip -> 0.U
read_mapping += CSRs.htval -> reg_htval
read_mapping += CSRs.htinst -> read_htinst
read_mapping += CSRs.henvcfg -> reg_henvcfg.asUInt
if (xLen == 32)
read_mapping += CSRs.henvcfgh -> (reg_henvcfg.asUInt >> 32)
val read_vsie = (read_hie & read_hideleg) >> 1
val read_vsip = (read_hip & read_hideleg) >> 1
val read_vsepc = readEPC(reg_vsepc).sextTo(xLen)
val read_vstval = reg_vstval.sextTo(xLen)
val read_vsstatus = io.gstatus.asUInt.extract(xLen-1,0)
read_mapping += CSRs.vsstatus -> read_vsstatus
read_mapping += CSRs.vsip -> read_vsip
read_mapping += CSRs.vsie -> read_vsie
read_mapping += CSRs.vsscratch -> reg_vsscratch
read_mapping += CSRs.vscause -> reg_vscause
read_mapping += CSRs.vstval -> read_vstval
read_mapping += CSRs.vsatp -> reg_vsatp.asUInt
read_mapping += CSRs.vsepc -> read_vsepc
read_mapping += CSRs.vstvec -> read_vstvec
}
// mimpid, marchid, mvendorid, and mconfigptr are 0 unless overridden by customCSRs
Seq(CSRs.mimpid, CSRs.marchid, CSRs.mvendorid, CSRs.mconfigptr).foreach(id => read_mapping.getOrElseUpdate(id, 0.U))
val decoded_addr = {
val addr = Cat(io.status.v, io.rw.addr)
val pats = for (((k, _), i) <- read_mapping.zipWithIndex)
yield (BitPat(k.U), (0 until read_mapping.size).map(j => BitPat((i == j).B)))
val decoded = DecodeLogic(addr, Seq.fill(read_mapping.size)(X), pats)
val unvirtualized_mapping = (for (((k, _), v) <- read_mapping zip decoded) yield k -> v.asBool).toMap
for ((k, v) <- unvirtualized_mapping) yield k -> {
val alt: Option[Bool] = CSR.mode(k) match {
// hcontext was assigned an unfortunate address; it lives where a
// hypothetical vscontext will live. Exclude them from the S/VS remapping.
// (on separate lines so scala-lint doesnt do something stupid)
case _ if k == CSRs.scontext => None
case _ if k == CSRs.hcontext => None
// When V=1, if a corresponding VS CSR exists, access it instead...
case PRV.H => unvirtualized_mapping.lift(k - (1 << CSR.modeLSB))
// ...and don't access the original S-mode version.
case PRV.S => unvirtualized_mapping.contains(k + (1 << CSR.modeLSB)).option(false.B)
case _ => None
}
alt.map(Mux(reg_mstatus.v, _, v)).getOrElse(v)
}
}
val wdata = readModifyWriteCSR(io.rw.cmd, io.rw.rdata, io.rw.wdata)
val system_insn = io.rw.cmd === CSR.I
val hlsv = Seq(HLV_B, HLV_BU, HLV_H, HLV_HU, HLV_W, HLV_WU, HLV_D, HSV_B, HSV_H, HSV_W, HSV_D, HLVX_HU, HLVX_WU)
val decode_table = Seq( ECALL-> List(Y,N,N,N,N,N,N,N,N),
EBREAK-> List(N,Y,N,N,N,N,N,N,N),
MRET-> List(N,N,Y,N,N,N,N,N,N),
CEASE-> List(N,N,N,Y,N,N,N,N,N),
WFI-> List(N,N,N,N,Y,N,N,N,N)) ++
usingDebug.option( DRET-> List(N,N,Y,N,N,N,N,N,N)) ++
usingNMI.option( MNRET-> List(N,N,Y,N,N,N,N,N,N)) ++
coreParams.haveCFlush.option(CFLUSH_D_L1-> List(N,N,N,N,N,N,N,N,N)) ++
usingSupervisor.option( SRET-> List(N,N,Y,N,N,N,N,N,N)) ++
usingVM.option( SFENCE_VMA-> List(N,N,N,N,N,Y,N,N,N)) ++
usingHypervisor.option( HFENCE_VVMA-> List(N,N,N,N,N,N,Y,N,N)) ++
usingHypervisor.option( HFENCE_GVMA-> List(N,N,N,N,N,N,N,Y,N)) ++
(if (usingHypervisor) hlsv.map(_-> List(N,N,N,N,N,N,N,N,Y)) else Seq())
val insn_call :: insn_break :: insn_ret :: insn_cease :: insn_wfi :: _ :: _ :: _ :: _ :: Nil = {
val insn = ECALL.value.U | (io.rw.addr << 20)
DecodeLogic(insn, decode_table(0)._2.map(x=>X), decode_table).map(system_insn && _.asBool)
}
for (io_dec <- io.decode) {
val addr = io_dec.inst(31, 20)
def decodeAny(m: LinkedHashMap[Int,Bits]): Bool = m.map { case(k: Int, _: Bits) => addr === k.U }.reduce(_||_)
def decodeFast(s: Seq[Int]): Bool = DecodeLogic(addr, s.map(_.U), (read_mapping -- s).keys.toList.map(_.U))
val _ :: is_break :: is_ret :: _ :: is_wfi :: is_sfence :: is_hfence_vvma :: is_hfence_gvma :: is_hlsv :: Nil =
DecodeLogic(io_dec.inst, decode_table(0)._2.map(x=>X), decode_table).map(_.asBool)
val is_counter = (addr.inRange(CSR.firstCtr.U, (CSR.firstCtr + CSR.nCtr).U) || addr.inRange(CSR.firstCtrH.U, (CSR.firstCtrH + CSR.nCtr).U))
val allow_wfi = (!usingSupervisor).B || reg_mstatus.prv > PRV.S.U || !reg_mstatus.tw && (!reg_mstatus.v || !reg_hstatus.vtw)
val allow_sfence_vma = (!usingVM).B || reg_mstatus.prv > PRV.S.U || !Mux(reg_mstatus.v, reg_hstatus.vtvm, reg_mstatus.tvm)
val allow_hfence_vvma = (!usingHypervisor).B || !reg_mstatus.v && (reg_mstatus.prv >= PRV.S.U)
val allow_hlsv = (!usingHypervisor).B || !reg_mstatus.v && (reg_mstatus.prv >= PRV.S.U || reg_hstatus.hu)
val allow_sret = (!usingSupervisor).B || reg_mstatus.prv > PRV.S.U || !Mux(reg_mstatus.v, reg_hstatus.vtsr, reg_mstatus.tsr)
val counter_addr = addr(log2Ceil(read_mcounteren.getWidth)-1, 0)
val allow_counter = (reg_mstatus.prv > PRV.S.U || read_mcounteren(counter_addr)) &&
(!usingSupervisor.B || reg_mstatus.prv >= PRV.S.U || read_scounteren(counter_addr)) &&
(!usingHypervisor.B || !reg_mstatus.v || read_hcounteren(counter_addr))
io_dec.fp_illegal := io.status.fs === 0.U || reg_mstatus.v && reg_vsstatus.fs === 0.U || !reg_misa('f'-'a')
io_dec.vector_illegal := io.status.vs === 0.U || reg_mstatus.v && reg_vsstatus.vs === 0.U || !reg_misa('v'-'a')
io_dec.fp_csr := decodeFast(fp_csrs.keys.toList)
io_dec.vector_csr := decodeFast(vector_csrs.keys.toList)
io_dec.rocc_illegal := io.status.xs === 0.U || reg_mstatus.v && reg_vsstatus.xs === 0.U || !reg_misa('x'-'a')
val csr_addr_legal = reg_mstatus.prv >= CSR.mode(addr) ||
usingHypervisor.B && !reg_mstatus.v && reg_mstatus.prv === PRV.S.U && CSR.mode(addr) === PRV.H.U
val csr_exists = decodeAny(read_mapping)
io_dec.read_illegal := !csr_addr_legal ||
!csr_exists ||
((addr === CSRs.satp.U || addr === CSRs.hgatp.U) && !allow_sfence_vma) ||
is_counter && !allow_counter ||
decodeFast(debug_csrs.keys.toList) && !reg_debug ||
decodeFast(vector_csrs.keys.toList) && io_dec.vector_illegal ||
io_dec.fp_csr && io_dec.fp_illegal
io_dec.write_illegal := addr(11,10).andR
io_dec.write_flush := {
val addr_m = addr | (PRV.M.U << CSR.modeLSB)
!(addr_m >= CSRs.mscratch.U && addr_m <= CSRs.mtval.U)
}
io_dec.system_illegal := !csr_addr_legal && !is_hlsv ||
is_wfi && !allow_wfi ||
is_ret && !allow_sret ||
is_ret && addr(10) && addr(7) && !reg_debug ||
(is_sfence || is_hfence_gvma) && !allow_sfence_vma ||
is_hfence_vvma && !allow_hfence_vvma ||
is_hlsv && !allow_hlsv
io_dec.virtual_access_illegal := reg_mstatus.v && csr_exists && (
CSR.mode(addr) === PRV.H.U ||
is_counter && read_mcounteren(counter_addr) && (!read_hcounteren(counter_addr) || !reg_mstatus.prv(0) && !read_scounteren(counter_addr)) ||
CSR.mode(addr) === PRV.S.U && !reg_mstatus.prv(0) ||
addr === CSRs.satp.U && reg_mstatus.prv(0) && reg_hstatus.vtvm)
io_dec.virtual_system_illegal := reg_mstatus.v && (
is_hfence_vvma ||
is_hfence_gvma ||
is_hlsv ||
is_wfi && (!reg_mstatus.prv(0) || !reg_mstatus.tw && reg_hstatus.vtw) ||
is_ret && CSR.mode(addr) === PRV.S.U && (!reg_mstatus.prv(0) || reg_hstatus.vtsr) ||
is_sfence && (!reg_mstatus.prv(0) || reg_hstatus.vtvm))
}
val cause =
Mux(insn_call, Causes.user_ecall.U + Mux(reg_mstatus.prv(0) && reg_mstatus.v, PRV.H.U, reg_mstatus.prv),
Mux[UInt](insn_break, Causes.breakpoint.U, io.cause))
val cause_lsbs = cause(log2Ceil(1 + CSR.busErrorIntCause)-1, 0)
val cause_deleg_lsbs = cause(log2Ceil(xLen)-1,0)
val causeIsDebugInt = cause(xLen-1) && cause_lsbs === CSR.debugIntCause.U
val causeIsDebugTrigger = !cause(xLen-1) && cause_lsbs === CSR.debugTriggerCause.U
val causeIsDebugBreak = !cause(xLen-1) && insn_break && Cat(reg_dcsr.ebreakm, reg_dcsr.ebreakh, reg_dcsr.ebreaks, reg_dcsr.ebreaku)(reg_mstatus.prv)
val trapToDebug = usingDebug.B && (reg_singleStepped || causeIsDebugInt || causeIsDebugTrigger || causeIsDebugBreak || reg_debug)
val debugEntry = p(DebugModuleKey).map(_.debugEntry).getOrElse(BigInt(0x800))
val debugException = p(DebugModuleKey).map(_.debugException).getOrElse(BigInt(0x808))
val debugTVec = Mux(reg_debug, Mux(insn_break, debugEntry.U, debugException.U), debugEntry.U)
val delegate = usingSupervisor.B && reg_mstatus.prv <= PRV.S.U && Mux(cause(xLen-1), read_mideleg(cause_deleg_lsbs), read_medeleg(cause_deleg_lsbs))
val delegateVS = reg_mstatus.v && delegate && Mux(cause(xLen-1), read_hideleg(cause_deleg_lsbs), read_hedeleg(cause_deleg_lsbs))
def mtvecBaseAlign = 2
def mtvecInterruptAlign = {
require(reg_mip.getWidth <= xLen)
log2Ceil(xLen)
}
val notDebugTVec = {
val base = Mux(delegate, Mux(delegateVS, read_vstvec, read_stvec), read_mtvec)
val interruptOffset = cause(mtvecInterruptAlign-1, 0) << mtvecBaseAlign
val interruptVec = Cat(base >> (mtvecInterruptAlign + mtvecBaseAlign), interruptOffset)
val doVector = base(0) && cause(cause.getWidth-1) && (cause_lsbs >> mtvecInterruptAlign) === 0.U
Mux(doVector, interruptVec, base >> mtvecBaseAlign << mtvecBaseAlign)
}
val causeIsRnmiInt = cause(xLen-1) && cause(xLen-2) && (cause_lsbs === CSR.rnmiIntCause.U || cause_lsbs === CSR.rnmiBEUCause.U)
val causeIsRnmiBEU = cause(xLen-1) && cause(xLen-2) && cause_lsbs === CSR.rnmiBEUCause.U
val causeIsNmi = causeIsRnmiInt
val nmiTVecInt = io.interrupts.nmi.map(nmi => nmi.rnmi_interrupt_vector).getOrElse(0.U)
val nmiTVecXcpt = io.interrupts.nmi.map(nmi => nmi.rnmi_exception_vector).getOrElse(0.U)
val trapToNmiInt = usingNMI.B && causeIsNmi
val trapToNmiXcpt = usingNMI.B && !nmie
val trapToNmi = trapToNmiInt || trapToNmiXcpt
val nmiTVec = (Mux(causeIsNmi, nmiTVecInt, nmiTVecXcpt)>>1)<<1
val tvec = Mux(trapToDebug, debugTVec, Mux(trapToNmi, nmiTVec, notDebugTVec))
io.evec := tvec
io.ptbr := reg_satp
io.hgatp := reg_hgatp
io.vsatp := reg_vsatp
io.eret := insn_call || insn_break || insn_ret
io.singleStep := reg_dcsr.step && !reg_debug
io.status := reg_mstatus
io.status.sd := io.status.fs.andR || io.status.xs.andR || io.status.vs.andR
io.status.debug := reg_debug
io.status.isa := reg_misa
io.status.uxl := (if (usingUser) log2Ceil(xLen) - 4 else 0).U
io.status.sxl := (if (usingSupervisor) log2Ceil(xLen) - 4 else 0).U
io.status.dprv := Mux(reg_mstatus.mprv && !reg_debug, reg_mstatus.mpp, reg_mstatus.prv)
io.status.dv := reg_mstatus.v || Mux(reg_mstatus.mprv && !reg_debug, reg_mstatus.mpv, false.B)
io.status.sd_rv32 := (xLen == 32).B && io.status.sd
io.status.mpv := reg_mstatus.mpv
io.status.gva := reg_mstatus.gva
io.hstatus := reg_hstatus
io.hstatus.vsxl := (if (usingSupervisor) log2Ceil(xLen) - 4 else 0).U
io.gstatus := reg_vsstatus
io.gstatus.sd := io.gstatus.fs.andR || io.gstatus.xs.andR || io.gstatus.vs.andR
io.gstatus.uxl := (if (usingUser) log2Ceil(xLen) - 4 else 0).U
io.gstatus.sd_rv32 := (xLen == 32).B && io.gstatus.sd
val exception = insn_call || insn_break || io.exception
assert(PopCount(insn_ret :: insn_call :: insn_break :: io.exception :: Nil) <= 1.U, "these conditions must be mutually exclusive")
when (insn_wfi && !io.singleStep && !reg_debug) { reg_wfi := true.B }
when (pending_interrupts.orR || io.interrupts.debug || exception) { reg_wfi := false.B }
io.interrupts.nmi.map(nmi => when (nmi.rnmi) { reg_wfi := false.B } )
when (io.retire(0) || exception) { reg_singleStepped := true.B }
when (!io.singleStep) { reg_singleStepped := false.B }
assert(!io.singleStep || io.retire <= 1.U)
assert(!reg_singleStepped || io.retire === 0.U)
val epc = formEPC(io.pc)
val tval = Mux(insn_break, epc, io.tval)
when (exception) {
when (trapToDebug) {
when (!reg_debug) {
reg_mstatus.v := false.B
reg_debug := true.B
reg_dpc := epc
reg_dcsr.cause := Mux(reg_singleStepped, 4.U, Mux(causeIsDebugInt, 3.U, Mux[UInt](causeIsDebugTrigger, 2.U, 1.U)))
reg_dcsr.prv := trimPrivilege(reg_mstatus.prv)
reg_dcsr.v := reg_mstatus.v
new_prv := PRV.M.U
}
}.elsewhen (trapToNmiInt) {
when (reg_rnmie) {
reg_mstatus.v := false.B
reg_mnstatus.mpv := reg_mstatus.v
reg_rnmie := false.B
reg_mnepc := epc
reg_mncause := (BigInt(1) << (xLen-1)).U | Mux(causeIsRnmiBEU, 3.U, 2.U)
reg_mnstatus.mpp := trimPrivilege(reg_mstatus.prv)
new_prv := PRV.M.U
}
}.elsewhen (delegateVS && nmie) {
reg_mstatus.v := true.B
reg_vsstatus.spp := reg_mstatus.prv
reg_vsepc := epc
reg_vscause := Mux(cause(xLen-1), Cat(cause(xLen-1, 2), 1.U(2.W)), cause)
reg_vstval := tval
reg_vsstatus.spie := reg_vsstatus.sie
reg_vsstatus.sie := false.B
new_prv := PRV.S.U
}.elsewhen (delegate && nmie) {
reg_mstatus.v := false.B
reg_hstatus.spvp := Mux(reg_mstatus.v, reg_mstatus.prv(0),reg_hstatus.spvp)
reg_hstatus.gva := io.gva
reg_hstatus.spv := reg_mstatus.v
reg_sepc := epc
reg_scause := cause
reg_stval := tval
reg_htval := io.htval
reg_htinst_read_pseudo := io.mhtinst_read_pseudo
reg_mstatus.spie := reg_mstatus.sie
reg_mstatus.spp := reg_mstatus.prv
reg_mstatus.sie := false.B
new_prv := PRV.S.U
}.otherwise {
reg_mstatus.v := false.B
reg_mstatus.mpv := reg_mstatus.v
reg_mstatus.gva := io.gva
reg_mepc := epc
reg_mcause := cause
reg_mtval := tval
reg_mtval2 := io.htval
reg_mtinst_read_pseudo := io.mhtinst_read_pseudo
reg_mstatus.mpie := reg_mstatus.mie
reg_mstatus.mpp := trimPrivilege(reg_mstatus.prv)
reg_mstatus.mie := false.B
new_prv := PRV.M.U
}
}
for (i <- 0 until supported_interrupts.getWidth) {
val en = exception && (supported_interrupts & (BigInt(1) << i).U) =/= 0.U && cause === (BigInt(1) << (xLen - 1)).U + i.U
val delegable = (delegable_interrupts & (BigInt(1) << i).U) =/= 0.U
property.cover(en && !delegate, s"INTERRUPT_M_$i")
property.cover(en && delegable && delegate, s"INTERRUPT_S_$i")
}
for (i <- 0 until xLen) {
val supported_exceptions: BigInt = 0x8fe |
(if (usingCompressed && !coreParams.misaWritable) 0 else 1) |
(if (usingUser) 0x100 else 0) |
(if (usingSupervisor) 0x200 else 0) |
(if (usingVM) 0xb000 else 0)
if (((supported_exceptions >> i) & 1) != 0) {
val en = exception && cause === i.U
val delegable = (delegable_exceptions & (BigInt(1) << i).U) =/= 0.U
property.cover(en && !delegate, s"EXCEPTION_M_$i")
property.cover(en && delegable && delegate, s"EXCEPTION_S_$i")
}
}
when (insn_ret) {
val ret_prv = WireInit(UInt(), DontCare)
when (usingSupervisor.B && !io.rw.addr(9)) {
when (!reg_mstatus.v) {
reg_mstatus.sie := reg_mstatus.spie
reg_mstatus.spie := true.B
reg_mstatus.spp := PRV.U.U
ret_prv := reg_mstatus.spp
reg_mstatus.v := usingHypervisor.B && reg_hstatus.spv
io.evec := readEPC(reg_sepc)
reg_hstatus.spv := false.B
}.otherwise {
reg_vsstatus.sie := reg_vsstatus.spie
reg_vsstatus.spie := true.B
reg_vsstatus.spp := PRV.U.U
ret_prv := reg_vsstatus.spp
reg_mstatus.v := usingHypervisor.B
io.evec := readEPC(reg_vsepc)
}
}.elsewhen (usingDebug.B && io.rw.addr(10) && io.rw.addr(7)) {
ret_prv := reg_dcsr.prv
reg_mstatus.v := usingHypervisor.B && reg_dcsr.v && reg_dcsr.prv <= PRV.S.U
reg_debug := false.B
io.evec := readEPC(reg_dpc)
}.elsewhen (usingNMI.B && io.rw.addr(10) && !io.rw.addr(7)) {
ret_prv := reg_mnstatus.mpp
reg_mstatus.v := usingHypervisor.B && reg_mnstatus.mpv && reg_mnstatus.mpp <= PRV.S.U
reg_rnmie := true.B
io.evec := readEPC(reg_mnepc)
}.otherwise {
reg_mstatus.mie := reg_mstatus.mpie
reg_mstatus.mpie := true.B
reg_mstatus.mpp := legalizePrivilege(PRV.U.U)
reg_mstatus.mpv := false.B
ret_prv := reg_mstatus.mpp
reg_mstatus.v := usingHypervisor.B && reg_mstatus.mpv && reg_mstatus.mpp <= PRV.S.U
io.evec := readEPC(reg_mepc)
}
new_prv := ret_prv
when (usingUser.B && ret_prv <= PRV.S.U) {
reg_mstatus.mprv := false.B
}
}
io.time := reg_cycle
io.csr_stall := reg_wfi || io.status.cease
io.status.cease := RegEnable(true.B, false.B, insn_cease)
io.status.wfi := reg_wfi
for ((io, reg) <- io.customCSRs zip reg_custom) {
io.wen := false.B
io.wdata := wdata
io.value := reg
}
for ((io, reg) <- io.roccCSRs zip reg_rocc) {
io.wen := false.B
io.wdata := wdata
io.value := reg
}
io.rw.rdata := Mux1H(for ((k, v) <- read_mapping) yield decoded_addr(k) -> v)
// cover access to register
val coverable_counters = read_mapping.filterNot { case (k, _) =>
k >= CSR.firstHPC + nPerfCounters && k < CSR.firstHPC + CSR.nHPM
}
coverable_counters.foreach( {case (k, v) => {
when (!k.U(11,10).andR) { // Cover points for RW CSR registers
property.cover(io.rw.cmd.isOneOf(CSR.W, CSR.S, CSR.C) && io.rw.addr===k.U, "CSR_access_"+k.toString, "Cover Accessing Core CSR field")
} .otherwise { // Cover points for RO CSR registers
property.cover(io.rw.cmd===CSR.R && io.rw.addr===k.U, "CSR_access_"+k.toString, "Cover Accessing Core CSR field")
}
}})
val set_vs_dirty = WireDefault(io.vector.map(_.set_vs_dirty).getOrElse(false.B))
io.vector.foreach { vio =>
when (set_vs_dirty) {
assert(reg_mstatus.vs > 0.U)
when (reg_mstatus.v) { reg_vsstatus.vs := 3.U }
reg_mstatus.vs := 3.U
}
}
val set_fs_dirty = WireDefault(io.set_fs_dirty.getOrElse(false.B))
if (coreParams.haveFSDirty) {
when (set_fs_dirty) {
assert(reg_mstatus.fs > 0.U)
when (reg_mstatus.v) { reg_vsstatus.fs := 3.U }
reg_mstatus.fs := 3.U
}
}
io.fcsr_rm := reg_frm
when (io.fcsr_flags.valid) {
reg_fflags := reg_fflags | io.fcsr_flags.bits
set_fs_dirty := true.B
}
io.vector.foreach { vio =>
when (vio.set_vxsat) {
reg_vxsat.get := true.B
set_vs_dirty := true.B
}
}
val csr_wen = io.rw.cmd.isOneOf(CSR.S, CSR.C, CSR.W) && !io.rw_stall
io.csrw_counter := Mux(coreParams.haveBasicCounters.B && csr_wen && (io.rw.addr.inRange(CSRs.mcycle.U, (CSRs.mcycle + CSR.nCtr).U) || io.rw.addr.inRange(CSRs.mcycleh.U, (CSRs.mcycleh + CSR.nCtr).U)), UIntToOH(io.rw.addr(log2Ceil(CSR.nCtr+nPerfCounters)-1, 0)), 0.U)
when (csr_wen) {
val scause_mask = ((BigInt(1) << (xLen-1)) + 31).U /* only implement 5 LSBs and MSB */
val satp_valid_modes = 0 +: (minPgLevels to pgLevels).map(new PTBR().pgLevelsToMode(_))
when (decoded_addr(CSRs.mstatus)) {
val new_mstatus = wdata.asTypeOf(new MStatus())
reg_mstatus.mie := new_mstatus.mie
reg_mstatus.mpie := new_mstatus.mpie
if (usingUser) {
reg_mstatus.mprv := new_mstatus.mprv
reg_mstatus.mpp := legalizePrivilege(new_mstatus.mpp)
if (usingSupervisor) {
reg_mstatus.spp := new_mstatus.spp
reg_mstatus.spie := new_mstatus.spie
reg_mstatus.sie := new_mstatus.sie
reg_mstatus.tw := new_mstatus.tw
reg_mstatus.tsr := new_mstatus.tsr
}
if (usingVM) {
reg_mstatus.mxr := new_mstatus.mxr
reg_mstatus.sum := new_mstatus.sum
reg_mstatus.tvm := new_mstatus.tvm
}
if (usingHypervisor) {
reg_mstatus.mpv := new_mstatus.mpv
reg_mstatus.gva := new_mstatus.gva
}
}
if (usingSupervisor || usingFPU) reg_mstatus.fs := formFS(new_mstatus.fs)
reg_mstatus.vs := formVS(new_mstatus.vs)
}
when (decoded_addr(CSRs.misa)) {
val mask = isaStringToMask(isaMaskString).U(xLen.W)
val f = wdata('f' - 'a')
// suppress write if it would cause the next fetch to be misaligned
when (!usingCompressed.B || !io.pc(1) || wdata('c' - 'a')) {
if (coreParams.misaWritable)
reg_misa := ~(~wdata | (!f << ('d' - 'a'))) & mask | reg_misa & ~mask
}
}
when (decoded_addr(CSRs.mip)) {
// MIP should be modified based on the value in reg_mip, not the value
// in read_mip, since read_mip.seip is the OR of reg_mip.seip and
// io.interrupts.seip. We don't want the value on the PLIC line to
// inadvertently be OR'd into read_mip.seip.
val new_mip = readModifyWriteCSR(io.rw.cmd, reg_mip.asUInt, io.rw.wdata).asTypeOf(new MIP)
if (usingSupervisor) {
reg_mip.ssip := new_mip.ssip
reg_mip.stip := new_mip.stip
reg_mip.seip := new_mip.seip
}
if (usingHypervisor) {
reg_mip.vssip := new_mip.vssip
}
}
when (decoded_addr(CSRs.mie)) { reg_mie := wdata & supported_interrupts }
when (decoded_addr(CSRs.mepc)) { reg_mepc := formEPC(wdata) }
when (decoded_addr(CSRs.mscratch)) { reg_mscratch := wdata }
if (mtvecWritable)
when (decoded_addr(CSRs.mtvec)) { reg_mtvec := wdata }
when (decoded_addr(CSRs.mcause)) { reg_mcause := wdata & ((BigInt(1) << (xLen-1)) + (BigInt(1) << whichInterrupt.getWidth) - 1).U }
when (decoded_addr(CSRs.mtval)) { reg_mtval := wdata }
if (usingNMI) {
val new_mnstatus = wdata.asTypeOf(new MNStatus())
when (decoded_addr(CustomCSRs.mnscratch)) { reg_mnscratch := wdata }
when (decoded_addr(CustomCSRs.mnepc)) { reg_mnepc := formEPC(wdata) }
when (decoded_addr(CustomCSRs.mncause)) { reg_mncause := wdata & ((BigInt(1) << (xLen-1)) + BigInt(3)).U }
when (decoded_addr(CustomCSRs.mnstatus)) {
reg_mnstatus.mpp := legalizePrivilege(new_mnstatus.mpp)
reg_mnstatus.mpv := usingHypervisor.B && new_mnstatus.mpv
reg_rnmie := reg_rnmie | new_mnstatus.mie // mnie bit settable but not clearable from software
}
}
for (((e, c), i) <- (reg_hpmevent zip reg_hpmcounter).zipWithIndex) {
writeCounter(i + CSR.firstMHPC, c, wdata)
when (decoded_addr(i + CSR.firstHPE)) { e := perfEventSets.maskEventSelector(wdata) }
}
if (coreParams.haveBasicCounters) {
when (decoded_addr(CSRs.mcountinhibit)) { reg_mcountinhibit := wdata & ~2.U(xLen.W) } // mcountinhibit bit [1] is tied zero
writeCounter(CSRs.mcycle, reg_cycle, wdata)
writeCounter(CSRs.minstret, reg_instret, wdata)
}
if (usingFPU) {
when (decoded_addr(CSRs.fflags)) { set_fs_dirty := true.B; reg_fflags := wdata }
when (decoded_addr(CSRs.frm)) { set_fs_dirty := true.B; reg_frm := wdata }
when (decoded_addr(CSRs.fcsr)) {
set_fs_dirty := true.B
reg_fflags := wdata
reg_frm := wdata >> reg_fflags.getWidth
}
}
if (usingDebug) {
when (decoded_addr(CSRs.dcsr)) {
val new_dcsr = wdata.asTypeOf(new DCSR())
reg_dcsr.step := new_dcsr.step
reg_dcsr.ebreakm := new_dcsr.ebreakm
if (usingSupervisor) reg_dcsr.ebreaks := new_dcsr.ebreaks
if (usingUser) reg_dcsr.ebreaku := new_dcsr.ebreaku
if (usingUser) reg_dcsr.prv := legalizePrivilege(new_dcsr.prv)
if (usingHypervisor) reg_dcsr.v := new_dcsr.v
}
when (decoded_addr(CSRs.dpc)) { reg_dpc := formEPC(wdata) }
when (decoded_addr(CSRs.dscratch0)) { reg_dscratch0 := wdata }
reg_dscratch1.foreach { r =>
when (decoded_addr(CSRs.dscratch1)) { r := wdata }
}
}
if (usingSupervisor) {
when (decoded_addr(CSRs.sstatus)) {
val new_sstatus = wdata.asTypeOf(new MStatus())
reg_mstatus.sie := new_sstatus.sie
reg_mstatus.spie := new_sstatus.spie
reg_mstatus.spp := new_sstatus.spp
reg_mstatus.fs := formFS(new_sstatus.fs)
reg_mstatus.vs := formVS(new_sstatus.vs)
if (usingVM) {
reg_mstatus.mxr := new_sstatus.mxr
reg_mstatus.sum := new_sstatus.sum
}
}
when (decoded_addr(CSRs.sip)) {
val new_sip = ((read_mip & ~read_mideleg) | (wdata & read_mideleg)).asTypeOf(new MIP())
reg_mip.ssip := new_sip.ssip
}
when (decoded_addr(CSRs.satp)) {
if (usingVM) {
val new_satp = wdata.asTypeOf(new PTBR())
when (new_satp.mode.isOneOf(satp_valid_modes.map(_.U))) {
reg_satp.mode := new_satp.mode & satp_valid_modes.reduce(_|_).U
reg_satp.ppn := new_satp.ppn(ppnBits-1,0)
if (asIdBits > 0) reg_satp.asid := new_satp.asid(asIdBits-1,0)
}
}
}
when (decoded_addr(CSRs.sie)) { reg_mie := (reg_mie & ~sie_mask) | (wdata & sie_mask) }
when (decoded_addr(CSRs.sscratch)) { reg_sscratch := wdata }
when (decoded_addr(CSRs.sepc)) { reg_sepc := formEPC(wdata) }
when (decoded_addr(CSRs.stvec)) { reg_stvec := wdata }
when (decoded_addr(CSRs.scause)) { reg_scause := wdata & scause_mask }
when (decoded_addr(CSRs.stval)) { reg_stval := wdata }
when (decoded_addr(CSRs.mideleg)) { reg_mideleg := wdata }
when (decoded_addr(CSRs.medeleg)) { reg_medeleg := wdata }
when (decoded_addr(CSRs.scounteren)) { reg_scounteren := wdata }
when (decoded_addr(CSRs.senvcfg)) { reg_senvcfg.write(wdata) }
}
if (usingHypervisor) {
when (decoded_addr(CSRs.hstatus)) {
val new_hstatus = wdata.asTypeOf(new HStatus())
reg_hstatus.gva := new_hstatus.gva
reg_hstatus.spv := new_hstatus.spv
reg_hstatus.spvp := new_hstatus.spvp
reg_hstatus.hu := new_hstatus.hu
reg_hstatus.vtvm := new_hstatus.vtvm
reg_hstatus.vtw := new_hstatus.vtw
reg_hstatus.vtsr := new_hstatus.vtsr
reg_hstatus.vsxl := new_hstatus.vsxl
}
when (decoded_addr(CSRs.hideleg)) { reg_hideleg := wdata }
when (decoded_addr(CSRs.hedeleg)) { reg_hedeleg := wdata }
when (decoded_addr(CSRs.hgatp)) {
val new_hgatp = wdata.asTypeOf(new PTBR())
val valid_modes = 0 +: (minPgLevels to pgLevels).map(new_hgatp.pgLevelsToMode(_))
when (new_hgatp.mode.isOneOf(valid_modes.map(_.U))) {
reg_hgatp.mode := new_hgatp.mode & valid_modes.reduce(_|_).U
}
reg_hgatp.ppn := Cat(new_hgatp.ppn(ppnBits-1,2), 0.U(2.W))
if (vmIdBits > 0) reg_hgatp.asid := new_hgatp.asid(vmIdBits-1,0)
}
when (decoded_addr(CSRs.hip)) {
val new_hip = ((read_mip & ~hs_delegable_interrupts) | (wdata & hs_delegable_interrupts)).asTypeOf(new MIP())
reg_mip.vssip := new_hip.vssip
}
when (decoded_addr(CSRs.hie)) { reg_mie := (reg_mie & ~hs_delegable_interrupts) | (wdata & hs_delegable_interrupts) }
when (decoded_addr(CSRs.hvip)) {
val new_sip = ((read_mip & ~hs_delegable_interrupts) | (wdata & hs_delegable_interrupts)).asTypeOf(new MIP())
reg_mip.vssip := new_sip.vssip
reg_mip.vstip := new_sip.vstip
reg_mip.vseip := new_sip.vseip
}
when (decoded_addr(CSRs.hcounteren)) { reg_hcounteren := wdata }
when (decoded_addr(CSRs.htval)) { reg_htval := wdata }
when (decoded_addr(CSRs.mtval2)) { reg_mtval2 := wdata }
val write_mhtinst_read_pseudo = wdata(13) && (xLen == 32).option(true.B).getOrElse(wdata(12))
when(decoded_addr(CSRs.mtinst)) { reg_mtinst_read_pseudo := write_mhtinst_read_pseudo }
when(decoded_addr(CSRs.htinst)) { reg_htinst_read_pseudo := write_mhtinst_read_pseudo }
when (decoded_addr(CSRs.vsstatus)) {
val new_vsstatus = wdata.asTypeOf(new MStatus())
reg_vsstatus.sie := new_vsstatus.sie
reg_vsstatus.spie := new_vsstatus.spie
reg_vsstatus.spp := new_vsstatus.spp
reg_vsstatus.mxr := new_vsstatus.mxr
reg_vsstatus.sum := new_vsstatus.sum
reg_vsstatus.fs := formFS(new_vsstatus.fs)
reg_vsstatus.vs := formVS(new_vsstatus.vs)
}
when (decoded_addr(CSRs.vsip)) {
val new_vsip = ((read_hip & ~read_hideleg) | ((wdata << 1) & read_hideleg)).asTypeOf(new MIP())
reg_mip.vssip := new_vsip.vssip
}
when (decoded_addr(CSRs.vsatp)) {
val new_vsatp = wdata.asTypeOf(new PTBR())
val mode_ok = new_vsatp.mode.isOneOf(satp_valid_modes.map(_.U))
when (mode_ok) {
reg_vsatp.mode := new_vsatp.mode & satp_valid_modes.reduce(_|_).U
}
when (mode_ok || !reg_mstatus.v) {
reg_vsatp.ppn := new_vsatp.ppn(vpnBits.min(new_vsatp.ppn.getWidth)-1,0)
if (asIdBits > 0) reg_vsatp.asid := new_vsatp.asid(asIdBits-1,0)
}
}
when (decoded_addr(CSRs.vsie)) { reg_mie := (reg_mie & ~read_hideleg) | ((wdata << 1) & read_hideleg) }
when (decoded_addr(CSRs.vsscratch)) { reg_vsscratch := wdata }
when (decoded_addr(CSRs.vsepc)) { reg_vsepc := formEPC(wdata) }
when (decoded_addr(CSRs.vstvec)) { reg_vstvec := wdata }
when (decoded_addr(CSRs.vscause)) { reg_vscause := wdata & scause_mask }
when (decoded_addr(CSRs.vstval)) { reg_vstval := wdata }
when (decoded_addr(CSRs.henvcfg)) { reg_henvcfg.write(wdata) }
}
if (usingUser) {
when (decoded_addr(CSRs.mcounteren)) { reg_mcounteren := wdata }
when (decoded_addr(CSRs.menvcfg)) { reg_menvcfg.write(wdata) }
}
if (nBreakpoints > 0) {
when (decoded_addr(CSRs.tselect)) { reg_tselect := wdata }
for ((bp, i) <- reg_bp.zipWithIndex) {
when (i.U === reg_tselect && (!bp.control.dmode || reg_debug)) {
when (decoded_addr(CSRs.tdata2)) { bp.address := wdata }
when (decoded_addr(CSRs.tdata3)) {
if (coreParams.mcontextWidth > 0) {
bp.textra.mselect := wdata(bp.textra.mselectPos)
bp.textra.mvalue := wdata >> bp.textra.mvaluePos
}
if (coreParams.scontextWidth > 0) {
bp.textra.sselect := wdata(bp.textra.sselectPos)
bp.textra.svalue := wdata >> bp.textra.svaluePos
}
}
when (decoded_addr(CSRs.tdata1)) {
bp.control := wdata.asTypeOf(bp.control)
val prevChain = if (i == 0) false.B else reg_bp(i-1).control.chain
val prevDMode = if (i == 0) false.B else reg_bp(i-1).control.dmode
val nextChain = if (i >= nBreakpoints-1) true.B else reg_bp(i+1).control.chain
val nextDMode = if (i >= nBreakpoints-1) true.B else reg_bp(i+1).control.dmode
val newBPC = readModifyWriteCSR(io.rw.cmd, bp.control.asUInt, io.rw.wdata).asTypeOf(bp.control)
val dMode = newBPC.dmode && reg_debug && (prevDMode || !prevChain)
bp.control.dmode := dMode
when (dMode || (newBPC.action > 1.U)) { bp.control.action := newBPC.action }.otherwise { bp.control.action := 0.U }
bp.control.chain := newBPC.chain && !(prevChain || nextChain) && (dMode || !nextDMode)
}
}
}
}
reg_mcontext.foreach { r => when (decoded_addr(CSRs.mcontext)) { r := wdata }}
reg_scontext.foreach { r => when (decoded_addr(CSRs.scontext)) { r := wdata }}
if (reg_pmp.nonEmpty) for (((pmp, next), i) <- (reg_pmp zip (reg_pmp.tail :+ reg_pmp.last)).zipWithIndex) {
require(xLen % pmp.cfg.getWidth == 0)
when (decoded_addr(CSRs.pmpcfg0 + pmpCfgIndex(i)) && !pmp.cfgLocked) {
val newCfg = (wdata >> ((i * pmp.cfg.getWidth) % xLen)).asTypeOf(new PMPConfig())
pmp.cfg := newCfg
// disallow unreadable but writable PMPs
pmp.cfg.w := newCfg.w && newCfg.r
// can't select a=NA4 with coarse-grained PMPs
if (pmpGranularity.log2 > PMP.lgAlign)
pmp.cfg.a := Cat(newCfg.a(1), newCfg.a.orR)
}
when (decoded_addr(CSRs.pmpaddr0 + i) && !pmp.addrLocked(next)) {
pmp.addr := wdata
}
}
def writeCustomCSR(io: CustomCSRIO, csr: CustomCSR, reg: UInt) = {
val mask = csr.mask.U(xLen.W)
when (decoded_addr(csr.id)) {
reg := (wdata & mask) | (reg & ~mask)
io.wen := true.B
}
}
for ((io, csr, reg) <- (io.customCSRs, customCSRs, reg_custom).zipped) {
writeCustomCSR(io, csr, reg)
}
for ((io, csr, reg) <- (io.roccCSRs, roccCSRs, reg_rocc).zipped) {
writeCustomCSR(io, csr, reg)
}
if (usingVector) {
when (decoded_addr(CSRs.vstart)) { set_vs_dirty := true.B; reg_vstart.get := wdata }
when (decoded_addr(CSRs.vxrm)) { set_vs_dirty := true.B; reg_vxrm.get := wdata }
when (decoded_addr(CSRs.vxsat)) { set_vs_dirty := true.B; reg_vxsat.get := wdata }
when (decoded_addr(CSRs.vcsr)) {
set_vs_dirty := true.B
reg_vxsat.get := wdata
reg_vxrm.get := wdata >> 1
}
}
}
def setCustomCSR(io: CustomCSRIO, csr: CustomCSR, reg: UInt) = {
val mask = csr.mask.U(xLen.W)
when (io.set) {
reg := (io.sdata & mask) | (reg & ~mask)
}
}
for ((io, csr, reg) <- (io.customCSRs, customCSRs, reg_custom).zipped) {
setCustomCSR(io, csr, reg)
}
for ((io, csr, reg) <- (io.roccCSRs, roccCSRs, reg_rocc).zipped) {
setCustomCSR(io, csr, reg)
}
io.vector.map { vio =>
when (vio.set_vconfig.valid) {
// user of CSRFile is responsible for set_vs_dirty in this case
assert(vio.set_vconfig.bits.vl <= vio.set_vconfig.bits.vtype.vlMax)
reg_vconfig.get := vio.set_vconfig.bits
}
when (vio.set_vstart.valid) {
set_vs_dirty := true.B
reg_vstart.get := vio.set_vstart.bits
}
vio.vstart := reg_vstart.get
vio.vconfig := reg_vconfig.get
vio.vxrm := reg_vxrm.get
when (reset.asBool) {
reg_vconfig.get.vl := 0.U
reg_vconfig.get.vtype := 0.U.asTypeOf(new VType)
reg_vconfig.get.vtype.vill := true.B
}
}
when(reset.asBool) {
reg_satp.mode := 0.U
reg_vsatp.mode := 0.U
reg_hgatp.mode := 0.U
}
if (!usingVM) {
reg_satp.mode := 0.U
reg_satp.ppn := 0.U
reg_satp.asid := 0.U
}
if (!usingHypervisor) {
reg_vsatp.mode := 0.U
reg_vsatp.ppn := 0.U
reg_vsatp.asid := 0.U
reg_hgatp.mode := 0.U
reg_hgatp.ppn := 0.U
reg_hgatp.asid := 0.U
}
if (!(asIdBits > 0)) {
reg_satp.asid := 0.U
reg_vsatp.asid := 0.U
}
if (!(vmIdBits > 0)) {
reg_hgatp.asid := 0.U
}
reg_vsstatus.xs := (if (usingRoCC) 3.U else 0.U)
if (nBreakpoints <= 1) reg_tselect := 0.U
for (bpc <- reg_bp map {_.control}) {
bpc.ttype := bpc.tType.U
bpc.maskmax := bpc.maskMax.U
bpc.reserved := 0.U
bpc.zero := 0.U
bpc.h := false.B
if (!usingSupervisor) bpc.s := false.B
if (!usingUser) bpc.u := false.B
if (!usingSupervisor && !usingUser) bpc.m := true.B
when (reset.asBool) {
bpc.action := 0.U
bpc.dmode := false.B
bpc.chain := false.B
bpc.r := false.B
bpc.w := false.B
bpc.x := false.B
}
}
for (bpx <- reg_bp map {_.textra}) {
if (coreParams.mcontextWidth == 0) bpx.mselect := false.B
if (coreParams.scontextWidth == 0) bpx.sselect := false.B
}
for (bp <- reg_bp drop nBreakpoints)
bp := 0.U.asTypeOf(new BP())
for (pmp <- reg_pmp) {
pmp.cfg.res := 0.U
when (reset.asBool) { pmp.reset() }
}
for (((t, insn), i) <- (io.trace zip io.inst).zipWithIndex) {
t.exception := io.retire >= i.U && exception
t.valid := io.retire > i.U || t.exception
t.insn := insn
t.iaddr := io.pc
t.priv := Cat(reg_debug, reg_mstatus.prv)
t.cause := cause
t.interrupt := cause(xLen-1)
t.tval := io.tval
t.wdata.foreach(_ := DontCare)
}
def chooseInterrupt(masksIn: Seq[UInt]): (Bool, UInt) = {
val nonstandard = supported_interrupts.getWidth-1 to 12 by -1
// MEI, MSI, MTI, SEI, SSI, STI, VSEI, VSSI, VSTI, UEI, USI, UTI
val standard = Seq(11, 3, 7, 9, 1, 5, 10, 2, 6, 8, 0, 4)
val priority = nonstandard ++ standard
val masks = masksIn.reverse
val any = masks.flatMap(m => priority.filter(_ < m.getWidth).map(i => m(i))).reduce(_||_)
val which = PriorityMux(masks.flatMap(m => priority.filter(_ < m.getWidth).map(i => (m(i), i.U))))
(any, which)
}
def readModifyWriteCSR(cmd: UInt, rdata: UInt, wdata: UInt) = {
(Mux(cmd(1), rdata, 0.U) | wdata) & ~Mux(cmd(1,0).andR, wdata, 0.U)
}
def legalizePrivilege(priv: UInt): UInt =
if (usingSupervisor) Mux(priv === PRV.H.U, PRV.U.U, priv)
else if (usingUser) Fill(2, priv(0))
else PRV.M.U
def trimPrivilege(priv: UInt): UInt =
if (usingSupervisor) priv
else legalizePrivilege(priv)
def writeCounter(lo: Int, ctr: WideCounter, wdata: UInt) = {
if (xLen == 32) {
val hi = lo + CSRs.mcycleh - CSRs.mcycle
when (decoded_addr(lo)) { ctr := Cat(ctr(ctr.getWidth-1, 32), wdata) }
when (decoded_addr(hi)) { ctr := Cat(wdata(ctr.getWidth-33, 0), ctr(31, 0)) }
} else {
when (decoded_addr(lo)) { ctr := wdata(ctr.getWidth-1, 0) }
}
}
def formEPC(x: UInt) = ~(~x | (if (usingCompressed) 1.U else 3.U))
def readEPC(x: UInt) = ~(~x | Mux(reg_misa('c' - 'a'), 1.U, 3.U))
def formTVec(x: UInt) = x andNot Mux(x(0), ((((BigInt(1) << mtvecInterruptAlign) - 1) << mtvecBaseAlign) | 2).U, 2.U)
def isaStringToMask(s: String) = s.map(x => 1 << (x - 'A')).foldLeft(0)(_|_)
def formFS(fs: UInt) = if (coreParams.haveFSDirty) fs else Fill(2, fs.orR)
def formVS(vs: UInt) = if (usingVector) vs else 0.U
}
| module CSRFile( // @[CSR.scala:377:7]
input clock, // @[CSR.scala:377:7]
input reset, // @[CSR.scala:377:7]
input io_ungated_clock, // @[CSR.scala:384:14]
input io_interrupts_debug, // @[CSR.scala:384:14]
input io_interrupts_mtip, // @[CSR.scala:384:14]
input io_interrupts_msip, // @[CSR.scala:384:14]
input io_interrupts_meip, // @[CSR.scala:384:14]
input io_interrupts_seip, // @[CSR.scala:384:14]
input [2:0] io_hartid, // @[CSR.scala:384:14]
input [11:0] io_rw_addr, // @[CSR.scala:384:14]
input [2:0] io_rw_cmd, // @[CSR.scala:384:14]
output [63:0] io_rw_rdata, // @[CSR.scala:384:14]
input [63:0] io_rw_wdata, // @[CSR.scala:384:14]
input [31:0] io_decode_0_inst, // @[CSR.scala:384:14]
output io_decode_0_fp_illegal, // @[CSR.scala:384:14]
output io_decode_0_fp_csr, // @[CSR.scala:384:14]
output io_decode_0_read_illegal, // @[CSR.scala:384:14]
output io_decode_0_write_illegal, // @[CSR.scala:384:14]
output io_decode_0_write_flush, // @[CSR.scala:384:14]
output io_decode_0_system_illegal, // @[CSR.scala:384:14]
output io_decode_0_virtual_access_illegal, // @[CSR.scala:384:14]
output io_decode_0_virtual_system_illegal, // @[CSR.scala:384:14]
output io_csr_stall, // @[CSR.scala:384:14]
output io_eret, // @[CSR.scala:384:14]
output io_singleStep, // @[CSR.scala:384:14]
output io_status_debug, // @[CSR.scala:384:14]
output io_status_cease, // @[CSR.scala:384:14]
output io_status_wfi, // @[CSR.scala:384:14]
output [31:0] io_status_isa, // @[CSR.scala:384:14]
output [1:0] io_status_dprv, // @[CSR.scala:384:14]
output io_status_dv, // @[CSR.scala:384:14]
output [1:0] io_status_prv, // @[CSR.scala:384:14]
output io_status_v, // @[CSR.scala:384:14]
output io_status_sd, // @[CSR.scala:384:14]
output io_status_mpv, // @[CSR.scala:384:14]
output io_status_gva, // @[CSR.scala:384:14]
output io_status_tsr, // @[CSR.scala:384:14]
output io_status_tw, // @[CSR.scala:384:14]
output io_status_tvm, // @[CSR.scala:384:14]
output io_status_mxr, // @[CSR.scala:384:14]
output io_status_sum, // @[CSR.scala:384:14]
output io_status_mprv, // @[CSR.scala:384:14]
output [1:0] io_status_fs, // @[CSR.scala:384:14]
output [1:0] io_status_mpp, // @[CSR.scala:384:14]
output io_status_spp, // @[CSR.scala:384:14]
output io_status_mpie, // @[CSR.scala:384:14]
output io_status_spie, // @[CSR.scala:384:14]
output io_status_mie, // @[CSR.scala:384:14]
output io_status_sie, // @[CSR.scala:384:14]
output io_hstatus_spvp, // @[CSR.scala:384:14]
output io_hstatus_spv, // @[CSR.scala:384:14]
output io_hstatus_gva, // @[CSR.scala:384:14]
output io_gstatus_debug, // @[CSR.scala:384:14]
output io_gstatus_cease, // @[CSR.scala:384:14]
output io_gstatus_wfi, // @[CSR.scala:384:14]
output [31:0] io_gstatus_isa, // @[CSR.scala:384:14]
output [1:0] io_gstatus_dprv, // @[CSR.scala:384:14]
output io_gstatus_dv, // @[CSR.scala:384:14]
output [1:0] io_gstatus_prv, // @[CSR.scala:384:14]
output io_gstatus_v, // @[CSR.scala:384:14]
output io_gstatus_sd, // @[CSR.scala:384:14]
output [22:0] io_gstatus_zero2, // @[CSR.scala:384:14]
output io_gstatus_mpv, // @[CSR.scala:384:14]
output io_gstatus_gva, // @[CSR.scala:384:14]
output io_gstatus_mbe, // @[CSR.scala:384:14]
output io_gstatus_sbe, // @[CSR.scala:384:14]
output [1:0] io_gstatus_sxl, // @[CSR.scala:384:14]
output [7:0] io_gstatus_zero1, // @[CSR.scala:384:14]
output io_gstatus_tsr, // @[CSR.scala:384:14]
output io_gstatus_tw, // @[CSR.scala:384:14]
output io_gstatus_tvm, // @[CSR.scala:384:14]
output io_gstatus_mxr, // @[CSR.scala:384:14]
output io_gstatus_sum, // @[CSR.scala:384:14]
output io_gstatus_mprv, // @[CSR.scala:384:14]
output [1:0] io_gstatus_fs, // @[CSR.scala:384:14]
output [1:0] io_gstatus_mpp, // @[CSR.scala:384:14]
output [1:0] io_gstatus_vs, // @[CSR.scala:384:14]
output io_gstatus_spp, // @[CSR.scala:384:14]
output io_gstatus_mpie, // @[CSR.scala:384:14]
output io_gstatus_ube, // @[CSR.scala:384:14]
output io_gstatus_spie, // @[CSR.scala:384:14]
output io_gstatus_upie, // @[CSR.scala:384:14]
output io_gstatus_mie, // @[CSR.scala:384:14]
output io_gstatus_hie, // @[CSR.scala:384:14]
output io_gstatus_sie, // @[CSR.scala:384:14]
output io_gstatus_uie, // @[CSR.scala:384:14]
output [3:0] io_ptbr_mode, // @[CSR.scala:384:14]
output [43:0] io_ptbr_ppn, // @[CSR.scala:384:14]
output [39:0] io_evec, // @[CSR.scala:384:14]
input io_exception, // @[CSR.scala:384:14]
input io_retire, // @[CSR.scala:384:14]
input [63:0] io_cause, // @[CSR.scala:384:14]
input [39:0] io_pc, // @[CSR.scala:384:14]
input [39:0] io_tval, // @[CSR.scala:384:14]
input [39:0] io_htval, // @[CSR.scala:384:14]
input io_mhtinst_read_pseudo, // @[CSR.scala:384:14]
input io_gva, // @[CSR.scala:384:14]
output [63:0] io_time, // @[CSR.scala:384:14]
output [2:0] io_fcsr_rm, // @[CSR.scala:384:14]
input io_fcsr_flags_valid, // @[CSR.scala:384:14]
input [4:0] io_fcsr_flags_bits, // @[CSR.scala:384:14]
output io_interrupt, // @[CSR.scala:384:14]
output [63:0] io_interrupt_cause, // @[CSR.scala:384:14]
output io_bp_0_control_dmode, // @[CSR.scala:384:14]
output io_bp_0_control_action, // @[CSR.scala:384:14]
output [1:0] io_bp_0_control_tmatch, // @[CSR.scala:384:14]
output io_bp_0_control_m, // @[CSR.scala:384:14]
output io_bp_0_control_s, // @[CSR.scala:384:14]
output io_bp_0_control_u, // @[CSR.scala:384:14]
output io_bp_0_control_x, // @[CSR.scala:384:14]
output io_bp_0_control_w, // @[CSR.scala:384:14]
output io_bp_0_control_r, // @[CSR.scala:384:14]
output [38:0] io_bp_0_address, // @[CSR.scala:384:14]
output [47:0] io_bp_0_textra_pad2, // @[CSR.scala:384:14]
output io_bp_0_textra_pad1, // @[CSR.scala:384:14]
output io_pmp_0_cfg_l, // @[CSR.scala:384:14]
output [1:0] io_pmp_0_cfg_a, // @[CSR.scala:384:14]
output io_pmp_0_cfg_x, // @[CSR.scala:384:14]
output io_pmp_0_cfg_w, // @[CSR.scala:384:14]
output io_pmp_0_cfg_r, // @[CSR.scala:384:14]
output [29:0] io_pmp_0_addr, // @[CSR.scala:384:14]
output [31:0] io_pmp_0_mask, // @[CSR.scala:384:14]
output io_pmp_1_cfg_l, // @[CSR.scala:384:14]
output [1:0] io_pmp_1_cfg_a, // @[CSR.scala:384:14]
output io_pmp_1_cfg_x, // @[CSR.scala:384:14]
output io_pmp_1_cfg_w, // @[CSR.scala:384:14]
output io_pmp_1_cfg_r, // @[CSR.scala:384:14]
output [29:0] io_pmp_1_addr, // @[CSR.scala:384:14]
output [31:0] io_pmp_1_mask, // @[CSR.scala:384:14]
output io_pmp_2_cfg_l, // @[CSR.scala:384:14]
output [1:0] io_pmp_2_cfg_a, // @[CSR.scala:384:14]
output io_pmp_2_cfg_x, // @[CSR.scala:384:14]
output io_pmp_2_cfg_w, // @[CSR.scala:384:14]
output io_pmp_2_cfg_r, // @[CSR.scala:384:14]
output [29:0] io_pmp_2_addr, // @[CSR.scala:384:14]
output [31:0] io_pmp_2_mask, // @[CSR.scala:384:14]
output io_pmp_3_cfg_l, // @[CSR.scala:384:14]
output [1:0] io_pmp_3_cfg_a, // @[CSR.scala:384:14]
output io_pmp_3_cfg_x, // @[CSR.scala:384:14]
output io_pmp_3_cfg_w, // @[CSR.scala:384:14]
output io_pmp_3_cfg_r, // @[CSR.scala:384:14]
output [29:0] io_pmp_3_addr, // @[CSR.scala:384:14]
output [31:0] io_pmp_3_mask, // @[CSR.scala:384:14]
output io_pmp_4_cfg_l, // @[CSR.scala:384:14]
output [1:0] io_pmp_4_cfg_a, // @[CSR.scala:384:14]
output io_pmp_4_cfg_x, // @[CSR.scala:384:14]
output io_pmp_4_cfg_w, // @[CSR.scala:384:14]
output io_pmp_4_cfg_r, // @[CSR.scala:384:14]
output [29:0] io_pmp_4_addr, // @[CSR.scala:384:14]
output [31:0] io_pmp_4_mask, // @[CSR.scala:384:14]
output io_pmp_5_cfg_l, // @[CSR.scala:384:14]
output [1:0] io_pmp_5_cfg_a, // @[CSR.scala:384:14]
output io_pmp_5_cfg_x, // @[CSR.scala:384:14]
output io_pmp_5_cfg_w, // @[CSR.scala:384:14]
output io_pmp_5_cfg_r, // @[CSR.scala:384:14]
output [29:0] io_pmp_5_addr, // @[CSR.scala:384:14]
output [31:0] io_pmp_5_mask, // @[CSR.scala:384:14]
output io_pmp_6_cfg_l, // @[CSR.scala:384:14]
output [1:0] io_pmp_6_cfg_a, // @[CSR.scala:384:14]
output io_pmp_6_cfg_x, // @[CSR.scala:384:14]
output io_pmp_6_cfg_w, // @[CSR.scala:384:14]
output io_pmp_6_cfg_r, // @[CSR.scala:384:14]
output [29:0] io_pmp_6_addr, // @[CSR.scala:384:14]
output [31:0] io_pmp_6_mask, // @[CSR.scala:384:14]
output io_pmp_7_cfg_l, // @[CSR.scala:384:14]
output [1:0] io_pmp_7_cfg_a, // @[CSR.scala:384:14]
output io_pmp_7_cfg_x, // @[CSR.scala:384:14]
output io_pmp_7_cfg_w, // @[CSR.scala:384:14]
output io_pmp_7_cfg_r, // @[CSR.scala:384:14]
output [29:0] io_pmp_7_addr, // @[CSR.scala:384:14]
output [31:0] io_pmp_7_mask, // @[CSR.scala:384:14]
output io_inhibit_cycle, // @[CSR.scala:384:14]
input [31:0] io_inst_0, // @[CSR.scala:384:14]
output io_trace_0_valid, // @[CSR.scala:384:14]
output [39:0] io_trace_0_iaddr, // @[CSR.scala:384:14]
output [31:0] io_trace_0_insn, // @[CSR.scala:384:14]
output [2:0] io_trace_0_priv, // @[CSR.scala:384:14]
output io_trace_0_exception, // @[CSR.scala:384:14]
output io_trace_0_interrupt, // @[CSR.scala:384:14]
output [63:0] io_trace_0_cause, // @[CSR.scala:384:14]
output [39:0] io_trace_0_tval, // @[CSR.scala:384:14]
output io_customCSRs_0_ren, // @[CSR.scala:384:14]
output io_customCSRs_0_wen, // @[CSR.scala:384:14]
output [63:0] io_customCSRs_0_wdata, // @[CSR.scala:384:14]
output [63:0] io_customCSRs_0_value, // @[CSR.scala:384:14]
output io_customCSRs_1_ren, // @[CSR.scala:384:14]
output io_customCSRs_1_wen, // @[CSR.scala:384:14]
output [63:0] io_customCSRs_1_wdata, // @[CSR.scala:384:14]
output [63:0] io_customCSRs_1_value, // @[CSR.scala:384:14]
output io_customCSRs_2_ren, // @[CSR.scala:384:14]
output io_customCSRs_2_wen, // @[CSR.scala:384:14]
output [63:0] io_customCSRs_2_wdata, // @[CSR.scala:384:14]
output [63:0] io_customCSRs_2_value, // @[CSR.scala:384:14]
output io_customCSRs_3_ren, // @[CSR.scala:384:14]
output io_customCSRs_3_wen, // @[CSR.scala:384:14]
output [63:0] io_customCSRs_3_wdata, // @[CSR.scala:384:14]
output [63:0] io_customCSRs_3_value // @[CSR.scala:384:14]
);
wire io_status_sie_0; // @[CSR.scala:377:7]
wire io_status_spie_0; // @[CSR.scala:377:7]
wire io_status_spp_0; // @[CSR.scala:377:7]
wire [1:0] io_status_fs_0; // @[CSR.scala:377:7]
wire io_status_sum_0; // @[CSR.scala:377:7]
wire io_status_mxr_0; // @[CSR.scala:377:7]
wire io_status_sd_0; // @[CSR.scala:377:7]
wire io_ungated_clock_0 = io_ungated_clock; // @[CSR.scala:377:7]
wire io_interrupts_debug_0 = io_interrupts_debug; // @[CSR.scala:377:7]
wire io_interrupts_mtip_0 = io_interrupts_mtip; // @[CSR.scala:377:7]
wire io_interrupts_msip_0 = io_interrupts_msip; // @[CSR.scala:377:7]
wire io_interrupts_meip_0 = io_interrupts_meip; // @[CSR.scala:377:7]
wire io_interrupts_seip_0 = io_interrupts_seip; // @[CSR.scala:377:7]
wire [2:0] io_hartid_0 = io_hartid; // @[CSR.scala:377:7]
wire [11:0] io_rw_addr_0 = io_rw_addr; // @[CSR.scala:377:7]
wire [2:0] io_rw_cmd_0 = io_rw_cmd; // @[CSR.scala:377:7]
wire [63:0] io_rw_wdata_0 = io_rw_wdata; // @[CSR.scala:377:7]
wire [31:0] io_decode_0_inst_0 = io_decode_0_inst; // @[CSR.scala:377:7]
wire io_exception_0 = io_exception; // @[CSR.scala:377:7]
wire io_retire_0 = io_retire; // @[CSR.scala:377:7]
wire [63:0] io_cause_0 = io_cause; // @[CSR.scala:377:7]
wire [39:0] io_pc_0 = io_pc; // @[CSR.scala:377:7]
wire [39:0] io_tval_0 = io_tval; // @[CSR.scala:377:7]
wire [39:0] io_htval_0 = io_htval; // @[CSR.scala:377:7]
wire io_mhtinst_read_pseudo_0 = io_mhtinst_read_pseudo; // @[CSR.scala:377:7]
wire io_gva_0 = io_gva; // @[CSR.scala:377:7]
wire io_fcsr_flags_valid_0 = io_fcsr_flags_valid; // @[CSR.scala:377:7]
wire [4:0] io_fcsr_flags_bits_0 = io_fcsr_flags_bits; // @[CSR.scala:377:7]
wire [31:0] io_inst_0_0 = io_inst_0; // @[CSR.scala:377:7]
wire io_decode_0_vector_illegal = 1'h1; // @[CSR.scala:377:7]
wire io_decode_0_rocc_illegal = 1'h1; // @[CSR.scala:377:7]
wire sup_meip = 1'h1; // @[CSR.scala:406:19]
wire sup_seip = 1'h1; // @[CSR.scala:406:19]
wire sup_mtip = 1'h1; // @[CSR.scala:406:19]
wire sup_stip = 1'h1; // @[CSR.scala:406:19]
wire sup_msip = 1'h1; // @[CSR.scala:406:19]
wire sup_ssip = 1'h1; // @[CSR.scala:406:19]
wire del_seip = 1'h1; // @[CSR.scala:426:26]
wire del_stip = 1'h1; // @[CSR.scala:426:26]
wire del_ssip = 1'h1; // @[CSR.scala:426:26]
wire read_mnstatus_mie = 1'h1; // @[CSR.scala:675:31]
wire sie_mask_sgeip_mask_sgeip = 1'h1; // @[CSR.scala:748:30]
wire _allow_wfi_T_4 = 1'h1; // @[CSR.scala:906:112]
wire _allow_wfi_T_5 = 1'h1; // @[CSR.scala:906:109]
wire allow_hfence_vvma = 1'h1; // @[CSR.scala:908:50]
wire allow_hlsv = 1'h1; // @[CSR.scala:909:43]
wire _allow_counter_T_11 = 1'h1; // @[CSR.scala:914:8]
wire _allow_counter_T_13 = 1'h1; // @[CSR.scala:914:27]
wire _allow_counter_T_16 = 1'h1; // @[CSR.scala:914:45]
wire _io_decode_0_fp_illegal_T_1 = 1'h1; // @[CSR.scala:915:83]
wire _io_decode_0_vector_illegal_T = 1'h1; // @[CSR.scala:916:43]
wire _io_decode_0_vector_illegal_T_1 = 1'h1; // @[CSR.scala:916:87]
wire _io_decode_0_vector_illegal_T_3 = 1'h1; // @[CSR.scala:916:51]
wire _io_decode_0_vector_illegal_T_6 = 1'h1; // @[CSR.scala:916:95]
wire _io_decode_0_rocc_illegal_T = 1'h1; // @[CSR.scala:919:41]
wire _io_decode_0_rocc_illegal_T_1 = 1'h1; // @[CSR.scala:919:85]
wire _io_decode_0_rocc_illegal_T_3 = 1'h1; // @[CSR.scala:919:49]
wire _io_decode_0_rocc_illegal_T_6 = 1'h1; // @[CSR.scala:919:93]
wire _en_T_7 = 1'h1; // @[CSR.scala:1096:71]
wire delegable_1 = 1'h1; // @[CSR.scala:1097:65]
wire _en_T_19 = 1'h1; // @[CSR.scala:1096:71]
wire _en_T_31 = 1'h1; // @[CSR.scala:1096:71]
wire delegable_5 = 1'h1; // @[CSR.scala:1097:65]
wire _en_T_43 = 1'h1; // @[CSR.scala:1096:71]
wire _en_T_55 = 1'h1; // @[CSR.scala:1096:71]
wire delegable_9 = 1'h1; // @[CSR.scala:1097:65]
wire _en_T_67 = 1'h1; // @[CSR.scala:1096:71]
wire delegable_16 = 1'h1; // @[CSR.scala:1109:67]
wire delegable_18 = 1'h1; // @[CSR.scala:1109:67]
wire delegable_19 = 1'h1; // @[CSR.scala:1109:67]
wire delegable_20 = 1'h1; // @[CSR.scala:1109:67]
wire delegable_22 = 1'h1; // @[CSR.scala:1109:67]
wire delegable_24 = 1'h1; // @[CSR.scala:1109:67]
wire delegable_27 = 1'h1; // @[CSR.scala:1109:67]
wire delegable_28 = 1'h1; // @[CSR.scala:1109:67]
wire delegable_29 = 1'h1; // @[CSR.scala:1109:67]
wire _csr_wen_T_5 = 1'h1; // @[CSR.scala:1222:59]
wire _dMode_T_1 = 1'h1; // @[CSR.scala:1478:68]
wire _dMode_T_2 = 1'h1; // @[CSR.scala:1478:65]
wire _reg_bp_0_control_chain_T = 1'h1; // @[CSR.scala:1481:61]
wire _dMode_T_4 = 1'h1; // @[CSR.scala:1478:68]
wire _dMode_T_5 = 1'h1; // @[CSR.scala:1478:65]
wire _reg_bp_1_control_chain_T = 1'h1; // @[CSR.scala:1481:61]
wire _io_trace_0_exception_T = 1'h1; // @[CSR.scala:1620:30]
wire [22:0] io_status_zero2 = 23'h0; // @[CSR.scala:377:7]
wire [22:0] io_gstatus_zero2_0 = 23'h0; // @[CSR.scala:377:7]
wire [22:0] _reset_mstatus_WIRE_zero2 = 23'h0; // @[CSR.scala:391:47]
wire [22:0] reset_mstatus_zero2 = 23'h0; // @[CSR.scala:391:34]
wire [22:0] _read_sstatus_WIRE_zero2 = 23'h0; // @[CSR.scala:755:48]
wire [22:0] read_sstatus_zero2 = 23'h0; // @[CSR.scala:755:35]
wire io_decode_0_vector_csr = 1'h0; // @[CSR.scala:377:7]
wire io_rw_stall = 1'h0; // @[CSR.scala:377:7]
wire io_status_mbe = 1'h0; // @[CSR.scala:377:7]
wire io_status_sbe = 1'h0; // @[CSR.scala:377:7]
wire io_status_sd_rv32 = 1'h0; // @[CSR.scala:377:7]
wire io_status_ube = 1'h0; // @[CSR.scala:377:7]
wire io_status_upie = 1'h0; // @[CSR.scala:377:7]
wire io_status_hie = 1'h0; // @[CSR.scala:377:7]
wire io_status_uie = 1'h0; // @[CSR.scala:377:7]
wire io_hstatus_vtsr = 1'h0; // @[CSR.scala:377:7]
wire io_hstatus_vtw = 1'h0; // @[CSR.scala:377:7]
wire io_hstatus_vtvm = 1'h0; // @[CSR.scala:377:7]
wire io_hstatus_hu = 1'h0; // @[CSR.scala:377:7]
wire io_hstatus_vsbe = 1'h0; // @[CSR.scala:377:7]
wire io_gstatus_debug_0 = 1'h0; // @[CSR.scala:377:7]
wire io_gstatus_cease_0 = 1'h0; // @[CSR.scala:377:7]
wire io_gstatus_wfi_0 = 1'h0; // @[CSR.scala:377:7]
wire io_gstatus_dv_0 = 1'h0; // @[CSR.scala:377:7]
wire io_gstatus_v_0 = 1'h0; // @[CSR.scala:377:7]
wire io_gstatus_mpv_0 = 1'h0; // @[CSR.scala:377:7]
wire io_gstatus_gva_0 = 1'h0; // @[CSR.scala:377:7]
wire io_gstatus_mbe_0 = 1'h0; // @[CSR.scala:377:7]
wire io_gstatus_sbe_0 = 1'h0; // @[CSR.scala:377:7]
wire io_gstatus_sd_rv32 = 1'h0; // @[CSR.scala:377:7]
wire io_gstatus_tsr_0 = 1'h0; // @[CSR.scala:377:7]
wire io_gstatus_tw_0 = 1'h0; // @[CSR.scala:377:7]
wire io_gstatus_tvm_0 = 1'h0; // @[CSR.scala:377:7]
wire io_gstatus_mxr_0 = 1'h0; // @[CSR.scala:377:7]
wire io_gstatus_sum_0 = 1'h0; // @[CSR.scala:377:7]
wire io_gstatus_mprv_0 = 1'h0; // @[CSR.scala:377:7]
wire io_gstatus_mpie_0 = 1'h0; // @[CSR.scala:377:7]
wire io_gstatus_ube_0 = 1'h0; // @[CSR.scala:377:7]
wire io_gstatus_upie_0 = 1'h0; // @[CSR.scala:377:7]
wire io_gstatus_mie_0 = 1'h0; // @[CSR.scala:377:7]
wire io_gstatus_hie_0 = 1'h0; // @[CSR.scala:377:7]
wire io_gstatus_uie_0 = 1'h0; // @[CSR.scala:377:7]
wire io_rocc_interrupt = 1'h0; // @[CSR.scala:377:7]
wire io_bp_0_control_chain = 1'h0; // @[CSR.scala:377:7]
wire io_bp_0_control_h = 1'h0; // @[CSR.scala:377:7]
wire io_bp_0_textra_mselect = 1'h0; // @[CSR.scala:377:7]
wire io_bp_0_textra_pad1_0 = 1'h0; // @[CSR.scala:377:7]
wire io_bp_0_textra_sselect = 1'h0; // @[CSR.scala:377:7]
wire io_customCSRs_0_stall = 1'h0; // @[CSR.scala:377:7]
wire io_customCSRs_0_set = 1'h0; // @[CSR.scala:377:7]
wire io_customCSRs_1_stall = 1'h0; // @[CSR.scala:377:7]
wire io_customCSRs_1_set = 1'h0; // @[CSR.scala:377:7]
wire io_customCSRs_2_stall = 1'h0; // @[CSR.scala:377:7]
wire io_customCSRs_2_set = 1'h0; // @[CSR.scala:377:7]
wire io_customCSRs_3_stall = 1'h0; // @[CSR.scala:377:7]
wire io_customCSRs_3_set = 1'h0; // @[CSR.scala:377:7]
wire _reset_mstatus_WIRE_debug = 1'h0; // @[CSR.scala:391:47]
wire _reset_mstatus_WIRE_cease = 1'h0; // @[CSR.scala:391:47]
wire _reset_mstatus_WIRE_wfi = 1'h0; // @[CSR.scala:391:47]
wire _reset_mstatus_WIRE_dv = 1'h0; // @[CSR.scala:391:47]
wire _reset_mstatus_WIRE_v = 1'h0; // @[CSR.scala:391:47]
wire _reset_mstatus_WIRE_sd = 1'h0; // @[CSR.scala:391:47]
wire _reset_mstatus_WIRE_mpv = 1'h0; // @[CSR.scala:391:47]
wire _reset_mstatus_WIRE_gva = 1'h0; // @[CSR.scala:391:47]
wire _reset_mstatus_WIRE_mbe = 1'h0; // @[CSR.scala:391:47]
wire _reset_mstatus_WIRE_sbe = 1'h0; // @[CSR.scala:391:47]
wire _reset_mstatus_WIRE_sd_rv32 = 1'h0; // @[CSR.scala:391:47]
wire _reset_mstatus_WIRE_tsr = 1'h0; // @[CSR.scala:391:47]
wire _reset_mstatus_WIRE_tw = 1'h0; // @[CSR.scala:391:47]
wire _reset_mstatus_WIRE_tvm = 1'h0; // @[CSR.scala:391:47]
wire _reset_mstatus_WIRE_mxr = 1'h0; // @[CSR.scala:391:47]
wire _reset_mstatus_WIRE_sum = 1'h0; // @[CSR.scala:391:47]
wire _reset_mstatus_WIRE_mprv = 1'h0; // @[CSR.scala:391:47]
wire _reset_mstatus_WIRE_spp = 1'h0; // @[CSR.scala:391:47]
wire _reset_mstatus_WIRE_mpie = 1'h0; // @[CSR.scala:391:47]
wire _reset_mstatus_WIRE_ube = 1'h0; // @[CSR.scala:391:47]
wire _reset_mstatus_WIRE_spie = 1'h0; // @[CSR.scala:391:47]
wire _reset_mstatus_WIRE_upie = 1'h0; // @[CSR.scala:391:47]
wire _reset_mstatus_WIRE_mie = 1'h0; // @[CSR.scala:391:47]
wire _reset_mstatus_WIRE_hie = 1'h0; // @[CSR.scala:391:47]
wire _reset_mstatus_WIRE_sie = 1'h0; // @[CSR.scala:391:47]
wire _reset_mstatus_WIRE_uie = 1'h0; // @[CSR.scala:391:47]
wire reset_mstatus_debug = 1'h0; // @[CSR.scala:391:34]
wire reset_mstatus_cease = 1'h0; // @[CSR.scala:391:34]
wire reset_mstatus_wfi = 1'h0; // @[CSR.scala:391:34]
wire reset_mstatus_dv = 1'h0; // @[CSR.scala:391:34]
wire reset_mstatus_v = 1'h0; // @[CSR.scala:391:34]
wire reset_mstatus_sd = 1'h0; // @[CSR.scala:391:34]
wire reset_mstatus_mpv = 1'h0; // @[CSR.scala:391:34]
wire reset_mstatus_gva = 1'h0; // @[CSR.scala:391:34]
wire reset_mstatus_mbe = 1'h0; // @[CSR.scala:391:34]
wire reset_mstatus_sbe = 1'h0; // @[CSR.scala:391:34]
wire reset_mstatus_sd_rv32 = 1'h0; // @[CSR.scala:391:34]
wire reset_mstatus_tsr = 1'h0; // @[CSR.scala:391:34]
wire reset_mstatus_tw = 1'h0; // @[CSR.scala:391:34]
wire reset_mstatus_tvm = 1'h0; // @[CSR.scala:391:34]
wire reset_mstatus_mxr = 1'h0; // @[CSR.scala:391:34]
wire reset_mstatus_sum = 1'h0; // @[CSR.scala:391:34]
wire reset_mstatus_mprv = 1'h0; // @[CSR.scala:391:34]
wire reset_mstatus_spp = 1'h0; // @[CSR.scala:391:34]
wire reset_mstatus_mpie = 1'h0; // @[CSR.scala:391:34]
wire reset_mstatus_ube = 1'h0; // @[CSR.scala:391:34]
wire reset_mstatus_spie = 1'h0; // @[CSR.scala:391:34]
wire reset_mstatus_upie = 1'h0; // @[CSR.scala:391:34]
wire reset_mstatus_mie = 1'h0; // @[CSR.scala:391:34]
wire reset_mstatus_hie = 1'h0; // @[CSR.scala:391:34]
wire reset_mstatus_sie = 1'h0; // @[CSR.scala:391:34]
wire reset_mstatus_uie = 1'h0; // @[CSR.scala:391:34]
wire _reset_dcsr_WIRE_ebreakm = 1'h0; // @[CSR.scala:400:44]
wire _reset_dcsr_WIRE_ebreakh = 1'h0; // @[CSR.scala:400:44]
wire _reset_dcsr_WIRE_ebreaks = 1'h0; // @[CSR.scala:400:44]
wire _reset_dcsr_WIRE_ebreaku = 1'h0; // @[CSR.scala:400:44]
wire _reset_dcsr_WIRE_zero2 = 1'h0; // @[CSR.scala:400:44]
wire _reset_dcsr_WIRE_stopcycle = 1'h0; // @[CSR.scala:400:44]
wire _reset_dcsr_WIRE_stoptime = 1'h0; // @[CSR.scala:400:44]
wire _reset_dcsr_WIRE_v = 1'h0; // @[CSR.scala:400:44]
wire _reset_dcsr_WIRE_step = 1'h0; // @[CSR.scala:400:44]
wire reset_dcsr_ebreakm = 1'h0; // @[CSR.scala:400:31]
wire reset_dcsr_ebreakh = 1'h0; // @[CSR.scala:400:31]
wire reset_dcsr_ebreaks = 1'h0; // @[CSR.scala:400:31]
wire reset_dcsr_ebreaku = 1'h0; // @[CSR.scala:400:31]
wire reset_dcsr_zero2 = 1'h0; // @[CSR.scala:400:31]
wire reset_dcsr_stopcycle = 1'h0; // @[CSR.scala:400:31]
wire reset_dcsr_stoptime = 1'h0; // @[CSR.scala:400:31]
wire reset_dcsr_v = 1'h0; // @[CSR.scala:400:31]
wire reset_dcsr_step = 1'h0; // @[CSR.scala:400:31]
wire sup_zero1 = 1'h0; // @[CSR.scala:406:19]
wire sup_debug = 1'h0; // @[CSR.scala:406:19]
wire sup_rocc = 1'h0; // @[CSR.scala:406:19]
wire sup_sgeip = 1'h0; // @[CSR.scala:406:19]
wire sup_vseip = 1'h0; // @[CSR.scala:406:19]
wire sup_ueip = 1'h0; // @[CSR.scala:406:19]
wire sup_vstip = 1'h0; // @[CSR.scala:406:19]
wire sup_utip = 1'h0; // @[CSR.scala:406:19]
wire sup_vssip = 1'h0; // @[CSR.scala:406:19]
wire sup_usip = 1'h0; // @[CSR.scala:406:19]
wire del_zero1 = 1'h0; // @[CSR.scala:426:26]
wire del_debug = 1'h0; // @[CSR.scala:426:26]
wire del_rocc = 1'h0; // @[CSR.scala:426:26]
wire del_sgeip = 1'h0; // @[CSR.scala:426:26]
wire del_meip = 1'h0; // @[CSR.scala:426:26]
wire del_vseip = 1'h0; // @[CSR.scala:426:26]
wire del_ueip = 1'h0; // @[CSR.scala:426:26]
wire del_mtip = 1'h0; // @[CSR.scala:426:26]
wire del_vstip = 1'h0; // @[CSR.scala:426:26]
wire del_utip = 1'h0; // @[CSR.scala:426:26]
wire del_msip = 1'h0; // @[CSR.scala:426:26]
wire del_vssip = 1'h0; // @[CSR.scala:426:26]
wire del_usip = 1'h0; // @[CSR.scala:426:26]
wire hi_hi_hi_hi = 1'h0; // @[CSR.scala:431:10]
wire hi_hi_hi_hi_1 = 1'h0; // @[CSR.scala:431:50]
wire _always_WIRE_zero1 = 1'h0; // @[CSR.scala:471:42]
wire _always_WIRE_debug = 1'h0; // @[CSR.scala:471:42]
wire _always_WIRE_rocc = 1'h0; // @[CSR.scala:471:42]
wire _always_WIRE_sgeip = 1'h0; // @[CSR.scala:471:42]
wire _always_WIRE_meip = 1'h0; // @[CSR.scala:471:42]
wire _always_WIRE_vseip = 1'h0; // @[CSR.scala:471:42]
wire _always_WIRE_seip = 1'h0; // @[CSR.scala:471:42]
wire _always_WIRE_ueip = 1'h0; // @[CSR.scala:471:42]
wire _always_WIRE_mtip = 1'h0; // @[CSR.scala:471:42]
wire _always_WIRE_vstip = 1'h0; // @[CSR.scala:471:42]
wire _always_WIRE_stip = 1'h0; // @[CSR.scala:471:42]
wire _always_WIRE_utip = 1'h0; // @[CSR.scala:471:42]
wire _always_WIRE_msip = 1'h0; // @[CSR.scala:471:42]
wire _always_WIRE_vssip = 1'h0; // @[CSR.scala:471:42]
wire _always_WIRE_ssip = 1'h0; // @[CSR.scala:471:42]
wire _always_WIRE_usip = 1'h0; // @[CSR.scala:471:42]
wire always_zero1 = 1'h0; // @[CSR.scala:471:29]
wire always_debug = 1'h0; // @[CSR.scala:471:29]
wire always_rocc = 1'h0; // @[CSR.scala:471:29]
wire always_sgeip = 1'h0; // @[CSR.scala:471:29]
wire always_meip = 1'h0; // @[CSR.scala:471:29]
wire always_vseip = 1'h0; // @[CSR.scala:471:29]
wire always_seip = 1'h0; // @[CSR.scala:471:29]
wire always_ueip = 1'h0; // @[CSR.scala:471:29]
wire always_mtip = 1'h0; // @[CSR.scala:471:29]
wire always_vstip = 1'h0; // @[CSR.scala:471:29]
wire always_stip = 1'h0; // @[CSR.scala:471:29]
wire always_utip = 1'h0; // @[CSR.scala:471:29]
wire always_msip = 1'h0; // @[CSR.scala:471:29]
wire always_vssip = 1'h0; // @[CSR.scala:471:29]
wire always_ssip = 1'h0; // @[CSR.scala:471:29]
wire always_usip = 1'h0; // @[CSR.scala:471:29]
wire deleg_zero1 = 1'h0; // @[CSR.scala:476:28]
wire deleg_debug = 1'h0; // @[CSR.scala:476:28]
wire deleg_rocc = 1'h0; // @[CSR.scala:476:28]
wire deleg_sgeip = 1'h0; // @[CSR.scala:476:28]
wire deleg_meip = 1'h0; // @[CSR.scala:476:28]
wire deleg_vseip = 1'h0; // @[CSR.scala:476:28]
wire deleg_seip = 1'h0; // @[CSR.scala:476:28]
wire deleg_ueip = 1'h0; // @[CSR.scala:476:28]
wire deleg_mtip = 1'h0; // @[CSR.scala:476:28]
wire deleg_vstip = 1'h0; // @[CSR.scala:476:28]
wire deleg_stip = 1'h0; // @[CSR.scala:476:28]
wire deleg_utip = 1'h0; // @[CSR.scala:476:28]
wire deleg_msip = 1'h0; // @[CSR.scala:476:28]
wire deleg_vssip = 1'h0; // @[CSR.scala:476:28]
wire deleg_ssip = 1'h0; // @[CSR.scala:476:28]
wire deleg_usip = 1'h0; // @[CSR.scala:476:28]
wire hi_hi_hi_hi_2 = 1'h0; // @[CSR.scala:479:12]
wire hi_hi_hi_hi_3 = 1'h0; // @[CSR.scala:479:27]
wire _reset_mnstatus_WIRE_mpv = 1'h0; // @[CSR.scala:516:48]
wire _reset_mnstatus_WIRE_mie = 1'h0; // @[CSR.scala:516:48]
wire reset_mnstatus_mpv = 1'h0; // @[CSR.scala:516:35]
wire reset_mnstatus_mie = 1'h0; // @[CSR.scala:516:35]
wire _reg_menvcfg_WIRE_stce = 1'h0; // @[CSR.scala:525:41]
wire _reg_menvcfg_WIRE_pbmte = 1'h0; // @[CSR.scala:525:41]
wire _reg_menvcfg_WIRE_cbze = 1'h0; // @[CSR.scala:525:41]
wire _reg_menvcfg_WIRE_cbcfe = 1'h0; // @[CSR.scala:525:41]
wire _reg_menvcfg_WIRE_fiom = 1'h0; // @[CSR.scala:525:41]
wire _reg_senvcfg_WIRE_stce = 1'h0; // @[CSR.scala:526:41]
wire _reg_senvcfg_WIRE_pbmte = 1'h0; // @[CSR.scala:526:41]
wire _reg_senvcfg_WIRE_cbze = 1'h0; // @[CSR.scala:526:41]
wire _reg_senvcfg_WIRE_cbcfe = 1'h0; // @[CSR.scala:526:41]
wire _reg_senvcfg_WIRE_fiom = 1'h0; // @[CSR.scala:526:41]
wire _reg_henvcfg_WIRE_stce = 1'h0; // @[CSR.scala:527:41]
wire _reg_henvcfg_WIRE_pbmte = 1'h0; // @[CSR.scala:527:41]
wire _reg_henvcfg_WIRE_cbze = 1'h0; // @[CSR.scala:527:41]
wire _reg_henvcfg_WIRE_cbcfe = 1'h0; // @[CSR.scala:527:41]
wire _reg_henvcfg_WIRE_fiom = 1'h0; // @[CSR.scala:527:41]
wire _reg_hstatus_WIRE_vtsr = 1'h0; // @[CSR.scala:552:41]
wire _reg_hstatus_WIRE_vtw = 1'h0; // @[CSR.scala:552:41]
wire _reg_hstatus_WIRE_vtvm = 1'h0; // @[CSR.scala:552:41]
wire _reg_hstatus_WIRE_hu = 1'h0; // @[CSR.scala:552:41]
wire _reg_hstatus_WIRE_spvp = 1'h0; // @[CSR.scala:552:41]
wire _reg_hstatus_WIRE_spv = 1'h0; // @[CSR.scala:552:41]
wire _reg_hstatus_WIRE_gva = 1'h0; // @[CSR.scala:552:41]
wire _reg_hstatus_WIRE_vsbe = 1'h0; // @[CSR.scala:552:41]
wire read_hvip_hi_hi_hi_hi = 1'h0; // @[CSR.scala:555:27]
wire mip_zero1 = 1'h0; // @[CSR.scala:600:24]
wire mip_debug = 1'h0; // @[CSR.scala:600:24]
wire mip_rocc = 1'h0; // @[CSR.scala:600:24]
wire mip_sgeip = 1'h0; // @[CSR.scala:600:24]
wire mip_vseip = 1'h0; // @[CSR.scala:600:24]
wire mip_ueip = 1'h0; // @[CSR.scala:600:24]
wire mip_vstip = 1'h0; // @[CSR.scala:600:24]
wire mip_utip = 1'h0; // @[CSR.scala:600:24]
wire mip_vssip = 1'h0; // @[CSR.scala:600:24]
wire mip_usip = 1'h0; // @[CSR.scala:600:24]
wire _any_T_47 = 1'h0; // @[CSR.scala:1637:76]
wire _any_T_48 = 1'h0; // @[CSR.scala:1637:76]
wire _any_T_49 = 1'h0; // @[CSR.scala:1637:76]
wire _any_T_50 = 1'h0; // @[CSR.scala:1637:76]
wire _any_T_51 = 1'h0; // @[CSR.scala:1637:76]
wire _any_T_52 = 1'h0; // @[CSR.scala:1637:76]
wire _any_T_53 = 1'h0; // @[CSR.scala:1637:76]
wire _any_T_54 = 1'h0; // @[CSR.scala:1637:76]
wire _any_T_55 = 1'h0; // @[CSR.scala:1637:76]
wire _any_T_56 = 1'h0; // @[CSR.scala:1637:76]
wire _any_T_57 = 1'h0; // @[CSR.scala:1637:76]
wire _any_T_58 = 1'h0; // @[CSR.scala:1637:76]
wire _any_T_59 = 1'h0; // @[CSR.scala:1637:76]
wire _any_T_60 = 1'h0; // @[CSR.scala:1637:76]
wire _any_T_61 = 1'h0; // @[CSR.scala:1637:76]
wire _any_T_62 = 1'h0; // @[CSR.scala:1637:76]
wire _which_T_47 = 1'h0; // @[CSR.scala:1638:91]
wire _which_T_48 = 1'h0; // @[CSR.scala:1638:91]
wire _which_T_49 = 1'h0; // @[CSR.scala:1638:91]
wire _which_T_50 = 1'h0; // @[CSR.scala:1638:91]
wire _which_T_51 = 1'h0; // @[CSR.scala:1638:91]
wire _which_T_52 = 1'h0; // @[CSR.scala:1638:91]
wire _which_T_53 = 1'h0; // @[CSR.scala:1638:91]
wire _which_T_54 = 1'h0; // @[CSR.scala:1638:91]
wire _which_T_55 = 1'h0; // @[CSR.scala:1638:91]
wire _which_T_56 = 1'h0; // @[CSR.scala:1638:91]
wire _which_T_57 = 1'h0; // @[CSR.scala:1638:91]
wire _which_T_58 = 1'h0; // @[CSR.scala:1638:91]
wire _which_T_59 = 1'h0; // @[CSR.scala:1638:91]
wire _which_T_60 = 1'h0; // @[CSR.scala:1638:91]
wire _which_T_61 = 1'h0; // @[CSR.scala:1638:91]
wire _which_T_62 = 1'h0; // @[CSR.scala:1638:91]
wire _io_fiom_T_5 = 1'h0; // @[CSR.scala:631:131]
wire _pmp_mask_base_T_2 = 1'h0; // @[PMP.scala:57:62]
wire _pmp_mask_base_T_5 = 1'h0; // @[PMP.scala:57:62]
wire _pmp_mask_base_T_8 = 1'h0; // @[PMP.scala:57:62]
wire _pmp_mask_base_T_11 = 1'h0; // @[PMP.scala:57:62]
wire _pmp_mask_base_T_14 = 1'h0; // @[PMP.scala:57:62]
wire _pmp_mask_base_T_17 = 1'h0; // @[PMP.scala:57:62]
wire _pmp_mask_base_T_20 = 1'h0; // @[PMP.scala:57:62]
wire _pmp_mask_base_T_23 = 1'h0; // @[PMP.scala:57:62]
wire read_mapping_lo_hi_1 = 1'h0; // @[CSR.scala:657:47]
wire read_mapping_hi_hi_1 = 1'h0; // @[CSR.scala:657:47]
wire _read_mnstatus_WIRE_mpv = 1'h0; // @[CSR.scala:675:44]
wire _read_mnstatus_WIRE_mie = 1'h0; // @[CSR.scala:675:44]
wire read_mnstatus_mpv = 1'h0; // @[CSR.scala:675:31]
wire _sie_mask_sgeip_mask_WIRE_zero1 = 1'h0; // @[CSR.scala:748:43]
wire _sie_mask_sgeip_mask_WIRE_debug = 1'h0; // @[CSR.scala:748:43]
wire _sie_mask_sgeip_mask_WIRE_rocc = 1'h0; // @[CSR.scala:748:43]
wire _sie_mask_sgeip_mask_WIRE_sgeip = 1'h0; // @[CSR.scala:748:43]
wire _sie_mask_sgeip_mask_WIRE_meip = 1'h0; // @[CSR.scala:748:43]
wire _sie_mask_sgeip_mask_WIRE_vseip = 1'h0; // @[CSR.scala:748:43]
wire _sie_mask_sgeip_mask_WIRE_seip = 1'h0; // @[CSR.scala:748:43]
wire _sie_mask_sgeip_mask_WIRE_ueip = 1'h0; // @[CSR.scala:748:43]
wire _sie_mask_sgeip_mask_WIRE_mtip = 1'h0; // @[CSR.scala:748:43]
wire _sie_mask_sgeip_mask_WIRE_vstip = 1'h0; // @[CSR.scala:748:43]
wire _sie_mask_sgeip_mask_WIRE_stip = 1'h0; // @[CSR.scala:748:43]
wire _sie_mask_sgeip_mask_WIRE_utip = 1'h0; // @[CSR.scala:748:43]
wire _sie_mask_sgeip_mask_WIRE_msip = 1'h0; // @[CSR.scala:748:43]
wire _sie_mask_sgeip_mask_WIRE_vssip = 1'h0; // @[CSR.scala:748:43]
wire _sie_mask_sgeip_mask_WIRE_ssip = 1'h0; // @[CSR.scala:748:43]
wire _sie_mask_sgeip_mask_WIRE_usip = 1'h0; // @[CSR.scala:748:43]
wire sie_mask_sgeip_mask_zero1 = 1'h0; // @[CSR.scala:748:30]
wire sie_mask_sgeip_mask_debug = 1'h0; // @[CSR.scala:748:30]
wire sie_mask_sgeip_mask_rocc = 1'h0; // @[CSR.scala:748:30]
wire sie_mask_sgeip_mask_meip = 1'h0; // @[CSR.scala:748:30]
wire sie_mask_sgeip_mask_vseip = 1'h0; // @[CSR.scala:748:30]
wire sie_mask_sgeip_mask_seip = 1'h0; // @[CSR.scala:748:30]
wire sie_mask_sgeip_mask_ueip = 1'h0; // @[CSR.scala:748:30]
wire sie_mask_sgeip_mask_mtip = 1'h0; // @[CSR.scala:748:30]
wire sie_mask_sgeip_mask_vstip = 1'h0; // @[CSR.scala:748:30]
wire sie_mask_sgeip_mask_stip = 1'h0; // @[CSR.scala:748:30]
wire sie_mask_sgeip_mask_utip = 1'h0; // @[CSR.scala:748:30]
wire sie_mask_sgeip_mask_msip = 1'h0; // @[CSR.scala:748:30]
wire sie_mask_sgeip_mask_vssip = 1'h0; // @[CSR.scala:748:30]
wire sie_mask_sgeip_mask_ssip = 1'h0; // @[CSR.scala:748:30]
wire sie_mask_sgeip_mask_usip = 1'h0; // @[CSR.scala:748:30]
wire sie_mask_hi_hi_hi_hi = 1'h0; // @[CSR.scala:750:59]
wire _read_sstatus_WIRE_debug = 1'h0; // @[CSR.scala:755:48]
wire _read_sstatus_WIRE_cease = 1'h0; // @[CSR.scala:755:48]
wire _read_sstatus_WIRE_wfi = 1'h0; // @[CSR.scala:755:48]
wire _read_sstatus_WIRE_dv = 1'h0; // @[CSR.scala:755:48]
wire _read_sstatus_WIRE_v = 1'h0; // @[CSR.scala:755:48]
wire _read_sstatus_WIRE_sd = 1'h0; // @[CSR.scala:755:48]
wire _read_sstatus_WIRE_mpv = 1'h0; // @[CSR.scala:755:48]
wire _read_sstatus_WIRE_gva = 1'h0; // @[CSR.scala:755:48]
wire _read_sstatus_WIRE_mbe = 1'h0; // @[CSR.scala:755:48]
wire _read_sstatus_WIRE_sbe = 1'h0; // @[CSR.scala:755:48]
wire _read_sstatus_WIRE_sd_rv32 = 1'h0; // @[CSR.scala:755:48]
wire _read_sstatus_WIRE_tsr = 1'h0; // @[CSR.scala:755:48]
wire _read_sstatus_WIRE_tw = 1'h0; // @[CSR.scala:755:48]
wire _read_sstatus_WIRE_tvm = 1'h0; // @[CSR.scala:755:48]
wire _read_sstatus_WIRE_mxr = 1'h0; // @[CSR.scala:755:48]
wire _read_sstatus_WIRE_sum = 1'h0; // @[CSR.scala:755:48]
wire _read_sstatus_WIRE_mprv = 1'h0; // @[CSR.scala:755:48]
wire _read_sstatus_WIRE_spp = 1'h0; // @[CSR.scala:755:48]
wire _read_sstatus_WIRE_mpie = 1'h0; // @[CSR.scala:755:48]
wire _read_sstatus_WIRE_ube = 1'h0; // @[CSR.scala:755:48]
wire _read_sstatus_WIRE_spie = 1'h0; // @[CSR.scala:755:48]
wire _read_sstatus_WIRE_upie = 1'h0; // @[CSR.scala:755:48]
wire _read_sstatus_WIRE_mie = 1'h0; // @[CSR.scala:755:48]
wire _read_sstatus_WIRE_hie = 1'h0; // @[CSR.scala:755:48]
wire _read_sstatus_WIRE_sie = 1'h0; // @[CSR.scala:755:48]
wire _read_sstatus_WIRE_uie = 1'h0; // @[CSR.scala:755:48]
wire read_sstatus_debug = 1'h0; // @[CSR.scala:755:35]
wire read_sstatus_cease = 1'h0; // @[CSR.scala:755:35]
wire read_sstatus_wfi = 1'h0; // @[CSR.scala:755:35]
wire read_sstatus_dv = 1'h0; // @[CSR.scala:755:35]
wire read_sstatus_v = 1'h0; // @[CSR.scala:755:35]
wire read_sstatus_mpv = 1'h0; // @[CSR.scala:755:35]
wire read_sstatus_gva = 1'h0; // @[CSR.scala:755:35]
wire read_sstatus_mbe = 1'h0; // @[CSR.scala:755:35]
wire read_sstatus_sbe = 1'h0; // @[CSR.scala:755:35]
wire read_sstatus_sd_rv32 = 1'h0; // @[CSR.scala:755:35]
wire read_sstatus_tsr = 1'h0; // @[CSR.scala:755:35]
wire read_sstatus_tw = 1'h0; // @[CSR.scala:755:35]
wire read_sstatus_tvm = 1'h0; // @[CSR.scala:755:35]
wire read_sstatus_mprv = 1'h0; // @[CSR.scala:755:35]
wire read_sstatus_mpie = 1'h0; // @[CSR.scala:755:35]
wire read_sstatus_ube = 1'h0; // @[CSR.scala:755:35]
wire read_sstatus_upie = 1'h0; // @[CSR.scala:755:35]
wire read_sstatus_mie = 1'h0; // @[CSR.scala:755:35]
wire read_sstatus_hie = 1'h0; // @[CSR.scala:755:35]
wire read_sstatus_uie = 1'h0; // @[CSR.scala:755:35]
wire read_pmp_15_cfg_l = 1'h0; // @[CSR.scala:787:59]
wire read_pmp_15_cfg_x = 1'h0; // @[CSR.scala:787:59]
wire read_pmp_15_cfg_w = 1'h0; // @[CSR.scala:787:59]
wire read_pmp_15_cfg_r = 1'h0; // @[CSR.scala:787:59]
wire _reg_custom_T = 1'h0; // @[CSR.scala:801:16]
wire _reg_custom_T_1 = 1'h0; // @[CSR.scala:801:16]
wire _reg_custom_T_2 = 1'h0; // @[CSR.scala:801:16]
wire _reg_custom_T_3 = 1'h0; // @[CSR.scala:801:16]
wire _allow_counter_T_4 = 1'h0; // @[CSR.scala:913:8]
wire io_decode_0_vector_csr_plaOutput = 1'h0; // @[pla.scala:81:23]
wire _io_decode_0_vector_csr_T = 1'h0; // @[Decode.scala:55:116]
wire _csr_addr_legal_T_3 = 1'h0; // @[CSR.scala:921:25]
wire _csr_addr_legal_T_5 = 1'h0; // @[CSR.scala:921:43]
wire _csr_addr_legal_T_8 = 1'h0; // @[CSR.scala:921:74]
wire io_decode_0_read_illegal_plaOutput_1 = 1'h0; // @[pla.scala:81:23]
wire _io_decode_0_read_illegal_T_16 = 1'h0; // @[Decode.scala:55:116]
wire _io_decode_0_read_illegal_T_17 = 1'h0; // @[CSR.scala:928:43]
wire _io_decode_0_system_illegal_T_20 = 1'h0; // @[CSR.scala:940:25]
wire _io_decode_0_system_illegal_T_21 = 1'h0; // @[CSR.scala:940:22]
wire _io_decode_0_system_illegal_T_23 = 1'h0; // @[CSR.scala:941:18]
wire _io_decode_0_system_illegal_T_24 = 1'h0; // @[CSR.scala:941:15]
wire _io_decode_0_virtual_access_illegal_T_27 = 1'h0; // @[CSR.scala:947:50]
wire _io_decode_0_virtual_system_illegal_T_5 = 1'h0; // @[CSR.scala:953:57]
wire trapToNmiInt = 1'h0; // @[CSR.scala:990:33]
wire _trapToNmiXcpt_T = 1'h0; // @[CSR.scala:991:37]
wire trapToNmiXcpt = 1'h0; // @[CSR.scala:991:34]
wire trapToNmi = 1'h0; // @[CSR.scala:992:32]
wire _nmiTVec_T = 1'h0; // @[CSR.scala:993:21]
wire _nmiTVec_T_1 = 1'h0; // @[CSR.scala:993:58]
wire _io_status_sd_T_1 = 1'h0; // @[CSR.scala:1003:53]
wire _io_status_sd_T_3 = 1'h0; // @[CSR.scala:1003:74]
wire _io_status_sd_rv32_T = 1'h0; // @[CSR.scala:1010:39]
wire _io_gstatus_sd_T_1 = 1'h0; // @[CSR.scala:1016:56]
wire _io_gstatus_sd_rv32_T = 1'h0; // @[CSR.scala:1018:40]
wire _en_T_1 = 1'h0; // @[CSR.scala:1096:71]
wire _en_T_2 = 1'h0; // @[CSR.scala:1096:24]
wire en = 1'h0; // @[CSR.scala:1096:79]
wire delegable = 1'h0; // @[CSR.scala:1097:65]
wire _en_T_13 = 1'h0; // @[CSR.scala:1096:71]
wire _en_T_14 = 1'h0; // @[CSR.scala:1096:24]
wire en_2 = 1'h0; // @[CSR.scala:1096:79]
wire delegable_2 = 1'h0; // @[CSR.scala:1097:65]
wire delegable_3 = 1'h0; // @[CSR.scala:1097:65]
wire _en_T_25 = 1'h0; // @[CSR.scala:1096:71]
wire _en_T_26 = 1'h0; // @[CSR.scala:1096:24]
wire en_4 = 1'h0; // @[CSR.scala:1096:79]
wire delegable_4 = 1'h0; // @[CSR.scala:1097:65]
wire _en_T_37 = 1'h0; // @[CSR.scala:1096:71]
wire _en_T_38 = 1'h0; // @[CSR.scala:1096:24]
wire en_6 = 1'h0; // @[CSR.scala:1096:79]
wire delegable_6 = 1'h0; // @[CSR.scala:1097:65]
wire delegable_7 = 1'h0; // @[CSR.scala:1097:65]
wire _en_T_49 = 1'h0; // @[CSR.scala:1096:71]
wire _en_T_50 = 1'h0; // @[CSR.scala:1096:24]
wire en_8 = 1'h0; // @[CSR.scala:1096:79]
wire delegable_8 = 1'h0; // @[CSR.scala:1097:65]
wire _en_T_61 = 1'h0; // @[CSR.scala:1096:71]
wire _en_T_62 = 1'h0; // @[CSR.scala:1096:24]
wire en_10 = 1'h0; // @[CSR.scala:1096:79]
wire delegable_10 = 1'h0; // @[CSR.scala:1097:65]
wire delegable_11 = 1'h0; // @[CSR.scala:1097:65]
wire _en_T_73 = 1'h0; // @[CSR.scala:1096:71]
wire _en_T_74 = 1'h0; // @[CSR.scala:1096:24]
wire en_12 = 1'h0; // @[CSR.scala:1096:79]
wire delegable_12 = 1'h0; // @[CSR.scala:1097:65]
wire _en_T_79 = 1'h0; // @[CSR.scala:1096:71]
wire _en_T_80 = 1'h0; // @[CSR.scala:1096:24]
wire en_13 = 1'h0; // @[CSR.scala:1096:79]
wire delegable_13 = 1'h0; // @[CSR.scala:1097:65]
wire _en_T_85 = 1'h0; // @[CSR.scala:1096:71]
wire _en_T_86 = 1'h0; // @[CSR.scala:1096:24]
wire en_14 = 1'h0; // @[CSR.scala:1096:79]
wire delegable_14 = 1'h0; // @[CSR.scala:1097:65]
wire _en_T_91 = 1'h0; // @[CSR.scala:1096:71]
wire _en_T_92 = 1'h0; // @[CSR.scala:1096:24]
wire en_15 = 1'h0; // @[CSR.scala:1096:79]
wire delegable_15 = 1'h0; // @[CSR.scala:1097:65]
wire delegable_17 = 1'h0; // @[CSR.scala:1109:67]
wire delegable_21 = 1'h0; // @[CSR.scala:1109:67]
wire delegable_23 = 1'h0; // @[CSR.scala:1109:67]
wire delegable_25 = 1'h0; // @[CSR.scala:1109:67]
wire delegable_26 = 1'h0; // @[CSR.scala:1109:67]
wire _reg_mstatus_v_T = 1'h0; // @[CSR.scala:1123:44]
wire _reg_mstatus_v_T_1 = 1'h0; // @[CSR.scala:1136:42]
wire _reg_mstatus_v_T_3 = 1'h0; // @[CSR.scala:1136:56]
wire _reg_mstatus_v_T_4 = 1'h0; // @[CSR.scala:1141:42]
wire _reg_mstatus_v_T_5 = 1'h0; // @[CSR.scala:1141:82]
wire _reg_mstatus_v_T_6 = 1'h0; // @[CSR.scala:1141:62]
wire _reg_mstatus_mpp_T = 1'h0; // @[CSR.scala:1647:35]
wire _reg_mstatus_mpp_T_1 = 1'h0; // @[CSR.scala:1647:29]
wire _reg_mstatus_v_T_7 = 1'h0; // @[CSR.scala:1150:42]
wire _reg_mstatus_v_T_9 = 1'h0; // @[CSR.scala:1150:61]
wire _io_rw_rdata_T = 1'h0; // @[Mux.scala:30:73]
wire _io_rw_rdata_T_23 = 1'h0; // @[Mux.scala:30:73]
wire _io_rw_rdata_T_24 = 1'h0; // @[Mux.scala:30:73]
wire _io_rw_rdata_T_25 = 1'h0; // @[Mux.scala:30:73]
wire _io_rw_rdata_T_26 = 1'h0; // @[Mux.scala:30:73]
wire _io_rw_rdata_T_27 = 1'h0; // @[Mux.scala:30:73]
wire _io_rw_rdata_T_28 = 1'h0; // @[Mux.scala:30:73]
wire _io_rw_rdata_T_29 = 1'h0; // @[Mux.scala:30:73]
wire _io_rw_rdata_T_30 = 1'h0; // @[Mux.scala:30:73]
wire _io_rw_rdata_T_31 = 1'h0; // @[Mux.scala:30:73]
wire _io_rw_rdata_T_32 = 1'h0; // @[Mux.scala:30:73]
wire _io_rw_rdata_T_33 = 1'h0; // @[Mux.scala:30:73]
wire _io_rw_rdata_T_34 = 1'h0; // @[Mux.scala:30:73]
wire _io_rw_rdata_T_35 = 1'h0; // @[Mux.scala:30:73]
wire _io_rw_rdata_T_36 = 1'h0; // @[Mux.scala:30:73]
wire _io_rw_rdata_T_37 = 1'h0; // @[Mux.scala:30:73]
wire _io_rw_rdata_T_38 = 1'h0; // @[Mux.scala:30:73]
wire _io_rw_rdata_T_39 = 1'h0; // @[Mux.scala:30:73]
wire _io_rw_rdata_T_40 = 1'h0; // @[Mux.scala:30:73]
wire _io_rw_rdata_T_41 = 1'h0; // @[Mux.scala:30:73]
wire _io_rw_rdata_T_42 = 1'h0; // @[Mux.scala:30:73]
wire _io_rw_rdata_T_43 = 1'h0; // @[Mux.scala:30:73]
wire _io_rw_rdata_T_44 = 1'h0; // @[Mux.scala:30:73]
wire _io_rw_rdata_T_45 = 1'h0; // @[Mux.scala:30:73]
wire _io_rw_rdata_T_46 = 1'h0; // @[Mux.scala:30:73]
wire _io_rw_rdata_T_47 = 1'h0; // @[Mux.scala:30:73]
wire _io_rw_rdata_T_48 = 1'h0; // @[Mux.scala:30:73]
wire _io_rw_rdata_T_49 = 1'h0; // @[Mux.scala:30:73]
wire _io_rw_rdata_T_50 = 1'h0; // @[Mux.scala:30:73]
wire _io_rw_rdata_T_51 = 1'h0; // @[Mux.scala:30:73]
wire _io_rw_rdata_T_52 = 1'h0; // @[Mux.scala:30:73]
wire _io_rw_rdata_T_53 = 1'h0; // @[Mux.scala:30:73]
wire _io_rw_rdata_T_54 = 1'h0; // @[Mux.scala:30:73]
wire _io_rw_rdata_T_55 = 1'h0; // @[Mux.scala:30:73]
wire _io_rw_rdata_T_56 = 1'h0; // @[Mux.scala:30:73]
wire _io_rw_rdata_T_57 = 1'h0; // @[Mux.scala:30:73]
wire _io_rw_rdata_T_58 = 1'h0; // @[Mux.scala:30:73]
wire _io_rw_rdata_T_59 = 1'h0; // @[Mux.scala:30:73]
wire _io_rw_rdata_T_60 = 1'h0; // @[Mux.scala:30:73]
wire _io_rw_rdata_T_61 = 1'h0; // @[Mux.scala:30:73]
wire _io_rw_rdata_T_62 = 1'h0; // @[Mux.scala:30:73]
wire _io_rw_rdata_T_63 = 1'h0; // @[Mux.scala:30:73]
wire _io_rw_rdata_T_64 = 1'h0; // @[Mux.scala:30:73]
wire _io_rw_rdata_T_65 = 1'h0; // @[Mux.scala:30:73]
wire _io_rw_rdata_T_66 = 1'h0; // @[Mux.scala:30:73]
wire _io_rw_rdata_T_67 = 1'h0; // @[Mux.scala:30:73]
wire _io_rw_rdata_T_68 = 1'h0; // @[Mux.scala:30:73]
wire _io_rw_rdata_T_69 = 1'h0; // @[Mux.scala:30:73]
wire _io_rw_rdata_T_70 = 1'h0; // @[Mux.scala:30:73]
wire _io_rw_rdata_T_71 = 1'h0; // @[Mux.scala:30:73]
wire _io_rw_rdata_T_72 = 1'h0; // @[Mux.scala:30:73]
wire _io_rw_rdata_T_73 = 1'h0; // @[Mux.scala:30:73]
wire _io_rw_rdata_T_74 = 1'h0; // @[Mux.scala:30:73]
wire _io_rw_rdata_T_75 = 1'h0; // @[Mux.scala:30:73]
wire _io_rw_rdata_T_76 = 1'h0; // @[Mux.scala:30:73]
wire _io_rw_rdata_T_77 = 1'h0; // @[Mux.scala:30:73]
wire _io_rw_rdata_T_78 = 1'h0; // @[Mux.scala:30:73]
wire _io_rw_rdata_T_79 = 1'h0; // @[Mux.scala:30:73]
wire _io_rw_rdata_T_80 = 1'h0; // @[Mux.scala:30:73]
wire _io_rw_rdata_T_81 = 1'h0; // @[Mux.scala:30:73]
wire _io_rw_rdata_T_82 = 1'h0; // @[Mux.scala:30:73]
wire _io_rw_rdata_T_83 = 1'h0; // @[Mux.scala:30:73]
wire _io_rw_rdata_T_84 = 1'h0; // @[Mux.scala:30:73]
wire _io_rw_rdata_T_85 = 1'h0; // @[Mux.scala:30:73]
wire _io_rw_rdata_T_86 = 1'h0; // @[Mux.scala:30:73]
wire _io_rw_rdata_T_87 = 1'h0; // @[Mux.scala:30:73]
wire _io_rw_rdata_T_88 = 1'h0; // @[Mux.scala:30:73]
wire _io_rw_rdata_T_89 = 1'h0; // @[Mux.scala:30:73]
wire _io_rw_rdata_T_90 = 1'h0; // @[Mux.scala:30:73]
wire _io_rw_rdata_T_91 = 1'h0; // @[Mux.scala:30:73]
wire _io_rw_rdata_T_92 = 1'h0; // @[Mux.scala:30:73]
wire _io_rw_rdata_T_93 = 1'h0; // @[Mux.scala:30:73]
wire _io_rw_rdata_T_94 = 1'h0; // @[Mux.scala:30:73]
wire _io_rw_rdata_T_95 = 1'h0; // @[Mux.scala:30:73]
wire _io_rw_rdata_T_96 = 1'h0; // @[Mux.scala:30:73]
wire _io_rw_rdata_T_97 = 1'h0; // @[Mux.scala:30:73]
wire _io_rw_rdata_T_98 = 1'h0; // @[Mux.scala:30:73]
wire _io_rw_rdata_T_99 = 1'h0; // @[Mux.scala:30:73]
wire _io_rw_rdata_T_100 = 1'h0; // @[Mux.scala:30:73]
wire _io_rw_rdata_T_101 = 1'h0; // @[Mux.scala:30:73]
wire _io_rw_rdata_T_102 = 1'h0; // @[Mux.scala:30:73]
wire _io_rw_rdata_T_103 = 1'h0; // @[Mux.scala:30:73]
wire _io_rw_rdata_T_104 = 1'h0; // @[Mux.scala:30:73]
wire _io_rw_rdata_T_105 = 1'h0; // @[Mux.scala:30:73]
wire _io_rw_rdata_T_106 = 1'h0; // @[Mux.scala:30:73]
wire _io_rw_rdata_T_107 = 1'h0; // @[Mux.scala:30:73]
wire _io_rw_rdata_T_108 = 1'h0; // @[Mux.scala:30:73]
wire _io_rw_rdata_T_109 = 1'h0; // @[Mux.scala:30:73]
wire _io_rw_rdata_T_149 = 1'h0; // @[Mux.scala:30:73]
wire set_vs_dirty = 1'h0; // @[CSR.scala:1191:33]
wire new_mip_hi_hi_hi_hi = 1'h0; // @[CSR.scala:1271:59]
wire _reg_bp_0_control_chain_T_1 = 1'h0; // @[CSR.scala:1481:49]
wire _reg_bp_0_control_chain_T_2 = 1'h0; // @[CSR.scala:1481:46]
wire _reg_bp_0_control_chain_T_3 = 1'h0; // @[CSR.scala:1481:88]
wire _reg_bp_0_control_chain_T_5 = 1'h0; // @[CSR.scala:1481:75]
wire _reg_bp_1_control_chain_T_1 = 1'h0; // @[CSR.scala:1481:49]
wire _reg_bp_1_control_chain_T_2 = 1'h0; // @[CSR.scala:1481:46]
wire _reg_bp_1_control_chain_T_3 = 1'h0; // @[CSR.scala:1481:88]
wire _reg_bp_1_control_chain_T_5 = 1'h0; // @[CSR.scala:1481:75]
wire _reg_bp_1_WIRE_control_dmode = 1'h0; // @[CSR.scala:1613:23]
wire _reg_bp_1_WIRE_control_action = 1'h0; // @[CSR.scala:1613:23]
wire _reg_bp_1_WIRE_control_chain = 1'h0; // @[CSR.scala:1613:23]
wire _reg_bp_1_WIRE_control_m = 1'h0; // @[CSR.scala:1613:23]
wire _reg_bp_1_WIRE_control_h = 1'h0; // @[CSR.scala:1613:23]
wire _reg_bp_1_WIRE_control_s = 1'h0; // @[CSR.scala:1613:23]
wire _reg_bp_1_WIRE_control_u = 1'h0; // @[CSR.scala:1613:23]
wire _reg_bp_1_WIRE_control_x = 1'h0; // @[CSR.scala:1613:23]
wire _reg_bp_1_WIRE_control_w = 1'h0; // @[CSR.scala:1613:23]
wire _reg_bp_1_WIRE_control_r = 1'h0; // @[CSR.scala:1613:23]
wire _reg_bp_1_WIRE_textra_mselect = 1'h0; // @[CSR.scala:1613:23]
wire _reg_bp_1_WIRE_textra_pad1 = 1'h0; // @[CSR.scala:1613:23]
wire _reg_bp_1_WIRE_textra_sselect = 1'h0; // @[CSR.scala:1613:23]
wire [7:0] io_status_zero1 = 8'h0; // @[CSR.scala:377:7]
wire [7:0] io_gstatus_zero1_0 = 8'h0; // @[CSR.scala:377:7]
wire [7:0] _reset_mstatus_WIRE_zero1 = 8'h0; // @[CSR.scala:391:47]
wire [7:0] reset_mstatus_zero1 = 8'h0; // @[CSR.scala:391:34]
wire [7:0] lo_2 = 8'h0; // @[CSR.scala:479:12]
wire [7:0] hi_2 = 8'h0; // @[CSR.scala:479:12]
wire [7:0] lo_3 = 8'h0; // @[CSR.scala:479:27]
wire [7:0] hi_3 = 8'h0; // @[CSR.scala:479:27]
wire [7:0] sie_mask_lo = 8'h0; // @[CSR.scala:750:59]
wire [7:0] _read_sstatus_WIRE_zero1 = 8'h0; // @[CSR.scala:755:48]
wire [7:0] read_sstatus_zero1 = 8'h0; // @[CSR.scala:755:35]
wire [1:0] io_status_xs = 2'h0; // @[CSR.scala:377:7]
wire [1:0] io_status_vs = 2'h0; // @[CSR.scala:377:7]
wire [1:0] io_hstatus_zero3 = 2'h0; // @[CSR.scala:377:7]
wire [1:0] io_hstatus_zero2 = 2'h0; // @[CSR.scala:377:7]
wire [1:0] io_gstatus_dprv_0 = 2'h0; // @[CSR.scala:377:7]
wire [1:0] io_gstatus_prv_0 = 2'h0; // @[CSR.scala:377:7]
wire [1:0] io_gstatus_sxl_0 = 2'h0; // @[CSR.scala:377:7]
wire [1:0] io_gstatus_xs = 2'h0; // @[CSR.scala:377:7]
wire [1:0] io_gstatus_fs_0 = 2'h0; // @[CSR.scala:377:7]
wire [1:0] io_gstatus_mpp_0 = 2'h0; // @[CSR.scala:377:7]
wire [1:0] io_gstatus_vs_0 = 2'h0; // @[CSR.scala:377:7]
wire [1:0] io_bp_0_control_zero = 2'h0; // @[CSR.scala:377:7]
wire [1:0] io_pmp_0_cfg_res = 2'h0; // @[CSR.scala:377:7]
wire [1:0] io_pmp_1_cfg_res = 2'h0; // @[CSR.scala:377:7]
wire [1:0] io_pmp_2_cfg_res = 2'h0; // @[CSR.scala:377:7]
wire [1:0] io_pmp_3_cfg_res = 2'h0; // @[CSR.scala:377:7]
wire [1:0] io_pmp_4_cfg_res = 2'h0; // @[CSR.scala:377:7]
wire [1:0] io_pmp_5_cfg_res = 2'h0; // @[CSR.scala:377:7]
wire [1:0] io_pmp_6_cfg_res = 2'h0; // @[CSR.scala:377:7]
wire [1:0] io_pmp_7_cfg_res = 2'h0; // @[CSR.scala:377:7]
wire [1:0] _reset_mstatus_WIRE_dprv = 2'h0; // @[CSR.scala:391:47]
wire [1:0] _reset_mstatus_WIRE_prv = 2'h0; // @[CSR.scala:391:47]
wire [1:0] _reset_mstatus_WIRE_sxl = 2'h0; // @[CSR.scala:391:47]
wire [1:0] _reset_mstatus_WIRE_uxl = 2'h0; // @[CSR.scala:391:47]
wire [1:0] _reset_mstatus_WIRE_xs = 2'h0; // @[CSR.scala:391:47]
wire [1:0] _reset_mstatus_WIRE_fs = 2'h0; // @[CSR.scala:391:47]
wire [1:0] _reset_mstatus_WIRE_mpp = 2'h0; // @[CSR.scala:391:47]
wire [1:0] _reset_mstatus_WIRE_vs = 2'h0; // @[CSR.scala:391:47]
wire [1:0] reset_mstatus_dprv = 2'h0; // @[CSR.scala:391:34]
wire [1:0] reset_mstatus_sxl = 2'h0; // @[CSR.scala:391:34]
wire [1:0] reset_mstatus_uxl = 2'h0; // @[CSR.scala:391:34]
wire [1:0] reset_mstatus_xs = 2'h0; // @[CSR.scala:391:34]
wire [1:0] reset_mstatus_fs = 2'h0; // @[CSR.scala:391:34]
wire [1:0] reset_mstatus_vs = 2'h0; // @[CSR.scala:391:34]
wire [1:0] _reset_dcsr_WIRE_xdebugver = 2'h0; // @[CSR.scala:400:44]
wire [1:0] _reset_dcsr_WIRE_zero4 = 2'h0; // @[CSR.scala:400:44]
wire [1:0] _reset_dcsr_WIRE_zero1 = 2'h0; // @[CSR.scala:400:44]
wire [1:0] _reset_dcsr_WIRE_prv = 2'h0; // @[CSR.scala:400:44]
wire [1:0] reset_dcsr_zero4 = 2'h0; // @[CSR.scala:400:31]
wire [1:0] reset_dcsr_zero1 = 2'h0; // @[CSR.scala:400:31]
wire [1:0] hi_hi_lo = 2'h0; // @[CSR.scala:431:10]
wire [1:0] hi_hi_hi = 2'h0; // @[CSR.scala:431:10]
wire [1:0] lo_lo_hi_1 = 2'h0; // @[CSR.scala:431:50]
wire [1:0] lo_hi_hi_1 = 2'h0; // @[CSR.scala:431:50]
wire [1:0] hi_lo_hi_1 = 2'h0; // @[CSR.scala:431:50]
wire [1:0] hi_hi_lo_1 = 2'h0; // @[CSR.scala:431:50]
wire [1:0] hi_hi_hi_1 = 2'h0; // @[CSR.scala:431:50]
wire [1:0] lo_lo_lo_2 = 2'h0; // @[CSR.scala:479:12]
wire [1:0] lo_lo_hi_2 = 2'h0; // @[CSR.scala:479:12]
wire [1:0] lo_hi_lo_2 = 2'h0; // @[CSR.scala:479:12]
wire [1:0] lo_hi_hi_2 = 2'h0; // @[CSR.scala:479:12]
wire [1:0] hi_lo_lo_2 = 2'h0; // @[CSR.scala:479:12]
wire [1:0] hi_lo_hi_2 = 2'h0; // @[CSR.scala:479:12]
wire [1:0] hi_hi_lo_2 = 2'h0; // @[CSR.scala:479:12]
wire [1:0] hi_hi_hi_2 = 2'h0; // @[CSR.scala:479:12]
wire [1:0] lo_lo_lo_3 = 2'h0; // @[CSR.scala:479:27]
wire [1:0] lo_lo_hi_3 = 2'h0; // @[CSR.scala:479:27]
wire [1:0] lo_hi_lo_3 = 2'h0; // @[CSR.scala:479:27]
wire [1:0] lo_hi_hi_3 = 2'h0; // @[CSR.scala:479:27]
wire [1:0] hi_lo_lo_3 = 2'h0; // @[CSR.scala:479:27]
wire [1:0] hi_lo_hi_3 = 2'h0; // @[CSR.scala:479:27]
wire [1:0] hi_hi_lo_3 = 2'h0; // @[CSR.scala:479:27]
wire [1:0] hi_hi_hi_3 = 2'h0; // @[CSR.scala:479:27]
wire [1:0] _reset_mnstatus_WIRE_mpp = 2'h0; // @[CSR.scala:516:48]
wire [1:0] _reg_menvcfg_WIRE_cbie = 2'h0; // @[CSR.scala:525:41]
wire [1:0] _reg_senvcfg_WIRE_cbie = 2'h0; // @[CSR.scala:526:41]
wire [1:0] _reg_henvcfg_WIRE_cbie = 2'h0; // @[CSR.scala:527:41]
wire [1:0] _reg_hstatus_WIRE_vsxl = 2'h0; // @[CSR.scala:552:41]
wire [1:0] _reg_hstatus_WIRE_zero3 = 2'h0; // @[CSR.scala:552:41]
wire [1:0] _reg_hstatus_WIRE_zero2 = 2'h0; // @[CSR.scala:552:41]
wire [1:0] read_hvip_lo_lo_hi = 2'h0; // @[CSR.scala:555:27]
wire [1:0] read_hvip_lo_hi_hi = 2'h0; // @[CSR.scala:555:27]
wire [1:0] read_hvip_hi_lo_hi = 2'h0; // @[CSR.scala:555:27]
wire [1:0] read_hvip_hi_hi_lo = 2'h0; // @[CSR.scala:555:27]
wire [1:0] pmp_cfg_res = 2'h0; // @[PMP.scala:24:19]
wire [1:0] pmp_1_cfg_res = 2'h0; // @[PMP.scala:24:19]
wire [1:0] pmp_2_cfg_res = 2'h0; // @[PMP.scala:24:19]
wire [1:0] pmp_3_cfg_res = 2'h0; // @[PMP.scala:24:19]
wire [1:0] pmp_4_cfg_res = 2'h0; // @[PMP.scala:24:19]
wire [1:0] pmp_5_cfg_res = 2'h0; // @[PMP.scala:24:19]
wire [1:0] pmp_6_cfg_res = 2'h0; // @[PMP.scala:24:19]
wire [1:0] pmp_7_cfg_res = 2'h0; // @[PMP.scala:24:19]
wire [1:0] debug_csrs_lo_hi_hi = 2'h0; // @[CSR.scala:670:27]
wire [1:0] _read_mnstatus_WIRE_mpp = 2'h0; // @[CSR.scala:675:44]
wire [1:0] read_vcsr = 2'h0; // @[CSR.scala:695:22]
wire [1:0] hi_hi_4 = 2'h0; // @[CSR.scala:742:49]
wire [1:0] sie_mask_lo_lo_lo = 2'h0; // @[CSR.scala:750:59]
wire [1:0] sie_mask_lo_lo_hi = 2'h0; // @[CSR.scala:750:59]
wire [1:0] sie_mask_lo_hi_lo = 2'h0; // @[CSR.scala:750:59]
wire [1:0] sie_mask_lo_hi_hi = 2'h0; // @[CSR.scala:750:59]
wire [1:0] sie_mask_hi_lo_lo = 2'h0; // @[CSR.scala:750:59]
wire [1:0] sie_mask_hi_lo_hi = 2'h0; // @[CSR.scala:750:59]
wire [1:0] sie_mask_hi_hi_hi = 2'h0; // @[CSR.scala:750:59]
wire [1:0] _read_sstatus_WIRE_dprv = 2'h0; // @[CSR.scala:755:48]
wire [1:0] _read_sstatus_WIRE_prv = 2'h0; // @[CSR.scala:755:48]
wire [1:0] _read_sstatus_WIRE_sxl = 2'h0; // @[CSR.scala:755:48]
wire [1:0] _read_sstatus_WIRE_uxl = 2'h0; // @[CSR.scala:755:48]
wire [1:0] _read_sstatus_WIRE_xs = 2'h0; // @[CSR.scala:755:48]
wire [1:0] _read_sstatus_WIRE_fs = 2'h0; // @[CSR.scala:755:48]
wire [1:0] _read_sstatus_WIRE_mpp = 2'h0; // @[CSR.scala:755:48]
wire [1:0] _read_sstatus_WIRE_vs = 2'h0; // @[CSR.scala:755:48]
wire [1:0] read_sstatus_dprv = 2'h0; // @[CSR.scala:755:35]
wire [1:0] read_sstatus_prv = 2'h0; // @[CSR.scala:755:35]
wire [1:0] read_sstatus_sxl = 2'h0; // @[CSR.scala:755:35]
wire [1:0] read_sstatus_xs = 2'h0; // @[CSR.scala:755:35]
wire [1:0] read_sstatus_mpp = 2'h0; // @[CSR.scala:755:35]
wire [1:0] read_sstatus_vs = 2'h0; // @[CSR.scala:755:35]
wire [1:0] lo_lo_lo_hi = 2'h0; // @[CSR.scala:768:51]
wire [1:0] lo_hi_hi_hi_hi = 2'h0; // @[CSR.scala:768:51]
wire [1:0] hi_lo_hi_hi_hi = 2'h0; // @[CSR.scala:768:51]
wire [1:0] hi_hi_hi_hi_hi = 2'h0; // @[CSR.scala:768:51]
wire [1:0] hi_hi_6 = 2'h0; // @[CSR.scala:780:49]
wire [1:0] read_pmp_15_cfg_res = 2'h0; // @[CSR.scala:787:59]
wire [1:0] read_pmp_15_cfg_a = 2'h0; // @[CSR.scala:787:59]
wire [1:0] lo_hi_16 = 2'h0; // @[package.scala:45:36]
wire [1:0] lo_hi_17 = 2'h0; // @[package.scala:45:36]
wire [1:0] lo_hi_18 = 2'h0; // @[package.scala:45:36]
wire [1:0] lo_hi_19 = 2'h0; // @[package.scala:45:36]
wire [1:0] lo_hi_20 = 2'h0; // @[package.scala:45:36]
wire [1:0] lo_hi_21 = 2'h0; // @[package.scala:45:36]
wire [1:0] lo_hi_22 = 2'h0; // @[package.scala:45:36]
wire [1:0] lo_hi_23 = 2'h0; // @[package.scala:45:36]
wire [1:0] decoded_orMatrixOutputs_lo_lo = 2'h0; // @[pla.scala:102:36]
wire [1:0] decoded_orMatrixOutputs_lo_lo_1 = 2'h0; // @[pla.scala:102:36]
wire [1:0] nmiTVec = 2'h0; // @[CSR.scala:993:62]
wire [1:0] new_mip_lo_lo_hi = 2'h0; // @[CSR.scala:1271:59]
wire [1:0] new_mip_lo_hi_hi = 2'h0; // @[CSR.scala:1271:59]
wire [1:0] new_mip_hi_lo_hi = 2'h0; // @[CSR.scala:1271:59]
wire [1:0] new_mip_hi_hi_lo = 2'h0; // @[CSR.scala:1271:59]
wire [1:0] newBPC_lo_lo_hi_1 = 2'h0; // @[CSR.scala:1477:67]
wire [1:0] newBPC_lo_hi_lo_1 = 2'h0; // @[CSR.scala:1477:67]
wire [1:0] newBPC_lo_hi_hi_1 = 2'h0; // @[CSR.scala:1477:67]
wire [1:0] newBPC_hi_lo_hi_1 = 2'h0; // @[CSR.scala:1477:67]
wire [1:0] _reg_bp_1_WIRE_control_zero = 2'h0; // @[CSR.scala:1613:23]
wire [1:0] _reg_bp_1_WIRE_control_tmatch = 2'h0; // @[CSR.scala:1613:23]
wire [29:0] io_hstatus_zero6 = 30'h0; // @[CSR.scala:377:7]
wire [29:0] _reg_hstatus_WIRE_zero6 = 30'h0; // @[CSR.scala:552:41]
wire [29:0] read_pmp_15_addr = 30'h0; // @[CSR.scala:787:59]
wire [29:0] _io_rw_rdata_T_137 = 30'h0; // @[Mux.scala:30:73]
wire [29:0] _io_rw_rdata_T_138 = 30'h0; // @[Mux.scala:30:73]
wire [29:0] _io_rw_rdata_T_139 = 30'h0; // @[Mux.scala:30:73]
wire [29:0] _io_rw_rdata_T_140 = 30'h0; // @[Mux.scala:30:73]
wire [29:0] _io_rw_rdata_T_141 = 30'h0; // @[Mux.scala:30:73]
wire [29:0] _io_rw_rdata_T_142 = 30'h0; // @[Mux.scala:30:73]
wire [29:0] _io_rw_rdata_T_143 = 30'h0; // @[Mux.scala:30:73]
wire [29:0] _io_rw_rdata_T_144 = 30'h0; // @[Mux.scala:30:73]
wire [8:0] io_hstatus_zero5 = 9'h0; // @[CSR.scala:377:7]
wire [8:0] _reg_hstatus_WIRE_zero5 = 9'h0; // @[CSR.scala:552:41]
wire [8:0] hi_lo_lo_lo = 9'h0; // @[CSR.scala:768:51]
wire [5:0] io_hstatus_vgein = 6'h0; // @[CSR.scala:377:7]
wire [5:0] _reg_hstatus_WIRE_vgein = 6'h0; // @[CSR.scala:552:41]
wire [5:0] hi_lo_hi_4 = 6'h0; // @[CSR.scala:768:51]
wire [5:0] newBPC_hi_lo_1 = 6'h0; // @[CSR.scala:1477:67]
wire [5:0] _reg_bp_1_WIRE_control_maskmax = 6'h0; // @[CSR.scala:1613:23]
wire [4:0] io_hstatus_zero1 = 5'h0; // @[CSR.scala:377:7]
wire [4:0] _reg_hstatus_WIRE_zero1 = 5'h0; // @[CSR.scala:552:41]
wire [4:0] hi_19 = 5'h0; // @[package.scala:45:36]
wire [4:0] hi_20 = 5'h0; // @[package.scala:45:36]
wire [4:0] hi_21 = 5'h0; // @[package.scala:45:36]
wire [4:0] hi_22 = 5'h0; // @[package.scala:45:36]
wire [4:0] hi_23 = 5'h0; // @[package.scala:45:36]
wire [4:0] hi_24 = 5'h0; // @[package.scala:45:36]
wire [4:0] hi_25 = 5'h0; // @[package.scala:45:36]
wire [4:0] hi_26 = 5'h0; // @[package.scala:45:36]
wire [4:0] newBPC_hi_hi_hi_1 = 5'h0; // @[CSR.scala:1477:67]
wire [15:0] io_ptbr_asid = 16'h0; // @[CSR.scala:377:7]
wire [15:0] io_hgatp_asid = 16'h0; // @[CSR.scala:377:7]
wire [15:0] io_vsatp_asid = 16'h0; // @[CSR.scala:377:7]
wire [15:0] hs_delegable_interrupts = 16'h0; // @[CSR.scala:479:12]
wire [15:0] mideleg_always_hs = 16'h0; // @[CSR.scala:479:27]
wire [15:0] read_hvip = 16'h0; // @[CSR.scala:555:34]
wire [15:0] read_hip = 16'h0; // @[CSR.scala:611:27]
wire [15:0] lo_lo_8 = 16'h0; // @[package.scala:45:27]
wire [15:0] lo_hi_24 = 16'h0; // @[package.scala:45:27]
wire [15:0] hi_lo_8 = 16'h0; // @[package.scala:45:27]
wire [15:0] hi_hi_24 = 16'h0; // @[package.scala:45:27]
wire [15:0] _en_T = 16'h0; // @[CSR.scala:1096:49]
wire [15:0] _delegable_T = 16'h0; // @[CSR.scala:1097:43]
wire [15:0] _en_T_12 = 16'h0; // @[CSR.scala:1096:49]
wire [15:0] _delegable_T_2 = 16'h0; // @[CSR.scala:1097:43]
wire [15:0] _delegable_T_3 = 16'h0; // @[CSR.scala:1097:43]
wire [15:0] _en_T_24 = 16'h0; // @[CSR.scala:1096:49]
wire [15:0] _delegable_T_4 = 16'h0; // @[CSR.scala:1097:43]
wire [15:0] _en_T_36 = 16'h0; // @[CSR.scala:1096:49]
wire [15:0] _delegable_T_6 = 16'h0; // @[CSR.scala:1097:43]
wire [15:0] _delegable_T_7 = 16'h0; // @[CSR.scala:1097:43]
wire [15:0] _en_T_48 = 16'h0; // @[CSR.scala:1096:49]
wire [15:0] _delegable_T_8 = 16'h0; // @[CSR.scala:1097:43]
wire [15:0] _en_T_60 = 16'h0; // @[CSR.scala:1096:49]
wire [15:0] _delegable_T_10 = 16'h0; // @[CSR.scala:1097:43]
wire [15:0] _delegable_T_11 = 16'h0; // @[CSR.scala:1097:43]
wire [15:0] _en_T_72 = 16'h0; // @[CSR.scala:1096:49]
wire [15:0] _delegable_T_12 = 16'h0; // @[CSR.scala:1097:43]
wire [15:0] _en_T_78 = 16'h0; // @[CSR.scala:1096:49]
wire [15:0] _delegable_T_13 = 16'h0; // @[CSR.scala:1097:43]
wire [15:0] _en_T_84 = 16'h0; // @[CSR.scala:1096:49]
wire [15:0] _delegable_T_14 = 16'h0; // @[CSR.scala:1097:43]
wire [15:0] _en_T_90 = 16'h0; // @[CSR.scala:1096:49]
wire [15:0] _delegable_T_15 = 16'h0; // @[CSR.scala:1097:43]
wire [15:0] _delegable_T_17 = 16'h0; // @[CSR.scala:1109:45]
wire [15:0] _delegable_T_21 = 16'h0; // @[CSR.scala:1109:45]
wire [15:0] _delegable_T_23 = 16'h0; // @[CSR.scala:1109:45]
wire [15:0] _delegable_T_25 = 16'h0; // @[CSR.scala:1109:45]
wire [15:0] _delegable_T_26 = 16'h0; // @[CSR.scala:1109:45]
wire [3:0] io_hgatp_mode = 4'h0; // @[CSR.scala:377:7]
wire [3:0] io_vsatp_mode = 4'h0; // @[CSR.scala:377:7]
wire [3:0] hi_hi = 4'h0; // @[CSR.scala:431:10]
wire [3:0] hi_hi_1 = 4'h0; // @[CSR.scala:431:50]
wire [3:0] lo_lo_2 = 4'h0; // @[CSR.scala:479:12]
wire [3:0] lo_hi_2 = 4'h0; // @[CSR.scala:479:12]
wire [3:0] hi_lo_2 = 4'h0; // @[CSR.scala:479:12]
wire [3:0] hi_hi_2 = 4'h0; // @[CSR.scala:479:12]
wire [3:0] lo_lo_3 = 4'h0; // @[CSR.scala:479:27]
wire [3:0] lo_hi_3 = 4'h0; // @[CSR.scala:479:27]
wire [3:0] hi_lo_3 = 4'h0; // @[CSR.scala:479:27]
wire [3:0] hi_hi_3 = 4'h0; // @[CSR.scala:479:27]
wire [3:0] sie_mask_lo_lo = 4'h0; // @[CSR.scala:750:59]
wire [3:0] sie_mask_lo_hi = 4'h0; // @[CSR.scala:750:59]
wire [3:0] sie_mask_hi_lo = 4'h0; // @[CSR.scala:750:59]
wire [3:0] lo_hi_lo_lo = 4'h0; // @[CSR.scala:768:51]
wire [3:0] hi_hi_lo_hi = 4'h0; // @[CSR.scala:768:51]
wire [3:0] newBPC_lo_hi_1 = 4'h0; // @[CSR.scala:1477:67]
wire [3:0] newBPC_hi_lo_lo_1 = 4'h0; // @[CSR.scala:1477:67]
wire [3:0] _reg_bp_1_WIRE_control_ttype = 4'h0; // @[CSR.scala:1613:23]
wire [43:0] io_hgatp_ppn = 44'h0; // @[CSR.scala:377:7]
wire [43:0] io_vsatp_ppn = 44'h0; // @[CSR.scala:377:7]
wire [3:0] io_bp_0_control_ttype = 4'h2; // @[CSR.scala:377:7]
wire [3:0] lo_lo_1 = 4'h2; // @[CSR.scala:431:50]
wire [3:0] lo_hi_1 = 4'h2; // @[CSR.scala:431:50]
wire [3:0] hi_lo_1 = 4'h2; // @[CSR.scala:431:50]
wire [5:0] io_bp_0_control_maskmax = 6'h4; // @[CSR.scala:377:7]
wire [39:0] io_bp_0_control_reserved = 40'h0; // @[CSR.scala:377:7]
wire [39:0] _reg_bp_1_WIRE_control_reserved = 40'h0; // @[CSR.scala:1613:23]
wire [63:0] io_customCSRs_0_sdata = 64'h0; // @[CSR.scala:377:7]
wire [63:0] io_customCSRs_1_sdata = 64'h0; // @[CSR.scala:377:7]
wire [63:0] io_customCSRs_2_sdata = 64'h0; // @[CSR.scala:377:7]
wire [63:0] io_customCSRs_3_sdata = 64'h0; // @[CSR.scala:377:7]
wire [63:0] read_hideleg = 64'h0; // @[CSR.scala:541:14]
wire [63:0] read_hedeleg = 64'h0; // @[CSR.scala:545:14]
wire [63:0] read_hie = 64'h0; // @[CSR.scala:556:26]
wire [63:0] read_vstvec = 64'h0; // @[package.scala:132:15]
wire [63:0] _vs_interrupts_T_6 = 64'h0; // @[CSR.scala:622:153]
wire [63:0] vs_interrupts = 64'h0; // @[CSR.scala:622:26]
wire [63:0] _io_rw_rdata_T_128 = 64'h0; // @[Mux.scala:30:73]
wire [63:0] _newBPC_T_24 = 64'h0; // @[CSR.scala:1477:67]
wire [63:0] _newBPC_T_26 = 64'h0; // @[CSR.scala:1643:9]
wire [63:0] _reg_custom_1_T = 64'h0; // @[CSR.scala:1506:23]
wire [63:0] _reg_custom_2_T = 64'h0; // @[CSR.scala:1506:23]
wire [63:0] _reg_custom_3_T = 64'h0; // @[CSR.scala:1506:23]
wire [63:0] _reg_custom_0_T_4 = 64'h0; // @[CSR.scala:1531:24]
wire [63:0] _reg_custom_1_T_4 = 64'h0; // @[CSR.scala:1531:24]
wire [63:0] _reg_custom_2_T_4 = 64'h0; // @[CSR.scala:1531:24]
wire [63:0] _reg_custom_3_T_4 = 64'h0; // @[CSR.scala:1531:24]
wire [56:0] hi_6 = 57'h0; // @[CSR.scala:742:49]
wire [56:0] hi_9 = 57'h0; // @[CSR.scala:780:49]
wire [56:0] newBPC_hi_1 = 57'h0; // @[CSR.scala:1477:67]
wire [50:0] newBPC_hi_hi_1 = 51'h0; // @[CSR.scala:1477:67]
wire [45:0] newBPC_hi_hi_lo_1 = 46'h0; // @[CSR.scala:1477:67]
wire [6:0] newBPC_lo_1 = 7'h0; // @[CSR.scala:1477:67]
wire [2:0] _reset_dcsr_WIRE_cause = 3'h0; // @[CSR.scala:400:44]
wire [2:0] reset_dcsr_cause = 3'h0; // @[CSR.scala:400:31]
wire [2:0] _reset_mnstatus_WIRE_zero3 = 3'h0; // @[CSR.scala:516:48]
wire [2:0] _reset_mnstatus_WIRE_zero2 = 3'h0; // @[CSR.scala:516:48]
wire [2:0] _reset_mnstatus_WIRE_zero1 = 3'h0; // @[CSR.scala:516:48]
wire [2:0] reset_mnstatus_zero3 = 3'h0; // @[CSR.scala:516:35]
wire [2:0] reset_mnstatus_zero2 = 3'h0; // @[CSR.scala:516:35]
wire [2:0] reset_mnstatus_zero1 = 3'h0; // @[CSR.scala:516:35]
wire [2:0] _reg_menvcfg_WIRE_zero3 = 3'h0; // @[CSR.scala:525:41]
wire [2:0] _reg_senvcfg_WIRE_zero3 = 3'h0; // @[CSR.scala:526:41]
wire [2:0] _reg_henvcfg_WIRE_zero3 = 3'h0; // @[CSR.scala:527:41]
wire [2:0] _read_mnstatus_WIRE_zero3 = 3'h0; // @[CSR.scala:675:44]
wire [2:0] _read_mnstatus_WIRE_zero2 = 3'h0; // @[CSR.scala:675:44]
wire [2:0] _read_mnstatus_WIRE_zero1 = 3'h0; // @[CSR.scala:675:44]
wire [2:0] read_mnstatus_zero3 = 3'h0; // @[CSR.scala:675:31]
wire [2:0] read_mnstatus_zero2 = 3'h0; // @[CSR.scala:675:31]
wire [2:0] read_mnstatus_zero1 = 3'h0; // @[CSR.scala:675:31]
wire [2:0] lo_hi_4 = 3'h0; // @[CSR.scala:742:49]
wire [2:0] hi_lo_hi_lo = 3'h0; // @[CSR.scala:768:51]
wire [2:0] hi_lo_hi_hi = 3'h0; // @[CSR.scala:768:51]
wire [2:0] hi_hi_lo_hi_hi = 3'h0; // @[CSR.scala:768:51]
wire [2:0] hi_hi_hi_hi_4 = 3'h0; // @[CSR.scala:768:51]
wire [2:0] lo_hi_6 = 3'h0; // @[CSR.scala:780:49]
wire [2:0] lo_16 = 3'h0; // @[package.scala:45:36]
wire [2:0] hi_hi_16 = 3'h0; // @[package.scala:45:36]
wire [2:0] lo_17 = 3'h0; // @[package.scala:45:36]
wire [2:0] hi_hi_17 = 3'h0; // @[package.scala:45:36]
wire [2:0] lo_18 = 3'h0; // @[package.scala:45:36]
wire [2:0] hi_hi_18 = 3'h0; // @[package.scala:45:36]
wire [2:0] lo_19 = 3'h0; // @[package.scala:45:36]
wire [2:0] hi_hi_19 = 3'h0; // @[package.scala:45:36]
wire [2:0] lo_20 = 3'h0; // @[package.scala:45:36]
wire [2:0] hi_hi_20 = 3'h0; // @[package.scala:45:36]
wire [2:0] lo_21 = 3'h0; // @[package.scala:45:36]
wire [2:0] hi_hi_21 = 3'h0; // @[package.scala:45:36]
wire [2:0] lo_22 = 3'h0; // @[package.scala:45:36]
wire [2:0] hi_hi_22 = 3'h0; // @[package.scala:45:36]
wire [2:0] lo_23 = 3'h0; // @[package.scala:45:36]
wire [2:0] hi_hi_23 = 3'h0; // @[package.scala:45:36]
wire [2:0] newBPC_lo_lo_1 = 3'h0; // @[CSR.scala:1477:67]
wire [45:0] read_mapping_hi_hi_lo = 46'h40000000000; // @[CSR.scala:655:48]
wire [45:0] newBPC_hi_hi_lo = 46'h40000000000; // @[CSR.scala:1477:67]
wire [54:0] hi_lo_4 = 55'h0; // @[CSR.scala:742:49]
wire [54:0] hi_lo_6 = 55'h0; // @[CSR.scala:780:49]
wire [1:0] reset_mstatus_prv = 2'h3; // @[CSR.scala:391:34]
wire [1:0] reset_mstatus_mpp = 2'h3; // @[CSR.scala:391:34]
wire [1:0] reset_dcsr_prv = 2'h3; // @[CSR.scala:400:31]
wire [1:0] reset_mnstatus_mpp = 2'h3; // @[CSR.scala:516:35]
wire [1:0] read_mnstatus_mpp = 2'h3; // @[CSR.scala:675:31]
wire [3:0] _which_T_64 = 4'h4; // @[Mux.scala:50:70]
wire [3:0] _which_T_65 = 4'h4; // @[Mux.scala:50:70]
wire [3:0] _which_T_66 = 4'h4; // @[Mux.scala:50:70]
wire [3:0] _which_T_67 = 4'h4; // @[Mux.scala:50:70]
wire [3:0] _which_T_68 = 4'h4; // @[Mux.scala:50:70]
wire [3:0] _which_T_69 = 4'h4; // @[Mux.scala:50:70]
wire [3:0] _which_T_70 = 4'h4; // @[Mux.scala:50:70]
wire [3:0] _which_T_71 = 4'h4; // @[Mux.scala:50:70]
wire [3:0] _which_T_72 = 4'h4; // @[Mux.scala:50:70]
wire [3:0] _which_T_73 = 4'h4; // @[Mux.scala:50:70]
wire [3:0] _which_T_74 = 4'h4; // @[Mux.scala:50:70]
wire [3:0] _which_T_75 = 4'h4; // @[Mux.scala:50:70]
wire [3:0] _which_T_76 = 4'h4; // @[Mux.scala:50:70]
wire [3:0] _which_T_77 = 4'h4; // @[Mux.scala:50:70]
wire [3:0] _which_T_78 = 4'h4; // @[Mux.scala:50:70]
wire [3:0] debug_csrs_hi_hi_hi = 4'h4; // @[CSR.scala:670:27]
wire [2:0] read_mstatus_hi_lo_hi_lo = 3'h2; // @[CSR.scala:649:32]
wire [47:0] io_bp_0_textra_pad2_0 = 48'h0; // @[CSR.scala:377:7]
wire [47:0] _reg_bp_1_WIRE_textra_pad2 = 48'h0; // @[CSR.scala:1613:23]
wire [38:0] _read_stvec_T_2 = 39'h0; // @[package.scala:174:46]
wire [38:0] _reg_bp_1_WIRE_address = 39'h0; // @[CSR.scala:1613:23]
wire [1:0] io_status_sxl = 2'h2; // @[CSR.scala:377:7]
wire [1:0] io_status_uxl = 2'h2; // @[CSR.scala:377:7]
wire [1:0] io_hstatus_vsxl = 2'h2; // @[CSR.scala:377:7]
wire [1:0] io_gstatus_uxl = 2'h2; // @[CSR.scala:377:7]
wire [1:0] lo_lo_lo = 2'h2; // @[CSR.scala:431:10]
wire [1:0] lo_lo_hi = 2'h2; // @[CSR.scala:431:10]
wire [1:0] lo_hi_lo = 2'h2; // @[CSR.scala:431:10]
wire [1:0] lo_hi_hi = 2'h2; // @[CSR.scala:431:10]
wire [1:0] hi_lo_lo = 2'h2; // @[CSR.scala:431:10]
wire [1:0] hi_lo_hi = 2'h2; // @[CSR.scala:431:10]
wire [1:0] lo_lo_lo_1 = 2'h2; // @[CSR.scala:431:50]
wire [1:0] lo_hi_lo_1 = 2'h2; // @[CSR.scala:431:50]
wire [1:0] hi_lo_lo_1 = 2'h2; // @[CSR.scala:431:50]
wire [1:0] read_sstatus_uxl = 2'h2; // @[CSR.scala:755:35]
wire [63:0] _s_interrupts_T_7 = 64'hFFFFFFFFFFFFFFFF; // @[CSR.scala:621:168]
wire [63:0] _reg_custom_1_T_1 = 64'hFFFFFFFFFFFFFFFF; // @[CSR.scala:1506:40]
wire [63:0] _reg_custom_2_T_1 = 64'hFFFFFFFFFFFFFFFF; // @[CSR.scala:1506:40]
wire [63:0] _reg_custom_3_T_1 = 64'hFFFFFFFFFFFFFFFF; // @[CSR.scala:1506:40]
wire [63:0] _reg_custom_1_T_5 = 64'hFFFFFFFFFFFFFFFF; // @[CSR.scala:1531:41]
wire [63:0] _reg_custom_2_T_5 = 64'hFFFFFFFFFFFFFFFF; // @[CSR.scala:1531:41]
wire [63:0] _reg_custom_3_T_5 = 64'hFFFFFFFFFFFFFFFF; // @[CSR.scala:1531:41]
wire [63:0] _reg_custom_0_T_1 = 64'hFFFFFFFFFFFFFDF7; // @[CSR.scala:1506:40]
wire [63:0] _reg_custom_0_T_5 = 64'hFFFFFFFFFFFFFDF7; // @[CSR.scala:1531:41]
wire [63:0] _reg_mcountinhibit_T = 64'hFFFFFFFFFFFFFFFD; // @[CSR.scala:1306:78]
wire [63:0] _reg_misa_T_6 = 64'hFFFFFFFFFFFFEFD2; // @[CSR.scala:1263:75]
wire [15:0] _sie_mask_T = 16'h1000; // @[CSR.scala:750:59]
wire [15:0] _sie_mask_T_1 = 16'h1000; // @[CSR.scala:750:46]
wire [15:0] _delegable_T_27 = 16'h1000; // @[CSR.scala:1109:45]
wire [15:0] _en_T_18 = 16'h8; // @[CSR.scala:1096:49]
wire [15:0] _delegable_T_19 = 16'h8; // @[CSR.scala:1109:45]
wire [63:0] _en_T_94 = 64'h800000000000000F; // @[CSR.scala:1096:120]
wire [63:0] _en_T_88 = 64'h800000000000000E; // @[CSR.scala:1096:120]
wire [63:0] _en_T_82 = 64'h800000000000000D; // @[CSR.scala:1096:120]
wire [63:0] _en_T_76 = 64'h800000000000000C; // @[CSR.scala:1096:120]
wire [63:0] _en_T_70 = 64'h800000000000000B; // @[CSR.scala:1096:120]
wire [15:0] _en_T_66 = 16'h800; // @[CSR.scala:1096:49]
wire [63:0] _en_T_64 = 64'h800000000000000A; // @[CSR.scala:1096:120]
wire [15:0] _en_T_54 = 16'h200; // @[CSR.scala:1096:49]
wire [15:0] _delegable_T_9 = 16'h200; // @[CSR.scala:1097:43]
wire [63:0] _en_T_58 = 64'h8000000000000009; // @[CSR.scala:1096:120]
wire [63:0] _en_T_52 = 64'h8000000000000008; // @[CSR.scala:1096:120]
wire [63:0] _en_T_46 = 64'h8000000000000007; // @[CSR.scala:1096:120]
wire [15:0] _en_T_42 = 16'h80; // @[CSR.scala:1096:49]
wire [63:0] _en_T_40 = 64'h8000000000000006; // @[CSR.scala:1096:120]
wire [15:0] _en_T_30 = 16'h20; // @[CSR.scala:1096:49]
wire [15:0] _delegable_T_5 = 16'h20; // @[CSR.scala:1097:43]
wire [63:0] _en_T_34 = 64'h8000000000000005; // @[CSR.scala:1096:120]
wire [63:0] _en_T_28 = 64'h8000000000000004; // @[CSR.scala:1096:120]
wire [63:0] _en_T_22 = 64'h8000000000000003; // @[CSR.scala:1096:120]
wire [63:0] _en_T_16 = 64'h8000000000000002; // @[CSR.scala:1096:120]
wire [15:0] _en_T_6 = 16'h2; // @[CSR.scala:1096:49]
wire [15:0] _delegable_T_1 = 16'h2; // @[CSR.scala:1097:43]
wire [63:0] _en_T_10 = 64'h8000000000000001; // @[CSR.scala:1096:120]
wire [63:0] _interruptCause_T_2 = 64'h8000000000000000; // @[CSR.scala:625:39]
wire [63:0] _en_T_4 = 64'h8000000000000000; // @[CSR.scala:1096:120]
wire [64:0] _interruptCause_T_1 = 65'h8000000000000000; // @[CSR.scala:625:39]
wire [64:0] _en_T_3 = 65'h8000000000000000; // @[CSR.scala:1096:120]
wire [9:0] _io_decode_0_write_flush_addr_m_T = 10'h300; // @[CSR.scala:932:36]
wire [31:0] io_gstatus_isa_0 = 32'h0; // @[CSR.scala:377:7]
wire [31:0] _reset_mstatus_WIRE_isa = 32'h0; // @[CSR.scala:391:47]
wire [31:0] reset_mstatus_isa = 32'h0; // @[CSR.scala:391:34]
wire [31:0] read_hcounteren = 32'h0; // @[CSR.scala:550:14]
wire [31:0] _read_mtvec_T_2 = 32'h0; // @[package.scala:174:46]
wire [31:0] _read_sstatus_WIRE_isa = 32'h0; // @[CSR.scala:755:48]
wire [31:0] read_sstatus_isa = 32'h0; // @[CSR.scala:755:35]
wire [31:0] read_pmp_15_mask = 32'h0; // @[CSR.scala:787:59]
wire [31:0] lo_24 = 32'h0; // @[package.scala:45:27]
wire [31:0] hi_27 = 32'h0; // @[package.scala:45:27]
wire [36:0] hi_hi_hi_4 = 37'h0; // @[CSR.scala:768:51]
wire [33:0] hi_hi_hi_lo = 34'h0; // @[CSR.scala:768:51]
wire [17:0] hi_lo_5 = 18'h800; // @[CSR.scala:768:51]
wire [11:0] hi_lo_lo_4 = 12'h800; // @[CSR.scala:768:51]
wire [2:0] _which_T_63 = 3'h4; // @[Mux.scala:50:70]
wire [2:0] read_mstatus_hi_lo_lo_hi = 3'h4; // @[CSR.scala:649:32]
wire [2:0] hi_lo_lo_hi = 3'h4; // @[CSR.scala:768:51]
wire [15:0] _sie_mask_T_2 = 16'hEFFF; // @[CSR.scala:750:20]
wire [7:0] sie_mask_hi = 8'h10; // @[CSR.scala:750:59]
wire [3:0] sie_mask_hi_hi = 4'h1; // @[CSR.scala:750:59]
wire [1:0] reset_dcsr_xdebugver = 2'h1; // @[CSR.scala:400:31]
wire [1:0] sie_mask_hi_hi_lo = 2'h1; // @[CSR.scala:750:59]
wire [53:0] _reg_menvcfg_WIRE_zero54 = 54'h0; // @[CSR.scala:525:41]
wire [53:0] _reg_senvcfg_WIRE_zero54 = 54'h0; // @[CSR.scala:526:41]
wire [53:0] _reg_henvcfg_WIRE_zero54 = 54'h0; // @[CSR.scala:527:41]
wire [15:0] delegable_interrupts = 16'h222; // @[CSR.scala:431:50]
wire [7:0] hi_1 = 8'h2; // @[CSR.scala:431:50]
wire [7:0] lo_1 = 8'h22; // @[CSR.scala:431:50]
wire [15:0] supported_interrupts = 16'hAAA; // @[CSR.scala:431:17]
wire [7:0] hi = 8'hA; // @[CSR.scala:431:10]
wire [3:0] lo_lo = 4'hA; // @[CSR.scala:431:10]
wire [3:0] lo_hi = 4'hA; // @[CSR.scala:431:10]
wire [3:0] hi_lo = 4'hA; // @[CSR.scala:431:10]
wire [7:0] lo = 8'hAA; // @[CSR.scala:431:10]
wire [11:0] _reset_dcsr_WIRE_zero3 = 12'h0; // @[CSR.scala:400:44]
wire [11:0] reset_dcsr_zero3 = 12'h0; // @[CSR.scala:400:31]
wire [15:0] _delegable_T_28 = 16'h2000; // @[CSR.scala:1109:45]
wire [15:0] _delegable_T_24 = 16'h100; // @[CSR.scala:1109:45]
wire [15:0] _delegable_T_22 = 16'h40; // @[CSR.scala:1109:45]
wire [15:0] _delegable_T_20 = 16'h10; // @[CSR.scala:1109:45]
wire [15:0] _delegable_T_18 = 16'h4; // @[CSR.scala:1109:45]
wire [15:0] _delegable_T_16 = 16'h1; // @[CSR.scala:1109:45]
wire [64:0] _en_T_93 = 65'h800000000000000F; // @[CSR.scala:1096:120]
wire [64:0] _en_T_87 = 65'h800000000000000E; // @[CSR.scala:1096:120]
wire [64:0] _en_T_81 = 65'h800000000000000D; // @[CSR.scala:1096:120]
wire [64:0] _en_T_75 = 65'h800000000000000C; // @[CSR.scala:1096:120]
wire [64:0] _en_T_69 = 65'h800000000000000B; // @[CSR.scala:1096:120]
wire [64:0] _en_T_63 = 65'h800000000000000A; // @[CSR.scala:1096:120]
wire [64:0] _en_T_57 = 65'h8000000000000009; // @[CSR.scala:1096:120]
wire [64:0] _en_T_51 = 65'h8000000000000008; // @[CSR.scala:1096:120]
wire [64:0] _en_T_45 = 65'h8000000000000007; // @[CSR.scala:1096:120]
wire [64:0] _en_T_39 = 65'h8000000000000006; // @[CSR.scala:1096:120]
wire [64:0] _en_T_33 = 65'h8000000000000005; // @[CSR.scala:1096:120]
wire [64:0] _en_T_27 = 65'h8000000000000004; // @[CSR.scala:1096:120]
wire [64:0] _en_T_21 = 65'h8000000000000003; // @[CSR.scala:1096:120]
wire [64:0] _en_T_15 = 65'h8000000000000002; // @[CSR.scala:1096:120]
wire [64:0] _en_T_9 = 65'h8000000000000001; // @[CSR.scala:1096:120]
wire [62:0] _interruptCause_T = 63'h0; // @[CSR.scala:625:50]
wire [15:0] _delegable_T_29 = 16'h8000; // @[CSR.scala:1109:45]
wire [39:0] _io_evec_T_15 = 40'hFFFFFFFFFF; // @[CSR.scala:1665:28]
wire [48:0] read_mapping_hi_1 = 49'h0; // @[CSR.scala:657:47]
wire mip_mtip = io_interrupts_mtip_0; // @[CSR.scala:377:7, :600:24]
wire mip_msip = io_interrupts_msip_0; // @[CSR.scala:377:7, :600:24]
wire mip_meip = io_interrupts_meip_0; // @[CSR.scala:377:7, :600:24]
wire [63:0] _io_rw_rdata_WIRE; // @[Mux.scala:30:73]
wire [63:0] _newBPC_T_27 = io_rw_wdata_0; // @[CSR.scala:377:7, :1643:30]
wire [31:0] decoded_plaInput_1 = io_decode_0_inst_0; // @[pla.scala:77:22]
wire _io_decode_0_fp_illegal_T_6; // @[CSR.scala:915:91]
wire _io_decode_0_fp_csr_T; // @[Decode.scala:55:116]
wire _io_decode_0_read_illegal_T_20; // @[CSR.scala:928:68]
wire _io_decode_0_write_illegal_T_1; // @[CSR.scala:930:41]
wire _io_decode_0_write_flush_T_3; // @[CSR.scala:933:7]
wire _io_decode_0_system_illegal_T_25; // @[CSR.scala:940:44]
wire _io_decode_0_virtual_access_illegal_T_29; // @[CSR.scala:943:66]
wire _io_decode_0_virtual_system_illegal_T_22; // @[CSR.scala:949:52]
wire _io_csr_stall_T; // @[CSR.scala:1161:27]
wire _io_eret_T_1; // @[CSR.scala:1000:38]
wire _io_singleStep_T_1; // @[CSR.scala:1001:34]
wire [1:0] _io_status_dprv_T_2; // @[CSR.scala:1008:24]
wire _io_status_dv_T_3; // @[CSR.scala:1009:33]
wire _io_status_sd_T_4; // @[CSR.scala:1003:58]
wire read_sstatus_sd = io_status_sd_0; // @[CSR.scala:377:7, :755:35]
wire read_sstatus_mxr = io_status_mxr_0; // @[CSR.scala:377:7, :755:35]
wire read_sstatus_sum = io_status_sum_0; // @[CSR.scala:377:7, :755:35]
wire [1:0] read_sstatus_fs = io_status_fs_0; // @[CSR.scala:377:7, :755:35]
wire read_sstatus_spp = io_status_spp_0; // @[CSR.scala:377:7, :755:35]
wire read_sstatus_spie = io_status_spie_0; // @[CSR.scala:377:7, :755:35]
wire read_sstatus_sie = io_status_sie_0; // @[CSR.scala:377:7, :755:35]
wire _io_gstatus_sd_T_4; // @[CSR.scala:1016:61]
wire _io_trace_0_valid_T = io_retire_0; // @[CSR.scala:377:7, :1621:26]
wire [39:0] io_trace_0_iaddr_0 = io_pc_0; // @[CSR.scala:377:7]
wire [39:0] io_trace_0_tval_0 = io_tval_0; // @[CSR.scala:377:7]
wire [63:0] value_1; // @[Counters.scala:55:30]
wire _io_interrupt_T_5; // @[CSR.scala:626:73]
wire [63:0] interruptCause; // @[CSR.scala:625:63]
wire pmp_cfg_l; // @[PMP.scala:24:19]
wire [1:0] pmp_cfg_a; // @[PMP.scala:24:19]
wire pmp_cfg_x; // @[PMP.scala:24:19]
wire pmp_cfg_w; // @[PMP.scala:24:19]
wire pmp_cfg_r; // @[PMP.scala:24:19]
wire [29:0] pmp_addr; // @[PMP.scala:24:19]
wire [31:0] pmp_mask; // @[PMP.scala:24:19]
wire pmp_1_cfg_l; // @[PMP.scala:24:19]
wire [1:0] pmp_1_cfg_a; // @[PMP.scala:24:19]
wire pmp_1_cfg_x; // @[PMP.scala:24:19]
wire pmp_1_cfg_w; // @[PMP.scala:24:19]
wire pmp_1_cfg_r; // @[PMP.scala:24:19]
wire [29:0] pmp_1_addr; // @[PMP.scala:24:19]
wire [31:0] pmp_1_mask; // @[PMP.scala:24:19]
wire pmp_2_cfg_l; // @[PMP.scala:24:19]
wire [1:0] pmp_2_cfg_a; // @[PMP.scala:24:19]
wire pmp_2_cfg_x; // @[PMP.scala:24:19]
wire pmp_2_cfg_w; // @[PMP.scala:24:19]
wire pmp_2_cfg_r; // @[PMP.scala:24:19]
wire [29:0] pmp_2_addr; // @[PMP.scala:24:19]
wire [31:0] pmp_2_mask; // @[PMP.scala:24:19]
wire pmp_3_cfg_l; // @[PMP.scala:24:19]
wire [1:0] pmp_3_cfg_a; // @[PMP.scala:24:19]
wire pmp_3_cfg_x; // @[PMP.scala:24:19]
wire pmp_3_cfg_w; // @[PMP.scala:24:19]
wire pmp_3_cfg_r; // @[PMP.scala:24:19]
wire [29:0] pmp_3_addr; // @[PMP.scala:24:19]
wire [31:0] pmp_3_mask; // @[PMP.scala:24:19]
wire pmp_4_cfg_l; // @[PMP.scala:24:19]
wire [1:0] pmp_4_cfg_a; // @[PMP.scala:24:19]
wire pmp_4_cfg_x; // @[PMP.scala:24:19]
wire pmp_4_cfg_w; // @[PMP.scala:24:19]
wire pmp_4_cfg_r; // @[PMP.scala:24:19]
wire [29:0] pmp_4_addr; // @[PMP.scala:24:19]
wire [31:0] pmp_4_mask; // @[PMP.scala:24:19]
wire pmp_5_cfg_l; // @[PMP.scala:24:19]
wire [1:0] pmp_5_cfg_a; // @[PMP.scala:24:19]
wire pmp_5_cfg_x; // @[PMP.scala:24:19]
wire pmp_5_cfg_w; // @[PMP.scala:24:19]
wire pmp_5_cfg_r; // @[PMP.scala:24:19]
wire [29:0] pmp_5_addr; // @[PMP.scala:24:19]
wire [31:0] pmp_5_mask; // @[PMP.scala:24:19]
wire pmp_6_cfg_l; // @[PMP.scala:24:19]
wire [1:0] pmp_6_cfg_a; // @[PMP.scala:24:19]
wire pmp_6_cfg_x; // @[PMP.scala:24:19]
wire pmp_6_cfg_w; // @[PMP.scala:24:19]
wire pmp_6_cfg_r; // @[PMP.scala:24:19]
wire [29:0] pmp_6_addr; // @[PMP.scala:24:19]
wire [31:0] pmp_6_mask; // @[PMP.scala:24:19]
wire pmp_7_cfg_l; // @[PMP.scala:24:19]
wire [1:0] pmp_7_cfg_a; // @[PMP.scala:24:19]
wire pmp_7_cfg_x; // @[PMP.scala:24:19]
wire pmp_7_cfg_w; // @[PMP.scala:24:19]
wire pmp_7_cfg_r; // @[PMP.scala:24:19]
wire [29:0] pmp_7_addr; // @[PMP.scala:24:19]
wire [31:0] pmp_7_mask; // @[PMP.scala:24:19]
wire [31:0] _io_csrw_counter_T_11; // @[CSR.scala:1223:25]
wire _io_inhibit_cycle_T; // @[CSR.scala:591:40]
wire [31:0] io_trace_0_insn_0 = io_inst_0_0; // @[CSR.scala:377:7]
wire _io_trace_0_valid_T_1; // @[CSR.scala:1621:32]
wire [2:0] _io_trace_0_priv_T; // @[CSR.scala:1624:18]
wire _io_trace_0_exception_T_1; // @[CSR.scala:1620:37]
wire _io_trace_0_interrupt_T; // @[CSR.scala:1626:25]
wire [63:0] cause; // @[CSR.scala:959:8]
wire _io_fiom_T_6; // @[CSR.scala:631:113]
wire reg_custom_read; // @[CSR.scala:799:36]
wire [63:0] wdata; // @[CSR.scala:1643:39]
wire reg_custom_read_1; // @[CSR.scala:799:36]
wire reg_custom_read_2; // @[CSR.scala:799:36]
wire reg_custom_read_3; // @[CSR.scala:799:36]
wire [63:0] io_rw_rdata_0; // @[CSR.scala:377:7]
wire io_decode_0_fp_illegal_0; // @[CSR.scala:377:7]
wire io_decode_0_fp_csr_0; // @[CSR.scala:377:7]
wire io_decode_0_read_illegal_0; // @[CSR.scala:377:7]
wire io_decode_0_write_illegal_0; // @[CSR.scala:377:7]
wire io_decode_0_write_flush_0; // @[CSR.scala:377:7]
wire io_decode_0_system_illegal_0; // @[CSR.scala:377:7]
wire io_decode_0_virtual_access_illegal_0; // @[CSR.scala:377:7]
wire io_decode_0_virtual_system_illegal_0; // @[CSR.scala:377:7]
wire io_status_debug_0; // @[CSR.scala:377:7]
wire io_status_cease_0; // @[CSR.scala:377:7]
wire io_status_wfi_0; // @[CSR.scala:377:7]
wire [31:0] io_status_isa_0; // @[CSR.scala:377:7]
wire [1:0] io_status_dprv_0; // @[CSR.scala:377:7]
wire io_status_dv_0; // @[CSR.scala:377:7]
wire [1:0] io_status_prv_0; // @[CSR.scala:377:7]
wire io_status_v_0; // @[CSR.scala:377:7]
wire io_status_mpv_0; // @[CSR.scala:377:7]
wire io_status_gva_0; // @[CSR.scala:377:7]
wire io_status_tsr_0; // @[CSR.scala:377:7]
wire io_status_tw_0; // @[CSR.scala:377:7]
wire io_status_tvm_0; // @[CSR.scala:377:7]
wire io_status_mprv_0; // @[CSR.scala:377:7]
wire [1:0] io_status_mpp_0; // @[CSR.scala:377:7]
wire io_status_mpie_0; // @[CSR.scala:377:7]
wire io_status_mie_0; // @[CSR.scala:377:7]
wire io_hstatus_spvp_0; // @[CSR.scala:377:7]
wire io_hstatus_spv_0; // @[CSR.scala:377:7]
wire io_hstatus_gva_0; // @[CSR.scala:377:7]
wire io_gstatus_sd_0; // @[CSR.scala:377:7]
wire io_gstatus_spp_0; // @[CSR.scala:377:7]
wire io_gstatus_spie_0; // @[CSR.scala:377:7]
wire io_gstatus_sie_0; // @[CSR.scala:377:7]
wire [3:0] io_ptbr_mode_0; // @[CSR.scala:377:7]
wire [43:0] io_ptbr_ppn_0; // @[CSR.scala:377:7]
wire io_bp_0_control_dmode_0; // @[CSR.scala:377:7]
wire io_bp_0_control_action_0; // @[CSR.scala:377:7]
wire [1:0] io_bp_0_control_tmatch_0; // @[CSR.scala:377:7]
wire io_bp_0_control_m_0; // @[CSR.scala:377:7]
wire io_bp_0_control_s_0; // @[CSR.scala:377:7]
wire io_bp_0_control_u_0; // @[CSR.scala:377:7]
wire io_bp_0_control_x_0; // @[CSR.scala:377:7]
wire io_bp_0_control_w_0; // @[CSR.scala:377:7]
wire io_bp_0_control_r_0; // @[CSR.scala:377:7]
wire [38:0] io_bp_0_address_0; // @[CSR.scala:377:7]
wire io_pmp_0_cfg_l_0; // @[CSR.scala:377:7]
wire [1:0] io_pmp_0_cfg_a_0; // @[CSR.scala:377:7]
wire io_pmp_0_cfg_x_0; // @[CSR.scala:377:7]
wire io_pmp_0_cfg_w_0; // @[CSR.scala:377:7]
wire io_pmp_0_cfg_r_0; // @[CSR.scala:377:7]
wire [29:0] io_pmp_0_addr_0; // @[CSR.scala:377:7]
wire [31:0] io_pmp_0_mask_0; // @[CSR.scala:377:7]
wire io_pmp_1_cfg_l_0; // @[CSR.scala:377:7]
wire [1:0] io_pmp_1_cfg_a_0; // @[CSR.scala:377:7]
wire io_pmp_1_cfg_x_0; // @[CSR.scala:377:7]
wire io_pmp_1_cfg_w_0; // @[CSR.scala:377:7]
wire io_pmp_1_cfg_r_0; // @[CSR.scala:377:7]
wire [29:0] io_pmp_1_addr_0; // @[CSR.scala:377:7]
wire [31:0] io_pmp_1_mask_0; // @[CSR.scala:377:7]
wire io_pmp_2_cfg_l_0; // @[CSR.scala:377:7]
wire [1:0] io_pmp_2_cfg_a_0; // @[CSR.scala:377:7]
wire io_pmp_2_cfg_x_0; // @[CSR.scala:377:7]
wire io_pmp_2_cfg_w_0; // @[CSR.scala:377:7]
wire io_pmp_2_cfg_r_0; // @[CSR.scala:377:7]
wire [29:0] io_pmp_2_addr_0; // @[CSR.scala:377:7]
wire [31:0] io_pmp_2_mask_0; // @[CSR.scala:377:7]
wire io_pmp_3_cfg_l_0; // @[CSR.scala:377:7]
wire [1:0] io_pmp_3_cfg_a_0; // @[CSR.scala:377:7]
wire io_pmp_3_cfg_x_0; // @[CSR.scala:377:7]
wire io_pmp_3_cfg_w_0; // @[CSR.scala:377:7]
wire io_pmp_3_cfg_r_0; // @[CSR.scala:377:7]
wire [29:0] io_pmp_3_addr_0; // @[CSR.scala:377:7]
wire [31:0] io_pmp_3_mask_0; // @[CSR.scala:377:7]
wire io_pmp_4_cfg_l_0; // @[CSR.scala:377:7]
wire [1:0] io_pmp_4_cfg_a_0; // @[CSR.scala:377:7]
wire io_pmp_4_cfg_x_0; // @[CSR.scala:377:7]
wire io_pmp_4_cfg_w_0; // @[CSR.scala:377:7]
wire io_pmp_4_cfg_r_0; // @[CSR.scala:377:7]
wire [29:0] io_pmp_4_addr_0; // @[CSR.scala:377:7]
wire [31:0] io_pmp_4_mask_0; // @[CSR.scala:377:7]
wire io_pmp_5_cfg_l_0; // @[CSR.scala:377:7]
wire [1:0] io_pmp_5_cfg_a_0; // @[CSR.scala:377:7]
wire io_pmp_5_cfg_x_0; // @[CSR.scala:377:7]
wire io_pmp_5_cfg_w_0; // @[CSR.scala:377:7]
wire io_pmp_5_cfg_r_0; // @[CSR.scala:377:7]
wire [29:0] io_pmp_5_addr_0; // @[CSR.scala:377:7]
wire [31:0] io_pmp_5_mask_0; // @[CSR.scala:377:7]
wire io_pmp_6_cfg_l_0; // @[CSR.scala:377:7]
wire [1:0] io_pmp_6_cfg_a_0; // @[CSR.scala:377:7]
wire io_pmp_6_cfg_x_0; // @[CSR.scala:377:7]
wire io_pmp_6_cfg_w_0; // @[CSR.scala:377:7]
wire io_pmp_6_cfg_r_0; // @[CSR.scala:377:7]
wire [29:0] io_pmp_6_addr_0; // @[CSR.scala:377:7]
wire [31:0] io_pmp_6_mask_0; // @[CSR.scala:377:7]
wire io_pmp_7_cfg_l_0; // @[CSR.scala:377:7]
wire [1:0] io_pmp_7_cfg_a_0; // @[CSR.scala:377:7]
wire io_pmp_7_cfg_x_0; // @[CSR.scala:377:7]
wire io_pmp_7_cfg_w_0; // @[CSR.scala:377:7]
wire io_pmp_7_cfg_r_0; // @[CSR.scala:377:7]
wire [29:0] io_pmp_7_addr_0; // @[CSR.scala:377:7]
wire [31:0] io_pmp_7_mask_0; // @[CSR.scala:377:7]
wire io_trace_0_valid_0; // @[CSR.scala:377:7]
wire [2:0] io_trace_0_priv_0; // @[CSR.scala:377:7]
wire io_trace_0_exception_0; // @[CSR.scala:377:7]
wire io_trace_0_interrupt_0; // @[CSR.scala:377:7]
wire [63:0] io_trace_0_cause_0; // @[CSR.scala:377:7]
wire io_customCSRs_0_ren_0; // @[CSR.scala:377:7]
wire io_customCSRs_0_wen_0; // @[CSR.scala:377:7]
wire [63:0] io_customCSRs_0_wdata_0; // @[CSR.scala:377:7]
wire [63:0] io_customCSRs_0_value_0; // @[CSR.scala:377:7]
wire io_customCSRs_1_ren_0; // @[CSR.scala:377:7]
wire io_customCSRs_1_wen_0; // @[CSR.scala:377:7]
wire [63:0] io_customCSRs_1_wdata_0; // @[CSR.scala:377:7]
wire [63:0] io_customCSRs_1_value_0; // @[CSR.scala:377:7]
wire io_customCSRs_2_ren_0; // @[CSR.scala:377:7]
wire io_customCSRs_2_wen_0; // @[CSR.scala:377:7]
wire [63:0] io_customCSRs_2_wdata_0; // @[CSR.scala:377:7]
wire [63:0] io_customCSRs_2_value_0; // @[CSR.scala:377:7]
wire io_customCSRs_3_ren_0; // @[CSR.scala:377:7]
wire io_customCSRs_3_wen_0; // @[CSR.scala:377:7]
wire [63:0] io_customCSRs_3_wdata_0; // @[CSR.scala:377:7]
wire [63:0] io_customCSRs_3_value_0; // @[CSR.scala:377:7]
wire io_csr_stall_0; // @[CSR.scala:377:7]
wire io_eret_0; // @[CSR.scala:377:7]
wire io_singleStep_0; // @[CSR.scala:377:7]
wire [39:0] io_evec_0; // @[CSR.scala:377:7]
wire [63:0] io_time_0; // @[CSR.scala:377:7]
wire [2:0] io_fcsr_rm_0; // @[CSR.scala:377:7]
wire io_interrupt_0; // @[CSR.scala:377:7]
wire [63:0] io_interrupt_cause_0; // @[CSR.scala:377:7]
wire [31:0] io_csrw_counter; // @[CSR.scala:377:7]
wire io_inhibit_cycle_0; // @[CSR.scala:377:7]
wire io_fiom; // @[CSR.scala:377:7]
reg [1:0] reg_mstatus_prv; // @[CSR.scala:395:28]
assign io_status_prv_0 = reg_mstatus_prv; // @[CSR.scala:377:7, :395:28]
reg reg_mstatus_v; // @[CSR.scala:395:28]
assign io_status_v_0 = reg_mstatus_v; // @[CSR.scala:377:7, :395:28]
wire _io_decode_0_rocc_illegal_T_2 = reg_mstatus_v; // @[CSR.scala:395:28, :919:66]
reg reg_mstatus_mpv; // @[CSR.scala:395:28]
assign io_status_mpv_0 = reg_mstatus_mpv; // @[CSR.scala:377:7, :395:28]
reg reg_mstatus_gva; // @[CSR.scala:395:28]
assign io_status_gva_0 = reg_mstatus_gva; // @[CSR.scala:377:7, :395:28]
reg reg_mstatus_tsr; // @[CSR.scala:395:28]
assign io_status_tsr_0 = reg_mstatus_tsr; // @[CSR.scala:377:7, :395:28]
reg reg_mstatus_tw; // @[CSR.scala:395:28]
assign io_status_tw_0 = reg_mstatus_tw; // @[CSR.scala:377:7, :395:28]
reg reg_mstatus_tvm; // @[CSR.scala:395:28]
assign io_status_tvm_0 = reg_mstatus_tvm; // @[CSR.scala:377:7, :395:28]
reg reg_mstatus_mxr; // @[CSR.scala:395:28]
assign io_status_mxr_0 = reg_mstatus_mxr; // @[CSR.scala:377:7, :395:28]
reg reg_mstatus_sum; // @[CSR.scala:395:28]
assign io_status_sum_0 = reg_mstatus_sum; // @[CSR.scala:377:7, :395:28]
reg reg_mstatus_mprv; // @[CSR.scala:395:28]
assign io_status_mprv_0 = reg_mstatus_mprv; // @[CSR.scala:377:7, :395:28]
reg [1:0] reg_mstatus_fs; // @[CSR.scala:395:28]
assign io_status_fs_0 = reg_mstatus_fs; // @[CSR.scala:377:7, :395:28]
reg [1:0] reg_mstatus_mpp; // @[CSR.scala:395:28]
assign io_status_mpp_0 = reg_mstatus_mpp; // @[CSR.scala:377:7, :395:28]
reg reg_mstatus_spp; // @[CSR.scala:395:28]
assign io_status_spp_0 = reg_mstatus_spp; // @[CSR.scala:377:7, :395:28]
reg reg_mstatus_mpie; // @[CSR.scala:395:28]
assign io_status_mpie_0 = reg_mstatus_mpie; // @[CSR.scala:377:7, :395:28]
reg reg_mstatus_spie; // @[CSR.scala:395:28]
assign io_status_spie_0 = reg_mstatus_spie; // @[CSR.scala:377:7, :395:28]
reg reg_mstatus_mie; // @[CSR.scala:395:28]
assign io_status_mie_0 = reg_mstatus_mie; // @[CSR.scala:377:7, :395:28]
reg reg_mstatus_sie; // @[CSR.scala:395:28]
assign io_status_sie_0 = reg_mstatus_sie; // @[CSR.scala:377:7, :395:28]
wire [1:0] new_prv; // @[CSR.scala:397:28]
wire _reg_mstatus_prv_T = new_prv == 2'h2; // @[CSR.scala:397:28, :1647:35]
wire [1:0] _reg_mstatus_prv_T_1 = _reg_mstatus_prv_T ? 2'h0 : new_prv; // @[CSR.scala:397:28, :1647:{29,35}]
reg reg_dcsr_ebreakm; // @[CSR.scala:403:25]
reg reg_dcsr_ebreaks; // @[CSR.scala:403:25]
reg reg_dcsr_ebreaku; // @[CSR.scala:403:25]
reg [2:0] reg_dcsr_cause; // @[CSR.scala:403:25]
reg reg_dcsr_v; // @[CSR.scala:403:25]
reg reg_dcsr_step; // @[CSR.scala:403:25]
reg [1:0] reg_dcsr_prv; // @[CSR.scala:403:25]
reg reg_debug; // @[CSR.scala:482:26]
assign io_status_debug_0 = reg_debug; // @[CSR.scala:377:7, :482:26]
reg [39:0] reg_dpc; // @[CSR.scala:483:20]
reg [63:0] reg_dscratch0; // @[CSR.scala:484:26]
reg reg_singleStepped; // @[CSR.scala:486:30]
reg reg_bp_0_control_dmode; // @[CSR.scala:492:19]
assign io_bp_0_control_dmode_0 = reg_bp_0_control_dmode; // @[CSR.scala:377:7, :492:19]
reg reg_bp_0_control_action; // @[CSR.scala:492:19]
assign io_bp_0_control_action_0 = reg_bp_0_control_action; // @[CSR.scala:377:7, :492:19]
reg [1:0] reg_bp_0_control_tmatch; // @[CSR.scala:492:19]
assign io_bp_0_control_tmatch_0 = reg_bp_0_control_tmatch; // @[CSR.scala:377:7, :492:19]
reg reg_bp_0_control_m; // @[CSR.scala:492:19]
assign io_bp_0_control_m_0 = reg_bp_0_control_m; // @[CSR.scala:377:7, :492:19]
reg reg_bp_0_control_s; // @[CSR.scala:492:19]
assign io_bp_0_control_s_0 = reg_bp_0_control_s; // @[CSR.scala:377:7, :492:19]
reg reg_bp_0_control_u; // @[CSR.scala:492:19]
assign io_bp_0_control_u_0 = reg_bp_0_control_u; // @[CSR.scala:377:7, :492:19]
reg reg_bp_0_control_x; // @[CSR.scala:492:19]
assign io_bp_0_control_x_0 = reg_bp_0_control_x; // @[CSR.scala:377:7, :492:19]
reg reg_bp_0_control_w; // @[CSR.scala:492:19]
assign io_bp_0_control_w_0 = reg_bp_0_control_w; // @[CSR.scala:377:7, :492:19]
reg reg_bp_0_control_r; // @[CSR.scala:492:19]
assign io_bp_0_control_r_0 = reg_bp_0_control_r; // @[CSR.scala:377:7, :492:19]
reg [38:0] reg_bp_0_address; // @[CSR.scala:492:19]
assign io_bp_0_address_0 = reg_bp_0_address; // @[CSR.scala:377:7, :492:19]
reg reg_pmp_0_cfg_l; // @[CSR.scala:493:20]
assign pmp_cfg_l = reg_pmp_0_cfg_l; // @[PMP.scala:24:19]
reg [1:0] reg_pmp_0_cfg_a; // @[CSR.scala:493:20]
assign pmp_cfg_a = reg_pmp_0_cfg_a; // @[PMP.scala:24:19]
reg reg_pmp_0_cfg_x; // @[CSR.scala:493:20]
assign pmp_cfg_x = reg_pmp_0_cfg_x; // @[PMP.scala:24:19]
reg reg_pmp_0_cfg_w; // @[CSR.scala:493:20]
assign pmp_cfg_w = reg_pmp_0_cfg_w; // @[PMP.scala:24:19]
reg reg_pmp_0_cfg_r; // @[CSR.scala:493:20]
assign pmp_cfg_r = reg_pmp_0_cfg_r; // @[PMP.scala:24:19]
reg [29:0] reg_pmp_0_addr; // @[CSR.scala:493:20]
assign pmp_addr = reg_pmp_0_addr; // @[PMP.scala:24:19]
reg reg_pmp_1_cfg_l; // @[CSR.scala:493:20]
assign pmp_1_cfg_l = reg_pmp_1_cfg_l; // @[PMP.scala:24:19]
reg [1:0] reg_pmp_1_cfg_a; // @[CSR.scala:493:20]
assign pmp_1_cfg_a = reg_pmp_1_cfg_a; // @[PMP.scala:24:19]
reg reg_pmp_1_cfg_x; // @[CSR.scala:493:20]
assign pmp_1_cfg_x = reg_pmp_1_cfg_x; // @[PMP.scala:24:19]
reg reg_pmp_1_cfg_w; // @[CSR.scala:493:20]
assign pmp_1_cfg_w = reg_pmp_1_cfg_w; // @[PMP.scala:24:19]
reg reg_pmp_1_cfg_r; // @[CSR.scala:493:20]
assign pmp_1_cfg_r = reg_pmp_1_cfg_r; // @[PMP.scala:24:19]
reg [29:0] reg_pmp_1_addr; // @[CSR.scala:493:20]
assign pmp_1_addr = reg_pmp_1_addr; // @[PMP.scala:24:19]
reg reg_pmp_2_cfg_l; // @[CSR.scala:493:20]
assign pmp_2_cfg_l = reg_pmp_2_cfg_l; // @[PMP.scala:24:19]
reg [1:0] reg_pmp_2_cfg_a; // @[CSR.scala:493:20]
assign pmp_2_cfg_a = reg_pmp_2_cfg_a; // @[PMP.scala:24:19]
reg reg_pmp_2_cfg_x; // @[CSR.scala:493:20]
assign pmp_2_cfg_x = reg_pmp_2_cfg_x; // @[PMP.scala:24:19]
reg reg_pmp_2_cfg_w; // @[CSR.scala:493:20]
assign pmp_2_cfg_w = reg_pmp_2_cfg_w; // @[PMP.scala:24:19]
reg reg_pmp_2_cfg_r; // @[CSR.scala:493:20]
assign pmp_2_cfg_r = reg_pmp_2_cfg_r; // @[PMP.scala:24:19]
reg [29:0] reg_pmp_2_addr; // @[CSR.scala:493:20]
assign pmp_2_addr = reg_pmp_2_addr; // @[PMP.scala:24:19]
reg reg_pmp_3_cfg_l; // @[CSR.scala:493:20]
assign pmp_3_cfg_l = reg_pmp_3_cfg_l; // @[PMP.scala:24:19]
reg [1:0] reg_pmp_3_cfg_a; // @[CSR.scala:493:20]
assign pmp_3_cfg_a = reg_pmp_3_cfg_a; // @[PMP.scala:24:19]
reg reg_pmp_3_cfg_x; // @[CSR.scala:493:20]
assign pmp_3_cfg_x = reg_pmp_3_cfg_x; // @[PMP.scala:24:19]
reg reg_pmp_3_cfg_w; // @[CSR.scala:493:20]
assign pmp_3_cfg_w = reg_pmp_3_cfg_w; // @[PMP.scala:24:19]
reg reg_pmp_3_cfg_r; // @[CSR.scala:493:20]
assign pmp_3_cfg_r = reg_pmp_3_cfg_r; // @[PMP.scala:24:19]
reg [29:0] reg_pmp_3_addr; // @[CSR.scala:493:20]
assign pmp_3_addr = reg_pmp_3_addr; // @[PMP.scala:24:19]
reg reg_pmp_4_cfg_l; // @[CSR.scala:493:20]
assign pmp_4_cfg_l = reg_pmp_4_cfg_l; // @[PMP.scala:24:19]
reg [1:0] reg_pmp_4_cfg_a; // @[CSR.scala:493:20]
assign pmp_4_cfg_a = reg_pmp_4_cfg_a; // @[PMP.scala:24:19]
reg reg_pmp_4_cfg_x; // @[CSR.scala:493:20]
assign pmp_4_cfg_x = reg_pmp_4_cfg_x; // @[PMP.scala:24:19]
reg reg_pmp_4_cfg_w; // @[CSR.scala:493:20]
assign pmp_4_cfg_w = reg_pmp_4_cfg_w; // @[PMP.scala:24:19]
reg reg_pmp_4_cfg_r; // @[CSR.scala:493:20]
assign pmp_4_cfg_r = reg_pmp_4_cfg_r; // @[PMP.scala:24:19]
reg [29:0] reg_pmp_4_addr; // @[CSR.scala:493:20]
assign pmp_4_addr = reg_pmp_4_addr; // @[PMP.scala:24:19]
reg reg_pmp_5_cfg_l; // @[CSR.scala:493:20]
assign pmp_5_cfg_l = reg_pmp_5_cfg_l; // @[PMP.scala:24:19]
reg [1:0] reg_pmp_5_cfg_a; // @[CSR.scala:493:20]
assign pmp_5_cfg_a = reg_pmp_5_cfg_a; // @[PMP.scala:24:19]
reg reg_pmp_5_cfg_x; // @[CSR.scala:493:20]
assign pmp_5_cfg_x = reg_pmp_5_cfg_x; // @[PMP.scala:24:19]
reg reg_pmp_5_cfg_w; // @[CSR.scala:493:20]
assign pmp_5_cfg_w = reg_pmp_5_cfg_w; // @[PMP.scala:24:19]
reg reg_pmp_5_cfg_r; // @[CSR.scala:493:20]
assign pmp_5_cfg_r = reg_pmp_5_cfg_r; // @[PMP.scala:24:19]
reg [29:0] reg_pmp_5_addr; // @[CSR.scala:493:20]
assign pmp_5_addr = reg_pmp_5_addr; // @[PMP.scala:24:19]
reg reg_pmp_6_cfg_l; // @[CSR.scala:493:20]
assign pmp_6_cfg_l = reg_pmp_6_cfg_l; // @[PMP.scala:24:19]
reg [1:0] reg_pmp_6_cfg_a; // @[CSR.scala:493:20]
assign pmp_6_cfg_a = reg_pmp_6_cfg_a; // @[PMP.scala:24:19]
reg reg_pmp_6_cfg_x; // @[CSR.scala:493:20]
assign pmp_6_cfg_x = reg_pmp_6_cfg_x; // @[PMP.scala:24:19]
reg reg_pmp_6_cfg_w; // @[CSR.scala:493:20]
assign pmp_6_cfg_w = reg_pmp_6_cfg_w; // @[PMP.scala:24:19]
reg reg_pmp_6_cfg_r; // @[CSR.scala:493:20]
assign pmp_6_cfg_r = reg_pmp_6_cfg_r; // @[PMP.scala:24:19]
reg [29:0] reg_pmp_6_addr; // @[CSR.scala:493:20]
assign pmp_6_addr = reg_pmp_6_addr; // @[PMP.scala:24:19]
reg reg_pmp_7_cfg_l; // @[CSR.scala:493:20]
assign pmp_7_cfg_l = reg_pmp_7_cfg_l; // @[PMP.scala:24:19]
reg [1:0] reg_pmp_7_cfg_a; // @[CSR.scala:493:20]
assign pmp_7_cfg_a = reg_pmp_7_cfg_a; // @[PMP.scala:24:19]
reg reg_pmp_7_cfg_x; // @[CSR.scala:493:20]
assign pmp_7_cfg_x = reg_pmp_7_cfg_x; // @[PMP.scala:24:19]
reg reg_pmp_7_cfg_w; // @[CSR.scala:493:20]
assign pmp_7_cfg_w = reg_pmp_7_cfg_w; // @[PMP.scala:24:19]
reg reg_pmp_7_cfg_r; // @[CSR.scala:493:20]
assign pmp_7_cfg_r = reg_pmp_7_cfg_r; // @[PMP.scala:24:19]
reg [29:0] reg_pmp_7_addr; // @[CSR.scala:493:20]
assign pmp_7_addr = reg_pmp_7_addr; // @[PMP.scala:24:19]
reg [63:0] reg_mie; // @[CSR.scala:495:20]
reg [63:0] reg_mideleg; // @[CSR.scala:497:18]
wire [63:0] read_mideleg = {54'h0, reg_mideleg[9:1] & 9'h111, 1'h0}; // @[CSR.scala:497:18, :498:{14,38,61}]
reg [63:0] reg_medeleg; // @[CSR.scala:501:18]
wire [63:0] read_medeleg = {48'h0, reg_medeleg[15:0] & 16'hB15D}; // @[CSR.scala:501:18, :502:{14,38}]
reg reg_mip_seip; // @[CSR.scala:504:20]
reg reg_mip_stip; // @[CSR.scala:504:20]
wire mip_stip = reg_mip_stip; // @[CSR.scala:504:20, :600:24]
reg reg_mip_ssip; // @[CSR.scala:504:20]
wire mip_ssip = reg_mip_ssip; // @[CSR.scala:504:20, :600:24]
reg [39:0] reg_mepc; // @[CSR.scala:505:21]
reg [63:0] reg_mcause; // @[CSR.scala:506:27]
reg [39:0] reg_mtval; // @[CSR.scala:507:22]
reg [39:0] reg_mtval2; // @[CSR.scala:508:23]
reg [63:0] reg_mscratch; // @[CSR.scala:509:25]
reg [31:0] reg_mtvec; // @[CSR.scala:512:31]
reg reg_menvcfg_fiom; // @[CSR.scala:525:28]
reg reg_senvcfg_fiom; // @[CSR.scala:526:28]
reg [31:0] reg_mcounteren; // @[CSR.scala:531:18]
wire [31:0] read_mcounteren = {29'h0, reg_mcounteren[2:0]}; // @[CSR.scala:531:18, :532:{14,32}]
reg [31:0] reg_scounteren; // @[CSR.scala:535:18]
wire [31:0] read_scounteren = {29'h0, reg_scounteren[2:0]}; // @[CSR.scala:535:18, :536:{14,38}]
reg reg_hstatus_spvp; // @[CSR.scala:552:28]
assign io_hstatus_spvp_0 = reg_hstatus_spvp; // @[CSR.scala:377:7, :552:28]
reg reg_hstatus_spv; // @[CSR.scala:552:28]
assign io_hstatus_spv_0 = reg_hstatus_spv; // @[CSR.scala:377:7, :552:28]
reg reg_hstatus_gva; // @[CSR.scala:552:28]
assign io_hstatus_gva_0 = reg_hstatus_gva; // @[CSR.scala:377:7, :552:28]
reg [39:0] reg_htval; // @[CSR.scala:554:22]
wire [1:0] _GEN = {reg_mip_ssip, 1'h0}; // @[CSR.scala:504:20, :555:27]
wire [1:0] read_hvip_lo_lo_lo; // @[CSR.scala:555:27]
assign read_hvip_lo_lo_lo = _GEN; // @[CSR.scala:555:27]
wire [1:0] new_mip_lo_lo_lo; // @[CSR.scala:1271:59]
assign new_mip_lo_lo_lo = _GEN; // @[CSR.scala:555:27, :1271:59]
wire [3:0] read_hvip_lo_lo = {read_hvip_lo_lo_hi, read_hvip_lo_lo_lo}; // @[CSR.scala:555:27]
wire [1:0] _GEN_0 = {reg_mip_stip, 1'h0}; // @[CSR.scala:504:20, :555:27]
wire [1:0] read_hvip_lo_hi_lo; // @[CSR.scala:555:27]
assign read_hvip_lo_hi_lo = _GEN_0; // @[CSR.scala:555:27]
wire [1:0] new_mip_lo_hi_lo; // @[CSR.scala:1271:59]
assign new_mip_lo_hi_lo = _GEN_0; // @[CSR.scala:555:27, :1271:59]
wire [3:0] read_hvip_lo_hi = {read_hvip_lo_hi_hi, read_hvip_lo_hi_lo}; // @[CSR.scala:555:27]
wire [7:0] read_hvip_lo = {read_hvip_lo_hi, read_hvip_lo_lo}; // @[CSR.scala:555:27]
wire [1:0] _GEN_1 = {reg_mip_seip, 1'h0}; // @[CSR.scala:504:20, :555:27]
wire [1:0] read_hvip_hi_lo_lo; // @[CSR.scala:555:27]
assign read_hvip_hi_lo_lo = _GEN_1; // @[CSR.scala:555:27]
wire [1:0] new_mip_hi_lo_lo; // @[CSR.scala:1271:59]
assign new_mip_hi_lo_lo = _GEN_1; // @[CSR.scala:555:27, :1271:59]
wire [3:0] read_hvip_hi_lo = {read_hvip_hi_lo_hi, read_hvip_hi_lo_lo}; // @[CSR.scala:555:27]
wire [1:0] read_hvip_hi_hi_hi = {read_hvip_hi_hi_hi_hi, 1'h0}; // @[CSR.scala:555:27]
wire [3:0] read_hvip_hi_hi = {read_hvip_hi_hi_hi, read_hvip_hi_hi_lo}; // @[CSR.scala:555:27]
wire [7:0] read_hvip_hi = {read_hvip_hi_hi, read_hvip_hi_lo}; // @[CSR.scala:555:27]
wire [15:0] _read_hvip_T = {read_hvip_hi, read_hvip_lo}; // @[CSR.scala:555:27]
reg reg_vsstatus_spp; // @[CSR.scala:562:25]
assign io_gstatus_spp_0 = reg_vsstatus_spp; // @[CSR.scala:377:7, :562:25]
reg reg_vsstatus_spie; // @[CSR.scala:562:25]
assign io_gstatus_spie_0 = reg_vsstatus_spie; // @[CSR.scala:377:7, :562:25]
reg reg_vsstatus_sie; // @[CSR.scala:562:25]
assign io_gstatus_sie_0 = reg_vsstatus_sie; // @[CSR.scala:377:7, :562:25]
reg [39:0] reg_vsepc; // @[CSR.scala:564:22]
reg [63:0] reg_vscause; // @[CSR.scala:565:24]
reg [39:0] reg_vstval; // @[CSR.scala:566:23]
reg [39:0] reg_sepc; // @[CSR.scala:569:21]
reg [63:0] reg_scause; // @[CSR.scala:570:23]
reg [39:0] reg_stval; // @[CSR.scala:571:22]
reg [63:0] reg_sscratch; // @[CSR.scala:572:25]
reg [38:0] reg_stvec; // @[CSR.scala:573:22]
reg [3:0] reg_satp_mode; // @[CSR.scala:574:21]
assign io_ptbr_mode_0 = reg_satp_mode; // @[CSR.scala:377:7, :574:21]
reg [43:0] reg_satp_ppn; // @[CSR.scala:574:21]
assign io_ptbr_ppn_0 = reg_satp_ppn; // @[CSR.scala:377:7, :574:21]
reg reg_wfi; // @[CSR.scala:575:54]
assign io_status_wfi_0 = reg_wfi; // @[CSR.scala:377:7, :575:54]
reg [4:0] reg_fflags; // @[CSR.scala:577:23]
reg [2:0] reg_frm; // @[CSR.scala:578:20]
assign io_fcsr_rm_0 = reg_frm; // @[CSR.scala:377:7, :578:20]
reg reg_mtinst_read_pseudo; // @[CSR.scala:584:35]
reg reg_htinst_read_pseudo; // @[CSR.scala:585:35]
wire [1:0] hi_4 = {2{reg_mtinst_read_pseudo}}; // @[CSR.scala:584:35, :588:103]
wire [13:0] read_mtinst = {hi_4, 12'h0}; // @[CSR.scala:588:103]
wire [1:0] hi_5 = {2{reg_htinst_read_pseudo}}; // @[CSR.scala:585:35, :588:103]
wire [13:0] read_htinst = {hi_5, 12'h0}; // @[CSR.scala:588:103]
reg [2:0] reg_mcountinhibit; // @[CSR.scala:590:34]
assign _io_inhibit_cycle_T = reg_mcountinhibit[0]; // @[CSR.scala:590:34, :591:40]
wire x11 = reg_mcountinhibit[0]; // @[CSR.scala:590:34, :591:40, :594:98]
assign io_inhibit_cycle_0 = _io_inhibit_cycle_T; // @[CSR.scala:377:7, :591:40]
wire x3 = reg_mcountinhibit[2]; // @[CSR.scala:590:34, :592:75]
reg [5:0] small_0; // @[Counters.scala:45:41]
wire [6:0] nextSmall = {1'h0, small_0} + {6'h0, io_retire_0}; // @[Counters.scala:45:41, :46:33]
wire _large_T_1 = ~x3; // @[Counters.scala:47:9, :51:36]
reg [57:0] large_0; // @[Counters.scala:50:31]
wire _large_T = nextSmall[6]; // @[Counters.scala:46:33, :51:20]
wire _large_T_2 = _large_T & _large_T_1; // @[Counters.scala:51:{20,33,36}]
wire [58:0] _large_r_T = {1'h0, large_0} + 59'h1; // @[Counters.scala:50:31, :51:55]
wire [57:0] _large_r_T_1 = _large_r_T[57:0]; // @[Counters.scala:51:55]
wire [63:0] value = {large_0, small_0}; // @[Counters.scala:45:41, :50:31, :55:30]
wire x10 = ~io_csr_stall_0; // @[CSR.scala:377:7, :594:56]
reg [5:0] small_1; // @[Counters.scala:45:41]
wire [6:0] nextSmall_1 = {1'h0, small_1} + {6'h0, x10}; // @[Counters.scala:45:41, :46:33]
wire _large_T_4 = ~x11; // @[Counters.scala:47:9, :51:36]
reg [57:0] large_1; // @[Counters.scala:50:31]
wire _large_T_3 = nextSmall_1[6]; // @[Counters.scala:46:33, :51:20]
wire _large_T_5 = _large_T_3 & _large_T_4; // @[Counters.scala:51:{20,33,36}]
wire [58:0] _large_r_T_2 = {1'h0, large_1} + 59'h1; // @[Counters.scala:50:31, :51:55]
wire [57:0] _large_r_T_3 = _large_r_T_2[57:0]; // @[Counters.scala:51:55]
assign value_1 = {large_1, small_1}; // @[Counters.scala:45:41, :50:31, :55:30]
assign io_time_0 = value_1; // @[Counters.scala:55:30]
wire read_mip_hi_hi_hi_hi = mip_zero1; // @[CSR.scala:600:24, :610:22]
wire _mip_seip_T; // @[CSR.scala:606:57]
wire mip_seip; // @[CSR.scala:600:24]
assign _mip_seip_T = reg_mip_seip | io_interrupts_seip_0; // @[CSR.scala:377:7, :504:20, :606:57]
assign mip_seip = _mip_seip_T; // @[CSR.scala:600:24, :606:57]
wire [1:0] read_mip_lo_lo_lo = {mip_ssip, mip_usip}; // @[CSR.scala:600:24, :610:22]
wire [1:0] read_mip_lo_lo_hi = {mip_msip, mip_vssip}; // @[CSR.scala:600:24, :610:22]
wire [3:0] read_mip_lo_lo = {read_mip_lo_lo_hi, read_mip_lo_lo_lo}; // @[CSR.scala:610:22]
wire [1:0] read_mip_lo_hi_lo = {mip_stip, mip_utip}; // @[CSR.scala:600:24, :610:22]
wire [1:0] read_mip_lo_hi_hi = {mip_mtip, mip_vstip}; // @[CSR.scala:600:24, :610:22]
wire [3:0] read_mip_lo_hi = {read_mip_lo_hi_hi, read_mip_lo_hi_lo}; // @[CSR.scala:610:22]
wire [7:0] read_mip_lo = {read_mip_lo_hi, read_mip_lo_lo}; // @[CSR.scala:610:22]
wire [1:0] read_mip_hi_lo_lo = {mip_seip, mip_ueip}; // @[CSR.scala:600:24, :610:22]
wire [1:0] read_mip_hi_lo_hi = {mip_meip, mip_vseip}; // @[CSR.scala:600:24, :610:22]
wire [3:0] read_mip_hi_lo = {read_mip_hi_lo_hi, read_mip_hi_lo_lo}; // @[CSR.scala:610:22]
wire [1:0] read_mip_hi_hi_lo = {1'h0, mip_sgeip}; // @[CSR.scala:600:24, :610:22]
wire [1:0] read_mip_hi_hi_hi = {read_mip_hi_hi_hi_hi, mip_debug}; // @[CSR.scala:600:24, :610:22]
wire [3:0] read_mip_hi_hi = {read_mip_hi_hi_hi, read_mip_hi_hi_lo}; // @[CSR.scala:610:22]
wire [7:0] read_mip_hi = {read_mip_hi_hi, read_mip_hi_lo}; // @[CSR.scala:610:22]
wire [15:0] _read_mip_T = {read_mip_hi, read_mip_lo}; // @[CSR.scala:610:22]
wire [15:0] read_mip = _read_mip_T & 16'hAAA; // @[CSR.scala:610:{22,29}]
wire [63:0] _pending_interrupts_T = {48'h0, reg_mie[15:0] & read_mip}; // @[CSR.scala:495:20, :610:29, :614:56]
wire [63:0] pending_interrupts = _pending_interrupts_T; // @[CSR.scala:614:{44,56}]
wire [14:0] d_interrupts = {io_interrupts_debug_0, 14'h0}; // @[CSR.scala:377:7, :615:42]
wire _allow_wfi_T = reg_mstatus_prv[1]; // @[CSR.scala:395:28, :620:51, :906:61]
wire _allow_sfence_vma_T = reg_mstatus_prv[1]; // @[CSR.scala:395:28, :620:51, :907:60]
wire _allow_sret_T = reg_mstatus_prv[1]; // @[CSR.scala:395:28, :620:51, :910:62]
wire _allow_counter_T = reg_mstatus_prv[1]; // @[CSR.scala:395:28, :620:51, :912:42]
wire _m_interrupts_T = ~(reg_mstatus_prv[1]); // @[CSR.scala:395:28, :620:51]
wire _m_interrupts_T_1 = _m_interrupts_T | reg_mstatus_mie; // @[CSR.scala:395:28, :620:{51,62}]
wire _m_interrupts_T_2 = _m_interrupts_T_1; // @[CSR.scala:620:{31,62}]
wire [63:0] _m_interrupts_T_3 = ~pending_interrupts; // @[CSR.scala:614:44, :620:85]
wire [63:0] _m_interrupts_T_4 = _m_interrupts_T_3 | read_mideleg; // @[CSR.scala:498:14, :620:{85,105}]
wire [63:0] _m_interrupts_T_5 = ~_m_interrupts_T_4; // @[CSR.scala:620:{83,105}]
wire [63:0] m_interrupts = _m_interrupts_T_2 ? _m_interrupts_T_5 : 64'h0; // @[CSR.scala:620:{25,31,83}]
wire _GEN_2 = reg_mstatus_prv == 2'h0; // @[CSR.scala:395:28, :621:68]
wire _s_interrupts_T; // @[CSR.scala:621:68]
assign _s_interrupts_T = _GEN_2; // @[CSR.scala:621:68]
wire _vs_interrupts_T; // @[CSR.scala:622:70]
assign _vs_interrupts_T = _GEN_2; // @[CSR.scala:621:68, :622:70]
wire _io_fiom_T_2; // @[CSR.scala:631:82]
assign _io_fiom_T_2 = _GEN_2; // @[CSR.scala:621:68, :631:82]
wire _s_interrupts_T_1 = reg_mstatus_v | _s_interrupts_T; // @[CSR.scala:395:28, :621:{49,68}]
wire _GEN_3 = reg_mstatus_prv == 2'h1; // @[CSR.scala:395:28, :621:98]
wire _s_interrupts_T_2; // @[CSR.scala:621:98]
assign _s_interrupts_T_2 = _GEN_3; // @[CSR.scala:621:98]
wire _vs_interrupts_T_1; // @[CSR.scala:622:99]
assign _vs_interrupts_T_1 = _GEN_3; // @[CSR.scala:621:98, :622:99]
wire _csr_addr_legal_T_4; // @[CSR.scala:921:62]
assign _csr_addr_legal_T_4 = _GEN_3; // @[CSR.scala:621:98, :921:62]
wire _s_interrupts_T_3 = _s_interrupts_T_2 & reg_mstatus_sie; // @[CSR.scala:395:28, :621:{98,110}]
wire _s_interrupts_T_4 = _s_interrupts_T_1 | _s_interrupts_T_3; // @[CSR.scala:621:{49,78,110}]
wire _s_interrupts_T_5 = _s_interrupts_T_4; // @[CSR.scala:621:{31,78}]
wire [63:0] _s_interrupts_T_6 = pending_interrupts & read_mideleg; // @[CSR.scala:498:14, :614:44, :621:151]
wire [63:0] _s_interrupts_T_8 = _s_interrupts_T_6; // @[CSR.scala:621:{151,166}]
wire [63:0] s_interrupts = _s_interrupts_T_5 ? _s_interrupts_T_8 : 64'h0; // @[CSR.scala:621:{25,31,166}]
wire _vs_interrupts_T_2 = _vs_interrupts_T_1 & reg_vsstatus_sie; // @[CSR.scala:562:25, :622:{99,111}]
wire _vs_interrupts_T_3 = _vs_interrupts_T | _vs_interrupts_T_2; // @[CSR.scala:622:{70,80,111}]
wire _vs_interrupts_T_4 = reg_mstatus_v & _vs_interrupts_T_3; // @[CSR.scala:395:28, :622:{50,80}]
wire _vs_interrupts_T_5 = _vs_interrupts_T_4; // @[CSR.scala:622:{32,50}]
wire _any_T = d_interrupts[14]; // @[CSR.scala:615:42, :1637:76]
wire _which_T = d_interrupts[14]; // @[CSR.scala:615:42, :1637:76, :1638:91]
wire _any_T_1 = d_interrupts[13]; // @[CSR.scala:615:42, :1637:76]
wire _which_T_1 = d_interrupts[13]; // @[CSR.scala:615:42, :1637:76, :1638:91]
wire _any_T_2 = d_interrupts[12]; // @[CSR.scala:615:42, :1637:76]
wire _which_T_2 = d_interrupts[12]; // @[CSR.scala:615:42, :1637:76, :1638:91]
wire _any_T_3 = d_interrupts[11]; // @[CSR.scala:615:42, :1637:76]
wire _which_T_3 = d_interrupts[11]; // @[CSR.scala:615:42, :1637:76, :1638:91]
wire _any_T_4 = d_interrupts[3]; // @[CSR.scala:615:42, :1637:76]
wire _which_T_4 = d_interrupts[3]; // @[CSR.scala:615:42, :1637:76, :1638:91]
wire _any_T_5 = d_interrupts[7]; // @[CSR.scala:615:42, :1637:76]
wire _which_T_5 = d_interrupts[7]; // @[CSR.scala:615:42, :1637:76, :1638:91]
wire _any_T_6 = d_interrupts[9]; // @[CSR.scala:615:42, :1637:76]
wire _which_T_6 = d_interrupts[9]; // @[CSR.scala:615:42, :1637:76, :1638:91]
wire _any_T_7 = d_interrupts[1]; // @[CSR.scala:615:42, :1637:76]
wire _which_T_7 = d_interrupts[1]; // @[CSR.scala:615:42, :1637:76, :1638:91]
wire _any_T_8 = d_interrupts[5]; // @[CSR.scala:615:42, :1637:76]
wire _which_T_8 = d_interrupts[5]; // @[CSR.scala:615:42, :1637:76, :1638:91]
wire _any_T_9 = d_interrupts[10]; // @[CSR.scala:615:42, :1637:76]
wire _which_T_9 = d_interrupts[10]; // @[CSR.scala:615:42, :1637:76, :1638:91]
wire _any_T_10 = d_interrupts[2]; // @[CSR.scala:615:42, :1637:76]
wire _which_T_10 = d_interrupts[2]; // @[CSR.scala:615:42, :1637:76, :1638:91]
wire _any_T_11 = d_interrupts[6]; // @[CSR.scala:615:42, :1637:76]
wire _which_T_11 = d_interrupts[6]; // @[CSR.scala:615:42, :1637:76, :1638:91]
wire _any_T_12 = d_interrupts[8]; // @[CSR.scala:615:42, :1637:76]
wire _which_T_12 = d_interrupts[8]; // @[CSR.scala:615:42, :1637:76, :1638:91]
wire _any_T_13 = d_interrupts[0]; // @[CSR.scala:615:42, :1637:76]
wire _which_T_13 = d_interrupts[0]; // @[CSR.scala:615:42, :1637:76, :1638:91]
wire _any_T_14 = d_interrupts[4]; // @[CSR.scala:615:42, :1637:76]
wire _which_T_14 = d_interrupts[4]; // @[CSR.scala:615:42, :1637:76, :1638:91]
wire _any_T_15 = m_interrupts[15]; // @[CSR.scala:620:25, :1637:76]
wire _which_T_15 = m_interrupts[15]; // @[CSR.scala:620:25, :1637:76, :1638:91]
wire _any_T_16 = m_interrupts[14]; // @[CSR.scala:620:25, :1637:76]
wire _which_T_16 = m_interrupts[14]; // @[CSR.scala:620:25, :1637:76, :1638:91]
wire _any_T_17 = m_interrupts[13]; // @[CSR.scala:620:25, :1637:76]
wire _which_T_17 = m_interrupts[13]; // @[CSR.scala:620:25, :1637:76, :1638:91]
wire _any_T_18 = m_interrupts[12]; // @[CSR.scala:620:25, :1637:76]
wire _which_T_18 = m_interrupts[12]; // @[CSR.scala:620:25, :1637:76, :1638:91]
wire _any_T_19 = m_interrupts[11]; // @[CSR.scala:620:25, :1637:76]
wire _which_T_19 = m_interrupts[11]; // @[CSR.scala:620:25, :1637:76, :1638:91]
wire _any_T_20 = m_interrupts[3]; // @[CSR.scala:620:25, :1637:76]
wire _which_T_20 = m_interrupts[3]; // @[CSR.scala:620:25, :1637:76, :1638:91]
wire _any_T_21 = m_interrupts[7]; // @[CSR.scala:620:25, :1637:76]
wire _which_T_21 = m_interrupts[7]; // @[CSR.scala:620:25, :1637:76, :1638:91]
wire _any_T_22 = m_interrupts[9]; // @[CSR.scala:620:25, :1637:76]
wire _which_T_22 = m_interrupts[9]; // @[CSR.scala:620:25, :1637:76, :1638:91]
wire _any_T_23 = m_interrupts[1]; // @[CSR.scala:620:25, :1637:76]
wire _which_T_23 = m_interrupts[1]; // @[CSR.scala:620:25, :1637:76, :1638:91]
wire _any_T_24 = m_interrupts[5]; // @[CSR.scala:620:25, :1637:76]
wire _which_T_24 = m_interrupts[5]; // @[CSR.scala:620:25, :1637:76, :1638:91]
wire _any_T_25 = m_interrupts[10]; // @[CSR.scala:620:25, :1637:76]
wire _which_T_25 = m_interrupts[10]; // @[CSR.scala:620:25, :1637:76, :1638:91]
wire _any_T_26 = m_interrupts[2]; // @[CSR.scala:620:25, :1637:76]
wire _which_T_26 = m_interrupts[2]; // @[CSR.scala:620:25, :1637:76, :1638:91]
wire _any_T_27 = m_interrupts[6]; // @[CSR.scala:620:25, :1637:76]
wire _which_T_27 = m_interrupts[6]; // @[CSR.scala:620:25, :1637:76, :1638:91]
wire _any_T_28 = m_interrupts[8]; // @[CSR.scala:620:25, :1637:76]
wire _which_T_28 = m_interrupts[8]; // @[CSR.scala:620:25, :1637:76, :1638:91]
wire _any_T_29 = m_interrupts[0]; // @[CSR.scala:620:25, :1637:76]
wire _which_T_29 = m_interrupts[0]; // @[CSR.scala:620:25, :1637:76, :1638:91]
wire _any_T_30 = m_interrupts[4]; // @[CSR.scala:620:25, :1637:76]
wire _which_T_30 = m_interrupts[4]; // @[CSR.scala:620:25, :1637:76, :1638:91]
wire _any_T_31 = s_interrupts[15]; // @[CSR.scala:621:25, :1637:76]
wire _which_T_31 = s_interrupts[15]; // @[CSR.scala:621:25, :1637:76, :1638:91]
wire _any_T_32 = s_interrupts[14]; // @[CSR.scala:621:25, :1637:76]
wire _which_T_32 = s_interrupts[14]; // @[CSR.scala:621:25, :1637:76, :1638:91]
wire _any_T_33 = s_interrupts[13]; // @[CSR.scala:621:25, :1637:76]
wire _which_T_33 = s_interrupts[13]; // @[CSR.scala:621:25, :1637:76, :1638:91]
wire _any_T_34 = s_interrupts[12]; // @[CSR.scala:621:25, :1637:76]
wire _which_T_34 = s_interrupts[12]; // @[CSR.scala:621:25, :1637:76, :1638:91]
wire _any_T_35 = s_interrupts[11]; // @[CSR.scala:621:25, :1637:76]
wire _which_T_35 = s_interrupts[11]; // @[CSR.scala:621:25, :1637:76, :1638:91]
wire _any_T_36 = s_interrupts[3]; // @[CSR.scala:621:25, :1637:76]
wire _which_T_36 = s_interrupts[3]; // @[CSR.scala:621:25, :1637:76, :1638:91]
wire _any_T_37 = s_interrupts[7]; // @[CSR.scala:621:25, :1637:76]
wire _which_T_37 = s_interrupts[7]; // @[CSR.scala:621:25, :1637:76, :1638:91]
wire _any_T_38 = s_interrupts[9]; // @[CSR.scala:621:25, :1637:76]
wire _which_T_38 = s_interrupts[9]; // @[CSR.scala:621:25, :1637:76, :1638:91]
wire _any_T_39 = s_interrupts[1]; // @[CSR.scala:621:25, :1637:76]
wire _which_T_39 = s_interrupts[1]; // @[CSR.scala:621:25, :1637:76, :1638:91]
wire _any_T_40 = s_interrupts[5]; // @[CSR.scala:621:25, :1637:76]
wire _which_T_40 = s_interrupts[5]; // @[CSR.scala:621:25, :1637:76, :1638:91]
wire _any_T_41 = s_interrupts[10]; // @[CSR.scala:621:25, :1637:76]
wire _which_T_41 = s_interrupts[10]; // @[CSR.scala:621:25, :1637:76, :1638:91]
wire _any_T_42 = s_interrupts[2]; // @[CSR.scala:621:25, :1637:76]
wire _which_T_42 = s_interrupts[2]; // @[CSR.scala:621:25, :1637:76, :1638:91]
wire _any_T_43 = s_interrupts[6]; // @[CSR.scala:621:25, :1637:76]
wire _which_T_43 = s_interrupts[6]; // @[CSR.scala:621:25, :1637:76, :1638:91]
wire _any_T_44 = s_interrupts[8]; // @[CSR.scala:621:25, :1637:76]
wire _which_T_44 = s_interrupts[8]; // @[CSR.scala:621:25, :1637:76, :1638:91]
wire _any_T_45 = s_interrupts[0]; // @[CSR.scala:621:25, :1637:76]
wire _which_T_45 = s_interrupts[0]; // @[CSR.scala:621:25, :1637:76, :1638:91]
wire _any_T_46 = s_interrupts[4]; // @[CSR.scala:621:25, :1637:76]
wire _which_T_46 = s_interrupts[4]; // @[CSR.scala:621:25, :1637:76, :1638:91]
wire _any_T_63 = _any_T | _any_T_1; // @[CSR.scala:1637:{76,90}]
wire _any_T_64 = _any_T_63 | _any_T_2; // @[CSR.scala:1637:{76,90}]
wire _any_T_65 = _any_T_64 | _any_T_3; // @[CSR.scala:1637:{76,90}]
wire _any_T_66 = _any_T_65 | _any_T_4; // @[CSR.scala:1637:{76,90}]
wire _any_T_67 = _any_T_66 | _any_T_5; // @[CSR.scala:1637:{76,90}]
wire _any_T_68 = _any_T_67 | _any_T_6; // @[CSR.scala:1637:{76,90}]
wire _any_T_69 = _any_T_68 | _any_T_7; // @[CSR.scala:1637:{76,90}]
wire _any_T_70 = _any_T_69 | _any_T_8; // @[CSR.scala:1637:{76,90}]
wire _any_T_71 = _any_T_70 | _any_T_9; // @[CSR.scala:1637:{76,90}]
wire _any_T_72 = _any_T_71 | _any_T_10; // @[CSR.scala:1637:{76,90}]
wire _any_T_73 = _any_T_72 | _any_T_11; // @[CSR.scala:1637:{76,90}]
wire _any_T_74 = _any_T_73 | _any_T_12; // @[CSR.scala:1637:{76,90}]
wire _any_T_75 = _any_T_74 | _any_T_13; // @[CSR.scala:1637:{76,90}]
wire _any_T_76 = _any_T_75 | _any_T_14; // @[CSR.scala:1637:{76,90}]
wire _any_T_77 = _any_T_76; // @[CSR.scala:1637:90]
wire _any_T_78 = _any_T_77 | _any_T_15; // @[CSR.scala:1637:{76,90}]
wire _any_T_79 = _any_T_78 | _any_T_16; // @[CSR.scala:1637:{76,90}]
wire _any_T_80 = _any_T_79 | _any_T_17; // @[CSR.scala:1637:{76,90}]
wire _any_T_81 = _any_T_80 | _any_T_18; // @[CSR.scala:1637:{76,90}]
wire _any_T_82 = _any_T_81 | _any_T_19; // @[CSR.scala:1637:{76,90}]
wire _any_T_83 = _any_T_82 | _any_T_20; // @[CSR.scala:1637:{76,90}]
wire _any_T_84 = _any_T_83 | _any_T_21; // @[CSR.scala:1637:{76,90}]
wire _any_T_85 = _any_T_84 | _any_T_22; // @[CSR.scala:1637:{76,90}]
wire _any_T_86 = _any_T_85 | _any_T_23; // @[CSR.scala:1637:{76,90}]
wire _any_T_87 = _any_T_86 | _any_T_24; // @[CSR.scala:1637:{76,90}]
wire _any_T_88 = _any_T_87 | _any_T_25; // @[CSR.scala:1637:{76,90}]
wire _any_T_89 = _any_T_88 | _any_T_26; // @[CSR.scala:1637:{76,90}]
wire _any_T_90 = _any_T_89 | _any_T_27; // @[CSR.scala:1637:{76,90}]
wire _any_T_91 = _any_T_90 | _any_T_28; // @[CSR.scala:1637:{76,90}]
wire _any_T_92 = _any_T_91 | _any_T_29; // @[CSR.scala:1637:{76,90}]
wire _any_T_93 = _any_T_92 | _any_T_30; // @[CSR.scala:1637:{76,90}]
wire _any_T_94 = _any_T_93 | _any_T_31; // @[CSR.scala:1637:{76,90}]
wire _any_T_95 = _any_T_94 | _any_T_32; // @[CSR.scala:1637:{76,90}]
wire _any_T_96 = _any_T_95 | _any_T_33; // @[CSR.scala:1637:{76,90}]
wire _any_T_97 = _any_T_96 | _any_T_34; // @[CSR.scala:1637:{76,90}]
wire _any_T_98 = _any_T_97 | _any_T_35; // @[CSR.scala:1637:{76,90}]
wire _any_T_99 = _any_T_98 | _any_T_36; // @[CSR.scala:1637:{76,90}]
wire _any_T_100 = _any_T_99 | _any_T_37; // @[CSR.scala:1637:{76,90}]
wire _any_T_101 = _any_T_100 | _any_T_38; // @[CSR.scala:1637:{76,90}]
wire _any_T_102 = _any_T_101 | _any_T_39; // @[CSR.scala:1637:{76,90}]
wire _any_T_103 = _any_T_102 | _any_T_40; // @[CSR.scala:1637:{76,90}]
wire _any_T_104 = _any_T_103 | _any_T_41; // @[CSR.scala:1637:{76,90}]
wire _any_T_105 = _any_T_104 | _any_T_42; // @[CSR.scala:1637:{76,90}]
wire _any_T_106 = _any_T_105 | _any_T_43; // @[CSR.scala:1637:{76,90}]
wire _any_T_107 = _any_T_106 | _any_T_44; // @[CSR.scala:1637:{76,90}]
wire _any_T_108 = _any_T_107 | _any_T_45; // @[CSR.scala:1637:{76,90}]
wire _any_T_109 = _any_T_108 | _any_T_46; // @[CSR.scala:1637:{76,90}]
wire _any_T_110 = _any_T_109; // @[CSR.scala:1637:90]
wire _any_T_111 = _any_T_110; // @[CSR.scala:1637:90]
wire _any_T_112 = _any_T_111; // @[CSR.scala:1637:90]
wire _any_T_113 = _any_T_112; // @[CSR.scala:1637:90]
wire _any_T_114 = _any_T_113; // @[CSR.scala:1637:90]
wire _any_T_115 = _any_T_114; // @[CSR.scala:1637:90]
wire _any_T_116 = _any_T_115; // @[CSR.scala:1637:90]
wire _any_T_117 = _any_T_116; // @[CSR.scala:1637:90]
wire _any_T_118 = _any_T_117; // @[CSR.scala:1637:90]
wire _any_T_119 = _any_T_118; // @[CSR.scala:1637:90]
wire _any_T_120 = _any_T_119; // @[CSR.scala:1637:90]
wire _any_T_121 = _any_T_120; // @[CSR.scala:1637:90]
wire _any_T_122 = _any_T_121; // @[CSR.scala:1637:90]
wire _any_T_123 = _any_T_122; // @[CSR.scala:1637:90]
wire _any_T_124 = _any_T_123; // @[CSR.scala:1637:90]
wire anyInterrupt = _any_T_124; // @[CSR.scala:1637:90]
wire [3:0] _which_T_79 = {1'h0, ~_which_T_45, 2'h0}; // @[Mux.scala:50:70]
wire [3:0] _which_T_80 = _which_T_44 ? 4'h8 : _which_T_79; // @[Mux.scala:50:70]
wire [3:0] _which_T_81 = _which_T_43 ? 4'h6 : _which_T_80; // @[Mux.scala:50:70]
wire [3:0] _which_T_82 = _which_T_42 ? 4'h2 : _which_T_81; // @[Mux.scala:50:70]
wire [3:0] _which_T_83 = _which_T_41 ? 4'hA : _which_T_82; // @[Mux.scala:50:70]
wire [3:0] _which_T_84 = _which_T_40 ? 4'h5 : _which_T_83; // @[Mux.scala:50:70]
wire [3:0] _which_T_85 = _which_T_39 ? 4'h1 : _which_T_84; // @[Mux.scala:50:70]
wire [3:0] _which_T_86 = _which_T_38 ? 4'h9 : _which_T_85; // @[Mux.scala:50:70]
wire [3:0] _which_T_87 = _which_T_37 ? 4'h7 : _which_T_86; // @[Mux.scala:50:70]
wire [3:0] _which_T_88 = _which_T_36 ? 4'h3 : _which_T_87; // @[Mux.scala:50:70]
wire [3:0] _which_T_89 = _which_T_35 ? 4'hB : _which_T_88; // @[Mux.scala:50:70]
wire [3:0] _which_T_90 = _which_T_34 ? 4'hC : _which_T_89; // @[Mux.scala:50:70]
wire [3:0] _which_T_91 = _which_T_33 ? 4'hD : _which_T_90; // @[Mux.scala:50:70]
wire [3:0] _which_T_92 = _which_T_32 ? 4'hE : _which_T_91; // @[Mux.scala:50:70]
wire [3:0] _which_T_93 = _which_T_31 ? 4'hF : _which_T_92; // @[Mux.scala:50:70]
wire [3:0] _which_T_94 = _which_T_30 ? 4'h4 : _which_T_93; // @[Mux.scala:50:70]
wire [3:0] _which_T_95 = _which_T_29 ? 4'h0 : _which_T_94; // @[Mux.scala:50:70]
wire [3:0] _which_T_96 = _which_T_28 ? 4'h8 : _which_T_95; // @[Mux.scala:50:70]
wire [3:0] _which_T_97 = _which_T_27 ? 4'h6 : _which_T_96; // @[Mux.scala:50:70]
wire [3:0] _which_T_98 = _which_T_26 ? 4'h2 : _which_T_97; // @[Mux.scala:50:70]
wire [3:0] _which_T_99 = _which_T_25 ? 4'hA : _which_T_98; // @[Mux.scala:50:70]
wire [3:0] _which_T_100 = _which_T_24 ? 4'h5 : _which_T_99; // @[Mux.scala:50:70]
wire [3:0] _which_T_101 = _which_T_23 ? 4'h1 : _which_T_100; // @[Mux.scala:50:70]
wire [3:0] _which_T_102 = _which_T_22 ? 4'h9 : _which_T_101; // @[Mux.scala:50:70]
wire [3:0] _which_T_103 = _which_T_21 ? 4'h7 : _which_T_102; // @[Mux.scala:50:70]
wire [3:0] _which_T_104 = _which_T_20 ? 4'h3 : _which_T_103; // @[Mux.scala:50:70]
wire [3:0] _which_T_105 = _which_T_19 ? 4'hB : _which_T_104; // @[Mux.scala:50:70]
wire [3:0] _which_T_106 = _which_T_18 ? 4'hC : _which_T_105; // @[Mux.scala:50:70]
wire [3:0] _which_T_107 = _which_T_17 ? 4'hD : _which_T_106; // @[Mux.scala:50:70]
wire [3:0] _which_T_108 = _which_T_16 ? 4'hE : _which_T_107; // @[Mux.scala:50:70]
wire [3:0] _which_T_109 = _which_T_15 ? 4'hF : _which_T_108; // @[Mux.scala:50:70]
wire [3:0] _which_T_110 = _which_T_109; // @[Mux.scala:50:70]
wire [3:0] _which_T_111 = _which_T_14 ? 4'h4 : _which_T_110; // @[Mux.scala:50:70]
wire [3:0] _which_T_112 = _which_T_13 ? 4'h0 : _which_T_111; // @[Mux.scala:50:70]
wire [3:0] _which_T_113 = _which_T_12 ? 4'h8 : _which_T_112; // @[Mux.scala:50:70]
wire [3:0] _which_T_114 = _which_T_11 ? 4'h6 : _which_T_113; // @[Mux.scala:50:70]
wire [3:0] _which_T_115 = _which_T_10 ? 4'h2 : _which_T_114; // @[Mux.scala:50:70]
wire [3:0] _which_T_116 = _which_T_9 ? 4'hA : _which_T_115; // @[Mux.scala:50:70]
wire [3:0] _which_T_117 = _which_T_8 ? 4'h5 : _which_T_116; // @[Mux.scala:50:70]
wire [3:0] _which_T_118 = _which_T_7 ? 4'h1 : _which_T_117; // @[Mux.scala:50:70]
wire [3:0] _which_T_119 = _which_T_6 ? 4'h9 : _which_T_118; // @[Mux.scala:50:70]
wire [3:0] _which_T_120 = _which_T_5 ? 4'h7 : _which_T_119; // @[Mux.scala:50:70]
wire [3:0] _which_T_121 = _which_T_4 ? 4'h3 : _which_T_120; // @[Mux.scala:50:70]
wire [3:0] _which_T_122 = _which_T_3 ? 4'hB : _which_T_121; // @[Mux.scala:50:70]
wire [3:0] _which_T_123 = _which_T_2 ? 4'hC : _which_T_122; // @[Mux.scala:50:70]
wire [3:0] _which_T_124 = _which_T_1 ? 4'hD : _which_T_123; // @[Mux.scala:50:70]
wire [3:0] whichInterrupt = _which_T ? 4'hE : _which_T_124; // @[Mux.scala:50:70]
wire [64:0] _interruptCause_T_3 = {61'h0, whichInterrupt} + 65'h8000000000000000; // @[Mux.scala:50:70]
assign interruptCause = _interruptCause_T_3[63:0]; // @[CSR.scala:625:63]
assign io_interrupt_cause_0 = interruptCause; // @[CSR.scala:377:7, :625:63]
wire _io_interrupt_T = ~io_singleStep_0; // @[CSR.scala:377:7, :626:36]
wire _io_interrupt_T_1 = anyInterrupt & _io_interrupt_T; // @[CSR.scala:626:{33,36}, :1637:90]
wire _io_interrupt_T_2 = _io_interrupt_T_1 | reg_singleStepped; // @[CSR.scala:486:30, :626:{33,51}]
wire _io_interrupt_T_3 = reg_debug | io_status_cease_0; // @[CSR.scala:377:7, :482:26, :626:88]
wire _io_interrupt_T_4 = ~_io_interrupt_T_3; // @[CSR.scala:626:{76,88}]
assign _io_interrupt_T_5 = _io_interrupt_T_2 & _io_interrupt_T_4; // @[CSR.scala:626:{51,73,76}]
assign io_interrupt_0 = _io_interrupt_T_5; // @[CSR.scala:377:7, :626:73]
wire _io_fiom_T = reg_mstatus_prv != 2'h3; // @[CSR.scala:395:28, :631:31]
wire _io_fiom_T_1 = _io_fiom_T & reg_menvcfg_fiom; // @[CSR.scala:525:28, :631:{31,41}]
wire _io_fiom_T_3 = _io_fiom_T_2 & reg_senvcfg_fiom; // @[CSR.scala:526:28, :631:{82,92}]
wire _io_fiom_T_4 = _io_fiom_T_1 | _io_fiom_T_3; // @[CSR.scala:631:{41,62,92}]
assign _io_fiom_T_6 = _io_fiom_T_4; // @[CSR.scala:631:{62,113}]
assign io_fiom = _io_fiom_T_6; // @[CSR.scala:377:7, :631:113]
assign io_pmp_0_cfg_l_0 = pmp_cfg_l; // @[PMP.scala:24:19]
assign io_pmp_0_cfg_a_0 = pmp_cfg_a; // @[PMP.scala:24:19]
assign io_pmp_0_cfg_x_0 = pmp_cfg_x; // @[PMP.scala:24:19]
assign io_pmp_0_cfg_w_0 = pmp_cfg_w; // @[PMP.scala:24:19]
assign io_pmp_0_cfg_r_0 = pmp_cfg_r; // @[PMP.scala:24:19]
assign io_pmp_0_addr_0 = pmp_addr; // @[PMP.scala:24:19]
assign io_pmp_0_mask_0 = pmp_mask; // @[PMP.scala:24:19]
wire _pmp_mask_base_T = pmp_cfg_a[0]; // @[PMP.scala:24:19, :57:31]
wire [30:0] _pmp_mask_base_T_1 = {pmp_addr, _pmp_mask_base_T}; // @[PMP.scala:24:19, :57:{19,31}]
wire [30:0] pmp_mask_base = _pmp_mask_base_T_1; // @[PMP.scala:57:{19,36}]
wire [31:0] _pmp_mask_T = {1'h0, pmp_mask_base} + 32'h1; // @[PMP.scala:57:36, :58:23]
wire [30:0] _pmp_mask_T_1 = _pmp_mask_T[30:0]; // @[PMP.scala:58:23]
wire [30:0] _pmp_mask_T_2 = ~_pmp_mask_T_1; // @[PMP.scala:58:{16,23}]
wire [30:0] _pmp_mask_T_3 = pmp_mask_base & _pmp_mask_T_2; // @[PMP.scala:57:36, :58:{14,16}]
wire [32:0] _pmp_mask_T_4 = {_pmp_mask_T_3, 2'h3}; // @[PMP.scala:58:{8,14}]
assign pmp_mask = _pmp_mask_T_4[31:0]; // @[PMP.scala:24:19, :27:14, :58:8]
assign io_pmp_1_cfg_l_0 = pmp_1_cfg_l; // @[PMP.scala:24:19]
assign io_pmp_1_cfg_a_0 = pmp_1_cfg_a; // @[PMP.scala:24:19]
assign io_pmp_1_cfg_x_0 = pmp_1_cfg_x; // @[PMP.scala:24:19]
assign io_pmp_1_cfg_w_0 = pmp_1_cfg_w; // @[PMP.scala:24:19]
assign io_pmp_1_cfg_r_0 = pmp_1_cfg_r; // @[PMP.scala:24:19]
assign io_pmp_1_addr_0 = pmp_1_addr; // @[PMP.scala:24:19]
assign io_pmp_1_mask_0 = pmp_1_mask; // @[PMP.scala:24:19]
wire _pmp_mask_base_T_3 = pmp_1_cfg_a[0]; // @[PMP.scala:24:19, :57:31]
wire [30:0] _pmp_mask_base_T_4 = {pmp_1_addr, _pmp_mask_base_T_3}; // @[PMP.scala:24:19, :57:{19,31}]
wire [30:0] pmp_mask_base_1 = _pmp_mask_base_T_4; // @[PMP.scala:57:{19,36}]
wire [31:0] _pmp_mask_T_5 = {1'h0, pmp_mask_base_1} + 32'h1; // @[PMP.scala:57:36, :58:23]
wire [30:0] _pmp_mask_T_6 = _pmp_mask_T_5[30:0]; // @[PMP.scala:58:23]
wire [30:0] _pmp_mask_T_7 = ~_pmp_mask_T_6; // @[PMP.scala:58:{16,23}]
wire [30:0] _pmp_mask_T_8 = pmp_mask_base_1 & _pmp_mask_T_7; // @[PMP.scala:57:36, :58:{14,16}]
wire [32:0] _pmp_mask_T_9 = {_pmp_mask_T_8, 2'h3}; // @[PMP.scala:58:{8,14}]
assign pmp_1_mask = _pmp_mask_T_9[31:0]; // @[PMP.scala:24:19, :27:14, :58:8]
assign io_pmp_2_cfg_l_0 = pmp_2_cfg_l; // @[PMP.scala:24:19]
assign io_pmp_2_cfg_a_0 = pmp_2_cfg_a; // @[PMP.scala:24:19]
assign io_pmp_2_cfg_x_0 = pmp_2_cfg_x; // @[PMP.scala:24:19]
assign io_pmp_2_cfg_w_0 = pmp_2_cfg_w; // @[PMP.scala:24:19]
assign io_pmp_2_cfg_r_0 = pmp_2_cfg_r; // @[PMP.scala:24:19]
assign io_pmp_2_addr_0 = pmp_2_addr; // @[PMP.scala:24:19]
assign io_pmp_2_mask_0 = pmp_2_mask; // @[PMP.scala:24:19]
wire _pmp_mask_base_T_6 = pmp_2_cfg_a[0]; // @[PMP.scala:24:19, :57:31]
wire [30:0] _pmp_mask_base_T_7 = {pmp_2_addr, _pmp_mask_base_T_6}; // @[PMP.scala:24:19, :57:{19,31}]
wire [30:0] pmp_mask_base_2 = _pmp_mask_base_T_7; // @[PMP.scala:57:{19,36}]
wire [31:0] _pmp_mask_T_10 = {1'h0, pmp_mask_base_2} + 32'h1; // @[PMP.scala:57:36, :58:23]
wire [30:0] _pmp_mask_T_11 = _pmp_mask_T_10[30:0]; // @[PMP.scala:58:23]
wire [30:0] _pmp_mask_T_12 = ~_pmp_mask_T_11; // @[PMP.scala:58:{16,23}]
wire [30:0] _pmp_mask_T_13 = pmp_mask_base_2 & _pmp_mask_T_12; // @[PMP.scala:57:36, :58:{14,16}]
wire [32:0] _pmp_mask_T_14 = {_pmp_mask_T_13, 2'h3}; // @[PMP.scala:58:{8,14}]
assign pmp_2_mask = _pmp_mask_T_14[31:0]; // @[PMP.scala:24:19, :27:14, :58:8]
assign io_pmp_3_cfg_l_0 = pmp_3_cfg_l; // @[PMP.scala:24:19]
assign io_pmp_3_cfg_a_0 = pmp_3_cfg_a; // @[PMP.scala:24:19]
assign io_pmp_3_cfg_x_0 = pmp_3_cfg_x; // @[PMP.scala:24:19]
assign io_pmp_3_cfg_w_0 = pmp_3_cfg_w; // @[PMP.scala:24:19]
assign io_pmp_3_cfg_r_0 = pmp_3_cfg_r; // @[PMP.scala:24:19]
assign io_pmp_3_addr_0 = pmp_3_addr; // @[PMP.scala:24:19]
assign io_pmp_3_mask_0 = pmp_3_mask; // @[PMP.scala:24:19]
wire _pmp_mask_base_T_9 = pmp_3_cfg_a[0]; // @[PMP.scala:24:19, :57:31]
wire [30:0] _pmp_mask_base_T_10 = {pmp_3_addr, _pmp_mask_base_T_9}; // @[PMP.scala:24:19, :57:{19,31}]
wire [30:0] pmp_mask_base_3 = _pmp_mask_base_T_10; // @[PMP.scala:57:{19,36}]
wire [31:0] _pmp_mask_T_15 = {1'h0, pmp_mask_base_3} + 32'h1; // @[PMP.scala:57:36, :58:23]
wire [30:0] _pmp_mask_T_16 = _pmp_mask_T_15[30:0]; // @[PMP.scala:58:23]
wire [30:0] _pmp_mask_T_17 = ~_pmp_mask_T_16; // @[PMP.scala:58:{16,23}]
wire [30:0] _pmp_mask_T_18 = pmp_mask_base_3 & _pmp_mask_T_17; // @[PMP.scala:57:36, :58:{14,16}]
wire [32:0] _pmp_mask_T_19 = {_pmp_mask_T_18, 2'h3}; // @[PMP.scala:58:{8,14}]
assign pmp_3_mask = _pmp_mask_T_19[31:0]; // @[PMP.scala:24:19, :27:14, :58:8]
assign io_pmp_4_cfg_l_0 = pmp_4_cfg_l; // @[PMP.scala:24:19]
assign io_pmp_4_cfg_a_0 = pmp_4_cfg_a; // @[PMP.scala:24:19]
assign io_pmp_4_cfg_x_0 = pmp_4_cfg_x; // @[PMP.scala:24:19]
assign io_pmp_4_cfg_w_0 = pmp_4_cfg_w; // @[PMP.scala:24:19]
assign io_pmp_4_cfg_r_0 = pmp_4_cfg_r; // @[PMP.scala:24:19]
assign io_pmp_4_addr_0 = pmp_4_addr; // @[PMP.scala:24:19]
assign io_pmp_4_mask_0 = pmp_4_mask; // @[PMP.scala:24:19]
wire _pmp_mask_base_T_12 = pmp_4_cfg_a[0]; // @[PMP.scala:24:19, :57:31]
wire [30:0] _pmp_mask_base_T_13 = {pmp_4_addr, _pmp_mask_base_T_12}; // @[PMP.scala:24:19, :57:{19,31}]
wire [30:0] pmp_mask_base_4 = _pmp_mask_base_T_13; // @[PMP.scala:57:{19,36}]
wire [31:0] _pmp_mask_T_20 = {1'h0, pmp_mask_base_4} + 32'h1; // @[PMP.scala:57:36, :58:23]
wire [30:0] _pmp_mask_T_21 = _pmp_mask_T_20[30:0]; // @[PMP.scala:58:23]
wire [30:0] _pmp_mask_T_22 = ~_pmp_mask_T_21; // @[PMP.scala:58:{16,23}]
wire [30:0] _pmp_mask_T_23 = pmp_mask_base_4 & _pmp_mask_T_22; // @[PMP.scala:57:36, :58:{14,16}]
wire [32:0] _pmp_mask_T_24 = {_pmp_mask_T_23, 2'h3}; // @[PMP.scala:58:{8,14}]
assign pmp_4_mask = _pmp_mask_T_24[31:0]; // @[PMP.scala:24:19, :27:14, :58:8]
assign io_pmp_5_cfg_l_0 = pmp_5_cfg_l; // @[PMP.scala:24:19]
assign io_pmp_5_cfg_a_0 = pmp_5_cfg_a; // @[PMP.scala:24:19]
assign io_pmp_5_cfg_x_0 = pmp_5_cfg_x; // @[PMP.scala:24:19]
assign io_pmp_5_cfg_w_0 = pmp_5_cfg_w; // @[PMP.scala:24:19]
assign io_pmp_5_cfg_r_0 = pmp_5_cfg_r; // @[PMP.scala:24:19]
assign io_pmp_5_addr_0 = pmp_5_addr; // @[PMP.scala:24:19]
assign io_pmp_5_mask_0 = pmp_5_mask; // @[PMP.scala:24:19]
wire _pmp_mask_base_T_15 = pmp_5_cfg_a[0]; // @[PMP.scala:24:19, :57:31]
wire [30:0] _pmp_mask_base_T_16 = {pmp_5_addr, _pmp_mask_base_T_15}; // @[PMP.scala:24:19, :57:{19,31}]
wire [30:0] pmp_mask_base_5 = _pmp_mask_base_T_16; // @[PMP.scala:57:{19,36}]
wire [31:0] _pmp_mask_T_25 = {1'h0, pmp_mask_base_5} + 32'h1; // @[PMP.scala:57:36, :58:23]
wire [30:0] _pmp_mask_T_26 = _pmp_mask_T_25[30:0]; // @[PMP.scala:58:23]
wire [30:0] _pmp_mask_T_27 = ~_pmp_mask_T_26; // @[PMP.scala:58:{16,23}]
wire [30:0] _pmp_mask_T_28 = pmp_mask_base_5 & _pmp_mask_T_27; // @[PMP.scala:57:36, :58:{14,16}]
wire [32:0] _pmp_mask_T_29 = {_pmp_mask_T_28, 2'h3}; // @[PMP.scala:58:{8,14}]
assign pmp_5_mask = _pmp_mask_T_29[31:0]; // @[PMP.scala:24:19, :27:14, :58:8]
assign io_pmp_6_cfg_l_0 = pmp_6_cfg_l; // @[PMP.scala:24:19]
assign io_pmp_6_cfg_a_0 = pmp_6_cfg_a; // @[PMP.scala:24:19]
assign io_pmp_6_cfg_x_0 = pmp_6_cfg_x; // @[PMP.scala:24:19]
assign io_pmp_6_cfg_w_0 = pmp_6_cfg_w; // @[PMP.scala:24:19]
assign io_pmp_6_cfg_r_0 = pmp_6_cfg_r; // @[PMP.scala:24:19]
assign io_pmp_6_addr_0 = pmp_6_addr; // @[PMP.scala:24:19]
assign io_pmp_6_mask_0 = pmp_6_mask; // @[PMP.scala:24:19]
wire _pmp_mask_base_T_18 = pmp_6_cfg_a[0]; // @[PMP.scala:24:19, :57:31]
wire [30:0] _pmp_mask_base_T_19 = {pmp_6_addr, _pmp_mask_base_T_18}; // @[PMP.scala:24:19, :57:{19,31}]
wire [30:0] pmp_mask_base_6 = _pmp_mask_base_T_19; // @[PMP.scala:57:{19,36}]
wire [31:0] _pmp_mask_T_30 = {1'h0, pmp_mask_base_6} + 32'h1; // @[PMP.scala:57:36, :58:23]
wire [30:0] _pmp_mask_T_31 = _pmp_mask_T_30[30:0]; // @[PMP.scala:58:23]
wire [30:0] _pmp_mask_T_32 = ~_pmp_mask_T_31; // @[PMP.scala:58:{16,23}]
wire [30:0] _pmp_mask_T_33 = pmp_mask_base_6 & _pmp_mask_T_32; // @[PMP.scala:57:36, :58:{14,16}]
wire [32:0] _pmp_mask_T_34 = {_pmp_mask_T_33, 2'h3}; // @[PMP.scala:58:{8,14}]
assign pmp_6_mask = _pmp_mask_T_34[31:0]; // @[PMP.scala:24:19, :27:14, :58:8]
assign io_pmp_7_cfg_l_0 = pmp_7_cfg_l; // @[PMP.scala:24:19]
assign io_pmp_7_cfg_a_0 = pmp_7_cfg_a; // @[PMP.scala:24:19]
assign io_pmp_7_cfg_x_0 = pmp_7_cfg_x; // @[PMP.scala:24:19]
assign io_pmp_7_cfg_w_0 = pmp_7_cfg_w; // @[PMP.scala:24:19]
assign io_pmp_7_cfg_r_0 = pmp_7_cfg_r; // @[PMP.scala:24:19]
assign io_pmp_7_addr_0 = pmp_7_addr; // @[PMP.scala:24:19]
assign io_pmp_7_mask_0 = pmp_7_mask; // @[PMP.scala:24:19]
wire _pmp_mask_base_T_21 = pmp_7_cfg_a[0]; // @[PMP.scala:24:19, :57:31]
wire [30:0] _pmp_mask_base_T_22 = {pmp_7_addr, _pmp_mask_base_T_21}; // @[PMP.scala:24:19, :57:{19,31}]
wire [30:0] pmp_mask_base_7 = _pmp_mask_base_T_22; // @[PMP.scala:57:{19,36}]
wire [31:0] _pmp_mask_T_35 = {1'h0, pmp_mask_base_7} + 32'h1; // @[PMP.scala:57:36, :58:23]
wire [30:0] _pmp_mask_T_36 = _pmp_mask_T_35[30:0]; // @[PMP.scala:58:23]
wire [30:0] _pmp_mask_T_37 = ~_pmp_mask_T_36; // @[PMP.scala:58:{16,23}]
wire [30:0] _pmp_mask_T_38 = pmp_mask_base_7 & _pmp_mask_T_37; // @[PMP.scala:57:36, :58:{14,16}]
wire [32:0] _pmp_mask_T_39 = {_pmp_mask_T_38, 2'h3}; // @[PMP.scala:58:{8,14}]
assign pmp_7_mask = _pmp_mask_T_39[31:0]; // @[PMP.scala:24:19, :27:14, :58:8]
reg [63:0] reg_misa; // @[CSR.scala:648:25]
wire [1:0] read_mstatus_lo_lo_lo_lo = {io_status_sie_0, 1'h0}; // @[CSR.scala:377:7, :649:32]
wire [1:0] read_mstatus_lo_lo_lo_hi = {io_status_mie_0, 1'h0}; // @[CSR.scala:377:7, :649:32]
wire [3:0] read_mstatus_lo_lo_lo = {read_mstatus_lo_lo_lo_hi, read_mstatus_lo_lo_lo_lo}; // @[CSR.scala:649:32]
wire [1:0] read_mstatus_lo_lo_hi_lo = {io_status_spie_0, 1'h0}; // @[CSR.scala:377:7, :649:32]
wire [1:0] read_mstatus_lo_lo_hi_hi_hi = {io_status_spp_0, io_status_mpie_0}; // @[CSR.scala:377:7, :649:32]
wire [2:0] read_mstatus_lo_lo_hi_hi = {read_mstatus_lo_lo_hi_hi_hi, 1'h0}; // @[CSR.scala:649:32]
wire [4:0] read_mstatus_lo_lo_hi = {read_mstatus_lo_lo_hi_hi, read_mstatus_lo_lo_hi_lo}; // @[CSR.scala:649:32]
wire [8:0] read_mstatus_lo_lo = {read_mstatus_lo_lo_hi, read_mstatus_lo_lo_lo}; // @[CSR.scala:649:32]
wire [3:0] read_mstatus_lo_hi_lo_lo = {io_status_mpp_0, 2'h0}; // @[CSR.scala:377:7, :649:32]
wire [3:0] read_mstatus_lo_hi_lo_hi = {2'h0, io_status_fs_0}; // @[CSR.scala:377:7, :649:32]
wire [7:0] read_mstatus_lo_hi_lo = {read_mstatus_lo_hi_lo_hi, read_mstatus_lo_hi_lo_lo}; // @[CSR.scala:649:32]
wire [1:0] read_mstatus_lo_hi_hi_lo = {io_status_sum_0, io_status_mprv_0}; // @[CSR.scala:377:7, :649:32]
wire [1:0] read_mstatus_lo_hi_hi_hi_hi = {io_status_tw_0, io_status_tvm_0}; // @[CSR.scala:377:7, :649:32]
wire [2:0] read_mstatus_lo_hi_hi_hi = {read_mstatus_lo_hi_hi_hi_hi, io_status_mxr_0}; // @[CSR.scala:377:7, :649:32]
wire [4:0] read_mstatus_lo_hi_hi = {read_mstatus_lo_hi_hi_hi, read_mstatus_lo_hi_hi_lo}; // @[CSR.scala:649:32]
wire [12:0] read_mstatus_lo_hi = {read_mstatus_lo_hi_hi, read_mstatus_lo_hi_lo}; // @[CSR.scala:649:32]
wire [21:0] read_mstatus_lo = {read_mstatus_lo_hi, read_mstatus_lo_lo}; // @[CSR.scala:649:32]
wire [8:0] read_mstatus_hi_lo_lo_lo = {8'h0, io_status_tsr_0}; // @[CSR.scala:377:7, :649:32]
wire [11:0] read_mstatus_hi_lo_lo = {3'h4, read_mstatus_hi_lo_lo_lo}; // @[CSR.scala:649:32]
wire [1:0] read_mstatus_hi_lo_hi_hi_hi = {io_status_mpv_0, io_status_gva_0}; // @[CSR.scala:377:7, :649:32]
wire [2:0] read_mstatus_hi_lo_hi_hi = {read_mstatus_hi_lo_hi_hi_hi, 1'h0}; // @[CSR.scala:649:32]
wire [5:0] read_mstatus_hi_lo_hi = {read_mstatus_hi_lo_hi_hi, 3'h2}; // @[CSR.scala:649:32]
wire [17:0] read_mstatus_hi_lo = {read_mstatus_hi_lo_hi, read_mstatus_hi_lo_lo}; // @[CSR.scala:649:32]
wire [23:0] read_mstatus_hi_hi_lo_lo = {io_status_sd_0, 23'h0}; // @[CSR.scala:377:7, :649:32]
wire [2:0] read_mstatus_hi_hi_lo_hi_hi = {io_status_dv_0, io_status_prv_0}; // @[CSR.scala:377:7, :649:32]
wire [3:0] read_mstatus_hi_hi_lo_hi = {read_mstatus_hi_hi_lo_hi_hi, io_status_v_0}; // @[CSR.scala:377:7, :649:32]
wire [27:0] read_mstatus_hi_hi_lo = {read_mstatus_hi_hi_lo_hi, read_mstatus_hi_hi_lo_lo}; // @[CSR.scala:649:32]
wire [33:0] read_mstatus_hi_hi_hi_lo = {io_status_isa_0, io_status_dprv_0}; // @[CSR.scala:377:7, :649:32]
wire [1:0] read_mstatus_hi_hi_hi_hi_hi = {io_status_debug_0, io_status_cease_0}; // @[CSR.scala:377:7, :649:32]
wire [2:0] read_mstatus_hi_hi_hi_hi = {read_mstatus_hi_hi_hi_hi_hi, io_status_wfi_0}; // @[CSR.scala:377:7, :649:32]
wire [36:0] read_mstatus_hi_hi_hi = {read_mstatus_hi_hi_hi_hi, read_mstatus_hi_hi_hi_lo}; // @[CSR.scala:649:32]
wire [64:0] read_mstatus_hi_hi = {read_mstatus_hi_hi_hi, read_mstatus_hi_hi_lo}; // @[CSR.scala:649:32]
wire [82:0] read_mstatus_hi = {read_mstatus_hi_hi, read_mstatus_hi_lo}; // @[CSR.scala:649:32]
wire [104:0] _read_mstatus_T = {read_mstatus_hi, read_mstatus_lo}; // @[CSR.scala:649:32]
wire [63:0] read_mstatus = _read_mstatus_T[63:0]; // @[package.scala:163:13]
wire _read_mtvec_T = reg_mtvec[0]; // @[CSR.scala:512:31, :1666:41]
wire [7:0] _read_mtvec_T_1 = _read_mtvec_T ? 8'hFE : 8'h2; // @[CSR.scala:1666:{39,41}]
wire [31:0] _read_mtvec_T_3 = {24'h0, _read_mtvec_T_1}; // @[package.scala:174:41]
wire [31:0] _read_mtvec_T_4 = ~_read_mtvec_T_3; // @[package.scala:174:{37,41}]
wire [31:0] _read_mtvec_T_5 = reg_mtvec & _read_mtvec_T_4; // @[package.scala:174:{35,37}]
wire [63:0] read_mtvec = {32'h0, _read_mtvec_T_5}; // @[package.scala:138:15, :174:35]
wire _read_stvec_T = reg_stvec[0]; // @[CSR.scala:573:22, :1666:41]
wire [7:0] _read_stvec_T_1 = _read_stvec_T ? 8'hFE : 8'h2; // @[CSR.scala:1666:{39,41}]
wire [38:0] _read_stvec_T_3 = {31'h0, _read_stvec_T_1}; // @[package.scala:174:41]
wire [38:0] _read_stvec_T_4 = ~_read_stvec_T_3; // @[package.scala:174:{37,41}]
wire [38:0] _read_stvec_T_5 = reg_stvec & _read_stvec_T_4; // @[package.scala:174:{35,37}]
wire _read_stvec_T_6 = _read_stvec_T_5[38]; // @[package.scala:132:38, :174:35]
wire [24:0] _read_stvec_T_7 = {25{_read_stvec_T_6}}; // @[package.scala:132:{20,38}]
wire [63:0] read_stvec = {_read_stvec_T_7, _read_stvec_T_5}; // @[package.scala:132:{15,20}, :174:35]
wire [1:0] _GEN_4 = {reg_bp_0_control_x, reg_bp_0_control_w}; // @[CSR.scala:492:19, :655:48]
wire [1:0] read_mapping_lo_lo_hi; // @[CSR.scala:655:48]
assign read_mapping_lo_lo_hi = _GEN_4; // @[CSR.scala:655:48]
wire [1:0] newBPC_lo_lo_hi; // @[CSR.scala:1477:67]
assign newBPC_lo_lo_hi = _GEN_4; // @[CSR.scala:655:48, :1477:67]
wire [2:0] read_mapping_lo_lo = {read_mapping_lo_lo_hi, reg_bp_0_control_r}; // @[CSR.scala:492:19, :655:48]
wire [1:0] _GEN_5 = {reg_bp_0_control_s, reg_bp_0_control_u}; // @[CSR.scala:492:19, :655:48]
wire [1:0] read_mapping_lo_hi_lo; // @[CSR.scala:655:48]
assign read_mapping_lo_hi_lo = _GEN_5; // @[CSR.scala:655:48]
wire [1:0] newBPC_lo_hi_lo; // @[CSR.scala:1477:67]
assign newBPC_lo_hi_lo = _GEN_5; // @[CSR.scala:655:48, :1477:67]
wire [1:0] _GEN_6 = {reg_bp_0_control_m, 1'h0}; // @[CSR.scala:492:19, :655:48]
wire [1:0] read_mapping_lo_hi_hi; // @[CSR.scala:655:48]
assign read_mapping_lo_hi_hi = _GEN_6; // @[CSR.scala:655:48]
wire [1:0] newBPC_lo_hi_hi; // @[CSR.scala:1477:67]
assign newBPC_lo_hi_hi = _GEN_6; // @[CSR.scala:655:48, :1477:67]
wire [3:0] read_mapping_lo_hi = {read_mapping_lo_hi_hi, read_mapping_lo_hi_lo}; // @[CSR.scala:655:48]
wire [6:0] read_mapping_lo = {read_mapping_lo_hi, read_mapping_lo_lo}; // @[CSR.scala:655:48]
wire [3:0] _GEN_7 = {2'h0, reg_bp_0_control_tmatch}; // @[CSR.scala:492:19, :655:48]
wire [3:0] read_mapping_hi_lo_lo; // @[CSR.scala:655:48]
assign read_mapping_hi_lo_lo = _GEN_7; // @[CSR.scala:655:48]
wire [3:0] newBPC_hi_lo_lo; // @[CSR.scala:1477:67]
assign newBPC_hi_lo_lo = _GEN_7; // @[CSR.scala:655:48, :1477:67]
wire [1:0] _GEN_8 = {reg_bp_0_control_action, 1'h0}; // @[CSR.scala:492:19, :655:48]
wire [1:0] read_mapping_hi_lo_hi; // @[CSR.scala:655:48]
assign read_mapping_hi_lo_hi = _GEN_8; // @[CSR.scala:655:48]
wire [1:0] newBPC_hi_lo_hi; // @[CSR.scala:1477:67]
assign newBPC_hi_lo_hi = _GEN_8; // @[CSR.scala:655:48, :1477:67]
wire [5:0] read_mapping_hi_lo = {read_mapping_hi_lo_hi, read_mapping_hi_lo_lo}; // @[CSR.scala:655:48]
wire [4:0] _GEN_9 = {4'h2, reg_bp_0_control_dmode}; // @[CSR.scala:492:19, :655:48]
wire [4:0] read_mapping_hi_hi_hi; // @[CSR.scala:655:48]
assign read_mapping_hi_hi_hi = _GEN_9; // @[CSR.scala:655:48]
wire [4:0] newBPC_hi_hi_hi; // @[CSR.scala:1477:67]
assign newBPC_hi_hi_hi = _GEN_9; // @[CSR.scala:655:48, :1477:67]
wire [50:0] read_mapping_hi_hi = {read_mapping_hi_hi_hi, 46'h40000000000}; // @[CSR.scala:655:48]
wire [56:0] read_mapping_hi = {read_mapping_hi_hi, read_mapping_hi_lo}; // @[CSR.scala:655:48]
wire [63:0] read_mapping_1_2 = {read_mapping_hi, read_mapping_lo}; // @[CSR.scala:655:48]
wire _read_mapping_T = reg_bp_0_address[38]; // @[package.scala:132:38]
wire [24:0] _read_mapping_T_1 = {25{_read_mapping_T}}; // @[package.scala:132:{20,38}]
wire [63:0] read_mapping_2_2 = {_read_mapping_T_1, reg_bp_0_address}; // @[package.scala:132:{15,20}]
wire [1:0] read_mapping_lo_1 = {read_mapping_lo_hi_1, 1'h0}; // @[CSR.scala:657:47]
wire [50:0] read_mapping_3_2 = {read_mapping_hi_1, read_mapping_lo_1}; // @[CSR.scala:657:47]
wire [39:0] _read_mapping_T_2 = ~reg_mepc; // @[CSR.scala:505:21, :1665:28]
wire _read_mapping_T_3 = reg_misa[2]; // @[CSR.scala:648:25, :1665:45]
wire _debug_csrs_T_1 = reg_misa[2]; // @[CSR.scala:648:25, :1665:45]
wire _io_evec_T_1 = reg_misa[2]; // @[CSR.scala:648:25, :1665:45]
wire _io_evec_T_6 = reg_misa[2]; // @[CSR.scala:648:25, :1665:45]
wire _io_evec_T_11 = reg_misa[2]; // @[CSR.scala:648:25, :1665:45]
wire _io_evec_T_16 = reg_misa[2]; // @[CSR.scala:648:25, :1665:45]
wire _io_evec_T_21 = reg_misa[2]; // @[CSR.scala:648:25, :1665:45]
wire [1:0] _read_mapping_T_4 = {~_read_mapping_T_3, 1'h1}; // @[CSR.scala:1665:{36,45}]
wire [39:0] _read_mapping_T_5 = {_read_mapping_T_2[39:2], _read_mapping_T_2[1:0] | _read_mapping_T_4}; // @[CSR.scala:1665:{28,31,36}]
wire [39:0] _read_mapping_T_6 = ~_read_mapping_T_5; // @[CSR.scala:1665:{26,31}]
wire _read_mapping_T_7 = _read_mapping_T_6[39]; // @[package.scala:132:38]
wire [23:0] _read_mapping_T_8 = {24{_read_mapping_T_7}}; // @[package.scala:132:{20,38}]
wire [63:0] read_mapping_10_2 = {_read_mapping_T_8, _read_mapping_T_6}; // @[package.scala:132:{15,20}]
wire _read_mapping_T_9 = reg_mtval[39]; // @[package.scala:132:38]
wire [23:0] _read_mapping_T_10 = {24{_read_mapping_T_9}}; // @[package.scala:132:{20,38}]
wire [63:0] read_mapping_11_2 = {_read_mapping_T_10, reg_mtval}; // @[package.scala:132:{15,20}]
wire [2:0] debug_csrs_lo_lo_hi = {2'h0, reg_dcsr_step}; // @[CSR.scala:403:25, :670:27]
wire [4:0] debug_csrs_lo_lo = {debug_csrs_lo_lo_hi, reg_dcsr_prv}; // @[CSR.scala:403:25, :670:27]
wire [3:0] debug_csrs_lo_hi_lo = {reg_dcsr_cause, reg_dcsr_v}; // @[CSR.scala:403:25, :670:27]
wire [5:0] debug_csrs_lo_hi = {2'h0, debug_csrs_lo_hi_lo}; // @[CSR.scala:670:27]
wire [10:0] debug_csrs_lo = {debug_csrs_lo_hi, debug_csrs_lo_lo}; // @[CSR.scala:670:27]
wire [1:0] debug_csrs_hi_lo_lo = {reg_dcsr_ebreaku, 1'h0}; // @[CSR.scala:403:25, :670:27]
wire [1:0] debug_csrs_hi_lo_hi = {1'h0, reg_dcsr_ebreaks}; // @[CSR.scala:403:25, :670:27]
wire [3:0] debug_csrs_hi_lo = {debug_csrs_hi_lo_hi, debug_csrs_hi_lo_lo}; // @[CSR.scala:670:27]
wire [12:0] debug_csrs_hi_hi_lo = {12'h0, reg_dcsr_ebreakm}; // @[CSR.scala:403:25, :670:27]
wire [16:0] debug_csrs_hi_hi = {4'h4, debug_csrs_hi_hi_lo}; // @[CSR.scala:670:27]
wire [20:0] debug_csrs_hi = {debug_csrs_hi_hi, debug_csrs_hi_lo}; // @[CSR.scala:670:27]
wire [31:0] debug_csrs_0_2 = {debug_csrs_hi, debug_csrs_lo}; // @[CSR.scala:670:27]
wire [39:0] _debug_csrs_T = ~reg_dpc; // @[CSR.scala:483:20, :1665:28]
wire [1:0] _debug_csrs_T_2 = {~_debug_csrs_T_1, 1'h1}; // @[CSR.scala:1665:{36,45}]
wire [39:0] _debug_csrs_T_3 = {_debug_csrs_T[39:2], _debug_csrs_T[1:0] | _debug_csrs_T_2}; // @[CSR.scala:1665:{28,31,36}]
wire [39:0] _debug_csrs_T_4 = ~_debug_csrs_T_3; // @[CSR.scala:1665:{26,31}]
wire _debug_csrs_T_5 = _debug_csrs_T_4[39]; // @[package.scala:132:38]
wire [23:0] _debug_csrs_T_6 = {24{_debug_csrs_T_5}}; // @[package.scala:132:{20,38}]
wire [63:0] debug_csrs_1_2 = {_debug_csrs_T_6, _debug_csrs_T_4}; // @[package.scala:132:{15,20}]
wire [7:0] read_fcsr = {reg_frm, reg_fflags}; // @[CSR.scala:577:23, :578:20, :689:22]
wire [3:0] lo_lo_4 = {3'h0, reg_menvcfg_fiom}; // @[CSR.scala:525:28, :742:49]
wire [6:0] lo_4 = {3'h0, lo_lo_4}; // @[CSR.scala:742:49]
wire [63:0] sie_mask = {48'h0, read_mideleg[15:0] & 16'hEFFF}; // @[CSR.scala:498:14, :750:18]
wire [63:0] read_sie = reg_mie & sie_mask; // @[CSR.scala:495:20, :750:18, :753:28]
wire [63:0] read_sip = {48'h0, sie_mask[15:0] & read_mip}; // @[CSR.scala:610:29, :750:18, :754:29]
wire [1:0] lo_lo_lo_lo = {read_sstatus_sie, 1'h0}; // @[CSR.scala:755:35, :768:51]
wire [3:0] lo_lo_lo_4 = {2'h0, lo_lo_lo_lo}; // @[CSR.scala:768:51]
wire [1:0] lo_lo_hi_lo = {read_sstatus_spie, 1'h0}; // @[CSR.scala:755:35, :768:51]
wire [1:0] lo_lo_hi_hi_hi = {read_sstatus_spp, 1'h0}; // @[CSR.scala:755:35, :768:51]
wire [2:0] lo_lo_hi_hi = {lo_lo_hi_hi_hi, 1'h0}; // @[CSR.scala:768:51]
wire [4:0] lo_lo_hi_4 = {lo_lo_hi_hi, lo_lo_hi_lo}; // @[CSR.scala:768:51]
wire [8:0] lo_lo_5 = {lo_lo_hi_4, lo_lo_lo_4}; // @[CSR.scala:768:51]
wire [3:0] lo_hi_lo_hi = {2'h0, read_sstatus_fs}; // @[CSR.scala:755:35, :768:51]
wire [7:0] lo_hi_lo_4 = {lo_hi_lo_hi, 4'h0}; // @[CSR.scala:768:51]
wire [1:0] lo_hi_hi_lo = {read_sstatus_sum, 1'h0}; // @[CSR.scala:755:35, :768:51]
wire [2:0] lo_hi_hi_hi = {2'h0, read_sstatus_mxr}; // @[CSR.scala:755:35, :768:51]
wire [4:0] lo_hi_hi_4 = {lo_hi_hi_hi, lo_hi_hi_lo}; // @[CSR.scala:768:51]
wire [12:0] lo_hi_5 = {lo_hi_hi_4, lo_hi_lo_4}; // @[CSR.scala:768:51]
wire [21:0] lo_5 = {lo_hi_5, lo_lo_5}; // @[CSR.scala:768:51]
wire [23:0] hi_hi_lo_lo = {read_sstatus_sd, 23'h0}; // @[CSR.scala:755:35, :768:51]
wire [27:0] hi_hi_lo_4 = {4'h0, hi_hi_lo_lo}; // @[CSR.scala:768:51]
wire [64:0] hi_hi_5 = {37'h0, hi_hi_lo_4}; // @[CSR.scala:768:51]
wire [82:0] hi_7 = {hi_hi_5, 18'h800}; // @[CSR.scala:768:51]
wire [19:0] hi_8 = {reg_satp_mode, 16'h0}; // @[CSR.scala:574:21, :774:43]
wire [39:0] _io_evec_T = ~reg_sepc; // @[CSR.scala:569:21, :1665:28]
wire [39:0] _T_30 = ~{_io_evec_T[39:2], _io_evec_T[1:0] | {~(reg_misa[2]), 1'h1}}; // @[CSR.scala:648:25, :1665:{26,28,31,36,45}]
wire [3:0] lo_lo_6 = {3'h0, reg_senvcfg_fiom}; // @[CSR.scala:526:28, :780:49]
wire [6:0] lo_6 = {3'h0, lo_lo_6}; // @[CSR.scala:780:49]
wire [1:0] lo_hi_7 = {reg_pmp_0_cfg_x, reg_pmp_0_cfg_w}; // @[package.scala:45:36]
wire [2:0] lo_7 = {lo_hi_7, reg_pmp_0_cfg_r}; // @[package.scala:45:36]
wire [2:0] hi_hi_7 = {reg_pmp_0_cfg_l, 2'h0}; // @[package.scala:45:36]
wire [4:0] hi_10 = {hi_hi_7, reg_pmp_0_cfg_a}; // @[package.scala:45:36]
wire [1:0] lo_hi_8 = {reg_pmp_1_cfg_x, reg_pmp_1_cfg_w}; // @[package.scala:45:36]
wire [2:0] lo_8 = {lo_hi_8, reg_pmp_1_cfg_r}; // @[package.scala:45:36]
wire [2:0] hi_hi_8 = {reg_pmp_1_cfg_l, 2'h0}; // @[package.scala:45:36]
wire [4:0] hi_11 = {hi_hi_8, reg_pmp_1_cfg_a}; // @[package.scala:45:36]
wire [1:0] lo_hi_9 = {reg_pmp_2_cfg_x, reg_pmp_2_cfg_w}; // @[package.scala:45:36]
wire [2:0] lo_9 = {lo_hi_9, reg_pmp_2_cfg_r}; // @[package.scala:45:36]
wire [2:0] hi_hi_9 = {reg_pmp_2_cfg_l, 2'h0}; // @[package.scala:45:36]
wire [4:0] hi_12 = {hi_hi_9, reg_pmp_2_cfg_a}; // @[package.scala:45:36]
wire [1:0] lo_hi_10 = {reg_pmp_3_cfg_x, reg_pmp_3_cfg_w}; // @[package.scala:45:36]
wire [2:0] lo_10 = {lo_hi_10, reg_pmp_3_cfg_r}; // @[package.scala:45:36]
wire [2:0] hi_hi_10 = {reg_pmp_3_cfg_l, 2'h0}; // @[package.scala:45:36]
wire [4:0] hi_13 = {hi_hi_10, reg_pmp_3_cfg_a}; // @[package.scala:45:36]
wire [1:0] lo_hi_11 = {reg_pmp_4_cfg_x, reg_pmp_4_cfg_w}; // @[package.scala:45:36]
wire [2:0] lo_11 = {lo_hi_11, reg_pmp_4_cfg_r}; // @[package.scala:45:36]
wire [2:0] hi_hi_11 = {reg_pmp_4_cfg_l, 2'h0}; // @[package.scala:45:36]
wire [4:0] hi_14 = {hi_hi_11, reg_pmp_4_cfg_a}; // @[package.scala:45:36]
wire [1:0] lo_hi_12 = {reg_pmp_5_cfg_x, reg_pmp_5_cfg_w}; // @[package.scala:45:36]
wire [2:0] lo_12 = {lo_hi_12, reg_pmp_5_cfg_r}; // @[package.scala:45:36]
wire [2:0] hi_hi_12 = {reg_pmp_5_cfg_l, 2'h0}; // @[package.scala:45:36]
wire [4:0] hi_15 = {hi_hi_12, reg_pmp_5_cfg_a}; // @[package.scala:45:36]
wire [1:0] lo_hi_13 = {reg_pmp_6_cfg_x, reg_pmp_6_cfg_w}; // @[package.scala:45:36]
wire [2:0] lo_13 = {lo_hi_13, reg_pmp_6_cfg_r}; // @[package.scala:45:36]
wire [2:0] hi_hi_13 = {reg_pmp_6_cfg_l, 2'h0}; // @[package.scala:45:36]
wire [4:0] hi_16 = {hi_hi_13, reg_pmp_6_cfg_a}; // @[package.scala:45:36]
wire [1:0] lo_hi_14 = {reg_pmp_7_cfg_x, reg_pmp_7_cfg_w}; // @[package.scala:45:36]
wire [2:0] lo_14 = {lo_hi_14, reg_pmp_7_cfg_r}; // @[package.scala:45:36]
wire [2:0] hi_hi_14 = {reg_pmp_7_cfg_l, 2'h0}; // @[package.scala:45:36]
wire [4:0] hi_17 = {hi_hi_14, reg_pmp_7_cfg_a}; // @[package.scala:45:36]
wire [15:0] lo_lo_7 = {hi_11, lo_8, hi_10, lo_7}; // @[package.scala:45:{27,36}]
wire [15:0] lo_hi_15 = {hi_13, lo_10, hi_12, lo_9}; // @[package.scala:45:{27,36}]
wire [31:0] lo_15 = {lo_hi_15, lo_lo_7}; // @[package.scala:45:27]
wire [15:0] hi_lo_7 = {hi_15, lo_12, hi_14, lo_11}; // @[package.scala:45:{27,36}]
wire [15:0] hi_hi_15 = {hi_17, lo_14, hi_16, lo_13}; // @[package.scala:45:{27,36}]
wire [31:0] hi_18 = {hi_hi_15, hi_lo_7}; // @[package.scala:45:27]
reg [63:0] reg_custom_0; // @[CSR.scala:798:43]
assign io_customCSRs_0_value_0 = reg_custom_0; // @[CSR.scala:377:7, :798:43]
wire _reg_custom_read_T = |io_rw_cmd_0; // @[CSR.scala:377:7, :799:26]
wire _reg_custom_read_T_1 = io_rw_addr_0 == 12'h7C1; // @[CSR.scala:377:7, :799:50]
assign reg_custom_read = _reg_custom_read_T & _reg_custom_read_T_1; // @[CSR.scala:799:{26,36,50}]
assign io_customCSRs_0_ren_0 = reg_custom_read; // @[CSR.scala:377:7, :799:36]
reg [63:0] reg_custom_1; // @[CSR.scala:798:43]
assign io_customCSRs_1_value_0 = reg_custom_1; // @[CSR.scala:377:7, :798:43]
wire [63:0] _reg_custom_1_T_2 = reg_custom_1; // @[CSR.scala:798:43, :1506:38]
wire [63:0] _reg_custom_1_T_6 = reg_custom_1; // @[CSR.scala:798:43, :1531:39]
wire _reg_custom_read_T_2 = |io_rw_cmd_0; // @[CSR.scala:377:7, :799:26]
wire _reg_custom_read_T_3 = io_rw_addr_0 == 12'hF12; // @[CSR.scala:377:7, :799:50]
assign reg_custom_read_1 = _reg_custom_read_T_2 & _reg_custom_read_T_3; // @[CSR.scala:799:{26,36,50}]
assign io_customCSRs_1_ren_0 = reg_custom_read_1; // @[CSR.scala:377:7, :799:36]
reg [63:0] reg_custom_2; // @[CSR.scala:798:43]
assign io_customCSRs_2_value_0 = reg_custom_2; // @[CSR.scala:377:7, :798:43]
wire [63:0] _reg_custom_2_T_2 = reg_custom_2; // @[CSR.scala:798:43, :1506:38]
wire [63:0] _reg_custom_2_T_6 = reg_custom_2; // @[CSR.scala:798:43, :1531:39]
wire _reg_custom_read_T_4 = |io_rw_cmd_0; // @[CSR.scala:377:7, :799:26]
wire _reg_custom_read_T_5 = io_rw_addr_0 == 12'hF11; // @[CSR.scala:377:7, :799:50]
assign reg_custom_read_2 = _reg_custom_read_T_4 & _reg_custom_read_T_5; // @[CSR.scala:799:{26,36,50}]
assign io_customCSRs_2_ren_0 = reg_custom_read_2; // @[CSR.scala:377:7, :799:36]
reg [63:0] reg_custom_3; // @[CSR.scala:798:43]
assign io_customCSRs_3_value_0 = reg_custom_3; // @[CSR.scala:377:7, :798:43]
wire [63:0] _reg_custom_3_T_2 = reg_custom_3; // @[CSR.scala:798:43, :1506:38]
wire [63:0] _reg_custom_3_T_6 = reg_custom_3; // @[CSR.scala:798:43, :1531:39]
wire _reg_custom_read_T_6 = |io_rw_cmd_0; // @[CSR.scala:377:7, :799:26]
wire _reg_custom_read_T_7 = io_rw_addr_0 == 12'hF13; // @[CSR.scala:377:7, :799:50]
assign reg_custom_read_3 = _reg_custom_read_T_6 & _reg_custom_read_T_7; // @[CSR.scala:799:{26,36,50}]
assign io_customCSRs_3_ren_0 = reg_custom_read_3; // @[CSR.scala:377:7, :799:36]
wire [12:0] decoded_addr_addr = {io_status_v_0, io_rw_addr_0}; // @[CSR.scala:377:7, :851:19]
wire [11:0] decoded_addr_decoded_decoded_plaInput; // @[pla.scala:77:22]
wire [11:0] decoded_addr_decoded_decoded_invInputs = ~decoded_addr_decoded_decoded_plaInput; // @[pla.scala:77:22, :78:21]
wire [149:0] decoded_addr_decoded_decoded_invMatrixOutputs; // @[pla.scala:120:37]
wire [149:0] decoded_addr_decoded_decoded; // @[pla.scala:81:23]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_4 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_5 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_8 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_9 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_14 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_15 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_18 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_19 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_22 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_24 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_25 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_28 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_29 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_32 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_33 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_36 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_37 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_40 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_41 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_44 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_45 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_48 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_49 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_52 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_53 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_57 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_59 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_60 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_63 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_64 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_67 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_68 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_71 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_72 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_75 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_76 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_79 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_80 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_83 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_86 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_87 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_90 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_91 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_94 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_95 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_98 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_99 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_102 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_103 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_106 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_107 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_110 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_111 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_114 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_117 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_118 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_121 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_122 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_125 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_126 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_129 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_130 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_133 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_134 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_137 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_138 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_141 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_142 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_145 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_148 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_149 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_1 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_2 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_3 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_8 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_9 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_10 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_11 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_14 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_15 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_16 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_17 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_22 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_23 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_28 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_29 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_30 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_31 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_36 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_37 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_38 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_39 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_44 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_45 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_46 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_47 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_52 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_53 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_54 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_55 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_57 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_58 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_59 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_60 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_61 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_62 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_67 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_68 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_69 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_70 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_75 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_76 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_77 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_78 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_79 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_80 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_81 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_83 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_84 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_85 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_90 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_91 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_92 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_93 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_98 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_99 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_100 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_101 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_106 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_107 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_108 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_109 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_114 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_115 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_116 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_121 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_122 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_123 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_124 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_129 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_130 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_131 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_132 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_137 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_138 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_139 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_140 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_145 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_146 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_147 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_1 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_2 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_3 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_4 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_5 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_6 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_8 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_9 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_10 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_11 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_12 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_14 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_15 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_16 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_17 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_18 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_19 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_20 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_22 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_23 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_24 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_25 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_26 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_27 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_36 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_37 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_38 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_39 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_40 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_41 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_42 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_43 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_52 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_53 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_54 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_55 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_56 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_57 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_58 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_59 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_60 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_61 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_62 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_63 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_64 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_65 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_66 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_75 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_76 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_77 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_78 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_79 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_80 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_81 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_83 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_84 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_85 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_86 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_87 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_88 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_89 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_98 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_99 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_100 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_101 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_102 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_103 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_104 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_105 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_114 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_115 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_116 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_117 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_118 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_119 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_120 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_129 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_130 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_131 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_132 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_133 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_134 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_135 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_136 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_145 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_146 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_147 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_148 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_149 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_1 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_2 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_3 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_4 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_5 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_6 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_7 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_8 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_9 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_10 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_11 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_12 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_14 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_15 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_16 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_17 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_18 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_19 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_20 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_21 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_22 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_23 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_24 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_25 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_26 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_27 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_28 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_29 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_30 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_31 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_32 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_33 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_34 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_35 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_52 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_53 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_54 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_55 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_56 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_57 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_58 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_75 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_76 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_77 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_78 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_83 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_84 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_85 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_86 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_87 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_88 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_89 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_90 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_91 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_92 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_93 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_94 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_95 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_96 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_97 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_114 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_115 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_116 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_117 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_118 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_119 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_120 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_121 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_122 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_123 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_124 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_125 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_126 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_127 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_128 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_1 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_2 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_3 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_4 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_5 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_6 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_7 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_8 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_9 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_10 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_11 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_12 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_13 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_14 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_15 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_16 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_17 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_18 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_20 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_21 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_51 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_52 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_53 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_54 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_56 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_83 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_83 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_84 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_85 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_86 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_87 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_88 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_89 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_90 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_91 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_92 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_93 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_94 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_95 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_96 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_97 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_98 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_99 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_100 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_101 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_102 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_103 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_104 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_105 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_106 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_107 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_108 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_109 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_110 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_111 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_112 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_114 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_114 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_115 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_116 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_117 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_118 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_119 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_120 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_121 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_122 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_123 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_124 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_125 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_126 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_127 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_128 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_129 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_130 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_131 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_132 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_133 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_134 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_135 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_136 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_137 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_138 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_139 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_140 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_141 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_142 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_143 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_145 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_145 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_146 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_147 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_148 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_1 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_2 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_3 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_4 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_5 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_6 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_7 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_13 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_14 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_15 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_16 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_17 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_18 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_19 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_21 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_21 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_22 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_23 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_24 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_25 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_26 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_27 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_28 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_29 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_30 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_31 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_32 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_33 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_34 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_35 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_36 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_37 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_38 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_39 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_40 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_41 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_42 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_43 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_44 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_45 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_46 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_47 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_48 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_49 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_50 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_56 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_57 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_58 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_59 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_60 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_61 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_62 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_63 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_64 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_65 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_66 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_67 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_68 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_69 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_70 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_71 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_72 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_73 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_74 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_75 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_76 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_77 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_78 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_79 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_80 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_82 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_82 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_83 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_84 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_85 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_86 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_87 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_88 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_89 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_90 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_91 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_92 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_93 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_94 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_95 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_96 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_97 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_98 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_99 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_100 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_101 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_102 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_103 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_104 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_105 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_106 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_107 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_108 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_109 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_110 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_111 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_113 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_113 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_114 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_115 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_116 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_117 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_118 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_119 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_120 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_121 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_122 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_123 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_124 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_125 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_126 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_127 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_128 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_129 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_130 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_131 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_132 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_133 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_134 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_135 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_136 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_137 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_138 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_139 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_140 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_141 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_142 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_144 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_144 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_145 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_146 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_147 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_1 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_2 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_3 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_4 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_5 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_6 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_7 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_8 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_9 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_10 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_11 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_12 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_13 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_14 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_15 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_16 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_17 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_18 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_19 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_21 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_21 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_22 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_23 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_24 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_25 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_26 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_27 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_28 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_29 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_30 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_31 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_32 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_33 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_34 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_35 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_36 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_37 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_38 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_39 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_40 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_41 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_42 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_43 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_44 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_45 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_46 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_47 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_48 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_49 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_50 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_51 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_52 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_53 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_54 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_55 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_81 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_82 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_83 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_84 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_85 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_86 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_87 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_88 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_89 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_90 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_91 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_92 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_93 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_94 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_95 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_96 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_97 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_98 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_99 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_100 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_101 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_102 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_103 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_104 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_105 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_106 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_107 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_108 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_109 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_110 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_111 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_112 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_113 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_114 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_115 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_116 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_117 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_118 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_119 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_120 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_121 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_122 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_123 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_124 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_125 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_126 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_127 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_128 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_129 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_130 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_131 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_132 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_133 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_134 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_135 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_136 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_137 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_138 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_139 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_140 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_141 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_142 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_143 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_144 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_145 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_146 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_147 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_1 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_2 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_112 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_113 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_114 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_115 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_116 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_117 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_118 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_119 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_120 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_121 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_122 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_123 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_124 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_125 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_126 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_127 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_128 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_129 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_130 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_131 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_132 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_133 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_134 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_135 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_136 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_137 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_138 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_139 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_140 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_141 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_142 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_1 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_2 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_3 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_4 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_5 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_6 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_7 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_7 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_8 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_9 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_10 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_12 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_13 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_112 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_111 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_112 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_113 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_114 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_115 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_116 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_117 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_118 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_119 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_120 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_121 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_122 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_123 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_124 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_125 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_126 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_127 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_128 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_129 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_130 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_131 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_132 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_133 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_134 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_135 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_136 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_137 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_138 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_139 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_140 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_1 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_2 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_3 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_3 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_4 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_6 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_7 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_6 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_7 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_8 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_9 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_12 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_13 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_10 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_11 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_12 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_13 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_14 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_15 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_18 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_20 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_19 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_20 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_19 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_20 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_21 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_22 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_23 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_24 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_25 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_26 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_27 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_28 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_29 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_30 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_31 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_32 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_33 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_34 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_35 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_36 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_37 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_38 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_39 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_40 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_41 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_42 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_43 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_44 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_45 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_46 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_47 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_48 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_49 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_50 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_55 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_54 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_55 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_53 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_54 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_55 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_56 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_57 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_58 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_59 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_60 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_61 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_62 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_63 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_64 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_65 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_66 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_67 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_68 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_79 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_77 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_78 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_79 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_80 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_81 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_82 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_83 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_84 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_85 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_86 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_87 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_88 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_89 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_90 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_91 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_92 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_93 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_94 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_95 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_96 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_97 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_98 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_99 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_100 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_101 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_102 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_103 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_104 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_105 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_106 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_1 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_3 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_2 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_3 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_5 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_7 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_4 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_5 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_6 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_7 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_11 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_13 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_8 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_9 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_10 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_11 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_12 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_13 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_16 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_20 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_17 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_18 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_14 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_15 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_16 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_17 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_18 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_19 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_20 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_21 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_22 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_23 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_24 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_25 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_26 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_27 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_28 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_29 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_30 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_31 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_32 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_33 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_34 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_35 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_36 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_37 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_38 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_39 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_40 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_41 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_42 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_43 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_44 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_45 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_53 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_51 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_52 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_46 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_47 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_48 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_49 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_50 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_51 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_52 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_53 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_54 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_55 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_56 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_57 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_58 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_59 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_60 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_61 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_62 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_63 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_64 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_65 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_66 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_67 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_75 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_81 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8}; // @[pla.scala:91:29, :98:53]
wire [4:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo}; // @[pla.scala:98:53]
wire [10:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T = {decoded_addr_decoded_decoded_andMatrixOutputs_hi, decoded_addr_decoded_decoded_andMatrixOutputs_lo}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_138_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_132 = decoded_addr_decoded_decoded_andMatrixOutputs_138_2; // @[pla.scala:98:70, :114:36]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_1 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_4 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_8 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_10 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_14 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_16 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_18 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_24 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_26 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_28 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_30 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_32 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_34 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_36 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_38 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_40 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_42 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_44 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_46 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_48 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_50 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_52 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_54 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_59 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_61 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_63 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_65 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_67 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_69 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_71 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_73 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_75 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_77 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_79 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_84 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_86 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_88 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_90 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_92 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_94 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_96 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_98 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_100 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_102 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_104 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_106 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_108 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_110 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_112 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_115 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_117 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_119 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_121 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_123 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_125 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_127 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_129 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_131 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_133 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_135 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_137 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_139 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_141 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_143 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_146 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_148 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_1 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_2 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_6 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_10 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_11 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_16 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_17 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_20 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_23 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_26 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_27 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_30 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_31 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_34 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_35 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_38 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_39 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_42 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_43 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_46 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_47 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_50 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_51 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_54 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_55 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_58 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_61 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_62 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_65 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_66 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_69 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_70 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_73 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_74 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_77 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_78 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_81 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_84 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_85 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_88 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_89 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_92 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_93 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_96 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_97 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_100 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_101 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_104 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_105 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_108 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_109 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_112 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_113 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_115 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_116 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_119 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_120 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_123 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_124 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_127 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_128 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_131 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_132 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_135 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_136 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_139 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_140 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_143 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_144 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_146 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_147 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_1, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_1}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_1 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_1 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_1, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_1}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_1 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_1, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_1}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_1 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_1, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_1}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_1 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_1, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_1}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_1 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_1, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_1}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_1 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_1, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_1}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_1 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_1, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_1}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_1 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_1, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_1}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_1 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_1, decoded_addr_decoded_decoded_andMatrixOutputs_lo_1}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_134_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_1; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_131 = decoded_addr_decoded_decoded_andMatrixOutputs_134_2; // @[pla.scala:98:70, :114:36]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_2 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_5 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_9 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_11 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_15 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_17 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_19 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_25 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_27 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_29 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_31 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_33 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_35 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_37 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_39 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_41 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_43 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_45 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_47 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_49 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_51 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_53 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_55 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_60 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_62 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_64 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_66 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_68 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_70 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_72 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_74 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_76 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_78 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_80 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_85 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_87 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_89 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_91 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_93 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_95 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_97 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_99 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_101 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_103 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_105 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_107 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_109 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_111 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_113 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_116 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_118 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_120 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_122 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_124 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_126 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_128 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_130 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_132 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_134 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_136 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_138 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_140 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_142 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_144 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_147 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_149 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_1 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_2, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_2}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_2 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_1, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_1}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_2 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_2, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_2}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_2 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_2, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_2}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_2 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_2, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_2}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_2 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_2, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_2}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_2 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_2, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_2}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_2 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_2, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_2}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_2 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_2, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_2}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_2 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_2, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_2}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_2 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_2, decoded_addr_decoded_decoded_andMatrixOutputs_lo_2}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_41_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_2; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_130 = decoded_addr_decoded_decoded_andMatrixOutputs_41_2; // @[pla.scala:98:70, :114:36]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_3 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_4 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_5 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_6 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_7 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_8 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_9 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_10 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_11 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_12 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_13 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_13 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_14 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_15 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_16 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_17 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_18 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_19 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_20 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_21 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_22 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_23 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_24 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_25 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_26 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_27 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_28 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_29 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_30 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_31 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_32 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_33 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_34 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_35 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_36 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_37 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_38 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_39 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_40 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_41 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_42 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_43 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_44 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_45 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_46 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_47 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_48 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_49 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_50 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_51 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_52 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_53 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_54 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_55 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_56 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_57 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_58 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_59 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_60 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_61 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_62 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_63 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_64 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_65 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_66 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_67 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_68 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_69 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_70 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_71 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_72 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_73 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_74 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_75 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_76 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_77 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_78 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_79 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_80 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_82 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_81 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_82 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_83 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_84 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_85 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_86 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_87 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_88 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_89 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_90 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_91 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_92 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_93 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_94 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_95 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_96 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_97 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_98 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_99 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_100 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_101 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_102 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_103 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_104 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_105 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_106 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_107 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_108 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_109 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_110 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_111 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_143 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_144 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_145 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_146 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_147 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_3 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_3, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_3}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_3 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_3, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_3}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_3 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_3, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_3}; // @[pla.scala:91:29, :98:53]
wire [4:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_3 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_3, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_3}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_3 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_3, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_3}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_3 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_3, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_3}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_3 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_3, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_3}; // @[pla.scala:91:29, :98:53]
wire [4:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_3 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_3, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_3}; // @[pla.scala:98:53]
wire [9:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_3 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_3, decoded_addr_decoded_decoded_andMatrixOutputs_lo_3}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_1_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_3; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_35 = decoded_addr_decoded_decoded_andMatrixOutputs_1_2; // @[pla.scala:98:70, :114:36]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_4 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_5 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_6 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_12 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_18 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_19 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_20 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_24 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_25 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_26 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_27 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_32 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_33 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_34 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_35 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_40 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_41 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_42 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_43 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_48 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_49 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_50 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_51 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_56 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_63 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_64 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_65 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_66 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_71 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_72 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_73 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_74 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_86 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_87 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_88 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_89 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_94 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_95 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_96 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_97 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_102 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_103 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_104 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_105 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_110 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_111 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_112 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_113 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_117 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_118 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_119 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_120 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_125 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_126 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_127 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_128 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_133 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_134 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_135 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_136 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_141 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_142 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_143 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_144 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_148 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_149 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_2 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_4, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_3}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_4 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_2, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_2}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_4 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_4, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_4}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_4 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_4, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_4}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_4 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_4, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_4}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_3 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_4, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_4}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_4 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_3, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_4}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_4 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_4, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_4}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_4 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_4, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_4}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_4 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_4, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_4}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_4 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_4, decoded_addr_decoded_decoded_andMatrixOutputs_lo_4}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_89_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_4; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_33 = decoded_addr_decoded_decoded_andMatrixOutputs_89_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_3 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_5, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_4}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_5 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_3, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_3}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_5 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_5, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_5}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_5 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_5, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_5}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_5 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_5, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_5}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_4 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_5, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_5}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_5 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_4, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_5}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_5 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_5, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_5}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_5 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_5, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_5}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_5 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_5, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_5}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_5 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_5, decoded_addr_decoded_decoded_andMatrixOutputs_lo_5}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_123_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_5; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_27 = decoded_addr_decoded_decoded_andMatrixOutputs_123_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_6 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_6, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_5}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_6 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_6, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_6}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_6 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_6, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_6}; // @[pla.scala:91:29, :98:53]
wire [4:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_6 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_6, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_6}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_5 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_6, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_6}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_6 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_5, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_6}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_6 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_6, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_6}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_6 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_6, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_6}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_6 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_6, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_6}; // @[pla.scala:98:53]
wire [10:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_6 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_6, decoded_addr_decoded_decoded_andMatrixOutputs_lo_6}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_27_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_6; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_26 = decoded_addr_decoded_decoded_andMatrixOutputs_27_2; // @[pla.scala:98:70, :114:36]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_7 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_21 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_28 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_29 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_30 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_31 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_32 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_33 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_34 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_35 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_44 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_45 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_46 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_47 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_48 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_49 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_50 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_51 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_67 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_68 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_69 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_70 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_71 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_72 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_73 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_74 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_90 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_91 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_92 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_93 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_94 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_95 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_96 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_97 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_106 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_107 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_108 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_109 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_110 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_111 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_112 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_113 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_121 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_122 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_123 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_124 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_125 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_126 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_127 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_128 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_137 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_138 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_139 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_140 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_141 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_142 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_143 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_144 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_7 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_7, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_7}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_7 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_7, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_7}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_7 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_7, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_7}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_7 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_7, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_7}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_7 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_7, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_7}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_7 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_7, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_7}; // @[pla.scala:91:29, :98:53]
wire [4:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_7 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_7, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_7}; // @[pla.scala:98:53]
wire [8:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_7 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_7, decoded_addr_decoded_decoded_andMatrixOutputs_lo_7}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_0_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_7; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_23 = decoded_addr_decoded_decoded_andMatrixOutputs_0_2; // @[pla.scala:98:70, :114:36]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_8 = decoded_addr_decoded_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_9 = decoded_addr_decoded_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_10 = decoded_addr_decoded_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_11 = decoded_addr_decoded_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_12 = decoded_addr_decoded_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_51 = decoded_addr_decoded_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_52 = decoded_addr_decoded_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_53 = decoded_addr_decoded_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_54 = decoded_addr_decoded_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_56 = decoded_addr_decoded_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_82 = decoded_addr_decoded_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_4 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_7, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_6}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_8 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_4, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_4}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_7 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_8, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_8}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_8 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_7, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_8}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_8 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_8, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_8}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_6 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_8, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_8}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_8 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_6, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_8}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_8 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_8, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_8}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_8 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_8, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_8}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_8 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_8, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_8}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_8 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_8, decoded_addr_decoded_decoded_andMatrixOutputs_lo_8}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_92_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_8; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_32 = decoded_addr_decoded_decoded_andMatrixOutputs_92_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_5 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_8, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_7}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_9 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_5, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_5}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_8 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_9, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_9}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_9 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_8, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_9}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_9 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_9, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_9}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_7 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_9, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_9}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_9 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_7, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_9}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_9 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_9, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_9}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_9 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_9, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_9}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_9 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_9, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_9}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_9 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_9, decoded_addr_decoded_decoded_andMatrixOutputs_lo_9}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_59_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_9; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_28 = decoded_addr_decoded_decoded_andMatrixOutputs_59_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_6 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_9, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_8}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_10 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_6, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_6}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_9 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_10, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_10}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_10 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_9, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_10}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_10 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_10, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_10}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_8 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_10, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_10}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_10 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_8, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_10}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_10 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_10, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_10}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_10 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_10, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_10}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_10 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_10, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_10}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_10 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_10, decoded_addr_decoded_decoded_andMatrixOutputs_lo_10}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_24_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_10; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_31 = decoded_addr_decoded_decoded_andMatrixOutputs_24_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_7 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_10, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_9}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_11 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_7, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_7}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_10 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_11, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_11}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_11 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_10, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_11}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_11 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_11, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_11}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_9 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_11, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_11}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_11 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_9, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_11}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_11 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_11, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_11}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_11 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_11, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_11}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_11 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_11, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_11}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_11 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_11, decoded_addr_decoded_decoded_andMatrixOutputs_lo_11}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_116_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_11; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_30 = decoded_addr_decoded_decoded_andMatrixOutputs_116_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_12 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_12, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_11}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_11 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_12, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_12}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_12 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_11, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_12}; // @[pla.scala:91:29, :98:53]
wire [4:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_12 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_12, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_12}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_12 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_12, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_12}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_12 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_12, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_12}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_12 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_12, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_12}; // @[pla.scala:91:29, :98:53]
wire [4:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_12 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_12, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_12}; // @[pla.scala:98:53]
wire [9:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_12 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_12, decoded_addr_decoded_decoded_andMatrixOutputs_lo_12}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_121_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_12; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_34 = decoded_addr_decoded_decoded_andMatrixOutputs_121_2; // @[pla.scala:98:70, :114:36]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_13 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_56 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_57 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_58 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_59 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_60 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_61 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_62 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_63 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_64 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_65 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_66 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_67 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_68 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_69 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_70 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_71 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_72 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_73 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_74 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_75 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_76 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_77 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_78 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_79 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_80 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_82 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_13 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_13, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_13}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_13 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_13, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_13}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_13 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_13, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_13}; // @[pla.scala:91:29, :98:53]
wire [4:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_13 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_13, decoded_addr_decoded_decoded_andMatrixOutputs_lo_13}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_74_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_13; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_29 = decoded_addr_decoded_decoded_andMatrixOutputs_74_2; // @[pla.scala:98:70, :114:36]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_12 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_13 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_14 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_15 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_16 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_17 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_19 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_20 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_21 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_22 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_21 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_22 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_23 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_24 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_25 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_26 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_27 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_28 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_29 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_30 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_31 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_32 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_33 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_34 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_35 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_36 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_37 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_38 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_39 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_40 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_41 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_42 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_43 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_44 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_45 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_46 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_47 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_48 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_49 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_50 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_51 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_52 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_55 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_56 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_57 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_56 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_57 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_58 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_59 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_60 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_61 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_62 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_63 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_64 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_65 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_66 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_67 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_68 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_69 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_70 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_71 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_72 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_73 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_74 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_75 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_76 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_77 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_80 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_82 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_81 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_80 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_81 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_82 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_83 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_84 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_85 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_86 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_87 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_88 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_89 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_90 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_91 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_92 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_93 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_94 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_95 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_96 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_97 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_98 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_99 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_100 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_101 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_102 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_103 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_104 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_105 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_106 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_107 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_108 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_109 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_143 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_142 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_143 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_144 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_145 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_8 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_12, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_10}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_13 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_8, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_8}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_12 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_13, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_13}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_13 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_12, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_13}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_14 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_13, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_13}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_10 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_14, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_14}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_13 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_10, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_13}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_13 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_14, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_14}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_14 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_13, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_14}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_14 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_14, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_13}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_14 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_14, decoded_addr_decoded_decoded_andMatrixOutputs_lo_14}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_114_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_14; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_144 = decoded_addr_decoded_decoded_andMatrixOutputs_114_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_9 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_13, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_11}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_14 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_9, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_9}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_13 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_14, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_14}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_14 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_13, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_14}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_15 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_14, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_14}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_11 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_15, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_15}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_14 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_11, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_14}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_14 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_15, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_15}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_15 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_14, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_15}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_15 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_15, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_14}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_15 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_15, decoded_addr_decoded_decoded_andMatrixOutputs_lo_15}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_104_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_15; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_145 = decoded_addr_decoded_decoded_andMatrixOutputs_104_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_10 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_14, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_12}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_15 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_10, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_10}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_14 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_15, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_15}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_15 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_14, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_15}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_16 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_15, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_15}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_12 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_16, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_16}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_15 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_12, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_15}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_15 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_16, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_16}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_16 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_15, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_16}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_16 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_16, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_15}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_16 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_16, decoded_addr_decoded_decoded_andMatrixOutputs_lo_16}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_82_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_16; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_24 = decoded_addr_decoded_decoded_andMatrixOutputs_82_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_11 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_15, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_13}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_16 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_11, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_11}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_15 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_16, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_16}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_16 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_15, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_16}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_17 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_16, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_16}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_13 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_17, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_17}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_16 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_13, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_16}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_16 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_17, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_17}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_17 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_16, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_17}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_17 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_17, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_16}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_17 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_17, decoded_addr_decoded_decoded_andMatrixOutputs_lo_17}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_28_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_17; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_25 = decoded_addr_decoded_decoded_andMatrixOutputs_28_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_12 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_16, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_14}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_17 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_12, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_12}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_16 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_17, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_17}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_17 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_16, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_17}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_18 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_17, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_17}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_14 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_18, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_18}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_17 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_14, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_17}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_17 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_18, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_18}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_18 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_17, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_18}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_18 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_18, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_17}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_18 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_18, decoded_addr_decoded_decoded_andMatrixOutputs_lo_18}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_91_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_18; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_141 = decoded_addr_decoded_decoded_andMatrixOutputs_91_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_13 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_17, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_15}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_18 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_13, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_13}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_17 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_18, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_18}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_18 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_17, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_18}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_19 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_18, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_18}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_15 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_19, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_19}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_18 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_15, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_18}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_18 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_19, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_19}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_19 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_18, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_19}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_19 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_19, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_18}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_19 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_19, decoded_addr_decoded_decoded_andMatrixOutputs_lo_19}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_68_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_19; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_143 = decoded_addr_decoded_decoded_andMatrixOutputs_68_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_19 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_18, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_16}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_18 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_19, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_19}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_19 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_18, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_19}; // @[pla.scala:90:45, :98:53]
wire [4:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_20 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_19, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_19}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_16 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_20, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_20}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_19 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_16, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_19}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_19 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_20, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_20}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_20 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_19, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_20}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_20 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_20, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_19}; // @[pla.scala:98:53]
wire [10:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_20 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_20, decoded_addr_decoded_decoded_andMatrixOutputs_lo_20}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_84_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_20; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_39 = decoded_addr_decoded_decoded_andMatrixOutputs_84_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_20 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_20, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_20}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_20 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_20, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_20}; // @[pla.scala:90:45, :98:53]
wire [3:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_21 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_20, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_20}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_20 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_21, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_21}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_20 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_21, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_21}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_21 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_20, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_21}; // @[pla.scala:91:29, :98:53]
wire [4:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_21 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_21, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_20}; // @[pla.scala:98:53]
wire [8:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_21 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_21, decoded_addr_decoded_decoded_andMatrixOutputs_lo_21}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_40_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_21; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_36 = decoded_addr_decoded_decoded_andMatrixOutputs_40_2; // @[pla.scala:98:70, :114:36]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_22 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_23 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_23 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_24 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_25 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_26 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_27 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_28 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_29 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_30 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_31 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_32 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_33 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_34 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_35 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_36 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_37 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_38 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_39 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_40 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_41 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_42 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_43 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_44 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_45 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_46 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_47 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_48 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_49 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_50 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_57 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_58 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_58 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_59 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_60 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_61 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_62 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_63 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_64 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_65 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_66 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_67 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_68 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_69 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_70 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_71 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_72 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_73 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_74 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_75 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_76 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_77 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_78 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_79 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_81 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_21 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_19, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_17}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_19 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_21, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_21}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_21 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_19, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_21}; // @[pla.scala:90:45, :98:53]
wire [4:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_22 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_21, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_21}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_17 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_22, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_22}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_21 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_17, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_21}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_21 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_22, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_22}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_22 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_21, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_22}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_22 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_22, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_21}; // @[pla.scala:98:53]
wire [10:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_22 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_22, decoded_addr_decoded_decoded_andMatrixOutputs_lo_22}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_34_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_22; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_129 = decoded_addr_decoded_decoded_andMatrixOutputs_34_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_22 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_20, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_18}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_20 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_22, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_22}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_22 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_20, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_22}; // @[pla.scala:90:45, :98:53]
wire [4:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_23 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_22, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_22}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_18 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_23, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_23}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_22 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_18, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_22}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_22 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_23, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_23}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_23 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_22, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_23}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_23 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_23, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_22}; // @[pla.scala:98:53]
wire [10:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_23 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_23, decoded_addr_decoded_decoded_andMatrixOutputs_lo_23}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_136_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_23; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_126 = decoded_addr_decoded_decoded_andMatrixOutputs_136_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_14 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_21, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_19}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_23 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_14, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_14}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_21 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_23, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_23}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_23 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_21, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_23}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_24 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_23, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_23}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_19 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_24, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_24}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_23 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_19, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_23}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_23 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_24, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_24}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_24 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_23, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_24}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_24 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_24, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_23}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_24 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_24, decoded_addr_decoded_decoded_andMatrixOutputs_lo_24}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_55_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_24; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_123 = decoded_addr_decoded_decoded_andMatrixOutputs_55_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_15 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_22, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_20}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_24 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_15, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_15}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_22 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_24, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_24}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_24 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_22, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_24}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_25 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_24, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_24}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_20 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_25, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_25}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_24 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_20, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_24}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_24 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_25, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_25}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_25 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_24, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_25}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_25 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_25, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_24}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_25 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_25, decoded_addr_decoded_decoded_andMatrixOutputs_lo_25}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_105_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_25; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_120 = decoded_addr_decoded_decoded_andMatrixOutputs_105_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_16 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_23, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_21}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_25 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_16, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_16}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_23 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_25, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_25}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_25 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_23, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_25}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_26 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_25, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_25}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_21 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_26, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_26}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_25 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_21, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_25}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_25 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_26, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_26}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_26 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_25, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_26}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_26 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_26, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_25}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_26 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_26, decoded_addr_decoded_decoded_andMatrixOutputs_lo_26}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_109_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_26; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_117 = decoded_addr_decoded_decoded_andMatrixOutputs_109_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_17 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_24, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_22}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_26 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_17, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_17}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_24 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_26, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_26}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_26 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_24, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_26}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_27 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_26, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_26}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_22 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_27, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_27}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_26 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_22, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_26}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_26 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_27, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_27}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_27 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_26, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_27}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_27 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_27, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_26}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_27 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_27, decoded_addr_decoded_decoded_andMatrixOutputs_lo_27}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_7_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_27; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_114 = decoded_addr_decoded_decoded_andMatrixOutputs_7_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_18 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_25, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_23}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_27 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_18, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_18}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_25 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_27, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_27}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_27 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_25, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_27}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_28 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_27, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_27}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_23 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_28, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_28}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_27 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_23, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_27}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_27 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_28, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_28}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_28 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_27, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_28}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_28 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_28, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_27}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_28 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_28, decoded_addr_decoded_decoded_andMatrixOutputs_lo_28}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_47_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_28; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_111 = decoded_addr_decoded_decoded_andMatrixOutputs_47_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_19 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_26, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_24}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_28 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_19, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_19}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_26 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_28, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_28}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_28 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_26, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_28}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_29 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_28, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_28}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_24 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_29, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_29}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_28 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_24, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_28}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_28 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_29, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_29}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_29 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_28, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_29}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_29 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_29, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_28}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_29 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_29, decoded_addr_decoded_decoded_andMatrixOutputs_lo_29}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_141_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_29; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_108 = decoded_addr_decoded_decoded_andMatrixOutputs_141_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_20 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_27, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_25}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_29 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_20, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_20}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_27 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_29, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_29}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_29 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_27, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_29}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_30 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_29, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_29}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_25 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_30, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_30}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_29 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_25, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_29}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_29 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_30, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_30}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_30 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_29, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_30}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_30 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_30, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_29}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_30 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_30, decoded_addr_decoded_decoded_andMatrixOutputs_lo_30}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_11_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_30; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_105 = decoded_addr_decoded_decoded_andMatrixOutputs_11_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_21 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_28, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_26}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_30 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_21, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_21}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_28 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_30, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_30}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_30 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_28, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_30}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_31 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_30, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_30}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_26 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_31, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_31}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_30 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_26, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_30}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_30 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_31, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_31}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_31 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_30, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_31}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_31 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_31, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_30}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_31 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_31, decoded_addr_decoded_decoded_andMatrixOutputs_lo_31}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_118_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_31; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_102 = decoded_addr_decoded_decoded_andMatrixOutputs_118_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_22 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_29, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_27}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_31 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_22, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_22}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_29 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_31, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_31}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_31 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_29, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_31}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_32 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_31, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_31}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_27 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_32, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_32}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_31 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_27, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_31}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_31 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_32, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_32}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_32 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_31, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_32}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_32 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_32, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_31}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_32 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_32, decoded_addr_decoded_decoded_andMatrixOutputs_lo_32}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_120_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_32; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_99 = decoded_addr_decoded_decoded_andMatrixOutputs_120_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_23 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_30, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_28}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_32 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_23, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_23}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_30 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_32, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_32}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_32 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_30, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_32}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_33 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_32, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_32}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_28 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_33, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_33}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_32 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_28, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_32}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_32 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_33, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_33}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_33 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_32, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_33}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_33 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_33, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_32}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_33 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_33, decoded_addr_decoded_decoded_andMatrixOutputs_lo_33}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_139_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_33; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_96 = decoded_addr_decoded_decoded_andMatrixOutputs_139_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_24 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_31, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_29}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_33 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_24, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_24}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_31 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_33, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_33}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_33 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_31, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_33}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_34 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_33, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_33}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_29 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_34, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_34}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_33 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_29, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_33}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_33 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_34, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_34}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_34 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_33, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_34}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_34 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_34, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_33}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_34 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_34, decoded_addr_decoded_decoded_andMatrixOutputs_lo_34}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_86_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_34; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_93 = decoded_addr_decoded_decoded_andMatrixOutputs_86_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_25 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_32, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_30}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_34 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_25, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_25}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_32 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_34, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_34}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_34 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_32, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_34}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_35 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_34, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_34}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_30 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_35, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_35}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_34 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_30, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_34}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_34 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_35, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_35}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_35 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_34, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_35}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_35 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_35, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_34}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_35 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_35, decoded_addr_decoded_decoded_andMatrixOutputs_lo_35}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_8_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_35; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_90 = decoded_addr_decoded_decoded_andMatrixOutputs_8_2; // @[pla.scala:98:70, :114:36]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_36 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_37 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_38 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_39 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_40 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_41 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_42 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_43 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_44 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_45 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_46 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_47 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_48 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_49 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_50 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_51 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_59 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_60 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_61 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_62 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_63 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_64 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_65 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_66 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_67 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_68 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_69 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_70 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_71 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_72 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_73 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_74 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_79 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_80 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_81 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_98 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_99 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_100 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_101 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_102 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_103 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_104 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_105 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_106 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_107 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_108 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_109 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_110 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_111 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_112 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_113 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_129 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_130 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_131 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_132 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_133 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_134 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_135 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_136 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_137 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_138 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_139 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_140 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_141 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_142 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_143 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_144 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_145 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_146 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_147 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_148 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_149 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_26 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_33, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_31}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_35 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_26, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_26}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_33 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_35, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_35}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_35 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_33, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_35}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_36 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_35, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_35}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_31 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_36, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_36}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_35 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_31, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_35}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_35 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_36, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_36}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_36 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_35, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_36}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_36 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_36, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_35}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_36 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_36, decoded_addr_decoded_decoded_andMatrixOutputs_lo_36}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_61_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_36; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_87 = decoded_addr_decoded_decoded_andMatrixOutputs_61_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_27 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_34, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_32}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_36 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_27, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_27}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_34 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_36, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_36}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_36 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_34, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_36}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_37 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_36, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_36}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_32 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_37, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_37}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_36 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_32, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_36}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_36 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_37, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_37}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_37 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_36, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_37}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_37 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_37, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_36}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_37 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_37, decoded_addr_decoded_decoded_andMatrixOutputs_lo_37}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_83_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_37; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_84 = decoded_addr_decoded_decoded_andMatrixOutputs_83_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_28 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_35, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_33}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_37 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_28, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_28}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_35 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_37, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_37}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_37 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_35, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_37}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_38 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_37, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_37}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_33 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_38, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_38}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_37 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_33, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_37}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_37 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_38, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_38}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_38 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_37, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_38}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_38 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_38, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_37}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_38 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_38, decoded_addr_decoded_decoded_andMatrixOutputs_lo_38}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_129_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_38; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_81 = decoded_addr_decoded_decoded_andMatrixOutputs_129_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_29 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_36, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_34}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_38 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_29, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_29}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_36 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_38, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_38}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_38 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_36, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_38}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_39 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_38, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_38}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_34 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_39, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_39}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_38 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_34, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_38}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_38 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_39, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_39}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_39 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_38, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_39}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_39 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_39, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_38}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_39 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_39, decoded_addr_decoded_decoded_andMatrixOutputs_lo_39}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_17_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_39; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_78 = decoded_addr_decoded_decoded_andMatrixOutputs_17_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_30 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_37, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_35}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_39 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_30, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_30}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_37 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_39, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_39}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_39 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_37, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_39}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_40 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_39, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_39}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_35 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_40, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_40}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_39 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_35, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_39}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_39 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_40, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_40}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_40 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_39, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_40}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_40 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_40, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_39}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_40 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_40, decoded_addr_decoded_decoded_andMatrixOutputs_lo_40}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_87_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_40; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_75 = decoded_addr_decoded_decoded_andMatrixOutputs_87_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_31 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_38, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_36}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_40 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_31, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_31}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_38 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_40, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_40}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_40 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_38, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_40}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_41 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_40, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_40}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_36 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_41, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_41}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_40 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_36, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_40}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_40 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_41, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_41}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_41 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_40, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_41}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_41 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_41, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_40}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_41 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_41, decoded_addr_decoded_decoded_andMatrixOutputs_lo_41}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_133_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_41; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_72 = decoded_addr_decoded_decoded_andMatrixOutputs_133_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_32 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_39, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_37}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_41 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_32, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_32}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_39 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_41, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_41}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_41 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_39, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_41}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_42 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_41, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_41}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_37 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_42, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_42}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_41 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_37, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_41}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_41 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_42, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_42}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_42 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_41, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_42}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_42 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_42, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_41}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_42 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_42, decoded_addr_decoded_decoded_andMatrixOutputs_lo_42}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_142_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_42; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_69 = decoded_addr_decoded_decoded_andMatrixOutputs_142_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_33 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_40, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_38}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_42 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_33, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_33}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_40 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_42, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_42}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_42 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_40, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_42}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_43 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_42, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_42}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_38 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_43, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_43}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_42 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_38, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_42}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_42 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_43, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_43}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_43 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_42, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_43}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_43 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_43, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_42}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_43 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_43, decoded_addr_decoded_decoded_andMatrixOutputs_lo_43}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_22_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_43; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_66 = decoded_addr_decoded_decoded_andMatrixOutputs_22_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_34 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_41, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_39}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_43 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_34, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_34}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_41 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_43, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_43}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_43 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_41, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_43}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_44 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_43, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_43}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_39 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_44, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_44}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_43 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_39, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_43}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_43 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_44, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_44}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_44 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_43, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_44}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_44 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_44, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_43}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_44 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_44, decoded_addr_decoded_decoded_andMatrixOutputs_lo_44}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_94_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_44; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_63 = decoded_addr_decoded_decoded_andMatrixOutputs_94_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_35 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_42, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_40}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_44 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_35, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_35}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_42 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_44, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_44}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_44 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_42, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_44}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_45 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_44, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_44}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_40 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_45, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_45}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_44 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_40, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_44}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_44 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_45, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_45}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_45 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_44, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_45}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_45 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_45, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_44}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_45 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_45, decoded_addr_decoded_decoded_andMatrixOutputs_lo_45}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_65_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_45; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_60 = decoded_addr_decoded_decoded_andMatrixOutputs_65_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_36 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_43, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_41}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_45 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_36, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_36}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_43 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_45, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_45}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_45 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_43, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_45}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_46 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_45, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_45}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_41 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_46, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_46}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_45 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_41, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_45}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_45 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_46, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_46}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_46 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_45, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_46}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_46 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_46, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_45}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_46 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_46, decoded_addr_decoded_decoded_andMatrixOutputs_lo_46}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_36_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_46; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_57 = decoded_addr_decoded_decoded_andMatrixOutputs_36_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_37 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_44, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_42}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_46 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_37, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_37}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_44 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_46, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_46}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_46 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_44, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_46}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_47 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_46, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_46}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_42 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_47, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_47}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_46 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_42, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_46}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_46 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_47, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_47}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_47 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_46, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_47}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_47 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_47, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_46}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_47 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_47, decoded_addr_decoded_decoded_andMatrixOutputs_lo_47}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_33_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_47; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_54 = decoded_addr_decoded_decoded_andMatrixOutputs_33_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_38 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_45, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_43}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_47 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_38, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_38}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_45 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_47, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_47}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_47 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_45, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_47}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_48 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_47, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_47}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_43 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_48, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_48}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_47 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_43, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_47}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_47 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_48, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_48}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_48 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_47, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_48}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_48 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_48, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_47}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_48 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_48, decoded_addr_decoded_decoded_andMatrixOutputs_lo_48}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_63_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_48; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_51 = decoded_addr_decoded_decoded_andMatrixOutputs_63_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_39 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_46, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_44}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_48 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_39, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_39}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_46 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_48, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_48}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_48 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_46, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_48}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_49 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_48, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_48}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_44 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_49, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_49}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_48 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_44, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_48}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_48 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_49, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_49}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_49 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_48, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_49}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_49 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_49, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_48}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_49 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_49, decoded_addr_decoded_decoded_andMatrixOutputs_lo_49}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_39_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_49; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_48 = decoded_addr_decoded_decoded_andMatrixOutputs_39_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_40 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_47, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_45}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_49 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_40, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_40}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_47 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_49, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_49}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_49 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_47, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_49}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_50 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_49, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_49}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_45 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_50, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_50}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_49 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_45, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_49}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_49 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_50, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_50}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_50 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_49, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_50}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_50 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_50, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_49}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_50 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_50, decoded_addr_decoded_decoded_andMatrixOutputs_lo_50}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_32_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_50; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_45 = decoded_addr_decoded_decoded_andMatrixOutputs_32_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_41 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_48, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_46}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_50 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_41, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_41}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_48 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_50, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_50}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_50 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_48, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_50}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_51 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_50, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_50}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_46 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_51, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_51}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_50 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_46, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_50}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_50 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_51, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_51}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_51 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_50, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_51}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_51 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_51, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_50}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_51 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_51, decoded_addr_decoded_decoded_andMatrixOutputs_lo_51}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_144_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_51; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_42 = decoded_addr_decoded_decoded_andMatrixOutputs_144_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_42 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_49, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_47}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_51 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_42, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_42}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_49 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_51, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_51}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_51 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_49, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_51}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_52 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_51, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_51}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_47 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_52, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_52}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_51 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_47, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_51}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_51 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_52, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_52}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_52 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_51, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_52}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_52 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_52, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_51}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_52 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_52, decoded_addr_decoded_decoded_andMatrixOutputs_lo_52}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_66_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_52; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_140 = decoded_addr_decoded_decoded_andMatrixOutputs_66_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_43 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_50, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_48}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_52 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_43, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_43}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_50 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_52, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_52}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_52 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_50, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_52}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_53 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_52, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_52}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_48 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_53, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_53}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_52 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_48, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_52}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_52 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_53, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_53}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_53 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_52, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_53}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_53 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_53, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_52}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_53 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_53, decoded_addr_decoded_decoded_andMatrixOutputs_lo_53}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_106_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_53; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_139 = decoded_addr_decoded_decoded_andMatrixOutputs_106_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_44 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_51, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_49}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_53 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_44, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_44}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_51 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_53, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_53}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_53 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_51, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_53}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_54 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_53, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_53}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_49 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_54, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_54}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_53 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_49, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_53}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_53 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_54, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_54}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_54 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_53, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_54}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_54 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_54, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_53}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_54 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_54, decoded_addr_decoded_decoded_andMatrixOutputs_lo_54}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_80_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_54; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_137 = decoded_addr_decoded_decoded_andMatrixOutputs_80_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_45 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_52, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_50}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_54 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_45, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_45}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_52 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_54, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_54}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_54 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_52, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_54}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_55 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_54, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_54}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_50 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_55, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_55}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_54 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_50, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_54}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_54 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_55, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_55}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_55 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_54, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_55}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_55 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_55, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_54}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_55 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_55, decoded_addr_decoded_decoded_andMatrixOutputs_lo_55}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_122_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_55; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_138 = decoded_addr_decoded_decoded_andMatrixOutputs_122_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_55 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_55, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_53}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_53 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_55, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_55}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_55 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_53, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_55}; // @[pla.scala:90:45, :98:53]
wire [4:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_56 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_55, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_55}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_55 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_56, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_56}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_55 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_56, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_56}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_56 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_55, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_56}; // @[pla.scala:91:29, :98:53]
wire [4:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_56 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_56, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_55}; // @[pla.scala:98:53]
wire [9:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_56 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_56, decoded_addr_decoded_decoded_andMatrixOutputs_lo_56}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_119_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_56; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_142 = decoded_addr_decoded_decoded_andMatrixOutputs_119_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_56 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_54, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_51}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_54 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_56, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_56}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_56 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_54, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_56}; // @[pla.scala:90:45, :98:53]
wire [4:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_57 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_56, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_56}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_51 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_57, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_57}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_56 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_51, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_56}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_56 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_57, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_57}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_57 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_56, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_57}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_57 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_57, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_56}; // @[pla.scala:98:53]
wire [10:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_57 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_57, decoded_addr_decoded_decoded_andMatrixOutputs_lo_57}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_67_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_57; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_22 = decoded_addr_decoded_decoded_andMatrixOutputs_67_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_57 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_55, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_52}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_55 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_57, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_57}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_57 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_55, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_57}; // @[pla.scala:90:45, :98:53]
wire [4:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_58 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_57, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_57}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_52 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_58, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_58}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_57 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_52, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_57}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_57 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_58, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_58}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_58 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_57, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_58}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_58 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_58, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_57}; // @[pla.scala:98:53]
wire [10:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_58 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_58, decoded_addr_decoded_decoded_andMatrixOutputs_lo_58}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_48_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_58; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_21 = decoded_addr_decoded_decoded_andMatrixOutputs_48_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_46 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_56, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_53}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_58 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_46, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_46}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_56 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_58, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_58}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_58 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_56, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_58}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_59 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_58, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_58}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_53 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_59, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_59}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_58 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_53, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_58}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_58 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_59, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_59}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_59 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_58, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_59}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_59 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_59, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_58}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_59 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_59, decoded_addr_decoded_decoded_andMatrixOutputs_lo_59}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_10_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_59; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_20 = decoded_addr_decoded_decoded_andMatrixOutputs_10_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_47 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_57, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_54}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_59 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_47, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_47}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_57 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_59, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_59}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_59 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_57, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_59}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_60 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_59, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_59}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_54 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_60, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_60}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_59 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_54, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_59}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_59 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_60, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_60}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_60 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_59, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_60}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_60 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_60, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_59}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_60 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_60, decoded_addr_decoded_decoded_andMatrixOutputs_lo_60}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_45_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_60; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_19 = decoded_addr_decoded_decoded_andMatrixOutputs_45_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_48 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_58, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_55}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_60 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_48, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_48}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_58 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_60, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_60}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_60 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_58, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_60}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_61 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_60, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_60}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_55 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_61, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_61}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_60 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_55, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_60}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_60 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_61, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_61}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_61 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_60, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_61}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_61 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_61, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_60}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_61 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_61, decoded_addr_decoded_decoded_andMatrixOutputs_lo_61}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_18_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_61; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_18 = decoded_addr_decoded_decoded_andMatrixOutputs_18_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_49 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_59, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_56}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_61 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_49, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_49}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_59 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_61, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_61}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_61 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_59, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_61}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_62 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_61, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_61}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_56 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_62, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_62}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_61 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_56, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_61}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_61 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_62, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_62}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_62 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_61, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_62}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_62 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_62, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_61}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_62 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_62, decoded_addr_decoded_decoded_andMatrixOutputs_lo_62}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_88_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_62; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_17 = decoded_addr_decoded_decoded_andMatrixOutputs_88_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_50 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_60, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_57}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_62 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_50, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_50}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_60 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_62, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_62}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_62 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_60, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_62}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_63 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_62, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_62}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_57 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_63, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_63}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_62 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_57, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_62}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_62 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_63, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_63}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_63 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_62, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_63}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_63 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_63, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_62}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_63 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_63, decoded_addr_decoded_decoded_andMatrixOutputs_lo_63}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_57_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_63; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_16 = decoded_addr_decoded_decoded_andMatrixOutputs_57_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_51 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_61, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_58}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_63 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_51, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_51}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_61 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_63, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_63}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_63 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_61, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_63}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_64 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_63, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_63}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_58 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_64, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_64}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_63 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_58, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_63}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_63 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_64, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_64}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_64 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_63, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_64}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_64 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_64, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_63}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_64 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_64, decoded_addr_decoded_decoded_andMatrixOutputs_lo_64}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_85_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_64; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_15 = decoded_addr_decoded_decoded_andMatrixOutputs_85_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_52 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_62, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_59}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_64 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_52, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_52}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_62 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_64, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_64}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_64 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_62, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_64}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_65 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_64, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_64}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_59 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_65, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_65}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_64 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_59, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_64}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_64 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_65, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_65}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_65 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_64, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_65}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_65 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_65, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_64}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_65 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_65, decoded_addr_decoded_decoded_andMatrixOutputs_lo_65}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_100_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_65; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_14 = decoded_addr_decoded_decoded_andMatrixOutputs_100_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_53 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_63, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_60}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_65 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_53, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_53}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_63 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_65, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_65}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_65 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_63, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_65}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_66 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_65, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_65}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_60 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_66, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_66}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_65 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_60, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_65}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_65 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_66, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_66}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_66 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_65, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_66}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_66 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_66, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_65}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_66 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_66, decoded_addr_decoded_decoded_andMatrixOutputs_lo_66}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_111_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_66; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_13 = decoded_addr_decoded_decoded_andMatrixOutputs_111_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_54 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_64, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_61}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_66 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_54, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_54}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_64 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_66, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_66}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_66 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_64, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_66}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_67 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_66, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_66}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_61 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_67, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_67}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_66 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_61, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_66}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_66 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_67, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_67}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_67 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_66, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_67}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_67 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_67, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_66}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_67 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_67, decoded_addr_decoded_decoded_andMatrixOutputs_lo_67}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_93_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_67; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_12 = decoded_addr_decoded_decoded_andMatrixOutputs_93_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_55 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_65, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_62}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_67 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_55, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_55}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_65 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_67, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_67}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_67 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_65, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_67}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_68 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_67, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_67}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_62 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_68, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_68}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_67 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_62, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_67}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_67 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_68, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_68}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_68 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_67, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_68}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_68 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_68, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_67}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_68 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_68, decoded_addr_decoded_decoded_andMatrixOutputs_lo_68}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_137_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_68; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_11 = decoded_addr_decoded_decoded_andMatrixOutputs_137_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_56 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_66, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_63}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_68 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_56, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_56}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_66 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_68, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_68}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_68 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_66, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_68}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_69 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_68, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_68}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_63 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_69, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_69}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_68 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_63, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_68}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_68 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_69, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_69}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_69 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_68, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_69}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_69 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_69, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_68}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_69 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_69, decoded_addr_decoded_decoded_andMatrixOutputs_lo_69}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_72_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_69; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_10 = decoded_addr_decoded_decoded_andMatrixOutputs_72_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_57 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_67, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_64}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_69 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_57, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_57}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_67 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_69, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_69}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_69 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_67, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_69}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_70 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_69, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_69}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_64 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_70, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_70}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_69 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_64, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_69}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_69 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_70, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_70}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_70 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_69, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_70}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_70 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_70, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_69}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_70 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_70, decoded_addr_decoded_decoded_andMatrixOutputs_lo_70}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_42_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_70; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_9 = decoded_addr_decoded_decoded_andMatrixOutputs_42_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_58 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_68, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_65}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_70 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_58, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_58}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_68 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_70, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_70}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_70 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_68, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_70}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_71 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_70, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_70}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_65 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_71, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_71}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_70 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_65, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_70}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_70 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_71, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_71}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_71 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_70, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_71}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_71 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_71, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_70}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_71 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_71, decoded_addr_decoded_decoded_andMatrixOutputs_lo_71}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_145_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_71; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_8 = decoded_addr_decoded_decoded_andMatrixOutputs_145_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_59 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_69, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_66}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_71 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_59, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_59}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_69 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_71, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_71}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_71 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_69, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_71}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_72 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_71, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_71}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_66 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_72, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_72}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_71 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_66, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_71}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_71 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_72, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_72}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_72 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_71, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_72}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_72 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_72, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_71}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_72 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_72, decoded_addr_decoded_decoded_andMatrixOutputs_lo_72}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_98_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_72; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_7 = decoded_addr_decoded_decoded_andMatrixOutputs_98_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_60 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_70, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_67}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_72 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_60, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_60}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_70 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_72, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_72}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_72 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_70, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_72}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_73 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_72, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_72}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_67 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_73, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_73}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_72 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_67, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_72}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_72 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_73, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_73}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_73 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_72, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_73}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_73 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_73, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_72}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_73 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_73, decoded_addr_decoded_decoded_andMatrixOutputs_lo_73}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_113_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_73; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_6 = decoded_addr_decoded_decoded_andMatrixOutputs_113_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_61 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_71, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_68}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_73 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_61, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_61}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_71 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_73, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_73}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_73 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_71, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_73}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_74 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_73, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_73}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_68 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_74, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_74}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_73 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_68, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_73}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_73 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_74, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_74}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_74 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_73, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_74}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_74 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_74, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_73}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_74 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_74, decoded_addr_decoded_decoded_andMatrixOutputs_lo_74}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_149_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_74; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_5 = decoded_addr_decoded_decoded_andMatrixOutputs_149_2; // @[pla.scala:98:70, :114:36]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_69 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_70 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_71 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_72 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_73 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_74 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_78 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_82 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_110 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_108 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_109 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_110 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_111 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_112 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_113 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_114 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_115 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_116 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_117 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_118 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_119 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_120 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_121 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_122 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_123 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_124 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_125 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_126 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_127 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_128 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_129 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_130 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_131 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_132 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_133 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_134 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_135 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_136 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_137 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_141 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_139 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_140 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_141 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_142 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_62 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_72, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_69}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_74 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_62, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_62}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_72 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_74, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_74}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_74 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_72, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_74}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_75 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_74, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_74}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_69 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_75, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_75}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_74 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_69, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_74}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_74 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_75, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_75}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_75 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_74, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_75}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_75 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_75, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_74}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_75 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_75, decoded_addr_decoded_decoded_andMatrixOutputs_lo_75}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_2_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_75; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_149 = decoded_addr_decoded_decoded_andMatrixOutputs_2_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_63 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_73, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_70}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_75 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_63, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_63}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_73 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_75, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_75}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_75 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_73, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_75}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_76 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_75, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_75}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_70 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_76, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_76}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_75 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_70, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_75}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_75 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_76, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_76}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_76 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_75, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_76}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_76 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_76, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_75}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_76 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_76, decoded_addr_decoded_decoded_andMatrixOutputs_lo_76}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_146_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_76; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_148 = decoded_addr_decoded_decoded_andMatrixOutputs_146_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_64 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_74, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_71}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_76 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_64, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_64}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_74 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_76, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_76}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_76 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_74, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_76}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_77 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_76, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_76}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_71 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_77, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_77}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_76 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_71, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_76}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_76 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_77, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_77}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_77 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_76, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_77}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_77 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_77, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_76}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_77 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_77, decoded_addr_decoded_decoded_andMatrixOutputs_lo_77}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_128_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_77; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_147 = decoded_addr_decoded_decoded_andMatrixOutputs_128_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_65 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_75, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_72}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_77 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_65, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_65}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_75 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_77, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_77}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_77 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_75, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_77}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_78 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_77, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_77}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_72 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_78, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_78}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_77 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_72, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_77}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_77 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_78, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_78}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_78 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_77, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_78}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_78 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_78, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_77}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_78 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_78, decoded_addr_decoded_decoded_andMatrixOutputs_lo_78}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_56_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_78; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_146 = decoded_addr_decoded_decoded_andMatrixOutputs_56_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_66 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_76, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_73}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_78 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_66, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_66}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_76 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_78, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_78}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_78 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_76, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_78}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_79 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_78, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_78}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_73 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_79, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_79}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_78 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_73, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_78}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_78 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_79, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_79}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_79 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_78, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_79}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_79 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_79, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_78}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_79 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_79, decoded_addr_decoded_decoded_andMatrixOutputs_lo_79}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_3_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_79; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_135 = decoded_addr_decoded_decoded_andMatrixOutputs_3_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_67 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_77, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_74}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_79 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_67, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_67}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_77 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_79, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_79}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_79 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_77, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_79}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_80 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_79, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_79}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_74 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_80, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_80}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_79 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_74, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_79}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_79 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_80, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_80}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_80 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_79, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_80}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_80 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_80, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_79}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_80 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_80, decoded_addr_decoded_decoded_andMatrixOutputs_lo_80}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_50_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_80; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_134 = decoded_addr_decoded_decoded_andMatrixOutputs_50_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_80 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_78, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_75}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_78 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_80, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_80}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_80 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_78, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_80}; // @[pla.scala:90:45, :98:53]
wire [4:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_81 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_80, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_80}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_75 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_81, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_81}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_80 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_75, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_80}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_80 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_81, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_81}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_81 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_80, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_81}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_81 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_81, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_80}; // @[pla.scala:98:53]
wire [10:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_81 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_81, decoded_addr_decoded_decoded_andMatrixOutputs_lo_81}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_23_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_81; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_133 = decoded_addr_decoded_decoded_andMatrixOutputs_23_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_81 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_82, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_82}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_82 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_81, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_81}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_82 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_82, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_82}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_82 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_82, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_82}; // @[pla.scala:90:45, :98:53]
wire [5:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_82 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_82, decoded_addr_decoded_decoded_andMatrixOutputs_lo_82}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_12_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_82; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_4 = decoded_addr_decoded_decoded_andMatrixOutputs_12_2; // @[pla.scala:98:70, :114:36]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_76 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_68 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_69 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_70 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_71 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_72 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_73 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_74 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_75 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_76 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_77 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_78 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_79 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_80 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_81 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_82 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_83 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_84 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_85 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_86 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_87 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_88 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_89 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_90 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_91 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_92 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_93 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_94 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_95 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_96 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_97 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_107 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_98 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_99 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_100 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_101 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_102 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_103 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_104 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_105 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_106 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_107 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_108 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_109 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_110 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_111 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_112 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_113 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_114 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_115 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_116 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_117 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_118 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_119 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_120 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_121 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_122 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_123 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_124 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_125 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_126 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_127 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_138 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_128 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_129 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_130 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_131 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_81 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_79, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_76}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_79 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_81, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_81}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_82 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_79, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_81}; // @[pla.scala:90:45, :98:53]
wire [4:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_83 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_82, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_81}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_76 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_83, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_83}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_81 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_76, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_82}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_81 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_83, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_83}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_83 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_81, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_83}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_83 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_83, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_81}; // @[pla.scala:98:53]
wire [10:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_83 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_83, decoded_addr_decoded_decoded_andMatrixOutputs_lo_83}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_76_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_83; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_128 = decoded_addr_decoded_decoded_andMatrixOutputs_76_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_68 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_80, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_77}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_82 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_68, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_68}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_80 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_82, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_82}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_83 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_80, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_82}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_84 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_83, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_82}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_77 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_84, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_84}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_82 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_77, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_83}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_82 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_84, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_84}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_84 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_82, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_84}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_84 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_84, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_82}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_84 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_84, decoded_addr_decoded_decoded_andMatrixOutputs_lo_84}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_79_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_84; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_127 = decoded_addr_decoded_decoded_andMatrixOutputs_79_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_69 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_81, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_78}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_83 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_69, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_69}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_81 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_83, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_83}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_84 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_81, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_83}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_85 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_84, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_83}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_78 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_85, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_85}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_83 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_78, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_84}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_83 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_85, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_85}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_85 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_83, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_85}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_85 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_85, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_83}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_85 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_85, decoded_addr_decoded_decoded_andMatrixOutputs_lo_85}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_95_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_85; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_125 = decoded_addr_decoded_decoded_andMatrixOutputs_95_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_70 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_82, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_79}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_84 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_70, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_70}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_82 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_84, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_84}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_85 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_82, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_84}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_86 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_85, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_84}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_79 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_86, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_86}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_84 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_79, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_85}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_84 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_86, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_86}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_86 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_84, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_86}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_86 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_86, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_84}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_86 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_86, decoded_addr_decoded_decoded_andMatrixOutputs_lo_86}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_26_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_86; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_122 = decoded_addr_decoded_decoded_andMatrixOutputs_26_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_71 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_83, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_80}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_85 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_71, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_71}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_83 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_85, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_85}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_86 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_83, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_85}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_87 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_86, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_85}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_80 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_87, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_87}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_85 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_80, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_86}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_85 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_87, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_87}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_87 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_85, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_87}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_87 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_87, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_85}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_87 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_87, decoded_addr_decoded_decoded_andMatrixOutputs_lo_87}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_124_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_87; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_119 = decoded_addr_decoded_decoded_andMatrixOutputs_124_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_72 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_84, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_81}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_86 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_72, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_72}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_84 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_86, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_86}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_87 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_84, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_86}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_88 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_87, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_86}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_81 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_88, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_88}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_86 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_81, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_87}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_86 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_88, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_88}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_88 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_86, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_88}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_88 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_88, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_86}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_88 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_88, decoded_addr_decoded_decoded_andMatrixOutputs_lo_88}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_147_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_88; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_116 = decoded_addr_decoded_decoded_andMatrixOutputs_147_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_73 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_85, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_82}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_87 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_73, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_73}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_85 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_87, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_87}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_88 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_85, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_87}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_89 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_88, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_87}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_82 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_89, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_89}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_87 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_82, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_88}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_87 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_89, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_89}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_89 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_87, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_89}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_89 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_89, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_87}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_89 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_89, decoded_addr_decoded_decoded_andMatrixOutputs_lo_89}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_77_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_89; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_113 = decoded_addr_decoded_decoded_andMatrixOutputs_77_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_74 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_86, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_83}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_88 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_74, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_74}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_86 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_88, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_88}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_89 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_86, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_88}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_90 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_89, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_88}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_83 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_90, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_90}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_88 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_83, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_89}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_88 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_90, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_90}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_90 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_88, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_90}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_90 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_90, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_88}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_90 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_90, decoded_addr_decoded_decoded_andMatrixOutputs_lo_90}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_140_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_90; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_110 = decoded_addr_decoded_decoded_andMatrixOutputs_140_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_75 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_87, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_84}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_89 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_75, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_75}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_87 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_89, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_89}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_90 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_87, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_89}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_91 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_90, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_89}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_84 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_91, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_91}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_89 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_84, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_90}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_89 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_91, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_91}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_91 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_89, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_91}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_91 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_91, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_89}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_91 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_91, decoded_addr_decoded_decoded_andMatrixOutputs_lo_91}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_44_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_91; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_107 = decoded_addr_decoded_decoded_andMatrixOutputs_44_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_76 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_88, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_85}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_90 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_76, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_76}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_88 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_90, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_90}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_91 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_88, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_90}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_92 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_91, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_90}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_85 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_92, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_92}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_90 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_85, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_91}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_90 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_92, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_92}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_92 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_90, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_92}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_92 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_92, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_90}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_92 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_92, decoded_addr_decoded_decoded_andMatrixOutputs_lo_92}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_31_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_92; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_104 = decoded_addr_decoded_decoded_andMatrixOutputs_31_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_77 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_89, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_86}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_91 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_77, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_77}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_89 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_91, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_91}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_92 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_89, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_91}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_93 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_92, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_91}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_86 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_93, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_93}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_91 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_86, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_92}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_91 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_93, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_93}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_93 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_91, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_93}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_93 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_93, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_91}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_93 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_93, decoded_addr_decoded_decoded_andMatrixOutputs_lo_93}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_62_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_93; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_101 = decoded_addr_decoded_decoded_andMatrixOutputs_62_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_78 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_90, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_87}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_92 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_78, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_78}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_90 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_92, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_92}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_93 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_90, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_92}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_94 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_93, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_92}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_87 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_94, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_94}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_92 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_87, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_93}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_92 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_94, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_94}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_94 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_92, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_94}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_94 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_94, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_92}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_94 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_94, decoded_addr_decoded_decoded_andMatrixOutputs_lo_94}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_58_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_94; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_98 = decoded_addr_decoded_decoded_andMatrixOutputs_58_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_79 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_91, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_88}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_93 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_79, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_79}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_91 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_93, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_93}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_94 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_91, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_93}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_95 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_94, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_93}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_88 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_95, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_95}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_93 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_88, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_94}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_93 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_95, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_95}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_95 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_93, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_95}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_95 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_95, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_93}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_95 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_95, decoded_addr_decoded_decoded_andMatrixOutputs_lo_95}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_132_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_95; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_95 = decoded_addr_decoded_decoded_andMatrixOutputs_132_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_80 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_92, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_89}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_94 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_80, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_80}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_92 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_94, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_94}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_95 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_92, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_94}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_96 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_95, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_94}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_89 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_96, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_96}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_94 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_89, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_95}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_94 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_96, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_96}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_96 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_94, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_96}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_96 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_96, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_94}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_96 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_96, decoded_addr_decoded_decoded_andMatrixOutputs_lo_96}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_9_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_96; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_92 = decoded_addr_decoded_decoded_andMatrixOutputs_9_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_81 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_93, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_90}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_95 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_81, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_81}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_93 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_95, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_95}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_96 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_93, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_95}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_97 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_96, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_95}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_90 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_97, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_97}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_95 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_90, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_96}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_95 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_97, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_97}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_97 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_95, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_97}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_97 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_97, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_95}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_97 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_97, decoded_addr_decoded_decoded_andMatrixOutputs_lo_97}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_115_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_97; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_89 = decoded_addr_decoded_decoded_andMatrixOutputs_115_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_82 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_94, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_91}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_96 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_82, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_82}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_94 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_96, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_96}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_97 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_94, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_96}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_98 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_97, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_96}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_91 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_98, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_98}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_96 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_91, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_97}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_96 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_98, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_98}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_98 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_96, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_98}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_98 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_98, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_96}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_98 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_98, decoded_addr_decoded_decoded_andMatrixOutputs_lo_98}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_5_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_98; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_86 = decoded_addr_decoded_decoded_andMatrixOutputs_5_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_83 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_95, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_92}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_97 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_83, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_83}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_95 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_97, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_97}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_98 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_95, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_97}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_99 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_98, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_97}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_92 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_99, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_99}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_97 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_92, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_98}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_97 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_99, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_99}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_99 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_97, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_99}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_99 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_99, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_97}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_99 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_99, decoded_addr_decoded_decoded_andMatrixOutputs_lo_99}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_71_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_99; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_83 = decoded_addr_decoded_decoded_andMatrixOutputs_71_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_84 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_96, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_93}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_98 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_84, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_84}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_96 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_98, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_98}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_99 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_96, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_98}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_100 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_99, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_98}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_93 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_100, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_100}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_98 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_93, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_99}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_98 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_100, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_100}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_100 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_98, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_100}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_100 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_100, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_98}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_100 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_100, decoded_addr_decoded_decoded_andMatrixOutputs_lo_100}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_130_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_100; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_80 = decoded_addr_decoded_decoded_andMatrixOutputs_130_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_85 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_97, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_94}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_99 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_85, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_85}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_97 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_99, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_99}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_100 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_97, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_99}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_101 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_100, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_99}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_94 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_101, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_101}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_99 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_94, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_100}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_99 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_101, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_101}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_101 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_99, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_101}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_101 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_101, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_99}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_101 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_101, decoded_addr_decoded_decoded_andMatrixOutputs_lo_101}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_102_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_101; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_77 = decoded_addr_decoded_decoded_andMatrixOutputs_102_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_86 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_98, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_95}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_100 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_86, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_86}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_98 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_100, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_100}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_101 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_98, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_100}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_102 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_101, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_100}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_95 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_102, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_102}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_100 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_95, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_101}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_100 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_102, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_102}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_102 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_100, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_102}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_102 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_102, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_100}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_102 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_102, decoded_addr_decoded_decoded_andMatrixOutputs_lo_102}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_4_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_102; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_74 = decoded_addr_decoded_decoded_andMatrixOutputs_4_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_87 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_99, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_96}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_101 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_87, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_87}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_99 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_101, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_101}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_102 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_99, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_101}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_103 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_102, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_101}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_96 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_103, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_103}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_101 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_96, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_102}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_101 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_103, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_103}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_103 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_101, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_103}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_103 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_103, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_101}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_103 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_103, decoded_addr_decoded_decoded_andMatrixOutputs_lo_103}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_29_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_103; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_71 = decoded_addr_decoded_decoded_andMatrixOutputs_29_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_88 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_100, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_97}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_102 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_88, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_88}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_100 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_102, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_102}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_103 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_100, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_102}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_104 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_103, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_102}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_97 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_104, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_104}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_102 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_97, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_103}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_102 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_104, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_104}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_104 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_102, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_104}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_104 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_104, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_102}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_104 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_104, decoded_addr_decoded_decoded_andMatrixOutputs_lo_104}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_16_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_104; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_68 = decoded_addr_decoded_decoded_andMatrixOutputs_16_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_89 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_101, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_98}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_103 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_89, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_89}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_101 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_103, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_103}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_104 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_101, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_103}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_105 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_104, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_103}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_98 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_105, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_105}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_103 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_98, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_104}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_103 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_105, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_105}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_105 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_103, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_105}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_105 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_105, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_103}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_105 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_105, decoded_addr_decoded_decoded_andMatrixOutputs_lo_105}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_143_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_105; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_65 = decoded_addr_decoded_decoded_andMatrixOutputs_143_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_90 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_102, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_99}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_104 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_90, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_90}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_102 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_104, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_104}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_105 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_102, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_104}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_106 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_105, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_104}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_99 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_106, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_106}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_104 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_99, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_105}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_104 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_106, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_106}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_106 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_104, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_106}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_106 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_106, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_104}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_106 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_106, decoded_addr_decoded_decoded_andMatrixOutputs_lo_106}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_131_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_106; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_62 = decoded_addr_decoded_decoded_andMatrixOutputs_131_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_91 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_103, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_100}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_105 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_91, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_91}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_103 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_105, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_105}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_106 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_103, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_105}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_107 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_106, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_105}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_100 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_107, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_107}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_105 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_100, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_106}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_105 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_107, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_107}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_107 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_105, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_107}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_107 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_107, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_105}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_107 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_107, decoded_addr_decoded_decoded_andMatrixOutputs_lo_107}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_14_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_107; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_59 = decoded_addr_decoded_decoded_andMatrixOutputs_14_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_92 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_104, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_101}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_106 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_92, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_92}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_104 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_106, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_106}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_107 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_104, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_106}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_108 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_107, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_106}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_101 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_108, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_108}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_106 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_101, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_107}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_106 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_108, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_108}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_108 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_106, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_108}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_108 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_108, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_106}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_108 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_108, decoded_addr_decoded_decoded_andMatrixOutputs_lo_108}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_90_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_108; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_56 = decoded_addr_decoded_decoded_andMatrixOutputs_90_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_93 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_105, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_102}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_107 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_93, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_93}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_105 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_107, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_107}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_108 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_105, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_107}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_109 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_108, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_107}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_102 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_109, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_109}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_107 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_102, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_108}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_107 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_109, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_109}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_109 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_107, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_109}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_109 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_109, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_107}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_109 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_109, decoded_addr_decoded_decoded_andMatrixOutputs_lo_109}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_97_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_109; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_53 = decoded_addr_decoded_decoded_andMatrixOutputs_97_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_94 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_106, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_103}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_108 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_94, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_94}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_106 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_108, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_108}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_109 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_106, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_108}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_110 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_109, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_108}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_103 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_110, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_110}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_108 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_103, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_109}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_108 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_110, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_110}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_110 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_108, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_110}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_110 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_110, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_108}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_110 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_110, decoded_addr_decoded_decoded_andMatrixOutputs_lo_110}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_60_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_110; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_50 = decoded_addr_decoded_decoded_andMatrixOutputs_60_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_95 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_107, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_104}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_109 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_95, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_95}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_107 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_109, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_109}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_110 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_107, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_109}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_111 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_110, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_109}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_104 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_111, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_111}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_109 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_104, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_110}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_109 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_111, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_111}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_111 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_109, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_111}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_111 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_111, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_109}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_111 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_111, decoded_addr_decoded_decoded_andMatrixOutputs_lo_111}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_96_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_111; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_47 = decoded_addr_decoded_decoded_andMatrixOutputs_96_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_96 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_108, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_105}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_110 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_96, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_96}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_108 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_110, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_110}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_111 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_108, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_110}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_112 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_111, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_110}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_105 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_112, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_112}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_110 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_105, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_111}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_110 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_112, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_112}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_112 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_110, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_112}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_112 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_112, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_110}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_112 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_112, decoded_addr_decoded_decoded_andMatrixOutputs_lo_112}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_54_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_112; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_44 = decoded_addr_decoded_decoded_andMatrixOutputs_54_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_97 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_109, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_106}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_111 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_97, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_97}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_109 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_111, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_111}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_112 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_109, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_111}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_113 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_112, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_111}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_106 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_113, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_113}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_111 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_106, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_112}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_111 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_113, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_113}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_113 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_111, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_113}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_113 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_113, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_111}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_113 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_113, decoded_addr_decoded_decoded_andMatrixOutputs_lo_113}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_126_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_113; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_41 = decoded_addr_decoded_decoded_andMatrixOutputs_126_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_112 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_110, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_107}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_110 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_112, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_112}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_113 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_110, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_112}; // @[pla.scala:91:29, :98:53]
wire [4:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_114 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_113, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_112}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_107 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_114, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_114}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_112 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_107, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_113}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_112 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_114, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_114}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_114 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_112, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_114}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_114 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_114, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_112}; // @[pla.scala:98:53]
wire [10:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_114 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_114, decoded_addr_decoded_decoded_andMatrixOutputs_lo_114}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_49_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_114; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_38 = decoded_addr_decoded_decoded_andMatrixOutputs_49_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_98 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_111, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_108}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_113 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_98, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_98}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_111 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_113, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_113}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_114 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_111, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_113}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_115 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_114, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_113}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_108 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_115, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_115}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_113 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_108, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_114}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_113 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_115, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_115}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_115 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_113, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_115}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_115 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_115, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_113}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_115 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_115, decoded_addr_decoded_decoded_andMatrixOutputs_lo_115}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_52_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_115; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_37 = decoded_addr_decoded_decoded_andMatrixOutputs_52_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_99 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_112, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_109}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_114 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_99, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_99}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_112 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_114, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_114}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_115 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_112, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_114}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_116 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_115, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_114}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_109 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_116, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_116}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_114 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_109, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_115}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_114 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_116, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_116}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_116 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_114, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_116}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_116 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_116, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_114}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_116 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_116, decoded_addr_decoded_decoded_andMatrixOutputs_lo_116}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_20_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_116; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_124 = decoded_addr_decoded_decoded_andMatrixOutputs_20_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_100 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_113, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_110}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_115 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_100, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_100}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_113 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_115, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_115}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_116 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_113, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_115}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_117 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_116, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_115}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_110 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_117, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_117}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_115 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_110, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_116}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_115 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_117, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_117}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_117 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_115, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_117}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_117 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_117, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_115}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_117 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_117, decoded_addr_decoded_decoded_andMatrixOutputs_lo_117}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_107_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_117; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_121 = decoded_addr_decoded_decoded_andMatrixOutputs_107_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_101 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_114, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_111}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_116 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_101, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_101}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_114 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_116, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_116}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_117 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_114, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_116}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_118 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_117, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_116}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_111 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_118, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_118}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_116 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_111, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_117}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_116 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_118, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_118}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_118 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_116, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_118}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_118 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_118, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_116}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_118 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_118, decoded_addr_decoded_decoded_andMatrixOutputs_lo_118}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_6_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_118; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_118 = decoded_addr_decoded_decoded_andMatrixOutputs_6_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_102 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_115, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_112}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_117 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_102, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_102}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_115 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_117, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_117}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_118 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_115, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_117}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_119 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_118, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_117}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_112 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_119, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_119}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_117 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_112, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_118}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_117 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_119, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_119}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_119 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_117, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_119}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_119 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_119, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_117}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_119 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_119, decoded_addr_decoded_decoded_andMatrixOutputs_lo_119}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_21_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_119; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_115 = decoded_addr_decoded_decoded_andMatrixOutputs_21_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_103 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_116, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_113}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_118 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_103, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_103}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_116 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_118, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_118}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_119 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_116, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_118}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_120 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_119, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_118}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_113 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_120, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_120}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_118 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_113, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_119}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_118 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_120, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_120}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_120 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_118, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_120}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_120 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_120, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_118}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_120 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_120, decoded_addr_decoded_decoded_andMatrixOutputs_lo_120}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_30_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_120; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_112 = decoded_addr_decoded_decoded_andMatrixOutputs_30_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_104 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_117, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_114}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_119 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_104, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_104}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_117 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_119, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_119}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_120 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_117, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_119}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_121 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_120, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_119}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_114 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_121, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_121}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_119 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_114, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_120}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_119 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_121, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_121}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_121 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_119, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_121}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_121 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_121, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_119}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_121 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_121, decoded_addr_decoded_decoded_andMatrixOutputs_lo_121}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_127_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_121; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_109 = decoded_addr_decoded_decoded_andMatrixOutputs_127_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_105 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_118, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_115}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_120 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_105, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_105}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_118 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_120, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_120}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_121 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_118, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_120}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_122 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_121, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_120}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_115 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_122, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_122}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_120 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_115, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_121}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_120 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_122, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_122}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_122 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_120, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_122}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_122 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_122, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_120}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_122 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_122, decoded_addr_decoded_decoded_andMatrixOutputs_lo_122}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_35_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_122; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_106 = decoded_addr_decoded_decoded_andMatrixOutputs_35_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_106 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_119, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_116}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_121 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_106, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_106}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_119 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_121, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_121}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_122 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_119, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_121}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_123 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_122, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_121}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_116 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_123, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_123}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_121 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_116, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_122}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_121 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_123, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_123}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_123 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_121, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_123}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_123 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_123, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_121}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_123 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_123, decoded_addr_decoded_decoded_andMatrixOutputs_lo_123}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_73_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_123; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_103 = decoded_addr_decoded_decoded_andMatrixOutputs_73_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_107 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_120, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_117}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_122 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_107, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_107}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_120 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_122, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_122}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_123 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_120, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_122}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_124 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_123, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_122}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_117 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_124, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_124}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_122 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_117, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_123}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_122 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_124, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_124}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_124 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_122, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_124}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_124 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_124, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_122}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_124 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_124, decoded_addr_decoded_decoded_andMatrixOutputs_lo_124}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_53_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_124; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_100 = decoded_addr_decoded_decoded_andMatrixOutputs_53_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_108 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_121, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_118}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_123 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_108, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_108}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_121 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_123, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_123}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_124 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_121, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_123}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_125 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_124, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_123}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_118 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_125, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_125}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_123 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_118, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_124}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_123 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_125, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_125}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_125 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_123, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_125}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_125 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_125, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_123}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_125 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_125, decoded_addr_decoded_decoded_andMatrixOutputs_lo_125}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_135_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_125; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_97 = decoded_addr_decoded_decoded_andMatrixOutputs_135_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_109 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_122, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_119}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_124 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_109, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_109}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_122 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_124, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_124}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_125 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_122, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_124}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_126 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_125, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_124}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_119 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_126, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_126}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_124 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_119, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_125}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_124 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_126, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_126}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_126 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_124, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_126}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_126 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_126, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_124}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_126 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_126, decoded_addr_decoded_decoded_andMatrixOutputs_lo_126}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_37_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_126; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_94 = decoded_addr_decoded_decoded_andMatrixOutputs_37_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_110 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_123, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_120}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_125 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_110, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_110}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_123 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_125, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_125}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_126 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_123, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_125}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_127 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_126, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_125}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_120 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_127, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_127}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_125 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_120, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_126}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_125 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_127, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_127}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_127 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_125, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_127}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_127 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_127, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_125}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_127 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_127, decoded_addr_decoded_decoded_andMatrixOutputs_lo_127}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_25_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_127; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_91 = decoded_addr_decoded_decoded_andMatrixOutputs_25_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_111 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_124, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_121}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_126 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_111, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_111}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_124 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_126, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_126}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_127 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_124, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_126}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_128 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_127, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_126}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_121 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_128, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_128}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_126 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_121, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_127}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_126 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_128, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_128}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_128 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_126, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_128}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_128 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_128, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_126}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_128 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_128, decoded_addr_decoded_decoded_andMatrixOutputs_lo_128}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_64_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_128; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_88 = decoded_addr_decoded_decoded_andMatrixOutputs_64_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_112 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_125, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_122}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_127 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_112, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_112}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_125 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_127, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_127}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_128 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_125, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_127}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_129 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_128, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_127}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_122 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_129, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_129}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_127 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_122, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_128}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_127 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_129, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_129}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_129 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_127, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_129}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_129 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_129, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_127}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_129 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_129, decoded_addr_decoded_decoded_andMatrixOutputs_lo_129}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_19_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_129; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_85 = decoded_addr_decoded_decoded_andMatrixOutputs_19_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_113 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_126, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_123}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_128 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_113, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_113}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_126 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_128, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_128}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_129 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_126, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_128}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_130 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_129, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_128}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_123 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_130, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_130}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_128 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_123, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_129}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_128 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_130, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_130}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_130 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_128, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_130}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_130 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_130, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_128}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_130 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_130, decoded_addr_decoded_decoded_andMatrixOutputs_lo_130}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_112_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_130; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_82 = decoded_addr_decoded_decoded_andMatrixOutputs_112_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_114 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_127, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_124}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_129 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_114, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_114}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_127 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_129, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_129}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_130 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_127, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_129}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_131 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_130, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_129}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_124 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_131, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_131}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_129 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_124, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_130}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_129 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_131, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_131}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_131 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_129, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_131}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_131 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_131, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_129}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_131 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_131, decoded_addr_decoded_decoded_andMatrixOutputs_lo_131}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_108_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_131; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_79 = decoded_addr_decoded_decoded_andMatrixOutputs_108_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_115 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_128, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_125}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_130 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_115, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_115}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_128 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_130, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_130}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_131 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_128, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_130}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_132 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_131, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_130}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_125 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_132, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_132}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_130 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_125, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_131}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_130 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_132, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_132}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_132 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_130, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_132}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_132 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_132, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_130}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_132 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_132, decoded_addr_decoded_decoded_andMatrixOutputs_lo_132}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_148_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_132; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_76 = decoded_addr_decoded_decoded_andMatrixOutputs_148_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_116 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_129, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_126}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_131 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_116, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_116}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_129 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_131, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_131}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_132 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_129, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_131}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_133 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_132, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_131}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_126 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_133, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_133}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_131 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_126, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_132}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_131 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_133, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_133}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_133 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_131, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_133}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_133 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_133, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_131}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_133 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_133, decoded_addr_decoded_decoded_andMatrixOutputs_lo_133}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_69_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_133; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_73 = decoded_addr_decoded_decoded_andMatrixOutputs_69_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_117 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_130, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_127}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_132 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_117, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_117}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_130 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_132, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_132}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_133 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_130, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_132}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_134 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_133, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_132}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_127 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_134, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_134}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_132 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_127, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_133}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_132 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_134, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_134}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_134 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_132, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_134}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_134 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_134, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_132}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_134 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_134, decoded_addr_decoded_decoded_andMatrixOutputs_lo_134}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_103_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_134; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_70 = decoded_addr_decoded_decoded_andMatrixOutputs_103_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_118 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_131, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_128}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_133 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_118, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_118}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_131 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_133, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_133}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_134 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_131, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_133}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_135 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_134, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_133}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_128 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_135, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_135}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_133 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_128, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_134}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_133 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_135, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_135}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_135 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_133, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_135}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_135 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_135, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_133}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_135 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_135, decoded_addr_decoded_decoded_andMatrixOutputs_lo_135}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_99_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_135; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_67 = decoded_addr_decoded_decoded_andMatrixOutputs_99_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_119 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_132, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_129}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_134 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_119, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_119}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_132 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_134, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_134}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_135 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_132, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_134}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_136 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_135, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_134}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_129 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_136, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_136}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_134 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_129, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_135}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_134 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_136, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_136}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_136 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_134, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_136}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_136 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_136, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_134}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_136 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_136, decoded_addr_decoded_decoded_andMatrixOutputs_lo_136}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_125_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_136; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_64 = decoded_addr_decoded_decoded_andMatrixOutputs_125_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_120 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_133, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_130}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_135 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_120, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_120}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_133 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_135, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_135}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_136 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_133, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_135}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_137 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_136, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_135}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_130 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_137, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_137}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_135 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_130, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_136}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_135 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_137, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_137}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_137 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_135, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_137}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_137 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_137, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_135}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_137 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_137, decoded_addr_decoded_decoded_andMatrixOutputs_lo_137}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_117_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_137; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_61 = decoded_addr_decoded_decoded_andMatrixOutputs_117_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_121 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_134, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_131}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_136 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_121, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_121}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_134 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_136, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_136}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_137 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_134, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_136}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_138 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_137, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_136}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_131 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_138, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_138}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_136 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_131, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_137}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_136 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_138, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_138}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_138 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_136, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_138}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_138 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_138, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_136}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_138 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_138, decoded_addr_decoded_decoded_andMatrixOutputs_lo_138}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_46_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_138; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_58 = decoded_addr_decoded_decoded_andMatrixOutputs_46_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_122 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_135, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_132}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_137 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_122, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_122}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_135 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_137, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_137}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_138 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_135, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_137}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_139 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_138, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_137}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_132 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_139, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_139}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_137 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_132, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_138}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_137 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_139, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_139}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_139 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_137, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_139}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_139 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_139, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_137}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_139 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_139, decoded_addr_decoded_decoded_andMatrixOutputs_lo_139}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_15_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_139; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_55 = decoded_addr_decoded_decoded_andMatrixOutputs_15_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_123 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_136, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_133}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_138 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_123, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_123}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_136 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_138, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_138}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_139 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_136, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_138}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_140 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_139, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_138}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_133 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_140, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_140}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_138 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_133, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_139}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_138 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_140, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_140}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_140 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_138, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_140}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_140 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_140, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_138}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_140 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_140, decoded_addr_decoded_decoded_andMatrixOutputs_lo_140}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_51_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_140; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_52 = decoded_addr_decoded_decoded_andMatrixOutputs_51_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_124 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_137, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_134}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_139 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_124, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_124}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_137 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_139, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_139}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_140 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_137, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_139}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_141 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_140, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_139}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_134 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_141, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_141}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_139 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_134, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_140}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_139 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_141, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_141}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_141 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_139, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_141}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_141 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_141, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_139}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_141 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_141, decoded_addr_decoded_decoded_andMatrixOutputs_lo_141}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_43_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_141; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_49 = decoded_addr_decoded_decoded_andMatrixOutputs_43_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_125 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_138, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_135}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_140 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_125, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_125}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_138 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_140, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_140}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_141 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_138, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_140}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_142 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_141, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_140}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_135 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_142, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_142}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_140 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_135, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_141}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_140 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_142, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_142}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_142 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_140, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_142}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_142 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_142, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_140}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_142 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_142, decoded_addr_decoded_decoded_andMatrixOutputs_lo_142}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_70_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_142; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_46 = decoded_addr_decoded_decoded_andMatrixOutputs_70_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_126 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_139, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_136}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_141 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_126, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_126}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_139 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_141, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_141}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_142 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_139, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_141}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_143 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_142, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_141}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_136 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_143, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_143}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_141 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_136, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_142}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_141 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_143, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_143}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_143 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_141, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_143}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_143 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_143, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_141}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_143 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_143, decoded_addr_decoded_decoded_andMatrixOutputs_lo_143}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_78_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_143; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_43 = decoded_addr_decoded_decoded_andMatrixOutputs_78_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_127 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_140, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_137}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_142 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_127, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_127}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_140 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_142, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_142}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_143 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_140, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_142}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_144 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_143, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_142}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_137 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_144, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_144}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_142 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_137, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_143}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_142 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_144, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_144}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_144 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_142, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_144}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_144 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_144, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_142}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_144 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_144, decoded_addr_decoded_decoded_andMatrixOutputs_lo_144}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_110_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_144; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_40 = decoded_addr_decoded_decoded_andMatrixOutputs_110_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_143 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_141, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_138}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_141 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_143, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_143}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_144 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_141, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_143}; // @[pla.scala:90:45, :98:53]
wire [4:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_145 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_144, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_143}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_138 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_145, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_145}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_143 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_138, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_144}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_143 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_145, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_145}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_145 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_143, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_145}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_145 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_145, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_143}; // @[pla.scala:98:53]
wire [10:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_145 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_145, decoded_addr_decoded_decoded_andMatrixOutputs_lo_145}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_101_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_145; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_2 = decoded_addr_decoded_decoded_andMatrixOutputs_101_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_128 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_142, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_139}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_144 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_128, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_128}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_142 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_144, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_144}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_145 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_142, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_144}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_146 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_145, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_144}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_139 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_146, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_146}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_144 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_139, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_145}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_144 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_146, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_146}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_146 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_144, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_146}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_146 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_146, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_144}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_146 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_146, decoded_addr_decoded_decoded_andMatrixOutputs_lo_146}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_38_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_146; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_3 = decoded_addr_decoded_decoded_andMatrixOutputs_38_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_129 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_143, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_140}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_145 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_129, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_129}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_143 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_145, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_145}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_146 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_143, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_145}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_147 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_146, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_145}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_140 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_147, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_147}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_145 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_140, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_146}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_145 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_147, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_147}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_147 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_145, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_147}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_147 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_147, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_145}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_147 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_147, decoded_addr_decoded_decoded_andMatrixOutputs_lo_147}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_13_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_147; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_1 = decoded_addr_decoded_decoded_andMatrixOutputs_13_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_130 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_144, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_141}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_146 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_130, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_130}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_144 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_146, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_146}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_147 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_144, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_146}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_148 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_147, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_146}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_141 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_148, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_148}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_146 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_141, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_147}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_146 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_148, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_148}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_148 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_146, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_148}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_148 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_148, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_146}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_148 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_148, decoded_addr_decoded_decoded_andMatrixOutputs_lo_148}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_81_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_148; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_136 = decoded_addr_decoded_decoded_andMatrixOutputs_81_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_131 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_145, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_142}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_147 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_131, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_131}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_145 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_147, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_147}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_148 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_145, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_147}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_149 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_148, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_147}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_142 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_149, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_149}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_147 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_142, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_148}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_147 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_149, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_149}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_149 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_147, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_149}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_149 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_149, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_147}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_149 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_149, decoded_addr_decoded_decoded_andMatrixOutputs_lo_149}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_75_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_149; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T = decoded_addr_decoded_decoded_andMatrixOutputs_75_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_lo_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_1, _decoded_addr_decoded_decoded_orMatrixOutputs_T}; // @[pla.scala:102:36, :114:36]
wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_lo_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_3, _decoded_addr_decoded_decoded_orMatrixOutputs_T_2}; // @[pla.scala:102:36, :114:36]
wire [3:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_lo_lo}; // @[pla.scala:102:36]
wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_hi_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_5, _decoded_addr_decoded_decoded_orMatrixOutputs_T_4}; // @[pla.scala:102:36, :114:36]
wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_hi_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_8, _decoded_addr_decoded_decoded_orMatrixOutputs_T_7}; // @[pla.scala:102:36, :114:36]
wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_6}; // @[pla.scala:102:36, :114:36]
wire [4:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_hi_lo}; // @[pla.scala:102:36]
wire [8:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_lo}; // @[pla.scala:102:36]
wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_lo_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_10, _decoded_addr_decoded_decoded_orMatrixOutputs_T_9}; // @[pla.scala:102:36, :114:36]
wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_lo_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_12, _decoded_addr_decoded_decoded_orMatrixOutputs_T_11}; // @[pla.scala:102:36, :114:36]
wire [3:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_lo_lo}; // @[pla.scala:102:36]
wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_14, _decoded_addr_decoded_decoded_orMatrixOutputs_T_13}; // @[pla.scala:102:36, :114:36]
wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_17, _decoded_addr_decoded_decoded_orMatrixOutputs_T_16}; // @[pla.scala:102:36, :114:36]
wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_15}; // @[pla.scala:102:36, :114:36]
wire [4:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_lo}; // @[pla.scala:102:36]
wire [8:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_lo}; // @[pla.scala:102:36]
wire [17:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo}; // @[pla.scala:102:36]
wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_lo_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_19, _decoded_addr_decoded_decoded_orMatrixOutputs_T_18}; // @[pla.scala:102:36, :114:36]
wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_lo_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_21, _decoded_addr_decoded_decoded_orMatrixOutputs_T_20}; // @[pla.scala:102:36, :114:36]
wire [3:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_lo_lo}; // @[pla.scala:102:36]
wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_hi_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_23, _decoded_addr_decoded_decoded_orMatrixOutputs_T_22}; // @[pla.scala:102:36, :114:36]
wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_hi_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_26, _decoded_addr_decoded_decoded_orMatrixOutputs_T_25}; // @[pla.scala:102:36, :114:36]
wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_24}; // @[pla.scala:102:36, :114:36]
wire [4:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_hi_lo}; // @[pla.scala:102:36]
wire [8:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_lo}; // @[pla.scala:102:36]
wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_lo_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_28, _decoded_addr_decoded_decoded_orMatrixOutputs_T_27}; // @[pla.scala:102:36, :114:36]
wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_lo_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_31, _decoded_addr_decoded_decoded_orMatrixOutputs_T_30}; // @[pla.scala:102:36, :114:36]
wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_lo_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_lo_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_29}; // @[pla.scala:102:36, :114:36]
wire [4:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_lo_lo}; // @[pla.scala:102:36]
wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_33, _decoded_addr_decoded_decoded_orMatrixOutputs_T_32}; // @[pla.scala:102:36, :114:36]
wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_36, _decoded_addr_decoded_decoded_orMatrixOutputs_T_35}; // @[pla.scala:102:36, :114:36]
wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_34}; // @[pla.scala:102:36, :114:36]
wire [4:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_lo}; // @[pla.scala:102:36]
wire [9:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_lo}; // @[pla.scala:102:36]
wire [18:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo}; // @[pla.scala:102:36]
wire [36:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo}; // @[pla.scala:102:36]
wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_lo_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_38, _decoded_addr_decoded_decoded_orMatrixOutputs_T_37}; // @[pla.scala:102:36, :114:36]
wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_lo_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_40, _decoded_addr_decoded_decoded_orMatrixOutputs_T_39}; // @[pla.scala:102:36, :114:36]
wire [3:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_lo_lo}; // @[pla.scala:102:36]
wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_hi_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_42, _decoded_addr_decoded_decoded_orMatrixOutputs_T_41}; // @[pla.scala:102:36, :114:36]
wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_hi_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_45, _decoded_addr_decoded_decoded_orMatrixOutputs_T_44}; // @[pla.scala:102:36, :114:36]
wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_43}; // @[pla.scala:102:36, :114:36]
wire [4:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_hi_lo}; // @[pla.scala:102:36]
wire [8:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_lo}; // @[pla.scala:102:36]
wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_lo_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_47, _decoded_addr_decoded_decoded_orMatrixOutputs_T_46}; // @[pla.scala:102:36, :114:36]
wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_lo_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_50, _decoded_addr_decoded_decoded_orMatrixOutputs_T_49}; // @[pla.scala:102:36, :114:36]
wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_lo_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_lo_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_48}; // @[pla.scala:102:36, :114:36]
wire [4:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_lo_lo}; // @[pla.scala:102:36]
wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_52, _decoded_addr_decoded_decoded_orMatrixOutputs_T_51}; // @[pla.scala:102:36, :114:36]
wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_55, _decoded_addr_decoded_decoded_orMatrixOutputs_T_54}; // @[pla.scala:102:36, :114:36]
wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_53}; // @[pla.scala:102:36, :114:36]
wire [4:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_lo}; // @[pla.scala:102:36]
wire [9:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_lo}; // @[pla.scala:102:36]
wire [18:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo}; // @[pla.scala:102:36]
wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_lo_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_57, _decoded_addr_decoded_decoded_orMatrixOutputs_T_56}; // @[pla.scala:102:36, :114:36]
wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_lo_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_59, _decoded_addr_decoded_decoded_orMatrixOutputs_T_58}; // @[pla.scala:102:36, :114:36]
wire [3:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_lo_lo}; // @[pla.scala:102:36]
wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_61, _decoded_addr_decoded_decoded_orMatrixOutputs_T_60}; // @[pla.scala:102:36, :114:36]
wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_64, _decoded_addr_decoded_decoded_orMatrixOutputs_T_63}; // @[pla.scala:102:36, :114:36]
wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_62}; // @[pla.scala:102:36, :114:36]
wire [4:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_lo}; // @[pla.scala:102:36]
wire [8:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_lo}; // @[pla.scala:102:36]
wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_lo_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_66, _decoded_addr_decoded_decoded_orMatrixOutputs_T_65}; // @[pla.scala:102:36, :114:36]
wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_lo_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_69, _decoded_addr_decoded_decoded_orMatrixOutputs_T_68}; // @[pla.scala:102:36, :114:36]
wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_lo_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_lo_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_67}; // @[pla.scala:102:36, :114:36]
wire [4:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_lo_lo}; // @[pla.scala:102:36]
wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_71, _decoded_addr_decoded_decoded_orMatrixOutputs_T_70}; // @[pla.scala:102:36, :114:36]
wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_74, _decoded_addr_decoded_decoded_orMatrixOutputs_T_73}; // @[pla.scala:102:36, :114:36]
wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_72}; // @[pla.scala:102:36, :114:36]
wire [4:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_lo}; // @[pla.scala:102:36]
wire [9:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_lo}; // @[pla.scala:102:36]
wire [18:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo}; // @[pla.scala:102:36]
wire [37:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo}; // @[pla.scala:102:36]
wire [74:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo}; // @[pla.scala:102:36]
wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_lo_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_76, _decoded_addr_decoded_decoded_orMatrixOutputs_T_75}; // @[pla.scala:102:36, :114:36]
wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_lo_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_78, _decoded_addr_decoded_decoded_orMatrixOutputs_T_77}; // @[pla.scala:102:36, :114:36]
wire [3:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_lo_lo}; // @[pla.scala:102:36]
wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_hi_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_80, _decoded_addr_decoded_decoded_orMatrixOutputs_T_79}; // @[pla.scala:102:36, :114:36]
wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_hi_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_83, _decoded_addr_decoded_decoded_orMatrixOutputs_T_82}; // @[pla.scala:102:36, :114:36]
wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_81}; // @[pla.scala:102:36, :114:36]
wire [4:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_hi_lo}; // @[pla.scala:102:36]
wire [8:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_lo}; // @[pla.scala:102:36]
wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_lo_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_85, _decoded_addr_decoded_decoded_orMatrixOutputs_T_84}; // @[pla.scala:102:36, :114:36]
wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_lo_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_87, _decoded_addr_decoded_decoded_orMatrixOutputs_T_86}; // @[pla.scala:102:36, :114:36]
wire [3:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_lo_lo}; // @[pla.scala:102:36]
wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_89, _decoded_addr_decoded_decoded_orMatrixOutputs_T_88}; // @[pla.scala:102:36, :114:36]
wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_92, _decoded_addr_decoded_decoded_orMatrixOutputs_T_91}; // @[pla.scala:102:36, :114:36]
wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_90}; // @[pla.scala:102:36, :114:36]
wire [4:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_lo}; // @[pla.scala:102:36]
wire [8:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_lo}; // @[pla.scala:102:36]
wire [17:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo}; // @[pla.scala:102:36]
wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_lo_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_94, _decoded_addr_decoded_decoded_orMatrixOutputs_T_93}; // @[pla.scala:102:36, :114:36]
wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_lo_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_96, _decoded_addr_decoded_decoded_orMatrixOutputs_T_95}; // @[pla.scala:102:36, :114:36]
wire [3:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_lo_lo}; // @[pla.scala:102:36]
wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_98, _decoded_addr_decoded_decoded_orMatrixOutputs_T_97}; // @[pla.scala:102:36, :114:36]
wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_101, _decoded_addr_decoded_decoded_orMatrixOutputs_T_100}; // @[pla.scala:102:36, :114:36]
wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_99}; // @[pla.scala:102:36, :114:36]
wire [4:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_lo}; // @[pla.scala:102:36]
wire [8:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_lo}; // @[pla.scala:102:36]
wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_lo_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_103, _decoded_addr_decoded_decoded_orMatrixOutputs_T_102}; // @[pla.scala:102:36, :114:36]
wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_lo_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_106, _decoded_addr_decoded_decoded_orMatrixOutputs_T_105}; // @[pla.scala:102:36, :114:36]
wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_lo_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_lo_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_104}; // @[pla.scala:102:36, :114:36]
wire [4:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_lo_lo}; // @[pla.scala:102:36]
wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_108, _decoded_addr_decoded_decoded_orMatrixOutputs_T_107}; // @[pla.scala:102:36, :114:36]
wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_111, _decoded_addr_decoded_decoded_orMatrixOutputs_T_110}; // @[pla.scala:102:36, :114:36]
wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_109}; // @[pla.scala:102:36, :114:36]
wire [4:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_lo}; // @[pla.scala:102:36]
wire [9:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_lo}; // @[pla.scala:102:36]
wire [18:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo}; // @[pla.scala:102:36]
wire [36:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo}; // @[pla.scala:102:36]
wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_lo_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_113, _decoded_addr_decoded_decoded_orMatrixOutputs_T_112}; // @[pla.scala:102:36, :114:36]
wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_lo_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_115, _decoded_addr_decoded_decoded_orMatrixOutputs_T_114}; // @[pla.scala:102:36, :114:36]
wire [3:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_lo_lo}; // @[pla.scala:102:36]
wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_hi_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_117, _decoded_addr_decoded_decoded_orMatrixOutputs_T_116}; // @[pla.scala:102:36, :114:36]
wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_hi_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_120, _decoded_addr_decoded_decoded_orMatrixOutputs_T_119}; // @[pla.scala:102:36, :114:36]
wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_118}; // @[pla.scala:102:36, :114:36]
wire [4:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_hi_lo}; // @[pla.scala:102:36]
wire [8:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_lo}; // @[pla.scala:102:36]
wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_lo_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_122, _decoded_addr_decoded_decoded_orMatrixOutputs_T_121}; // @[pla.scala:102:36, :114:36]
wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_lo_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_125, _decoded_addr_decoded_decoded_orMatrixOutputs_T_124}; // @[pla.scala:102:36, :114:36]
wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_lo_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_lo_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_123}; // @[pla.scala:102:36, :114:36]
wire [4:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_lo_lo}; // @[pla.scala:102:36]
wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_127, _decoded_addr_decoded_decoded_orMatrixOutputs_T_126}; // @[pla.scala:102:36, :114:36]
wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_130, _decoded_addr_decoded_decoded_orMatrixOutputs_T_129}; // @[pla.scala:102:36, :114:36]
wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_128}; // @[pla.scala:102:36, :114:36]
wire [4:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_lo}; // @[pla.scala:102:36]
wire [9:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_lo}; // @[pla.scala:102:36]
wire [18:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo}; // @[pla.scala:102:36]
wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_lo_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_132, _decoded_addr_decoded_decoded_orMatrixOutputs_T_131}; // @[pla.scala:102:36, :114:36]
wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_lo_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_134, _decoded_addr_decoded_decoded_orMatrixOutputs_T_133}; // @[pla.scala:102:36, :114:36]
wire [3:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_lo_lo}; // @[pla.scala:102:36]
wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_136, _decoded_addr_decoded_decoded_orMatrixOutputs_T_135}; // @[pla.scala:102:36, :114:36]
wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_139, _decoded_addr_decoded_decoded_orMatrixOutputs_T_138}; // @[pla.scala:102:36, :114:36]
wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_137}; // @[pla.scala:102:36, :114:36]
wire [4:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_lo}; // @[pla.scala:102:36]
wire [8:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_lo}; // @[pla.scala:102:36]
wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_lo_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_141, _decoded_addr_decoded_decoded_orMatrixOutputs_T_140}; // @[pla.scala:102:36, :114:36]
wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_lo_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_144, _decoded_addr_decoded_decoded_orMatrixOutputs_T_143}; // @[pla.scala:102:36, :114:36]
wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_lo_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_lo_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_142}; // @[pla.scala:102:36, :114:36]
wire [4:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_lo_lo}; // @[pla.scala:102:36]
wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_146, _decoded_addr_decoded_decoded_orMatrixOutputs_T_145}; // @[pla.scala:102:36, :114:36]
wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_149, _decoded_addr_decoded_decoded_orMatrixOutputs_T_148}; // @[pla.scala:102:36, :114:36]
wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_147}; // @[pla.scala:102:36, :114:36]
wire [4:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_lo}; // @[pla.scala:102:36]
wire [9:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_lo}; // @[pla.scala:102:36]
wire [18:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo}; // @[pla.scala:102:36]
wire [37:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo}; // @[pla.scala:102:36]
wire [74:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo}; // @[pla.scala:102:36]
wire [149:0] decoded_addr_decoded_decoded_orMatrixOutputs = {decoded_addr_decoded_decoded_orMatrixOutputs_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo}; // @[pla.scala:102:36]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T = decoded_addr_decoded_decoded_orMatrixOutputs[0]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_1 = decoded_addr_decoded_decoded_orMatrixOutputs[1]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_2 = decoded_addr_decoded_decoded_orMatrixOutputs[2]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_3 = decoded_addr_decoded_decoded_orMatrixOutputs[3]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_4 = decoded_addr_decoded_decoded_orMatrixOutputs[4]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_5 = decoded_addr_decoded_decoded_orMatrixOutputs[5]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_6 = decoded_addr_decoded_decoded_orMatrixOutputs[6]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_7 = decoded_addr_decoded_decoded_orMatrixOutputs[7]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_8 = decoded_addr_decoded_decoded_orMatrixOutputs[8]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_9 = decoded_addr_decoded_decoded_orMatrixOutputs[9]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_10 = decoded_addr_decoded_decoded_orMatrixOutputs[10]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_11 = decoded_addr_decoded_decoded_orMatrixOutputs[11]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_12 = decoded_addr_decoded_decoded_orMatrixOutputs[12]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_13 = decoded_addr_decoded_decoded_orMatrixOutputs[13]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_14 = decoded_addr_decoded_decoded_orMatrixOutputs[14]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_15 = decoded_addr_decoded_decoded_orMatrixOutputs[15]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_16 = decoded_addr_decoded_decoded_orMatrixOutputs[16]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_17 = decoded_addr_decoded_decoded_orMatrixOutputs[17]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_18 = decoded_addr_decoded_decoded_orMatrixOutputs[18]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_19 = decoded_addr_decoded_decoded_orMatrixOutputs[19]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_20 = decoded_addr_decoded_decoded_orMatrixOutputs[20]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_21 = decoded_addr_decoded_decoded_orMatrixOutputs[21]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_22 = decoded_addr_decoded_decoded_orMatrixOutputs[22]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_23 = decoded_addr_decoded_decoded_orMatrixOutputs[23]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_24 = decoded_addr_decoded_decoded_orMatrixOutputs[24]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_25 = decoded_addr_decoded_decoded_orMatrixOutputs[25]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_26 = decoded_addr_decoded_decoded_orMatrixOutputs[26]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_27 = decoded_addr_decoded_decoded_orMatrixOutputs[27]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_28 = decoded_addr_decoded_decoded_orMatrixOutputs[28]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_29 = decoded_addr_decoded_decoded_orMatrixOutputs[29]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_30 = decoded_addr_decoded_decoded_orMatrixOutputs[30]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_31 = decoded_addr_decoded_decoded_orMatrixOutputs[31]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_32 = decoded_addr_decoded_decoded_orMatrixOutputs[32]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_33 = decoded_addr_decoded_decoded_orMatrixOutputs[33]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_34 = decoded_addr_decoded_decoded_orMatrixOutputs[34]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_35 = decoded_addr_decoded_decoded_orMatrixOutputs[35]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_36 = decoded_addr_decoded_decoded_orMatrixOutputs[36]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_37 = decoded_addr_decoded_decoded_orMatrixOutputs[37]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_38 = decoded_addr_decoded_decoded_orMatrixOutputs[38]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_39 = decoded_addr_decoded_decoded_orMatrixOutputs[39]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_40 = decoded_addr_decoded_decoded_orMatrixOutputs[40]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_41 = decoded_addr_decoded_decoded_orMatrixOutputs[41]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_42 = decoded_addr_decoded_decoded_orMatrixOutputs[42]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_43 = decoded_addr_decoded_decoded_orMatrixOutputs[43]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_44 = decoded_addr_decoded_decoded_orMatrixOutputs[44]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_45 = decoded_addr_decoded_decoded_orMatrixOutputs[45]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_46 = decoded_addr_decoded_decoded_orMatrixOutputs[46]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_47 = decoded_addr_decoded_decoded_orMatrixOutputs[47]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_48 = decoded_addr_decoded_decoded_orMatrixOutputs[48]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_49 = decoded_addr_decoded_decoded_orMatrixOutputs[49]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_50 = decoded_addr_decoded_decoded_orMatrixOutputs[50]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_51 = decoded_addr_decoded_decoded_orMatrixOutputs[51]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_52 = decoded_addr_decoded_decoded_orMatrixOutputs[52]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_53 = decoded_addr_decoded_decoded_orMatrixOutputs[53]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_54 = decoded_addr_decoded_decoded_orMatrixOutputs[54]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_55 = decoded_addr_decoded_decoded_orMatrixOutputs[55]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_56 = decoded_addr_decoded_decoded_orMatrixOutputs[56]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_57 = decoded_addr_decoded_decoded_orMatrixOutputs[57]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_58 = decoded_addr_decoded_decoded_orMatrixOutputs[58]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_59 = decoded_addr_decoded_decoded_orMatrixOutputs[59]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_60 = decoded_addr_decoded_decoded_orMatrixOutputs[60]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_61 = decoded_addr_decoded_decoded_orMatrixOutputs[61]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_62 = decoded_addr_decoded_decoded_orMatrixOutputs[62]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_63 = decoded_addr_decoded_decoded_orMatrixOutputs[63]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_64 = decoded_addr_decoded_decoded_orMatrixOutputs[64]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_65 = decoded_addr_decoded_decoded_orMatrixOutputs[65]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_66 = decoded_addr_decoded_decoded_orMatrixOutputs[66]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_67 = decoded_addr_decoded_decoded_orMatrixOutputs[67]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_68 = decoded_addr_decoded_decoded_orMatrixOutputs[68]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_69 = decoded_addr_decoded_decoded_orMatrixOutputs[69]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_70 = decoded_addr_decoded_decoded_orMatrixOutputs[70]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_71 = decoded_addr_decoded_decoded_orMatrixOutputs[71]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_72 = decoded_addr_decoded_decoded_orMatrixOutputs[72]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_73 = decoded_addr_decoded_decoded_orMatrixOutputs[73]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_74 = decoded_addr_decoded_decoded_orMatrixOutputs[74]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_75 = decoded_addr_decoded_decoded_orMatrixOutputs[75]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_76 = decoded_addr_decoded_decoded_orMatrixOutputs[76]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_77 = decoded_addr_decoded_decoded_orMatrixOutputs[77]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_78 = decoded_addr_decoded_decoded_orMatrixOutputs[78]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_79 = decoded_addr_decoded_decoded_orMatrixOutputs[79]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_80 = decoded_addr_decoded_decoded_orMatrixOutputs[80]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_81 = decoded_addr_decoded_decoded_orMatrixOutputs[81]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_82 = decoded_addr_decoded_decoded_orMatrixOutputs[82]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_83 = decoded_addr_decoded_decoded_orMatrixOutputs[83]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_84 = decoded_addr_decoded_decoded_orMatrixOutputs[84]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_85 = decoded_addr_decoded_decoded_orMatrixOutputs[85]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_86 = decoded_addr_decoded_decoded_orMatrixOutputs[86]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_87 = decoded_addr_decoded_decoded_orMatrixOutputs[87]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_88 = decoded_addr_decoded_decoded_orMatrixOutputs[88]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_89 = decoded_addr_decoded_decoded_orMatrixOutputs[89]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_90 = decoded_addr_decoded_decoded_orMatrixOutputs[90]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_91 = decoded_addr_decoded_decoded_orMatrixOutputs[91]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_92 = decoded_addr_decoded_decoded_orMatrixOutputs[92]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_93 = decoded_addr_decoded_decoded_orMatrixOutputs[93]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_94 = decoded_addr_decoded_decoded_orMatrixOutputs[94]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_95 = decoded_addr_decoded_decoded_orMatrixOutputs[95]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_96 = decoded_addr_decoded_decoded_orMatrixOutputs[96]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_97 = decoded_addr_decoded_decoded_orMatrixOutputs[97]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_98 = decoded_addr_decoded_decoded_orMatrixOutputs[98]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_99 = decoded_addr_decoded_decoded_orMatrixOutputs[99]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_100 = decoded_addr_decoded_decoded_orMatrixOutputs[100]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_101 = decoded_addr_decoded_decoded_orMatrixOutputs[101]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_102 = decoded_addr_decoded_decoded_orMatrixOutputs[102]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_103 = decoded_addr_decoded_decoded_orMatrixOutputs[103]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_104 = decoded_addr_decoded_decoded_orMatrixOutputs[104]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_105 = decoded_addr_decoded_decoded_orMatrixOutputs[105]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_106 = decoded_addr_decoded_decoded_orMatrixOutputs[106]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_107 = decoded_addr_decoded_decoded_orMatrixOutputs[107]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_108 = decoded_addr_decoded_decoded_orMatrixOutputs[108]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_109 = decoded_addr_decoded_decoded_orMatrixOutputs[109]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_110 = decoded_addr_decoded_decoded_orMatrixOutputs[110]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_111 = decoded_addr_decoded_decoded_orMatrixOutputs[111]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_112 = decoded_addr_decoded_decoded_orMatrixOutputs[112]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_113 = decoded_addr_decoded_decoded_orMatrixOutputs[113]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_114 = decoded_addr_decoded_decoded_orMatrixOutputs[114]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_115 = decoded_addr_decoded_decoded_orMatrixOutputs[115]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_116 = decoded_addr_decoded_decoded_orMatrixOutputs[116]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_117 = decoded_addr_decoded_decoded_orMatrixOutputs[117]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_118 = decoded_addr_decoded_decoded_orMatrixOutputs[118]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_119 = decoded_addr_decoded_decoded_orMatrixOutputs[119]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_120 = decoded_addr_decoded_decoded_orMatrixOutputs[120]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_121 = decoded_addr_decoded_decoded_orMatrixOutputs[121]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_122 = decoded_addr_decoded_decoded_orMatrixOutputs[122]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_123 = decoded_addr_decoded_decoded_orMatrixOutputs[123]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_124 = decoded_addr_decoded_decoded_orMatrixOutputs[124]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_125 = decoded_addr_decoded_decoded_orMatrixOutputs[125]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_126 = decoded_addr_decoded_decoded_orMatrixOutputs[126]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_127 = decoded_addr_decoded_decoded_orMatrixOutputs[127]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_128 = decoded_addr_decoded_decoded_orMatrixOutputs[128]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_129 = decoded_addr_decoded_decoded_orMatrixOutputs[129]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_130 = decoded_addr_decoded_decoded_orMatrixOutputs[130]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_131 = decoded_addr_decoded_decoded_orMatrixOutputs[131]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_132 = decoded_addr_decoded_decoded_orMatrixOutputs[132]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_133 = decoded_addr_decoded_decoded_orMatrixOutputs[133]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_134 = decoded_addr_decoded_decoded_orMatrixOutputs[134]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_135 = decoded_addr_decoded_decoded_orMatrixOutputs[135]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_136 = decoded_addr_decoded_decoded_orMatrixOutputs[136]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_137 = decoded_addr_decoded_decoded_orMatrixOutputs[137]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_138 = decoded_addr_decoded_decoded_orMatrixOutputs[138]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_139 = decoded_addr_decoded_decoded_orMatrixOutputs[139]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_140 = decoded_addr_decoded_decoded_orMatrixOutputs[140]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_141 = decoded_addr_decoded_decoded_orMatrixOutputs[141]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_142 = decoded_addr_decoded_decoded_orMatrixOutputs[142]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_143 = decoded_addr_decoded_decoded_orMatrixOutputs[143]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_144 = decoded_addr_decoded_decoded_orMatrixOutputs[144]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_145 = decoded_addr_decoded_decoded_orMatrixOutputs[145]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_146 = decoded_addr_decoded_decoded_orMatrixOutputs[146]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_147 = decoded_addr_decoded_decoded_orMatrixOutputs[147]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_148 = decoded_addr_decoded_decoded_orMatrixOutputs[148]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_149 = decoded_addr_decoded_decoded_orMatrixOutputs[149]; // @[pla.scala:102:36, :124:31]
wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_lo_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_1, _decoded_addr_decoded_decoded_invMatrixOutputs_T}; // @[pla.scala:120:37, :124:31]
wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_lo_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_3, _decoded_addr_decoded_decoded_invMatrixOutputs_T_2}; // @[pla.scala:120:37, :124:31]
wire [3:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_lo_lo}; // @[pla.scala:120:37]
wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_hi_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_5, _decoded_addr_decoded_decoded_invMatrixOutputs_T_4}; // @[pla.scala:120:37, :124:31]
wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_hi_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_8, _decoded_addr_decoded_decoded_invMatrixOutputs_T_7}; // @[pla.scala:120:37, :124:31]
wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_6}; // @[pla.scala:120:37, :124:31]
wire [4:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_hi_lo}; // @[pla.scala:120:37]
wire [8:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_lo}; // @[pla.scala:120:37]
wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_lo_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_10, _decoded_addr_decoded_decoded_invMatrixOutputs_T_9}; // @[pla.scala:120:37, :124:31]
wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_lo_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_12, _decoded_addr_decoded_decoded_invMatrixOutputs_T_11}; // @[pla.scala:120:37, :124:31]
wire [3:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_lo_lo}; // @[pla.scala:120:37]
wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_hi_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_14, _decoded_addr_decoded_decoded_invMatrixOutputs_T_13}; // @[pla.scala:120:37, :124:31]
wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_hi_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_17, _decoded_addr_decoded_decoded_invMatrixOutputs_T_16}; // @[pla.scala:120:37, :124:31]
wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_15}; // @[pla.scala:120:37, :124:31]
wire [4:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_hi_lo}; // @[pla.scala:120:37]
wire [8:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_lo}; // @[pla.scala:120:37]
wire [17:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo}; // @[pla.scala:120:37]
wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_lo_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_19, _decoded_addr_decoded_decoded_invMatrixOutputs_T_18}; // @[pla.scala:120:37, :124:31]
wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_lo_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_21, _decoded_addr_decoded_decoded_invMatrixOutputs_T_20}; // @[pla.scala:120:37, :124:31]
wire [3:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_lo_lo}; // @[pla.scala:120:37]
wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_hi_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_23, _decoded_addr_decoded_decoded_invMatrixOutputs_T_22}; // @[pla.scala:120:37, :124:31]
wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_hi_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_26, _decoded_addr_decoded_decoded_invMatrixOutputs_T_25}; // @[pla.scala:120:37, :124:31]
wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_24}; // @[pla.scala:120:37, :124:31]
wire [4:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_hi_lo}; // @[pla.scala:120:37]
wire [8:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_lo}; // @[pla.scala:120:37]
wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_lo_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_28, _decoded_addr_decoded_decoded_invMatrixOutputs_T_27}; // @[pla.scala:120:37, :124:31]
wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_lo_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_31, _decoded_addr_decoded_decoded_invMatrixOutputs_T_30}; // @[pla.scala:120:37, :124:31]
wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_lo_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_lo_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_29}; // @[pla.scala:120:37, :124:31]
wire [4:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_lo_lo}; // @[pla.scala:120:37]
wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_hi_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_33, _decoded_addr_decoded_decoded_invMatrixOutputs_T_32}; // @[pla.scala:120:37, :124:31]
wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_hi_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_36, _decoded_addr_decoded_decoded_invMatrixOutputs_T_35}; // @[pla.scala:120:37, :124:31]
wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_34}; // @[pla.scala:120:37, :124:31]
wire [4:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_hi_lo}; // @[pla.scala:120:37]
wire [9:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_lo}; // @[pla.scala:120:37]
wire [18:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo}; // @[pla.scala:120:37]
wire [36:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo}; // @[pla.scala:120:37]
wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_lo_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_38, _decoded_addr_decoded_decoded_invMatrixOutputs_T_37}; // @[pla.scala:120:37, :124:31]
wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_lo_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_40, _decoded_addr_decoded_decoded_invMatrixOutputs_T_39}; // @[pla.scala:120:37, :124:31]
wire [3:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_lo_lo}; // @[pla.scala:120:37]
wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_hi_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_42, _decoded_addr_decoded_decoded_invMatrixOutputs_T_41}; // @[pla.scala:120:37, :124:31]
wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_hi_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_45, _decoded_addr_decoded_decoded_invMatrixOutputs_T_44}; // @[pla.scala:120:37, :124:31]
wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_43}; // @[pla.scala:120:37, :124:31]
wire [4:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_hi_lo}; // @[pla.scala:120:37]
wire [8:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_lo}; // @[pla.scala:120:37]
wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_lo_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_47, _decoded_addr_decoded_decoded_invMatrixOutputs_T_46}; // @[pla.scala:120:37, :124:31]
wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_lo_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_50, _decoded_addr_decoded_decoded_invMatrixOutputs_T_49}; // @[pla.scala:120:37, :124:31]
wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_lo_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_lo_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_48}; // @[pla.scala:120:37, :124:31]
wire [4:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_lo_lo}; // @[pla.scala:120:37]
wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_hi_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_52, _decoded_addr_decoded_decoded_invMatrixOutputs_T_51}; // @[pla.scala:120:37, :124:31]
wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_hi_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_55, _decoded_addr_decoded_decoded_invMatrixOutputs_T_54}; // @[pla.scala:120:37, :124:31]
wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_53}; // @[pla.scala:120:37, :124:31]
wire [4:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_hi_lo}; // @[pla.scala:120:37]
wire [9:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_lo}; // @[pla.scala:120:37]
wire [18:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo}; // @[pla.scala:120:37]
wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_lo_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_57, _decoded_addr_decoded_decoded_invMatrixOutputs_T_56}; // @[pla.scala:120:37, :124:31]
wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_lo_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_59, _decoded_addr_decoded_decoded_invMatrixOutputs_T_58}; // @[pla.scala:120:37, :124:31]
wire [3:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_lo_lo}; // @[pla.scala:120:37]
wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_hi_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_61, _decoded_addr_decoded_decoded_invMatrixOutputs_T_60}; // @[pla.scala:120:37, :124:31]
wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_hi_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_64, _decoded_addr_decoded_decoded_invMatrixOutputs_T_63}; // @[pla.scala:120:37, :124:31]
wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_62}; // @[pla.scala:120:37, :124:31]
wire [4:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_hi_lo}; // @[pla.scala:120:37]
wire [8:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_lo}; // @[pla.scala:120:37]
wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_lo_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_66, _decoded_addr_decoded_decoded_invMatrixOutputs_T_65}; // @[pla.scala:120:37, :124:31]
wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_lo_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_69, _decoded_addr_decoded_decoded_invMatrixOutputs_T_68}; // @[pla.scala:120:37, :124:31]
wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_lo_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_lo_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_67}; // @[pla.scala:120:37, :124:31]
wire [4:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_lo_lo}; // @[pla.scala:120:37]
wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_hi_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_71, _decoded_addr_decoded_decoded_invMatrixOutputs_T_70}; // @[pla.scala:120:37, :124:31]
wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_hi_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_74, _decoded_addr_decoded_decoded_invMatrixOutputs_T_73}; // @[pla.scala:120:37, :124:31]
wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_72}; // @[pla.scala:120:37, :124:31]
wire [4:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_hi_lo}; // @[pla.scala:120:37]
wire [9:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_lo}; // @[pla.scala:120:37]
wire [18:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo}; // @[pla.scala:120:37]
wire [37:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo}; // @[pla.scala:120:37]
wire [74:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo}; // @[pla.scala:120:37]
wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_lo_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_76, _decoded_addr_decoded_decoded_invMatrixOutputs_T_75}; // @[pla.scala:120:37, :124:31]
wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_lo_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_78, _decoded_addr_decoded_decoded_invMatrixOutputs_T_77}; // @[pla.scala:120:37, :124:31]
wire [3:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_lo_lo}; // @[pla.scala:120:37]
wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_hi_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_80, _decoded_addr_decoded_decoded_invMatrixOutputs_T_79}; // @[pla.scala:120:37, :124:31]
wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_hi_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_83, _decoded_addr_decoded_decoded_invMatrixOutputs_T_82}; // @[pla.scala:120:37, :124:31]
wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_81}; // @[pla.scala:120:37, :124:31]
wire [4:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_hi_lo}; // @[pla.scala:120:37]
wire [8:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_lo}; // @[pla.scala:120:37]
wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_lo_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_85, _decoded_addr_decoded_decoded_invMatrixOutputs_T_84}; // @[pla.scala:120:37, :124:31]
wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_lo_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_87, _decoded_addr_decoded_decoded_invMatrixOutputs_T_86}; // @[pla.scala:120:37, :124:31]
wire [3:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_lo_lo}; // @[pla.scala:120:37]
wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_hi_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_89, _decoded_addr_decoded_decoded_invMatrixOutputs_T_88}; // @[pla.scala:120:37, :124:31]
wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_hi_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_92, _decoded_addr_decoded_decoded_invMatrixOutputs_T_91}; // @[pla.scala:120:37, :124:31]
wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_90}; // @[pla.scala:120:37, :124:31]
wire [4:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_hi_lo}; // @[pla.scala:120:37]
wire [8:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_lo}; // @[pla.scala:120:37]
wire [17:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo}; // @[pla.scala:120:37]
wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_lo_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_94, _decoded_addr_decoded_decoded_invMatrixOutputs_T_93}; // @[pla.scala:120:37, :124:31]
wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_lo_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_96, _decoded_addr_decoded_decoded_invMatrixOutputs_T_95}; // @[pla.scala:120:37, :124:31]
wire [3:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_lo_lo}; // @[pla.scala:120:37]
wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_hi_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_98, _decoded_addr_decoded_decoded_invMatrixOutputs_T_97}; // @[pla.scala:120:37, :124:31]
wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_hi_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_101, _decoded_addr_decoded_decoded_invMatrixOutputs_T_100}; // @[pla.scala:120:37, :124:31]
wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_99}; // @[pla.scala:120:37, :124:31]
wire [4:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_hi_lo}; // @[pla.scala:120:37]
wire [8:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_lo}; // @[pla.scala:120:37]
wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_lo_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_103, _decoded_addr_decoded_decoded_invMatrixOutputs_T_102}; // @[pla.scala:120:37, :124:31]
wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_lo_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_106, _decoded_addr_decoded_decoded_invMatrixOutputs_T_105}; // @[pla.scala:120:37, :124:31]
wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_lo_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_lo_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_104}; // @[pla.scala:120:37, :124:31]
wire [4:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_lo_lo}; // @[pla.scala:120:37]
wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_hi_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_108, _decoded_addr_decoded_decoded_invMatrixOutputs_T_107}; // @[pla.scala:120:37, :124:31]
wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_hi_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_111, _decoded_addr_decoded_decoded_invMatrixOutputs_T_110}; // @[pla.scala:120:37, :124:31]
wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_109}; // @[pla.scala:120:37, :124:31]
wire [4:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_hi_lo}; // @[pla.scala:120:37]
wire [9:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_lo}; // @[pla.scala:120:37]
wire [18:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo}; // @[pla.scala:120:37]
wire [36:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo}; // @[pla.scala:120:37]
wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_lo_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_113, _decoded_addr_decoded_decoded_invMatrixOutputs_T_112}; // @[pla.scala:120:37, :124:31]
wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_lo_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_115, _decoded_addr_decoded_decoded_invMatrixOutputs_T_114}; // @[pla.scala:120:37, :124:31]
wire [3:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_lo_lo}; // @[pla.scala:120:37]
wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_hi_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_117, _decoded_addr_decoded_decoded_invMatrixOutputs_T_116}; // @[pla.scala:120:37, :124:31]
wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_hi_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_120, _decoded_addr_decoded_decoded_invMatrixOutputs_T_119}; // @[pla.scala:120:37, :124:31]
wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_118}; // @[pla.scala:120:37, :124:31]
wire [4:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_hi_lo}; // @[pla.scala:120:37]
wire [8:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_lo}; // @[pla.scala:120:37]
wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_lo_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_122, _decoded_addr_decoded_decoded_invMatrixOutputs_T_121}; // @[pla.scala:120:37, :124:31]
wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_lo_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_125, _decoded_addr_decoded_decoded_invMatrixOutputs_T_124}; // @[pla.scala:120:37, :124:31]
wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_lo_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_lo_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_123}; // @[pla.scala:120:37, :124:31]
wire [4:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_lo_lo}; // @[pla.scala:120:37]
wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_hi_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_127, _decoded_addr_decoded_decoded_invMatrixOutputs_T_126}; // @[pla.scala:120:37, :124:31]
wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_hi_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_130, _decoded_addr_decoded_decoded_invMatrixOutputs_T_129}; // @[pla.scala:120:37, :124:31]
wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_128}; // @[pla.scala:120:37, :124:31]
wire [4:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_hi_lo}; // @[pla.scala:120:37]
wire [9:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_lo}; // @[pla.scala:120:37]
wire [18:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo}; // @[pla.scala:120:37]
wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_lo_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_132, _decoded_addr_decoded_decoded_invMatrixOutputs_T_131}; // @[pla.scala:120:37, :124:31]
wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_lo_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_134, _decoded_addr_decoded_decoded_invMatrixOutputs_T_133}; // @[pla.scala:120:37, :124:31]
wire [3:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_lo_lo}; // @[pla.scala:120:37]
wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_hi_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_136, _decoded_addr_decoded_decoded_invMatrixOutputs_T_135}; // @[pla.scala:120:37, :124:31]
wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_hi_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_139, _decoded_addr_decoded_decoded_invMatrixOutputs_T_138}; // @[pla.scala:120:37, :124:31]
wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_137}; // @[pla.scala:120:37, :124:31]
wire [4:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_hi_lo}; // @[pla.scala:120:37]
wire [8:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_lo}; // @[pla.scala:120:37]
wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_lo_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_141, _decoded_addr_decoded_decoded_invMatrixOutputs_T_140}; // @[pla.scala:120:37, :124:31]
wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_lo_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_144, _decoded_addr_decoded_decoded_invMatrixOutputs_T_143}; // @[pla.scala:120:37, :124:31]
wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_lo_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_lo_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_142}; // @[pla.scala:120:37, :124:31]
wire [4:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_lo_lo}; // @[pla.scala:120:37]
wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_hi_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_146, _decoded_addr_decoded_decoded_invMatrixOutputs_T_145}; // @[pla.scala:120:37, :124:31]
wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_hi_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_149, _decoded_addr_decoded_decoded_invMatrixOutputs_T_148}; // @[pla.scala:120:37, :124:31]
wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_147}; // @[pla.scala:120:37, :124:31]
wire [4:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_hi_lo}; // @[pla.scala:120:37]
wire [9:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_lo}; // @[pla.scala:120:37]
wire [18:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo}; // @[pla.scala:120:37]
wire [37:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo}; // @[pla.scala:120:37]
wire [74:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo}; // @[pla.scala:120:37]
assign decoded_addr_decoded_decoded_invMatrixOutputs = {decoded_addr_decoded_decoded_invMatrixOutputs_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo}; // @[pla.scala:120:37]
assign decoded_addr_decoded_decoded = decoded_addr_decoded_decoded_invMatrixOutputs; // @[pla.scala:81:23, :120:37]
assign decoded_addr_decoded_decoded_plaInput = decoded_addr_addr[11:0]; // @[pla.scala:77:22]
wire decoded_addr_decoded_0 = decoded_addr_decoded_decoded[149]; // @[pla.scala:81:23]
wire decoded_addr_97_2 = decoded_addr_decoded_0; // @[Decode.scala:50:77]
wire decoded_addr_decoded_1 = decoded_addr_decoded_decoded[148]; // @[pla.scala:81:23]
wire decoded_addr_55_2 = decoded_addr_decoded_1; // @[Decode.scala:50:77]
wire decoded_addr_decoded_2 = decoded_addr_decoded_decoded[147]; // @[pla.scala:81:23]
wire decoded_addr_10_2 = decoded_addr_decoded_2; // @[Decode.scala:50:77]
wire decoded_addr_decoded_3 = decoded_addr_decoded_decoded[146]; // @[pla.scala:81:23]
wire decoded_addr_118_2 = decoded_addr_decoded_3; // @[Decode.scala:50:77]
wire decoded_addr_decoded_4 = decoded_addr_decoded_decoded[145]; // @[pla.scala:81:23]
wire decoded_addr_94_2 = decoded_addr_decoded_4; // @[Decode.scala:50:77]
wire decoded_addr_decoded_5 = decoded_addr_decoded_decoded[144]; // @[pla.scala:81:23]
wire decoded_addr_100_2 = decoded_addr_decoded_5; // @[Decode.scala:50:77]
wire decoded_addr_decoded_6 = decoded_addr_decoded_decoded[143]; // @[pla.scala:81:23]
wire decoded_addr_72_2 = decoded_addr_decoded_6; // @[Decode.scala:50:77]
wire decoded_addr_decoded_7 = decoded_addr_decoded_decoded[142]; // @[pla.scala:81:23]
wire decoded_addr_108_2 = decoded_addr_decoded_7; // @[Decode.scala:50:77]
wire decoded_addr_decoded_8 = decoded_addr_decoded_decoded[141]; // @[pla.scala:81:23]
wire decoded_addr_76_2 = decoded_addr_decoded_8; // @[Decode.scala:50:77]
wire decoded_addr_decoded_9 = decoded_addr_decoded_decoded[140]; // @[pla.scala:81:23]
wire decoded_addr_129_2 = decoded_addr_decoded_9; // @[Decode.scala:50:77]
wire decoded_addr_decoded_10 = decoded_addr_decoded_decoded[139]; // @[pla.scala:81:23]
wire decoded_addr_132_2 = decoded_addr_decoded_10; // @[Decode.scala:50:77]
wire decoded_addr_decoded_11 = decoded_addr_decoded_decoded[138]; // @[pla.scala:81:23]
wire decoded_addr_136_2 = decoded_addr_decoded_11; // @[Decode.scala:50:77]
wire decoded_addr_decoded_12 = decoded_addr_decoded_decoded[137]; // @[pla.scala:81:23]
wire decoded_addr_29_2 = decoded_addr_decoded_12; // @[Decode.scala:50:77]
wire decoded_addr_decoded_13 = decoded_addr_decoded_decoded[136]; // @[pla.scala:81:23]
wire decoded_addr_131_2 = decoded_addr_decoded_13; // @[Decode.scala:50:77]
wire decoded_addr_decoded_14 = decoded_addr_decoded_decoded[135]; // @[pla.scala:81:23]
wire decoded_addr_49_2 = decoded_addr_decoded_14; // @[Decode.scala:50:77]
wire decoded_addr_decoded_15 = decoded_addr_decoded_decoded[134]; // @[pla.scala:81:23]
wire decoded_addr_89_2 = decoded_addr_decoded_15; // @[Decode.scala:50:77]
wire decoded_addr_decoded_16 = decoded_addr_decoded_decoded[133]; // @[pla.scala:81:23]
wire decoded_addr_57_2 = decoded_addr_decoded_16; // @[Decode.scala:50:77]
wire decoded_addr_decoded_17 = decoded_addr_decoded_decoded[132]; // @[pla.scala:81:23]
wire decoded_addr_36_2 = decoded_addr_decoded_17; // @[Decode.scala:50:77]
wire decoded_addr_decoded_18 = decoded_addr_decoded_decoded[131]; // @[pla.scala:81:23]
wire decoded_addr_68_2 = decoded_addr_decoded_18; // @[Decode.scala:50:77]
wire decoded_addr_decoded_19 = decoded_addr_decoded_decoded[130]; // @[pla.scala:81:23]
wire decoded_addr_99_2 = decoded_addr_decoded_19; // @[Decode.scala:50:77]
wire decoded_addr_decoded_20 = decoded_addr_decoded_decoded[129]; // @[pla.scala:81:23]
wire decoded_addr_130_2 = decoded_addr_decoded_20; // @[Decode.scala:50:77]
wire decoded_addr_decoded_21 = decoded_addr_decoded_decoded[128]; // @[pla.scala:81:23]
wire decoded_addr_103_2 = decoded_addr_decoded_21; // @[Decode.scala:50:77]
wire decoded_addr_decoded_22 = decoded_addr_decoded_decoded[127]; // @[pla.scala:81:23]
wire decoded_addr_121_2 = decoded_addr_decoded_22; // @[Decode.scala:50:77]
wire decoded_addr_decoded_23 = decoded_addr_decoded_decoded[126]; // @[pla.scala:81:23]
wire decoded_addr_146_2 = decoded_addr_decoded_23; // @[Decode.scala:50:77]
wire decoded_addr_decoded_24 = decoded_addr_decoded_decoded[125]; // @[pla.scala:81:23]
wire decoded_addr_17_2 = decoded_addr_decoded_24; // @[Decode.scala:50:77]
wire decoded_addr_decoded_25 = decoded_addr_decoded_decoded[124]; // @[pla.scala:81:23]
wire decoded_addr_27_2 = decoded_addr_decoded_25; // @[Decode.scala:50:77]
wire decoded_addr_decoded_26 = decoded_addr_decoded_decoded[123]; // @[pla.scala:81:23]
wire decoded_addr_83_2 = decoded_addr_decoded_26; // @[Decode.scala:50:77]
wire decoded_addr_decoded_27 = decoded_addr_decoded_decoded[122]; // @[pla.scala:81:23]
wire decoded_addr_52_2 = decoded_addr_decoded_27; // @[Decode.scala:50:77]
wire decoded_addr_decoded_28 = decoded_addr_decoded_decoded[121]; // @[pla.scala:81:23]
wire decoded_addr_144_2 = decoded_addr_decoded_28; // @[Decode.scala:50:77]
wire decoded_addr_decoded_29 = decoded_addr_decoded_decoded[120]; // @[pla.scala:81:23]
wire decoded_addr_70_2 = decoded_addr_decoded_29; // @[Decode.scala:50:77]
wire decoded_addr_decoded_30 = decoded_addr_decoded_decoded[119]; // @[pla.scala:81:23]
wire decoded_addr_111_2 = decoded_addr_decoded_30; // @[Decode.scala:50:77]
wire decoded_addr_decoded_31 = decoded_addr_decoded_decoded[118]; // @[pla.scala:81:23]
wire decoded_addr_82_2 = decoded_addr_decoded_31; // @[Decode.scala:50:77]
wire decoded_addr_decoded_32 = decoded_addr_decoded_decoded[117]; // @[pla.scala:81:23]
wire decoded_addr_31_2 = decoded_addr_decoded_32; // @[Decode.scala:50:77]
wire decoded_addr_decoded_33 = decoded_addr_decoded_decoded[116]; // @[pla.scala:81:23]
wire decoded_addr_0_2 = decoded_addr_decoded_33; // @[Decode.scala:50:77]
wire decoded_addr_decoded_34 = decoded_addr_decoded_decoded[115]; // @[pla.scala:81:23]
wire decoded_addr_59_2 = decoded_addr_decoded_34; // @[Decode.scala:50:77]
wire decoded_addr_decoded_35 = decoded_addr_decoded_decoded[114]; // @[pla.scala:81:23]
wire decoded_addr_138_2 = decoded_addr_decoded_35; // @[Decode.scala:50:77]
wire decoded_addr_decoded_36 = decoded_addr_decoded_decoded[113]; // @[pla.scala:81:23]
wire decoded_addr_126_2 = decoded_addr_decoded_36; // @[Decode.scala:50:77]
wire decoded_addr_decoded_37 = decoded_addr_decoded_decoded[112]; // @[pla.scala:81:23]
wire decoded_addr_74_2 = decoded_addr_decoded_37; // @[Decode.scala:50:77]
wire decoded_addr_decoded_38 = decoded_addr_decoded_decoded[111]; // @[pla.scala:81:23]
wire decoded_addr_116_2 = decoded_addr_decoded_38; // @[Decode.scala:50:77]
wire decoded_addr_decoded_39 = decoded_addr_decoded_decoded[110]; // @[pla.scala:81:23]
wire decoded_addr_90_2 = decoded_addr_decoded_39; // @[Decode.scala:50:77]
wire decoded_addr_decoded_40 = decoded_addr_decoded_decoded[109]; // @[pla.scala:81:23]
wire decoded_addr_113_2 = decoded_addr_decoded_40; // @[Decode.scala:50:77]
wire decoded_addr_decoded_41 = decoded_addr_decoded_decoded[108]; // @[pla.scala:81:23]
wire decoded_addr_1_2 = decoded_addr_decoded_41; // @[Decode.scala:50:77]
wire decoded_addr_decoded_42 = decoded_addr_decoded_decoded[107]; // @[pla.scala:81:23]
wire decoded_addr_16_2 = decoded_addr_decoded_42; // @[Decode.scala:50:77]
wire decoded_addr_decoded_43 = decoded_addr_decoded_decoded[106]; // @[pla.scala:81:23]
wire decoded_addr_78_2 = decoded_addr_decoded_43; // @[Decode.scala:50:77]
wire decoded_addr_decoded_44 = decoded_addr_decoded_decoded[105]; // @[pla.scala:81:23]
wire decoded_addr_39_2 = decoded_addr_decoded_44; // @[Decode.scala:50:77]
wire decoded_addr_decoded_45 = decoded_addr_decoded_decoded[104]; // @[pla.scala:81:23]
wire decoded_addr_51_2 = decoded_addr_decoded_45; // @[Decode.scala:50:77]
wire decoded_addr_decoded_46 = decoded_addr_decoded_decoded[103]; // @[pla.scala:81:23]
wire decoded_addr_109_2 = decoded_addr_decoded_46; // @[Decode.scala:50:77]
wire decoded_addr_decoded_47 = decoded_addr_decoded_decoded[102]; // @[pla.scala:81:23]
wire decoded_addr_91_2 = decoded_addr_decoded_47; // @[Decode.scala:50:77]
wire decoded_addr_decoded_48 = decoded_addr_decoded_decoded[101]; // @[pla.scala:81:23]
wire decoded_addr_81_2 = decoded_addr_decoded_48; // @[Decode.scala:50:77]
wire decoded_addr_decoded_49 = decoded_addr_decoded_decoded[100]; // @[pla.scala:81:23]
wire decoded_addr_67_2 = decoded_addr_decoded_49; // @[Decode.scala:50:77]
wire decoded_addr_decoded_50 = decoded_addr_decoded_decoded[99]; // @[pla.scala:81:23]
wire decoded_addr_105_2 = decoded_addr_decoded_50; // @[Decode.scala:50:77]
wire decoded_addr_decoded_51 = decoded_addr_decoded_decoded[98]; // @[pla.scala:81:23]
wire decoded_addr_122_2 = decoded_addr_decoded_51; // @[Decode.scala:50:77]
wire decoded_addr_decoded_52 = decoded_addr_decoded_decoded[97]; // @[pla.scala:81:23]
wire decoded_addr_24_2 = decoded_addr_decoded_52; // @[Decode.scala:50:77]
wire decoded_addr_decoded_53 = decoded_addr_decoded_decoded[96]; // @[pla.scala:81:23]
wire decoded_addr_124_2 = decoded_addr_decoded_53; // @[Decode.scala:50:77]
wire decoded_addr_decoded_54 = decoded_addr_decoded_decoded[95]; // @[pla.scala:81:23]
wire decoded_addr_26_2 = decoded_addr_decoded_54; // @[Decode.scala:50:77]
wire decoded_addr_decoded_55 = decoded_addr_decoded_decoded[94]; // @[pla.scala:81:23]
wire decoded_addr_128_2 = decoded_addr_decoded_55; // @[Decode.scala:50:77]
wire decoded_addr_decoded_56 = decoded_addr_decoded_decoded[93]; // @[pla.scala:81:23]
wire decoded_addr_7_2 = decoded_addr_decoded_56; // @[Decode.scala:50:77]
wire decoded_addr_decoded_57 = decoded_addr_decoded_decoded[92]; // @[pla.scala:81:23]
wire decoded_addr_62_2 = decoded_addr_decoded_57; // @[Decode.scala:50:77]
wire decoded_addr_decoded_58 = decoded_addr_decoded_decoded[91]; // @[pla.scala:81:23]
wire decoded_addr_77_2 = decoded_addr_decoded_58; // @[Decode.scala:50:77]
wire decoded_addr_decoded_59 = decoded_addr_decoded_decoded[90]; // @[pla.scala:81:23]
wire decoded_addr_46_2 = decoded_addr_decoded_59; // @[Decode.scala:50:77]
wire decoded_addr_decoded_60 = decoded_addr_decoded_decoded[89]; // @[pla.scala:81:23]
wire decoded_addr_112_2 = decoded_addr_decoded_60; // @[Decode.scala:50:77]
wire decoded_addr_decoded_61 = decoded_addr_decoded_decoded[88]; // @[pla.scala:81:23]
wire decoded_addr_60_2 = decoded_addr_decoded_61; // @[Decode.scala:50:77]
wire decoded_addr_decoded_62 = decoded_addr_decoded_decoded[87]; // @[pla.scala:81:23]
wire decoded_addr_92_2 = decoded_addr_decoded_62; // @[Decode.scala:50:77]
wire decoded_addr_decoded_63 = decoded_addr_decoded_decoded[86]; // @[pla.scala:81:23]
wire decoded_addr_148_2 = decoded_addr_decoded_63; // @[Decode.scala:50:77]
wire decoded_addr_decoded_64 = decoded_addr_decoded_decoded[85]; // @[pla.scala:81:23]
wire decoded_addr_14_2 = decoded_addr_decoded_64; // @[Decode.scala:50:77]
wire decoded_addr_decoded_65 = decoded_addr_decoded_decoded[84]; // @[pla.scala:81:23]
wire decoded_addr_21_2 = decoded_addr_decoded_65; // @[Decode.scala:50:77]
wire decoded_addr_decoded_66 = decoded_addr_decoded_decoded[83]; // @[pla.scala:81:23]
wire decoded_addr_33_2 = decoded_addr_decoded_66; // @[Decode.scala:50:77]
wire decoded_addr_decoded_67 = decoded_addr_decoded_decoded[82]; // @[pla.scala:81:23]
wire decoded_addr_19_2 = decoded_addr_decoded_67; // @[Decode.scala:50:77]
wire decoded_addr_decoded_68 = decoded_addr_decoded_decoded[81]; // @[pla.scala:81:23]
wire decoded_addr_133_2 = decoded_addr_decoded_68; // @[Decode.scala:50:77]
wire decoded_addr_decoded_69 = decoded_addr_decoded_decoded[80]; // @[pla.scala:81:23]
wire decoded_addr_149_2 = decoded_addr_decoded_69; // @[Decode.scala:50:77]
wire decoded_addr_decoded_70 = decoded_addr_decoded_decoded[79]; // @[pla.scala:81:23]
wire decoded_addr_50_2 = decoded_addr_decoded_70; // @[Decode.scala:50:77]
wire decoded_addr_decoded_71 = decoded_addr_decoded_decoded[78]; // @[pla.scala:81:23]
wire decoded_addr_75_2 = decoded_addr_decoded_71; // @[Decode.scala:50:77]
wire decoded_addr_decoded_72 = decoded_addr_decoded_decoded[77]; // @[pla.scala:81:23]
wire decoded_addr_102_2 = decoded_addr_decoded_72; // @[Decode.scala:50:77]
wire decoded_addr_decoded_73 = decoded_addr_decoded_decoded[76]; // @[pla.scala:81:23]
wire decoded_addr_84_2 = decoded_addr_decoded_73; // @[Decode.scala:50:77]
wire decoded_addr_decoded_74 = decoded_addr_decoded_decoded[75]; // @[pla.scala:81:23]
wire decoded_addr_45_2 = decoded_addr_decoded_74; // @[Decode.scala:50:77]
wire decoded_addr_decoded_75 = decoded_addr_decoded_decoded[74]; // @[pla.scala:81:23]
wire decoded_addr_64_2 = decoded_addr_decoded_75; // @[Decode.scala:50:77]
wire decoded_addr_decoded_76 = decoded_addr_decoded_decoded[73]; // @[pla.scala:81:23]
wire decoded_addr_120_2 = decoded_addr_decoded_76; // @[Decode.scala:50:77]
wire decoded_addr_decoded_77 = decoded_addr_decoded_decoded[72]; // @[pla.scala:81:23]
wire decoded_addr_30_2 = decoded_addr_decoded_77; // @[Decode.scala:50:77]
wire decoded_addr_decoded_78 = decoded_addr_decoded_decoded[71]; // @[pla.scala:81:23]
wire decoded_addr_5_2 = decoded_addr_decoded_78; // @[Decode.scala:50:77]
wire decoded_addr_decoded_79 = decoded_addr_decoded_decoded[70]; // @[pla.scala:81:23]
wire decoded_addr_32_2 = decoded_addr_decoded_79; // @[Decode.scala:50:77]
wire decoded_addr_decoded_80 = decoded_addr_decoded_decoded[69]; // @[pla.scala:81:23]
wire decoded_addr_143_2 = decoded_addr_decoded_80; // @[Decode.scala:50:77]
wire decoded_addr_decoded_81 = decoded_addr_decoded_decoded[68]; // @[pla.scala:81:23]
wire decoded_addr_117_2 = decoded_addr_decoded_81; // @[Decode.scala:50:77]
wire decoded_addr_decoded_82 = decoded_addr_decoded_decoded[67]; // @[pla.scala:81:23]
wire decoded_addr_63_2 = decoded_addr_decoded_82; // @[Decode.scala:50:77]
wire decoded_addr_decoded_83 = decoded_addr_decoded_decoded[66]; // @[pla.scala:81:23]
wire decoded_addr_107_2 = decoded_addr_decoded_83; // @[Decode.scala:50:77]
wire decoded_addr_decoded_84 = decoded_addr_decoded_decoded[65]; // @[pla.scala:81:23]
wire decoded_addr_88_2 = decoded_addr_decoded_84; // @[Decode.scala:50:77]
wire decoded_addr_decoded_85 = decoded_addr_decoded_decoded[64]; // @[pla.scala:81:23]
wire decoded_addr_114_2 = decoded_addr_decoded_85; // @[Decode.scala:50:77]
wire decoded_addr_decoded_86 = decoded_addr_decoded_decoded[63]; // @[pla.scala:81:23]
wire decoded_addr_73_2 = decoded_addr_decoded_86; // @[Decode.scala:50:77]
wire decoded_addr_decoded_87 = decoded_addr_decoded_decoded[62]; // @[pla.scala:81:23]
wire decoded_addr_53_2 = decoded_addr_decoded_87; // @[Decode.scala:50:77]
wire decoded_addr_decoded_88 = decoded_addr_decoded_decoded[61]; // @[pla.scala:81:23]
wire decoded_addr_147_2 = decoded_addr_decoded_88; // @[Decode.scala:50:77]
wire decoded_addr_decoded_89 = decoded_addr_decoded_decoded[60]; // @[pla.scala:81:23]
wire decoded_addr_41_2 = decoded_addr_decoded_89; // @[Decode.scala:50:77]
wire decoded_addr_decoded_90 = decoded_addr_decoded_decoded[59]; // @[pla.scala:81:23]
wire decoded_addr_56_2 = decoded_addr_decoded_90; // @[Decode.scala:50:77]
wire decoded_addr_decoded_91 = decoded_addr_decoded_decoded[58]; // @[pla.scala:81:23]
wire decoded_addr_37_2 = decoded_addr_decoded_91; // @[Decode.scala:50:77]
wire decoded_addr_decoded_92 = decoded_addr_decoded_decoded[57]; // @[pla.scala:81:23]
wire decoded_addr_79_2 = decoded_addr_decoded_92; // @[Decode.scala:50:77]
wire decoded_addr_decoded_93 = decoded_addr_decoded_decoded[56]; // @[pla.scala:81:23]
wire decoded_addr_96_2 = decoded_addr_decoded_93; // @[Decode.scala:50:77]
wire decoded_addr_decoded_94 = decoded_addr_decoded_decoded[55]; // @[pla.scala:81:23]
wire decoded_addr_4_2 = decoded_addr_decoded_94; // @[Decode.scala:50:77]
wire decoded_addr_decoded_95 = decoded_addr_decoded_decoded[54]; // @[pla.scala:81:23]
wire decoded_addr_101_2 = decoded_addr_decoded_95; // @[Decode.scala:50:77]
wire decoded_addr_decoded_96 = decoded_addr_decoded_decoded[53]; // @[pla.scala:81:23]
wire decoded_addr_119_2 = decoded_addr_decoded_96; // @[Decode.scala:50:77]
wire decoded_addr_decoded_97 = decoded_addr_decoded_decoded[52]; // @[pla.scala:81:23]
wire decoded_addr_22_2 = decoded_addr_decoded_97; // @[Decode.scala:50:77]
wire decoded_addr_decoded_98 = decoded_addr_decoded_decoded[51]; // @[pla.scala:81:23]
wire decoded_addr_139_2 = decoded_addr_decoded_98; // @[Decode.scala:50:77]
wire decoded_addr_decoded_99 = decoded_addr_decoded_decoded[50]; // @[pla.scala:81:23]
wire decoded_addr_11_2 = decoded_addr_decoded_99; // @[Decode.scala:50:77]
wire decoded_addr_decoded_100 = decoded_addr_decoded_decoded[49]; // @[pla.scala:81:23]
wire decoded_addr_134_2 = decoded_addr_decoded_100; // @[Decode.scala:50:77]
wire decoded_addr_decoded_101 = decoded_addr_decoded_decoded[48]; // @[pla.scala:81:23]
wire decoded_addr_12_2 = decoded_addr_decoded_101; // @[Decode.scala:50:77]
wire decoded_addr_decoded_102 = decoded_addr_decoded_decoded[47]; // @[pla.scala:81:23]
wire decoded_addr_65_2 = decoded_addr_decoded_102; // @[Decode.scala:50:77]
wire decoded_addr_decoded_103 = decoded_addr_decoded_decoded[46]; // @[pla.scala:81:23]
wire decoded_addr_86_2 = decoded_addr_decoded_103; // @[Decode.scala:50:77]
wire decoded_addr_decoded_104 = decoded_addr_decoded_decoded[45]; // @[pla.scala:81:23]
wire decoded_addr_47_2 = decoded_addr_decoded_104; // @[Decode.scala:50:77]
wire decoded_addr_decoded_105 = decoded_addr_decoded_decoded[44]; // @[pla.scala:81:23]
wire decoded_addr_106_2 = decoded_addr_decoded_105; // @[Decode.scala:50:77]
wire decoded_addr_decoded_106 = decoded_addr_decoded_decoded[43]; // @[pla.scala:81:23]
wire decoded_addr_58_2 = decoded_addr_decoded_106; // @[Decode.scala:50:77]
wire decoded_addr_decoded_107 = decoded_addr_decoded_decoded[42]; // @[pla.scala:81:23]
wire decoded_addr_87_2 = decoded_addr_decoded_107; // @[Decode.scala:50:77]
wire decoded_addr_decoded_108 = decoded_addr_decoded_decoded[41]; // @[pla.scala:81:23]
wire decoded_addr_142_2 = decoded_addr_decoded_108; // @[Decode.scala:50:77]
wire decoded_addr_decoded_109 = decoded_addr_decoded_decoded[40]; // @[pla.scala:81:23]
wire decoded_addr_13_2 = decoded_addr_decoded_109; // @[Decode.scala:50:77]
wire decoded_addr_decoded_110 = decoded_addr_decoded_decoded[39]; // @[pla.scala:81:23]
wire decoded_addr_35_2 = decoded_addr_decoded_110; // @[Decode.scala:50:77]
wire decoded_addr_decoded_111 = decoded_addr_decoded_decoded[38]; // @[pla.scala:81:23]
wire decoded_addr_2_2 = decoded_addr_decoded_111; // @[Decode.scala:50:77]
wire decoded_addr_decoded_112 = decoded_addr_decoded_decoded[37]; // @[pla.scala:81:23]
wire decoded_addr_66_2 = decoded_addr_decoded_112; // @[Decode.scala:50:77]
wire decoded_addr_decoded_113 = decoded_addr_decoded_decoded[36]; // @[pla.scala:81:23]
wire decoded_addr_42_2 = decoded_addr_decoded_113; // @[Decode.scala:50:77]
wire decoded_addr_decoded_114 = decoded_addr_decoded_decoded[35]; // @[pla.scala:81:23]
wire decoded_addr_61_2 = decoded_addr_decoded_114; // @[Decode.scala:50:77]
wire decoded_addr_decoded_115 = decoded_addr_decoded_decoded[34]; // @[pla.scala:81:23]
wire decoded_addr_48_2 = decoded_addr_decoded_115; // @[Decode.scala:50:77]
wire decoded_addr_decoded_116 = decoded_addr_decoded_decoded[33]; // @[pla.scala:81:23]
wire decoded_addr_44_2 = decoded_addr_decoded_116; // @[Decode.scala:50:77]
wire decoded_addr_decoded_117 = decoded_addr_decoded_decoded[32]; // @[pla.scala:81:23]
wire decoded_addr_15_2 = decoded_addr_decoded_117; // @[Decode.scala:50:77]
wire decoded_addr_decoded_118 = decoded_addr_decoded_decoded[31]; // @[pla.scala:81:23]
wire decoded_addr_145_2 = decoded_addr_decoded_118; // @[Decode.scala:50:77]
wire decoded_addr_decoded_119 = decoded_addr_decoded_decoded[30]; // @[pla.scala:81:23]
wire decoded_addr_93_2 = decoded_addr_decoded_119; // @[Decode.scala:50:77]
wire decoded_addr_decoded_120 = decoded_addr_decoded_decoded[29]; // @[pla.scala:81:23]
wire decoded_addr_6_2 = decoded_addr_decoded_120; // @[Decode.scala:50:77]
wire decoded_addr_decoded_121 = decoded_addr_decoded_decoded[28]; // @[pla.scala:81:23]
wire decoded_addr_28_2 = decoded_addr_decoded_121; // @[Decode.scala:50:77]
wire decoded_addr_decoded_122 = decoded_addr_decoded_decoded[27]; // @[pla.scala:81:23]
wire decoded_addr_25_2 = decoded_addr_decoded_122; // @[Decode.scala:50:77]
wire decoded_addr_decoded_123 = decoded_addr_decoded_decoded[26]; // @[pla.scala:81:23]
wire decoded_addr_137_2 = decoded_addr_decoded_123; // @[Decode.scala:50:77]
wire decoded_addr_decoded_124 = decoded_addr_decoded_decoded[25]; // @[pla.scala:81:23]
wire decoded_addr_123_2 = decoded_addr_decoded_124; // @[Decode.scala:50:77]
wire decoded_addr_decoded_125 = decoded_addr_decoded_decoded[24]; // @[pla.scala:81:23]
wire decoded_addr_23_2 = decoded_addr_decoded_125; // @[Decode.scala:50:77]
wire decoded_addr_decoded_126 = decoded_addr_decoded_decoded[23]; // @[pla.scala:81:23]
wire decoded_addr_69_2 = decoded_addr_decoded_126; // @[Decode.scala:50:77]
wire decoded_addr_decoded_127 = decoded_addr_decoded_decoded[22]; // @[pla.scala:81:23]
wire decoded_addr_141_2 = decoded_addr_decoded_127; // @[Decode.scala:50:77]
wire decoded_addr_decoded_128 = decoded_addr_decoded_decoded[21]; // @[pla.scala:81:23]
wire decoded_addr_9_2 = decoded_addr_decoded_128; // @[Decode.scala:50:77]
wire decoded_addr_decoded_129 = decoded_addr_decoded_decoded[20]; // @[pla.scala:81:23]
wire decoded_addr_104_2 = decoded_addr_decoded_129; // @[Decode.scala:50:77]
wire decoded_addr_decoded_130 = decoded_addr_decoded_decoded[19]; // @[pla.scala:81:23]
wire decoded_addr_8_2 = decoded_addr_decoded_130; // @[Decode.scala:50:77]
wire decoded_addr_decoded_131 = decoded_addr_decoded_decoded[18]; // @[pla.scala:81:23]
wire decoded_addr_125_2 = decoded_addr_decoded_131; // @[Decode.scala:50:77]
wire decoded_addr_decoded_132 = decoded_addr_decoded_decoded[17]; // @[pla.scala:81:23]
wire decoded_addr_85_2 = decoded_addr_decoded_132; // @[Decode.scala:50:77]
wire decoded_addr_decoded_133 = decoded_addr_decoded_decoded[16]; // @[pla.scala:81:23]
wire decoded_addr_54_2 = decoded_addr_decoded_133; // @[Decode.scala:50:77]
wire decoded_addr_decoded_134 = decoded_addr_decoded_decoded[15]; // @[pla.scala:81:23]
wire decoded_addr_20_2 = decoded_addr_decoded_134; // @[Decode.scala:50:77]
wire decoded_addr_decoded_135 = decoded_addr_decoded_decoded[14]; // @[pla.scala:81:23]
wire decoded_addr_135_2 = decoded_addr_decoded_135; // @[Decode.scala:50:77]
wire decoded_addr_decoded_136 = decoded_addr_decoded_decoded[13]; // @[pla.scala:81:23]
wire decoded_addr_115_2 = decoded_addr_decoded_136; // @[Decode.scala:50:77]
wire decoded_addr_decoded_137 = decoded_addr_decoded_decoded[12]; // @[pla.scala:81:23]
wire decoded_addr_43_2 = decoded_addr_decoded_137; // @[Decode.scala:50:77]
wire decoded_addr_decoded_138 = decoded_addr_decoded_decoded[11]; // @[pla.scala:81:23]
wire decoded_addr_71_2 = decoded_addr_decoded_138; // @[Decode.scala:50:77]
wire decoded_addr_decoded_139 = decoded_addr_decoded_decoded[10]; // @[pla.scala:81:23]
wire decoded_addr_110_2 = decoded_addr_decoded_139; // @[Decode.scala:50:77]
wire decoded_addr_decoded_140 = decoded_addr_decoded_decoded[9]; // @[pla.scala:81:23]
wire decoded_addr_140_2 = decoded_addr_decoded_140; // @[Decode.scala:50:77]
wire decoded_addr_decoded_141 = decoded_addr_decoded_decoded[8]; // @[pla.scala:81:23]
wire decoded_addr_34_2 = decoded_addr_decoded_141; // @[Decode.scala:50:77]
wire decoded_addr_decoded_142 = decoded_addr_decoded_decoded[7]; // @[pla.scala:81:23]
wire decoded_addr_40_2 = decoded_addr_decoded_142; // @[Decode.scala:50:77]
wire decoded_addr_decoded_143 = decoded_addr_decoded_decoded[6]; // @[pla.scala:81:23]
wire decoded_addr_80_2 = decoded_addr_decoded_143; // @[Decode.scala:50:77]
wire decoded_addr_decoded_144 = decoded_addr_decoded_decoded[5]; // @[pla.scala:81:23]
wire decoded_addr_98_2 = decoded_addr_decoded_144; // @[Decode.scala:50:77]
wire decoded_addr_decoded_145 = decoded_addr_decoded_decoded[4]; // @[pla.scala:81:23]
wire decoded_addr_18_2 = decoded_addr_decoded_145; // @[Decode.scala:50:77]
wire decoded_addr_decoded_146 = decoded_addr_decoded_decoded[3]; // @[pla.scala:81:23]
wire decoded_addr_3_2 = decoded_addr_decoded_146; // @[Decode.scala:50:77]
wire decoded_addr_decoded_147 = decoded_addr_decoded_decoded[2]; // @[pla.scala:81:23]
wire decoded_addr_38_2 = decoded_addr_decoded_147; // @[Decode.scala:50:77]
wire decoded_addr_decoded_148 = decoded_addr_decoded_decoded[1]; // @[pla.scala:81:23]
wire decoded_addr_127_2 = decoded_addr_decoded_148; // @[Decode.scala:50:77]
wire decoded_addr_decoded_149 = decoded_addr_decoded_decoded[0]; // @[pla.scala:81:23]
wire decoded_addr_95_2 = decoded_addr_decoded_149; // @[Decode.scala:50:77]
wire _wdata_T = io_rw_cmd_0[1]; // @[CSR.scala:377:7, :1643:13]
wire _new_mip_T_1 = io_rw_cmd_0[1]; // @[CSR.scala:377:7, :1643:13]
wire _newBPC_T_1 = io_rw_cmd_0[1]; // @[CSR.scala:377:7, :1643:13]
wire _newBPC_T_25 = io_rw_cmd_0[1]; // @[CSR.scala:377:7, :1643:13]
wire [63:0] _wdata_T_1 = _wdata_T ? io_rw_rdata_0 : 64'h0; // @[CSR.scala:377:7, :1643:{9,13}]
wire [63:0] _wdata_T_2 = _wdata_T_1 | io_rw_wdata_0; // @[CSR.scala:377:7, :1643:{9,30}]
wire [1:0] _wdata_T_3 = io_rw_cmd_0[1:0]; // @[CSR.scala:377:7, :1643:49]
wire [1:0] _new_mip_T_4 = io_rw_cmd_0[1:0]; // @[CSR.scala:377:7, :1643:49]
wire [1:0] _newBPC_T_4 = io_rw_cmd_0[1:0]; // @[CSR.scala:377:7, :1643:49]
wire [1:0] _newBPC_T_28 = io_rw_cmd_0[1:0]; // @[CSR.scala:377:7, :1643:49]
wire _wdata_T_4 = &_wdata_T_3; // @[CSR.scala:1643:{49,55}]
wire [63:0] _wdata_T_5 = _wdata_T_4 ? io_rw_wdata_0 : 64'h0; // @[CSR.scala:377:7, :1643:{45,55}]
wire [63:0] _wdata_T_6 = ~_wdata_T_5; // @[CSR.scala:1643:{41,45}]
assign wdata = _wdata_T_2 & _wdata_T_6; // @[CSR.scala:1643:{30,39,41}]
assign io_customCSRs_0_wdata_0 = wdata; // @[CSR.scala:377:7, :1643:39]
assign io_customCSRs_1_wdata_0 = wdata; // @[CSR.scala:377:7, :1643:39]
assign io_customCSRs_2_wdata_0 = wdata; // @[CSR.scala:377:7, :1643:39]
assign io_customCSRs_3_wdata_0 = wdata; // @[CSR.scala:377:7, :1643:39]
wire [63:0] _new_satp_WIRE = wdata; // @[CSR.scala:1355:40, :1643:39]
wire [63:0] _new_envcfg_WIRE = wdata; // @[CSR.scala:137:36, :1643:39]
wire [63:0] _new_envcfg_WIRE_1 = wdata; // @[CSR.scala:137:36, :1643:39]
wire [63:0] _reg_bp_0_control_WIRE_1 = wdata; // @[CSR.scala:1471:41, :1643:39]
wire [63:0] _reg_bp_1_control_WIRE_1 = wdata; // @[CSR.scala:1471:41, :1643:39]
wire [63:0] _newCfg_T = wdata; // @[CSR.scala:1491:29, :1643:39]
wire system_insn = io_rw_cmd_0 == 3'h4; // @[CSR.scala:377:7, :876:31]
wire [31:0] _insn_T = {io_rw_addr_0, 20'h0}; // @[CSR.scala:377:7, :892:44]
wire [31:0] insn = {_insn_T[31:7], _insn_T[6:0] | 7'h73}; // @[CSR.scala:892:{30,44}]
wire [31:0] decoded_plaInput = insn; // @[pla.scala:77:22]
wire [31:0] decoded_invInputs = ~decoded_plaInput; // @[pla.scala:77:22, :78:21]
wire [8:0] decoded_invMatrixOutputs; // @[pla.scala:120:37]
wire [8:0] decoded; // @[pla.scala:81:23]
wire decoded_andMatrixOutputs_andMatrixInput_0 = decoded_invInputs[20]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_1 = decoded_invInputs[21]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_1_1 = decoded_invInputs[21]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_2 = decoded_invInputs[22]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_2_1 = decoded_invInputs[22]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_1_2 = decoded_invInputs[22]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_3 = decoded_invInputs[23]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_3_1 = decoded_invInputs[23]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_2_2 = decoded_invInputs[23]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_1_3 = decoded_invInputs[23]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_1_5 = decoded_invInputs[23]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_4 = decoded_invInputs[24]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_4_1 = decoded_invInputs[24]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_3_2 = decoded_invInputs[24]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_2_3 = decoded_invInputs[24]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_2_5 = decoded_invInputs[24]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_5 = decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_5_1 = decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_4_2 = decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_3_3 = decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_3_5 = decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_6 = decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_6_1 = decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_5_2 = decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_4_3 = decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_11_2 = decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_4_5 = decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_7 = decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_7_1 = decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_6_2 = decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_5_3 = decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_12 = decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_5_5 = decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_8 = decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_8_1 = decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_9 = decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_9_1 = decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_7_3 = decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_14 = decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_10 = decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_10_1 = decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_8_2 = decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_8_3 = decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_15 = decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_8_5 = decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_11 = decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_11_1 = decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_9_2 = decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_9_3 = decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_16 = decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_9_5 = decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_1_6 = decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire [1:0] decoded_andMatrixOutputs_lo_lo_hi = {decoded_andMatrixOutputs_andMatrixInput_9, decoded_andMatrixOutputs_andMatrixInput_10}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_andMatrixOutputs_lo_lo = {decoded_andMatrixOutputs_lo_lo_hi, decoded_andMatrixOutputs_andMatrixInput_11}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_andMatrixOutputs_lo_hi_hi = {decoded_andMatrixOutputs_andMatrixInput_6, decoded_andMatrixOutputs_andMatrixInput_7}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_andMatrixOutputs_lo_hi = {decoded_andMatrixOutputs_lo_hi_hi, decoded_andMatrixOutputs_andMatrixInput_8}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_andMatrixOutputs_lo = {decoded_andMatrixOutputs_lo_hi, decoded_andMatrixOutputs_lo_lo}; // @[pla.scala:98:53]
wire [1:0] decoded_andMatrixOutputs_hi_lo_hi = {decoded_andMatrixOutputs_andMatrixInput_3, decoded_andMatrixOutputs_andMatrixInput_4}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_andMatrixOutputs_hi_lo = {decoded_andMatrixOutputs_hi_lo_hi, decoded_andMatrixOutputs_andMatrixInput_5}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_andMatrixOutputs_hi_hi_hi = {decoded_andMatrixOutputs_andMatrixInput_0, decoded_andMatrixOutputs_andMatrixInput_1}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_andMatrixOutputs_hi_hi = {decoded_andMatrixOutputs_hi_hi_hi, decoded_andMatrixOutputs_andMatrixInput_2}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_andMatrixOutputs_hi = {decoded_andMatrixOutputs_hi_hi, decoded_andMatrixOutputs_hi_lo}; // @[pla.scala:98:53]
wire [11:0] _decoded_andMatrixOutputs_T = {decoded_andMatrixOutputs_hi, decoded_andMatrixOutputs_lo}; // @[pla.scala:98:53]
wire decoded_andMatrixOutputs_6_2 = &_decoded_andMatrixOutputs_T; // @[pla.scala:98:{53,70}]
wire _decoded_orMatrixOutputs_T_6 = decoded_andMatrixOutputs_6_2; // @[pla.scala:98:70, :114:36]
wire decoded_andMatrixOutputs_andMatrixInput_0_1 = decoded_plaInput[20]; // @[pla.scala:77:22, :90:45]
wire [1:0] decoded_andMatrixOutputs_lo_lo_hi_1 = {decoded_andMatrixOutputs_andMatrixInput_9_1, decoded_andMatrixOutputs_andMatrixInput_10_1}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_andMatrixOutputs_lo_lo_1 = {decoded_andMatrixOutputs_lo_lo_hi_1, decoded_andMatrixOutputs_andMatrixInput_11_1}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_andMatrixOutputs_lo_hi_hi_1 = {decoded_andMatrixOutputs_andMatrixInput_6_1, decoded_andMatrixOutputs_andMatrixInput_7_1}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_andMatrixOutputs_lo_hi_1 = {decoded_andMatrixOutputs_lo_hi_hi_1, decoded_andMatrixOutputs_andMatrixInput_8_1}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_andMatrixOutputs_lo_1 = {decoded_andMatrixOutputs_lo_hi_1, decoded_andMatrixOutputs_lo_lo_1}; // @[pla.scala:98:53]
wire [1:0] decoded_andMatrixOutputs_hi_lo_hi_1 = {decoded_andMatrixOutputs_andMatrixInput_3_1, decoded_andMatrixOutputs_andMatrixInput_4_1}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_andMatrixOutputs_hi_lo_1 = {decoded_andMatrixOutputs_hi_lo_hi_1, decoded_andMatrixOutputs_andMatrixInput_5_1}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_andMatrixOutputs_hi_hi_hi_1 = {decoded_andMatrixOutputs_andMatrixInput_0_1, decoded_andMatrixOutputs_andMatrixInput_1_1}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_andMatrixOutputs_hi_hi_1 = {decoded_andMatrixOutputs_hi_hi_hi_1, decoded_andMatrixOutputs_andMatrixInput_2_1}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_andMatrixOutputs_hi_1 = {decoded_andMatrixOutputs_hi_hi_1, decoded_andMatrixOutputs_hi_lo_1}; // @[pla.scala:98:53]
wire [11:0] _decoded_andMatrixOutputs_T_1 = {decoded_andMatrixOutputs_hi_1, decoded_andMatrixOutputs_lo_1}; // @[pla.scala:98:53]
wire decoded_andMatrixOutputs_4_2 = &_decoded_andMatrixOutputs_T_1; // @[pla.scala:98:{53,70}]
wire _decoded_orMatrixOutputs_T_5 = decoded_andMatrixOutputs_4_2; // @[pla.scala:98:70, :114:36]
wire decoded_andMatrixOutputs_andMatrixInput_0_2 = decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoded_andMatrixOutputs_andMatrixInput_0_4 = decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoded_andMatrixOutputs_andMatrixInput_7_2 = decoded_plaInput[28]; // @[pla.scala:77:22, :90:45]
wire decoded_andMatrixOutputs_andMatrixInput_6_3 = decoded_plaInput[28]; // @[pla.scala:77:22, :90:45]
wire decoded_andMatrixOutputs_andMatrixInput_13 = decoded_plaInput[28]; // @[pla.scala:77:22, :90:45]
wire decoded_andMatrixOutputs_andMatrixInput_6_5 = decoded_plaInput[28]; // @[pla.scala:77:22, :90:45]
wire [1:0] decoded_andMatrixOutputs_lo_lo_2 = {decoded_andMatrixOutputs_andMatrixInput_8_2, decoded_andMatrixOutputs_andMatrixInput_9_2}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_andMatrixOutputs_lo_hi_hi_2 = {decoded_andMatrixOutputs_andMatrixInput_5_2, decoded_andMatrixOutputs_andMatrixInput_6_2}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_andMatrixOutputs_lo_hi_2 = {decoded_andMatrixOutputs_lo_hi_hi_2, decoded_andMatrixOutputs_andMatrixInput_7_2}; // @[pla.scala:90:45, :98:53]
wire [4:0] decoded_andMatrixOutputs_lo_2 = {decoded_andMatrixOutputs_lo_hi_2, decoded_andMatrixOutputs_lo_lo_2}; // @[pla.scala:98:53]
wire [1:0] decoded_andMatrixOutputs_hi_lo_2 = {decoded_andMatrixOutputs_andMatrixInput_3_2, decoded_andMatrixOutputs_andMatrixInput_4_2}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_andMatrixOutputs_hi_hi_hi_2 = {decoded_andMatrixOutputs_andMatrixInput_0_2, decoded_andMatrixOutputs_andMatrixInput_1_2}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_andMatrixOutputs_hi_hi_2 = {decoded_andMatrixOutputs_hi_hi_hi_2, decoded_andMatrixOutputs_andMatrixInput_2_2}; // @[pla.scala:91:29, :98:53]
wire [4:0] decoded_andMatrixOutputs_hi_2 = {decoded_andMatrixOutputs_hi_hi_2, decoded_andMatrixOutputs_hi_lo_2}; // @[pla.scala:98:53]
wire [9:0] _decoded_andMatrixOutputs_T_2 = {decoded_andMatrixOutputs_hi_2, decoded_andMatrixOutputs_lo_2}; // @[pla.scala:98:53]
wire decoded_andMatrixOutputs_3_2 = &_decoded_andMatrixOutputs_T_2; // @[pla.scala:98:{53,70}]
wire decoded_andMatrixOutputs_andMatrixInput_0_3 = decoded_plaInput[22]; // @[pla.scala:77:22, :90:45]
wire decoded_andMatrixOutputs_andMatrixInput_0_5 = decoded_plaInput[22]; // @[pla.scala:77:22, :90:45]
wire [1:0] decoded_andMatrixOutputs_lo_lo_3 = {decoded_andMatrixOutputs_andMatrixInput_8_3, decoded_andMatrixOutputs_andMatrixInput_9_3}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_andMatrixOutputs_lo_hi_hi_3 = {decoded_andMatrixOutputs_andMatrixInput_5_3, decoded_andMatrixOutputs_andMatrixInput_6_3}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_andMatrixOutputs_lo_hi_3 = {decoded_andMatrixOutputs_lo_hi_hi_3, decoded_andMatrixOutputs_andMatrixInput_7_3}; // @[pla.scala:91:29, :98:53]
wire [4:0] decoded_andMatrixOutputs_lo_3 = {decoded_andMatrixOutputs_lo_hi_3, decoded_andMatrixOutputs_lo_lo_3}; // @[pla.scala:98:53]
wire [1:0] decoded_andMatrixOutputs_hi_lo_3 = {decoded_andMatrixOutputs_andMatrixInput_3_3, decoded_andMatrixOutputs_andMatrixInput_4_3}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_andMatrixOutputs_hi_hi_hi_3 = {decoded_andMatrixOutputs_andMatrixInput_0_3, decoded_andMatrixOutputs_andMatrixInput_1_3}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_andMatrixOutputs_hi_hi_3 = {decoded_andMatrixOutputs_hi_hi_hi_3, decoded_andMatrixOutputs_andMatrixInput_2_3}; // @[pla.scala:91:29, :98:53]
wire [4:0] decoded_andMatrixOutputs_hi_3 = {decoded_andMatrixOutputs_hi_hi_3, decoded_andMatrixOutputs_hi_lo_3}; // @[pla.scala:98:53]
wire [9:0] _decoded_andMatrixOutputs_T_3 = {decoded_andMatrixOutputs_hi_3, decoded_andMatrixOutputs_lo_3}; // @[pla.scala:98:53]
wire decoded_andMatrixOutputs_1_2 = &_decoded_andMatrixOutputs_T_3; // @[pla.scala:98:{53,70}]
wire _decoded_orMatrixOutputs_T_1 = decoded_andMatrixOutputs_1_2; // @[pla.scala:98:70, :114:36]
wire decoded_andMatrixOutputs_andMatrixInput_1_4 = decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoded_andMatrixOutputs_andMatrixInput_2_4 = decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_3_4 = decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_4_4 = decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoded_andMatrixOutputs_andMatrixInput_5_4 = decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire decoded_andMatrixOutputs_andMatrixInput_6_4 = decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire decoded_andMatrixOutputs_andMatrixInput_7_4 = decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_8_4 = decoded_invInputs[8]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_9_4 = decoded_invInputs[9]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_10_2 = decoded_plaInput[25]; // @[pla.scala:77:22, :90:45]
wire [1:0] decoded_andMatrixOutputs_lo_lo_lo = {decoded_andMatrixOutputs_andMatrixInput_15, decoded_andMatrixOutputs_andMatrixInput_16}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_andMatrixOutputs_lo_lo_hi_2 = {decoded_andMatrixOutputs_andMatrixInput_13, decoded_andMatrixOutputs_andMatrixInput_14}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] decoded_andMatrixOutputs_lo_lo_4 = {decoded_andMatrixOutputs_lo_lo_hi_2, decoded_andMatrixOutputs_lo_lo_lo}; // @[pla.scala:98:53]
wire [1:0] decoded_andMatrixOutputs_lo_hi_lo = {decoded_andMatrixOutputs_andMatrixInput_11_2, decoded_andMatrixOutputs_andMatrixInput_12}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_andMatrixOutputs_lo_hi_hi_4 = {decoded_andMatrixOutputs_andMatrixInput_9_4, decoded_andMatrixOutputs_andMatrixInput_10_2}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] decoded_andMatrixOutputs_lo_hi_4 = {decoded_andMatrixOutputs_lo_hi_hi_4, decoded_andMatrixOutputs_lo_hi_lo}; // @[pla.scala:98:53]
wire [7:0] decoded_andMatrixOutputs_lo_4 = {decoded_andMatrixOutputs_lo_hi_4, decoded_andMatrixOutputs_lo_lo_4}; // @[pla.scala:98:53]
wire [1:0] decoded_andMatrixOutputs_hi_lo_lo = {decoded_andMatrixOutputs_andMatrixInput_7_4, decoded_andMatrixOutputs_andMatrixInput_8_4}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_andMatrixOutputs_hi_lo_hi_2 = {decoded_andMatrixOutputs_andMatrixInput_5_4, decoded_andMatrixOutputs_andMatrixInput_6_4}; // @[pla.scala:90:45, :98:53]
wire [3:0] decoded_andMatrixOutputs_hi_lo_4 = {decoded_andMatrixOutputs_hi_lo_hi_2, decoded_andMatrixOutputs_hi_lo_lo}; // @[pla.scala:98:53]
wire [1:0] decoded_andMatrixOutputs_hi_hi_lo = {decoded_andMatrixOutputs_andMatrixInput_3_4, decoded_andMatrixOutputs_andMatrixInput_4_4}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] decoded_andMatrixOutputs_hi_hi_hi_hi = {decoded_andMatrixOutputs_andMatrixInput_0_4, decoded_andMatrixOutputs_andMatrixInput_1_4}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoded_andMatrixOutputs_hi_hi_hi_4 = {decoded_andMatrixOutputs_hi_hi_hi_hi, decoded_andMatrixOutputs_andMatrixInput_2_4}; // @[pla.scala:91:29, :98:53]
wire [4:0] decoded_andMatrixOutputs_hi_hi_4 = {decoded_andMatrixOutputs_hi_hi_hi_4, decoded_andMatrixOutputs_hi_hi_lo}; // @[pla.scala:98:53]
wire [8:0] decoded_andMatrixOutputs_hi_4 = {decoded_andMatrixOutputs_hi_hi_4, decoded_andMatrixOutputs_hi_lo_4}; // @[pla.scala:98:53]
wire [16:0] _decoded_andMatrixOutputs_T_4 = {decoded_andMatrixOutputs_hi_4, decoded_andMatrixOutputs_lo_4}; // @[pla.scala:98:53]
wire decoded_andMatrixOutputs_0_2 = &_decoded_andMatrixOutputs_T_4; // @[pla.scala:98:{53,70}]
wire _decoded_orMatrixOutputs_T = decoded_andMatrixOutputs_0_2; // @[pla.scala:98:70, :114:36]
wire decoded_andMatrixOutputs_andMatrixInput_7_5 = decoded_plaInput[29]; // @[pla.scala:77:22, :90:45]
wire [1:0] decoded_andMatrixOutputs_lo_lo_5 = {decoded_andMatrixOutputs_andMatrixInput_8_5, decoded_andMatrixOutputs_andMatrixInput_9_5}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_andMatrixOutputs_lo_hi_hi_5 = {decoded_andMatrixOutputs_andMatrixInput_5_5, decoded_andMatrixOutputs_andMatrixInput_6_5}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_andMatrixOutputs_lo_hi_5 = {decoded_andMatrixOutputs_lo_hi_hi_5, decoded_andMatrixOutputs_andMatrixInput_7_5}; // @[pla.scala:90:45, :98:53]
wire [4:0] decoded_andMatrixOutputs_lo_5 = {decoded_andMatrixOutputs_lo_hi_5, decoded_andMatrixOutputs_lo_lo_5}; // @[pla.scala:98:53]
wire [1:0] decoded_andMatrixOutputs_hi_lo_5 = {decoded_andMatrixOutputs_andMatrixInput_3_5, decoded_andMatrixOutputs_andMatrixInput_4_5}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_andMatrixOutputs_hi_hi_hi_5 = {decoded_andMatrixOutputs_andMatrixInput_0_5, decoded_andMatrixOutputs_andMatrixInput_1_5}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_andMatrixOutputs_hi_hi_5 = {decoded_andMatrixOutputs_hi_hi_hi_5, decoded_andMatrixOutputs_andMatrixInput_2_5}; // @[pla.scala:91:29, :98:53]
wire [4:0] decoded_andMatrixOutputs_hi_5 = {decoded_andMatrixOutputs_hi_hi_5, decoded_andMatrixOutputs_hi_lo_5}; // @[pla.scala:98:53]
wire [9:0] _decoded_andMatrixOutputs_T_5 = {decoded_andMatrixOutputs_hi_5, decoded_andMatrixOutputs_lo_5}; // @[pla.scala:98:53]
wire decoded_andMatrixOutputs_5_2 = &_decoded_andMatrixOutputs_T_5; // @[pla.scala:98:{53,70}]
wire _decoded_orMatrixOutputs_T_2 = decoded_andMatrixOutputs_5_2; // @[pla.scala:98:70, :114:36]
wire decoded_andMatrixOutputs_andMatrixInput_0_6 = decoded_plaInput[30]; // @[pla.scala:77:22, :90:45]
wire [1:0] _decoded_andMatrixOutputs_T_6 = {decoded_andMatrixOutputs_andMatrixInput_0_6, decoded_andMatrixOutputs_andMatrixInput_1_6}; // @[pla.scala:90:45, :91:29, :98:53]
wire decoded_andMatrixOutputs_2_2 = &_decoded_andMatrixOutputs_T_6; // @[pla.scala:98:{53,70}]
wire [1:0] _decoded_orMatrixOutputs_T_3 = {decoded_andMatrixOutputs_3_2, decoded_andMatrixOutputs_2_2}; // @[pla.scala:98:70, :114:19]
wire _decoded_orMatrixOutputs_T_4 = |_decoded_orMatrixOutputs_T_3; // @[pla.scala:114:{19,36}]
wire [1:0] decoded_orMatrixOutputs_lo_hi = {_decoded_orMatrixOutputs_T, 1'h0}; // @[pla.scala:102:36, :114:36]
wire [3:0] decoded_orMatrixOutputs_lo = {decoded_orMatrixOutputs_lo_hi, 2'h0}; // @[pla.scala:102:36]
wire [1:0] decoded_orMatrixOutputs_hi_lo = {_decoded_orMatrixOutputs_T_2, _decoded_orMatrixOutputs_T_1}; // @[pla.scala:102:36, :114:36]
wire [1:0] decoded_orMatrixOutputs_hi_hi_hi = {_decoded_orMatrixOutputs_T_6, _decoded_orMatrixOutputs_T_5}; // @[pla.scala:102:36, :114:36]
wire [2:0] decoded_orMatrixOutputs_hi_hi = {decoded_orMatrixOutputs_hi_hi_hi, _decoded_orMatrixOutputs_T_4}; // @[pla.scala:102:36, :114:36]
wire [4:0] decoded_orMatrixOutputs_hi = {decoded_orMatrixOutputs_hi_hi, decoded_orMatrixOutputs_hi_lo}; // @[pla.scala:102:36]
wire [8:0] decoded_orMatrixOutputs = {decoded_orMatrixOutputs_hi, decoded_orMatrixOutputs_lo}; // @[pla.scala:102:36]
wire _decoded_invMatrixOutputs_T = decoded_orMatrixOutputs[0]; // @[pla.scala:102:36, :124:31]
wire _decoded_invMatrixOutputs_T_1 = decoded_orMatrixOutputs[1]; // @[pla.scala:102:36, :124:31]
wire _decoded_invMatrixOutputs_T_2 = decoded_orMatrixOutputs[2]; // @[pla.scala:102:36, :124:31]
wire _decoded_invMatrixOutputs_T_3 = decoded_orMatrixOutputs[3]; // @[pla.scala:102:36, :124:31]
wire _decoded_invMatrixOutputs_T_4 = decoded_orMatrixOutputs[4]; // @[pla.scala:102:36, :124:31]
wire _decoded_invMatrixOutputs_T_5 = decoded_orMatrixOutputs[5]; // @[pla.scala:102:36, :124:31]
wire _decoded_invMatrixOutputs_T_6 = decoded_orMatrixOutputs[6]; // @[pla.scala:102:36, :124:31]
wire _decoded_invMatrixOutputs_T_7 = decoded_orMatrixOutputs[7]; // @[pla.scala:102:36, :124:31]
wire _decoded_invMatrixOutputs_T_8 = decoded_orMatrixOutputs[8]; // @[pla.scala:102:36, :124:31]
wire [1:0] decoded_invMatrixOutputs_lo_lo = {_decoded_invMatrixOutputs_T_1, _decoded_invMatrixOutputs_T}; // @[pla.scala:120:37, :124:31]
wire [1:0] decoded_invMatrixOutputs_lo_hi = {_decoded_invMatrixOutputs_T_3, _decoded_invMatrixOutputs_T_2}; // @[pla.scala:120:37, :124:31]
wire [3:0] decoded_invMatrixOutputs_lo = {decoded_invMatrixOutputs_lo_hi, decoded_invMatrixOutputs_lo_lo}; // @[pla.scala:120:37]
wire [1:0] decoded_invMatrixOutputs_hi_lo = {_decoded_invMatrixOutputs_T_5, _decoded_invMatrixOutputs_T_4}; // @[pla.scala:120:37, :124:31]
wire [1:0] decoded_invMatrixOutputs_hi_hi_hi = {_decoded_invMatrixOutputs_T_8, _decoded_invMatrixOutputs_T_7}; // @[pla.scala:120:37, :124:31]
wire [2:0] decoded_invMatrixOutputs_hi_hi = {decoded_invMatrixOutputs_hi_hi_hi, _decoded_invMatrixOutputs_T_6}; // @[pla.scala:120:37, :124:31]
wire [4:0] decoded_invMatrixOutputs_hi = {decoded_invMatrixOutputs_hi_hi, decoded_invMatrixOutputs_hi_lo}; // @[pla.scala:120:37]
assign decoded_invMatrixOutputs = {decoded_invMatrixOutputs_hi, decoded_invMatrixOutputs_lo}; // @[pla.scala:120:37]
assign decoded = decoded_invMatrixOutputs; // @[pla.scala:81:23, :120:37]
wire insn_call = system_insn & decoded[8]; // @[pla.scala:81:23]
wire insn_break = system_insn & decoded[7]; // @[pla.scala:81:23]
wire insn_ret = system_insn & decoded[6]; // @[pla.scala:81:23]
wire insn_cease = system_insn & decoded[5]; // @[pla.scala:81:23]
wire insn_wfi = system_insn & decoded[4]; // @[pla.scala:81:23]
wire [11:0] addr = io_decode_0_inst_0[31:20]; // @[CSR.scala:377:7, :897:27]
wire [11:0] io_decode_0_fp_csr_plaInput = addr; // @[pla.scala:77:22]
wire [11:0] io_decode_0_vector_csr_plaInput = addr; // @[pla.scala:77:22]
wire [11:0] io_decode_0_read_illegal_plaInput = addr; // @[pla.scala:77:22]
wire [11:0] io_decode_0_read_illegal_plaInput_1 = addr; // @[pla.scala:77:22]
wire [31:0] decoded_invInputs_1 = ~decoded_plaInput_1; // @[pla.scala:77:22, :78:21]
wire [8:0] decoded_invMatrixOutputs_1; // @[pla.scala:120:37]
wire [8:0] decoded_1; // @[pla.scala:81:23]
wire decoded_andMatrixOutputs_andMatrixInput_0_7 = decoded_invInputs_1[20]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_1_7 = decoded_invInputs_1[21]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_1_8 = decoded_invInputs_1[21]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_2_6 = decoded_invInputs_1[22]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_2_7 = decoded_invInputs_1[22]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_1_9 = decoded_invInputs_1[22]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_3_6 = decoded_invInputs_1[23]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_3_7 = decoded_invInputs_1[23]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_2_8 = decoded_invInputs_1[23]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_1_10 = decoded_invInputs_1[23]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_1_12 = decoded_invInputs_1[23]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_4_6 = decoded_invInputs_1[24]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_4_7 = decoded_invInputs_1[24]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_3_8 = decoded_invInputs_1[24]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_2_9 = decoded_invInputs_1[24]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_2_11 = decoded_invInputs_1[24]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_5_6 = decoded_invInputs_1[25]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_5_7 = decoded_invInputs_1[25]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_4_8 = decoded_invInputs_1[25]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_3_9 = decoded_invInputs_1[25]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_3_11 = decoded_invInputs_1[25]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_6_6 = decoded_invInputs_1[26]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_6_7 = decoded_invInputs_1[26]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_5_8 = decoded_invInputs_1[26]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_4_9 = decoded_invInputs_1[26]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_11_5 = decoded_invInputs_1[26]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_4_11 = decoded_invInputs_1[26]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_7_6 = decoded_invInputs_1[27]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_7_7 = decoded_invInputs_1[27]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_6_8 = decoded_invInputs_1[27]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_5_9 = decoded_invInputs_1[27]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_12_1 = decoded_invInputs_1[27]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_5_11 = decoded_invInputs_1[27]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_8_6 = decoded_invInputs_1[28]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_8_7 = decoded_invInputs_1[28]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_9_6 = decoded_invInputs_1[29]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_9_7 = decoded_invInputs_1[29]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_7_9 = decoded_invInputs_1[29]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_14_1 = decoded_invInputs_1[29]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_10_3 = decoded_invInputs_1[30]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_10_4 = decoded_invInputs_1[30]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_8_8 = decoded_invInputs_1[30]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_8_9 = decoded_invInputs_1[30]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_15_1 = decoded_invInputs_1[30]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_8_11 = decoded_invInputs_1[30]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_11_3 = decoded_invInputs_1[31]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_11_4 = decoded_invInputs_1[31]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_9_8 = decoded_invInputs_1[31]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_9_9 = decoded_invInputs_1[31]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_16_1 = decoded_invInputs_1[31]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_9_11 = decoded_invInputs_1[31]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_1_13 = decoded_invInputs_1[31]; // @[pla.scala:78:21, :91:29]
wire [1:0] decoded_andMatrixOutputs_lo_lo_hi_3 = {decoded_andMatrixOutputs_andMatrixInput_9_6, decoded_andMatrixOutputs_andMatrixInput_10_3}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_andMatrixOutputs_lo_lo_6 = {decoded_andMatrixOutputs_lo_lo_hi_3, decoded_andMatrixOutputs_andMatrixInput_11_3}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_andMatrixOutputs_lo_hi_hi_6 = {decoded_andMatrixOutputs_andMatrixInput_6_6, decoded_andMatrixOutputs_andMatrixInput_7_6}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_andMatrixOutputs_lo_hi_6 = {decoded_andMatrixOutputs_lo_hi_hi_6, decoded_andMatrixOutputs_andMatrixInput_8_6}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_andMatrixOutputs_lo_6 = {decoded_andMatrixOutputs_lo_hi_6, decoded_andMatrixOutputs_lo_lo_6}; // @[pla.scala:98:53]
wire [1:0] decoded_andMatrixOutputs_hi_lo_hi_3 = {decoded_andMatrixOutputs_andMatrixInput_3_6, decoded_andMatrixOutputs_andMatrixInput_4_6}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_andMatrixOutputs_hi_lo_6 = {decoded_andMatrixOutputs_hi_lo_hi_3, decoded_andMatrixOutputs_andMatrixInput_5_6}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_andMatrixOutputs_hi_hi_hi_6 = {decoded_andMatrixOutputs_andMatrixInput_0_7, decoded_andMatrixOutputs_andMatrixInput_1_7}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_andMatrixOutputs_hi_hi_6 = {decoded_andMatrixOutputs_hi_hi_hi_6, decoded_andMatrixOutputs_andMatrixInput_2_6}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_andMatrixOutputs_hi_6 = {decoded_andMatrixOutputs_hi_hi_6, decoded_andMatrixOutputs_hi_lo_6}; // @[pla.scala:98:53]
wire [11:0] _decoded_andMatrixOutputs_T_7 = {decoded_andMatrixOutputs_hi_6, decoded_andMatrixOutputs_lo_6}; // @[pla.scala:98:53]
wire decoded_andMatrixOutputs_6_2_1 = &_decoded_andMatrixOutputs_T_7; // @[pla.scala:98:{53,70}]
wire _decoded_orMatrixOutputs_T_13 = decoded_andMatrixOutputs_6_2_1; // @[pla.scala:98:70, :114:36]
wire decoded_andMatrixOutputs_andMatrixInput_0_8 = decoded_plaInput_1[20]; // @[pla.scala:77:22, :90:45]
wire [1:0] decoded_andMatrixOutputs_lo_lo_hi_4 = {decoded_andMatrixOutputs_andMatrixInput_9_7, decoded_andMatrixOutputs_andMatrixInput_10_4}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_andMatrixOutputs_lo_lo_7 = {decoded_andMatrixOutputs_lo_lo_hi_4, decoded_andMatrixOutputs_andMatrixInput_11_4}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_andMatrixOutputs_lo_hi_hi_7 = {decoded_andMatrixOutputs_andMatrixInput_6_7, decoded_andMatrixOutputs_andMatrixInput_7_7}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_andMatrixOutputs_lo_hi_7 = {decoded_andMatrixOutputs_lo_hi_hi_7, decoded_andMatrixOutputs_andMatrixInput_8_7}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_andMatrixOutputs_lo_7 = {decoded_andMatrixOutputs_lo_hi_7, decoded_andMatrixOutputs_lo_lo_7}; // @[pla.scala:98:53]
wire [1:0] decoded_andMatrixOutputs_hi_lo_hi_4 = {decoded_andMatrixOutputs_andMatrixInput_3_7, decoded_andMatrixOutputs_andMatrixInput_4_7}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_andMatrixOutputs_hi_lo_7 = {decoded_andMatrixOutputs_hi_lo_hi_4, decoded_andMatrixOutputs_andMatrixInput_5_7}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_andMatrixOutputs_hi_hi_hi_7 = {decoded_andMatrixOutputs_andMatrixInput_0_8, decoded_andMatrixOutputs_andMatrixInput_1_8}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_andMatrixOutputs_hi_hi_7 = {decoded_andMatrixOutputs_hi_hi_hi_7, decoded_andMatrixOutputs_andMatrixInput_2_7}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_andMatrixOutputs_hi_7 = {decoded_andMatrixOutputs_hi_hi_7, decoded_andMatrixOutputs_hi_lo_7}; // @[pla.scala:98:53]
wire [11:0] _decoded_andMatrixOutputs_T_8 = {decoded_andMatrixOutputs_hi_7, decoded_andMatrixOutputs_lo_7}; // @[pla.scala:98:53]
wire decoded_andMatrixOutputs_4_2_1 = &_decoded_andMatrixOutputs_T_8; // @[pla.scala:98:{53,70}]
wire _decoded_orMatrixOutputs_T_12 = decoded_andMatrixOutputs_4_2_1; // @[pla.scala:98:70, :114:36]
wire decoded_andMatrixOutputs_andMatrixInput_0_9 = decoded_plaInput_1[0]; // @[pla.scala:77:22, :90:45]
wire decoded_andMatrixOutputs_andMatrixInput_0_11 = decoded_plaInput_1[0]; // @[pla.scala:77:22, :90:45]
wire decoded_andMatrixOutputs_andMatrixInput_7_8 = decoded_plaInput_1[28]; // @[pla.scala:77:22, :90:45]
wire decoded_andMatrixOutputs_andMatrixInput_6_9 = decoded_plaInput_1[28]; // @[pla.scala:77:22, :90:45]
wire decoded_andMatrixOutputs_andMatrixInput_13_1 = decoded_plaInput_1[28]; // @[pla.scala:77:22, :90:45]
wire decoded_andMatrixOutputs_andMatrixInput_6_11 = decoded_plaInput_1[28]; // @[pla.scala:77:22, :90:45]
wire [1:0] decoded_andMatrixOutputs_lo_lo_8 = {decoded_andMatrixOutputs_andMatrixInput_8_8, decoded_andMatrixOutputs_andMatrixInput_9_8}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_andMatrixOutputs_lo_hi_hi_8 = {decoded_andMatrixOutputs_andMatrixInput_5_8, decoded_andMatrixOutputs_andMatrixInput_6_8}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_andMatrixOutputs_lo_hi_8 = {decoded_andMatrixOutputs_lo_hi_hi_8, decoded_andMatrixOutputs_andMatrixInput_7_8}; // @[pla.scala:90:45, :98:53]
wire [4:0] decoded_andMatrixOutputs_lo_8 = {decoded_andMatrixOutputs_lo_hi_8, decoded_andMatrixOutputs_lo_lo_8}; // @[pla.scala:98:53]
wire [1:0] decoded_andMatrixOutputs_hi_lo_8 = {decoded_andMatrixOutputs_andMatrixInput_3_8, decoded_andMatrixOutputs_andMatrixInput_4_8}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_andMatrixOutputs_hi_hi_hi_8 = {decoded_andMatrixOutputs_andMatrixInput_0_9, decoded_andMatrixOutputs_andMatrixInput_1_9}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_andMatrixOutputs_hi_hi_8 = {decoded_andMatrixOutputs_hi_hi_hi_8, decoded_andMatrixOutputs_andMatrixInput_2_8}; // @[pla.scala:91:29, :98:53]
wire [4:0] decoded_andMatrixOutputs_hi_8 = {decoded_andMatrixOutputs_hi_hi_8, decoded_andMatrixOutputs_hi_lo_8}; // @[pla.scala:98:53]
wire [9:0] _decoded_andMatrixOutputs_T_9 = {decoded_andMatrixOutputs_hi_8, decoded_andMatrixOutputs_lo_8}; // @[pla.scala:98:53]
wire decoded_andMatrixOutputs_3_2_1 = &_decoded_andMatrixOutputs_T_9; // @[pla.scala:98:{53,70}]
wire decoded_andMatrixOutputs_andMatrixInput_0_10 = decoded_plaInput_1[22]; // @[pla.scala:77:22, :90:45]
wire decoded_andMatrixOutputs_andMatrixInput_0_12 = decoded_plaInput_1[22]; // @[pla.scala:77:22, :90:45]
wire [1:0] decoded_andMatrixOutputs_lo_lo_9 = {decoded_andMatrixOutputs_andMatrixInput_8_9, decoded_andMatrixOutputs_andMatrixInput_9_9}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_andMatrixOutputs_lo_hi_hi_9 = {decoded_andMatrixOutputs_andMatrixInput_5_9, decoded_andMatrixOutputs_andMatrixInput_6_9}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_andMatrixOutputs_lo_hi_9 = {decoded_andMatrixOutputs_lo_hi_hi_9, decoded_andMatrixOutputs_andMatrixInput_7_9}; // @[pla.scala:91:29, :98:53]
wire [4:0] decoded_andMatrixOutputs_lo_9 = {decoded_andMatrixOutputs_lo_hi_9, decoded_andMatrixOutputs_lo_lo_9}; // @[pla.scala:98:53]
wire [1:0] decoded_andMatrixOutputs_hi_lo_9 = {decoded_andMatrixOutputs_andMatrixInput_3_9, decoded_andMatrixOutputs_andMatrixInput_4_9}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_andMatrixOutputs_hi_hi_hi_9 = {decoded_andMatrixOutputs_andMatrixInput_0_10, decoded_andMatrixOutputs_andMatrixInput_1_10}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_andMatrixOutputs_hi_hi_9 = {decoded_andMatrixOutputs_hi_hi_hi_9, decoded_andMatrixOutputs_andMatrixInput_2_9}; // @[pla.scala:91:29, :98:53]
wire [4:0] decoded_andMatrixOutputs_hi_9 = {decoded_andMatrixOutputs_hi_hi_9, decoded_andMatrixOutputs_hi_lo_9}; // @[pla.scala:98:53]
wire [9:0] _decoded_andMatrixOutputs_T_10 = {decoded_andMatrixOutputs_hi_9, decoded_andMatrixOutputs_lo_9}; // @[pla.scala:98:53]
wire decoded_andMatrixOutputs_1_2_1 = &_decoded_andMatrixOutputs_T_10; // @[pla.scala:98:{53,70}]
wire _decoded_orMatrixOutputs_T_8 = decoded_andMatrixOutputs_1_2_1; // @[pla.scala:98:70, :114:36]
wire decoded_andMatrixOutputs_andMatrixInput_1_11 = decoded_plaInput_1[1]; // @[pla.scala:77:22, :90:45]
wire decoded_andMatrixOutputs_andMatrixInput_2_10 = decoded_invInputs_1[2]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_3_10 = decoded_invInputs_1[3]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_4_10 = decoded_plaInput_1[4]; // @[pla.scala:77:22, :90:45]
wire decoded_andMatrixOutputs_andMatrixInput_5_10 = decoded_plaInput_1[5]; // @[pla.scala:77:22, :90:45]
wire decoded_andMatrixOutputs_andMatrixInput_6_10 = decoded_plaInput_1[6]; // @[pla.scala:77:22, :90:45]
wire decoded_andMatrixOutputs_andMatrixInput_7_10 = decoded_invInputs_1[7]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_8_10 = decoded_invInputs_1[8]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_9_10 = decoded_invInputs_1[9]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_10_5 = decoded_plaInput_1[25]; // @[pla.scala:77:22, :90:45]
wire [1:0] decoded_andMatrixOutputs_lo_lo_lo_1 = {decoded_andMatrixOutputs_andMatrixInput_15_1, decoded_andMatrixOutputs_andMatrixInput_16_1}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_andMatrixOutputs_lo_lo_hi_5 = {decoded_andMatrixOutputs_andMatrixInput_13_1, decoded_andMatrixOutputs_andMatrixInput_14_1}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] decoded_andMatrixOutputs_lo_lo_10 = {decoded_andMatrixOutputs_lo_lo_hi_5, decoded_andMatrixOutputs_lo_lo_lo_1}; // @[pla.scala:98:53]
wire [1:0] decoded_andMatrixOutputs_lo_hi_lo_1 = {decoded_andMatrixOutputs_andMatrixInput_11_5, decoded_andMatrixOutputs_andMatrixInput_12_1}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_andMatrixOutputs_lo_hi_hi_10 = {decoded_andMatrixOutputs_andMatrixInput_9_10, decoded_andMatrixOutputs_andMatrixInput_10_5}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] decoded_andMatrixOutputs_lo_hi_10 = {decoded_andMatrixOutputs_lo_hi_hi_10, decoded_andMatrixOutputs_lo_hi_lo_1}; // @[pla.scala:98:53]
wire [7:0] decoded_andMatrixOutputs_lo_10 = {decoded_andMatrixOutputs_lo_hi_10, decoded_andMatrixOutputs_lo_lo_10}; // @[pla.scala:98:53]
wire [1:0] decoded_andMatrixOutputs_hi_lo_lo_1 = {decoded_andMatrixOutputs_andMatrixInput_7_10, decoded_andMatrixOutputs_andMatrixInput_8_10}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_andMatrixOutputs_hi_lo_hi_5 = {decoded_andMatrixOutputs_andMatrixInput_5_10, decoded_andMatrixOutputs_andMatrixInput_6_10}; // @[pla.scala:90:45, :98:53]
wire [3:0] decoded_andMatrixOutputs_hi_lo_10 = {decoded_andMatrixOutputs_hi_lo_hi_5, decoded_andMatrixOutputs_hi_lo_lo_1}; // @[pla.scala:98:53]
wire [1:0] decoded_andMatrixOutputs_hi_hi_lo_1 = {decoded_andMatrixOutputs_andMatrixInput_3_10, decoded_andMatrixOutputs_andMatrixInput_4_10}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] decoded_andMatrixOutputs_hi_hi_hi_hi_1 = {decoded_andMatrixOutputs_andMatrixInput_0_11, decoded_andMatrixOutputs_andMatrixInput_1_11}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoded_andMatrixOutputs_hi_hi_hi_10 = {decoded_andMatrixOutputs_hi_hi_hi_hi_1, decoded_andMatrixOutputs_andMatrixInput_2_10}; // @[pla.scala:91:29, :98:53]
wire [4:0] decoded_andMatrixOutputs_hi_hi_10 = {decoded_andMatrixOutputs_hi_hi_hi_10, decoded_andMatrixOutputs_hi_hi_lo_1}; // @[pla.scala:98:53]
wire [8:0] decoded_andMatrixOutputs_hi_10 = {decoded_andMatrixOutputs_hi_hi_10, decoded_andMatrixOutputs_hi_lo_10}; // @[pla.scala:98:53]
wire [16:0] _decoded_andMatrixOutputs_T_11 = {decoded_andMatrixOutputs_hi_10, decoded_andMatrixOutputs_lo_10}; // @[pla.scala:98:53]
wire decoded_andMatrixOutputs_0_2_1 = &_decoded_andMatrixOutputs_T_11; // @[pla.scala:98:{53,70}]
wire _decoded_orMatrixOutputs_T_7 = decoded_andMatrixOutputs_0_2_1; // @[pla.scala:98:70, :114:36]
wire decoded_andMatrixOutputs_andMatrixInput_7_11 = decoded_plaInput_1[29]; // @[pla.scala:77:22, :90:45]
wire [1:0] decoded_andMatrixOutputs_lo_lo_11 = {decoded_andMatrixOutputs_andMatrixInput_8_11, decoded_andMatrixOutputs_andMatrixInput_9_11}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_andMatrixOutputs_lo_hi_hi_11 = {decoded_andMatrixOutputs_andMatrixInput_5_11, decoded_andMatrixOutputs_andMatrixInput_6_11}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_andMatrixOutputs_lo_hi_11 = {decoded_andMatrixOutputs_lo_hi_hi_11, decoded_andMatrixOutputs_andMatrixInput_7_11}; // @[pla.scala:90:45, :98:53]
wire [4:0] decoded_andMatrixOutputs_lo_11 = {decoded_andMatrixOutputs_lo_hi_11, decoded_andMatrixOutputs_lo_lo_11}; // @[pla.scala:98:53]
wire [1:0] decoded_andMatrixOutputs_hi_lo_11 = {decoded_andMatrixOutputs_andMatrixInput_3_11, decoded_andMatrixOutputs_andMatrixInput_4_11}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_andMatrixOutputs_hi_hi_hi_11 = {decoded_andMatrixOutputs_andMatrixInput_0_12, decoded_andMatrixOutputs_andMatrixInput_1_12}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_andMatrixOutputs_hi_hi_11 = {decoded_andMatrixOutputs_hi_hi_hi_11, decoded_andMatrixOutputs_andMatrixInput_2_11}; // @[pla.scala:91:29, :98:53]
wire [4:0] decoded_andMatrixOutputs_hi_11 = {decoded_andMatrixOutputs_hi_hi_11, decoded_andMatrixOutputs_hi_lo_11}; // @[pla.scala:98:53]
wire [9:0] _decoded_andMatrixOutputs_T_12 = {decoded_andMatrixOutputs_hi_11, decoded_andMatrixOutputs_lo_11}; // @[pla.scala:98:53]
wire decoded_andMatrixOutputs_5_2_1 = &_decoded_andMatrixOutputs_T_12; // @[pla.scala:98:{53,70}]
wire _decoded_orMatrixOutputs_T_9 = decoded_andMatrixOutputs_5_2_1; // @[pla.scala:98:70, :114:36]
wire decoded_andMatrixOutputs_andMatrixInput_0_13 = decoded_plaInput_1[30]; // @[pla.scala:77:22, :90:45]
wire [1:0] _decoded_andMatrixOutputs_T_13 = {decoded_andMatrixOutputs_andMatrixInput_0_13, decoded_andMatrixOutputs_andMatrixInput_1_13}; // @[pla.scala:90:45, :91:29, :98:53]
wire decoded_andMatrixOutputs_2_2_1 = &_decoded_andMatrixOutputs_T_13; // @[pla.scala:98:{53,70}]
wire [1:0] _decoded_orMatrixOutputs_T_10 = {decoded_andMatrixOutputs_3_2_1, decoded_andMatrixOutputs_2_2_1}; // @[pla.scala:98:70, :114:19]
wire _decoded_orMatrixOutputs_T_11 = |_decoded_orMatrixOutputs_T_10; // @[pla.scala:114:{19,36}]
wire [1:0] decoded_orMatrixOutputs_lo_hi_1 = {_decoded_orMatrixOutputs_T_7, 1'h0}; // @[pla.scala:102:36, :114:36]
wire [3:0] decoded_orMatrixOutputs_lo_1 = {decoded_orMatrixOutputs_lo_hi_1, 2'h0}; // @[pla.scala:102:36]
wire [1:0] decoded_orMatrixOutputs_hi_lo_1 = {_decoded_orMatrixOutputs_T_9, _decoded_orMatrixOutputs_T_8}; // @[pla.scala:102:36, :114:36]
wire [1:0] decoded_orMatrixOutputs_hi_hi_hi_1 = {_decoded_orMatrixOutputs_T_13, _decoded_orMatrixOutputs_T_12}; // @[pla.scala:102:36, :114:36]
wire [2:0] decoded_orMatrixOutputs_hi_hi_1 = {decoded_orMatrixOutputs_hi_hi_hi_1, _decoded_orMatrixOutputs_T_11}; // @[pla.scala:102:36, :114:36]
wire [4:0] decoded_orMatrixOutputs_hi_1 = {decoded_orMatrixOutputs_hi_hi_1, decoded_orMatrixOutputs_hi_lo_1}; // @[pla.scala:102:36]
wire [8:0] decoded_orMatrixOutputs_1 = {decoded_orMatrixOutputs_hi_1, decoded_orMatrixOutputs_lo_1}; // @[pla.scala:102:36]
wire _decoded_invMatrixOutputs_T_9 = decoded_orMatrixOutputs_1[0]; // @[pla.scala:102:36, :124:31]
wire _decoded_invMatrixOutputs_T_10 = decoded_orMatrixOutputs_1[1]; // @[pla.scala:102:36, :124:31]
wire _decoded_invMatrixOutputs_T_11 = decoded_orMatrixOutputs_1[2]; // @[pla.scala:102:36, :124:31]
wire _decoded_invMatrixOutputs_T_12 = decoded_orMatrixOutputs_1[3]; // @[pla.scala:102:36, :124:31]
wire _decoded_invMatrixOutputs_T_13 = decoded_orMatrixOutputs_1[4]; // @[pla.scala:102:36, :124:31]
wire _decoded_invMatrixOutputs_T_14 = decoded_orMatrixOutputs_1[5]; // @[pla.scala:102:36, :124:31]
wire _decoded_invMatrixOutputs_T_15 = decoded_orMatrixOutputs_1[6]; // @[pla.scala:102:36, :124:31]
wire _decoded_invMatrixOutputs_T_16 = decoded_orMatrixOutputs_1[7]; // @[pla.scala:102:36, :124:31]
wire _decoded_invMatrixOutputs_T_17 = decoded_orMatrixOutputs_1[8]; // @[pla.scala:102:36, :124:31]
wire [1:0] decoded_invMatrixOutputs_lo_lo_1 = {_decoded_invMatrixOutputs_T_10, _decoded_invMatrixOutputs_T_9}; // @[pla.scala:120:37, :124:31]
wire [1:0] decoded_invMatrixOutputs_lo_hi_1 = {_decoded_invMatrixOutputs_T_12, _decoded_invMatrixOutputs_T_11}; // @[pla.scala:120:37, :124:31]
wire [3:0] decoded_invMatrixOutputs_lo_1 = {decoded_invMatrixOutputs_lo_hi_1, decoded_invMatrixOutputs_lo_lo_1}; // @[pla.scala:120:37]
wire [1:0] decoded_invMatrixOutputs_hi_lo_1 = {_decoded_invMatrixOutputs_T_14, _decoded_invMatrixOutputs_T_13}; // @[pla.scala:120:37, :124:31]
wire [1:0] decoded_invMatrixOutputs_hi_hi_hi_1 = {_decoded_invMatrixOutputs_T_17, _decoded_invMatrixOutputs_T_16}; // @[pla.scala:120:37, :124:31]
wire [2:0] decoded_invMatrixOutputs_hi_hi_1 = {decoded_invMatrixOutputs_hi_hi_hi_1, _decoded_invMatrixOutputs_T_15}; // @[pla.scala:120:37, :124:31]
wire [4:0] decoded_invMatrixOutputs_hi_1 = {decoded_invMatrixOutputs_hi_hi_1, decoded_invMatrixOutputs_hi_lo_1}; // @[pla.scala:120:37]
assign decoded_invMatrixOutputs_1 = {decoded_invMatrixOutputs_hi_1, decoded_invMatrixOutputs_lo_1}; // @[pla.scala:120:37]
assign decoded_1 = decoded_invMatrixOutputs_1; // @[pla.scala:81:23, :120:37]
wire is_break = decoded_1[7]; // @[pla.scala:81:23]
wire is_ret = decoded_1[6]; // @[pla.scala:81:23]
wire is_wfi = decoded_1[4]; // @[pla.scala:81:23]
wire is_sfence = decoded_1[3]; // @[pla.scala:81:23]
wire is_hfence_vvma = decoded_1[2]; // @[pla.scala:81:23]
wire is_hfence_gvma = decoded_1[1]; // @[pla.scala:81:23]
wire is_hlsv = decoded_1[0]; // @[pla.scala:81:23]
wire _is_counter_T = addr > 12'hBFF; // @[package.scala:213:47]
wire _is_counter_T_1 = addr < 12'hC20; // @[package.scala:213:60]
wire _is_counter_T_2 = _is_counter_T & _is_counter_T_1; // @[package.scala:213:{47,55,60}]
wire _is_counter_T_3 = addr > 12'hC7F; // @[package.scala:213:47]
wire _is_counter_T_4 = addr < 12'hCA0; // @[package.scala:213:60]
wire _is_counter_T_5 = _is_counter_T_3 & _is_counter_T_4; // @[package.scala:213:{47,55,60}]
wire is_counter = _is_counter_T_2 | _is_counter_T_5; // @[package.scala:213:55]
wire _allow_wfi_T_1 = _allow_wfi_T; // @[CSR.scala:906:{42,61}]
wire _allow_wfi_T_2 = ~reg_mstatus_tw; // @[CSR.scala:395:28, :906:74]
wire _allow_wfi_T_6 = _allow_wfi_T_2; // @[CSR.scala:906:{74,90}]
wire _allow_wfi_T_3 = ~reg_mstatus_v; // @[CSR.scala:395:28, :906:94]
wire allow_wfi = _allow_wfi_T_1 | _allow_wfi_T_6; // @[CSR.scala:906:{42,71,90}]
wire _allow_sfence_vma_T_1 = _allow_sfence_vma_T; // @[CSR.scala:907:{41,60}]
wire _allow_sfence_vma_T_2 = ~reg_mstatus_v & reg_mstatus_tvm; // @[CSR.scala:395:28, :907:77]
wire _allow_sfence_vma_T_3 = ~_allow_sfence_vma_T_2; // @[CSR.scala:907:{73,77}]
wire allow_sfence_vma = _allow_sfence_vma_T_1 | _allow_sfence_vma_T_3; // @[CSR.scala:907:{41,70,73}]
wire _allow_hfence_vvma_T = ~reg_mstatus_v; // @[CSR.scala:395:28, :906:94, :908:53]
wire _allow_hfence_vvma_T_1 = |reg_mstatus_prv; // @[CSR.scala:395:28, :908:88]
wire _allow_hfence_vvma_T_2 = _allow_hfence_vvma_T & _allow_hfence_vvma_T_1; // @[CSR.scala:908:{53,68,88}]
wire _allow_hlsv_T = ~reg_mstatus_v; // @[CSR.scala:395:28, :906:94, :909:46]
wire _allow_hlsv_T_1 = |reg_mstatus_prv; // @[CSR.scala:395:28, :908:88, :909:81]
wire _allow_hlsv_T_2 = _allow_hlsv_T_1; // @[CSR.scala:909:{81,92}]
wire _allow_hlsv_T_3 = _allow_hlsv_T & _allow_hlsv_T_2; // @[CSR.scala:909:{46,61,92}]
wire _allow_sret_T_1 = _allow_sret_T; // @[CSR.scala:910:{43,62}]
wire _allow_sret_T_2 = ~reg_mstatus_v & reg_mstatus_tsr; // @[CSR.scala:395:28, :907:77, :910:79]
wire _allow_sret_T_3 = ~_allow_sret_T_2; // @[CSR.scala:910:{75,79}]
wire allow_sret = _allow_sret_T_1 | _allow_sret_T_3; // @[CSR.scala:910:{43,72,75}]
wire [4:0] counter_addr = addr[4:0]; // @[CSR.scala:897:27, :911:28]
wire [31:0] _GEN_10 = {27'h0, counter_addr}; // @[CSR.scala:911:28, :912:70]
wire [31:0] _GEN_11 = read_mcounteren >> _GEN_10; // @[CSR.scala:532:14, :912:70]
wire [31:0] _allow_counter_T_1; // @[CSR.scala:912:70]
assign _allow_counter_T_1 = _GEN_11; // @[CSR.scala:912:70]
wire [31:0] _io_decode_0_virtual_access_illegal_T_3; // @[CSR.scala:945:36]
assign _io_decode_0_virtual_access_illegal_T_3 = _GEN_11; // @[CSR.scala:912:70, :945:36]
wire _allow_counter_T_2 = _allow_counter_T_1[0]; // @[CSR.scala:912:70]
wire _allow_counter_T_3 = _allow_counter_T | _allow_counter_T_2; // @[CSR.scala:912:{42,52,70}]
wire _allow_counter_T_5 = |reg_mstatus_prv; // @[CSR.scala:395:28, :908:88, :913:46]
wire _allow_counter_T_6 = _allow_counter_T_5; // @[CSR.scala:913:{27,46}]
wire [31:0] _GEN_12 = read_scounteren >> _GEN_10; // @[CSR.scala:536:14, :912:70, :913:75]
wire [31:0] _allow_counter_T_7; // @[CSR.scala:913:75]
assign _allow_counter_T_7 = _GEN_12; // @[CSR.scala:913:75]
wire [31:0] _io_decode_0_virtual_access_illegal_T_11; // @[CSR.scala:945:128]
assign _io_decode_0_virtual_access_illegal_T_11 = _GEN_12; // @[CSR.scala:913:75, :945:128]
wire _allow_counter_T_8 = _allow_counter_T_7[0]; // @[CSR.scala:913:75]
wire _allow_counter_T_9 = _allow_counter_T_6 | _allow_counter_T_8; // @[CSR.scala:913:{27,57,75}]
wire _allow_counter_T_10 = _allow_counter_T_3 & _allow_counter_T_9; // @[CSR.scala:912:{52,86}, :913:57]
wire allow_counter = _allow_counter_T_10; // @[CSR.scala:912:86, :913:91]
wire _allow_counter_T_12 = ~reg_mstatus_v; // @[CSR.scala:395:28, :906:94, :914:30]
wire [31:0] _GEN_13 = 32'h0 >> _GEN_10; // @[CSR.scala:912:70, :914:63]
wire [31:0] _allow_counter_T_14; // @[CSR.scala:914:63]
assign _allow_counter_T_14 = _GEN_13; // @[CSR.scala:914:63]
wire [31:0] _io_decode_0_virtual_access_illegal_T_6; // @[CSR.scala:945:71]
assign _io_decode_0_virtual_access_illegal_T_6 = _GEN_13; // @[CSR.scala:914:63, :945:71]
wire _allow_counter_T_15 = _allow_counter_T_14[0]; // @[CSR.scala:914:63]
wire _io_decode_0_fp_illegal_T = io_status_fs_0 == 2'h0; // @[CSR.scala:377:7, :915:39]
wire _io_decode_0_fp_illegal_T_2 = reg_mstatus_v & _io_decode_0_fp_illegal_T_1; // @[CSR.scala:395:28, :915:{64,83}]
wire _io_decode_0_fp_illegal_T_3 = _io_decode_0_fp_illegal_T | _io_decode_0_fp_illegal_T_2; // @[CSR.scala:915:{39,47,64}]
wire _io_decode_0_fp_illegal_T_4 = reg_misa[5]; // @[CSR.scala:648:25, :915:103]
wire _io_decode_0_fp_illegal_T_5 = ~_io_decode_0_fp_illegal_T_4; // @[CSR.scala:915:{94,103}]
assign _io_decode_0_fp_illegal_T_6 = _io_decode_0_fp_illegal_T_3 | _io_decode_0_fp_illegal_T_5; // @[CSR.scala:915:{47,91,94}]
assign io_decode_0_fp_illegal_0 = _io_decode_0_fp_illegal_T_6; // @[CSR.scala:377:7, :915:91]
wire _io_decode_0_vector_illegal_T_2 = reg_mstatus_v & _io_decode_0_vector_illegal_T_1; // @[CSR.scala:395:28, :916:{68,87}]
wire _io_decode_0_vector_illegal_T_4 = reg_misa[21]; // @[CSR.scala:648:25, :916:107]
wire _io_decode_0_vector_illegal_T_5 = ~_io_decode_0_vector_illegal_T_4; // @[CSR.scala:916:{98,107}]
wire [11:0] io_decode_0_fp_csr_invInputs = ~io_decode_0_fp_csr_plaInput; // @[pla.scala:77:22, :78:21]
wire io_decode_0_fp_csr_invMatrixOutputs; // @[pla.scala:124:31]
wire io_decode_0_fp_csr_plaOutput; // @[pla.scala:81:23]
assign _io_decode_0_fp_csr_T = io_decode_0_fp_csr_plaOutput; // @[pla.scala:81:23]
wire io_decode_0_fp_csr_andMatrixOutputs_andMatrixInput_0 = io_decode_0_fp_csr_invInputs[8]; // @[pla.scala:78:21, :91:29]
wire io_decode_0_fp_csr_andMatrixOutputs_andMatrixInput_1 = io_decode_0_fp_csr_invInputs[9]; // @[pla.scala:78:21, :91:29]
wire io_decode_0_fp_csr_andMatrixOutputs_andMatrixInput_2 = io_decode_0_fp_csr_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire io_decode_0_fp_csr_andMatrixOutputs_andMatrixInput_3 = io_decode_0_fp_csr_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire [1:0] io_decode_0_fp_csr_andMatrixOutputs_lo = {io_decode_0_fp_csr_andMatrixOutputs_andMatrixInput_2, io_decode_0_fp_csr_andMatrixOutputs_andMatrixInput_3}; // @[pla.scala:91:29, :98:53]
wire [1:0] io_decode_0_fp_csr_andMatrixOutputs_hi = {io_decode_0_fp_csr_andMatrixOutputs_andMatrixInput_0, io_decode_0_fp_csr_andMatrixOutputs_andMatrixInput_1}; // @[pla.scala:91:29, :98:53]
wire [3:0] _io_decode_0_fp_csr_andMatrixOutputs_T = {io_decode_0_fp_csr_andMatrixOutputs_hi, io_decode_0_fp_csr_andMatrixOutputs_lo}; // @[pla.scala:98:53]
wire io_decode_0_fp_csr_andMatrixOutputs_0_2 = &_io_decode_0_fp_csr_andMatrixOutputs_T; // @[pla.scala:98:{53,70}]
wire io_decode_0_fp_csr_orMatrixOutputs = io_decode_0_fp_csr_andMatrixOutputs_0_2; // @[pla.scala:98:70, :114:36]
assign io_decode_0_fp_csr_invMatrixOutputs = io_decode_0_fp_csr_orMatrixOutputs; // @[pla.scala:114:36, :124:31]
assign io_decode_0_fp_csr_plaOutput = io_decode_0_fp_csr_invMatrixOutputs; // @[pla.scala:81:23, :124:31]
assign io_decode_0_fp_csr_0 = _io_decode_0_fp_csr_T; // @[Decode.scala:55:116]
wire [11:0] io_decode_0_vector_csr_invInputs = ~io_decode_0_vector_csr_plaInput; // @[pla.scala:77:22, :78:21]
wire _io_decode_0_rocc_illegal_T_4 = reg_misa[23]; // @[CSR.scala:648:25, :919:105]
wire _io_decode_0_rocc_illegal_T_5 = ~_io_decode_0_rocc_illegal_T_4; // @[CSR.scala:919:{96,105}]
wire [1:0] _csr_addr_legal_T = addr[9:8]; // @[CSR.scala:190:36, :897:27]
wire [1:0] _csr_addr_legal_T_6 = addr[9:8]; // @[CSR.scala:190:36, :897:27]
wire [1:0] _io_decode_0_virtual_access_illegal_T_1 = addr[9:8]; // @[CSR.scala:190:36, :897:27]
wire [1:0] _io_decode_0_virtual_access_illegal_T_18 = addr[9:8]; // @[CSR.scala:190:36, :897:27]
wire [1:0] _io_decode_0_virtual_system_illegal_T_9 = addr[9:8]; // @[CSR.scala:190:36, :897:27]
wire _csr_addr_legal_T_1 = reg_mstatus_prv >= _csr_addr_legal_T; // @[CSR.scala:190:36, :395:28, :920:42]
wire csr_addr_legal = _csr_addr_legal_T_1; // @[CSR.scala:920:{42,60}]
wire _csr_addr_legal_T_2 = ~reg_mstatus_v; // @[CSR.scala:395:28, :906:94, :921:28]
wire _csr_addr_legal_T_7 = _csr_addr_legal_T_6 == 2'h2; // @[CSR.scala:190:36, :921:92]
wire _csr_exists_T = addr == 12'h7A0; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_1 = addr == 12'h7A1; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_2 = addr == 12'h7A2; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_3 = addr == 12'h7A3; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_4 = addr == 12'h301; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_5 = addr == 12'h300; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_6 = addr == 12'h305; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_7 = addr == 12'h344; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_8 = addr == 12'h304; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_9 = addr == 12'h340; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_10 = addr == 12'h341; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_11 = addr == 12'h343; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_12 = addr == 12'h342; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_13 = addr == 12'hF14; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_14 = addr == 12'h7B0; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_15 = addr == 12'h7B1; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_16 = addr == 12'h7B2; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_17 = addr == 12'h1; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_18 = addr == 12'h2; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_19 = addr == 12'h3; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_20 = addr == 12'h320; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_21 = addr == 12'hB00; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_22 = addr == 12'hB02; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_23 = addr == 12'h323; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_24 = addr == 12'hB03; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_25 = addr == 12'hC03; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_26 = addr == 12'h324; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_27 = addr == 12'hB04; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_28 = addr == 12'hC04; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_29 = addr == 12'h325; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_30 = addr == 12'hB05; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_31 = addr == 12'hC05; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_32 = addr == 12'h326; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_33 = addr == 12'hB06; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_34 = addr == 12'hC06; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_35 = addr == 12'h327; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_36 = addr == 12'hB07; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_37 = addr == 12'hC07; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_38 = addr == 12'h328; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_39 = addr == 12'hB08; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_40 = addr == 12'hC08; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_41 = addr == 12'h329; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_42 = addr == 12'hB09; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_43 = addr == 12'hC09; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_44 = addr == 12'h32A; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_45 = addr == 12'hB0A; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_46 = addr == 12'hC0A; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_47 = addr == 12'h32B; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_48 = addr == 12'hB0B; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_49 = addr == 12'hC0B; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_50 = addr == 12'h32C; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_51 = addr == 12'hB0C; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_52 = addr == 12'hC0C; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_53 = addr == 12'h32D; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_54 = addr == 12'hB0D; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_55 = addr == 12'hC0D; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_56 = addr == 12'h32E; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_57 = addr == 12'hB0E; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_58 = addr == 12'hC0E; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_59 = addr == 12'h32F; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_60 = addr == 12'hB0F; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_61 = addr == 12'hC0F; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_62 = addr == 12'h330; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_63 = addr == 12'hB10; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_64 = addr == 12'hC10; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_65 = addr == 12'h331; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_66 = addr == 12'hB11; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_67 = addr == 12'hC11; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_68 = addr == 12'h332; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_69 = addr == 12'hB12; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_70 = addr == 12'hC12; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_71 = addr == 12'h333; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_72 = addr == 12'hB13; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_73 = addr == 12'hC13; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_74 = addr == 12'h334; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_75 = addr == 12'hB14; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_76 = addr == 12'hC14; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_77 = addr == 12'h335; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_78 = addr == 12'hB15; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_79 = addr == 12'hC15; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_80 = addr == 12'h336; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_81 = addr == 12'hB16; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_82 = addr == 12'hC16; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_83 = addr == 12'h337; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_84 = addr == 12'hB17; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_85 = addr == 12'hC17; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_86 = addr == 12'h338; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_87 = addr == 12'hB18; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_88 = addr == 12'hC18; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_89 = addr == 12'h339; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_90 = addr == 12'hB19; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_91 = addr == 12'hC19; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_92 = addr == 12'h33A; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_93 = addr == 12'hB1A; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_94 = addr == 12'hC1A; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_95 = addr == 12'h33B; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_96 = addr == 12'hB1B; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_97 = addr == 12'hC1B; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_98 = addr == 12'h33C; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_99 = addr == 12'hB1C; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_100 = addr == 12'hC1C; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_101 = addr == 12'h33D; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_102 = addr == 12'hB1D; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_103 = addr == 12'hC1D; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_104 = addr == 12'h33E; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_105 = addr == 12'hB1E; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_106 = addr == 12'hC1E; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_107 = addr == 12'h33F; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_108 = addr == 12'hB1F; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_109 = addr == 12'hC1F; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_110 = addr == 12'h306; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_111 = addr == 12'hC00; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_112 = addr == 12'hC02; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_113 = addr == 12'h30A; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_114 = addr == 12'h100; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_115 = addr == 12'h144; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_116 = addr == 12'h104; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_117 = addr == 12'h140; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_118 = addr == 12'h142; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_119 = addr == 12'h143; // @[CSR.scala:897:27, :899:93]
wire _GEN_14 = addr == 12'h180; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_120; // @[CSR.scala:899:93]
assign _csr_exists_T_120 = _GEN_14; // @[CSR.scala:899:93]
wire _io_decode_0_read_illegal_T_3; // @[CSR.scala:925:14]
assign _io_decode_0_read_illegal_T_3 = _GEN_14; // @[CSR.scala:899:93, :925:14]
wire _io_decode_0_virtual_access_illegal_T_24; // @[CSR.scala:947:12]
assign _io_decode_0_virtual_access_illegal_T_24 = _GEN_14; // @[CSR.scala:899:93, :947:12]
wire _csr_exists_T_121 = addr == 12'h141; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_122 = addr == 12'h105; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_123 = addr == 12'h106; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_124 = addr == 12'h303; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_125 = addr == 12'h302; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_126 = addr == 12'h10A; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_127 = addr == 12'h3A0; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_128 = addr == 12'h3A2; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_129 = addr == 12'h3B0; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_130 = addr == 12'h3B1; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_131 = addr == 12'h3B2; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_132 = addr == 12'h3B3; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_133 = addr == 12'h3B4; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_134 = addr == 12'h3B5; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_135 = addr == 12'h3B6; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_136 = addr == 12'h3B7; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_137 = addr == 12'h3B8; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_138 = addr == 12'h3B9; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_139 = addr == 12'h3BA; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_140 = addr == 12'h3BB; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_141 = addr == 12'h3BC; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_142 = addr == 12'h3BD; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_143 = addr == 12'h3BE; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_144 = addr == 12'h3BF; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_145 = addr == 12'h7C1; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_146 = addr == 12'hF12; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_147 = addr == 12'hF11; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_148 = addr == 12'hF13; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_149 = addr == 12'hF15; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_150 = _csr_exists_T | _csr_exists_T_1; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_151 = _csr_exists_T_150 | _csr_exists_T_2; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_152 = _csr_exists_T_151 | _csr_exists_T_3; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_153 = _csr_exists_T_152 | _csr_exists_T_4; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_154 = _csr_exists_T_153 | _csr_exists_T_5; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_155 = _csr_exists_T_154 | _csr_exists_T_6; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_156 = _csr_exists_T_155 | _csr_exists_T_7; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_157 = _csr_exists_T_156 | _csr_exists_T_8; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_158 = _csr_exists_T_157 | _csr_exists_T_9; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_159 = _csr_exists_T_158 | _csr_exists_T_10; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_160 = _csr_exists_T_159 | _csr_exists_T_11; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_161 = _csr_exists_T_160 | _csr_exists_T_12; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_162 = _csr_exists_T_161 | _csr_exists_T_13; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_163 = _csr_exists_T_162 | _csr_exists_T_14; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_164 = _csr_exists_T_163 | _csr_exists_T_15; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_165 = _csr_exists_T_164 | _csr_exists_T_16; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_166 = _csr_exists_T_165 | _csr_exists_T_17; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_167 = _csr_exists_T_166 | _csr_exists_T_18; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_168 = _csr_exists_T_167 | _csr_exists_T_19; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_169 = _csr_exists_T_168 | _csr_exists_T_20; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_170 = _csr_exists_T_169 | _csr_exists_T_21; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_171 = _csr_exists_T_170 | _csr_exists_T_22; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_172 = _csr_exists_T_171 | _csr_exists_T_23; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_173 = _csr_exists_T_172 | _csr_exists_T_24; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_174 = _csr_exists_T_173 | _csr_exists_T_25; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_175 = _csr_exists_T_174 | _csr_exists_T_26; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_176 = _csr_exists_T_175 | _csr_exists_T_27; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_177 = _csr_exists_T_176 | _csr_exists_T_28; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_178 = _csr_exists_T_177 | _csr_exists_T_29; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_179 = _csr_exists_T_178 | _csr_exists_T_30; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_180 = _csr_exists_T_179 | _csr_exists_T_31; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_181 = _csr_exists_T_180 | _csr_exists_T_32; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_182 = _csr_exists_T_181 | _csr_exists_T_33; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_183 = _csr_exists_T_182 | _csr_exists_T_34; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_184 = _csr_exists_T_183 | _csr_exists_T_35; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_185 = _csr_exists_T_184 | _csr_exists_T_36; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_186 = _csr_exists_T_185 | _csr_exists_T_37; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_187 = _csr_exists_T_186 | _csr_exists_T_38; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_188 = _csr_exists_T_187 | _csr_exists_T_39; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_189 = _csr_exists_T_188 | _csr_exists_T_40; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_190 = _csr_exists_T_189 | _csr_exists_T_41; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_191 = _csr_exists_T_190 | _csr_exists_T_42; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_192 = _csr_exists_T_191 | _csr_exists_T_43; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_193 = _csr_exists_T_192 | _csr_exists_T_44; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_194 = _csr_exists_T_193 | _csr_exists_T_45; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_195 = _csr_exists_T_194 | _csr_exists_T_46; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_196 = _csr_exists_T_195 | _csr_exists_T_47; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_197 = _csr_exists_T_196 | _csr_exists_T_48; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_198 = _csr_exists_T_197 | _csr_exists_T_49; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_199 = _csr_exists_T_198 | _csr_exists_T_50; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_200 = _csr_exists_T_199 | _csr_exists_T_51; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_201 = _csr_exists_T_200 | _csr_exists_T_52; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_202 = _csr_exists_T_201 | _csr_exists_T_53; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_203 = _csr_exists_T_202 | _csr_exists_T_54; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_204 = _csr_exists_T_203 | _csr_exists_T_55; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_205 = _csr_exists_T_204 | _csr_exists_T_56; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_206 = _csr_exists_T_205 | _csr_exists_T_57; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_207 = _csr_exists_T_206 | _csr_exists_T_58; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_208 = _csr_exists_T_207 | _csr_exists_T_59; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_209 = _csr_exists_T_208 | _csr_exists_T_60; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_210 = _csr_exists_T_209 | _csr_exists_T_61; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_211 = _csr_exists_T_210 | _csr_exists_T_62; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_212 = _csr_exists_T_211 | _csr_exists_T_63; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_213 = _csr_exists_T_212 | _csr_exists_T_64; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_214 = _csr_exists_T_213 | _csr_exists_T_65; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_215 = _csr_exists_T_214 | _csr_exists_T_66; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_216 = _csr_exists_T_215 | _csr_exists_T_67; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_217 = _csr_exists_T_216 | _csr_exists_T_68; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_218 = _csr_exists_T_217 | _csr_exists_T_69; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_219 = _csr_exists_T_218 | _csr_exists_T_70; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_220 = _csr_exists_T_219 | _csr_exists_T_71; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_221 = _csr_exists_T_220 | _csr_exists_T_72; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_222 = _csr_exists_T_221 | _csr_exists_T_73; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_223 = _csr_exists_T_222 | _csr_exists_T_74; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_224 = _csr_exists_T_223 | _csr_exists_T_75; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_225 = _csr_exists_T_224 | _csr_exists_T_76; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_226 = _csr_exists_T_225 | _csr_exists_T_77; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_227 = _csr_exists_T_226 | _csr_exists_T_78; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_228 = _csr_exists_T_227 | _csr_exists_T_79; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_229 = _csr_exists_T_228 | _csr_exists_T_80; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_230 = _csr_exists_T_229 | _csr_exists_T_81; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_231 = _csr_exists_T_230 | _csr_exists_T_82; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_232 = _csr_exists_T_231 | _csr_exists_T_83; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_233 = _csr_exists_T_232 | _csr_exists_T_84; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_234 = _csr_exists_T_233 | _csr_exists_T_85; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_235 = _csr_exists_T_234 | _csr_exists_T_86; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_236 = _csr_exists_T_235 | _csr_exists_T_87; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_237 = _csr_exists_T_236 | _csr_exists_T_88; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_238 = _csr_exists_T_237 | _csr_exists_T_89; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_239 = _csr_exists_T_238 | _csr_exists_T_90; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_240 = _csr_exists_T_239 | _csr_exists_T_91; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_241 = _csr_exists_T_240 | _csr_exists_T_92; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_242 = _csr_exists_T_241 | _csr_exists_T_93; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_243 = _csr_exists_T_242 | _csr_exists_T_94; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_244 = _csr_exists_T_243 | _csr_exists_T_95; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_245 = _csr_exists_T_244 | _csr_exists_T_96; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_246 = _csr_exists_T_245 | _csr_exists_T_97; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_247 = _csr_exists_T_246 | _csr_exists_T_98; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_248 = _csr_exists_T_247 | _csr_exists_T_99; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_249 = _csr_exists_T_248 | _csr_exists_T_100; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_250 = _csr_exists_T_249 | _csr_exists_T_101; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_251 = _csr_exists_T_250 | _csr_exists_T_102; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_252 = _csr_exists_T_251 | _csr_exists_T_103; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_253 = _csr_exists_T_252 | _csr_exists_T_104; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_254 = _csr_exists_T_253 | _csr_exists_T_105; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_255 = _csr_exists_T_254 | _csr_exists_T_106; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_256 = _csr_exists_T_255 | _csr_exists_T_107; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_257 = _csr_exists_T_256 | _csr_exists_T_108; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_258 = _csr_exists_T_257 | _csr_exists_T_109; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_259 = _csr_exists_T_258 | _csr_exists_T_110; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_260 = _csr_exists_T_259 | _csr_exists_T_111; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_261 = _csr_exists_T_260 | _csr_exists_T_112; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_262 = _csr_exists_T_261 | _csr_exists_T_113; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_263 = _csr_exists_T_262 | _csr_exists_T_114; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_264 = _csr_exists_T_263 | _csr_exists_T_115; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_265 = _csr_exists_T_264 | _csr_exists_T_116; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_266 = _csr_exists_T_265 | _csr_exists_T_117; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_267 = _csr_exists_T_266 | _csr_exists_T_118; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_268 = _csr_exists_T_267 | _csr_exists_T_119; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_269 = _csr_exists_T_268 | _csr_exists_T_120; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_270 = _csr_exists_T_269 | _csr_exists_T_121; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_271 = _csr_exists_T_270 | _csr_exists_T_122; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_272 = _csr_exists_T_271 | _csr_exists_T_123; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_273 = _csr_exists_T_272 | _csr_exists_T_124; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_274 = _csr_exists_T_273 | _csr_exists_T_125; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_275 = _csr_exists_T_274 | _csr_exists_T_126; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_276 = _csr_exists_T_275 | _csr_exists_T_127; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_277 = _csr_exists_T_276 | _csr_exists_T_128; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_278 = _csr_exists_T_277 | _csr_exists_T_129; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_279 = _csr_exists_T_278 | _csr_exists_T_130; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_280 = _csr_exists_T_279 | _csr_exists_T_131; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_281 = _csr_exists_T_280 | _csr_exists_T_132; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_282 = _csr_exists_T_281 | _csr_exists_T_133; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_283 = _csr_exists_T_282 | _csr_exists_T_134; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_284 = _csr_exists_T_283 | _csr_exists_T_135; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_285 = _csr_exists_T_284 | _csr_exists_T_136; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_286 = _csr_exists_T_285 | _csr_exists_T_137; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_287 = _csr_exists_T_286 | _csr_exists_T_138; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_288 = _csr_exists_T_287 | _csr_exists_T_139; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_289 = _csr_exists_T_288 | _csr_exists_T_140; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_290 = _csr_exists_T_289 | _csr_exists_T_141; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_291 = _csr_exists_T_290 | _csr_exists_T_142; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_292 = _csr_exists_T_291 | _csr_exists_T_143; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_293 = _csr_exists_T_292 | _csr_exists_T_144; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_294 = _csr_exists_T_293 | _csr_exists_T_145; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_295 = _csr_exists_T_294 | _csr_exists_T_146; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_296 = _csr_exists_T_295 | _csr_exists_T_147; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_297 = _csr_exists_T_296 | _csr_exists_T_148; // @[CSR.scala:899:{93,111}]
wire csr_exists = _csr_exists_T_297 | _csr_exists_T_149; // @[CSR.scala:899:{93,111}]
wire _io_decode_0_read_illegal_T = ~csr_addr_legal; // @[CSR.scala:920:60, :923:28]
wire _io_decode_0_read_illegal_T_1 = ~csr_exists; // @[CSR.scala:899:111, :924:7]
wire _io_decode_0_read_illegal_T_2 = _io_decode_0_read_illegal_T | _io_decode_0_read_illegal_T_1; // @[CSR.scala:923:{28,44}, :924:7]
wire _io_decode_0_read_illegal_T_4 = addr == 12'h680; // @[CSR.scala:897:27, :925:38]
wire _io_decode_0_read_illegal_T_5 = _io_decode_0_read_illegal_T_3 | _io_decode_0_read_illegal_T_4; // @[CSR.scala:925:{14,30,38}]
wire _io_decode_0_read_illegal_T_6 = ~allow_sfence_vma; // @[CSR.scala:907:70, :925:59]
wire _io_decode_0_read_illegal_T_7 = _io_decode_0_read_illegal_T_5 & _io_decode_0_read_illegal_T_6; // @[CSR.scala:925:{30,56,59}]
wire _io_decode_0_read_illegal_T_8 = _io_decode_0_read_illegal_T_2 | _io_decode_0_read_illegal_T_7; // @[CSR.scala:923:44, :924:19, :925:56]
wire _io_decode_0_read_illegal_T_9 = ~allow_counter; // @[CSR.scala:913:91, :926:21]
wire _io_decode_0_read_illegal_T_10 = is_counter & _io_decode_0_read_illegal_T_9; // @[CSR.scala:904:81, :926:{18,21}]
wire _io_decode_0_read_illegal_T_11 = _io_decode_0_read_illegal_T_8 | _io_decode_0_read_illegal_T_10; // @[CSR.scala:924:19, :925:78, :926:18]
wire [11:0] io_decode_0_read_illegal_invInputs = ~io_decode_0_read_illegal_plaInput; // @[pla.scala:77:22, :78:21]
wire io_decode_0_read_illegal_invMatrixOutputs; // @[pla.scala:124:31]
wire io_decode_0_read_illegal_plaOutput; // @[pla.scala:81:23]
wire _io_decode_0_read_illegal_T_12 = io_decode_0_read_illegal_plaOutput; // @[pla.scala:81:23]
wire io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_0 = io_decode_0_read_illegal_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_1 = io_decode_0_read_illegal_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_2 = io_decode_0_read_illegal_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_3 = io_decode_0_read_illegal_plaInput[7]; // @[pla.scala:77:22, :90:45]
wire io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_4 = io_decode_0_read_illegal_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_5 = io_decode_0_read_illegal_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_6 = io_decode_0_read_illegal_plaInput[10]; // @[pla.scala:77:22, :90:45]
wire io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_7 = io_decode_0_read_illegal_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire [1:0] io_decode_0_read_illegal_andMatrixOutputs_lo_lo = {io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_6, io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_7}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] io_decode_0_read_illegal_andMatrixOutputs_lo_hi = {io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_4, io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_5}; // @[pla.scala:90:45, :98:53]
wire [3:0] io_decode_0_read_illegal_andMatrixOutputs_lo = {io_decode_0_read_illegal_andMatrixOutputs_lo_hi, io_decode_0_read_illegal_andMatrixOutputs_lo_lo}; // @[pla.scala:98:53]
wire [1:0] io_decode_0_read_illegal_andMatrixOutputs_hi_lo = {io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_2, io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_3}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] io_decode_0_read_illegal_andMatrixOutputs_hi_hi = {io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_0, io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_1}; // @[pla.scala:90:45, :98:53]
wire [3:0] io_decode_0_read_illegal_andMatrixOutputs_hi = {io_decode_0_read_illegal_andMatrixOutputs_hi_hi, io_decode_0_read_illegal_andMatrixOutputs_hi_lo}; // @[pla.scala:98:53]
wire [7:0] _io_decode_0_read_illegal_andMatrixOutputs_T = {io_decode_0_read_illegal_andMatrixOutputs_hi, io_decode_0_read_illegal_andMatrixOutputs_lo}; // @[pla.scala:98:53]
wire io_decode_0_read_illegal_andMatrixOutputs_0_2 = &_io_decode_0_read_illegal_andMatrixOutputs_T; // @[pla.scala:98:{53,70}]
wire io_decode_0_read_illegal_orMatrixOutputs = io_decode_0_read_illegal_andMatrixOutputs_0_2; // @[pla.scala:98:70, :114:36]
assign io_decode_0_read_illegal_invMatrixOutputs = io_decode_0_read_illegal_orMatrixOutputs; // @[pla.scala:114:36, :124:31]
assign io_decode_0_read_illegal_plaOutput = io_decode_0_read_illegal_invMatrixOutputs; // @[pla.scala:81:23, :124:31]
wire _io_decode_0_read_illegal_T_13 = ~reg_debug; // @[CSR.scala:482:26, :927:45]
wire _io_decode_0_read_illegal_T_14 = _io_decode_0_read_illegal_T_12 & _io_decode_0_read_illegal_T_13; // @[Decode.scala:55:116]
wire _io_decode_0_read_illegal_T_15 = _io_decode_0_read_illegal_T_11 | _io_decode_0_read_illegal_T_14; // @[CSR.scala:925:78, :926:36, :927:42]
wire _io_decode_0_read_illegal_T_18 = _io_decode_0_read_illegal_T_15; // @[CSR.scala:926:36, :927:56]
wire [11:0] io_decode_0_read_illegal_invInputs_1 = ~io_decode_0_read_illegal_plaInput_1; // @[pla.scala:77:22, :78:21]
wire _io_decode_0_read_illegal_T_19 = io_decode_0_fp_csr_0 & io_decode_0_fp_illegal_0; // @[CSR.scala:377:7, :929:21]
assign _io_decode_0_read_illegal_T_20 = _io_decode_0_read_illegal_T_18 | _io_decode_0_read_illegal_T_19; // @[CSR.scala:927:56, :928:68, :929:21]
assign io_decode_0_read_illegal_0 = _io_decode_0_read_illegal_T_20; // @[CSR.scala:377:7, :928:68]
wire [1:0] _io_decode_0_write_illegal_T = addr[11:10]; // @[CSR.scala:897:27, :930:33]
assign _io_decode_0_write_illegal_T_1 = &_io_decode_0_write_illegal_T; // @[CSR.scala:930:{33,41}]
assign io_decode_0_write_illegal_0 = _io_decode_0_write_illegal_T_1; // @[CSR.scala:377:7, :930:41]
wire [11:0] io_decode_0_write_flush_addr_m = {_io_decode_0_write_illegal_T, addr[9:0] | 10'h300}; // @[CSR.scala:897:27, :930:33, :932:25]
wire _io_decode_0_write_flush_T = io_decode_0_write_flush_addr_m > 12'h33F; // @[CSR.scala:932:25, :933:16]
wire _io_decode_0_write_flush_T_1 = io_decode_0_write_flush_addr_m < 12'h344; // @[CSR.scala:932:25, :933:45]
wire _io_decode_0_write_flush_T_2 = _io_decode_0_write_flush_T & _io_decode_0_write_flush_T_1; // @[CSR.scala:933:{16,35,45}]
assign _io_decode_0_write_flush_T_3 = ~_io_decode_0_write_flush_T_2; // @[CSR.scala:933:{7,35}]
assign io_decode_0_write_flush_0 = _io_decode_0_write_flush_T_3; // @[CSR.scala:377:7, :933:7]
wire _io_decode_0_system_illegal_T = ~csr_addr_legal; // @[CSR.scala:920:60, :923:28, :935:30]
wire _io_decode_0_system_illegal_T_1 = ~is_hlsv; // @[CSR.scala:903:82, :935:49]
wire _io_decode_0_system_illegal_T_2 = _io_decode_0_system_illegal_T & _io_decode_0_system_illegal_T_1; // @[CSR.scala:935:{30,46,49}]
wire _io_decode_0_system_illegal_T_3 = ~allow_wfi; // @[CSR.scala:906:71, :936:17]
wire _io_decode_0_system_illegal_T_4 = is_wfi & _io_decode_0_system_illegal_T_3; // @[CSR.scala:903:82, :936:{14,17}]
wire _io_decode_0_system_illegal_T_5 = _io_decode_0_system_illegal_T_2 | _io_decode_0_system_illegal_T_4; // @[CSR.scala:935:{46,58}, :936:14]
wire _io_decode_0_system_illegal_T_6 = ~allow_sret; // @[CSR.scala:910:72, :937:17]
wire _io_decode_0_system_illegal_T_7 = is_ret & _io_decode_0_system_illegal_T_6; // @[CSR.scala:903:82, :937:{14,17}]
wire _io_decode_0_system_illegal_T_8 = _io_decode_0_system_illegal_T_5 | _io_decode_0_system_illegal_T_7; // @[CSR.scala:935:58, :936:28, :937:14]
wire _io_decode_0_system_illegal_T_9 = addr[10]; // @[CSR.scala:897:27, :938:21]
wire _io_decode_0_system_illegal_T_10 = is_ret & _io_decode_0_system_illegal_T_9; // @[CSR.scala:903:82, :938:{14,21}]
wire _io_decode_0_system_illegal_T_11 = addr[7]; // @[CSR.scala:897:27, :938:33]
wire _io_decode_0_system_illegal_T_12 = _io_decode_0_system_illegal_T_10 & _io_decode_0_system_illegal_T_11; // @[CSR.scala:938:{14,26,33}]
wire _io_decode_0_system_illegal_T_13 = ~reg_debug; // @[CSR.scala:482:26, :927:45, :938:40]
wire _io_decode_0_system_illegal_T_14 = _io_decode_0_system_illegal_T_12 & _io_decode_0_system_illegal_T_13; // @[CSR.scala:938:{26,37,40}]
wire _io_decode_0_system_illegal_T_15 = _io_decode_0_system_illegal_T_8 | _io_decode_0_system_illegal_T_14; // @[CSR.scala:936:28, :937:29, :938:37]
wire _io_decode_0_system_illegal_T_16 = is_sfence | is_hfence_gvma; // @[CSR.scala:903:82, :939:18]
wire _io_decode_0_system_illegal_T_17 = ~allow_sfence_vma; // @[CSR.scala:907:70, :925:59, :939:40]
wire _io_decode_0_system_illegal_T_18 = _io_decode_0_system_illegal_T_16 & _io_decode_0_system_illegal_T_17; // @[CSR.scala:939:{18,37,40}]
wire _io_decode_0_system_illegal_T_19 = _io_decode_0_system_illegal_T_15 | _io_decode_0_system_illegal_T_18; // @[CSR.scala:937:29, :938:51, :939:37]
wire _io_decode_0_system_illegal_T_22 = _io_decode_0_system_illegal_T_19; // @[CSR.scala:938:51, :939:58]
assign _io_decode_0_system_illegal_T_25 = _io_decode_0_system_illegal_T_22; // @[CSR.scala:939:58, :940:44]
assign io_decode_0_system_illegal_0 = _io_decode_0_system_illegal_T_25; // @[CSR.scala:377:7, :940:44]
wire _io_decode_0_virtual_access_illegal_T = reg_mstatus_v & csr_exists; // @[CSR.scala:395:28, :899:111, :943:52]
wire _io_decode_0_virtual_access_illegal_T_2 = _io_decode_0_virtual_access_illegal_T_1 == 2'h2; // @[CSR.scala:190:36, :944:22]
wire _io_decode_0_virtual_access_illegal_T_4 = _io_decode_0_virtual_access_illegal_T_3[0]; // @[CSR.scala:945:36]
wire _io_decode_0_virtual_access_illegal_T_5 = is_counter & _io_decode_0_virtual_access_illegal_T_4; // @[CSR.scala:904:81, :945:{18,36}]
wire _io_decode_0_virtual_access_illegal_T_7 = _io_decode_0_virtual_access_illegal_T_6[0]; // @[CSR.scala:945:71]
wire _io_decode_0_virtual_access_illegal_T_8 = ~_io_decode_0_virtual_access_illegal_T_7; // @[CSR.scala:945:{55,71}]
wire _io_decode_0_virtual_access_illegal_T_9 = reg_mstatus_prv[0]; // @[CSR.scala:395:28, :945:105]
wire _io_decode_0_virtual_access_illegal_T_20 = reg_mstatus_prv[0]; // @[CSR.scala:395:28, :945:105, :946:53]
wire _io_decode_0_virtual_access_illegal_T_25 = reg_mstatus_prv[0]; // @[CSR.scala:395:28, :945:105, :947:46]
wire _io_decode_0_virtual_system_illegal_T_2 = reg_mstatus_prv[0]; // @[CSR.scala:395:28, :945:105, :953:34]
wire _io_decode_0_virtual_system_illegal_T_12 = reg_mstatus_prv[0]; // @[CSR.scala:395:28, :945:105, :954:64]
wire _io_decode_0_virtual_system_illegal_T_17 = reg_mstatus_prv[0]; // @[CSR.scala:395:28, :945:105, :955:37]
wire _cause_T = reg_mstatus_prv[0]; // @[CSR.scala:395:28, :945:105, :959:61]
wire _reg_hstatus_spvp_T = reg_mstatus_prv[0]; // @[CSR.scala:395:28, :945:105, :1067:61]
wire _io_decode_0_virtual_access_illegal_T_10 = ~_io_decode_0_virtual_access_illegal_T_9; // @[CSR.scala:945:{89,105}]
wire _io_decode_0_virtual_access_illegal_T_12 = _io_decode_0_virtual_access_illegal_T_11[0]; // @[CSR.scala:945:128]
wire _io_decode_0_virtual_access_illegal_T_13 = ~_io_decode_0_virtual_access_illegal_T_12; // @[CSR.scala:945:{112,128}]
wire _io_decode_0_virtual_access_illegal_T_14 = _io_decode_0_virtual_access_illegal_T_10 & _io_decode_0_virtual_access_illegal_T_13; // @[CSR.scala:945:{89,109,112}]
wire _io_decode_0_virtual_access_illegal_T_15 = _io_decode_0_virtual_access_illegal_T_8 | _io_decode_0_virtual_access_illegal_T_14; // @[CSR.scala:945:{55,86,109}]
wire _io_decode_0_virtual_access_illegal_T_16 = _io_decode_0_virtual_access_illegal_T_5 & _io_decode_0_virtual_access_illegal_T_15; // @[CSR.scala:945:{18,51,86}]
wire _io_decode_0_virtual_access_illegal_T_17 = _io_decode_0_virtual_access_illegal_T_2 | _io_decode_0_virtual_access_illegal_T_16; // @[CSR.scala:944:{22,34}, :945:51]
wire _io_decode_0_virtual_access_illegal_T_19 = _io_decode_0_virtual_access_illegal_T_18 == 2'h1; // @[CSR.scala:190:36, :946:22]
wire _io_decode_0_virtual_access_illegal_T_21 = ~_io_decode_0_virtual_access_illegal_T_20; // @[CSR.scala:946:{37,53}]
wire _io_decode_0_virtual_access_illegal_T_22 = _io_decode_0_virtual_access_illegal_T_19 & _io_decode_0_virtual_access_illegal_T_21; // @[CSR.scala:946:{22,34,37}]
wire _io_decode_0_virtual_access_illegal_T_23 = _io_decode_0_virtual_access_illegal_T_17 | _io_decode_0_virtual_access_illegal_T_22; // @[CSR.scala:944:34, :945:144, :946:34]
wire _io_decode_0_virtual_access_illegal_T_28 = _io_decode_0_virtual_access_illegal_T_23; // @[CSR.scala:945:144, :946:57]
wire _io_decode_0_virtual_access_illegal_T_26 = _io_decode_0_virtual_access_illegal_T_24 & _io_decode_0_virtual_access_illegal_T_25; // @[CSR.scala:947:{12,28,46}]
assign _io_decode_0_virtual_access_illegal_T_29 = _io_decode_0_virtual_access_illegal_T & _io_decode_0_virtual_access_illegal_T_28; // @[CSR.scala:943:{52,66}, :946:57]
assign io_decode_0_virtual_access_illegal_0 = _io_decode_0_virtual_access_illegal_T_29; // @[CSR.scala:377:7, :943:66]
wire _io_decode_0_virtual_system_illegal_T = is_hfence_vvma | is_hfence_gvma; // @[CSR.scala:903:82, :950:22]
wire _io_decode_0_virtual_system_illegal_T_1 = _io_decode_0_virtual_system_illegal_T | is_hlsv; // @[CSR.scala:903:82, :950:22, :951:22]
wire _io_decode_0_virtual_system_illegal_T_3 = ~_io_decode_0_virtual_system_illegal_T_2; // @[CSR.scala:953:{18,34}]
wire _io_decode_0_virtual_system_illegal_T_6 = _io_decode_0_virtual_system_illegal_T_3; // @[CSR.scala:953:{18,38}]
wire _io_decode_0_virtual_system_illegal_T_4 = ~reg_mstatus_tw; // @[CSR.scala:395:28, :906:74, :953:41]
wire _io_decode_0_virtual_system_illegal_T_7 = is_wfi & _io_decode_0_virtual_system_illegal_T_6; // @[CSR.scala:903:82, :953:{14,38}]
wire _io_decode_0_virtual_system_illegal_T_8 = _io_decode_0_virtual_system_illegal_T_1 | _io_decode_0_virtual_system_illegal_T_7; // @[CSR.scala:951:22, :952:15, :953:14]
wire _io_decode_0_virtual_system_illegal_T_10 = _io_decode_0_virtual_system_illegal_T_9 == 2'h1; // @[CSR.scala:190:36, :954:32]
wire _io_decode_0_virtual_system_illegal_T_11 = is_ret & _io_decode_0_virtual_system_illegal_T_10; // @[CSR.scala:903:82, :954:{14,32}]
wire _io_decode_0_virtual_system_illegal_T_13 = ~_io_decode_0_virtual_system_illegal_T_12; // @[CSR.scala:954:{48,64}]
wire _io_decode_0_virtual_system_illegal_T_14 = _io_decode_0_virtual_system_illegal_T_13; // @[CSR.scala:954:{48,68}]
wire _io_decode_0_virtual_system_illegal_T_15 = _io_decode_0_virtual_system_illegal_T_11 & _io_decode_0_virtual_system_illegal_T_14; // @[CSR.scala:954:{14,44,68}]
wire _io_decode_0_virtual_system_illegal_T_16 = _io_decode_0_virtual_system_illegal_T_8 | _io_decode_0_virtual_system_illegal_T_15; // @[CSR.scala:952:15, :953:77, :954:44]
wire _io_decode_0_virtual_system_illegal_T_18 = ~_io_decode_0_virtual_system_illegal_T_17; // @[CSR.scala:955:{21,37}]
wire _io_decode_0_virtual_system_illegal_T_19 = _io_decode_0_virtual_system_illegal_T_18; // @[CSR.scala:955:{21,41}]
wire _io_decode_0_virtual_system_illegal_T_20 = is_sfence & _io_decode_0_virtual_system_illegal_T_19; // @[CSR.scala:903:82, :955:{17,41}]
wire _io_decode_0_virtual_system_illegal_T_21 = _io_decode_0_virtual_system_illegal_T_16 | _io_decode_0_virtual_system_illegal_T_20; // @[CSR.scala:953:77, :954:89, :955:17]
assign _io_decode_0_virtual_system_illegal_T_22 = reg_mstatus_v & _io_decode_0_virtual_system_illegal_T_21; // @[CSR.scala:395:28, :949:52, :954:89]
assign io_decode_0_virtual_system_illegal_0 = _io_decode_0_virtual_system_illegal_T_22; // @[CSR.scala:377:7, :949:52]
wire _cause_T_1 = _cause_T & reg_mstatus_v; // @[CSR.scala:395:28, :959:{61,65}]
wire [1:0] _cause_T_2 = _cause_T_1 ? 2'h2 : reg_mstatus_prv; // @[CSR.scala:395:28, :959:{45,65}]
wire [4:0] _cause_T_3 = {3'h0, _cause_T_2} + 5'h8; // @[CSR.scala:959:{40,45}]
wire [3:0] _cause_T_4 = _cause_T_3[3:0]; // @[CSR.scala:959:40]
wire [63:0] _cause_T_5 = insn_break ? 64'h3 : io_cause_0; // @[CSR.scala:377:7, :893:83, :960:14]
assign cause = insn_call ? {60'h0, _cause_T_4} : _cause_T_5; // @[CSR.scala:893:83, :959:{8,40}, :960:14]
assign io_trace_0_cause_0 = cause; // @[CSR.scala:377:7, :959:8]
wire [7:0] cause_lsbs = cause[7:0]; // @[CSR.scala:959:8, :961:25]
wire [5:0] cause_deleg_lsbs = cause[5:0]; // @[CSR.scala:959:8, :962:31]
wire [5:0] _notDebugTVec_interruptOffset_T = cause[5:0]; // @[CSR.scala:959:8, :962:31, :979:32]
wire _causeIsDebugInt_T = cause[63]; // @[CSR.scala:959:8, :963:30]
wire _causeIsDebugTrigger_T = cause[63]; // @[CSR.scala:959:8, :963:30, :964:35]
wire _causeIsDebugBreak_T = cause[63]; // @[CSR.scala:959:8, :963:30, :965:33]
wire _delegate_T_2 = cause[63]; // @[CSR.scala:959:8, :963:30, :970:78]
wire _delegateVS_T_1 = cause[63]; // @[CSR.scala:959:8, :963:30, :971:58]
wire _notDebugTVec_doVector_T_1 = cause[63]; // @[CSR.scala:959:8, :963:30, :981:36]
wire _causeIsRnmiInt_T = cause[63]; // @[CSR.scala:959:8, :963:30, :985:29]
wire _causeIsRnmiBEU_T = cause[63]; // @[CSR.scala:959:8, :963:30, :986:29]
wire _reg_vscause_T = cause[63]; // @[CSR.scala:959:8, :963:30, :1060:31]
assign _io_trace_0_interrupt_T = cause[63]; // @[CSR.scala:959:8, :963:30, :1626:25]
wire _GEN_15 = cause_lsbs == 8'hE; // @[CSR.scala:961:25, :963:53]
wire _causeIsDebugInt_T_1; // @[CSR.scala:963:53]
assign _causeIsDebugInt_T_1 = _GEN_15; // @[CSR.scala:963:53]
wire _causeIsDebugTrigger_T_2; // @[CSR.scala:964:58]
assign _causeIsDebugTrigger_T_2 = _GEN_15; // @[CSR.scala:963:53, :964:58]
wire causeIsDebugInt = _causeIsDebugInt_T & _causeIsDebugInt_T_1; // @[CSR.scala:963:{30,39,53}]
wire _causeIsDebugTrigger_T_1 = ~_causeIsDebugTrigger_T; // @[CSR.scala:964:{29,35}]
wire causeIsDebugTrigger = _causeIsDebugTrigger_T_1 & _causeIsDebugTrigger_T_2; // @[CSR.scala:964:{29,44,58}]
wire _causeIsDebugBreak_T_1 = ~_causeIsDebugBreak_T; // @[CSR.scala:965:{27,33}]
wire _causeIsDebugBreak_T_2 = _causeIsDebugBreak_T_1 & insn_break; // @[CSR.scala:893:83, :965:{27,42}]
wire [1:0] causeIsDebugBreak_lo = {reg_dcsr_ebreaks, reg_dcsr_ebreaku}; // @[CSR.scala:403:25, :965:62]
wire [1:0] causeIsDebugBreak_hi = {reg_dcsr_ebreakm, 1'h0}; // @[CSR.scala:403:25, :965:62]
wire [3:0] _causeIsDebugBreak_T_3 = {causeIsDebugBreak_hi, causeIsDebugBreak_lo}; // @[CSR.scala:965:62]
wire [3:0] _causeIsDebugBreak_T_4 = _causeIsDebugBreak_T_3 >> reg_mstatus_prv; // @[CSR.scala:395:28, :965:{62,134}]
wire _causeIsDebugBreak_T_5 = _causeIsDebugBreak_T_4[0]; // @[CSR.scala:965:134]
wire causeIsDebugBreak = _causeIsDebugBreak_T_2 & _causeIsDebugBreak_T_5; // @[CSR.scala:965:{42,56,134}]
wire _trapToDebug_T = reg_singleStepped | causeIsDebugInt; // @[CSR.scala:486:30, :963:39, :966:56]
wire _trapToDebug_T_1 = _trapToDebug_T | causeIsDebugTrigger; // @[CSR.scala:964:44, :966:{56,75}]
wire _trapToDebug_T_2 = _trapToDebug_T_1 | causeIsDebugBreak; // @[CSR.scala:965:56, :966:{75,98}]
wire _trapToDebug_T_3 = _trapToDebug_T_2 | reg_debug; // @[CSR.scala:482:26, :966:{98,119}]
wire trapToDebug = _trapToDebug_T_3; // @[CSR.scala:966:{34,119}]
wire [11:0] _debugTVec_T = {8'h80, ~insn_break, 3'h0}; // @[CSR.scala:893:83, :969:37]
wire [11:0] debugTVec = reg_debug ? _debugTVec_T : 12'h800; // @[CSR.scala:482:26, :969:{22,37}]
wire _delegate_T = ~(reg_mstatus_prv[1]); // @[CSR.scala:395:28, :620:51, :970:55]
wire _delegate_T_1 = _delegate_T; // @[CSR.scala:970:{36,55}]
wire [63:0] _GEN_16 = {58'h0, cause_deleg_lsbs}; // @[CSR.scala:962:31, :970:100]
wire [63:0] _delegate_T_3 = read_mideleg >> _GEN_16; // @[CSR.scala:498:14, :970:100]
wire _delegate_T_4 = _delegate_T_3[0]; // @[CSR.scala:970:100]
wire [63:0] _delegate_T_5 = read_medeleg >> _GEN_16; // @[CSR.scala:502:14, :970:{100,132}]
wire _delegate_T_6 = _delegate_T_5[0]; // @[CSR.scala:970:132]
wire _delegate_T_7 = _delegate_T_2 ? _delegate_T_4 : _delegate_T_6; // @[CSR.scala:970:{72,78,100,132}]
wire delegate = _delegate_T_1 & _delegate_T_7; // @[CSR.scala:970:{36,66,72}]
wire _delegateVS_T = reg_mstatus_v & delegate; // @[CSR.scala:395:28, :970:66, :971:34]
wire [63:0] _GEN_17 = 64'h0 >> _GEN_16; // @[CSR.scala:970:100, :971:80]
wire [63:0] _delegateVS_T_2; // @[CSR.scala:971:80]
assign _delegateVS_T_2 = _GEN_17; // @[CSR.scala:971:80]
wire [63:0] _delegateVS_T_4; // @[CSR.scala:971:112]
assign _delegateVS_T_4 = _GEN_17; // @[CSR.scala:971:{80,112}]
wire _delegateVS_T_3 = _delegateVS_T_2[0]; // @[CSR.scala:971:80]
wire _delegateVS_T_5 = _delegateVS_T_4[0]; // @[CSR.scala:971:112]
wire _delegateVS_T_6 = _delegateVS_T_1 ? _delegateVS_T_3 : _delegateVS_T_5; // @[CSR.scala:971:{52,58,80,112}]
wire delegateVS = _delegateVS_T & _delegateVS_T_6; // @[CSR.scala:971:{34,46,52}]
wire [63:0] _notDebugTVec_base_T = delegateVS ? read_vstvec : read_stvec; // @[package.scala:132:15]
wire [63:0] notDebugTVec_base = delegate ? _notDebugTVec_base_T : read_mtvec; // @[package.scala:138:15]
wire [7:0] notDebugTVec_interruptOffset = {_notDebugTVec_interruptOffset_T, 2'h0}; // @[CSR.scala:979:{32,59}]
wire [55:0] _notDebugTVec_interruptVec_T = notDebugTVec_base[63:8]; // @[CSR.scala:978:19, :980:33]
wire [63:0] notDebugTVec_interruptVec = {_notDebugTVec_interruptVec_T, notDebugTVec_interruptOffset}; // @[CSR.scala:979:59, :980:{27,33}]
wire _notDebugTVec_doVector_T = notDebugTVec_base[0]; // @[CSR.scala:978:19, :981:24]
wire _notDebugTVec_doVector_T_2 = _notDebugTVec_doVector_T & _notDebugTVec_doVector_T_1; // @[CSR.scala:981:{24,28,36}]
wire [1:0] _notDebugTVec_doVector_T_3 = cause_lsbs[7:6]; // @[CSR.scala:961:25, :981:70]
wire _notDebugTVec_doVector_T_4 = _notDebugTVec_doVector_T_3 == 2'h0; // @[CSR.scala:981:{70,94}]
wire notDebugTVec_doVector = _notDebugTVec_doVector_T_2 & _notDebugTVec_doVector_T_4; // @[CSR.scala:981:{28,55,94}]
wire [61:0] _notDebugTVec_T = notDebugTVec_base[63:2]; // @[CSR.scala:978:19, :982:38]
wire [63:0] _notDebugTVec_T_1 = {_notDebugTVec_T, 2'h0}; // @[CSR.scala:982:{38,56}]
wire [63:0] notDebugTVec = notDebugTVec_doVector ? notDebugTVec_interruptVec : _notDebugTVec_T_1; // @[CSR.scala:980:27, :981:55, :982:{8,56}]
wire [63:0] _tvec_T = notDebugTVec; // @[CSR.scala:982:8, :995:45]
wire _causeIsRnmiInt_T_1 = cause[62]; // @[CSR.scala:959:8, :985:46]
wire _causeIsRnmiBEU_T_1 = cause[62]; // @[CSR.scala:959:8, :985:46, :986:46]
wire _causeIsRnmiInt_T_2 = _causeIsRnmiInt_T & _causeIsRnmiInt_T_1; // @[CSR.scala:985:{29,38,46}]
wire _causeIsRnmiInt_T_3 = cause_lsbs == 8'hD; // @[CSR.scala:961:25, :985:70]
wire _GEN_18 = cause_lsbs == 8'hC; // @[CSR.scala:961:25, :985:107]
wire _causeIsRnmiInt_T_4; // @[CSR.scala:985:107]
assign _causeIsRnmiInt_T_4 = _GEN_18; // @[CSR.scala:985:107]
wire _causeIsRnmiBEU_T_3; // @[CSR.scala:986:69]
assign _causeIsRnmiBEU_T_3 = _GEN_18; // @[CSR.scala:985:107, :986:69]
wire _causeIsRnmiInt_T_5 = _causeIsRnmiInt_T_3 | _causeIsRnmiInt_T_4; // @[CSR.scala:985:{70,93,107}]
wire causeIsRnmiInt = _causeIsRnmiInt_T_2 & _causeIsRnmiInt_T_5; // @[CSR.scala:985:{38,55,93}]
wire _causeIsRnmiBEU_T_2 = _causeIsRnmiBEU_T & _causeIsRnmiBEU_T_1; // @[CSR.scala:986:{29,38,46}]
wire causeIsRnmiBEU = _causeIsRnmiBEU_T_2 & _causeIsRnmiBEU_T_3; // @[CSR.scala:986:{38,55,69}]
wire [63:0] tvec = trapToDebug ? {52'h0, debugTVec} : _tvec_T; // @[CSR.scala:966:34, :969:22, :995:{17,45}]
wire _GEN_19 = insn_call | insn_break; // @[CSR.scala:893:83, :1000:24]
wire _io_eret_T; // @[CSR.scala:1000:24]
assign _io_eret_T = _GEN_19; // @[CSR.scala:1000:24]
wire _exception_T; // @[CSR.scala:1020:29]
assign _exception_T = _GEN_19; // @[CSR.scala:1000:24, :1020:29]
assign _io_eret_T_1 = _io_eret_T | insn_ret; // @[CSR.scala:893:83, :1000:{24,38}]
assign io_eret_0 = _io_eret_T_1; // @[CSR.scala:377:7, :1000:38]
wire _io_singleStep_T = ~reg_debug; // @[CSR.scala:482:26, :927:45, :1001:37]
assign _io_singleStep_T_1 = reg_dcsr_step & _io_singleStep_T; // @[CSR.scala:403:25, :1001:{34,37}]
assign io_singleStep_0 = _io_singleStep_T_1; // @[CSR.scala:377:7, :1001:34]
wire _io_status_sd_T = &io_status_fs_0; // @[CSR.scala:377:7, :1003:32]
wire _io_status_sd_T_2 = _io_status_sd_T; // @[CSR.scala:1003:{32,37}]
assign _io_status_sd_T_4 = _io_status_sd_T_2; // @[CSR.scala:1003:{37,58}]
assign io_status_sd_0 = _io_status_sd_T_4; // @[CSR.scala:377:7, :1003:58]
assign io_status_isa_0 = reg_misa[31:0]; // @[CSR.scala:377:7, :648:25, :1005:17]
wire _io_status_dprv_T = ~reg_debug; // @[CSR.scala:482:26, :927:45, :1008:45]
wire _io_status_dprv_T_1 = reg_mstatus_mprv & _io_status_dprv_T; // @[CSR.scala:395:28, :1008:{42,45}]
assign _io_status_dprv_T_2 = _io_status_dprv_T_1 ? reg_mstatus_mpp : reg_mstatus_prv; // @[CSR.scala:395:28, :1008:{24,42}]
assign io_status_dprv_0 = _io_status_dprv_T_2; // @[CSR.scala:377:7, :1008:24]
wire _io_status_dv_T = ~reg_debug; // @[CSR.scala:482:26, :927:45, :1009:60]
wire _io_status_dv_T_1 = reg_mstatus_mprv & _io_status_dv_T; // @[CSR.scala:395:28, :1009:{57,60}]
wire _io_status_dv_T_2 = _io_status_dv_T_1 & reg_mstatus_mpv; // @[CSR.scala:395:28, :1009:{39,57}]
assign _io_status_dv_T_3 = reg_mstatus_v | _io_status_dv_T_2; // @[CSR.scala:395:28, :1009:{33,39}]
assign io_status_dv_0 = _io_status_dv_T_3; // @[CSR.scala:377:7, :1009:33]
wire _io_gstatus_sd_T = &io_gstatus_fs_0; // @[CSR.scala:377:7, :1016:34]
wire _io_gstatus_sd_T_2 = _io_gstatus_sd_T; // @[CSR.scala:1016:{34,39}]
wire _io_gstatus_sd_T_3 = &io_gstatus_vs_0; // @[CSR.scala:377:7, :1016:78]
assign _io_gstatus_sd_T_4 = _io_gstatus_sd_T_2 | _io_gstatus_sd_T_3; // @[CSR.scala:1016:{39,61,78}]
assign io_gstatus_sd_0 = _io_gstatus_sd_T_4; // @[CSR.scala:377:7, :1016:61]
wire exception = _exception_T | io_exception_0; // @[CSR.scala:377:7, :1020:{29,43}]
wire _en_T_8 = exception; // @[CSR.scala:1020:43, :1096:24]
wire _en_T_20 = exception; // @[CSR.scala:1020:43, :1096:24]
wire _en_T_32 = exception; // @[CSR.scala:1020:43, :1096:24]
wire _en_T_44 = exception; // @[CSR.scala:1020:43, :1096:24]
wire _en_T_56 = exception; // @[CSR.scala:1020:43, :1096:24]
wire _en_T_68 = exception; // @[CSR.scala:1020:43, :1096:24]
assign _io_trace_0_exception_T_1 = exception; // @[CSR.scala:1020:43, :1620:37] |
Generate the Verilog code corresponding to the following Chisel files.
File Mem.scala:
package saturn.mem
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config._
import freechips.rocketchip.rocket._
import freechips.rocketchip.util._
import freechips.rocketchip.tile._
import saturn.common._
class LSIQEntry(implicit p: Parameters) extends CoreBundle()(p) with HasVectorParams {
val op = new VectorMemMacroOp
def bound_all = op.mop =/= mopUnit
val bound_offset = UInt(pgIdxBits.W)
val ld_dep_mask = Vec(vParams.vliqEntries, Bool())
val st_dep_mask = Vec(vParams.vsiqEntries, Bool())
def containsBlock(addr: UInt) = {
val cl = addr(pgIdxBits-1,lgCacheBlockBytes)
val base_cl = op.base_offset >> lgCacheBlockBytes
val bound_cl = bound_offset >> lgCacheBlockBytes
(((addr >> pgIdxBits) === op.page) && (base_cl <= cl && bound_cl >= cl)) || bound_all
}
def overlaps(other: LSIQEntry) = {
(op.page === other.op.page) && (bound_all || other.bound_all || (
(op.base_offset <= other.bound_offset && bound_offset >= other.op.base_offset)
))
}
}
class IFQEntry(implicit p: Parameters) extends CoreBundle()(p) with HasVectorParams {
val head = UInt(log2Ceil(dLenB).W)
val tail = UInt(log2Ceil(dLenB).W)
val masked = Bool()
val last = Bool()
val lsiq_id = UInt(lsiqIdBits.W)
val page_offset = UInt(pgIdxBits.W)
}
class MemRequest(bytes: Int, tagBits: Int)(implicit p: Parameters) extends CoreBundle()(p) {
val addr = UInt(coreMaxAddrBits.W)
val data = UInt((bytes*8).W)
val mask = UInt(bytes.W)
val tag = UInt(tagBits.W)
val store = Bool()
}
class MemResponse(bytes: Int, tagBits: Int)(implicit p: Parameters) extends CoreBundle()(p) {
val data = UInt((bytes*8).W)
val tag = UInt(tagBits.W)
}
class ScalarMemOrderCheckIO(implicit p: Parameters) extends CoreBundle()(p) with HasVectorParams {
val addr = Input(UInt(coreMaxAddrBits.W))
val size = Input(UInt(2.W))
val store = Input(Bool())
val conflict = Output(Bool())
}
class VectorMemIO(implicit p: Parameters) extends CoreBundle()(p) with HasVectorParams {
val load_req = Decoupled(new MemRequest(dLenB, dmemTagBits))
val load_resp = Input(Valid(new MemResponse(dLenB, dmemTagBits)))
val store_req = Decoupled(new MemRequest(dLenB, dmemTagBits))
val store_ack = Input(Valid(new MemResponse(dLenB, dmemTagBits)))
}
class VectorSGMemIO(implicit p: Parameters) extends CoreBundle()(p) with HasVectorParams {
val req = Vec(vParams.vsgPorts, Decoupled(new MemRequest(1, sgmemTagBits)))
val resp = Vec(vParams.vsgPorts, Input(Valid(new MemResponse(1, sgmemTagBits))))
}
class VectorMemDatapathIO(implicit p: Parameters) extends CoreBundle()(p) with HasVectorParams {
val lresp = Decoupled(new Bundle {
val data = UInt(dLen.W)
val debug_id = UInt(debugIdSz.W)
})
val sdata = Flipped(Decoupled(new StoreDataMicroOp))
val mask_pop = Decoupled(new CompactorReq(dLenB))
val mask_data = Input(Vec(dLenB, Bool()))
val index_pop = Decoupled(new CompactorReq(dLenB))
val index_data = Input(Vec(dLenB, UInt(8.W)))
}
class VectorMemUnit(sgSize: Option[BigInt] = None)(implicit p: Parameters) extends CoreModule()(p) with HasVectorParams {
val io = IO(new Bundle {
val enq = Flipped(Decoupled(new VectorMemMacroOp))
val dmem = new VectorMemIO
val sgmem = sgSize.map(_ => new VectorSGMemIO)
val scalar_check = new ScalarMemOrderCheckIO
val vu = new VectorMemDatapathIO
val busy = Output(Bool())
})
def ptrIncr(u: UInt, sz: Int): Unit = {
val n = u +& 1.U
u := Mux(n === sz.U, 0.U, n)
}
val sgas = sgSize.map { size => Module(new ScatterGatherAddrGen(size)) }
val las = Module(new AddrGen)
val lifq = Module(new LoadOrderBuffer(vParams.vlifqEntries, vParams.vlrobEntries))
val lcu = Module(new Compactor(dLenB, dLenB, UInt(8.W), true))
val lss = Module(new LoadSegmenter)
val scu = Module(new Compactor(dLenB, dLenB, new MaskedByte, false))
val sss = Module(new StoreSegmenter)
val sas = Module(new AddrGen)
val sifq = Module(new DCEQueue(new IFQEntry, vParams.vsifqEntries))
val liq = Reg(Vec(vParams.vliqEntries, new LSIQEntry))
val liq_valids = RegInit(VecInit.fill(vParams.vliqEntries)(false.B))
val liq_las = RegInit(VecInit.fill(vParams.vliqEntries)(false.B))
val liq_enq_ptr = RegInit(0.U(log2Ceil(vParams.vliqEntries).W))
val liq_las_ptr = RegInit(0.U(log2Ceil(vParams.vliqEntries).W))
val liq_lss_ptr = RegInit(0.U(log2Ceil(vParams.vliqEntries).W))
val liq_enq_fire = Wire(Bool())
val liq_las_fire = Wire(Bool())
val liq_lss_fire = Wire(Bool())
val liq_enq_ready = !liq_valids(liq_enq_ptr)
val liq_las_valid = !liq_las(liq_las_ptr) && liq_valids(liq_las_ptr)
val liq_lss_valid = liq_valids(liq_lss_ptr)
val siq = Reg(Vec(vParams.vsiqEntries, new LSIQEntry))
val siq_valids = RegInit(VecInit.fill(vParams.vsiqEntries)(false.B))
val siq_sss = RegInit(VecInit.fill(vParams.vsiqEntries)(false.B))
val siq_sas = RegInit(VecInit.fill(vParams.vsiqEntries)(false.B))
val siq_enq_ptr = RegInit(0.U(log2Ceil(vParams.vsiqEntries).W))
val siq_sss_ptr = RegInit(0.U(log2Ceil(vParams.vsiqEntries).W))
val siq_sas_ptr = RegInit(0.U(log2Ceil(vParams.vsiqEntries).W))
val siq_deq_ptr = RegInit(0.U(log2Ceil(vParams.vsiqEntries).W))
val siq_enq_fire = Wire(Bool())
val siq_sss_fire = Wire(Bool())
val siq_sas_fire = Wire(Bool())
val siq_deq_fire = Wire(Bool())
val siq_enq_ready = !siq_valids(siq_enq_ptr)
val siq_sss_valid = !siq_sss(siq_sss_ptr) && siq_valids(siq_sss_ptr)
val siq_sas_valid = !siq_sas(siq_sas_ptr) && siq_valids(siq_sas_ptr)
val enq_bound_max = (((io.enq.bits.nf +& 1.U) * io.enq.bits.vl) << io.enq.bits.elem_size) + io.enq.bits.base_offset - 1.U
val enq_bound = Mux((enq_bound_max >> pgIdxBits) =/= 0.U, ~(0.U(pgIdxBits.W)), enq_bound_max)
when (liq_enq_fire) {
liq(liq_enq_ptr).op := io.enq.bits
liq(liq_enq_ptr).bound_offset := enq_bound
liq(liq_enq_ptr).st_dep_mask := siq_valids
liq_las(liq_enq_ptr) := false.B
ptrIncr(liq_enq_ptr, vParams.vliqEntries)
liq_valids(liq_enq_ptr) := true.B
}
when (liq_las_fire) {
ptrIncr(liq_las_ptr, vParams.vliqEntries)
liq_las(liq_las_ptr) := true.B
}
when (liq_lss_fire) {
ptrIncr(liq_lss_ptr, vParams.vliqEntries)
liq_valids(liq_lss_ptr) := false.B
assert(liq_las(liq_lss_ptr) || (liq_lss_ptr === liq_las_ptr && liq_las_fire))
}
when (siq_enq_fire) {
siq(siq_enq_ptr).op := io.enq.bits
siq(siq_enq_ptr).bound_offset := enq_bound
siq(siq_enq_ptr).ld_dep_mask := liq_valids
siq_sss(siq_enq_ptr) := false.B
siq_sas(siq_enq_ptr) := false.B
ptrIncr(siq_enq_ptr, vParams.vsiqEntries)
siq_valids(siq_enq_ptr) := true.B
}
when (siq_sss_fire) {
ptrIncr(siq_sss_ptr, vParams.vsiqEntries)
siq_sss(siq_sss_ptr) := true.B
}
when (siq_sas_fire) {
ptrIncr(siq_sas_ptr, vParams.vsiqEntries)
siq_sas(siq_sas_ptr) := true.B
assert(siq_sss(siq_sas_ptr) || (siq_sss_fire && siq_sss_ptr === siq_sas_ptr))
}
when (siq_deq_fire) {
ptrIncr(siq_deq_ptr, vParams.vsiqEntries)
siq_valids(siq_deq_ptr) := false.B
assert(siq_sas(siq_deq_ptr) || (siq_sas_fire && siq_sas_ptr === siq_deq_ptr))
}
io.enq.ready := Mux(io.enq.bits.store, siq_enq_ready, liq_enq_ready)
liq_enq_fire := io.enq.valid && liq_enq_ready && !io.enq.bits.store
siq_enq_fire := io.enq.valid && siq_enq_ready && io.enq.bits.store
when (liq_lss_fire) { siq.foreach(_.ld_dep_mask(liq_lss_ptr) := false.B) }
when (siq_deq_fire) { liq.foreach(_.st_dep_mask(siq_deq_ptr) := false.B) }
val scalar_store_conflict = (0 until vParams.vsiqEntries).map { i =>
siq_valids(i) && (siq(i).containsBlock(io.scalar_check.addr) || !vParams.enableScalarVectorAddrDisambiguation.B)
}.orR
val scalar_load_conflict = (0 until vParams.vliqEntries).map { i =>
liq_valids(i) && (liq(i).containsBlock(io.scalar_check.addr) || !vParams.enableScalarVectorAddrDisambiguation.B)
}.orR
io.scalar_check.conflict := scalar_store_conflict || (scalar_load_conflict && io.scalar_check.store)
// Send indices/masks to las/sas
val las_older_than_sas = (liq_las_valid && !liq(liq_las_ptr).st_dep_mask(siq_sas_ptr)) || !siq_sas_valid
val maskindex_load = liq_las_valid && las_older_than_sas && !liq(liq_las_ptr).op.fast_sg
val maskindex_store = siq_sas_valid && !las_older_than_sas && !siq(siq_sas_ptr).op.fast_sg
val maskindex_gather = liq_las_valid && las_older_than_sas && liq(liq_las_ptr).op.fast_sg
val maskindex_scatter = siq_sas_valid && !las_older_than_sas && siq(siq_sas_ptr).op.fast_sg
las.io.maskindex.index := io.vu.index_data.asUInt
sas.io.maskindex.index := io.vu.index_data.asUInt
las.io.maskindex.mask := io.vu.mask_data(0)
sas.io.maskindex.mask := io.vu.mask_data(0)
io.vu.mask_pop.valid := false.B
io.vu.mask_pop.bits.head := 0.U
io.vu.mask_pop.bits.tail := 1.U
io.vu.index_pop.valid := false.B
io.vu.index_pop.bits.head := 0.U
io.vu.index_pop.bits.tail := 1.U
when (maskindex_load) {
io.vu.mask_pop.valid := las.io.maskindex.needs_mask && las.io.maskindex.ready
io.vu.index_pop.valid := las.io.maskindex.needs_index && las.io.maskindex.ready
io.vu.index_pop.bits.tail := 1.U << las.io.maskindex.eew
}
when (maskindex_store) {
io.vu.mask_pop.valid := sas.io.maskindex.needs_mask && sas.io.maskindex.ready
io.vu.index_pop.valid := sas.io.maskindex.needs_index && sas.io.maskindex.ready
io.vu.index_pop.bits.tail := 1.U << sas.io.maskindex.eew
}
// scatter/gather paths
sgas.foreach { sgas =>
sgas.io.index_pop.ready := false.B
sgas.io.mask_pop.ready := false.B
when (maskindex_gather || maskindex_scatter) {
io.vu.mask_pop <> sgas.io.mask_pop
io.vu.index_pop <> sgas.io.index_pop
}
sgas.io.index_data := io.vu.index_data
sgas.io.mask_data := io.vu.mask_data
sgas.io.valid := maskindex_gather || maskindex_scatter
sgas.io.lsiq_id := Mux(maskindex_gather, liq_las_ptr, siq_sas_ptr)
sgas.io.op := Mux(maskindex_gather, liq(liq_las_ptr).op, siq(siq_sas_ptr).op)
sgas.io.req <> io.sgmem.get.req
sgas.io.resp <> io.sgmem.get.resp
}
las.io.maskindex.valid := maskindex_load && (io.vu.mask_pop.ready || !las.io.maskindex.needs_mask) && (io.vu.index_pop.ready || !las.io.maskindex.needs_index)
sas.io.maskindex.valid := !maskindex_load && (io.vu.mask_pop.ready || !sas.io.maskindex.needs_mask) && (io.vu.index_pop.ready || !sas.io.maskindex.needs_index)
// Load Addr Sequencing
val las_order_block = (0 until vParams.vsiqEntries).map { i =>
val addr_conflict = siq(i).overlaps(liq(liq_las_ptr))
siq_valids(i) && addr_conflict && liq(liq_las_ptr).st_dep_mask(i)
}.orR
val dae_block = !vParams.enableDAE.B && (!io.vu.lresp.ready ||
io.vu.lresp.bits.debug_id =/= liq(liq_las_ptr).op.debug_id)
las.io.valid := liq_las_valid && !las_order_block && !liq(liq_las_ptr).op.fast_sg && !dae_block
las.io.lsiq_id := liq_las_ptr
las.io.op := liq(liq_las_ptr).op
liq_las_fire := Mux(liq(liq_las_ptr).op.fast_sg,
sgas.map(_.io.done && maskindex_gather).getOrElse(false.B), las.io.done)
las.io.tag <> lifq.io.reserve
las.io.out.ready := lifq.io.reserve.valid
lifq.io.entry := las.io.out.bits
lifq.io.push.valid := io.dmem.load_resp.valid
lifq.io.push.bits.data := io.dmem.load_resp.bits.data
lifq.io.push.bits.tag := io.dmem.load_resp.bits.tag
val load_arb = Module(new Arbiter(new MemRequest(dLenB, dmemTagBits), 2))
load_arb.io.in(1) <> las.io.req
load_arb.io.in(1).bits.store := false.B
load_arb.io.in(0) <> lifq.io.replay
load_arb.io.in(0).bits.addr := Cat(liq(lifq.io.replay_liq_id).op.page, lifq.io.replay.bits.addr(pgIdxBits-1,0))
when (io.dmem.store_req.valid) {
load_arb.io.in(0).valid := false.B
lifq.io.replay.ready := false.B
}
// Load compacting
lcu.io.push.valid := lifq.io.deq.valid
lcu.io.push.bits.head := lifq.io.deq.bits.head
lcu.io.push.bits.tail := lifq.io.deq.bits.tail
lcu.io.push_data := lifq.io.deq_data.asTypeOf(Vec(dLenB, UInt(8.W)))
lifq.io.deq.ready := lcu.io.push.ready
sgas.foreach { sgas =>
sgas.io.load_resp.ready := false.B
when (maskindex_gather && !lifq.io.busy) {
sgas.io.load_resp.ready := lcu.io.push.ready
lcu.io.push.valid := sgas.io.load_resp.valid
lcu.io.push.bits := sgas.io.load_resp.bits
lcu.io.push_data := sgas.io.load_data
}
}
// Load segment sequencing
lss.io.valid := liq_lss_valid
lss.io.op := liq(liq_lss_ptr).op
lcu.io.pop <> lss.io.compactor
lss.io.compactor_data := lcu.io.pop_data.asUInt
io.vu.lresp <> lss.io.resp
liq_lss_fire := lss.io.done
// Store segment sequencing
sss.io.valid := siq_sss_valid
sss.io.op := siq(siq_sss_ptr).op
scu.io.push <> sss.io.compactor
scu.io.push_data := sss.io.compactor_data
sss.io.stdata <> io.vu.sdata
siq_sss_fire := sss.io.done
// Store address sequencing
val sas_order_block = (0 until vParams.vliqEntries).map { i =>
val addr_conflict = liq(i).overlaps(siq(siq_sas_ptr))
liq_valids(i) && addr_conflict && siq(siq_sas_ptr).ld_dep_mask(i)
}.orR
sas.io.valid := siq_sas_valid && !sas_order_block && !siq(siq_sas_ptr).op.fast_sg
sas.io.lsiq_id := siq_sas_ptr
sas.io.op := siq(siq_sas_ptr).op
siq_sas_fire := Mux(siq(siq_sas_ptr).op.fast_sg, sgas.map(_.io.done && maskindex_scatter).getOrElse(false.B), sas.io.done)
val store_req_q = Module(new DCEQueue(new MemRequest(dLenB, dmemTagBits), 2))
store_req_q.io.enq <> sas.io.req
store_req_q.io.enq.bits.store := true.B
store_req_q.io.enq.bits.data := VecInit(scu.io.pop_data.map(_.data)).asUInt
store_req_q.io.enq.bits.mask := VecInit(scu.io.pop_data.map(_.mask)).asUInt & sas.io.req.bits.mask
val store_rob = Module(new ReorderBuffer(Bool(), vParams.vsifqEntries))
sas.io.tag <> store_rob.io.reserve
store_rob.io.reserve.ready := sas.io.tag.ready && sas.io.req.valid
sas.io.out.ready := sifq.io.enq.ready && scu.io.pop.ready
sifq.io.enq.valid := sas.io.out.valid && scu.io.pop.ready
sifq.io.enq.bits := sas.io.out.bits
scu.io.pop.valid := sas.io.out.valid && sifq.io.enq.ready
when (scu.io.pop.fire) {
for (i <- 0 until dLenB) {
assert(scu.io.pop_data(i).debug_id === sas.io.op.debug_id ||
i.U < scu.io.pop.bits.head ||
(i.U >= scu.io.pop.bits.tail && scu.io.pop.bits.tail =/= 0.U))
}
}
scu.io.pop.bits.head := sas.io.out.bits.head
scu.io.pop.bits.tail := sas.io.out.bits.tail
sgas.foreach { sgas =>
sgas.io.store_pop.ready := false.B
sgas.io.store_data := scu.io.pop_data.map(_.data)
when (maskindex_scatter && !store_rob.io.busy) {
sgas.io.store_pop.ready := scu.io.pop.ready
scu.io.pop.valid := sgas.io.store_pop.valid
scu.io.pop.bits := sgas.io.store_pop.bits
}
}
store_rob.io.push.valid := io.dmem.store_ack.valid
store_rob.io.push.bits.tag := io.dmem.store_ack.bits.tag
store_rob.io.push.bits.data := DontCare
sifq.io.deq.ready := sifq.io.deq.bits.masked || store_rob.io.deq.valid
store_rob.io.deq.ready := !sifq.io.deq.bits.masked && sifq.io.deq.valid
when (store_rob.io.deq.valid) { assert(sifq.io.deq.valid) }
siq_deq_fire := sifq.io.deq.fire && sifq.io.deq.bits.last
sgas.foreach { sgas =>
when (maskindex_scatter && sgas.io.valid && sgas.io.done) { siq_deq_fire := true.B }
}
if (vParams.latencyInject) {
val latency = Wire(UInt(32.W))
latency := PlusArg("saturn_mem_latency")
val delay_timer = RegInit(0.U(64.W))
delay_timer := delay_timer + 1.U
val load_delay = Module(new DelayQueue(new MemRequest(dLenB, dmemTagBits), 1024, 64))
val store_delay = Module(new DelayQueue(new MemRequest(dLenB, dmemTagBits), 1024, 64))
load_delay.io.timer := delay_timer
store_delay.io.timer := delay_timer
load_delay.io.delay := latency
store_delay.io.delay := latency
load_delay.io.enq <> load_arb.io.out
store_delay.io.enq <> store_req_q.io.deq
io.dmem.load_req <> load_delay.io.deq
io.dmem.store_req <> store_delay.io.deq
} else {
io.dmem.load_req <> load_arb.io.out
io.dmem.store_req <> store_req_q.io.deq
}
io.dmem.load_req.bits.mask := ~(0.U(dLenB.W))
io.busy := liq_valids.orR || siq_valids.orR
}
| module VectorMemUnit( // @[Mem.scala:86:7]
input clock, // @[Mem.scala:86:7]
input reset, // @[Mem.scala:86:7]
output io_enq_ready, // @[Mem.scala:87:14]
input io_enq_valid, // @[Mem.scala:87:14]
input [15:0] io_enq_bits_debug_id, // @[Mem.scala:87:14]
input [11:0] io_enq_bits_base_offset, // @[Mem.scala:87:14]
input [19:0] io_enq_bits_page, // @[Mem.scala:87:14]
input [11:0] io_enq_bits_stride, // @[Mem.scala:87:14]
input [2:0] io_enq_bits_segstart, // @[Mem.scala:87:14]
input [2:0] io_enq_bits_segend, // @[Mem.scala:87:14]
input [5:0] io_enq_bits_vstart, // @[Mem.scala:87:14]
input [6:0] io_enq_bits_vl, // @[Mem.scala:87:14]
input [1:0] io_enq_bits_mop, // @[Mem.scala:87:14]
input io_enq_bits_vm, // @[Mem.scala:87:14]
input [2:0] io_enq_bits_nf, // @[Mem.scala:87:14]
input [1:0] io_enq_bits_idx_size, // @[Mem.scala:87:14]
input [1:0] io_enq_bits_elem_size, // @[Mem.scala:87:14]
input io_enq_bits_whole_reg, // @[Mem.scala:87:14]
input io_enq_bits_store, // @[Mem.scala:87:14]
input io_dmem_load_req_ready, // @[Mem.scala:87:14]
output io_dmem_load_req_valid, // @[Mem.scala:87:14]
output [39:0] io_dmem_load_req_bits_addr, // @[Mem.scala:87:14]
output [3:0] io_dmem_load_req_bits_tag, // @[Mem.scala:87:14]
input io_dmem_load_resp_valid, // @[Mem.scala:87:14]
input [63:0] io_dmem_load_resp_bits_data, // @[Mem.scala:87:14]
input [3:0] io_dmem_load_resp_bits_tag, // @[Mem.scala:87:14]
input io_dmem_store_req_ready, // @[Mem.scala:87:14]
output io_dmem_store_req_valid, // @[Mem.scala:87:14]
output [39:0] io_dmem_store_req_bits_addr, // @[Mem.scala:87:14]
output [63:0] io_dmem_store_req_bits_data, // @[Mem.scala:87:14]
output [7:0] io_dmem_store_req_bits_mask, // @[Mem.scala:87:14]
output [3:0] io_dmem_store_req_bits_tag, // @[Mem.scala:87:14]
input io_dmem_store_ack_valid, // @[Mem.scala:87:14]
input [3:0] io_dmem_store_ack_bits_tag, // @[Mem.scala:87:14]
input [39:0] io_scalar_check_addr, // @[Mem.scala:87:14]
input io_scalar_check_store, // @[Mem.scala:87:14]
output io_scalar_check_conflict, // @[Mem.scala:87:14]
input io_vu_lresp_ready, // @[Mem.scala:87:14]
output io_vu_lresp_valid, // @[Mem.scala:87:14]
output [63:0] io_vu_lresp_bits_data, // @[Mem.scala:87:14]
output [15:0] io_vu_lresp_bits_debug_id, // @[Mem.scala:87:14]
output io_vu_sdata_ready, // @[Mem.scala:87:14]
input io_vu_sdata_valid, // @[Mem.scala:87:14]
input [63:0] io_vu_sdata_bits_stdata, // @[Mem.scala:87:14]
input [7:0] io_vu_sdata_bits_stmask, // @[Mem.scala:87:14]
input [15:0] io_vu_sdata_bits_debug_id, // @[Mem.scala:87:14]
input io_vu_mask_pop_ready, // @[Mem.scala:87:14]
output io_vu_mask_pop_valid, // @[Mem.scala:87:14]
input io_vu_mask_data_0, // @[Mem.scala:87:14]
input io_vu_index_pop_ready, // @[Mem.scala:87:14]
output io_vu_index_pop_valid, // @[Mem.scala:87:14]
output [2:0] io_vu_index_pop_bits_tail, // @[Mem.scala:87:14]
input [7:0] io_vu_index_data_0, // @[Mem.scala:87:14]
input [7:0] io_vu_index_data_1, // @[Mem.scala:87:14]
input [7:0] io_vu_index_data_2, // @[Mem.scala:87:14]
input [7:0] io_vu_index_data_3, // @[Mem.scala:87:14]
input [7:0] io_vu_index_data_4, // @[Mem.scala:87:14]
input [7:0] io_vu_index_data_5, // @[Mem.scala:87:14]
input [7:0] io_vu_index_data_6, // @[Mem.scala:87:14]
input [7:0] io_vu_index_data_7, // @[Mem.scala:87:14]
output io_busy // @[Mem.scala:87:14]
);
wire siq_deq_fire; // @[Decoupled.scala:51:35]
wire _store_rob_io_reserve_valid; // @[Mem.scala:338:25]
wire [3:0] _store_rob_io_reserve_bits; // @[Mem.scala:338:25]
wire _store_rob_io_deq_valid; // @[Mem.scala:338:25]
wire _store_req_q_io_enq_ready; // @[Mem.scala:332:27]
wire _store_req_q_io_deq_valid; // @[Mem.scala:332:27]
wire _load_arb_io_in_0_ready; // @[Mem.scala:279:24]
wire _load_arb_io_in_1_ready; // @[Mem.scala:279:24]
wire _sifq_io_enq_ready; // @[Mem.scala:114:20]
wire _sifq_io_deq_valid; // @[Mem.scala:114:20]
wire _sifq_io_deq_bits_masked; // @[Mem.scala:114:20]
wire _sifq_io_deq_bits_last; // @[Mem.scala:114:20]
wire _sas_io_done; // @[Mem.scala:113:19]
wire _sas_io_tag_ready; // @[Mem.scala:113:19]
wire [1:0] _sas_io_maskindex_eew; // @[Mem.scala:113:19]
wire _sas_io_maskindex_needs_mask; // @[Mem.scala:113:19]
wire _sas_io_maskindex_needs_index; // @[Mem.scala:113:19]
wire _sas_io_maskindex_ready; // @[Mem.scala:113:19]
wire _sas_io_req_valid; // @[Mem.scala:113:19]
wire [39:0] _sas_io_req_bits_addr; // @[Mem.scala:113:19]
wire [7:0] _sas_io_req_bits_mask; // @[Mem.scala:113:19]
wire [3:0] _sas_io_req_bits_tag; // @[Mem.scala:113:19]
wire _sas_io_out_valid; // @[Mem.scala:113:19]
wire [2:0] _sas_io_out_bits_head; // @[Mem.scala:113:19]
wire [2:0] _sas_io_out_bits_tail; // @[Mem.scala:113:19]
wire _sas_io_out_bits_masked; // @[Mem.scala:113:19]
wire _sas_io_out_bits_last; // @[Mem.scala:113:19]
wire _sss_io_done; // @[Mem.scala:112:19]
wire _sss_io_compactor_valid; // @[Mem.scala:112:19]
wire [2:0] _sss_io_compactor_bits_head; // @[Mem.scala:112:19]
wire [2:0] _sss_io_compactor_bits_tail; // @[Mem.scala:112:19]
wire [15:0] _sss_io_compactor_data_0_debug_id; // @[Mem.scala:112:19]
wire [7:0] _sss_io_compactor_data_0_data; // @[Mem.scala:112:19]
wire _sss_io_compactor_data_0_mask; // @[Mem.scala:112:19]
wire [15:0] _sss_io_compactor_data_1_debug_id; // @[Mem.scala:112:19]
wire [7:0] _sss_io_compactor_data_1_data; // @[Mem.scala:112:19]
wire _sss_io_compactor_data_1_mask; // @[Mem.scala:112:19]
wire [15:0] _sss_io_compactor_data_2_debug_id; // @[Mem.scala:112:19]
wire [7:0] _sss_io_compactor_data_2_data; // @[Mem.scala:112:19]
wire _sss_io_compactor_data_2_mask; // @[Mem.scala:112:19]
wire [15:0] _sss_io_compactor_data_3_debug_id; // @[Mem.scala:112:19]
wire [7:0] _sss_io_compactor_data_3_data; // @[Mem.scala:112:19]
wire _sss_io_compactor_data_3_mask; // @[Mem.scala:112:19]
wire [15:0] _sss_io_compactor_data_4_debug_id; // @[Mem.scala:112:19]
wire [7:0] _sss_io_compactor_data_4_data; // @[Mem.scala:112:19]
wire _sss_io_compactor_data_4_mask; // @[Mem.scala:112:19]
wire [15:0] _sss_io_compactor_data_5_debug_id; // @[Mem.scala:112:19]
wire [7:0] _sss_io_compactor_data_5_data; // @[Mem.scala:112:19]
wire _sss_io_compactor_data_5_mask; // @[Mem.scala:112:19]
wire [15:0] _sss_io_compactor_data_6_debug_id; // @[Mem.scala:112:19]
wire [7:0] _sss_io_compactor_data_6_data; // @[Mem.scala:112:19]
wire _sss_io_compactor_data_6_mask; // @[Mem.scala:112:19]
wire [15:0] _sss_io_compactor_data_7_debug_id; // @[Mem.scala:112:19]
wire [7:0] _sss_io_compactor_data_7_data; // @[Mem.scala:112:19]
wire _sss_io_compactor_data_7_mask; // @[Mem.scala:112:19]
wire _scu_io_push_ready; // @[Mem.scala:111:19]
wire _scu_io_pop_ready; // @[Mem.scala:111:19]
wire [15:0] _scu_io_pop_data_0_debug_id; // @[Mem.scala:111:19]
wire [7:0] _scu_io_pop_data_0_data; // @[Mem.scala:111:19]
wire _scu_io_pop_data_0_mask; // @[Mem.scala:111:19]
wire [15:0] _scu_io_pop_data_1_debug_id; // @[Mem.scala:111:19]
wire [7:0] _scu_io_pop_data_1_data; // @[Mem.scala:111:19]
wire _scu_io_pop_data_1_mask; // @[Mem.scala:111:19]
wire [15:0] _scu_io_pop_data_2_debug_id; // @[Mem.scala:111:19]
wire [7:0] _scu_io_pop_data_2_data; // @[Mem.scala:111:19]
wire _scu_io_pop_data_2_mask; // @[Mem.scala:111:19]
wire [15:0] _scu_io_pop_data_3_debug_id; // @[Mem.scala:111:19]
wire [7:0] _scu_io_pop_data_3_data; // @[Mem.scala:111:19]
wire _scu_io_pop_data_3_mask; // @[Mem.scala:111:19]
wire [15:0] _scu_io_pop_data_4_debug_id; // @[Mem.scala:111:19]
wire [7:0] _scu_io_pop_data_4_data; // @[Mem.scala:111:19]
wire _scu_io_pop_data_4_mask; // @[Mem.scala:111:19]
wire [15:0] _scu_io_pop_data_5_debug_id; // @[Mem.scala:111:19]
wire [7:0] _scu_io_pop_data_5_data; // @[Mem.scala:111:19]
wire _scu_io_pop_data_5_mask; // @[Mem.scala:111:19]
wire [15:0] _scu_io_pop_data_6_debug_id; // @[Mem.scala:111:19]
wire [7:0] _scu_io_pop_data_6_data; // @[Mem.scala:111:19]
wire _scu_io_pop_data_6_mask; // @[Mem.scala:111:19]
wire [15:0] _scu_io_pop_data_7_debug_id; // @[Mem.scala:111:19]
wire [7:0] _scu_io_pop_data_7_data; // @[Mem.scala:111:19]
wire _scu_io_pop_data_7_mask; // @[Mem.scala:111:19]
wire _lss_io_done; // @[Mem.scala:109:19]
wire _lss_io_compactor_valid; // @[Mem.scala:109:19]
wire [2:0] _lss_io_compactor_bits_head; // @[Mem.scala:109:19]
wire [2:0] _lss_io_compactor_bits_tail; // @[Mem.scala:109:19]
wire _lcu_io_push_ready; // @[Mem.scala:108:19]
wire _lcu_io_pop_ready; // @[Mem.scala:108:19]
wire [7:0] _lcu_io_pop_data_0; // @[Mem.scala:108:19]
wire [7:0] _lcu_io_pop_data_1; // @[Mem.scala:108:19]
wire [7:0] _lcu_io_pop_data_2; // @[Mem.scala:108:19]
wire [7:0] _lcu_io_pop_data_3; // @[Mem.scala:108:19]
wire [7:0] _lcu_io_pop_data_4; // @[Mem.scala:108:19]
wire [7:0] _lcu_io_pop_data_5; // @[Mem.scala:108:19]
wire [7:0] _lcu_io_pop_data_6; // @[Mem.scala:108:19]
wire [7:0] _lcu_io_pop_data_7; // @[Mem.scala:108:19]
wire _lifq_io_reserve_valid; // @[Mem.scala:107:20]
wire [2:0] _lifq_io_reserve_bits; // @[Mem.scala:107:20]
wire [1:0] _lifq_io_replay_liq_id; // @[Mem.scala:107:20]
wire _lifq_io_replay_valid; // @[Mem.scala:107:20]
wire [39:0] _lifq_io_replay_bits_addr; // @[Mem.scala:107:20]
wire [3:0] _lifq_io_replay_bits_tag; // @[Mem.scala:107:20]
wire _lifq_io_deq_valid; // @[Mem.scala:107:20]
wire [2:0] _lifq_io_deq_bits_head; // @[Mem.scala:107:20]
wire [2:0] _lifq_io_deq_bits_tail; // @[Mem.scala:107:20]
wire [63:0] _lifq_io_deq_data; // @[Mem.scala:107:20]
wire _las_io_done; // @[Mem.scala:106:19]
wire _las_io_tag_ready; // @[Mem.scala:106:19]
wire [1:0] _las_io_maskindex_eew; // @[Mem.scala:106:19]
wire _las_io_maskindex_needs_mask; // @[Mem.scala:106:19]
wire _las_io_maskindex_needs_index; // @[Mem.scala:106:19]
wire _las_io_maskindex_ready; // @[Mem.scala:106:19]
wire _las_io_req_valid; // @[Mem.scala:106:19]
wire [39:0] _las_io_req_bits_addr; // @[Mem.scala:106:19]
wire [3:0] _las_io_req_bits_tag; // @[Mem.scala:106:19]
wire [2:0] _las_io_out_bits_head; // @[Mem.scala:106:19]
wire [2:0] _las_io_out_bits_tail; // @[Mem.scala:106:19]
wire _las_io_out_bits_masked; // @[Mem.scala:106:19]
wire [1:0] _las_io_out_bits_lsiq_id; // @[Mem.scala:106:19]
wire [11:0] _las_io_out_bits_page_offset; // @[Mem.scala:106:19]
reg [15:0] liq_0_op_debug_id; // @[Mem.scala:116:16]
reg [11:0] liq_0_op_base_offset; // @[Mem.scala:116:16]
reg [19:0] liq_0_op_page; // @[Mem.scala:116:16]
reg [11:0] liq_0_op_stride; // @[Mem.scala:116:16]
reg [2:0] liq_0_op_segstart; // @[Mem.scala:116:16]
reg [2:0] liq_0_op_segend; // @[Mem.scala:116:16]
reg [5:0] liq_0_op_vstart; // @[Mem.scala:116:16]
reg [6:0] liq_0_op_vl; // @[Mem.scala:116:16]
reg [1:0] liq_0_op_mop; // @[Mem.scala:116:16]
reg liq_0_op_vm; // @[Mem.scala:116:16]
reg [2:0] liq_0_op_nf; // @[Mem.scala:116:16]
reg [1:0] liq_0_op_idx_size; // @[Mem.scala:116:16]
reg [1:0] liq_0_op_elem_size; // @[Mem.scala:116:16]
reg liq_0_op_whole_reg; // @[Mem.scala:116:16]
reg liq_0_op_fast_sg; // @[Mem.scala:116:16]
reg [11:0] liq_0_bound_offset; // @[Mem.scala:116:16]
reg liq_0_st_dep_mask_0; // @[Mem.scala:116:16]
reg liq_0_st_dep_mask_1; // @[Mem.scala:116:16]
reg liq_0_st_dep_mask_2; // @[Mem.scala:116:16]
reg liq_0_st_dep_mask_3; // @[Mem.scala:116:16]
reg [15:0] liq_1_op_debug_id; // @[Mem.scala:116:16]
reg [11:0] liq_1_op_base_offset; // @[Mem.scala:116:16]
reg [19:0] liq_1_op_page; // @[Mem.scala:116:16]
reg [11:0] liq_1_op_stride; // @[Mem.scala:116:16]
reg [2:0] liq_1_op_segstart; // @[Mem.scala:116:16]
reg [2:0] liq_1_op_segend; // @[Mem.scala:116:16]
reg [5:0] liq_1_op_vstart; // @[Mem.scala:116:16]
reg [6:0] liq_1_op_vl; // @[Mem.scala:116:16]
reg [1:0] liq_1_op_mop; // @[Mem.scala:116:16]
reg liq_1_op_vm; // @[Mem.scala:116:16]
reg [2:0] liq_1_op_nf; // @[Mem.scala:116:16]
reg [1:0] liq_1_op_idx_size; // @[Mem.scala:116:16]
reg [1:0] liq_1_op_elem_size; // @[Mem.scala:116:16]
reg liq_1_op_whole_reg; // @[Mem.scala:116:16]
reg liq_1_op_fast_sg; // @[Mem.scala:116:16]
reg [11:0] liq_1_bound_offset; // @[Mem.scala:116:16]
reg liq_1_st_dep_mask_0; // @[Mem.scala:116:16]
reg liq_1_st_dep_mask_1; // @[Mem.scala:116:16]
reg liq_1_st_dep_mask_2; // @[Mem.scala:116:16]
reg liq_1_st_dep_mask_3; // @[Mem.scala:116:16]
reg [15:0] liq_2_op_debug_id; // @[Mem.scala:116:16]
reg [11:0] liq_2_op_base_offset; // @[Mem.scala:116:16]
reg [19:0] liq_2_op_page; // @[Mem.scala:116:16]
reg [11:0] liq_2_op_stride; // @[Mem.scala:116:16]
reg [2:0] liq_2_op_segstart; // @[Mem.scala:116:16]
reg [2:0] liq_2_op_segend; // @[Mem.scala:116:16]
reg [5:0] liq_2_op_vstart; // @[Mem.scala:116:16]
reg [6:0] liq_2_op_vl; // @[Mem.scala:116:16]
reg [1:0] liq_2_op_mop; // @[Mem.scala:116:16]
reg liq_2_op_vm; // @[Mem.scala:116:16]
reg [2:0] liq_2_op_nf; // @[Mem.scala:116:16]
reg [1:0] liq_2_op_idx_size; // @[Mem.scala:116:16]
reg [1:0] liq_2_op_elem_size; // @[Mem.scala:116:16]
reg liq_2_op_whole_reg; // @[Mem.scala:116:16]
reg liq_2_op_fast_sg; // @[Mem.scala:116:16]
reg [11:0] liq_2_bound_offset; // @[Mem.scala:116:16]
reg liq_2_st_dep_mask_0; // @[Mem.scala:116:16]
reg liq_2_st_dep_mask_1; // @[Mem.scala:116:16]
reg liq_2_st_dep_mask_2; // @[Mem.scala:116:16]
reg liq_2_st_dep_mask_3; // @[Mem.scala:116:16]
reg [15:0] liq_3_op_debug_id; // @[Mem.scala:116:16]
reg [11:0] liq_3_op_base_offset; // @[Mem.scala:116:16]
reg [19:0] liq_3_op_page; // @[Mem.scala:116:16]
reg [11:0] liq_3_op_stride; // @[Mem.scala:116:16]
reg [2:0] liq_3_op_segstart; // @[Mem.scala:116:16]
reg [2:0] liq_3_op_segend; // @[Mem.scala:116:16]
reg [5:0] liq_3_op_vstart; // @[Mem.scala:116:16]
reg [6:0] liq_3_op_vl; // @[Mem.scala:116:16]
reg [1:0] liq_3_op_mop; // @[Mem.scala:116:16]
reg liq_3_op_vm; // @[Mem.scala:116:16]
reg [2:0] liq_3_op_nf; // @[Mem.scala:116:16]
reg [1:0] liq_3_op_idx_size; // @[Mem.scala:116:16]
reg [1:0] liq_3_op_elem_size; // @[Mem.scala:116:16]
reg liq_3_op_whole_reg; // @[Mem.scala:116:16]
reg liq_3_op_fast_sg; // @[Mem.scala:116:16]
reg [11:0] liq_3_bound_offset; // @[Mem.scala:116:16]
reg liq_3_st_dep_mask_0; // @[Mem.scala:116:16]
reg liq_3_st_dep_mask_1; // @[Mem.scala:116:16]
reg liq_3_st_dep_mask_2; // @[Mem.scala:116:16]
reg liq_3_st_dep_mask_3; // @[Mem.scala:116:16]
reg liq_valids_0; // @[Mem.scala:117:30]
reg liq_valids_1; // @[Mem.scala:117:30]
reg liq_valids_2; // @[Mem.scala:117:30]
reg liq_valids_3; // @[Mem.scala:117:30]
reg liq_las_0; // @[Mem.scala:118:30]
reg liq_las_1; // @[Mem.scala:118:30]
reg liq_las_2; // @[Mem.scala:118:30]
reg liq_las_3; // @[Mem.scala:118:30]
reg [1:0] liq_enq_ptr; // @[Mem.scala:119:30]
reg [1:0] liq_las_ptr; // @[Mem.scala:120:30]
reg [1:0] liq_lss_ptr; // @[Mem.scala:121:30]
wire [3:0] _GEN = {{liq_valids_3}, {liq_valids_2}, {liq_valids_1}, {liq_valids_0}}; // @[Mem.scala:117:30, :127:23]
wire _GEN_0 = _GEN[liq_enq_ptr]; // @[Mem.scala:119:30, :127:23]
wire [3:0] _GEN_1 = {{liq_las_3}, {liq_las_2}, {liq_las_1}, {liq_las_0}}; // @[Mem.scala:118:30, :128:23]
wire liq_las_valid = ~_GEN_1[liq_las_ptr] & _GEN[liq_las_ptr]; // @[Mem.scala:120:30, :127:23, :128:{23,45}]
reg [15:0] siq_0_op_debug_id; // @[Mem.scala:131:16]
reg [11:0] siq_0_op_base_offset; // @[Mem.scala:131:16]
reg [19:0] siq_0_op_page; // @[Mem.scala:131:16]
reg [11:0] siq_0_op_stride; // @[Mem.scala:131:16]
reg [2:0] siq_0_op_segstart; // @[Mem.scala:131:16]
reg [2:0] siq_0_op_segend; // @[Mem.scala:131:16]
reg [5:0] siq_0_op_vstart; // @[Mem.scala:131:16]
reg [6:0] siq_0_op_vl; // @[Mem.scala:131:16]
reg [1:0] siq_0_op_mop; // @[Mem.scala:131:16]
reg siq_0_op_vm; // @[Mem.scala:131:16]
reg [2:0] siq_0_op_nf; // @[Mem.scala:131:16]
reg [1:0] siq_0_op_idx_size; // @[Mem.scala:131:16]
reg [1:0] siq_0_op_elem_size; // @[Mem.scala:131:16]
reg siq_0_op_whole_reg; // @[Mem.scala:131:16]
reg siq_0_op_fast_sg; // @[Mem.scala:131:16]
reg [11:0] siq_0_bound_offset; // @[Mem.scala:131:16]
reg siq_0_ld_dep_mask_0; // @[Mem.scala:131:16]
reg siq_0_ld_dep_mask_1; // @[Mem.scala:131:16]
reg siq_0_ld_dep_mask_2; // @[Mem.scala:131:16]
reg siq_0_ld_dep_mask_3; // @[Mem.scala:131:16]
reg [15:0] siq_1_op_debug_id; // @[Mem.scala:131:16]
reg [11:0] siq_1_op_base_offset; // @[Mem.scala:131:16]
reg [19:0] siq_1_op_page; // @[Mem.scala:131:16]
reg [11:0] siq_1_op_stride; // @[Mem.scala:131:16]
reg [2:0] siq_1_op_segstart; // @[Mem.scala:131:16]
reg [2:0] siq_1_op_segend; // @[Mem.scala:131:16]
reg [5:0] siq_1_op_vstart; // @[Mem.scala:131:16]
reg [6:0] siq_1_op_vl; // @[Mem.scala:131:16]
reg [1:0] siq_1_op_mop; // @[Mem.scala:131:16]
reg siq_1_op_vm; // @[Mem.scala:131:16]
reg [2:0] siq_1_op_nf; // @[Mem.scala:131:16]
reg [1:0] siq_1_op_idx_size; // @[Mem.scala:131:16]
reg [1:0] siq_1_op_elem_size; // @[Mem.scala:131:16]
reg siq_1_op_whole_reg; // @[Mem.scala:131:16]
reg siq_1_op_fast_sg; // @[Mem.scala:131:16]
reg [11:0] siq_1_bound_offset; // @[Mem.scala:131:16]
reg siq_1_ld_dep_mask_0; // @[Mem.scala:131:16]
reg siq_1_ld_dep_mask_1; // @[Mem.scala:131:16]
reg siq_1_ld_dep_mask_2; // @[Mem.scala:131:16]
reg siq_1_ld_dep_mask_3; // @[Mem.scala:131:16]
reg [15:0] siq_2_op_debug_id; // @[Mem.scala:131:16]
reg [11:0] siq_2_op_base_offset; // @[Mem.scala:131:16]
reg [19:0] siq_2_op_page; // @[Mem.scala:131:16]
reg [11:0] siq_2_op_stride; // @[Mem.scala:131:16]
reg [2:0] siq_2_op_segstart; // @[Mem.scala:131:16]
reg [2:0] siq_2_op_segend; // @[Mem.scala:131:16]
reg [5:0] siq_2_op_vstart; // @[Mem.scala:131:16]
reg [6:0] siq_2_op_vl; // @[Mem.scala:131:16]
reg [1:0] siq_2_op_mop; // @[Mem.scala:131:16]
reg siq_2_op_vm; // @[Mem.scala:131:16]
reg [2:0] siq_2_op_nf; // @[Mem.scala:131:16]
reg [1:0] siq_2_op_idx_size; // @[Mem.scala:131:16]
reg [1:0] siq_2_op_elem_size; // @[Mem.scala:131:16]
reg siq_2_op_whole_reg; // @[Mem.scala:131:16]
reg siq_2_op_fast_sg; // @[Mem.scala:131:16]
reg [11:0] siq_2_bound_offset; // @[Mem.scala:131:16]
reg siq_2_ld_dep_mask_0; // @[Mem.scala:131:16]
reg siq_2_ld_dep_mask_1; // @[Mem.scala:131:16]
reg siq_2_ld_dep_mask_2; // @[Mem.scala:131:16]
reg siq_2_ld_dep_mask_3; // @[Mem.scala:131:16]
reg [15:0] siq_3_op_debug_id; // @[Mem.scala:131:16]
reg [11:0] siq_3_op_base_offset; // @[Mem.scala:131:16]
reg [19:0] siq_3_op_page; // @[Mem.scala:131:16]
reg [11:0] siq_3_op_stride; // @[Mem.scala:131:16]
reg [2:0] siq_3_op_segstart; // @[Mem.scala:131:16]
reg [2:0] siq_3_op_segend; // @[Mem.scala:131:16]
reg [5:0] siq_3_op_vstart; // @[Mem.scala:131:16]
reg [6:0] siq_3_op_vl; // @[Mem.scala:131:16]
reg [1:0] siq_3_op_mop; // @[Mem.scala:131:16]
reg siq_3_op_vm; // @[Mem.scala:131:16]
reg [2:0] siq_3_op_nf; // @[Mem.scala:131:16]
reg [1:0] siq_3_op_idx_size; // @[Mem.scala:131:16]
reg [1:0] siq_3_op_elem_size; // @[Mem.scala:131:16]
reg siq_3_op_whole_reg; // @[Mem.scala:131:16]
reg siq_3_op_fast_sg; // @[Mem.scala:131:16]
reg [11:0] siq_3_bound_offset; // @[Mem.scala:131:16]
reg siq_3_ld_dep_mask_0; // @[Mem.scala:131:16]
reg siq_3_ld_dep_mask_1; // @[Mem.scala:131:16]
reg siq_3_ld_dep_mask_2; // @[Mem.scala:131:16]
reg siq_3_ld_dep_mask_3; // @[Mem.scala:131:16]
reg siq_valids_0; // @[Mem.scala:132:30]
reg siq_valids_1; // @[Mem.scala:132:30]
reg siq_valids_2; // @[Mem.scala:132:30]
reg siq_valids_3; // @[Mem.scala:132:30]
reg siq_sss_0; // @[Mem.scala:133:30]
reg siq_sss_1; // @[Mem.scala:133:30]
reg siq_sss_2; // @[Mem.scala:133:30]
reg siq_sss_3; // @[Mem.scala:133:30]
reg siq_sas_0; // @[Mem.scala:134:30]
reg siq_sas_1; // @[Mem.scala:134:30]
reg siq_sas_2; // @[Mem.scala:134:30]
reg siq_sas_3; // @[Mem.scala:134:30]
reg [1:0] siq_enq_ptr; // @[Mem.scala:135:30]
reg [1:0] siq_sss_ptr; // @[Mem.scala:136:30]
reg [1:0] siq_sas_ptr; // @[Mem.scala:137:30]
reg [1:0] siq_deq_ptr; // @[Mem.scala:138:30]
wire [3:0] _GEN_2 = {{siq_valids_3}, {siq_valids_2}, {siq_valids_1}, {siq_valids_0}}; // @[Mem.scala:132:30, :145:23]
wire _GEN_3 = _GEN_2[siq_enq_ptr]; // @[Mem.scala:135:30, :145:23]
wire [3:0] _GEN_4 = {{siq_sss_3}, {siq_sss_2}, {siq_sss_1}, {siq_sss_0}}; // @[Mem.scala:133:30, :146:23]
wire [3:0] _GEN_5 = {{siq_sas_3}, {siq_sas_2}, {siq_sas_1}, {siq_sas_0}}; // @[Mem.scala:134:30, :147:23]
wire siq_sas_valid = ~_GEN_5[siq_sas_ptr] & _GEN_2[siq_sas_ptr]; // @[Mem.scala:137:30, :145:23, :147:{23,45}]
wire liq_enq_fire = io_enq_valid & ~_GEN_0 & ~io_enq_bits_store; // @[Mem.scala:127:23, :195:{32,49,52}]
wire siq_enq_fire = io_enq_valid & ~_GEN_3 & io_enq_bits_store; // @[Mem.scala:145:23, :196:{32,49}]
wire [3:0][11:0] _GEN_6 = {{liq_3_op_base_offset}, {liq_2_op_base_offset}, {liq_1_op_base_offset}, {liq_0_op_base_offset}}; // @[Mem.scala:116:16, :211:46]
wire [11:0] las_io_op_base_offset = _GEN_6[liq_las_ptr]; // @[Mem.scala:120:30, :211:46]
wire [3:0][19:0] _GEN_7 = {{liq_3_op_page}, {liq_2_op_page}, {liq_1_op_page}, {liq_0_op_page}}; // @[Mem.scala:116:16, :211:46]
wire [19:0] las_io_op_page = _GEN_7[liq_las_ptr]; // @[Mem.scala:120:30, :211:46]
wire [3:0][11:0] _GEN_8 = {{liq_3_op_stride}, {liq_2_op_stride}, {liq_1_op_stride}, {liq_0_op_stride}}; // @[Mem.scala:116:16, :211:46]
wire [3:0][2:0] _GEN_9 = {{liq_3_op_segstart}, {liq_2_op_segstart}, {liq_1_op_segstart}, {liq_0_op_segstart}}; // @[Mem.scala:116:16, :211:46]
wire [3:0][2:0] _GEN_10 = {{liq_3_op_segend}, {liq_2_op_segend}, {liq_1_op_segend}, {liq_0_op_segend}}; // @[Mem.scala:116:16, :211:46]
wire [3:0][5:0] _GEN_11 = {{liq_3_op_vstart}, {liq_2_op_vstart}, {liq_1_op_vstart}, {liq_0_op_vstart}}; // @[Mem.scala:116:16, :211:46]
wire [3:0][6:0] _GEN_12 = {{liq_3_op_vl}, {liq_2_op_vl}, {liq_1_op_vl}, {liq_0_op_vl}}; // @[Mem.scala:116:16, :211:46]
wire [3:0][1:0] _GEN_13 = {{liq_3_op_mop}, {liq_2_op_mop}, {liq_1_op_mop}, {liq_0_op_mop}}; // @[Mem.scala:116:16, :211:46]
wire [1:0] las_io_op_mop = _GEN_13[liq_las_ptr]; // @[Mem.scala:120:30, :211:46]
wire [3:0] _GEN_14 = {{liq_3_op_vm}, {liq_2_op_vm}, {liq_1_op_vm}, {liq_0_op_vm}}; // @[Mem.scala:116:16, :211:46]
wire [3:0][2:0] _GEN_15 = {{liq_3_op_nf}, {liq_2_op_nf}, {liq_1_op_nf}, {liq_0_op_nf}}; // @[Mem.scala:116:16, :211:46]
wire [3:0][1:0] _GEN_16 = {{liq_3_op_idx_size}, {liq_2_op_idx_size}, {liq_1_op_idx_size}, {liq_0_op_idx_size}}; // @[Mem.scala:116:16, :211:46]
wire [3:0][1:0] _GEN_17 = {{liq_3_op_elem_size}, {liq_2_op_elem_size}, {liq_1_op_elem_size}, {liq_0_op_elem_size}}; // @[Mem.scala:116:16, :211:46]
wire [3:0] _GEN_18 = {{liq_3_op_whole_reg}, {liq_2_op_whole_reg}, {liq_1_op_whole_reg}, {liq_0_op_whole_reg}}; // @[Mem.scala:116:16, :211:46]
wire [3:0] _GEN_19 = {{liq_3_op_fast_sg}, {liq_2_op_fast_sg}, {liq_1_op_fast_sg}, {liq_0_op_fast_sg}}; // @[Mem.scala:116:16, :211:46]
wire _GEN_20 = _GEN_19[liq_las_ptr]; // @[Mem.scala:120:30, :211:46]
wire [3:0][11:0] _GEN_21 = {{liq_3_bound_offset}, {liq_2_bound_offset}, {liq_1_bound_offset}, {liq_0_bound_offset}}; // @[Mem.scala:116:16, :211:46]
wire [11:0] _GEN_22 = _GEN_21[liq_las_ptr]; // @[Mem.scala:120:30, :211:46]
wire [3:0] _GEN_23 = {{liq_3_st_dep_mask_0}, {liq_2_st_dep_mask_0}, {liq_1_st_dep_mask_0}, {liq_0_st_dep_mask_0}}; // @[Mem.scala:116:16, :211:46]
wire _GEN_24 = _GEN_23[liq_las_ptr]; // @[Mem.scala:120:30, :211:46]
wire [3:0] _GEN_25 = {{liq_3_st_dep_mask_1}, {liq_2_st_dep_mask_1}, {liq_1_st_dep_mask_1}, {liq_0_st_dep_mask_1}}; // @[Mem.scala:116:16, :211:46]
wire _GEN_26 = _GEN_25[liq_las_ptr]; // @[Mem.scala:120:30, :211:46]
wire [3:0] _GEN_27 = {{liq_3_st_dep_mask_2}, {liq_2_st_dep_mask_2}, {liq_1_st_dep_mask_2}, {liq_0_st_dep_mask_2}}; // @[Mem.scala:116:16, :211:46]
wire _GEN_28 = _GEN_27[liq_las_ptr]; // @[Mem.scala:120:30, :211:46]
wire [3:0] _GEN_29 = {{liq_3_st_dep_mask_3}, {liq_2_st_dep_mask_3}, {liq_1_st_dep_mask_3}, {liq_0_st_dep_mask_3}}; // @[Mem.scala:116:16, :211:46]
wire _GEN_30 = _GEN_29[liq_las_ptr]; // @[Mem.scala:120:30, :211:46]
wire [3:0] _GEN_31 = {{_GEN_30}, {_GEN_28}, {_GEN_26}, {_GEN_24}}; // @[Mem.scala:211:46]
wire las_older_than_sas = liq_las_valid & ~_GEN_31[siq_sas_ptr] | ~siq_sas_valid; // @[Mem.scala:128:45, :137:30, :147:45, :211:{43,46,90,93}]
wire maskindex_load = liq_las_valid & las_older_than_sas & ~_GEN_20; // @[Mem.scala:128:45, :211:{46,90}, :212:{41,64,67}]
wire [3:0][15:0] _GEN_32 = {{siq_3_op_debug_id}, {siq_2_op_debug_id}, {siq_1_op_debug_id}, {siq_0_op_debug_id}}; // @[Mem.scala:131:16, :213:67]
wire [3:0][11:0] _GEN_33 = {{siq_3_op_base_offset}, {siq_2_op_base_offset}, {siq_1_op_base_offset}, {siq_0_op_base_offset}}; // @[Mem.scala:131:16, :213:67]
wire [11:0] sas_io_op_base_offset = _GEN_33[siq_sas_ptr]; // @[Mem.scala:137:30, :213:67]
wire [3:0][19:0] _GEN_34 = {{siq_3_op_page}, {siq_2_op_page}, {siq_1_op_page}, {siq_0_op_page}}; // @[Mem.scala:131:16, :213:67]
wire [19:0] sas_io_op_page = _GEN_34[siq_sas_ptr]; // @[Mem.scala:137:30, :213:67]
wire [3:0][11:0] _GEN_35 = {{siq_3_op_stride}, {siq_2_op_stride}, {siq_1_op_stride}, {siq_0_op_stride}}; // @[Mem.scala:131:16, :213:67]
wire [3:0][2:0] _GEN_36 = {{siq_3_op_segstart}, {siq_2_op_segstart}, {siq_1_op_segstart}, {siq_0_op_segstart}}; // @[Mem.scala:131:16, :213:67]
wire [3:0][2:0] _GEN_37 = {{siq_3_op_segend}, {siq_2_op_segend}, {siq_1_op_segend}, {siq_0_op_segend}}; // @[Mem.scala:131:16, :213:67]
wire [3:0][5:0] _GEN_38 = {{siq_3_op_vstart}, {siq_2_op_vstart}, {siq_1_op_vstart}, {siq_0_op_vstart}}; // @[Mem.scala:131:16, :213:67]
wire [3:0][6:0] _GEN_39 = {{siq_3_op_vl}, {siq_2_op_vl}, {siq_1_op_vl}, {siq_0_op_vl}}; // @[Mem.scala:131:16, :213:67]
wire [3:0][1:0] _GEN_40 = {{siq_3_op_mop}, {siq_2_op_mop}, {siq_1_op_mop}, {siq_0_op_mop}}; // @[Mem.scala:131:16, :213:67]
wire [1:0] sas_io_op_mop = _GEN_40[siq_sas_ptr]; // @[Mem.scala:137:30, :213:67]
wire [3:0] _GEN_41 = {{siq_3_op_vm}, {siq_2_op_vm}, {siq_1_op_vm}, {siq_0_op_vm}}; // @[Mem.scala:131:16, :213:67]
wire [3:0][2:0] _GEN_42 = {{siq_3_op_nf}, {siq_2_op_nf}, {siq_1_op_nf}, {siq_0_op_nf}}; // @[Mem.scala:131:16, :213:67]
wire [3:0][1:0] _GEN_43 = {{siq_3_op_idx_size}, {siq_2_op_idx_size}, {siq_1_op_idx_size}, {siq_0_op_idx_size}}; // @[Mem.scala:131:16, :213:67]
wire [3:0][1:0] _GEN_44 = {{siq_3_op_elem_size}, {siq_2_op_elem_size}, {siq_1_op_elem_size}, {siq_0_op_elem_size}}; // @[Mem.scala:131:16, :213:67]
wire [3:0] _GEN_45 = {{siq_3_op_whole_reg}, {siq_2_op_whole_reg}, {siq_1_op_whole_reg}, {siq_0_op_whole_reg}}; // @[Mem.scala:131:16, :213:67]
wire [3:0] _GEN_46 = {{siq_3_op_fast_sg}, {siq_2_op_fast_sg}, {siq_1_op_fast_sg}, {siq_0_op_fast_sg}}; // @[Mem.scala:131:16, :213:67]
wire _GEN_47 = _GEN_46[siq_sas_ptr]; // @[Mem.scala:137:30, :213:67]
wire [3:0][11:0] _GEN_48 = {{siq_3_bound_offset}, {siq_2_bound_offset}, {siq_1_bound_offset}, {siq_0_bound_offset}}; // @[Mem.scala:131:16, :213:67]
wire [11:0] _GEN_49 = _GEN_48[siq_sas_ptr]; // @[Mem.scala:137:30, :213:67]
wire [3:0] _GEN_50 = {{siq_3_ld_dep_mask_0}, {siq_2_ld_dep_mask_0}, {siq_1_ld_dep_mask_0}, {siq_0_ld_dep_mask_0}}; // @[Mem.scala:131:16, :213:67]
wire [3:0] _GEN_51 = {{siq_3_ld_dep_mask_1}, {siq_2_ld_dep_mask_1}, {siq_1_ld_dep_mask_1}, {siq_0_ld_dep_mask_1}}; // @[Mem.scala:131:16, :213:67]
wire [3:0] _GEN_52 = {{siq_3_ld_dep_mask_2}, {siq_2_ld_dep_mask_2}, {siq_1_ld_dep_mask_2}, {siq_0_ld_dep_mask_2}}; // @[Mem.scala:131:16, :213:67]
wire [3:0] _GEN_53 = {{siq_3_ld_dep_mask_3}, {siq_2_ld_dep_mask_3}, {siq_1_ld_dep_mask_3}, {siq_0_ld_dep_mask_3}}; // @[Mem.scala:131:16, :213:67]
wire maskindex_store = siq_sas_valid & ~las_older_than_sas & ~_GEN_47; // @[Mem.scala:147:45, :211:90, :213:{41,44,64,67}]
wire [3:0] _io_vu_index_pop_bits_tail_T = 4'h1 << _las_io_maskindex_eew; // @[Mem.scala:106:19, :230:38]
wire [3:0] _io_vu_index_pop_bits_tail_T_1 = 4'h1 << _sas_io_maskindex_eew; // @[Mem.scala:113:19, :235:38]
wire liq_las_fire = ~_GEN_20 & _las_io_done; // @[Mem.scala:106:19, :211:46, :268:22]
wire [3:0][15:0] _GEN_54 = {{liq_3_op_debug_id}, {liq_2_op_debug_id}, {liq_1_op_debug_id}, {liq_0_op_debug_id}}; // @[Mem.scala:116:16, :308:13]
wire siq_sas_fire = ~_GEN_47 & _sas_io_done; // @[Mem.scala:113:19, :213:67, :330:22]
wire scu_io_pop_valid = _sas_io_out_valid & _sifq_io_enq_ready; // @[Mem.scala:113:19, :114:20, :345:40]
wire sifq_io_deq_ready = _sifq_io_deq_bits_masked | _store_rob_io_deq_valid; // @[Mem.scala:114:20, :338:25, :371:48] |
Generate the Verilog code corresponding to the following Chisel files.
File Nodes.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import org.chipsalliance.diplomacy.nodes._
import freechips.rocketchip.util.{AsyncQueueParams,RationalDirection}
case object TLMonitorBuilder extends Field[TLMonitorArgs => TLMonitorBase](args => new TLMonitor(args))
object TLImp extends NodeImp[TLMasterPortParameters, TLSlavePortParameters, TLEdgeOut, TLEdgeIn, TLBundle]
{
def edgeO(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeOut(pd, pu, p, sourceInfo)
def edgeI(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeIn (pd, pu, p, sourceInfo)
def bundleO(eo: TLEdgeOut) = TLBundle(eo.bundle)
def bundleI(ei: TLEdgeIn) = TLBundle(ei.bundle)
def render(ei: TLEdgeIn) = RenderedEdge(colour = "#000000" /* black */, label = (ei.manager.beatBytes * 8).toString)
override def monitor(bundle: TLBundle, edge: TLEdgeIn): Unit = {
val monitor = Module(edge.params(TLMonitorBuilder)(TLMonitorArgs(edge)))
monitor.io.in := bundle
}
override def mixO(pd: TLMasterPortParameters, node: OutwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLMasterPortParameters =
pd.v1copy(clients = pd.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })
override def mixI(pu: TLSlavePortParameters, node: InwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLSlavePortParameters =
pu.v1copy(managers = pu.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })
}
trait TLFormatNode extends FormatNode[TLEdgeIn, TLEdgeOut]
case class TLClientNode(portParams: Seq[TLMasterPortParameters])(implicit valName: ValName) extends SourceNode(TLImp)(portParams) with TLFormatNode
case class TLManagerNode(portParams: Seq[TLSlavePortParameters])(implicit valName: ValName) extends SinkNode(TLImp)(portParams) with TLFormatNode
case class TLAdapterNode(
clientFn: TLMasterPortParameters => TLMasterPortParameters = { s => s },
managerFn: TLSlavePortParameters => TLSlavePortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLImp)(clientFn, managerFn) with TLFormatNode
case class TLJunctionNode(
clientFn: Seq[TLMasterPortParameters] => Seq[TLMasterPortParameters],
managerFn: Seq[TLSlavePortParameters] => Seq[TLSlavePortParameters])(
implicit valName: ValName)
extends JunctionNode(TLImp)(clientFn, managerFn) with TLFormatNode
case class TLIdentityNode()(implicit valName: ValName) extends IdentityNode(TLImp)() with TLFormatNode
object TLNameNode {
def apply(name: ValName) = TLIdentityNode()(name)
def apply(name: Option[String]): TLIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLIdentityNode = apply(Some(name))
}
case class TLEphemeralNode()(implicit valName: ValName) extends EphemeralNode(TLImp)()
object TLTempNode {
def apply(): TLEphemeralNode = TLEphemeralNode()(ValName("temp"))
}
case class TLNexusNode(
clientFn: Seq[TLMasterPortParameters] => TLMasterPortParameters,
managerFn: Seq[TLSlavePortParameters] => TLSlavePortParameters)(
implicit valName: ValName)
extends NexusNode(TLImp)(clientFn, managerFn) with TLFormatNode
abstract class TLCustomNode(implicit valName: ValName)
extends CustomNode(TLImp) with TLFormatNode
// Asynchronous crossings
trait TLAsyncFormatNode extends FormatNode[TLAsyncEdgeParameters, TLAsyncEdgeParameters]
object TLAsyncImp extends SimpleNodeImp[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncEdgeParameters, TLAsyncBundle]
{
def edge(pd: TLAsyncClientPortParameters, pu: TLAsyncManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLAsyncEdgeParameters(pd, pu, p, sourceInfo)
def bundle(e: TLAsyncEdgeParameters) = new TLAsyncBundle(e.bundle)
def render(e: TLAsyncEdgeParameters) = RenderedEdge(colour = "#ff0000" /* red */, label = e.manager.async.depth.toString)
override def mixO(pd: TLAsyncClientPortParameters, node: OutwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncClientPortParameters =
pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }))
override def mixI(pu: TLAsyncManagerPortParameters, node: InwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncManagerPortParameters =
pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }))
}
case class TLAsyncAdapterNode(
clientFn: TLAsyncClientPortParameters => TLAsyncClientPortParameters = { s => s },
managerFn: TLAsyncManagerPortParameters => TLAsyncManagerPortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLAsyncImp)(clientFn, managerFn) with TLAsyncFormatNode
case class TLAsyncIdentityNode()(implicit valName: ValName) extends IdentityNode(TLAsyncImp)() with TLAsyncFormatNode
object TLAsyncNameNode {
def apply(name: ValName) = TLAsyncIdentityNode()(name)
def apply(name: Option[String]): TLAsyncIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLAsyncIdentityNode = apply(Some(name))
}
case class TLAsyncSourceNode(sync: Option[Int])(implicit valName: ValName)
extends MixedAdapterNode(TLImp, TLAsyncImp)(
dFn = { p => TLAsyncClientPortParameters(p) },
uFn = { p => p.base.v1copy(minLatency = p.base.minLatency + sync.getOrElse(p.async.sync)) }) with FormatNode[TLEdgeIn, TLAsyncEdgeParameters] // discard cycles in other clock domain
case class TLAsyncSinkNode(async: AsyncQueueParams)(implicit valName: ValName)
extends MixedAdapterNode(TLAsyncImp, TLImp)(
dFn = { p => p.base.v1copy(minLatency = p.base.minLatency + async.sync) },
uFn = { p => TLAsyncManagerPortParameters(async, p) }) with FormatNode[TLAsyncEdgeParameters, TLEdgeOut]
// Rationally related crossings
trait TLRationalFormatNode extends FormatNode[TLRationalEdgeParameters, TLRationalEdgeParameters]
object TLRationalImp extends SimpleNodeImp[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalEdgeParameters, TLRationalBundle]
{
def edge(pd: TLRationalClientPortParameters, pu: TLRationalManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLRationalEdgeParameters(pd, pu, p, sourceInfo)
def bundle(e: TLRationalEdgeParameters) = new TLRationalBundle(e.bundle)
def render(e: TLRationalEdgeParameters) = RenderedEdge(colour = "#00ff00" /* green */)
override def mixO(pd: TLRationalClientPortParameters, node: OutwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalClientPortParameters =
pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }))
override def mixI(pu: TLRationalManagerPortParameters, node: InwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalManagerPortParameters =
pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }))
}
case class TLRationalAdapterNode(
clientFn: TLRationalClientPortParameters => TLRationalClientPortParameters = { s => s },
managerFn: TLRationalManagerPortParameters => TLRationalManagerPortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLRationalImp)(clientFn, managerFn) with TLRationalFormatNode
case class TLRationalIdentityNode()(implicit valName: ValName) extends IdentityNode(TLRationalImp)() with TLRationalFormatNode
object TLRationalNameNode {
def apply(name: ValName) = TLRationalIdentityNode()(name)
def apply(name: Option[String]): TLRationalIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLRationalIdentityNode = apply(Some(name))
}
case class TLRationalSourceNode()(implicit valName: ValName)
extends MixedAdapterNode(TLImp, TLRationalImp)(
dFn = { p => TLRationalClientPortParameters(p) },
uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLRationalEdgeParameters] // discard cycles from other clock domain
case class TLRationalSinkNode(direction: RationalDirection)(implicit valName: ValName)
extends MixedAdapterNode(TLRationalImp, TLImp)(
dFn = { p => p.base.v1copy(minLatency = 1) },
uFn = { p => TLRationalManagerPortParameters(direction, p) }) with FormatNode[TLRationalEdgeParameters, TLEdgeOut]
// Credited version of TileLink channels
trait TLCreditedFormatNode extends FormatNode[TLCreditedEdgeParameters, TLCreditedEdgeParameters]
object TLCreditedImp extends SimpleNodeImp[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedEdgeParameters, TLCreditedBundle]
{
def edge(pd: TLCreditedClientPortParameters, pu: TLCreditedManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLCreditedEdgeParameters(pd, pu, p, sourceInfo)
def bundle(e: TLCreditedEdgeParameters) = new TLCreditedBundle(e.bundle)
def render(e: TLCreditedEdgeParameters) = RenderedEdge(colour = "#ffff00" /* yellow */, e.delay.toString)
override def mixO(pd: TLCreditedClientPortParameters, node: OutwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedClientPortParameters =
pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }))
override def mixI(pu: TLCreditedManagerPortParameters, node: InwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedManagerPortParameters =
pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }))
}
case class TLCreditedAdapterNode(
clientFn: TLCreditedClientPortParameters => TLCreditedClientPortParameters = { s => s },
managerFn: TLCreditedManagerPortParameters => TLCreditedManagerPortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLCreditedImp)(clientFn, managerFn) with TLCreditedFormatNode
case class TLCreditedIdentityNode()(implicit valName: ValName) extends IdentityNode(TLCreditedImp)() with TLCreditedFormatNode
object TLCreditedNameNode {
def apply(name: ValName) = TLCreditedIdentityNode()(name)
def apply(name: Option[String]): TLCreditedIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLCreditedIdentityNode = apply(Some(name))
}
case class TLCreditedSourceNode(delay: TLCreditedDelay)(implicit valName: ValName)
extends MixedAdapterNode(TLImp, TLCreditedImp)(
dFn = { p => TLCreditedClientPortParameters(delay, p) },
uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLCreditedEdgeParameters] // discard cycles from other clock domain
case class TLCreditedSinkNode(delay: TLCreditedDelay)(implicit valName: ValName)
extends MixedAdapterNode(TLCreditedImp, TLImp)(
dFn = { p => p.base.v1copy(minLatency = 1) },
uFn = { p => TLCreditedManagerPortParameters(delay, p) }) with FormatNode[TLCreditedEdgeParameters, TLEdgeOut]
File LazyModuleImp.scala:
package org.chipsalliance.diplomacy.lazymodule
import chisel3.{withClockAndReset, Module, RawModule, Reset, _}
import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo}
import firrtl.passes.InlineAnnotation
import org.chipsalliance.cde.config.Parameters
import org.chipsalliance.diplomacy.nodes.Dangle
import scala.collection.immutable.SortedMap
/** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]].
*
* This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy.
*/
sealed trait LazyModuleImpLike extends RawModule {
/** [[LazyModule]] that contains this instance. */
val wrapper: LazyModule
/** IOs that will be automatically "punched" for this instance. */
val auto: AutoBundle
/** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */
protected[diplomacy] val dangles: Seq[Dangle]
// [[wrapper.module]] had better not be accessed while LazyModules are still being built!
require(
LazyModule.scope.isEmpty,
s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}"
)
/** Set module name. Defaults to the containing LazyModule's desiredName. */
override def desiredName: String = wrapper.desiredName
suggestName(wrapper.suggestedName)
/** [[Parameters]] for chisel [[Module]]s. */
implicit val p: Parameters = wrapper.p
/** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and
* submodules.
*/
protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = {
// 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]],
// 2. return [[Dangle]]s from each module.
val childDangles = wrapper.children.reverse.flatMap { c =>
implicit val sourceInfo: SourceInfo = c.info
c.cloneProto.map { cp =>
// If the child is a clone, then recursively set cloneProto of its children as well
def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = {
require(bases.size == clones.size)
(bases.zip(clones)).map { case (l, r) =>
require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}")
l.cloneProto = Some(r)
assignCloneProtos(l.children, r.children)
}
}
assignCloneProtos(c.children, cp.children)
// Clone the child module as a record, and get its [[AutoBundle]]
val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName)
val clonedAuto = clone("auto").asInstanceOf[AutoBundle]
// Get the empty [[Dangle]]'s of the cloned child
val rawDangles = c.cloneDangles()
require(rawDangles.size == clonedAuto.elements.size)
// Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s
val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) }
dangles
}.getOrElse {
// For non-clones, instantiate the child module
val mod = try {
Module(c.module)
} catch {
case e: ChiselException => {
println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}")
throw e
}
}
mod.dangles
}
}
// Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]].
// This will result in a sequence of [[Dangle]] from these [[BaseNode]]s.
val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate())
// Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]]
val allDangles = nodeDangles ++ childDangles
// Group [[allDangles]] by their [[source]].
val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*)
// For each [[source]] set of [[Dangle]]s of size 2, ensure that these
// can be connected as a source-sink pair (have opposite flipped value).
// Make the connection and mark them as [[done]].
val done = Set() ++ pairing.values.filter(_.size == 2).map {
case Seq(a, b) =>
require(a.flipped != b.flipped)
// @todo <> in chisel3 makes directionless connection.
if (a.flipped) {
a.data <> b.data
} else {
b.data <> a.data
}
a.source
case _ => None
}
// Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module.
val forward = allDangles.filter(d => !done(d.source))
// Generate [[AutoBundle]] IO from [[forward]].
val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*))
// Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]]
val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) =>
if (d.flipped) {
d.data <> io
} else {
io <> d.data
}
d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name)
}
// Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]].
wrapper.inModuleBody.reverse.foreach {
_()
}
if (wrapper.shouldBeInlined) {
chisel3.experimental.annotate(new ChiselAnnotation {
def toFirrtl = InlineAnnotation(toNamed)
})
}
// Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]].
(auto, dangles)
}
}
/** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike {
/** Instantiate hardware of this `Module`. */
val (auto, dangles) = instantiate()
}
/** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike {
// These wires are the default clock+reset for all LazyModule children.
// It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the
// [[LazyRawModuleImp]] children.
// Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly.
/** drive clock explicitly. */
val childClock: Clock = Wire(Clock())
/** drive reset explicitly. */
val childReset: Reset = Wire(Reset())
// the default is that these are disabled
childClock := false.B.asClock
childReset := chisel3.DontCare
def provideImplicitClockToLazyChildren: Boolean = false
val (auto, dangles) =
if (provideImplicitClockToLazyChildren) {
withClockAndReset(childClock, childReset) { instantiate() }
} else {
instantiate()
}
}
File Parameters.scala:
/*
* Copyright 2019 SiFive, Inc.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You should have received a copy of LICENSE.Apache2 along with
* this software. If not, you may obtain a copy at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
package sifive.blocks.inclusivecache
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config._
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.tilelink._
import freechips.rocketchip.util._
import freechips.rocketchip.util.property.cover
import scala.math.{min,max}
case class CacheParameters(
level: Int,
ways: Int,
sets: Int,
blockBytes: Int,
beatBytes: Int, // inner
hintsSkipProbe: Boolean)
{
require (ways > 0)
require (sets > 0)
require (blockBytes > 0 && isPow2(blockBytes))
require (beatBytes > 0 && isPow2(beatBytes))
require (blockBytes >= beatBytes)
val blocks = ways * sets
val sizeBytes = blocks * blockBytes
val blockBeats = blockBytes/beatBytes
}
case class InclusiveCachePortParameters(
a: BufferParams,
b: BufferParams,
c: BufferParams,
d: BufferParams,
e: BufferParams)
{
def apply()(implicit p: Parameters, valName: ValName) = LazyModule(new TLBuffer(a, b, c, d, e))
}
object InclusiveCachePortParameters
{
val none = InclusiveCachePortParameters(
a = BufferParams.none,
b = BufferParams.none,
c = BufferParams.none,
d = BufferParams.none,
e = BufferParams.none)
val full = InclusiveCachePortParameters(
a = BufferParams.default,
b = BufferParams.default,
c = BufferParams.default,
d = BufferParams.default,
e = BufferParams.default)
// This removes feed-through paths from C=>A and A=>C
val fullC = InclusiveCachePortParameters(
a = BufferParams.none,
b = BufferParams.none,
c = BufferParams.default,
d = BufferParams.none,
e = BufferParams.none)
val flowAD = InclusiveCachePortParameters(
a = BufferParams.flow,
b = BufferParams.none,
c = BufferParams.none,
d = BufferParams.flow,
e = BufferParams.none)
val flowAE = InclusiveCachePortParameters(
a = BufferParams.flow,
b = BufferParams.none,
c = BufferParams.none,
d = BufferParams.none,
e = BufferParams.flow)
// For innerBuf:
// SinkA: no restrictions, flows into scheduler+putbuffer
// SourceB: no restrictions, flows out of scheduler
// sinkC: no restrictions, flows into scheduler+putbuffer & buffered to bankedStore
// SourceD: no restrictions, flows out of bankedStore/regout
// SinkE: no restrictions, flows into scheduler
//
// ... so while none is possible, you probably want at least flowAC to cut ready
// from the scheduler delay and flowD to ease SourceD back-pressure
// For outerBufer:
// SourceA: must not be pipe, flows out of scheduler
// SinkB: no restrictions, flows into scheduler
// SourceC: pipe is useless, flows out of bankedStore/regout, parameter depth ignored
// SinkD: no restrictions, flows into scheduler & bankedStore
// SourceE: must not be pipe, flows out of scheduler
//
// ... AE take the channel ready into the scheduler, so you need at least flowAE
}
case class InclusiveCacheMicroParameters(
writeBytes: Int, // backing store update granularity
memCycles: Int = 40, // # of L2 clock cycles for a memory round-trip (50ns @ 800MHz)
portFactor: Int = 4, // numSubBanks = (widest TL port * portFactor) / writeBytes
dirReg: Boolean = false,
innerBuf: InclusiveCachePortParameters = InclusiveCachePortParameters.fullC, // or none
outerBuf: InclusiveCachePortParameters = InclusiveCachePortParameters.full) // or flowAE
{
require (writeBytes > 0 && isPow2(writeBytes))
require (memCycles > 0)
require (portFactor >= 2) // for inner RMW and concurrent outer Relase + Grant
}
case class InclusiveCacheControlParameters(
address: BigInt,
beatBytes: Int,
bankedControl: Boolean)
case class InclusiveCacheParameters(
cache: CacheParameters,
micro: InclusiveCacheMicroParameters,
control: Boolean,
inner: TLEdgeIn,
outer: TLEdgeOut)(implicit val p: Parameters)
{
require (cache.ways > 1)
require (cache.sets > 1 && isPow2(cache.sets))
require (micro.writeBytes <= inner.manager.beatBytes)
require (micro.writeBytes <= outer.manager.beatBytes)
require (inner.manager.beatBytes <= cache.blockBytes)
require (outer.manager.beatBytes <= cache.blockBytes)
// Require that all cached address ranges have contiguous blocks
outer.manager.managers.flatMap(_.address).foreach { a =>
require (a.alignment >= cache.blockBytes)
}
// If we are the first level cache, we do not need to support inner-BCE
val firstLevel = !inner.client.clients.exists(_.supports.probe)
// If we are the last level cache, we do not need to support outer-B
val lastLevel = !outer.manager.managers.exists(_.regionType > RegionType.UNCACHED)
require (lastLevel)
// Provision enough resources to achieve full throughput with missing single-beat accesses
val mshrs = InclusiveCacheParameters.all_mshrs(cache, micro)
val secondary = max(mshrs, micro.memCycles - mshrs)
val putLists = micro.memCycles // allow every request to be single beat
val putBeats = max(2*cache.blockBeats, micro.memCycles)
val relLists = 2
val relBeats = relLists*cache.blockBeats
val flatAddresses = AddressSet.unify(outer.manager.managers.flatMap(_.address))
val pickMask = AddressDecoder(flatAddresses.map(Seq(_)), flatAddresses.map(_.mask).reduce(_|_))
def bitOffsets(x: BigInt, offset: Int = 0, tail: List[Int] = List.empty[Int]): List[Int] =
if (x == 0) tail.reverse else bitOffsets(x >> 1, offset + 1, if ((x & 1) == 1) offset :: tail else tail)
val addressMapping = bitOffsets(pickMask)
val addressBits = addressMapping.size
// println(s"addresses: ${flatAddresses} => ${pickMask} => ${addressBits}")
val allClients = inner.client.clients.size
val clientBitsRaw = inner.client.clients.filter(_.supports.probe).size
val clientBits = max(1, clientBitsRaw)
val stateBits = 2
val wayBits = log2Ceil(cache.ways)
val setBits = log2Ceil(cache.sets)
val offsetBits = log2Ceil(cache.blockBytes)
val tagBits = addressBits - setBits - offsetBits
val putBits = log2Ceil(max(putLists, relLists))
require (tagBits > 0)
require (offsetBits > 0)
val innerBeatBits = (offsetBits - log2Ceil(inner.manager.beatBytes)) max 1
val outerBeatBits = (offsetBits - log2Ceil(outer.manager.beatBytes)) max 1
val innerMaskBits = inner.manager.beatBytes / micro.writeBytes
val outerMaskBits = outer.manager.beatBytes / micro.writeBytes
def clientBit(source: UInt): UInt = {
if (clientBitsRaw == 0) {
0.U
} else {
Cat(inner.client.clients.filter(_.supports.probe).map(_.sourceId.contains(source)).reverse)
}
}
def clientSource(bit: UInt): UInt = {
if (clientBitsRaw == 0) {
0.U
} else {
Mux1H(bit, inner.client.clients.filter(_.supports.probe).map(c => c.sourceId.start.U))
}
}
def parseAddress(x: UInt): (UInt, UInt, UInt) = {
val offset = Cat(addressMapping.map(o => x(o,o)).reverse)
val set = offset >> offsetBits
val tag = set >> setBits
(tag(tagBits-1, 0), set(setBits-1, 0), offset(offsetBits-1, 0))
}
def widen(x: UInt, width: Int): UInt = {
val y = x | 0.U(width.W)
assert (y >> width === 0.U)
y(width-1, 0)
}
def expandAddress(tag: UInt, set: UInt, offset: UInt): UInt = {
val base = Cat(widen(tag, tagBits), widen(set, setBits), widen(offset, offsetBits))
val bits = Array.fill(outer.bundle.addressBits) { 0.U(1.W) }
addressMapping.zipWithIndex.foreach { case (a, i) => bits(a) = base(i,i) }
Cat(bits.reverse)
}
def restoreAddress(expanded: UInt): UInt = {
val missingBits = flatAddresses
.map { a => (a.widen(pickMask).base, a.widen(~pickMask)) } // key is the bits to restore on match
.groupBy(_._1)
.view
.mapValues(_.map(_._2))
val muxMask = AddressDecoder(missingBits.values.toList)
val mux = missingBits.toList.map { case (bits, addrs) =>
val widen = addrs.map(_.widen(~muxMask))
val matches = AddressSet
.unify(widen.distinct)
.map(_.contains(expanded))
.reduce(_ || _)
(matches, bits.U)
}
expanded | Mux1H(mux)
}
def dirReg[T <: Data](x: T, en: Bool = true.B): T = {
if (micro.dirReg) RegEnable(x, en) else x
}
def ccover(cond: Bool, label: String, desc: String)(implicit sourceInfo: SourceInfo) =
cover(cond, "CCACHE_L" + cache.level + "_" + label, "MemorySystem;;" + desc)
}
object MetaData
{
val stateBits = 2
def INVALID: UInt = 0.U(stateBits.W) // way is empty
def BRANCH: UInt = 1.U(stateBits.W) // outer slave cache is trunk
def TRUNK: UInt = 2.U(stateBits.W) // unique inner master cache is trunk
def TIP: UInt = 3.U(stateBits.W) // we are trunk, inner masters are branch
// Does a request need trunk?
def needT(opcode: UInt, param: UInt): Bool = {
!opcode(2) ||
(opcode === TLMessages.Hint && param === TLHints.PREFETCH_WRITE) ||
((opcode === TLMessages.AcquireBlock || opcode === TLMessages.AcquirePerm) && param =/= TLPermissions.NtoB)
}
// Does a request prove the client need not be probed?
def skipProbeN(opcode: UInt, hintsSkipProbe: Boolean): Bool = {
// Acquire(toB) and Get => is N, so no probe
// Acquire(*toT) => is N or B, but need T, so no probe
// Hint => could be anything, so probe IS needed, if hintsSkipProbe is enabled, skip probe the same client
// Put* => is N or B, so probe IS needed
opcode === TLMessages.AcquireBlock || opcode === TLMessages.AcquirePerm || opcode === TLMessages.Get || (opcode === TLMessages.Hint && hintsSkipProbe.B)
}
def isToN(param: UInt): Bool = {
param === TLPermissions.TtoN || param === TLPermissions.BtoN || param === TLPermissions.NtoN
}
def isToB(param: UInt): Bool = {
param === TLPermissions.TtoB || param === TLPermissions.BtoB
}
}
object InclusiveCacheParameters
{
val lfsrBits = 10
val L2ControlAddress = 0x2010000
val L2ControlSize = 0x1000
def out_mshrs(cache: CacheParameters, micro: InclusiveCacheMicroParameters): Int = {
// We need 2-3 normal MSHRs to cover the Directory latency
// To fully exploit memory bandwidth-delay-product, we need memCyles/blockBeats MSHRs
max(if (micro.dirReg) 3 else 2, (micro.memCycles + cache.blockBeats - 1) / cache.blockBeats)
}
def all_mshrs(cache: CacheParameters, micro: InclusiveCacheMicroParameters): Int =
// We need a dedicated MSHR for B+C each
2 + out_mshrs(cache, micro)
}
class InclusiveCacheBundle(params: InclusiveCacheParameters) extends Bundle
File InclusiveCache.scala:
/*
* Copyright 2019 SiFive, Inc.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You should have received a copy of LICENSE.Apache2 along with
* this software. If not, you may obtain a copy at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
package sifive.blocks.inclusivecache
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config._
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.subsystem.{SubsystemBankedCoherenceKey}
import freechips.rocketchip.regmapper._
import freechips.rocketchip.tilelink._
class InclusiveCache(
val cache: CacheParameters,
val micro: InclusiveCacheMicroParameters,
control: Option[InclusiveCacheControlParameters] = None
)(implicit p: Parameters)
extends LazyModule
{
val access = TransferSizes(1, cache.blockBytes)
val xfer = TransferSizes(cache.blockBytes, cache.blockBytes)
val atom = TransferSizes(1, cache.beatBytes)
var resourcesOpt: Option[ResourceBindings] = None
val device: SimpleDevice = new SimpleDevice("cache-controller", Seq("sifive,inclusivecache0", "cache")) {
def ofInt(x: Int) = Seq(ResourceInt(BigInt(x)))
override def describe(resources: ResourceBindings): Description = {
resourcesOpt = Some(resources)
val Description(name, mapping) = super.describe(resources)
// Find the outer caches
val outer = node.edges.out
.flatMap(_.manager.managers)
.filter(_.supportsAcquireB)
.flatMap(_.resources.headOption)
.map(_.owner.label)
.distinct
val nextlevel: Option[(String, Seq[ResourceValue])] =
if (outer.isEmpty) {
None
} else {
Some("next-level-cache" -> outer.map(l => ResourceReference(l)).toList)
}
val extra = Map(
"cache-level" -> ofInt(2),
"cache-unified" -> Nil,
"cache-size" -> ofInt(cache.sizeBytes * node.edges.in.size),
"cache-sets" -> ofInt(cache.sets * node.edges.in.size),
"cache-block-size" -> ofInt(cache.blockBytes),
"sifive,mshr-count" -> ofInt(InclusiveCacheParameters.all_mshrs(cache, micro)))
Description(name, mapping ++ extra ++ nextlevel)
}
}
val node: TLAdapterNode = TLAdapterNode(
clientFn = { _ => TLClientPortParameters(Seq(TLClientParameters(
name = s"L${cache.level} InclusiveCache",
sourceId = IdRange(0, InclusiveCacheParameters.out_mshrs(cache, micro)),
supportsProbe = xfer)))
},
managerFn = { m => TLManagerPortParameters(
managers = m.managers.map { m => m.copy(
regionType = if (m.regionType >= RegionType.UNCACHED) RegionType.CACHED else m.regionType,
resources = Resource(device, "caches") +: m.resources,
supportsAcquireB = xfer,
supportsAcquireT = if (m.supportsAcquireT) xfer else TransferSizes.none,
supportsArithmetic = if (m.supportsAcquireT) atom else TransferSizes.none,
supportsLogical = if (m.supportsAcquireT) atom else TransferSizes.none,
supportsGet = access,
supportsPutFull = if (m.supportsAcquireT) access else TransferSizes.none,
supportsPutPartial = if (m.supportsAcquireT) access else TransferSizes.none,
supportsHint = access,
alwaysGrantsT = false,
fifoId = None)
},
beatBytes = cache.beatBytes,
endSinkId = InclusiveCacheParameters.all_mshrs(cache, micro),
minLatency = 2)
})
val ctrls = control.map { c =>
val nCtrls = if (c.bankedControl) p(SubsystemBankedCoherenceKey).nBanks else 1
Seq.tabulate(nCtrls) { i => LazyModule(new InclusiveCacheControl(this,
c.copy(address = c.address + i * InclusiveCacheParameters.L2ControlSize))) }
}.getOrElse(Nil)
lazy val module = new Impl
class Impl extends LazyModuleImp(this) {
// If you have a control port, you must have at least one cache port
require (ctrls.isEmpty || !node.edges.in.isEmpty)
// Extract the client IdRanges; must be the same on all ports!
val clientIds = node.edges.in.headOption.map(_.client.clients.map(_.sourceId).sortBy(_.start))
node.edges.in.foreach { e => require(e.client.clients.map(_.sourceId).sortBy(_.start) == clientIds.get) }
// Use the natural ordering of clients (just like in Directory)
node.edges.in.headOption.foreach { n =>
println(s"L${cache.level} InclusiveCache Client Map:")
n.client.clients.zipWithIndex.foreach { case (c,i) =>
println(s"\t${i} <= ${c.name}")
}
println("")
}
// Create the L2 Banks
val mods = (node.in zip node.out) map { case ((in, edgeIn), (out, edgeOut)) =>
edgeOut.manager.managers.foreach { m =>
require (m.supportsAcquireB.contains(xfer),
s"All managers behind the L2 must support acquireB($xfer) " +
s"but ${m.name} only supports (${m.supportsAcquireB})!")
if (m.supportsAcquireT) require (m.supportsAcquireT.contains(xfer),
s"Any probing managers behind the L2 must support acquireT($xfer) " +
s"but ${m.name} only supports (${m.supportsAcquireT})!")
}
val params = InclusiveCacheParameters(cache, micro, !ctrls.isEmpty, edgeIn, edgeOut)
val scheduler = Module(new InclusiveCacheBankScheduler(params)).suggestName("inclusive_cache_bank_sched")
scheduler.io.in <> in
out <> scheduler.io.out
scheduler.io.ways := DontCare
scheduler.io.divs := DontCare
// Tie down default values in case there is no controller
scheduler.io.req.valid := false.B
scheduler.io.req.bits.address := 0.U
scheduler.io.resp.ready := true.B
// Fix-up the missing addresses. We do this here so that the Scheduler can be
// deduplicated by Firrtl to make hierarchical place-and-route easier.
out.a.bits.address := params.restoreAddress(scheduler.io.out.a.bits.address)
in .b.bits.address := params.restoreAddress(scheduler.io.in .b.bits.address)
out.c.bits.address := params.restoreAddress(scheduler.io.out.c.bits.address)
scheduler
}
ctrls.foreach { ctrl =>
ctrl.module.io.flush_req.ready := false.B
ctrl.module.io.flush_resp := false.B
ctrl.module.io.flush_match := false.B
}
mods.zip(node.edges.in).zipWithIndex.foreach { case ((sched, edgeIn), i) =>
val ctrl = if (ctrls.size > 1) Some(ctrls(i)) else ctrls.headOption
ctrl.foreach { ctrl => {
val contained = edgeIn.manager.managers.flatMap(_.address)
.map(_.contains(ctrl.module.io.flush_req.bits)).reduce(_||_)
when (contained) { ctrl.module.io.flush_match := true.B }
sched.io.req.valid := contained && ctrl.module.io.flush_req.valid
sched.io.req.bits.address := ctrl.module.io.flush_req.bits
when (contained && sched.io.req.ready) { ctrl.module.io.flush_req.ready := true.B }
when (sched.io.resp.valid) { ctrl.module.io.flush_resp := true.B }
sched.io.resp.ready := true.B
}}
}
def json = s"""{"banks":[${mods.map(_.json).mkString(",")}]}"""
}
}
| module InclusiveCache( // @[InclusiveCache.scala:108:9]
input clock, // @[InclusiveCache.scala:108:9]
input reset, // @[InclusiveCache.scala:108:9]
output auto_ctrls_ctrl_in_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_ctrls_ctrl_in_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_ctrls_ctrl_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_ctrls_ctrl_in_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_ctrls_ctrl_in_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [11:0] auto_ctrls_ctrl_in_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [25:0] auto_ctrls_ctrl_in_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_ctrls_ctrl_in_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_ctrls_ctrl_in_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_ctrls_ctrl_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_ctrls_ctrl_in_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_ctrls_ctrl_in_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_ctrls_ctrl_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_ctrls_ctrl_in_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [11:0] auto_ctrls_ctrl_in_d_bits_source, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_ctrls_ctrl_in_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_in_3_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_in_3_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_3_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_3_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_3_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [6:0] auto_in_3_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_in_3_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [15:0] auto_in_3_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [127:0] auto_in_3_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_in_3_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_in_3_b_ready, // @[LazyModuleImp.scala:107:25]
output auto_in_3_b_valid, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_in_3_b_bits_param, // @[LazyModuleImp.scala:107:25]
output [6:0] auto_in_3_b_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_in_3_b_bits_address, // @[LazyModuleImp.scala:107:25]
output auto_in_3_c_ready, // @[LazyModuleImp.scala:107:25]
input auto_in_3_c_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_3_c_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_3_c_bits_param, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_3_c_bits_size, // @[LazyModuleImp.scala:107:25]
input [6:0] auto_in_3_c_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_in_3_c_bits_address, // @[LazyModuleImp.scala:107:25]
input [127:0] auto_in_3_c_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_in_3_c_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_in_3_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_in_3_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_in_3_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_in_3_d_bits_param, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_in_3_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [6:0] auto_in_3_d_bits_source, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_in_3_d_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_in_3_d_bits_denied, // @[LazyModuleImp.scala:107:25]
output [127:0] auto_in_3_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_in_3_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_in_3_e_valid, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_in_3_e_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_in_2_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_in_2_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_2_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_2_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_2_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [6:0] auto_in_2_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_in_2_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [15:0] auto_in_2_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [127:0] auto_in_2_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_in_2_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_in_2_b_ready, // @[LazyModuleImp.scala:107:25]
output auto_in_2_b_valid, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_in_2_b_bits_param, // @[LazyModuleImp.scala:107:25]
output [6:0] auto_in_2_b_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_in_2_b_bits_address, // @[LazyModuleImp.scala:107:25]
output auto_in_2_c_ready, // @[LazyModuleImp.scala:107:25]
input auto_in_2_c_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_2_c_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_2_c_bits_param, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_2_c_bits_size, // @[LazyModuleImp.scala:107:25]
input [6:0] auto_in_2_c_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_in_2_c_bits_address, // @[LazyModuleImp.scala:107:25]
input [127:0] auto_in_2_c_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_in_2_c_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_in_2_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_in_2_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_in_2_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_in_2_d_bits_param, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_in_2_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [6:0] auto_in_2_d_bits_source, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_in_2_d_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_in_2_d_bits_denied, // @[LazyModuleImp.scala:107:25]
output [127:0] auto_in_2_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_in_2_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_in_2_e_valid, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_in_2_e_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_in_1_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_in_1_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_1_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_1_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_1_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [6:0] auto_in_1_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_in_1_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [15:0] auto_in_1_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [127:0] auto_in_1_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_in_1_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_in_1_b_ready, // @[LazyModuleImp.scala:107:25]
output auto_in_1_b_valid, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_in_1_b_bits_param, // @[LazyModuleImp.scala:107:25]
output [6:0] auto_in_1_b_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_in_1_b_bits_address, // @[LazyModuleImp.scala:107:25]
output auto_in_1_c_ready, // @[LazyModuleImp.scala:107:25]
input auto_in_1_c_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_1_c_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_1_c_bits_param, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_1_c_bits_size, // @[LazyModuleImp.scala:107:25]
input [6:0] auto_in_1_c_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_in_1_c_bits_address, // @[LazyModuleImp.scala:107:25]
input [127:0] auto_in_1_c_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_in_1_c_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_in_1_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_in_1_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_in_1_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_in_1_d_bits_param, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_in_1_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [6:0] auto_in_1_d_bits_source, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_in_1_d_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_in_1_d_bits_denied, // @[LazyModuleImp.scala:107:25]
output [127:0] auto_in_1_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_in_1_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_in_1_e_valid, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_in_1_e_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_in_0_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_in_0_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_0_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_0_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_0_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [6:0] auto_in_0_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_in_0_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [15:0] auto_in_0_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [127:0] auto_in_0_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_in_0_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_in_0_b_ready, // @[LazyModuleImp.scala:107:25]
output auto_in_0_b_valid, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_in_0_b_bits_param, // @[LazyModuleImp.scala:107:25]
output [6:0] auto_in_0_b_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_in_0_b_bits_address, // @[LazyModuleImp.scala:107:25]
output auto_in_0_c_ready, // @[LazyModuleImp.scala:107:25]
input auto_in_0_c_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_0_c_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_0_c_bits_param, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_0_c_bits_size, // @[LazyModuleImp.scala:107:25]
input [6:0] auto_in_0_c_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_in_0_c_bits_address, // @[LazyModuleImp.scala:107:25]
input [127:0] auto_in_0_c_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_in_0_c_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_in_0_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_in_0_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_in_0_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_in_0_d_bits_param, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_in_0_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [6:0] auto_in_0_d_bits_source, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_in_0_d_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_in_0_d_bits_denied, // @[LazyModuleImp.scala:107:25]
output [127:0] auto_in_0_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_in_0_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_in_0_e_valid, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_in_0_e_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_out_3_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_out_3_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_3_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_3_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_3_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_out_3_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_out_3_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_out_3_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_out_3_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_out_3_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_out_3_c_ready, // @[LazyModuleImp.scala:107:25]
output auto_out_3_c_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_3_c_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_3_c_bits_param, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_3_c_bits_size, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_out_3_c_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_out_3_c_bits_address, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_out_3_c_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_out_3_c_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_out_3_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_out_3_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_3_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_out_3_d_bits_param, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_3_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_out_3_d_bits_source, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_3_d_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_out_3_d_bits_denied, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_out_3_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_out_3_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_out_3_e_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_3_e_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_out_2_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_out_2_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_2_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_2_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_2_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_out_2_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_out_2_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_out_2_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_out_2_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_out_2_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_out_2_c_ready, // @[LazyModuleImp.scala:107:25]
output auto_out_2_c_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_2_c_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_2_c_bits_param, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_2_c_bits_size, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_out_2_c_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_out_2_c_bits_address, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_out_2_c_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_out_2_c_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_out_2_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_out_2_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_2_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_out_2_d_bits_param, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_2_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_out_2_d_bits_source, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_2_d_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_out_2_d_bits_denied, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_out_2_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_out_2_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_out_2_e_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_2_e_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_out_1_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_out_1_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_1_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_1_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_1_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_out_1_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_out_1_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_out_1_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_out_1_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_out_1_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_out_1_c_ready, // @[LazyModuleImp.scala:107:25]
output auto_out_1_c_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_1_c_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_1_c_bits_param, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_1_c_bits_size, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_out_1_c_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_out_1_c_bits_address, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_out_1_c_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_out_1_c_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_out_1_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_out_1_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_1_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_out_1_d_bits_param, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_1_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_out_1_d_bits_source, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_1_d_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_out_1_d_bits_denied, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_out_1_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_out_1_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_out_1_e_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_1_e_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_out_0_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_out_0_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_0_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_0_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_0_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_out_0_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_out_0_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_out_0_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_out_0_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_out_0_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_out_0_c_ready, // @[LazyModuleImp.scala:107:25]
output auto_out_0_c_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_0_c_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_0_c_bits_param, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_0_c_bits_size, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_out_0_c_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_out_0_c_bits_address, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_out_0_c_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_out_0_c_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_out_0_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_out_0_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_0_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_out_0_d_bits_param, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_0_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_out_0_d_bits_source, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_0_d_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_out_0_d_bits_denied, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_out_0_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_out_0_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_out_0_e_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_0_e_bits_sink // @[LazyModuleImp.scala:107:25]
);
wire _inclusive_cache_bank_sched_3_io_in_a_ready; // @[InclusiveCache.scala:137:29]
wire _inclusive_cache_bank_sched_3_io_in_b_valid; // @[InclusiveCache.scala:137:29]
wire [1:0] _inclusive_cache_bank_sched_3_io_in_b_bits_param; // @[InclusiveCache.scala:137:29]
wire [6:0] _inclusive_cache_bank_sched_3_io_in_b_bits_source; // @[InclusiveCache.scala:137:29]
wire [31:0] _inclusive_cache_bank_sched_3_io_in_b_bits_address; // @[InclusiveCache.scala:137:29]
wire _inclusive_cache_bank_sched_3_io_in_c_ready; // @[InclusiveCache.scala:137:29]
wire _inclusive_cache_bank_sched_3_io_in_d_valid; // @[InclusiveCache.scala:137:29]
wire [2:0] _inclusive_cache_bank_sched_3_io_in_d_bits_opcode; // @[InclusiveCache.scala:137:29]
wire [1:0] _inclusive_cache_bank_sched_3_io_in_d_bits_param; // @[InclusiveCache.scala:137:29]
wire [2:0] _inclusive_cache_bank_sched_3_io_in_d_bits_size; // @[InclusiveCache.scala:137:29]
wire [6:0] _inclusive_cache_bank_sched_3_io_in_d_bits_source; // @[InclusiveCache.scala:137:29]
wire [3:0] _inclusive_cache_bank_sched_3_io_in_d_bits_sink; // @[InclusiveCache.scala:137:29]
wire _inclusive_cache_bank_sched_3_io_in_d_bits_denied; // @[InclusiveCache.scala:137:29]
wire _inclusive_cache_bank_sched_3_io_in_d_bits_corrupt; // @[InclusiveCache.scala:137:29]
wire [31:0] _inclusive_cache_bank_sched_3_io_out_a_bits_address; // @[InclusiveCache.scala:137:29]
wire [31:0] _inclusive_cache_bank_sched_3_io_out_c_bits_address; // @[InclusiveCache.scala:137:29]
wire _inclusive_cache_bank_sched_3_io_req_ready; // @[InclusiveCache.scala:137:29]
wire _inclusive_cache_bank_sched_3_io_resp_valid; // @[InclusiveCache.scala:137:29]
wire _inclusive_cache_bank_sched_2_io_in_a_ready; // @[InclusiveCache.scala:137:29]
wire _inclusive_cache_bank_sched_2_io_in_b_valid; // @[InclusiveCache.scala:137:29]
wire [1:0] _inclusive_cache_bank_sched_2_io_in_b_bits_param; // @[InclusiveCache.scala:137:29]
wire [6:0] _inclusive_cache_bank_sched_2_io_in_b_bits_source; // @[InclusiveCache.scala:137:29]
wire [31:0] _inclusive_cache_bank_sched_2_io_in_b_bits_address; // @[InclusiveCache.scala:137:29]
wire _inclusive_cache_bank_sched_2_io_in_c_ready; // @[InclusiveCache.scala:137:29]
wire _inclusive_cache_bank_sched_2_io_in_d_valid; // @[InclusiveCache.scala:137:29]
wire [2:0] _inclusive_cache_bank_sched_2_io_in_d_bits_opcode; // @[InclusiveCache.scala:137:29]
wire [1:0] _inclusive_cache_bank_sched_2_io_in_d_bits_param; // @[InclusiveCache.scala:137:29]
wire [2:0] _inclusive_cache_bank_sched_2_io_in_d_bits_size; // @[InclusiveCache.scala:137:29]
wire [6:0] _inclusive_cache_bank_sched_2_io_in_d_bits_source; // @[InclusiveCache.scala:137:29]
wire [3:0] _inclusive_cache_bank_sched_2_io_in_d_bits_sink; // @[InclusiveCache.scala:137:29]
wire _inclusive_cache_bank_sched_2_io_in_d_bits_denied; // @[InclusiveCache.scala:137:29]
wire _inclusive_cache_bank_sched_2_io_in_d_bits_corrupt; // @[InclusiveCache.scala:137:29]
wire [31:0] _inclusive_cache_bank_sched_2_io_out_a_bits_address; // @[InclusiveCache.scala:137:29]
wire [31:0] _inclusive_cache_bank_sched_2_io_out_c_bits_address; // @[InclusiveCache.scala:137:29]
wire _inclusive_cache_bank_sched_2_io_req_ready; // @[InclusiveCache.scala:137:29]
wire _inclusive_cache_bank_sched_2_io_resp_valid; // @[InclusiveCache.scala:137:29]
wire _inclusive_cache_bank_sched_1_io_in_a_ready; // @[InclusiveCache.scala:137:29]
wire _inclusive_cache_bank_sched_1_io_in_b_valid; // @[InclusiveCache.scala:137:29]
wire [1:0] _inclusive_cache_bank_sched_1_io_in_b_bits_param; // @[InclusiveCache.scala:137:29]
wire [6:0] _inclusive_cache_bank_sched_1_io_in_b_bits_source; // @[InclusiveCache.scala:137:29]
wire [31:0] _inclusive_cache_bank_sched_1_io_in_b_bits_address; // @[InclusiveCache.scala:137:29]
wire _inclusive_cache_bank_sched_1_io_in_c_ready; // @[InclusiveCache.scala:137:29]
wire _inclusive_cache_bank_sched_1_io_in_d_valid; // @[InclusiveCache.scala:137:29]
wire [2:0] _inclusive_cache_bank_sched_1_io_in_d_bits_opcode; // @[InclusiveCache.scala:137:29]
wire [1:0] _inclusive_cache_bank_sched_1_io_in_d_bits_param; // @[InclusiveCache.scala:137:29]
wire [2:0] _inclusive_cache_bank_sched_1_io_in_d_bits_size; // @[InclusiveCache.scala:137:29]
wire [6:0] _inclusive_cache_bank_sched_1_io_in_d_bits_source; // @[InclusiveCache.scala:137:29]
wire [3:0] _inclusive_cache_bank_sched_1_io_in_d_bits_sink; // @[InclusiveCache.scala:137:29]
wire _inclusive_cache_bank_sched_1_io_in_d_bits_denied; // @[InclusiveCache.scala:137:29]
wire _inclusive_cache_bank_sched_1_io_in_d_bits_corrupt; // @[InclusiveCache.scala:137:29]
wire [31:0] _inclusive_cache_bank_sched_1_io_out_a_bits_address; // @[InclusiveCache.scala:137:29]
wire [31:0] _inclusive_cache_bank_sched_1_io_out_c_bits_address; // @[InclusiveCache.scala:137:29]
wire _inclusive_cache_bank_sched_1_io_req_ready; // @[InclusiveCache.scala:137:29]
wire _inclusive_cache_bank_sched_1_io_resp_valid; // @[InclusiveCache.scala:137:29]
wire _inclusive_cache_bank_sched_io_in_a_ready; // @[InclusiveCache.scala:137:29]
wire _inclusive_cache_bank_sched_io_in_b_valid; // @[InclusiveCache.scala:137:29]
wire [1:0] _inclusive_cache_bank_sched_io_in_b_bits_param; // @[InclusiveCache.scala:137:29]
wire [6:0] _inclusive_cache_bank_sched_io_in_b_bits_source; // @[InclusiveCache.scala:137:29]
wire [31:0] _inclusive_cache_bank_sched_io_in_b_bits_address; // @[InclusiveCache.scala:137:29]
wire _inclusive_cache_bank_sched_io_in_c_ready; // @[InclusiveCache.scala:137:29]
wire _inclusive_cache_bank_sched_io_in_d_valid; // @[InclusiveCache.scala:137:29]
wire [2:0] _inclusive_cache_bank_sched_io_in_d_bits_opcode; // @[InclusiveCache.scala:137:29]
wire [1:0] _inclusive_cache_bank_sched_io_in_d_bits_param; // @[InclusiveCache.scala:137:29]
wire [2:0] _inclusive_cache_bank_sched_io_in_d_bits_size; // @[InclusiveCache.scala:137:29]
wire [6:0] _inclusive_cache_bank_sched_io_in_d_bits_source; // @[InclusiveCache.scala:137:29]
wire [3:0] _inclusive_cache_bank_sched_io_in_d_bits_sink; // @[InclusiveCache.scala:137:29]
wire _inclusive_cache_bank_sched_io_in_d_bits_denied; // @[InclusiveCache.scala:137:29]
wire _inclusive_cache_bank_sched_io_in_d_bits_corrupt; // @[InclusiveCache.scala:137:29]
wire _inclusive_cache_bank_sched_io_req_ready; // @[InclusiveCache.scala:137:29]
wire _inclusive_cache_bank_sched_io_resp_valid; // @[InclusiveCache.scala:137:29]
wire _ctrls_io_flush_req_valid; // @[InclusiveCache.scala:103:43]
wire [63:0] _ctrls_io_flush_req_bits; // @[InclusiveCache.scala:103:43]
wire [31:0] nodeIn_1_b_bits_address = {_inclusive_cache_bank_sched_1_io_in_b_bits_address[31:7], _inclusive_cache_bank_sched_1_io_in_b_bits_address[6:0] | 7'h40}; // @[Parameters.scala:248:14]
wire [31:0] nodeIn_2_b_bits_address = {_inclusive_cache_bank_sched_2_io_in_b_bits_address[31:8], _inclusive_cache_bank_sched_2_io_in_b_bits_address[7:0] | 8'h80}; // @[Parameters.scala:248:14]
wire [31:0] nodeIn_3_b_bits_address = {_inclusive_cache_bank_sched_3_io_in_b_bits_address[31:8], _inclusive_cache_bank_sched_3_io_in_b_bits_address[7:0] | 8'hC0}; // @[Parameters.scala:248:14]
wire contained = {_ctrls_io_flush_req_bits[63:32], _ctrls_io_flush_req_bits[31:28] ^ 4'h8, _ctrls_io_flush_req_bits[7:6]} == 38'h0 | {_ctrls_io_flush_req_bits[63:28], _ctrls_io_flush_req_bits[27:16] ^ 12'h800, _ctrls_io_flush_req_bits[7:6]} == 50'h0; // @[Parameters.scala:137:{31,41,46,59}]
wire [25:0] _GEN = _ctrls_io_flush_req_bits[31:6] ^ 26'h2000001; // @[Parameters.scala:137:31]
wire [21:0] _GEN_0 = _ctrls_io_flush_req_bits[27:6] ^ 22'h200001; // @[Parameters.scala:137:31]
wire contained_1 = {_ctrls_io_flush_req_bits[63:32], _GEN[25:22], _GEN[1:0]} == 38'h0 | {_ctrls_io_flush_req_bits[63:28], _GEN_0[21:10], _GEN_0[1:0]} == 50'h0; // @[Parameters.scala:137:{31,41,46,59}]
wire [25:0] _GEN_1 = _ctrls_io_flush_req_bits[31:6] ^ 26'h2000002; // @[Parameters.scala:137:31]
wire [21:0] _GEN_2 = _ctrls_io_flush_req_bits[27:6] ^ 22'h200002; // @[Parameters.scala:137:31]
wire contained_2 = {_ctrls_io_flush_req_bits[63:32], _GEN_1[25:22], _GEN_1[1:0]} == 38'h0 | {_ctrls_io_flush_req_bits[63:28], _GEN_2[21:10], _GEN_2[1:0]} == 50'h0; // @[Parameters.scala:137:{31,41,46,59}]
wire [25:0] _GEN_3 = _ctrls_io_flush_req_bits[31:6] ^ 26'h2000003; // @[Parameters.scala:137:31]
wire [21:0] _GEN_4 = _ctrls_io_flush_req_bits[27:6] ^ 22'h200003; // @[Parameters.scala:137:31]
wire contained_3 = {_ctrls_io_flush_req_bits[63:32], _GEN_3[25:22], _GEN_3[1:0]} == 38'h0 | {_ctrls_io_flush_req_bits[63:28], _GEN_4[21:10], _GEN_4[1:0]} == 50'h0; // @[Parameters.scala:137:{31,41,46,59}]
InclusiveCacheControl ctrls ( // @[InclusiveCache.scala:103:43]
.clock (clock),
.reset (reset),
.auto_ctrl_in_a_ready (auto_ctrls_ctrl_in_a_ready),
.auto_ctrl_in_a_valid (auto_ctrls_ctrl_in_a_valid),
.auto_ctrl_in_a_bits_opcode (auto_ctrls_ctrl_in_a_bits_opcode),
.auto_ctrl_in_a_bits_param (auto_ctrls_ctrl_in_a_bits_param),
.auto_ctrl_in_a_bits_size (auto_ctrls_ctrl_in_a_bits_size),
.auto_ctrl_in_a_bits_source (auto_ctrls_ctrl_in_a_bits_source),
.auto_ctrl_in_a_bits_address (auto_ctrls_ctrl_in_a_bits_address),
.auto_ctrl_in_a_bits_mask (auto_ctrls_ctrl_in_a_bits_mask),
.auto_ctrl_in_a_bits_data (auto_ctrls_ctrl_in_a_bits_data),
.auto_ctrl_in_a_bits_corrupt (auto_ctrls_ctrl_in_a_bits_corrupt),
.auto_ctrl_in_d_ready (auto_ctrls_ctrl_in_d_ready),
.auto_ctrl_in_d_valid (auto_ctrls_ctrl_in_d_valid),
.auto_ctrl_in_d_bits_opcode (auto_ctrls_ctrl_in_d_bits_opcode),
.auto_ctrl_in_d_bits_size (auto_ctrls_ctrl_in_d_bits_size),
.auto_ctrl_in_d_bits_source (auto_ctrls_ctrl_in_d_bits_source),
.auto_ctrl_in_d_bits_data (auto_ctrls_ctrl_in_d_bits_data),
.io_flush_match (contained_3 | contained_2 | contained_1 | contained), // @[InclusiveCache.scala:169:67, :170:{26,55}]
.io_flush_req_ready (contained_3 & _inclusive_cache_bank_sched_3_io_req_ready | contained_2 & _inclusive_cache_bank_sched_2_io_req_ready | contained_1 & _inclusive_cache_bank_sched_1_io_req_ready | contained & _inclusive_cache_bank_sched_io_req_ready), // @[InclusiveCache.scala:137:29, :169:67, :174:{25,48,81}]
.io_flush_req_valid (_ctrls_io_flush_req_valid),
.io_flush_req_bits (_ctrls_io_flush_req_bits),
.io_flush_resp (_inclusive_cache_bank_sched_3_io_resp_valid | _inclusive_cache_bank_sched_2_io_resp_valid | _inclusive_cache_bank_sched_1_io_resp_valid | _inclusive_cache_bank_sched_io_resp_valid) // @[InclusiveCache.scala:137:29, :176:{36,64}]
); // @[InclusiveCache.scala:103:43]
TLMonitor_50 monitor ( // @[Nodes.scala:27:25]
.clock (clock),
.reset (reset),
.io_in_a_ready (_inclusive_cache_bank_sched_io_in_a_ready), // @[InclusiveCache.scala:137:29]
.io_in_a_valid (auto_in_0_a_valid),
.io_in_a_bits_opcode (auto_in_0_a_bits_opcode),
.io_in_a_bits_param (auto_in_0_a_bits_param),
.io_in_a_bits_size (auto_in_0_a_bits_size),
.io_in_a_bits_source (auto_in_0_a_bits_source),
.io_in_a_bits_address (auto_in_0_a_bits_address),
.io_in_a_bits_mask (auto_in_0_a_bits_mask),
.io_in_a_bits_corrupt (auto_in_0_a_bits_corrupt),
.io_in_b_ready (auto_in_0_b_ready),
.io_in_b_valid (_inclusive_cache_bank_sched_io_in_b_valid), // @[InclusiveCache.scala:137:29]
.io_in_b_bits_param (_inclusive_cache_bank_sched_io_in_b_bits_param), // @[InclusiveCache.scala:137:29]
.io_in_b_bits_source (_inclusive_cache_bank_sched_io_in_b_bits_source), // @[InclusiveCache.scala:137:29]
.io_in_b_bits_address (_inclusive_cache_bank_sched_io_in_b_bits_address), // @[InclusiveCache.scala:137:29]
.io_in_c_ready (_inclusive_cache_bank_sched_io_in_c_ready), // @[InclusiveCache.scala:137:29]
.io_in_c_valid (auto_in_0_c_valid),
.io_in_c_bits_opcode (auto_in_0_c_bits_opcode),
.io_in_c_bits_param (auto_in_0_c_bits_param),
.io_in_c_bits_size (auto_in_0_c_bits_size),
.io_in_c_bits_source (auto_in_0_c_bits_source),
.io_in_c_bits_address (auto_in_0_c_bits_address),
.io_in_c_bits_corrupt (auto_in_0_c_bits_corrupt),
.io_in_d_ready (auto_in_0_d_ready),
.io_in_d_valid (_inclusive_cache_bank_sched_io_in_d_valid), // @[InclusiveCache.scala:137:29]
.io_in_d_bits_opcode (_inclusive_cache_bank_sched_io_in_d_bits_opcode), // @[InclusiveCache.scala:137:29]
.io_in_d_bits_param (_inclusive_cache_bank_sched_io_in_d_bits_param), // @[InclusiveCache.scala:137:29]
.io_in_d_bits_size (_inclusive_cache_bank_sched_io_in_d_bits_size), // @[InclusiveCache.scala:137:29]
.io_in_d_bits_source (_inclusive_cache_bank_sched_io_in_d_bits_source), // @[InclusiveCache.scala:137:29]
.io_in_d_bits_sink (_inclusive_cache_bank_sched_io_in_d_bits_sink), // @[InclusiveCache.scala:137:29]
.io_in_d_bits_denied (_inclusive_cache_bank_sched_io_in_d_bits_denied), // @[InclusiveCache.scala:137:29]
.io_in_d_bits_corrupt (_inclusive_cache_bank_sched_io_in_d_bits_corrupt), // @[InclusiveCache.scala:137:29]
.io_in_e_valid (auto_in_0_e_valid),
.io_in_e_bits_sink (auto_in_0_e_bits_sink)
); // @[Nodes.scala:27:25]
TLMonitor_51 monitor_1 ( // @[Nodes.scala:27:25]
.clock (clock),
.reset (reset),
.io_in_a_ready (_inclusive_cache_bank_sched_1_io_in_a_ready), // @[InclusiveCache.scala:137:29]
.io_in_a_valid (auto_in_1_a_valid),
.io_in_a_bits_opcode (auto_in_1_a_bits_opcode),
.io_in_a_bits_param (auto_in_1_a_bits_param),
.io_in_a_bits_size (auto_in_1_a_bits_size),
.io_in_a_bits_source (auto_in_1_a_bits_source),
.io_in_a_bits_address (auto_in_1_a_bits_address),
.io_in_a_bits_mask (auto_in_1_a_bits_mask),
.io_in_a_bits_corrupt (auto_in_1_a_bits_corrupt),
.io_in_b_ready (auto_in_1_b_ready),
.io_in_b_valid (_inclusive_cache_bank_sched_1_io_in_b_valid), // @[InclusiveCache.scala:137:29]
.io_in_b_bits_param (_inclusive_cache_bank_sched_1_io_in_b_bits_param), // @[InclusiveCache.scala:137:29]
.io_in_b_bits_source (_inclusive_cache_bank_sched_1_io_in_b_bits_source), // @[InclusiveCache.scala:137:29]
.io_in_b_bits_address (nodeIn_1_b_bits_address), // @[Parameters.scala:248:14]
.io_in_c_ready (_inclusive_cache_bank_sched_1_io_in_c_ready), // @[InclusiveCache.scala:137:29]
.io_in_c_valid (auto_in_1_c_valid),
.io_in_c_bits_opcode (auto_in_1_c_bits_opcode),
.io_in_c_bits_param (auto_in_1_c_bits_param),
.io_in_c_bits_size (auto_in_1_c_bits_size),
.io_in_c_bits_source (auto_in_1_c_bits_source),
.io_in_c_bits_address (auto_in_1_c_bits_address),
.io_in_c_bits_corrupt (auto_in_1_c_bits_corrupt),
.io_in_d_ready (auto_in_1_d_ready),
.io_in_d_valid (_inclusive_cache_bank_sched_1_io_in_d_valid), // @[InclusiveCache.scala:137:29]
.io_in_d_bits_opcode (_inclusive_cache_bank_sched_1_io_in_d_bits_opcode), // @[InclusiveCache.scala:137:29]
.io_in_d_bits_param (_inclusive_cache_bank_sched_1_io_in_d_bits_param), // @[InclusiveCache.scala:137:29]
.io_in_d_bits_size (_inclusive_cache_bank_sched_1_io_in_d_bits_size), // @[InclusiveCache.scala:137:29]
.io_in_d_bits_source (_inclusive_cache_bank_sched_1_io_in_d_bits_source), // @[InclusiveCache.scala:137:29]
.io_in_d_bits_sink (_inclusive_cache_bank_sched_1_io_in_d_bits_sink), // @[InclusiveCache.scala:137:29]
.io_in_d_bits_denied (_inclusive_cache_bank_sched_1_io_in_d_bits_denied), // @[InclusiveCache.scala:137:29]
.io_in_d_bits_corrupt (_inclusive_cache_bank_sched_1_io_in_d_bits_corrupt), // @[InclusiveCache.scala:137:29]
.io_in_e_valid (auto_in_1_e_valid),
.io_in_e_bits_sink (auto_in_1_e_bits_sink)
); // @[Nodes.scala:27:25]
TLMonitor_52 monitor_2 ( // @[Nodes.scala:27:25]
.clock (clock),
.reset (reset),
.io_in_a_ready (_inclusive_cache_bank_sched_2_io_in_a_ready), // @[InclusiveCache.scala:137:29]
.io_in_a_valid (auto_in_2_a_valid),
.io_in_a_bits_opcode (auto_in_2_a_bits_opcode),
.io_in_a_bits_param (auto_in_2_a_bits_param),
.io_in_a_bits_size (auto_in_2_a_bits_size),
.io_in_a_bits_source (auto_in_2_a_bits_source),
.io_in_a_bits_address (auto_in_2_a_bits_address),
.io_in_a_bits_mask (auto_in_2_a_bits_mask),
.io_in_a_bits_corrupt (auto_in_2_a_bits_corrupt),
.io_in_b_ready (auto_in_2_b_ready),
.io_in_b_valid (_inclusive_cache_bank_sched_2_io_in_b_valid), // @[InclusiveCache.scala:137:29]
.io_in_b_bits_param (_inclusive_cache_bank_sched_2_io_in_b_bits_param), // @[InclusiveCache.scala:137:29]
.io_in_b_bits_source (_inclusive_cache_bank_sched_2_io_in_b_bits_source), // @[InclusiveCache.scala:137:29]
.io_in_b_bits_address (nodeIn_2_b_bits_address), // @[Parameters.scala:248:14]
.io_in_c_ready (_inclusive_cache_bank_sched_2_io_in_c_ready), // @[InclusiveCache.scala:137:29]
.io_in_c_valid (auto_in_2_c_valid),
.io_in_c_bits_opcode (auto_in_2_c_bits_opcode),
.io_in_c_bits_param (auto_in_2_c_bits_param),
.io_in_c_bits_size (auto_in_2_c_bits_size),
.io_in_c_bits_source (auto_in_2_c_bits_source),
.io_in_c_bits_address (auto_in_2_c_bits_address),
.io_in_c_bits_corrupt (auto_in_2_c_bits_corrupt),
.io_in_d_ready (auto_in_2_d_ready),
.io_in_d_valid (_inclusive_cache_bank_sched_2_io_in_d_valid), // @[InclusiveCache.scala:137:29]
.io_in_d_bits_opcode (_inclusive_cache_bank_sched_2_io_in_d_bits_opcode), // @[InclusiveCache.scala:137:29]
.io_in_d_bits_param (_inclusive_cache_bank_sched_2_io_in_d_bits_param), // @[InclusiveCache.scala:137:29]
.io_in_d_bits_size (_inclusive_cache_bank_sched_2_io_in_d_bits_size), // @[InclusiveCache.scala:137:29]
.io_in_d_bits_source (_inclusive_cache_bank_sched_2_io_in_d_bits_source), // @[InclusiveCache.scala:137:29]
.io_in_d_bits_sink (_inclusive_cache_bank_sched_2_io_in_d_bits_sink), // @[InclusiveCache.scala:137:29]
.io_in_d_bits_denied (_inclusive_cache_bank_sched_2_io_in_d_bits_denied), // @[InclusiveCache.scala:137:29]
.io_in_d_bits_corrupt (_inclusive_cache_bank_sched_2_io_in_d_bits_corrupt), // @[InclusiveCache.scala:137:29]
.io_in_e_valid (auto_in_2_e_valid),
.io_in_e_bits_sink (auto_in_2_e_bits_sink)
); // @[Nodes.scala:27:25]
TLMonitor_53 monitor_3 ( // @[Nodes.scala:27:25]
.clock (clock),
.reset (reset),
.io_in_a_ready (_inclusive_cache_bank_sched_3_io_in_a_ready), // @[InclusiveCache.scala:137:29]
.io_in_a_valid (auto_in_3_a_valid),
.io_in_a_bits_opcode (auto_in_3_a_bits_opcode),
.io_in_a_bits_param (auto_in_3_a_bits_param),
.io_in_a_bits_size (auto_in_3_a_bits_size),
.io_in_a_bits_source (auto_in_3_a_bits_source),
.io_in_a_bits_address (auto_in_3_a_bits_address),
.io_in_a_bits_mask (auto_in_3_a_bits_mask),
.io_in_a_bits_corrupt (auto_in_3_a_bits_corrupt),
.io_in_b_ready (auto_in_3_b_ready),
.io_in_b_valid (_inclusive_cache_bank_sched_3_io_in_b_valid), // @[InclusiveCache.scala:137:29]
.io_in_b_bits_param (_inclusive_cache_bank_sched_3_io_in_b_bits_param), // @[InclusiveCache.scala:137:29]
.io_in_b_bits_source (_inclusive_cache_bank_sched_3_io_in_b_bits_source), // @[InclusiveCache.scala:137:29]
.io_in_b_bits_address (nodeIn_3_b_bits_address), // @[Parameters.scala:248:14]
.io_in_c_ready (_inclusive_cache_bank_sched_3_io_in_c_ready), // @[InclusiveCache.scala:137:29]
.io_in_c_valid (auto_in_3_c_valid),
.io_in_c_bits_opcode (auto_in_3_c_bits_opcode),
.io_in_c_bits_param (auto_in_3_c_bits_param),
.io_in_c_bits_size (auto_in_3_c_bits_size),
.io_in_c_bits_source (auto_in_3_c_bits_source),
.io_in_c_bits_address (auto_in_3_c_bits_address),
.io_in_c_bits_corrupt (auto_in_3_c_bits_corrupt),
.io_in_d_ready (auto_in_3_d_ready),
.io_in_d_valid (_inclusive_cache_bank_sched_3_io_in_d_valid), // @[InclusiveCache.scala:137:29]
.io_in_d_bits_opcode (_inclusive_cache_bank_sched_3_io_in_d_bits_opcode), // @[InclusiveCache.scala:137:29]
.io_in_d_bits_param (_inclusive_cache_bank_sched_3_io_in_d_bits_param), // @[InclusiveCache.scala:137:29]
.io_in_d_bits_size (_inclusive_cache_bank_sched_3_io_in_d_bits_size), // @[InclusiveCache.scala:137:29]
.io_in_d_bits_source (_inclusive_cache_bank_sched_3_io_in_d_bits_source), // @[InclusiveCache.scala:137:29]
.io_in_d_bits_sink (_inclusive_cache_bank_sched_3_io_in_d_bits_sink), // @[InclusiveCache.scala:137:29]
.io_in_d_bits_denied (_inclusive_cache_bank_sched_3_io_in_d_bits_denied), // @[InclusiveCache.scala:137:29]
.io_in_d_bits_corrupt (_inclusive_cache_bank_sched_3_io_in_d_bits_corrupt), // @[InclusiveCache.scala:137:29]
.io_in_e_valid (auto_in_3_e_valid),
.io_in_e_bits_sink (auto_in_3_e_bits_sink)
); // @[Nodes.scala:27:25]
InclusiveCacheBankScheduler inclusive_cache_bank_sched ( // @[InclusiveCache.scala:137:29]
.clock (clock),
.reset (reset),
.io_in_a_ready (_inclusive_cache_bank_sched_io_in_a_ready),
.io_in_a_valid (auto_in_0_a_valid),
.io_in_a_bits_opcode (auto_in_0_a_bits_opcode),
.io_in_a_bits_param (auto_in_0_a_bits_param),
.io_in_a_bits_size (auto_in_0_a_bits_size),
.io_in_a_bits_source (auto_in_0_a_bits_source),
.io_in_a_bits_address (auto_in_0_a_bits_address),
.io_in_a_bits_mask (auto_in_0_a_bits_mask),
.io_in_a_bits_data (auto_in_0_a_bits_data),
.io_in_a_bits_corrupt (auto_in_0_a_bits_corrupt),
.io_in_b_ready (auto_in_0_b_ready),
.io_in_b_valid (_inclusive_cache_bank_sched_io_in_b_valid),
.io_in_b_bits_param (_inclusive_cache_bank_sched_io_in_b_bits_param),
.io_in_b_bits_source (_inclusive_cache_bank_sched_io_in_b_bits_source),
.io_in_b_bits_address (_inclusive_cache_bank_sched_io_in_b_bits_address),
.io_in_c_ready (_inclusive_cache_bank_sched_io_in_c_ready),
.io_in_c_valid (auto_in_0_c_valid),
.io_in_c_bits_opcode (auto_in_0_c_bits_opcode),
.io_in_c_bits_param (auto_in_0_c_bits_param),
.io_in_c_bits_size (auto_in_0_c_bits_size),
.io_in_c_bits_source (auto_in_0_c_bits_source),
.io_in_c_bits_address (auto_in_0_c_bits_address),
.io_in_c_bits_data (auto_in_0_c_bits_data),
.io_in_c_bits_corrupt (auto_in_0_c_bits_corrupt),
.io_in_d_ready (auto_in_0_d_ready),
.io_in_d_valid (_inclusive_cache_bank_sched_io_in_d_valid),
.io_in_d_bits_opcode (_inclusive_cache_bank_sched_io_in_d_bits_opcode),
.io_in_d_bits_param (_inclusive_cache_bank_sched_io_in_d_bits_param),
.io_in_d_bits_size (_inclusive_cache_bank_sched_io_in_d_bits_size),
.io_in_d_bits_source (_inclusive_cache_bank_sched_io_in_d_bits_source),
.io_in_d_bits_sink (_inclusive_cache_bank_sched_io_in_d_bits_sink),
.io_in_d_bits_denied (_inclusive_cache_bank_sched_io_in_d_bits_denied),
.io_in_d_bits_data (auto_in_0_d_bits_data),
.io_in_d_bits_corrupt (_inclusive_cache_bank_sched_io_in_d_bits_corrupt),
.io_in_e_valid (auto_in_0_e_valid),
.io_in_e_bits_sink (auto_in_0_e_bits_sink),
.io_out_a_ready (auto_out_0_a_ready),
.io_out_a_valid (auto_out_0_a_valid),
.io_out_a_bits_opcode (auto_out_0_a_bits_opcode),
.io_out_a_bits_param (auto_out_0_a_bits_param),
.io_out_a_bits_size (auto_out_0_a_bits_size),
.io_out_a_bits_source (auto_out_0_a_bits_source),
.io_out_a_bits_address (auto_out_0_a_bits_address),
.io_out_a_bits_mask (auto_out_0_a_bits_mask),
.io_out_a_bits_data (auto_out_0_a_bits_data),
.io_out_a_bits_corrupt (auto_out_0_a_bits_corrupt),
.io_out_c_ready (auto_out_0_c_ready),
.io_out_c_valid (auto_out_0_c_valid),
.io_out_c_bits_opcode (auto_out_0_c_bits_opcode),
.io_out_c_bits_param (auto_out_0_c_bits_param),
.io_out_c_bits_size (auto_out_0_c_bits_size),
.io_out_c_bits_source (auto_out_0_c_bits_source),
.io_out_c_bits_address (auto_out_0_c_bits_address),
.io_out_c_bits_data (auto_out_0_c_bits_data),
.io_out_c_bits_corrupt (auto_out_0_c_bits_corrupt),
.io_out_d_ready (auto_out_0_d_ready),
.io_out_d_valid (auto_out_0_d_valid),
.io_out_d_bits_opcode (auto_out_0_d_bits_opcode),
.io_out_d_bits_param (auto_out_0_d_bits_param),
.io_out_d_bits_size (auto_out_0_d_bits_size),
.io_out_d_bits_source (auto_out_0_d_bits_source),
.io_out_d_bits_sink (auto_out_0_d_bits_sink),
.io_out_d_bits_denied (auto_out_0_d_bits_denied),
.io_out_d_bits_data (auto_out_0_d_bits_data),
.io_out_d_bits_corrupt (auto_out_0_d_bits_corrupt),
.io_out_e_valid (auto_out_0_e_valid),
.io_out_e_bits_sink (auto_out_0_e_bits_sink),
.io_req_ready (_inclusive_cache_bank_sched_io_req_ready),
.io_req_valid (contained & _ctrls_io_flush_req_valid), // @[InclusiveCache.scala:103:43, :169:67, :172:41]
.io_req_bits_address (_ctrls_io_flush_req_bits[31:0]), // @[Parameters.scala:137:31]
.io_resp_valid (_inclusive_cache_bank_sched_io_resp_valid)
); // @[InclusiveCache.scala:137:29]
InclusiveCacheBankScheduler inclusive_cache_bank_sched_1 ( // @[InclusiveCache.scala:137:29]
.clock (clock),
.reset (reset),
.io_in_a_ready (_inclusive_cache_bank_sched_1_io_in_a_ready),
.io_in_a_valid (auto_in_1_a_valid),
.io_in_a_bits_opcode (auto_in_1_a_bits_opcode),
.io_in_a_bits_param (auto_in_1_a_bits_param),
.io_in_a_bits_size (auto_in_1_a_bits_size),
.io_in_a_bits_source (auto_in_1_a_bits_source),
.io_in_a_bits_address (auto_in_1_a_bits_address),
.io_in_a_bits_mask (auto_in_1_a_bits_mask),
.io_in_a_bits_data (auto_in_1_a_bits_data),
.io_in_a_bits_corrupt (auto_in_1_a_bits_corrupt),
.io_in_b_ready (auto_in_1_b_ready),
.io_in_b_valid (_inclusive_cache_bank_sched_1_io_in_b_valid),
.io_in_b_bits_param (_inclusive_cache_bank_sched_1_io_in_b_bits_param),
.io_in_b_bits_source (_inclusive_cache_bank_sched_1_io_in_b_bits_source),
.io_in_b_bits_address (_inclusive_cache_bank_sched_1_io_in_b_bits_address),
.io_in_c_ready (_inclusive_cache_bank_sched_1_io_in_c_ready),
.io_in_c_valid (auto_in_1_c_valid),
.io_in_c_bits_opcode (auto_in_1_c_bits_opcode),
.io_in_c_bits_param (auto_in_1_c_bits_param),
.io_in_c_bits_size (auto_in_1_c_bits_size),
.io_in_c_bits_source (auto_in_1_c_bits_source),
.io_in_c_bits_address (auto_in_1_c_bits_address),
.io_in_c_bits_data (auto_in_1_c_bits_data),
.io_in_c_bits_corrupt (auto_in_1_c_bits_corrupt),
.io_in_d_ready (auto_in_1_d_ready),
.io_in_d_valid (_inclusive_cache_bank_sched_1_io_in_d_valid),
.io_in_d_bits_opcode (_inclusive_cache_bank_sched_1_io_in_d_bits_opcode),
.io_in_d_bits_param (_inclusive_cache_bank_sched_1_io_in_d_bits_param),
.io_in_d_bits_size (_inclusive_cache_bank_sched_1_io_in_d_bits_size),
.io_in_d_bits_source (_inclusive_cache_bank_sched_1_io_in_d_bits_source),
.io_in_d_bits_sink (_inclusive_cache_bank_sched_1_io_in_d_bits_sink),
.io_in_d_bits_denied (_inclusive_cache_bank_sched_1_io_in_d_bits_denied),
.io_in_d_bits_data (auto_in_1_d_bits_data),
.io_in_d_bits_corrupt (_inclusive_cache_bank_sched_1_io_in_d_bits_corrupt),
.io_in_e_valid (auto_in_1_e_valid),
.io_in_e_bits_sink (auto_in_1_e_bits_sink),
.io_out_a_ready (auto_out_1_a_ready),
.io_out_a_valid (auto_out_1_a_valid),
.io_out_a_bits_opcode (auto_out_1_a_bits_opcode),
.io_out_a_bits_param (auto_out_1_a_bits_param),
.io_out_a_bits_size (auto_out_1_a_bits_size),
.io_out_a_bits_source (auto_out_1_a_bits_source),
.io_out_a_bits_address (_inclusive_cache_bank_sched_1_io_out_a_bits_address),
.io_out_a_bits_mask (auto_out_1_a_bits_mask),
.io_out_a_bits_data (auto_out_1_a_bits_data),
.io_out_a_bits_corrupt (auto_out_1_a_bits_corrupt),
.io_out_c_ready (auto_out_1_c_ready),
.io_out_c_valid (auto_out_1_c_valid),
.io_out_c_bits_opcode (auto_out_1_c_bits_opcode),
.io_out_c_bits_param (auto_out_1_c_bits_param),
.io_out_c_bits_size (auto_out_1_c_bits_size),
.io_out_c_bits_source (auto_out_1_c_bits_source),
.io_out_c_bits_address (_inclusive_cache_bank_sched_1_io_out_c_bits_address),
.io_out_c_bits_data (auto_out_1_c_bits_data),
.io_out_c_bits_corrupt (auto_out_1_c_bits_corrupt),
.io_out_d_ready (auto_out_1_d_ready),
.io_out_d_valid (auto_out_1_d_valid),
.io_out_d_bits_opcode (auto_out_1_d_bits_opcode),
.io_out_d_bits_param (auto_out_1_d_bits_param),
.io_out_d_bits_size (auto_out_1_d_bits_size),
.io_out_d_bits_source (auto_out_1_d_bits_source),
.io_out_d_bits_sink (auto_out_1_d_bits_sink),
.io_out_d_bits_denied (auto_out_1_d_bits_denied),
.io_out_d_bits_data (auto_out_1_d_bits_data),
.io_out_d_bits_corrupt (auto_out_1_d_bits_corrupt),
.io_out_e_valid (auto_out_1_e_valid),
.io_out_e_bits_sink (auto_out_1_e_bits_sink),
.io_req_ready (_inclusive_cache_bank_sched_1_io_req_ready),
.io_req_valid (contained_1 & _ctrls_io_flush_req_valid), // @[InclusiveCache.scala:103:43, :169:67, :172:41]
.io_req_bits_address (_ctrls_io_flush_req_bits[31:0]), // @[Parameters.scala:137:31]
.io_resp_valid (_inclusive_cache_bank_sched_1_io_resp_valid)
); // @[InclusiveCache.scala:137:29]
InclusiveCacheBankScheduler inclusive_cache_bank_sched_2 ( // @[InclusiveCache.scala:137:29]
.clock (clock),
.reset (reset),
.io_in_a_ready (_inclusive_cache_bank_sched_2_io_in_a_ready),
.io_in_a_valid (auto_in_2_a_valid),
.io_in_a_bits_opcode (auto_in_2_a_bits_opcode),
.io_in_a_bits_param (auto_in_2_a_bits_param),
.io_in_a_bits_size (auto_in_2_a_bits_size),
.io_in_a_bits_source (auto_in_2_a_bits_source),
.io_in_a_bits_address (auto_in_2_a_bits_address),
.io_in_a_bits_mask (auto_in_2_a_bits_mask),
.io_in_a_bits_data (auto_in_2_a_bits_data),
.io_in_a_bits_corrupt (auto_in_2_a_bits_corrupt),
.io_in_b_ready (auto_in_2_b_ready),
.io_in_b_valid (_inclusive_cache_bank_sched_2_io_in_b_valid),
.io_in_b_bits_param (_inclusive_cache_bank_sched_2_io_in_b_bits_param),
.io_in_b_bits_source (_inclusive_cache_bank_sched_2_io_in_b_bits_source),
.io_in_b_bits_address (_inclusive_cache_bank_sched_2_io_in_b_bits_address),
.io_in_c_ready (_inclusive_cache_bank_sched_2_io_in_c_ready),
.io_in_c_valid (auto_in_2_c_valid),
.io_in_c_bits_opcode (auto_in_2_c_bits_opcode),
.io_in_c_bits_param (auto_in_2_c_bits_param),
.io_in_c_bits_size (auto_in_2_c_bits_size),
.io_in_c_bits_source (auto_in_2_c_bits_source),
.io_in_c_bits_address (auto_in_2_c_bits_address),
.io_in_c_bits_data (auto_in_2_c_bits_data),
.io_in_c_bits_corrupt (auto_in_2_c_bits_corrupt),
.io_in_d_ready (auto_in_2_d_ready),
.io_in_d_valid (_inclusive_cache_bank_sched_2_io_in_d_valid),
.io_in_d_bits_opcode (_inclusive_cache_bank_sched_2_io_in_d_bits_opcode),
.io_in_d_bits_param (_inclusive_cache_bank_sched_2_io_in_d_bits_param),
.io_in_d_bits_size (_inclusive_cache_bank_sched_2_io_in_d_bits_size),
.io_in_d_bits_source (_inclusive_cache_bank_sched_2_io_in_d_bits_source),
.io_in_d_bits_sink (_inclusive_cache_bank_sched_2_io_in_d_bits_sink),
.io_in_d_bits_denied (_inclusive_cache_bank_sched_2_io_in_d_bits_denied),
.io_in_d_bits_data (auto_in_2_d_bits_data),
.io_in_d_bits_corrupt (_inclusive_cache_bank_sched_2_io_in_d_bits_corrupt),
.io_in_e_valid (auto_in_2_e_valid),
.io_in_e_bits_sink (auto_in_2_e_bits_sink),
.io_out_a_ready (auto_out_2_a_ready),
.io_out_a_valid (auto_out_2_a_valid),
.io_out_a_bits_opcode (auto_out_2_a_bits_opcode),
.io_out_a_bits_param (auto_out_2_a_bits_param),
.io_out_a_bits_size (auto_out_2_a_bits_size),
.io_out_a_bits_source (auto_out_2_a_bits_source),
.io_out_a_bits_address (_inclusive_cache_bank_sched_2_io_out_a_bits_address),
.io_out_a_bits_mask (auto_out_2_a_bits_mask),
.io_out_a_bits_data (auto_out_2_a_bits_data),
.io_out_a_bits_corrupt (auto_out_2_a_bits_corrupt),
.io_out_c_ready (auto_out_2_c_ready),
.io_out_c_valid (auto_out_2_c_valid),
.io_out_c_bits_opcode (auto_out_2_c_bits_opcode),
.io_out_c_bits_param (auto_out_2_c_bits_param),
.io_out_c_bits_size (auto_out_2_c_bits_size),
.io_out_c_bits_source (auto_out_2_c_bits_source),
.io_out_c_bits_address (_inclusive_cache_bank_sched_2_io_out_c_bits_address),
.io_out_c_bits_data (auto_out_2_c_bits_data),
.io_out_c_bits_corrupt (auto_out_2_c_bits_corrupt),
.io_out_d_ready (auto_out_2_d_ready),
.io_out_d_valid (auto_out_2_d_valid),
.io_out_d_bits_opcode (auto_out_2_d_bits_opcode),
.io_out_d_bits_param (auto_out_2_d_bits_param),
.io_out_d_bits_size (auto_out_2_d_bits_size),
.io_out_d_bits_source (auto_out_2_d_bits_source),
.io_out_d_bits_sink (auto_out_2_d_bits_sink),
.io_out_d_bits_denied (auto_out_2_d_bits_denied),
.io_out_d_bits_data (auto_out_2_d_bits_data),
.io_out_d_bits_corrupt (auto_out_2_d_bits_corrupt),
.io_out_e_valid (auto_out_2_e_valid),
.io_out_e_bits_sink (auto_out_2_e_bits_sink),
.io_req_ready (_inclusive_cache_bank_sched_2_io_req_ready),
.io_req_valid (contained_2 & _ctrls_io_flush_req_valid), // @[InclusiveCache.scala:103:43, :169:67, :172:41]
.io_req_bits_address (_ctrls_io_flush_req_bits[31:0]), // @[Parameters.scala:137:31]
.io_resp_valid (_inclusive_cache_bank_sched_2_io_resp_valid)
); // @[InclusiveCache.scala:137:29]
InclusiveCacheBankScheduler inclusive_cache_bank_sched_3 ( // @[InclusiveCache.scala:137:29]
.clock (clock),
.reset (reset),
.io_in_a_ready (_inclusive_cache_bank_sched_3_io_in_a_ready),
.io_in_a_valid (auto_in_3_a_valid),
.io_in_a_bits_opcode (auto_in_3_a_bits_opcode),
.io_in_a_bits_param (auto_in_3_a_bits_param),
.io_in_a_bits_size (auto_in_3_a_bits_size),
.io_in_a_bits_source (auto_in_3_a_bits_source),
.io_in_a_bits_address (auto_in_3_a_bits_address),
.io_in_a_bits_mask (auto_in_3_a_bits_mask),
.io_in_a_bits_data (auto_in_3_a_bits_data),
.io_in_a_bits_corrupt (auto_in_3_a_bits_corrupt),
.io_in_b_ready (auto_in_3_b_ready),
.io_in_b_valid (_inclusive_cache_bank_sched_3_io_in_b_valid),
.io_in_b_bits_param (_inclusive_cache_bank_sched_3_io_in_b_bits_param),
.io_in_b_bits_source (_inclusive_cache_bank_sched_3_io_in_b_bits_source),
.io_in_b_bits_address (_inclusive_cache_bank_sched_3_io_in_b_bits_address),
.io_in_c_ready (_inclusive_cache_bank_sched_3_io_in_c_ready),
.io_in_c_valid (auto_in_3_c_valid),
.io_in_c_bits_opcode (auto_in_3_c_bits_opcode),
.io_in_c_bits_param (auto_in_3_c_bits_param),
.io_in_c_bits_size (auto_in_3_c_bits_size),
.io_in_c_bits_source (auto_in_3_c_bits_source),
.io_in_c_bits_address (auto_in_3_c_bits_address),
.io_in_c_bits_data (auto_in_3_c_bits_data),
.io_in_c_bits_corrupt (auto_in_3_c_bits_corrupt),
.io_in_d_ready (auto_in_3_d_ready),
.io_in_d_valid (_inclusive_cache_bank_sched_3_io_in_d_valid),
.io_in_d_bits_opcode (_inclusive_cache_bank_sched_3_io_in_d_bits_opcode),
.io_in_d_bits_param (_inclusive_cache_bank_sched_3_io_in_d_bits_param),
.io_in_d_bits_size (_inclusive_cache_bank_sched_3_io_in_d_bits_size),
.io_in_d_bits_source (_inclusive_cache_bank_sched_3_io_in_d_bits_source),
.io_in_d_bits_sink (_inclusive_cache_bank_sched_3_io_in_d_bits_sink),
.io_in_d_bits_denied (_inclusive_cache_bank_sched_3_io_in_d_bits_denied),
.io_in_d_bits_data (auto_in_3_d_bits_data),
.io_in_d_bits_corrupt (_inclusive_cache_bank_sched_3_io_in_d_bits_corrupt),
.io_in_e_valid (auto_in_3_e_valid),
.io_in_e_bits_sink (auto_in_3_e_bits_sink),
.io_out_a_ready (auto_out_3_a_ready),
.io_out_a_valid (auto_out_3_a_valid),
.io_out_a_bits_opcode (auto_out_3_a_bits_opcode),
.io_out_a_bits_param (auto_out_3_a_bits_param),
.io_out_a_bits_size (auto_out_3_a_bits_size),
.io_out_a_bits_source (auto_out_3_a_bits_source),
.io_out_a_bits_address (_inclusive_cache_bank_sched_3_io_out_a_bits_address),
.io_out_a_bits_mask (auto_out_3_a_bits_mask),
.io_out_a_bits_data (auto_out_3_a_bits_data),
.io_out_a_bits_corrupt (auto_out_3_a_bits_corrupt),
.io_out_c_ready (auto_out_3_c_ready),
.io_out_c_valid (auto_out_3_c_valid),
.io_out_c_bits_opcode (auto_out_3_c_bits_opcode),
.io_out_c_bits_param (auto_out_3_c_bits_param),
.io_out_c_bits_size (auto_out_3_c_bits_size),
.io_out_c_bits_source (auto_out_3_c_bits_source),
.io_out_c_bits_address (_inclusive_cache_bank_sched_3_io_out_c_bits_address),
.io_out_c_bits_data (auto_out_3_c_bits_data),
.io_out_c_bits_corrupt (auto_out_3_c_bits_corrupt),
.io_out_d_ready (auto_out_3_d_ready),
.io_out_d_valid (auto_out_3_d_valid),
.io_out_d_bits_opcode (auto_out_3_d_bits_opcode),
.io_out_d_bits_param (auto_out_3_d_bits_param),
.io_out_d_bits_size (auto_out_3_d_bits_size),
.io_out_d_bits_source (auto_out_3_d_bits_source),
.io_out_d_bits_sink (auto_out_3_d_bits_sink),
.io_out_d_bits_denied (auto_out_3_d_bits_denied),
.io_out_d_bits_data (auto_out_3_d_bits_data),
.io_out_d_bits_corrupt (auto_out_3_d_bits_corrupt),
.io_out_e_valid (auto_out_3_e_valid),
.io_out_e_bits_sink (auto_out_3_e_bits_sink),
.io_req_ready (_inclusive_cache_bank_sched_3_io_req_ready),
.io_req_valid (contained_3 & _ctrls_io_flush_req_valid), // @[InclusiveCache.scala:103:43, :169:67, :172:41]
.io_req_bits_address (_ctrls_io_flush_req_bits[31:0]), // @[Parameters.scala:137:31]
.io_resp_valid (_inclusive_cache_bank_sched_3_io_resp_valid)
); // @[InclusiveCache.scala:137:29]
assign auto_in_3_a_ready = _inclusive_cache_bank_sched_3_io_in_a_ready; // @[InclusiveCache.scala:108:9, :137:29]
assign auto_in_3_b_valid = _inclusive_cache_bank_sched_3_io_in_b_valid; // @[InclusiveCache.scala:108:9, :137:29]
assign auto_in_3_b_bits_param = _inclusive_cache_bank_sched_3_io_in_b_bits_param; // @[InclusiveCache.scala:108:9, :137:29]
assign auto_in_3_b_bits_source = _inclusive_cache_bank_sched_3_io_in_b_bits_source; // @[InclusiveCache.scala:108:9, :137:29]
assign auto_in_3_b_bits_address = nodeIn_3_b_bits_address; // @[Parameters.scala:248:14]
assign auto_in_3_c_ready = _inclusive_cache_bank_sched_3_io_in_c_ready; // @[InclusiveCache.scala:108:9, :137:29]
assign auto_in_3_d_valid = _inclusive_cache_bank_sched_3_io_in_d_valid; // @[InclusiveCache.scala:108:9, :137:29]
assign auto_in_3_d_bits_opcode = _inclusive_cache_bank_sched_3_io_in_d_bits_opcode; // @[InclusiveCache.scala:108:9, :137:29]
assign auto_in_3_d_bits_param = _inclusive_cache_bank_sched_3_io_in_d_bits_param; // @[InclusiveCache.scala:108:9, :137:29]
assign auto_in_3_d_bits_size = _inclusive_cache_bank_sched_3_io_in_d_bits_size; // @[InclusiveCache.scala:108:9, :137:29]
assign auto_in_3_d_bits_source = _inclusive_cache_bank_sched_3_io_in_d_bits_source; // @[InclusiveCache.scala:108:9, :137:29]
assign auto_in_3_d_bits_sink = _inclusive_cache_bank_sched_3_io_in_d_bits_sink; // @[InclusiveCache.scala:108:9, :137:29]
assign auto_in_3_d_bits_denied = _inclusive_cache_bank_sched_3_io_in_d_bits_denied; // @[InclusiveCache.scala:108:9, :137:29]
assign auto_in_3_d_bits_corrupt = _inclusive_cache_bank_sched_3_io_in_d_bits_corrupt; // @[InclusiveCache.scala:108:9, :137:29]
assign auto_in_2_a_ready = _inclusive_cache_bank_sched_2_io_in_a_ready; // @[InclusiveCache.scala:108:9, :137:29]
assign auto_in_2_b_valid = _inclusive_cache_bank_sched_2_io_in_b_valid; // @[InclusiveCache.scala:108:9, :137:29]
assign auto_in_2_b_bits_param = _inclusive_cache_bank_sched_2_io_in_b_bits_param; // @[InclusiveCache.scala:108:9, :137:29]
assign auto_in_2_b_bits_source = _inclusive_cache_bank_sched_2_io_in_b_bits_source; // @[InclusiveCache.scala:108:9, :137:29]
assign auto_in_2_b_bits_address = nodeIn_2_b_bits_address; // @[Parameters.scala:248:14]
assign auto_in_2_c_ready = _inclusive_cache_bank_sched_2_io_in_c_ready; // @[InclusiveCache.scala:108:9, :137:29]
assign auto_in_2_d_valid = _inclusive_cache_bank_sched_2_io_in_d_valid; // @[InclusiveCache.scala:108:9, :137:29]
assign auto_in_2_d_bits_opcode = _inclusive_cache_bank_sched_2_io_in_d_bits_opcode; // @[InclusiveCache.scala:108:9, :137:29]
assign auto_in_2_d_bits_param = _inclusive_cache_bank_sched_2_io_in_d_bits_param; // @[InclusiveCache.scala:108:9, :137:29]
assign auto_in_2_d_bits_size = _inclusive_cache_bank_sched_2_io_in_d_bits_size; // @[InclusiveCache.scala:108:9, :137:29]
assign auto_in_2_d_bits_source = _inclusive_cache_bank_sched_2_io_in_d_bits_source; // @[InclusiveCache.scala:108:9, :137:29]
assign auto_in_2_d_bits_sink = _inclusive_cache_bank_sched_2_io_in_d_bits_sink; // @[InclusiveCache.scala:108:9, :137:29]
assign auto_in_2_d_bits_denied = _inclusive_cache_bank_sched_2_io_in_d_bits_denied; // @[InclusiveCache.scala:108:9, :137:29]
assign auto_in_2_d_bits_corrupt = _inclusive_cache_bank_sched_2_io_in_d_bits_corrupt; // @[InclusiveCache.scala:108:9, :137:29]
assign auto_in_1_a_ready = _inclusive_cache_bank_sched_1_io_in_a_ready; // @[InclusiveCache.scala:108:9, :137:29]
assign auto_in_1_b_valid = _inclusive_cache_bank_sched_1_io_in_b_valid; // @[InclusiveCache.scala:108:9, :137:29]
assign auto_in_1_b_bits_param = _inclusive_cache_bank_sched_1_io_in_b_bits_param; // @[InclusiveCache.scala:108:9, :137:29]
assign auto_in_1_b_bits_source = _inclusive_cache_bank_sched_1_io_in_b_bits_source; // @[InclusiveCache.scala:108:9, :137:29]
assign auto_in_1_b_bits_address = nodeIn_1_b_bits_address; // @[Parameters.scala:248:14]
assign auto_in_1_c_ready = _inclusive_cache_bank_sched_1_io_in_c_ready; // @[InclusiveCache.scala:108:9, :137:29]
assign auto_in_1_d_valid = _inclusive_cache_bank_sched_1_io_in_d_valid; // @[InclusiveCache.scala:108:9, :137:29]
assign auto_in_1_d_bits_opcode = _inclusive_cache_bank_sched_1_io_in_d_bits_opcode; // @[InclusiveCache.scala:108:9, :137:29]
assign auto_in_1_d_bits_param = _inclusive_cache_bank_sched_1_io_in_d_bits_param; // @[InclusiveCache.scala:108:9, :137:29]
assign auto_in_1_d_bits_size = _inclusive_cache_bank_sched_1_io_in_d_bits_size; // @[InclusiveCache.scala:108:9, :137:29]
assign auto_in_1_d_bits_source = _inclusive_cache_bank_sched_1_io_in_d_bits_source; // @[InclusiveCache.scala:108:9, :137:29]
assign auto_in_1_d_bits_sink = _inclusive_cache_bank_sched_1_io_in_d_bits_sink; // @[InclusiveCache.scala:108:9, :137:29]
assign auto_in_1_d_bits_denied = _inclusive_cache_bank_sched_1_io_in_d_bits_denied; // @[InclusiveCache.scala:108:9, :137:29]
assign auto_in_1_d_bits_corrupt = _inclusive_cache_bank_sched_1_io_in_d_bits_corrupt; // @[InclusiveCache.scala:108:9, :137:29]
assign auto_in_0_a_ready = _inclusive_cache_bank_sched_io_in_a_ready; // @[InclusiveCache.scala:108:9, :137:29]
assign auto_in_0_b_valid = _inclusive_cache_bank_sched_io_in_b_valid; // @[InclusiveCache.scala:108:9, :137:29]
assign auto_in_0_b_bits_param = _inclusive_cache_bank_sched_io_in_b_bits_param; // @[InclusiveCache.scala:108:9, :137:29]
assign auto_in_0_b_bits_source = _inclusive_cache_bank_sched_io_in_b_bits_source; // @[InclusiveCache.scala:108:9, :137:29]
assign auto_in_0_b_bits_address = _inclusive_cache_bank_sched_io_in_b_bits_address; // @[InclusiveCache.scala:108:9, :137:29]
assign auto_in_0_c_ready = _inclusive_cache_bank_sched_io_in_c_ready; // @[InclusiveCache.scala:108:9, :137:29]
assign auto_in_0_d_valid = _inclusive_cache_bank_sched_io_in_d_valid; // @[InclusiveCache.scala:108:9, :137:29]
assign auto_in_0_d_bits_opcode = _inclusive_cache_bank_sched_io_in_d_bits_opcode; // @[InclusiveCache.scala:108:9, :137:29]
assign auto_in_0_d_bits_param = _inclusive_cache_bank_sched_io_in_d_bits_param; // @[InclusiveCache.scala:108:9, :137:29]
assign auto_in_0_d_bits_size = _inclusive_cache_bank_sched_io_in_d_bits_size; // @[InclusiveCache.scala:108:9, :137:29]
assign auto_in_0_d_bits_source = _inclusive_cache_bank_sched_io_in_d_bits_source; // @[InclusiveCache.scala:108:9, :137:29]
assign auto_in_0_d_bits_sink = _inclusive_cache_bank_sched_io_in_d_bits_sink; // @[InclusiveCache.scala:108:9, :137:29]
assign auto_in_0_d_bits_denied = _inclusive_cache_bank_sched_io_in_d_bits_denied; // @[InclusiveCache.scala:108:9, :137:29]
assign auto_in_0_d_bits_corrupt = _inclusive_cache_bank_sched_io_in_d_bits_corrupt; // @[InclusiveCache.scala:108:9, :137:29]
assign auto_out_3_a_bits_address = {_inclusive_cache_bank_sched_3_io_out_a_bits_address[31:8], _inclusive_cache_bank_sched_3_io_out_a_bits_address[7:0] | 8'hC0}; // @[Parameters.scala:248:14]
assign auto_out_3_c_bits_address = {_inclusive_cache_bank_sched_3_io_out_c_bits_address[31:8], _inclusive_cache_bank_sched_3_io_out_c_bits_address[7:0] | 8'hC0}; // @[Parameters.scala:248:14]
assign auto_out_2_a_bits_address = {_inclusive_cache_bank_sched_2_io_out_a_bits_address[31:8], _inclusive_cache_bank_sched_2_io_out_a_bits_address[7:0] | 8'h80}; // @[Parameters.scala:248:14]
assign auto_out_2_c_bits_address = {_inclusive_cache_bank_sched_2_io_out_c_bits_address[31:8], _inclusive_cache_bank_sched_2_io_out_c_bits_address[7:0] | 8'h80}; // @[Parameters.scala:248:14]
assign auto_out_1_a_bits_address = {_inclusive_cache_bank_sched_1_io_out_a_bits_address[31:7], _inclusive_cache_bank_sched_1_io_out_a_bits_address[6:0] | 7'h40}; // @[Parameters.scala:248:14]
assign auto_out_1_c_bits_address = {_inclusive_cache_bank_sched_1_io_out_c_bits_address[31:7], _inclusive_cache_bank_sched_1_io_out_c_bits_address[6:0] | 7'h40}; // @[Parameters.scala:248:14]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File ShiftRegisterPriorityQueue.scala:
package compressacc
import chisel3._
import chisel3.util._
import chisel3.util._
// TODO : support enq & deq at the same cycle
class PriorityQueueStageIO(keyWidth: Int, value: ValueInfo) extends Bundle {
val output_prev = KeyValue(keyWidth, value)
val output_nxt = KeyValue(keyWidth, value)
val input_prev = Flipped(KeyValue(keyWidth, value))
val input_nxt = Flipped(KeyValue(keyWidth, value))
val cmd = Flipped(Valid(UInt(1.W)))
val insert_here = Input(Bool())
val cur_input_keyval = Flipped(KeyValue(keyWidth, value))
val cur_output_keyval = KeyValue(keyWidth, value)
}
class PriorityQueueStage(keyWidth: Int, value: ValueInfo) extends Module {
val io = IO(new PriorityQueueStageIO(keyWidth, value))
dontTouch(io)
val CMD_DEQ = 0.U
val CMD_ENQ = 1.U
val MAX_VALUE = (1 << keyWidth) - 1
val key_reg = RegInit(MAX_VALUE.U(keyWidth.W))
val value_reg = Reg(value)
io.output_prev.key := key_reg
io.output_prev.value := value_reg
io.output_nxt.key := key_reg
io.output_nxt.value := value_reg
io.cur_output_keyval.key := key_reg
io.cur_output_keyval.value := value_reg
when (io.cmd.valid) {
switch (io.cmd.bits) {
is (CMD_DEQ) {
key_reg := io.input_nxt.key
value_reg := io.input_nxt.value
}
is (CMD_ENQ) {
when (io.insert_here) {
key_reg := io.cur_input_keyval.key
value_reg := io.cur_input_keyval.value
} .elsewhen (key_reg >= io.cur_input_keyval.key) {
key_reg := io.input_prev.key
value_reg := io.input_prev.value
} .otherwise {
// do nothing
}
}
}
}
}
object PriorityQueueStage {
def apply(keyWidth: Int, v: ValueInfo): PriorityQueueStage = new PriorityQueueStage(keyWidth, v)
}
// TODO
// - This design is not scalable as the enqued_keyval is broadcasted to all the stages
// - Add pipeline registers later
class PriorityQueueIO(queSize: Int, keyWidth: Int, value: ValueInfo) extends Bundle {
val cnt_bits = log2Ceil(queSize+1)
val counter = Output(UInt(cnt_bits.W))
val enq = Flipped(Decoupled(KeyValue(keyWidth, value)))
val deq = Decoupled(KeyValue(keyWidth, value))
}
class PriorityQueue(queSize: Int, keyWidth: Int, value: ValueInfo) extends Module {
val keyWidthInternal = keyWidth + 1
val CMD_DEQ = 0.U
val CMD_ENQ = 1.U
val io = IO(new PriorityQueueIO(queSize, keyWidthInternal, value))
dontTouch(io)
val MAX_VALUE = ((1 << keyWidthInternal) - 1).U
val cnt_bits = log2Ceil(queSize+1)
// do not consider cases where we are inserting more entries then the queSize
val counter = RegInit(0.U(cnt_bits.W))
io.counter := counter
val full = (counter === queSize.U)
val empty = (counter === 0.U)
io.deq.valid := !empty
io.enq.ready := !full
when (io.enq.fire) {
counter := counter + 1.U
}
when (io.deq.fire) {
counter := counter - 1.U
}
val cmd_valid = io.enq.valid || io.deq.ready
val cmd = Mux(io.enq.valid, CMD_ENQ, CMD_DEQ)
assert(!(io.enq.valid && io.deq.ready))
val stages = Seq.fill(queSize)(Module(new PriorityQueueStage(keyWidthInternal, value)))
for (i <- 0 until (queSize - 1)) {
stages(i+1).io.input_prev <> stages(i).io.output_nxt
stages(i).io.input_nxt <> stages(i+1).io.output_prev
}
stages(queSize-1).io.input_nxt.key := MAX_VALUE
// stages(queSize-1).io.input_nxt.value :=
stages(queSize-1).io.input_nxt.value.symbol := 0.U
// stages(queSize-1).io.input_nxt.value.child(0) := 0.U
// stages(queSize-1).io.input_nxt.value.child(1) := 0.U
stages(0).io.input_prev.key := io.enq.bits.key
stages(0).io.input_prev.value <> io.enq.bits.value
for (i <- 0 until queSize) {
stages(i).io.cmd.valid := cmd_valid
stages(i).io.cmd.bits := cmd
stages(i).io.cur_input_keyval <> io.enq.bits
}
val is_large_or_equal = WireInit(VecInit(Seq.fill(queSize)(false.B)))
for (i <- 0 until queSize) {
is_large_or_equal(i) := (stages(i).io.cur_output_keyval.key >= io.enq.bits.key)
}
val is_large_or_equal_cat = Wire(UInt(queSize.W))
is_large_or_equal_cat := Cat(is_large_or_equal.reverse)
val insert_here_idx = PriorityEncoder(is_large_or_equal_cat)
for (i <- 0 until queSize) {
when (i.U === insert_here_idx) {
stages(i).io.insert_here := true.B
} .otherwise {
stages(i).io.insert_here := false.B
}
}
io.deq.bits <> stages(0).io.output_prev
}
| module PriorityQueueStage_136( // @[ShiftRegisterPriorityQueue.scala:21:7]
input clock, // @[ShiftRegisterPriorityQueue.scala:21:7]
input reset, // @[ShiftRegisterPriorityQueue.scala:21:7]
output [30:0] io_output_prev_key, // @[ShiftRegisterPriorityQueue.scala:22:14]
output [9:0] io_output_prev_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14]
output [30:0] io_output_nxt_key, // @[ShiftRegisterPriorityQueue.scala:22:14]
output [9:0] io_output_nxt_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14]
input [30:0] io_input_prev_key, // @[ShiftRegisterPriorityQueue.scala:22:14]
input [9:0] io_input_prev_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14]
input [30:0] io_input_nxt_key, // @[ShiftRegisterPriorityQueue.scala:22:14]
input [9:0] io_input_nxt_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14]
input io_cmd_valid, // @[ShiftRegisterPriorityQueue.scala:22:14]
input io_cmd_bits, // @[ShiftRegisterPriorityQueue.scala:22:14]
input io_insert_here, // @[ShiftRegisterPriorityQueue.scala:22:14]
input [30:0] io_cur_input_keyval_key, // @[ShiftRegisterPriorityQueue.scala:22:14]
input [9:0] io_cur_input_keyval_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14]
output [30:0] io_cur_output_keyval_key, // @[ShiftRegisterPriorityQueue.scala:22:14]
output [9:0] io_cur_output_keyval_value_symbol // @[ShiftRegisterPriorityQueue.scala:22:14]
);
wire [30:0] io_input_prev_key_0 = io_input_prev_key; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [9:0] io_input_prev_value_symbol_0 = io_input_prev_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [30:0] io_input_nxt_key_0 = io_input_nxt_key; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [9:0] io_input_nxt_value_symbol_0 = io_input_nxt_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire io_cmd_valid_0 = io_cmd_valid; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire io_cmd_bits_0 = io_cmd_bits; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire io_insert_here_0 = io_insert_here; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [30:0] io_cur_input_keyval_key_0 = io_cur_input_keyval_key; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [9:0] io_cur_input_keyval_value_symbol_0 = io_cur_input_keyval_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [9:0] io_output_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [30:0] io_output_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [9:0] io_output_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [30:0] io_output_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [9:0] io_cur_output_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [30:0] io_cur_output_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
reg [30:0] key_reg; // @[ShiftRegisterPriorityQueue.scala:30:24]
assign io_output_prev_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]
assign io_output_nxt_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]
assign io_cur_output_keyval_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]
reg [9:0] value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:31:22]
assign io_output_prev_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]
assign io_output_nxt_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]
assign io_cur_output_keyval_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]
wire _T_2 = key_reg >= io_cur_input_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24, :52:30]
always @(posedge clock) begin // @[ShiftRegisterPriorityQueue.scala:21:7]
if (reset) // @[ShiftRegisterPriorityQueue.scala:21:7]
key_reg <= 31'h7FFFFFFF; // @[ShiftRegisterPriorityQueue.scala:30:24]
else if (io_cmd_valid_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7]
if (io_cmd_bits_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7]
if (io_insert_here_0) // @[ShiftRegisterPriorityQueue.scala:21:7]
key_reg <= io_cur_input_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]
else if (_T_2) // @[ShiftRegisterPriorityQueue.scala:52:30]
key_reg <= io_input_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]
end
else // @[ShiftRegisterPriorityQueue.scala:21:7]
key_reg <= io_input_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]
end
if (io_cmd_valid_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7]
if (io_cmd_bits_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7]
if (io_insert_here_0) // @[ShiftRegisterPriorityQueue.scala:21:7]
value_reg_symbol <= io_cur_input_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]
else if (_T_2) // @[ShiftRegisterPriorityQueue.scala:52:30]
value_reg_symbol <= io_input_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]
end
else // @[ShiftRegisterPriorityQueue.scala:21:7]
value_reg_symbol <= io_input_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]
end
always @(posedge)
assign io_output_prev_key = io_output_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
assign io_output_prev_value_symbol = io_output_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
assign io_output_nxt_key = io_output_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
assign io_output_nxt_value_symbol = io_output_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
assign io_cur_output_keyval_key = io_cur_output_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
assign io_cur_output_keyval_value_symbol = io_cur_output_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File TilelinkAdapters.scala:
package constellation.protocol
import chisel3._
import chisel3.util._
import constellation.channel._
import constellation.noc._
import constellation.soc.{CanAttachToGlobalNoC}
import org.chipsalliance.cde.config._
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.util._
import freechips.rocketchip.tilelink._
import scala.collection.immutable.{ListMap}
abstract class TLChannelToNoC[T <: TLChannel](gen: => T, edge: TLEdge, idToEgress: Int => Int)(implicit val p: Parameters) extends Module with TLFieldHelper {
val flitWidth = minTLPayloadWidth(gen)
val io = IO(new Bundle {
val protocol = Flipped(Decoupled(gen))
val flit = Decoupled(new IngressFlit(flitWidth))
})
def unique(x: Vector[Boolean]): Bool = (x.filter(x=>x).size <= 1).B
// convert decoupled to irrevocable
val q = Module(new Queue(gen, 1, pipe=true, flow=true))
val protocol = q.io.deq
val has_body = Wire(Bool())
val body_fields = getBodyFields(protocol.bits)
val const_fields = getConstFields(protocol.bits)
val head = edge.first(protocol.bits, protocol.fire)
val tail = edge.last(protocol.bits, protocol.fire)
def requestOH: Seq[Bool]
val body = Cat( body_fields.filter(_.getWidth > 0).map(_.asUInt))
val const = Cat(const_fields.filter(_.getWidth > 0).map(_.asUInt))
val is_body = RegInit(false.B)
io.flit.valid := protocol.valid
protocol.ready := io.flit.ready && (is_body || !has_body)
io.flit.bits.head := head && !is_body
io.flit.bits.tail := tail && (is_body || !has_body)
io.flit.bits.egress_id := Mux1H(requestOH.zipWithIndex.map { case (r, i) =>
r -> idToEgress(i).U
})
io.flit.bits.payload := Mux(is_body, body, const)
when (io.flit.fire && io.flit.bits.head) { is_body := true.B }
when (io.flit.fire && io.flit.bits.tail) { is_body := false.B }
}
abstract class TLChannelFromNoC[T <: TLChannel](gen: => T)(implicit val p: Parameters) extends Module with TLFieldHelper {
val flitWidth = minTLPayloadWidth(gen)
val io = IO(new Bundle {
val protocol = Decoupled(gen)
val flit = Flipped(Decoupled(new EgressFlit(flitWidth)))
})
// Handle size = 1 gracefully (Chisel3 empty range is broken)
def trim(id: UInt, size: Int): UInt = if (size <= 1) 0.U else id(log2Ceil(size)-1, 0)
val protocol = Wire(Decoupled(gen))
val body_fields = getBodyFields(protocol.bits)
val const_fields = getConstFields(protocol.bits)
val is_const = RegInit(true.B)
val const_reg = Reg(UInt(const_fields.map(_.getWidth).sum.W))
val const = Mux(io.flit.bits.head, io.flit.bits.payload, const_reg)
io.flit.ready := (is_const && !io.flit.bits.tail) || protocol.ready
protocol.valid := (!is_const || io.flit.bits.tail) && io.flit.valid
def assign(i: UInt, sigs: Seq[Data]) = {
var t = i
for (s <- sigs.reverse) {
s := t.asTypeOf(s.cloneType)
t = t >> s.getWidth
}
}
assign(const, const_fields)
assign(io.flit.bits.payload, body_fields)
when (io.flit.fire && io.flit.bits.head) { is_const := false.B; const_reg := io.flit.bits.payload }
when (io.flit.fire && io.flit.bits.tail) { is_const := true.B }
}
trait HasAddressDecoder {
// Filter a list to only those elements selected
def filter[T](data: Seq[T], mask: Seq[Boolean]) = (data zip mask).filter(_._2).map(_._1)
val edgeIn: TLEdge
val edgesOut: Seq[TLEdge]
lazy val reacheableIO = edgesOut.map { mp =>
edgeIn.client.clients.exists { c => mp.manager.managers.exists { m =>
c.visibility.exists { ca => m.address.exists { ma =>
ca.overlaps(ma)
}}
}}
}.toVector
lazy val releaseIO = (edgesOut zip reacheableIO).map { case (mp, reachable) =>
reachable && edgeIn.client.anySupportProbe && mp.manager.anySupportAcquireB
}.toVector
def outputPortFn(connectIO: Seq[Boolean]) = {
val port_addrs = edgesOut.map(_.manager.managers.flatMap(_.address))
val routingMask = AddressDecoder(filter(port_addrs, connectIO))
val route_addrs = port_addrs.map(seq => AddressSet.unify(seq.map(_.widen(~routingMask)).distinct))
route_addrs.map(seq => (addr: UInt) => seq.map(_.contains(addr)).reduce(_||_))
}
}
class TLAToNoC(
val edgeIn: TLEdge,
val edgesOut: Seq[TLEdge],
bundle: TLBundleParameters,
slaveToAEgress: Int => Int,
sourceStart: Int
)(implicit p: Parameters) extends TLChannelToNoC(new TLBundleA(bundle), edgeIn, slaveToAEgress)(p) with HasAddressDecoder {
has_body := edgeIn.hasData(protocol.bits) || (~protocol.bits.mask =/= 0.U)
lazy val connectAIO = reacheableIO
lazy val requestOH = outputPortFn(connectAIO).zipWithIndex.map { case (o, j) =>
connectAIO(j).B && (unique(connectAIO) || o(protocol.bits.address))
}
q.io.enq <> io.protocol
q.io.enq.bits.source := io.protocol.bits.source | sourceStart.U
}
class TLAFromNoC(edgeOut: TLEdge, bundle: TLBundleParameters)(implicit p: Parameters) extends TLChannelFromNoC(new TLBundleA(bundle))(p) {
io.protocol <> protocol
when (io.flit.bits.head) { io.protocol.bits.mask := ~(0.U(io.protocol.bits.mask.getWidth.W)) }
}
class TLBToNoC(
edgeOut: TLEdge,
edgesIn: Seq[TLEdge],
bundle: TLBundleParameters,
masterToBIngress: Int => Int
)(implicit p: Parameters) extends TLChannelToNoC(new TLBundleB(bundle), edgeOut, masterToBIngress)(p) {
has_body := edgeOut.hasData(protocol.bits) || (~protocol.bits.mask =/= 0.U)
lazy val inputIdRanges = TLXbar.mapInputIds(edgesIn.map(_.client))
lazy val requestOH = inputIdRanges.map { i => i.contains(protocol.bits.source) }
q.io.enq <> io.protocol
}
class TLBFromNoC(edgeIn: TLEdge, bundle: TLBundleParameters, sourceSize: Int)(implicit p: Parameters) extends TLChannelFromNoC(new TLBundleB(bundle))(p) {
io.protocol <> protocol
io.protocol.bits.source := trim(protocol.bits.source, sourceSize)
when (io.flit.bits.head) { io.protocol.bits.mask := ~(0.U(io.protocol.bits.mask.getWidth.W)) }
}
class TLCToNoC(
val edgeIn: TLEdge,
val edgesOut: Seq[TLEdge],
bundle: TLBundleParameters,
slaveToCEgress: Int => Int,
sourceStart: Int
)(implicit p: Parameters) extends TLChannelToNoC(new TLBundleC(bundle), edgeIn, slaveToCEgress)(p) with HasAddressDecoder {
has_body := edgeIn.hasData(protocol.bits)
lazy val connectCIO = releaseIO
lazy val requestOH = outputPortFn(connectCIO).zipWithIndex.map {
case (o, j) => connectCIO(j).B && (unique(connectCIO) || o(protocol.bits.address))
}
q.io.enq <> io.protocol
q.io.enq.bits.source := io.protocol.bits.source | sourceStart.U
}
class TLCFromNoC(edgeOut: TLEdge, bundle: TLBundleParameters)(implicit p: Parameters) extends TLChannelFromNoC(new TLBundleC(bundle))(p) {
io.protocol <> protocol
}
class TLDToNoC(
edgeOut: TLEdge,
edgesIn: Seq[TLEdge],
bundle: TLBundleParameters,
masterToDIngress: Int => Int,
sourceStart: Int
)(implicit p: Parameters) extends TLChannelToNoC(new TLBundleD(bundle), edgeOut, masterToDIngress)(p) {
has_body := edgeOut.hasData(protocol.bits)
lazy val inputIdRanges = TLXbar.mapInputIds(edgesIn.map(_.client))
lazy val requestOH = inputIdRanges.map { i => i.contains(protocol.bits.source) }
q.io.enq <> io.protocol
q.io.enq.bits.sink := io.protocol.bits.sink | sourceStart.U
}
class TLDFromNoC(edgeIn: TLEdge, bundle: TLBundleParameters, sourceSize: Int)(implicit p: Parameters) extends TLChannelFromNoC(new TLBundleD(bundle))(p)
{
io.protocol <> protocol
io.protocol.bits.source := trim(protocol.bits.source, sourceSize)
}
class TLEToNoC(
val edgeIn: TLEdge,
val edgesOut: Seq[TLEdge],
bundle: TLBundleParameters,
slaveToEEgress: Int => Int
)(implicit p: Parameters) extends TLChannelToNoC(new TLBundleE(bundle), edgeIn, slaveToEEgress)(p) {
has_body := edgeIn.hasData(protocol.bits)
lazy val outputIdRanges = TLXbar.mapOutputIds(edgesOut.map(_.manager))
lazy val requestOH = outputIdRanges.map { o => o.contains(protocol.bits.sink) }
q.io.enq <> io.protocol
}
class TLEFromNoC(edgeOut: TLEdge, bundle: TLBundleParameters, sourceSize: Int)(implicit p: Parameters) extends TLChannelFromNoC(new TLBundleE(bundle))(p) {
io.protocol <> protocol
io.protocol.bits.sink := trim(protocol.bits.sink, sourceSize)
}
File Edges.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.util._
class TLEdge(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdgeParameters(client, manager, params, sourceInfo)
{
def isAligned(address: UInt, lgSize: UInt): Bool = {
if (maxLgSize == 0) true.B else {
val mask = UIntToOH1(lgSize, maxLgSize)
(address & mask) === 0.U
}
}
def mask(address: UInt, lgSize: UInt): UInt =
MaskGen(address, lgSize, manager.beatBytes)
def staticHasData(bundle: TLChannel): Option[Boolean] = {
bundle match {
case _:TLBundleA => {
// Do there exist A messages with Data?
val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial
// Do there exist A messages without Data?
val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint
// Statically optimize the case where hasData is a constant
if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None
}
case _:TLBundleB => {
// Do there exist B messages with Data?
val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial
// Do there exist B messages without Data?
val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint
// Statically optimize the case where hasData is a constant
if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None
}
case _:TLBundleC => {
// Do there eixst C messages with Data?
val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe
// Do there exist C messages without Data?
val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe
if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None
}
case _:TLBundleD => {
// Do there eixst D messages with Data?
val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB
// Do there exist D messages without Data?
val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT
if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None
}
case _:TLBundleE => Some(false)
}
}
def isRequest(x: TLChannel): Bool = {
x match {
case a: TLBundleA => true.B
case b: TLBundleB => true.B
case c: TLBundleC => c.opcode(2) && c.opcode(1)
// opcode === TLMessages.Release ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(2) && !d.opcode(1)
// opcode === TLMessages.Grant ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
}
def isResponse(x: TLChannel): Bool = {
x match {
case a: TLBundleA => false.B
case b: TLBundleB => false.B
case c: TLBundleC => !c.opcode(2) || !c.opcode(1)
// opcode =/= TLMessages.Release &&
// opcode =/= TLMessages.ReleaseData
case d: TLBundleD => true.B // Grant isResponse + isRequest
case e: TLBundleE => true.B
}
}
def hasData(x: TLChannel): Bool = {
val opdata = x match {
case a: TLBundleA => !a.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case b: TLBundleB => !b.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case c: TLBundleC => c.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.ProbeAckData ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
staticHasData(x).map(_.B).getOrElse(opdata)
}
def opcode(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.opcode
case b: TLBundleB => b.opcode
case c: TLBundleC => c.opcode
case d: TLBundleD => d.opcode
}
}
def param(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.param
case b: TLBundleB => b.param
case c: TLBundleC => c.param
case d: TLBundleD => d.param
}
}
def size(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.size
case b: TLBundleB => b.size
case c: TLBundleC => c.size
case d: TLBundleD => d.size
}
}
def data(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.data
case b: TLBundleB => b.data
case c: TLBundleC => c.data
case d: TLBundleD => d.data
}
}
def corrupt(x: TLDataChannel): Bool = {
x match {
case a: TLBundleA => a.corrupt
case b: TLBundleB => b.corrupt
case c: TLBundleC => c.corrupt
case d: TLBundleD => d.corrupt
}
}
def mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.mask
case b: TLBundleB => b.mask
case c: TLBundleC => mask(c.address, c.size)
}
}
def full_mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => mask(a.address, a.size)
case b: TLBundleB => mask(b.address, b.size)
case c: TLBundleC => mask(c.address, c.size)
}
}
def address(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.address
case b: TLBundleB => b.address
case c: TLBundleC => c.address
}
}
def source(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.source
case b: TLBundleB => b.source
case c: TLBundleC => c.source
case d: TLBundleD => d.source
}
}
def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes)
def addr_lo(x: UInt): UInt =
if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0)
def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x))
def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x))
def numBeats(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 1.U
case bundle: TLDataChannel => {
val hasData = this.hasData(bundle)
val size = this.size(bundle)
val cutoff = log2Ceil(manager.beatBytes)
val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U
val decode = UIntToOH(size, maxLgSize+1) >> cutoff
Mux(hasData, decode | small.asUInt, 1.U)
}
}
}
def numBeats1(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 0.U
case bundle: TLDataChannel => {
if (maxLgSize == 0) {
0.U
} else {
val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes)
Mux(hasData(bundle), decode, 0.U)
}
}
}
}
def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val beats1 = numBeats1(bits)
val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W))
val counter1 = counter - 1.U
val first = counter === 0.U
val last = counter === 1.U || beats1 === 0.U
val done = last && fire
val count = (beats1 & ~counter1)
when (fire) {
counter := Mux(first, beats1, counter1)
}
(first, last, done, count)
}
def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1
def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire)
def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid)
def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2
def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire)
def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid)
def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3
def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire)
def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid)
def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3)
}
def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire)
def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid)
def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4)
}
def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire)
def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid)
def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes))
}
def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire)
def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid)
// Does the request need T permissions to be executed?
def needT(a: TLBundleA): Bool = {
val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLPermissions.NtoB -> false.B,
TLPermissions.NtoT -> true.B,
TLPermissions.BtoT -> true.B))
MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array(
TLMessages.PutFullData -> true.B,
TLMessages.PutPartialData -> true.B,
TLMessages.ArithmeticData -> true.B,
TLMessages.LogicalData -> true.B,
TLMessages.Get -> false.B,
TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLHints.PREFETCH_READ -> false.B,
TLHints.PREFETCH_WRITE -> true.B)),
TLMessages.AcquireBlock -> acq_needT,
TLMessages.AcquirePerm -> acq_needT))
}
// This is a very expensive circuit; use only if you really mean it!
def inFlight(x: TLBundle): (UInt, UInt) = {
val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W))
val bce = manager.anySupportAcquireB && client.anySupportProbe
val (a_first, a_last, _) = firstlast(x.a)
val (b_first, b_last, _) = firstlast(x.b)
val (c_first, c_last, _) = firstlast(x.c)
val (d_first, d_last, _) = firstlast(x.d)
val (e_first, e_last, _) = firstlast(x.e)
val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits))
val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits))
val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits))
val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits))
val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits))
val a_inc = x.a.fire && a_first && a_request
val b_inc = x.b.fire && b_first && b_request
val c_inc = x.c.fire && c_first && c_request
val d_inc = x.d.fire && d_first && d_request
val e_inc = x.e.fire && e_first && e_request
val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil))
val a_dec = x.a.fire && a_last && a_response
val b_dec = x.b.fire && b_last && b_response
val c_dec = x.c.fire && c_last && c_response
val d_dec = x.d.fire && d_last && d_response
val e_dec = x.e.fire && e_last && e_response
val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil))
val next_flight = flight + PopCount(inc) - PopCount(dec)
flight := next_flight
(flight, next_flight)
}
def prettySourceMapping(context: String): String = {
s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n"
}
}
class TLEdgeOut(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
// Transfers
def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquireBlock
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquirePerm
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.Release
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ReleaseData
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) =
Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B)
def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAck
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions, data)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAckData
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B)
def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink)
def GrantAck(toSink: UInt): TLBundleE = {
val e = Wire(new TLBundleE(bundle))
e.sink := toSink
e
}
// Accesses
def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsGetFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Get
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutFullFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutFullData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, mask, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutPartialFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutPartialData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = {
require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsArithmeticFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.ArithmeticData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsLogicalFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.LogicalData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = {
require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsHintFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Hint
a.param := param
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data)
def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAckData
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size)
def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.HintAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
}
class TLEdgeIn(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = {
val todo = x.filter(!_.isEmpty)
val heads = todo.map(_.head)
val tails = todo.map(_.tail)
if (todo.isEmpty) Nil else { heads +: myTranspose(tails) }
}
// Transfers
def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = {
require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}")
val legal = client.supportsProbe(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Probe
b.param := capPermissions
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.Grant
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.GrantData
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B)
def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.ReleaseAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
// Accesses
def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = {
require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsGet(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Get
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsPutFull(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutFullData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, mask, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsPutPartial(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutPartialData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsArithmetic(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.ArithmeticData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsLogical(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.LogicalData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = {
require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsHint(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Hint
b.param := param
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size)
def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied)
def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data)
def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAckData
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B)
def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied)
def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B)
def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.HintAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
}
| module TLBToNoC_1( // @[TilelinkAdapters.scala:133:7]
input clock, // @[TilelinkAdapters.scala:133:7]
input reset, // @[TilelinkAdapters.scala:133:7]
output io_protocol_ready, // @[TilelinkAdapters.scala:19:14]
input io_protocol_valid, // @[TilelinkAdapters.scala:19:14]
input [1:0] io_protocol_bits_param, // @[TilelinkAdapters.scala:19:14]
input [6:0] io_protocol_bits_source, // @[TilelinkAdapters.scala:19:14]
input [31:0] io_protocol_bits_address, // @[TilelinkAdapters.scala:19:14]
input io_flit_ready, // @[TilelinkAdapters.scala:19:14]
output io_flit_valid, // @[TilelinkAdapters.scala:19:14]
output io_flit_bits_head, // @[TilelinkAdapters.scala:19:14]
output io_flit_bits_tail, // @[TilelinkAdapters.scala:19:14]
output [144:0] io_flit_bits_payload, // @[TilelinkAdapters.scala:19:14]
output [3:0] io_flit_bits_egress_id // @[TilelinkAdapters.scala:19:14]
);
wire _q_io_deq_valid; // @[TilelinkAdapters.scala:26:17]
wire [2:0] _q_io_deq_bits_opcode; // @[TilelinkAdapters.scala:26:17]
wire [1:0] _q_io_deq_bits_param; // @[TilelinkAdapters.scala:26:17]
wire [3:0] _q_io_deq_bits_size; // @[TilelinkAdapters.scala:26:17]
wire [6:0] _q_io_deq_bits_source; // @[TilelinkAdapters.scala:26:17]
wire [31:0] _q_io_deq_bits_address; // @[TilelinkAdapters.scala:26:17]
wire [15:0] _q_io_deq_bits_mask; // @[TilelinkAdapters.scala:26:17]
wire [127:0] _q_io_deq_bits_data; // @[TilelinkAdapters.scala:26:17]
wire _q_io_deq_bits_corrupt; // @[TilelinkAdapters.scala:26:17]
reg [1:0] head_counter; // @[Edges.scala:229:27]
wire head = head_counter == 2'h0; // @[Edges.scala:229:27, :231:25]
reg is_body; // @[TilelinkAdapters.scala:39:24]
wire q_io_deq_ready = io_flit_ready & (is_body | (&_q_io_deq_bits_mask)); // @[TilelinkAdapters.scala:26:17, :39:24, :41:{35,47}, :139:70]
wire io_flit_bits_head_0 = head & ~is_body; // @[Edges.scala:231:25]
wire io_flit_bits_tail_0 = is_body | (&_q_io_deq_bits_mask); // @[TilelinkAdapters.scala:26:17, :39:24, :44:47, :139:70]
wire _GEN = io_flit_ready & _q_io_deq_valid; // @[Decoupled.scala:51:35]
always @(posedge clock) begin // @[TilelinkAdapters.scala:133:7]
if (reset) begin // @[TilelinkAdapters.scala:133:7]
head_counter <= 2'h0; // @[Edges.scala:229:27]
is_body <= 1'h0; // @[TilelinkAdapters.scala:39:24, :133:7]
end
else begin // @[TilelinkAdapters.scala:133:7]
if (q_io_deq_ready & _q_io_deq_valid) // @[Decoupled.scala:51:35]
head_counter <= head ? 2'h0 : head_counter - 2'h1; // @[Edges.scala:229:27, :230:28, :231:25, :236:21]
is_body <= ~(_GEN & io_flit_bits_tail_0) & (_GEN & io_flit_bits_head_0 | is_body); // @[Decoupled.scala:51:35]
end
always @(posedge) |
Generate the Verilog code corresponding to the following Chisel files.
File MSHR.scala:
/*
* Copyright 2019 SiFive, Inc.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You should have received a copy of LICENSE.Apache2 along with
* this software. If not, you may obtain a copy at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
package sifive.blocks.inclusivecache
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceInfo
import freechips.rocketchip.tilelink._
import TLPermissions._
import TLMessages._
import MetaData._
import chisel3.PrintableHelper
import chisel3.experimental.dataview._
class ScheduleRequest(params: InclusiveCacheParameters) extends InclusiveCacheBundle(params)
{
val a = Valid(new SourceARequest(params))
val b = Valid(new SourceBRequest(params))
val c = Valid(new SourceCRequest(params))
val d = Valid(new SourceDRequest(params))
val e = Valid(new SourceERequest(params))
val x = Valid(new SourceXRequest(params))
val dir = Valid(new DirectoryWrite(params))
val reload = Bool() // get next request via allocate (if any)
}
class MSHRStatus(params: InclusiveCacheParameters) extends InclusiveCacheBundle(params)
{
val set = UInt(params.setBits.W)
val tag = UInt(params.tagBits.W)
val way = UInt(params.wayBits.W)
val blockB = Bool()
val nestB = Bool()
val blockC = Bool()
val nestC = Bool()
}
class NestedWriteback(params: InclusiveCacheParameters) extends InclusiveCacheBundle(params)
{
val set = UInt(params.setBits.W)
val tag = UInt(params.tagBits.W)
val b_toN = Bool() // nested Probes may unhit us
val b_toB = Bool() // nested Probes may demote us
val b_clr_dirty = Bool() // nested Probes clear dirty
val c_set_dirty = Bool() // nested Releases MAY set dirty
}
sealed trait CacheState
{
val code = CacheState.index.U
CacheState.index = CacheState.index + 1
}
object CacheState
{
var index = 0
}
case object S_INVALID extends CacheState
case object S_BRANCH extends CacheState
case object S_BRANCH_C extends CacheState
case object S_TIP extends CacheState
case object S_TIP_C extends CacheState
case object S_TIP_CD extends CacheState
case object S_TIP_D extends CacheState
case object S_TRUNK_C extends CacheState
case object S_TRUNK_CD extends CacheState
class MSHR(params: InclusiveCacheParameters) extends Module
{
val io = IO(new Bundle {
val allocate = Flipped(Valid(new AllocateRequest(params))) // refills MSHR for next cycle
val directory = Flipped(Valid(new DirectoryResult(params))) // triggers schedule setup
val status = Valid(new MSHRStatus(params))
val schedule = Decoupled(new ScheduleRequest(params))
val sinkc = Flipped(Valid(new SinkCResponse(params)))
val sinkd = Flipped(Valid(new SinkDResponse(params)))
val sinke = Flipped(Valid(new SinkEResponse(params)))
val nestedwb = Flipped(new NestedWriteback(params))
})
val request_valid = RegInit(false.B)
val request = Reg(new FullRequest(params))
val meta_valid = RegInit(false.B)
val meta = Reg(new DirectoryResult(params))
// Define which states are valid
when (meta_valid) {
when (meta.state === INVALID) {
assert (!meta.clients.orR)
assert (!meta.dirty)
}
when (meta.state === BRANCH) {
assert (!meta.dirty)
}
when (meta.state === TRUNK) {
assert (meta.clients.orR)
assert ((meta.clients & (meta.clients - 1.U)) === 0.U) // at most one
}
when (meta.state === TIP) {
// noop
}
}
// Completed transitions (s_ = scheduled), (w_ = waiting)
val s_rprobe = RegInit(true.B) // B
val w_rprobeackfirst = RegInit(true.B)
val w_rprobeacklast = RegInit(true.B)
val s_release = RegInit(true.B) // CW w_rprobeackfirst
val w_releaseack = RegInit(true.B)
val s_pprobe = RegInit(true.B) // B
val s_acquire = RegInit(true.B) // A s_release, s_pprobe [1]
val s_flush = RegInit(true.B) // X w_releaseack
val w_grantfirst = RegInit(true.B)
val w_grantlast = RegInit(true.B)
val w_grant = RegInit(true.B) // first | last depending on wormhole
val w_pprobeackfirst = RegInit(true.B)
val w_pprobeacklast = RegInit(true.B)
val w_pprobeack = RegInit(true.B) // first | last depending on wormhole
val s_probeack = RegInit(true.B) // C w_pprobeackfirst (mutually exclusive with next two s_*)
val s_grantack = RegInit(true.B) // E w_grantfirst ... CAN require both outE&inD to service outD
val s_execute = RegInit(true.B) // D w_pprobeack, w_grant
val w_grantack = RegInit(true.B)
val s_writeback = RegInit(true.B) // W w_*
// [1]: We cannot issue outer Acquire while holding blockB (=> outA can stall)
// However, inB and outC are higher priority than outB, so s_release and s_pprobe
// may be safely issued while blockB. Thus we must NOT try to schedule the
// potentially stuck s_acquire with either of them (scheduler is all or none).
// Meta-data that we discover underway
val sink = Reg(UInt(params.outer.bundle.sinkBits.W))
val gotT = Reg(Bool())
val bad_grant = Reg(Bool())
val probes_done = Reg(UInt(params.clientBits.W))
val probes_toN = Reg(UInt(params.clientBits.W))
val probes_noT = Reg(Bool())
// When a nested transaction completes, update our meta data
when (meta_valid && meta.state =/= INVALID &&
io.nestedwb.set === request.set && io.nestedwb.tag === meta.tag) {
when (io.nestedwb.b_clr_dirty) { meta.dirty := false.B }
when (io.nestedwb.c_set_dirty) { meta.dirty := true.B }
when (io.nestedwb.b_toB) { meta.state := BRANCH }
when (io.nestedwb.b_toN) { meta.hit := false.B }
}
// Scheduler status
io.status.valid := request_valid
io.status.bits.set := request.set
io.status.bits.tag := request.tag
io.status.bits.way := meta.way
io.status.bits.blockB := !meta_valid || ((!w_releaseack || !w_rprobeacklast || !w_pprobeacklast) && !w_grantfirst)
io.status.bits.nestB := meta_valid && w_releaseack && w_rprobeacklast && w_pprobeacklast && !w_grantfirst
// The above rules ensure we will block and not nest an outer probe while still doing our
// own inner probes. Thus every probe wakes exactly one MSHR.
io.status.bits.blockC := !meta_valid
io.status.bits.nestC := meta_valid && (!w_rprobeackfirst || !w_pprobeackfirst || !w_grantfirst)
// The w_grantfirst in nestC is necessary to deal with:
// acquire waiting for grant, inner release gets queued, outer probe -> inner probe -> deadlock
// ... this is possible because the release+probe can be for same set, but different tag
// We can only demand: block, nest, or queue
assert (!io.status.bits.nestB || !io.status.bits.blockB)
assert (!io.status.bits.nestC || !io.status.bits.blockC)
// Scheduler requests
val no_wait = w_rprobeacklast && w_releaseack && w_grantlast && w_pprobeacklast && w_grantack
io.schedule.bits.a.valid := !s_acquire && s_release && s_pprobe
io.schedule.bits.b.valid := !s_rprobe || !s_pprobe
io.schedule.bits.c.valid := (!s_release && w_rprobeackfirst) || (!s_probeack && w_pprobeackfirst)
io.schedule.bits.d.valid := !s_execute && w_pprobeack && w_grant
io.schedule.bits.e.valid := !s_grantack && w_grantfirst
io.schedule.bits.x.valid := !s_flush && w_releaseack
io.schedule.bits.dir.valid := (!s_release && w_rprobeackfirst) || (!s_writeback && no_wait)
io.schedule.bits.reload := no_wait
io.schedule.valid := io.schedule.bits.a.valid || io.schedule.bits.b.valid || io.schedule.bits.c.valid ||
io.schedule.bits.d.valid || io.schedule.bits.e.valid || io.schedule.bits.x.valid ||
io.schedule.bits.dir.valid
// Schedule completions
when (io.schedule.ready) {
s_rprobe := true.B
when (w_rprobeackfirst) { s_release := true.B }
s_pprobe := true.B
when (s_release && s_pprobe) { s_acquire := true.B }
when (w_releaseack) { s_flush := true.B }
when (w_pprobeackfirst) { s_probeack := true.B }
when (w_grantfirst) { s_grantack := true.B }
when (w_pprobeack && w_grant) { s_execute := true.B }
when (no_wait) { s_writeback := true.B }
// Await the next operation
when (no_wait) {
request_valid := false.B
meta_valid := false.B
}
}
// Resulting meta-data
val final_meta_writeback = WireInit(meta)
val req_clientBit = params.clientBit(request.source)
val req_needT = needT(request.opcode, request.param)
val req_acquire = request.opcode === AcquireBlock || request.opcode === AcquirePerm
val meta_no_clients = !meta.clients.orR
val req_promoteT = req_acquire && Mux(meta.hit, meta_no_clients && meta.state === TIP, gotT)
when (request.prio(2) && (!params.firstLevel).B) { // always a hit
final_meta_writeback.dirty := meta.dirty || request.opcode(0)
final_meta_writeback.state := Mux(request.param =/= TtoT && meta.state === TRUNK, TIP, meta.state)
final_meta_writeback.clients := meta.clients & ~Mux(isToN(request.param), req_clientBit, 0.U)
final_meta_writeback.hit := true.B // chained requests are hits
} .elsewhen (request.control && params.control.B) { // request.prio(0)
when (meta.hit) {
final_meta_writeback.dirty := false.B
final_meta_writeback.state := INVALID
final_meta_writeback.clients := meta.clients & ~probes_toN
}
final_meta_writeback.hit := false.B
} .otherwise {
final_meta_writeback.dirty := (meta.hit && meta.dirty) || !request.opcode(2)
final_meta_writeback.state := Mux(req_needT,
Mux(req_acquire, TRUNK, TIP),
Mux(!meta.hit, Mux(gotT, Mux(req_acquire, TRUNK, TIP), BRANCH),
MuxLookup(meta.state, 0.U(2.W))(Seq(
INVALID -> BRANCH,
BRANCH -> BRANCH,
TRUNK -> TIP,
TIP -> Mux(meta_no_clients && req_acquire, TRUNK, TIP)))))
final_meta_writeback.clients := Mux(meta.hit, meta.clients & ~probes_toN, 0.U) |
Mux(req_acquire, req_clientBit, 0.U)
final_meta_writeback.tag := request.tag
final_meta_writeback.hit := true.B
}
when (bad_grant) {
when (meta.hit) {
// upgrade failed (B -> T)
assert (!meta_valid || meta.state === BRANCH)
final_meta_writeback.hit := true.B
final_meta_writeback.dirty := false.B
final_meta_writeback.state := BRANCH
final_meta_writeback.clients := meta.clients & ~probes_toN
} .otherwise {
// failed N -> (T or B)
final_meta_writeback.hit := false.B
final_meta_writeback.dirty := false.B
final_meta_writeback.state := INVALID
final_meta_writeback.clients := 0.U
}
}
val invalid = Wire(new DirectoryEntry(params))
invalid.dirty := false.B
invalid.state := INVALID
invalid.clients := 0.U
invalid.tag := 0.U
// Just because a client says BtoT, by the time we process the request he may be N.
// Therefore, we must consult our own meta-data state to confirm he owns the line still.
val honour_BtoT = meta.hit && (meta.clients & req_clientBit).orR
// The client asking us to act is proof they don't have permissions.
val excluded_client = Mux(meta.hit && request.prio(0) && skipProbeN(request.opcode, params.cache.hintsSkipProbe), req_clientBit, 0.U)
io.schedule.bits.a.bits.tag := request.tag
io.schedule.bits.a.bits.set := request.set
io.schedule.bits.a.bits.param := Mux(req_needT, Mux(meta.hit, BtoT, NtoT), NtoB)
io.schedule.bits.a.bits.block := request.size =/= log2Ceil(params.cache.blockBytes).U ||
!(request.opcode === PutFullData || request.opcode === AcquirePerm)
io.schedule.bits.a.bits.source := 0.U
io.schedule.bits.b.bits.param := Mux(!s_rprobe, toN, Mux(request.prio(1), request.param, Mux(req_needT, toN, toB)))
io.schedule.bits.b.bits.tag := Mux(!s_rprobe, meta.tag, request.tag)
io.schedule.bits.b.bits.set := request.set
io.schedule.bits.b.bits.clients := meta.clients & ~excluded_client
io.schedule.bits.c.bits.opcode := Mux(meta.dirty, ReleaseData, Release)
io.schedule.bits.c.bits.param := Mux(meta.state === BRANCH, BtoN, TtoN)
io.schedule.bits.c.bits.source := 0.U
io.schedule.bits.c.bits.tag := meta.tag
io.schedule.bits.c.bits.set := request.set
io.schedule.bits.c.bits.way := meta.way
io.schedule.bits.c.bits.dirty := meta.dirty
io.schedule.bits.d.bits.viewAsSupertype(chiselTypeOf(request)) := request
io.schedule.bits.d.bits.param := Mux(!req_acquire, request.param,
MuxLookup(request.param, request.param)(Seq(
NtoB -> Mux(req_promoteT, NtoT, NtoB),
BtoT -> Mux(honour_BtoT, BtoT, NtoT),
NtoT -> NtoT)))
io.schedule.bits.d.bits.sink := 0.U
io.schedule.bits.d.bits.way := meta.way
io.schedule.bits.d.bits.bad := bad_grant
io.schedule.bits.e.bits.sink := sink
io.schedule.bits.x.bits.fail := false.B
io.schedule.bits.dir.bits.set := request.set
io.schedule.bits.dir.bits.way := meta.way
io.schedule.bits.dir.bits.data := Mux(!s_release, invalid, WireInit(new DirectoryEntry(params), init = final_meta_writeback))
// Coverage of state transitions
def cacheState(entry: DirectoryEntry, hit: Bool) = {
val out = WireDefault(0.U)
val c = entry.clients.orR
val d = entry.dirty
switch (entry.state) {
is (BRANCH) { out := Mux(c, S_BRANCH_C.code, S_BRANCH.code) }
is (TRUNK) { out := Mux(d, S_TRUNK_CD.code, S_TRUNK_C.code) }
is (TIP) { out := Mux(c, Mux(d, S_TIP_CD.code, S_TIP_C.code), Mux(d, S_TIP_D.code, S_TIP.code)) }
is (INVALID) { out := S_INVALID.code }
}
when (!hit) { out := S_INVALID.code }
out
}
val p = !params.lastLevel // can be probed
val c = !params.firstLevel // can be acquired
val m = params.inner.client.clients.exists(!_.supports.probe) // can be written (or read)
val r = params.outer.manager.managers.exists(!_.alwaysGrantsT) // read-only devices exist
val f = params.control // flush control register exists
val cfg = (p, c, m, r, f)
val b = r || p // can reach branch state (via probe downgrade or read-only device)
// The cache must be used for something or we would not be here
require(c || m)
val evict = cacheState(meta, !meta.hit)
val before = cacheState(meta, meta.hit)
val after = cacheState(final_meta_writeback, true.B)
def eviction(from: CacheState, cover: Boolean)(implicit sourceInfo: SourceInfo) {
if (cover) {
params.ccover(evict === from.code, s"MSHR_${from}_EVICT", s"State transition from ${from} to evicted ${cfg}")
} else {
assert(!(evict === from.code), cf"State transition from ${from} to evicted should be impossible ${cfg}")
}
if (cover && f) {
params.ccover(before === from.code, s"MSHR_${from}_FLUSH", s"State transition from ${from} to flushed ${cfg}")
} else {
assert(!(before === from.code), cf"State transition from ${from} to flushed should be impossible ${cfg}")
}
}
def transition(from: CacheState, to: CacheState, cover: Boolean)(implicit sourceInfo: SourceInfo) {
if (cover) {
params.ccover(before === from.code && after === to.code, s"MSHR_${from}_${to}", s"State transition from ${from} to ${to} ${cfg}")
} else {
assert(!(before === from.code && after === to.code), cf"State transition from ${from} to ${to} should be impossible ${cfg}")
}
}
when ((!s_release && w_rprobeackfirst) && io.schedule.ready) {
eviction(S_BRANCH, b) // MMIO read to read-only device
eviction(S_BRANCH_C, b && c) // you need children to become C
eviction(S_TIP, true) // MMIO read || clean release can lead to this state
eviction(S_TIP_C, c) // needs two clients || client + mmio || downgrading client
eviction(S_TIP_CD, c) // needs two clients || client + mmio || downgrading client
eviction(S_TIP_D, true) // MMIO write || dirty release lead here
eviction(S_TRUNK_C, c) // acquire for write
eviction(S_TRUNK_CD, c) // dirty release then reacquire
}
when ((!s_writeback && no_wait) && io.schedule.ready) {
transition(S_INVALID, S_BRANCH, b && m) // only MMIO can bring us to BRANCH state
transition(S_INVALID, S_BRANCH_C, b && c) // C state is only possible if there are inner caches
transition(S_INVALID, S_TIP, m) // MMIO read
transition(S_INVALID, S_TIP_C, false) // we would go S_TRUNK_C instead
transition(S_INVALID, S_TIP_CD, false) // acquire does not cause dirty immediately
transition(S_INVALID, S_TIP_D, m) // MMIO write
transition(S_INVALID, S_TRUNK_C, c) // acquire
transition(S_INVALID, S_TRUNK_CD, false) // acquire does not cause dirty immediately
transition(S_BRANCH, S_INVALID, b && p) // probe can do this (flushes run as evictions)
transition(S_BRANCH, S_BRANCH_C, b && c) // acquire
transition(S_BRANCH, S_TIP, b && m) // prefetch write
transition(S_BRANCH, S_TIP_C, false) // we would go S_TRUNK_C instead
transition(S_BRANCH, S_TIP_CD, false) // acquire does not cause dirty immediately
transition(S_BRANCH, S_TIP_D, b && m) // MMIO write
transition(S_BRANCH, S_TRUNK_C, b && c) // acquire
transition(S_BRANCH, S_TRUNK_CD, false) // acquire does not cause dirty immediately
transition(S_BRANCH_C, S_INVALID, b && c && p)
transition(S_BRANCH_C, S_BRANCH, b && c) // clean release (optional)
transition(S_BRANCH_C, S_TIP, b && c && m) // prefetch write
transition(S_BRANCH_C, S_TIP_C, false) // we would go S_TRUNK_C instead
transition(S_BRANCH_C, S_TIP_D, b && c && m) // MMIO write
transition(S_BRANCH_C, S_TIP_CD, false) // going dirty means we must shoot down clients
transition(S_BRANCH_C, S_TRUNK_C, b && c) // acquire
transition(S_BRANCH_C, S_TRUNK_CD, false) // acquire does not cause dirty immediately
transition(S_TIP, S_INVALID, p)
transition(S_TIP, S_BRANCH, p) // losing TIP only possible via probe
transition(S_TIP, S_BRANCH_C, false) // we would go S_TRUNK_C instead
transition(S_TIP, S_TIP_C, false) // we would go S_TRUNK_C instead
transition(S_TIP, S_TIP_D, m) // direct dirty only via MMIO write
transition(S_TIP, S_TIP_CD, false) // acquire does not make us dirty immediately
transition(S_TIP, S_TRUNK_C, c) // acquire
transition(S_TIP, S_TRUNK_CD, false) // acquire does not make us dirty immediately
transition(S_TIP_C, S_INVALID, c && p)
transition(S_TIP_C, S_BRANCH, c && p) // losing TIP only possible via probe
transition(S_TIP_C, S_BRANCH_C, c && p) // losing TIP only possible via probe
transition(S_TIP_C, S_TIP, c) // probed while MMIO read || clean release (optional)
transition(S_TIP_C, S_TIP_D, c && m) // direct dirty only via MMIO write
transition(S_TIP_C, S_TIP_CD, false) // going dirty means we must shoot down clients
transition(S_TIP_C, S_TRUNK_C, c) // acquire
transition(S_TIP_C, S_TRUNK_CD, false) // acquire does not make us immediately dirty
transition(S_TIP_D, S_INVALID, p)
transition(S_TIP_D, S_BRANCH, p) // losing D is only possible via probe
transition(S_TIP_D, S_BRANCH_C, p && c) // probed while acquire shared
transition(S_TIP_D, S_TIP, p) // probed while MMIO read || outer probe.toT (optional)
transition(S_TIP_D, S_TIP_C, false) // we would go S_TRUNK_C instead
transition(S_TIP_D, S_TIP_CD, false) // we would go S_TRUNK_CD instead
transition(S_TIP_D, S_TRUNK_C, p && c) // probed while acquired
transition(S_TIP_D, S_TRUNK_CD, c) // acquire
transition(S_TIP_CD, S_INVALID, c && p)
transition(S_TIP_CD, S_BRANCH, c && p) // losing D is only possible via probe
transition(S_TIP_CD, S_BRANCH_C, c && p) // losing D is only possible via probe
transition(S_TIP_CD, S_TIP, c && p) // probed while MMIO read || outer probe.toT (optional)
transition(S_TIP_CD, S_TIP_C, false) // we would go S_TRUNK_C instead
transition(S_TIP_CD, S_TIP_D, c) // MMIO write || clean release (optional)
transition(S_TIP_CD, S_TRUNK_C, c && p) // probed while acquire
transition(S_TIP_CD, S_TRUNK_CD, c) // acquire
transition(S_TRUNK_C, S_INVALID, c && p)
transition(S_TRUNK_C, S_BRANCH, c && p) // losing TIP only possible via probe
transition(S_TRUNK_C, S_BRANCH_C, c && p) // losing TIP only possible via probe
transition(S_TRUNK_C, S_TIP, c) // MMIO read || clean release (optional)
transition(S_TRUNK_C, S_TIP_C, c) // bounce shared
transition(S_TRUNK_C, S_TIP_D, c) // dirty release
transition(S_TRUNK_C, S_TIP_CD, c) // dirty bounce shared
transition(S_TRUNK_C, S_TRUNK_CD, c) // dirty bounce
transition(S_TRUNK_CD, S_INVALID, c && p)
transition(S_TRUNK_CD, S_BRANCH, c && p) // losing D only possible via probe
transition(S_TRUNK_CD, S_BRANCH_C, c && p) // losing D only possible via probe
transition(S_TRUNK_CD, S_TIP, c && p) // probed while MMIO read || outer probe.toT (optional)
transition(S_TRUNK_CD, S_TIP_C, false) // we would go S_TRUNK_C instead
transition(S_TRUNK_CD, S_TIP_D, c) // dirty release
transition(S_TRUNK_CD, S_TIP_CD, c) // bounce shared
transition(S_TRUNK_CD, S_TRUNK_C, c && p) // probed while acquire
}
// Handle response messages
val probe_bit = params.clientBit(io.sinkc.bits.source)
val last_probe = (probes_done | probe_bit) === (meta.clients & ~excluded_client)
val probe_toN = isToN(io.sinkc.bits.param)
if (!params.firstLevel) when (io.sinkc.valid) {
params.ccover( probe_toN && io.schedule.bits.b.bits.param === toB, "MSHR_PROBE_FULL", "Client downgraded to N when asked only to do B")
params.ccover(!probe_toN && io.schedule.bits.b.bits.param === toB, "MSHR_PROBE_HALF", "Client downgraded to B when asked only to do B")
// Caution: the probe matches us only in set.
// We would never allow an outer probe to nest until both w_[rp]probeack complete, so
// it is safe to just unguardedly update the probe FSM.
probes_done := probes_done | probe_bit
probes_toN := probes_toN | Mux(probe_toN, probe_bit, 0.U)
probes_noT := probes_noT || io.sinkc.bits.param =/= TtoT
w_rprobeackfirst := w_rprobeackfirst || last_probe
w_rprobeacklast := w_rprobeacklast || (last_probe && io.sinkc.bits.last)
w_pprobeackfirst := w_pprobeackfirst || last_probe
w_pprobeacklast := w_pprobeacklast || (last_probe && io.sinkc.bits.last)
// Allow wormhole routing from sinkC if the first request beat has offset 0
val set_pprobeack = last_probe && (io.sinkc.bits.last || request.offset === 0.U)
w_pprobeack := w_pprobeack || set_pprobeack
params.ccover(!set_pprobeack && w_rprobeackfirst, "MSHR_PROBE_SERIAL", "Sequential routing of probe response data")
params.ccover( set_pprobeack && w_rprobeackfirst, "MSHR_PROBE_WORMHOLE", "Wormhole routing of probe response data")
// However, meta-data updates need to be done more cautiously
when (meta.state =/= INVALID && io.sinkc.bits.tag === meta.tag && io.sinkc.bits.data) { meta.dirty := true.B } // !!!
}
when (io.sinkd.valid) {
when (io.sinkd.bits.opcode === Grant || io.sinkd.bits.opcode === GrantData) {
sink := io.sinkd.bits.sink
w_grantfirst := true.B
w_grantlast := io.sinkd.bits.last
// Record if we need to prevent taking ownership
bad_grant := io.sinkd.bits.denied
// Allow wormhole routing for requests whose first beat has offset 0
w_grant := request.offset === 0.U || io.sinkd.bits.last
params.ccover(io.sinkd.bits.opcode === GrantData && request.offset === 0.U, "MSHR_GRANT_WORMHOLE", "Wormhole routing of grant response data")
params.ccover(io.sinkd.bits.opcode === GrantData && request.offset =/= 0.U, "MSHR_GRANT_SERIAL", "Sequential routing of grant response data")
gotT := io.sinkd.bits.param === toT
}
.elsewhen (io.sinkd.bits.opcode === ReleaseAck) {
w_releaseack := true.B
}
}
when (io.sinke.valid) {
w_grantack := true.B
}
// Bootstrap new requests
val allocate_as_full = WireInit(new FullRequest(params), init = io.allocate.bits)
val new_meta = Mux(io.allocate.valid && io.allocate.bits.repeat, final_meta_writeback, io.directory.bits)
val new_request = Mux(io.allocate.valid, allocate_as_full, request)
val new_needT = needT(new_request.opcode, new_request.param)
val new_clientBit = params.clientBit(new_request.source)
val new_skipProbe = Mux(skipProbeN(new_request.opcode, params.cache.hintsSkipProbe), new_clientBit, 0.U)
val prior = cacheState(final_meta_writeback, true.B)
def bypass(from: CacheState, cover: Boolean)(implicit sourceInfo: SourceInfo) {
if (cover) {
params.ccover(prior === from.code, s"MSHR_${from}_BYPASS", s"State bypass transition from ${from} ${cfg}")
} else {
assert(!(prior === from.code), cf"State bypass from ${from} should be impossible ${cfg}")
}
}
when (io.allocate.valid && io.allocate.bits.repeat) {
bypass(S_INVALID, f || p) // Can lose permissions (probe/flush)
bypass(S_BRANCH, b) // MMIO read to read-only device
bypass(S_BRANCH_C, b && c) // you need children to become C
bypass(S_TIP, true) // MMIO read || clean release can lead to this state
bypass(S_TIP_C, c) // needs two clients || client + mmio || downgrading client
bypass(S_TIP_CD, c) // needs two clients || client + mmio || downgrading client
bypass(S_TIP_D, true) // MMIO write || dirty release lead here
bypass(S_TRUNK_C, c) // acquire for write
bypass(S_TRUNK_CD, c) // dirty release then reacquire
}
when (io.allocate.valid) {
assert (!request_valid || (no_wait && io.schedule.fire))
request_valid := true.B
request := io.allocate.bits
}
// Create execution plan
when (io.directory.valid || (io.allocate.valid && io.allocate.bits.repeat)) {
meta_valid := true.B
meta := new_meta
probes_done := 0.U
probes_toN := 0.U
probes_noT := false.B
gotT := false.B
bad_grant := false.B
// These should already be either true or turning true
// We clear them here explicitly to simplify the mux tree
s_rprobe := true.B
w_rprobeackfirst := true.B
w_rprobeacklast := true.B
s_release := true.B
w_releaseack := true.B
s_pprobe := true.B
s_acquire := true.B
s_flush := true.B
w_grantfirst := true.B
w_grantlast := true.B
w_grant := true.B
w_pprobeackfirst := true.B
w_pprobeacklast := true.B
w_pprobeack := true.B
s_probeack := true.B
s_grantack := true.B
s_execute := true.B
w_grantack := true.B
s_writeback := true.B
// For C channel requests (ie: Release[Data])
when (new_request.prio(2) && (!params.firstLevel).B) {
s_execute := false.B
// Do we need to go dirty?
when (new_request.opcode(0) && !new_meta.dirty) {
s_writeback := false.B
}
// Does our state change?
when (isToB(new_request.param) && new_meta.state === TRUNK) {
s_writeback := false.B
}
// Do our clients change?
when (isToN(new_request.param) && (new_meta.clients & new_clientBit) =/= 0.U) {
s_writeback := false.B
}
assert (new_meta.hit)
}
// For X channel requests (ie: flush)
.elsewhen (new_request.control && params.control.B) { // new_request.prio(0)
s_flush := false.B
// Do we need to actually do something?
when (new_meta.hit) {
s_release := false.B
w_releaseack := false.B
// Do we need to shoot-down inner caches?
when ((!params.firstLevel).B && (new_meta.clients =/= 0.U)) {
s_rprobe := false.B
w_rprobeackfirst := false.B
w_rprobeacklast := false.B
}
}
}
// For A channel requests
.otherwise { // new_request.prio(0) && !new_request.control
s_execute := false.B
// Do we need an eviction?
when (!new_meta.hit && new_meta.state =/= INVALID) {
s_release := false.B
w_releaseack := false.B
// Do we need to shoot-down inner caches?
when ((!params.firstLevel).B & (new_meta.clients =/= 0.U)) {
s_rprobe := false.B
w_rprobeackfirst := false.B
w_rprobeacklast := false.B
}
}
// Do we need an acquire?
when (!new_meta.hit || (new_meta.state === BRANCH && new_needT)) {
s_acquire := false.B
w_grantfirst := false.B
w_grantlast := false.B
w_grant := false.B
s_grantack := false.B
s_writeback := false.B
}
// Do we need a probe?
when ((!params.firstLevel).B && (new_meta.hit &&
(new_needT || new_meta.state === TRUNK) &&
(new_meta.clients & ~new_skipProbe) =/= 0.U)) {
s_pprobe := false.B
w_pprobeackfirst := false.B
w_pprobeacklast := false.B
w_pprobeack := false.B
s_writeback := false.B
}
// Do we need a grantack?
when (new_request.opcode === AcquireBlock || new_request.opcode === AcquirePerm) {
w_grantack := false.B
s_writeback := false.B
}
// Becomes dirty?
when (!new_request.opcode(2) && new_meta.hit && !new_meta.dirty) {
s_writeback := false.B
}
}
}
}
File Parameters.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.diplomacy
import chisel3._
import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor}
import freechips.rocketchip.util.ShiftQueue
/** Options for describing the attributes of memory regions */
object RegionType {
// Define the 'more relaxed than' ordering
val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS)
sealed trait T extends Ordered[T] {
def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this)
}
case object CACHED extends T // an intermediate agent may have cached a copy of the region for you
case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided
case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible
case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached
case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects
case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed
case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively
}
// A non-empty half-open range; [start, end)
case class IdRange(start: Int, end: Int) extends Ordered[IdRange]
{
require (start >= 0, s"Ids cannot be negative, but got: $start.")
require (start <= end, "Id ranges cannot be negative.")
def compare(x: IdRange) = {
val primary = (this.start - x.start).signum
val secondary = (x.end - this.end).signum
if (primary != 0) primary else secondary
}
def overlaps(x: IdRange) = start < x.end && x.start < end
def contains(x: IdRange) = start <= x.start && x.end <= end
def contains(x: Int) = start <= x && x < end
def contains(x: UInt) =
if (size == 0) {
false.B
} else if (size == 1) { // simple comparison
x === start.U
} else {
// find index of largest different bit
val largestDeltaBit = log2Floor(start ^ (end-1))
val smallestCommonBit = largestDeltaBit + 1 // may not exist in x
val uncommonMask = (1 << smallestCommonBit) - 1
val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0)
// the prefix must match exactly (note: may shift ALL bits away)
(x >> smallestCommonBit) === (start >> smallestCommonBit).U &&
// firrtl constant prop range analysis can eliminate these two:
(start & uncommonMask).U <= uncommonBits &&
uncommonBits <= ((end-1) & uncommonMask).U
}
def shift(x: Int) = IdRange(start+x, end+x)
def size = end - start
def isEmpty = end == start
def range = start until end
}
object IdRange
{
def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else {
val ranges = s.sorted
(ranges.tail zip ranges.init) find { case (a, b) => a overlaps b }
}
}
// An potentially empty inclusive range of 2-powers [min, max] (in bytes)
case class TransferSizes(min: Int, max: Int)
{
def this(x: Int) = this(x, x)
require (min <= max, s"Min transfer $min > max transfer $max")
require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)")
require (max == 0 || isPow2(max), s"TransferSizes must be a power of 2, got: $max")
require (min == 0 || isPow2(min), s"TransferSizes must be a power of 2, got: $min")
require (max == 0 || min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)")
def none = min == 0
def contains(x: Int) = isPow2(x) && min <= x && x <= max
def containsLg(x: Int) = contains(1 << x)
def containsLg(x: UInt) =
if (none) false.B
else if (min == max) { log2Ceil(min).U === x }
else { log2Ceil(min).U <= x && x <= log2Ceil(max).U }
def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max)
def intersect(x: TransferSizes) =
if (x.max < min || max < x.min) TransferSizes.none
else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max))
// Not a union, because the result may contain sizes contained by neither term
// NOT TO BE CONFUSED WITH COVERPOINTS
def mincover(x: TransferSizes) = {
if (none) {
x
} else if (x.none) {
this
} else {
TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max))
}
}
override def toString() = "TransferSizes[%d, %d]".format(min, max)
}
object TransferSizes {
def apply(x: Int) = new TransferSizes(x)
val none = new TransferSizes(0)
def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _)
def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _)
implicit def asBool(x: TransferSizes) = !x.none
}
// AddressSets specify the address space managed by the manager
// Base is the base address, and mask are the bits consumed by the manager
// e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff
// e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ...
case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet]
{
// Forbid misaligned base address (and empty sets)
require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}")
require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous
// We do allow negative mask (=> ignore all high bits)
def contains(x: BigInt) = ((x ^ base) & ~mask) == 0
def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S
// turn x into an address contained in this set
def legalize(x: UInt): UInt = base.U | (mask.U & x)
// overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1)
def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0
// contains iff bitwise: x.mask => mask && contains(x.base)
def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0
// The number of bytes to which the manager must be aligned
def alignment = ((mask + 1) & ~mask)
// Is this a contiguous memory range
def contiguous = alignment == mask+1
def finite = mask >= 0
def max = { require (finite, "Max cannot be calculated on infinite mask"); base | mask }
// Widen the match function to ignore all bits in imask
def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask)
// Return an AddressSet that only contains the addresses both sets contain
def intersect(x: AddressSet): Option[AddressSet] = {
if (!overlaps(x)) {
None
} else {
val r_mask = mask & x.mask
val r_base = base | x.base
Some(AddressSet(r_base, r_mask))
}
}
def subtract(x: AddressSet): Seq[AddressSet] = {
intersect(x) match {
case None => Seq(this)
case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit =>
val nmask = (mask & (bit-1)) | remove.mask
val nbase = (remove.base ^ bit) & ~nmask
AddressSet(nbase, nmask)
}
}
}
// AddressSets have one natural Ordering (the containment order, if contiguous)
def compare(x: AddressSet) = {
val primary = (this.base - x.base).signum // smallest address first
val secondary = (x.mask - this.mask).signum // largest mask first
if (primary != 0) primary else secondary
}
// We always want to see things in hex
override def toString() = {
if (mask >= 0) {
"AddressSet(0x%x, 0x%x)".format(base, mask)
} else {
"AddressSet(0x%x, ~0x%x)".format(base, ~mask)
}
}
def toRanges = {
require (finite, "Ranges cannot be calculated on infinite mask")
val size = alignment
val fragments = mask & ~(size-1)
val bits = bitIndexes(fragments)
(BigInt(0) until (BigInt(1) << bits.size)).map { i =>
val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) }
AddressRange(off, size)
}
}
}
object AddressSet
{
val everything = AddressSet(0, -1)
def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = {
if (size == 0) tail.reverse else {
val maxBaseAlignment = base & (-base) // 0 for infinite (LSB)
val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size
val step =
if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment)
maxSizeAlignment else maxBaseAlignment
misaligned(base+step, size-step, AddressSet(base, step-1) +: tail)
}
}
def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = {
// Pair terms up by ignoring 'bit'
seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) =>
if (seq.size == 1) {
seq.head // singleton -> unaffected
} else {
key.copy(mask = key.mask | bit) // pair - widen mask by bit
}
}.toList
}
def unify(seq: Seq[AddressSet]): Seq[AddressSet] = {
val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _)
AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted
}
def enumerateMask(mask: BigInt): Seq[BigInt] = {
def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] =
if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail)
helper(0, Nil)
}
def enumerateBits(mask: BigInt): Seq[BigInt] = {
def helper(x: BigInt): Seq[BigInt] = {
if (x == 0) {
Nil
} else {
val bit = x & (-x)
bit +: helper(x & ~bit)
}
}
helper(mask)
}
}
case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean)
{
require (depth >= 0, "Buffer depth must be >= 0")
def isDefined = depth > 0
def latency = if (isDefined && !flow) 1 else 0
def apply[T <: Data](x: DecoupledIO[T]) =
if (isDefined) Queue(x, depth, flow=flow, pipe=pipe)
else x
def irrevocable[T <: Data](x: ReadyValidIO[T]) =
if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe)
else x
def sq[T <: Data](x: DecoupledIO[T]) =
if (!isDefined) x else {
val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe))
sq.io.enq <> x
sq.io.deq
}
override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "")
}
object BufferParams
{
implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false)
val default = BufferParams(2)
val none = BufferParams(0)
val flow = BufferParams(1, true, false)
val pipe = BufferParams(1, false, true)
}
case class TriStateValue(value: Boolean, set: Boolean)
{
def update(orig: Boolean) = if (set) value else orig
}
object TriStateValue
{
implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true)
def unset = TriStateValue(false, false)
}
trait DirectedBuffers[T] {
def copyIn(x: BufferParams): T
def copyOut(x: BufferParams): T
def copyInOut(x: BufferParams): T
}
trait IdMapEntry {
def name: String
def from: IdRange
def to: IdRange
def isCache: Boolean
def requestFifo: Boolean
def maxTransactionsInFlight: Option[Int]
def pretty(fmt: String) =
if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5
fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "")
} else {
fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "")
}
}
abstract class IdMap[T <: IdMapEntry] {
protected val fmt: String
val mapping: Seq[T]
def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n")
}
| module MSHR_11( // @[MSHR.scala:84:7]
input clock, // @[MSHR.scala:84:7]
input reset, // @[MSHR.scala:84:7]
input io_allocate_valid, // @[MSHR.scala:86:14]
input io_allocate_bits_prio_2, // @[MSHR.scala:86:14]
input io_allocate_bits_control, // @[MSHR.scala:86:14]
input [2:0] io_allocate_bits_opcode, // @[MSHR.scala:86:14]
input [2:0] io_allocate_bits_param, // @[MSHR.scala:86:14]
input [2:0] io_allocate_bits_size, // @[MSHR.scala:86:14]
input [5:0] io_allocate_bits_source, // @[MSHR.scala:86:14]
input [12:0] io_allocate_bits_tag, // @[MSHR.scala:86:14]
input [5:0] io_allocate_bits_offset, // @[MSHR.scala:86:14]
input [5:0] io_allocate_bits_put, // @[MSHR.scala:86:14]
input [9:0] io_allocate_bits_set, // @[MSHR.scala:86:14]
input io_allocate_bits_repeat, // @[MSHR.scala:86:14]
input io_directory_valid, // @[MSHR.scala:86:14]
input io_directory_bits_dirty, // @[MSHR.scala:86:14]
input [1:0] io_directory_bits_state, // @[MSHR.scala:86:14]
input io_directory_bits_clients, // @[MSHR.scala:86:14]
input [12:0] io_directory_bits_tag, // @[MSHR.scala:86:14]
input io_directory_bits_hit, // @[MSHR.scala:86:14]
input [2:0] io_directory_bits_way, // @[MSHR.scala:86:14]
output io_status_valid, // @[MSHR.scala:86:14]
output [9:0] io_status_bits_set, // @[MSHR.scala:86:14]
output [12:0] io_status_bits_tag, // @[MSHR.scala:86:14]
output [2:0] io_status_bits_way, // @[MSHR.scala:86:14]
output io_status_bits_blockB, // @[MSHR.scala:86:14]
output io_status_bits_nestB, // @[MSHR.scala:86:14]
output io_status_bits_blockC, // @[MSHR.scala:86:14]
output io_status_bits_nestC, // @[MSHR.scala:86:14]
input io_schedule_ready, // @[MSHR.scala:86:14]
output io_schedule_valid, // @[MSHR.scala:86:14]
output io_schedule_bits_a_valid, // @[MSHR.scala:86:14]
output [12:0] io_schedule_bits_a_bits_tag, // @[MSHR.scala:86:14]
output [9:0] io_schedule_bits_a_bits_set, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_a_bits_param, // @[MSHR.scala:86:14]
output io_schedule_bits_a_bits_block, // @[MSHR.scala:86:14]
output io_schedule_bits_b_valid, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_b_bits_param, // @[MSHR.scala:86:14]
output [12:0] io_schedule_bits_b_bits_tag, // @[MSHR.scala:86:14]
output [9:0] io_schedule_bits_b_bits_set, // @[MSHR.scala:86:14]
output io_schedule_bits_b_bits_clients, // @[MSHR.scala:86:14]
output io_schedule_bits_c_valid, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_c_bits_opcode, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_c_bits_param, // @[MSHR.scala:86:14]
output [12:0] io_schedule_bits_c_bits_tag, // @[MSHR.scala:86:14]
output [9:0] io_schedule_bits_c_bits_set, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_c_bits_way, // @[MSHR.scala:86:14]
output io_schedule_bits_c_bits_dirty, // @[MSHR.scala:86:14]
output io_schedule_bits_d_valid, // @[MSHR.scala:86:14]
output io_schedule_bits_d_bits_prio_2, // @[MSHR.scala:86:14]
output io_schedule_bits_d_bits_control, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_d_bits_opcode, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_d_bits_param, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_d_bits_size, // @[MSHR.scala:86:14]
output [5:0] io_schedule_bits_d_bits_source, // @[MSHR.scala:86:14]
output [12:0] io_schedule_bits_d_bits_tag, // @[MSHR.scala:86:14]
output [5:0] io_schedule_bits_d_bits_offset, // @[MSHR.scala:86:14]
output [5:0] io_schedule_bits_d_bits_put, // @[MSHR.scala:86:14]
output [9:0] io_schedule_bits_d_bits_set, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_d_bits_way, // @[MSHR.scala:86:14]
output io_schedule_bits_d_bits_bad, // @[MSHR.scala:86:14]
output io_schedule_bits_e_valid, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_e_bits_sink, // @[MSHR.scala:86:14]
output io_schedule_bits_x_valid, // @[MSHR.scala:86:14]
output io_schedule_bits_dir_valid, // @[MSHR.scala:86:14]
output [9:0] io_schedule_bits_dir_bits_set, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_dir_bits_way, // @[MSHR.scala:86:14]
output io_schedule_bits_dir_bits_data_dirty, // @[MSHR.scala:86:14]
output [1:0] io_schedule_bits_dir_bits_data_state, // @[MSHR.scala:86:14]
output io_schedule_bits_dir_bits_data_clients, // @[MSHR.scala:86:14]
output [12:0] io_schedule_bits_dir_bits_data_tag, // @[MSHR.scala:86:14]
output io_schedule_bits_reload, // @[MSHR.scala:86:14]
input io_sinkc_valid, // @[MSHR.scala:86:14]
input io_sinkc_bits_last, // @[MSHR.scala:86:14]
input [9:0] io_sinkc_bits_set, // @[MSHR.scala:86:14]
input [12:0] io_sinkc_bits_tag, // @[MSHR.scala:86:14]
input [5:0] io_sinkc_bits_source, // @[MSHR.scala:86:14]
input [2:0] io_sinkc_bits_param, // @[MSHR.scala:86:14]
input io_sinkc_bits_data, // @[MSHR.scala:86:14]
input io_sinkd_valid, // @[MSHR.scala:86:14]
input io_sinkd_bits_last, // @[MSHR.scala:86:14]
input [2:0] io_sinkd_bits_opcode, // @[MSHR.scala:86:14]
input [2:0] io_sinkd_bits_param, // @[MSHR.scala:86:14]
input [3:0] io_sinkd_bits_source, // @[MSHR.scala:86:14]
input [2:0] io_sinkd_bits_sink, // @[MSHR.scala:86:14]
input io_sinkd_bits_denied, // @[MSHR.scala:86:14]
input io_sinke_valid, // @[MSHR.scala:86:14]
input [3:0] io_sinke_bits_sink, // @[MSHR.scala:86:14]
input [9:0] io_nestedwb_set, // @[MSHR.scala:86:14]
input [12:0] io_nestedwb_tag, // @[MSHR.scala:86:14]
input io_nestedwb_b_toN, // @[MSHR.scala:86:14]
input io_nestedwb_b_toB, // @[MSHR.scala:86:14]
input io_nestedwb_b_clr_dirty, // @[MSHR.scala:86:14]
input io_nestedwb_c_set_dirty // @[MSHR.scala:86:14]
);
wire [12:0] final_meta_writeback_tag; // @[MSHR.scala:215:38]
wire final_meta_writeback_clients; // @[MSHR.scala:215:38]
wire [1:0] final_meta_writeback_state; // @[MSHR.scala:215:38]
wire final_meta_writeback_dirty; // @[MSHR.scala:215:38]
wire io_allocate_valid_0 = io_allocate_valid; // @[MSHR.scala:84:7]
wire io_allocate_bits_prio_2_0 = io_allocate_bits_prio_2; // @[MSHR.scala:84:7]
wire io_allocate_bits_control_0 = io_allocate_bits_control; // @[MSHR.scala:84:7]
wire [2:0] io_allocate_bits_opcode_0 = io_allocate_bits_opcode; // @[MSHR.scala:84:7]
wire [2:0] io_allocate_bits_param_0 = io_allocate_bits_param; // @[MSHR.scala:84:7]
wire [2:0] io_allocate_bits_size_0 = io_allocate_bits_size; // @[MSHR.scala:84:7]
wire [5:0] io_allocate_bits_source_0 = io_allocate_bits_source; // @[MSHR.scala:84:7]
wire [12:0] io_allocate_bits_tag_0 = io_allocate_bits_tag; // @[MSHR.scala:84:7]
wire [5:0] io_allocate_bits_offset_0 = io_allocate_bits_offset; // @[MSHR.scala:84:7]
wire [5:0] io_allocate_bits_put_0 = io_allocate_bits_put; // @[MSHR.scala:84:7]
wire [9:0] io_allocate_bits_set_0 = io_allocate_bits_set; // @[MSHR.scala:84:7]
wire io_allocate_bits_repeat_0 = io_allocate_bits_repeat; // @[MSHR.scala:84:7]
wire io_directory_valid_0 = io_directory_valid; // @[MSHR.scala:84:7]
wire io_directory_bits_dirty_0 = io_directory_bits_dirty; // @[MSHR.scala:84:7]
wire [1:0] io_directory_bits_state_0 = io_directory_bits_state; // @[MSHR.scala:84:7]
wire io_directory_bits_clients_0 = io_directory_bits_clients; // @[MSHR.scala:84:7]
wire [12:0] io_directory_bits_tag_0 = io_directory_bits_tag; // @[MSHR.scala:84:7]
wire io_directory_bits_hit_0 = io_directory_bits_hit; // @[MSHR.scala:84:7]
wire [2:0] io_directory_bits_way_0 = io_directory_bits_way; // @[MSHR.scala:84:7]
wire io_schedule_ready_0 = io_schedule_ready; // @[MSHR.scala:84:7]
wire io_sinkc_valid_0 = io_sinkc_valid; // @[MSHR.scala:84:7]
wire io_sinkc_bits_last_0 = io_sinkc_bits_last; // @[MSHR.scala:84:7]
wire [9:0] io_sinkc_bits_set_0 = io_sinkc_bits_set; // @[MSHR.scala:84:7]
wire [12:0] io_sinkc_bits_tag_0 = io_sinkc_bits_tag; // @[MSHR.scala:84:7]
wire [5:0] io_sinkc_bits_source_0 = io_sinkc_bits_source; // @[MSHR.scala:84:7]
wire [2:0] io_sinkc_bits_param_0 = io_sinkc_bits_param; // @[MSHR.scala:84:7]
wire io_sinkc_bits_data_0 = io_sinkc_bits_data; // @[MSHR.scala:84:7]
wire io_sinkd_valid_0 = io_sinkd_valid; // @[MSHR.scala:84:7]
wire io_sinkd_bits_last_0 = io_sinkd_bits_last; // @[MSHR.scala:84:7]
wire [2:0] io_sinkd_bits_opcode_0 = io_sinkd_bits_opcode; // @[MSHR.scala:84:7]
wire [2:0] io_sinkd_bits_param_0 = io_sinkd_bits_param; // @[MSHR.scala:84:7]
wire [3:0] io_sinkd_bits_source_0 = io_sinkd_bits_source; // @[MSHR.scala:84:7]
wire [2:0] io_sinkd_bits_sink_0 = io_sinkd_bits_sink; // @[MSHR.scala:84:7]
wire io_sinkd_bits_denied_0 = io_sinkd_bits_denied; // @[MSHR.scala:84:7]
wire io_sinke_valid_0 = io_sinke_valid; // @[MSHR.scala:84:7]
wire [3:0] io_sinke_bits_sink_0 = io_sinke_bits_sink; // @[MSHR.scala:84:7]
wire [9:0] io_nestedwb_set_0 = io_nestedwb_set; // @[MSHR.scala:84:7]
wire [12:0] io_nestedwb_tag_0 = io_nestedwb_tag; // @[MSHR.scala:84:7]
wire io_nestedwb_b_toN_0 = io_nestedwb_b_toN; // @[MSHR.scala:84:7]
wire io_nestedwb_b_toB_0 = io_nestedwb_b_toB; // @[MSHR.scala:84:7]
wire io_nestedwb_b_clr_dirty_0 = io_nestedwb_b_clr_dirty; // @[MSHR.scala:84:7]
wire io_nestedwb_c_set_dirty_0 = io_nestedwb_c_set_dirty; // @[MSHR.scala:84:7]
wire io_allocate_bits_prio_0 = 1'h0; // @[MSHR.scala:84:7]
wire io_allocate_bits_prio_1 = 1'h0; // @[MSHR.scala:84:7]
wire io_schedule_bits_d_bits_prio_0 = 1'h0; // @[MSHR.scala:84:7]
wire io_schedule_bits_d_bits_prio_1 = 1'h0; // @[MSHR.scala:84:7]
wire io_schedule_bits_x_bits_fail = 1'h0; // @[MSHR.scala:84:7]
wire _io_schedule_bits_c_valid_T_2 = 1'h0; // @[MSHR.scala:186:68]
wire _io_schedule_bits_c_valid_T_3 = 1'h0; // @[MSHR.scala:186:80]
wire invalid_dirty = 1'h0; // @[MSHR.scala:268:21]
wire invalid_clients = 1'h0; // @[MSHR.scala:268:21]
wire _excluded_client_T = 1'h0; // @[MSHR.scala:279:38]
wire _excluded_client_T_7 = 1'h0; // @[Parameters.scala:279:137]
wire _excluded_client_T_9 = 1'h0; // @[MSHR.scala:279:57]
wire excluded_client = 1'h0; // @[MSHR.scala:279:28]
wire _after_T_4 = 1'h0; // @[MSHR.scala:323:11]
wire allocate_as_full_prio_0 = 1'h0; // @[MSHR.scala:504:34]
wire allocate_as_full_prio_1 = 1'h0; // @[MSHR.scala:504:34]
wire new_request_prio_0 = 1'h0; // @[MSHR.scala:506:24]
wire new_request_prio_1 = 1'h0; // @[MSHR.scala:506:24]
wire _new_skipProbe_T_6 = 1'h0; // @[Parameters.scala:279:137]
wire _prior_T_4 = 1'h0; // @[MSHR.scala:323:11]
wire _req_clientBit_T_2 = 1'h1; // @[Parameters.scala:56:32]
wire _io_schedule_bits_b_bits_clients_T = 1'h1; // @[MSHR.scala:289:53]
wire _probe_bit_T_2 = 1'h1; // @[Parameters.scala:56:32]
wire _last_probe_T_1 = 1'h1; // @[MSHR.scala:459:66]
wire _new_clientBit_T_2 = 1'h1; // @[Parameters.scala:56:32]
wire [3:0] io_schedule_bits_a_bits_source = 4'h0; // @[MSHR.scala:84:7]
wire [3:0] io_schedule_bits_c_bits_source = 4'h0; // @[MSHR.scala:84:7]
wire [3:0] io_schedule_bits_d_bits_sink = 4'h0; // @[MSHR.scala:84:7]
wire [12:0] invalid_tag = 13'h0; // @[MSHR.scala:268:21]
wire [1:0] invalid_state = 2'h0; // @[MSHR.scala:268:21]
wire [1:0] _final_meta_writeback_state_T_11 = 2'h1; // @[MSHR.scala:240:70]
wire allocate_as_full_prio_2 = io_allocate_bits_prio_2_0; // @[MSHR.scala:84:7, :504:34]
wire allocate_as_full_control = io_allocate_bits_control_0; // @[MSHR.scala:84:7, :504:34]
wire [2:0] allocate_as_full_opcode = io_allocate_bits_opcode_0; // @[MSHR.scala:84:7, :504:34]
wire [2:0] allocate_as_full_param = io_allocate_bits_param_0; // @[MSHR.scala:84:7, :504:34]
wire [2:0] allocate_as_full_size = io_allocate_bits_size_0; // @[MSHR.scala:84:7, :504:34]
wire [5:0] allocate_as_full_source = io_allocate_bits_source_0; // @[MSHR.scala:84:7, :504:34]
wire [12:0] allocate_as_full_tag = io_allocate_bits_tag_0; // @[MSHR.scala:84:7, :504:34]
wire [5:0] allocate_as_full_offset = io_allocate_bits_offset_0; // @[MSHR.scala:84:7, :504:34]
wire [5:0] allocate_as_full_put = io_allocate_bits_put_0; // @[MSHR.scala:84:7, :504:34]
wire [9:0] allocate_as_full_set = io_allocate_bits_set_0; // @[MSHR.scala:84:7, :504:34]
wire _io_status_bits_blockB_T_8; // @[MSHR.scala:168:40]
wire _io_status_bits_nestB_T_4; // @[MSHR.scala:169:93]
wire _io_status_bits_blockC_T; // @[MSHR.scala:172:28]
wire _io_status_bits_nestC_T_5; // @[MSHR.scala:173:39]
wire _io_schedule_valid_T_5; // @[MSHR.scala:193:105]
wire _io_schedule_bits_a_valid_T_2; // @[MSHR.scala:184:55]
wire _io_schedule_bits_a_bits_block_T_5; // @[MSHR.scala:283:91]
wire _io_schedule_bits_b_valid_T_2; // @[MSHR.scala:185:41]
wire [2:0] _io_schedule_bits_b_bits_param_T_3; // @[MSHR.scala:286:41]
wire [12:0] _io_schedule_bits_b_bits_tag_T_1; // @[MSHR.scala:287:41]
wire _io_schedule_bits_b_bits_clients_T_1; // @[MSHR.scala:289:51]
wire _io_schedule_bits_c_valid_T_4; // @[MSHR.scala:186:64]
wire [2:0] _io_schedule_bits_c_bits_opcode_T; // @[MSHR.scala:290:41]
wire [2:0] _io_schedule_bits_c_bits_param_T_1; // @[MSHR.scala:291:41]
wire _io_schedule_bits_d_valid_T_2; // @[MSHR.scala:187:57]
wire [2:0] _io_schedule_bits_d_bits_param_T_9; // @[MSHR.scala:298:41]
wire _io_schedule_bits_e_valid_T_1; // @[MSHR.scala:188:43]
wire _io_schedule_bits_x_valid_T_1; // @[MSHR.scala:189:40]
wire _io_schedule_bits_dir_valid_T_4; // @[MSHR.scala:190:66]
wire _io_schedule_bits_dir_bits_data_T_1_dirty; // @[MSHR.scala:310:41]
wire [1:0] _io_schedule_bits_dir_bits_data_T_1_state; // @[MSHR.scala:310:41]
wire _io_schedule_bits_dir_bits_data_T_1_clients; // @[MSHR.scala:310:41]
wire [12:0] _io_schedule_bits_dir_bits_data_T_1_tag; // @[MSHR.scala:310:41]
wire no_wait; // @[MSHR.scala:183:83]
wire [5:0] _probe_bit_uncommonBits_T = io_sinkc_bits_source_0; // @[Parameters.scala:52:29]
wire [9:0] io_status_bits_set_0; // @[MSHR.scala:84:7]
wire [12:0] io_status_bits_tag_0; // @[MSHR.scala:84:7]
wire [2:0] io_status_bits_way_0; // @[MSHR.scala:84:7]
wire io_status_bits_blockB_0; // @[MSHR.scala:84:7]
wire io_status_bits_nestB_0; // @[MSHR.scala:84:7]
wire io_status_bits_blockC_0; // @[MSHR.scala:84:7]
wire io_status_bits_nestC_0; // @[MSHR.scala:84:7]
wire io_status_valid_0; // @[MSHR.scala:84:7]
wire [12:0] io_schedule_bits_a_bits_tag_0; // @[MSHR.scala:84:7]
wire [9:0] io_schedule_bits_a_bits_set_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_a_bits_param_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_a_bits_block_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_a_valid_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_b_bits_param_0; // @[MSHR.scala:84:7]
wire [12:0] io_schedule_bits_b_bits_tag_0; // @[MSHR.scala:84:7]
wire [9:0] io_schedule_bits_b_bits_set_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_b_bits_clients_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_b_valid_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_c_bits_opcode_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_c_bits_param_0; // @[MSHR.scala:84:7]
wire [12:0] io_schedule_bits_c_bits_tag_0; // @[MSHR.scala:84:7]
wire [9:0] io_schedule_bits_c_bits_set_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_c_bits_way_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_c_bits_dirty_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_c_valid_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_d_bits_prio_2_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_d_bits_control_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_d_bits_opcode_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_d_bits_param_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_d_bits_size_0; // @[MSHR.scala:84:7]
wire [5:0] io_schedule_bits_d_bits_source_0; // @[MSHR.scala:84:7]
wire [12:0] io_schedule_bits_d_bits_tag_0; // @[MSHR.scala:84:7]
wire [5:0] io_schedule_bits_d_bits_offset_0; // @[MSHR.scala:84:7]
wire [5:0] io_schedule_bits_d_bits_put_0; // @[MSHR.scala:84:7]
wire [9:0] io_schedule_bits_d_bits_set_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_d_bits_way_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_d_bits_bad_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_d_valid_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_e_bits_sink_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_e_valid_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_x_valid_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_dir_bits_data_dirty_0; // @[MSHR.scala:84:7]
wire [1:0] io_schedule_bits_dir_bits_data_state_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_dir_bits_data_clients_0; // @[MSHR.scala:84:7]
wire [12:0] io_schedule_bits_dir_bits_data_tag_0; // @[MSHR.scala:84:7]
wire [9:0] io_schedule_bits_dir_bits_set_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_dir_bits_way_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_dir_valid_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_reload_0; // @[MSHR.scala:84:7]
wire io_schedule_valid_0; // @[MSHR.scala:84:7]
reg request_valid; // @[MSHR.scala:97:30]
assign io_status_valid_0 = request_valid; // @[MSHR.scala:84:7, :97:30]
reg request_prio_2; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_prio_2_0 = request_prio_2; // @[MSHR.scala:84:7, :98:20]
reg request_control; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_control_0 = request_control; // @[MSHR.scala:84:7, :98:20]
reg [2:0] request_opcode; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_opcode_0 = request_opcode; // @[MSHR.scala:84:7, :98:20]
reg [2:0] request_param; // @[MSHR.scala:98:20]
reg [2:0] request_size; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_size_0 = request_size; // @[MSHR.scala:84:7, :98:20]
reg [5:0] request_source; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_source_0 = request_source; // @[MSHR.scala:84:7, :98:20]
wire [5:0] _req_clientBit_uncommonBits_T = request_source; // @[Parameters.scala:52:29]
reg [12:0] request_tag; // @[MSHR.scala:98:20]
assign io_status_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20]
assign io_schedule_bits_a_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20]
assign io_schedule_bits_d_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20]
reg [5:0] request_offset; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_offset_0 = request_offset; // @[MSHR.scala:84:7, :98:20]
reg [5:0] request_put; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_put_0 = request_put; // @[MSHR.scala:84:7, :98:20]
reg [9:0] request_set; // @[MSHR.scala:98:20]
assign io_status_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20]
assign io_schedule_bits_a_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20]
assign io_schedule_bits_b_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20]
assign io_schedule_bits_c_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20]
assign io_schedule_bits_d_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20]
assign io_schedule_bits_dir_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20]
reg meta_valid; // @[MSHR.scala:99:27]
reg meta_dirty; // @[MSHR.scala:100:17]
assign io_schedule_bits_c_bits_dirty_0 = meta_dirty; // @[MSHR.scala:84:7, :100:17]
reg [1:0] meta_state; // @[MSHR.scala:100:17]
reg meta_clients; // @[MSHR.scala:100:17]
wire _meta_no_clients_T = meta_clients; // @[MSHR.scala:100:17, :220:39]
assign _io_schedule_bits_b_bits_clients_T_1 = meta_clients; // @[MSHR.scala:100:17, :289:51]
wire evict_c = meta_clients; // @[MSHR.scala:100:17, :315:27]
wire before_c = meta_clients; // @[MSHR.scala:100:17, :315:27]
wire _last_probe_T_2 = meta_clients; // @[MSHR.scala:100:17, :459:64]
reg [12:0] meta_tag; // @[MSHR.scala:100:17]
assign io_schedule_bits_c_bits_tag_0 = meta_tag; // @[MSHR.scala:84:7, :100:17]
reg meta_hit; // @[MSHR.scala:100:17]
reg [2:0] meta_way; // @[MSHR.scala:100:17]
assign io_status_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17]
assign io_schedule_bits_c_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17]
assign io_schedule_bits_d_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17]
assign io_schedule_bits_dir_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17]
wire [2:0] final_meta_writeback_way = meta_way; // @[MSHR.scala:100:17, :215:38]
reg s_rprobe; // @[MSHR.scala:121:33]
reg w_rprobeackfirst; // @[MSHR.scala:122:33]
reg w_rprobeacklast; // @[MSHR.scala:123:33]
reg s_release; // @[MSHR.scala:124:33]
reg w_releaseack; // @[MSHR.scala:125:33]
reg s_pprobe; // @[MSHR.scala:126:33]
reg s_acquire; // @[MSHR.scala:127:33]
reg s_flush; // @[MSHR.scala:128:33]
reg w_grantfirst; // @[MSHR.scala:129:33]
reg w_grantlast; // @[MSHR.scala:130:33]
reg w_grant; // @[MSHR.scala:131:33]
reg w_pprobeackfirst; // @[MSHR.scala:132:33]
reg w_pprobeacklast; // @[MSHR.scala:133:33]
reg w_pprobeack; // @[MSHR.scala:134:33]
reg s_grantack; // @[MSHR.scala:136:33]
reg s_execute; // @[MSHR.scala:137:33]
reg w_grantack; // @[MSHR.scala:138:33]
reg s_writeback; // @[MSHR.scala:139:33]
reg [2:0] sink; // @[MSHR.scala:147:17]
assign io_schedule_bits_e_bits_sink_0 = sink; // @[MSHR.scala:84:7, :147:17]
reg gotT; // @[MSHR.scala:148:17]
reg bad_grant; // @[MSHR.scala:149:22]
assign io_schedule_bits_d_bits_bad_0 = bad_grant; // @[MSHR.scala:84:7, :149:22]
reg probes_done; // @[MSHR.scala:150:24]
reg probes_toN; // @[MSHR.scala:151:23]
reg probes_noT; // @[MSHR.scala:152:23]
wire _io_status_bits_blockB_T = ~meta_valid; // @[MSHR.scala:99:27, :168:28]
wire _io_status_bits_blockB_T_1 = ~w_releaseack; // @[MSHR.scala:125:33, :168:45]
wire _io_status_bits_blockB_T_2 = ~w_rprobeacklast; // @[MSHR.scala:123:33, :168:62]
wire _io_status_bits_blockB_T_3 = _io_status_bits_blockB_T_1 | _io_status_bits_blockB_T_2; // @[MSHR.scala:168:{45,59,62}]
wire _io_status_bits_blockB_T_4 = ~w_pprobeacklast; // @[MSHR.scala:133:33, :168:82]
wire _io_status_bits_blockB_T_5 = _io_status_bits_blockB_T_3 | _io_status_bits_blockB_T_4; // @[MSHR.scala:168:{59,79,82}]
wire _io_status_bits_blockB_T_6 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103]
wire _io_status_bits_blockB_T_7 = _io_status_bits_blockB_T_5 & _io_status_bits_blockB_T_6; // @[MSHR.scala:168:{79,100,103}]
assign _io_status_bits_blockB_T_8 = _io_status_bits_blockB_T | _io_status_bits_blockB_T_7; // @[MSHR.scala:168:{28,40,100}]
assign io_status_bits_blockB_0 = _io_status_bits_blockB_T_8; // @[MSHR.scala:84:7, :168:40]
wire _io_status_bits_nestB_T = meta_valid & w_releaseack; // @[MSHR.scala:99:27, :125:33, :169:39]
wire _io_status_bits_nestB_T_1 = _io_status_bits_nestB_T & w_rprobeacklast; // @[MSHR.scala:123:33, :169:{39,55}]
wire _io_status_bits_nestB_T_2 = _io_status_bits_nestB_T_1 & w_pprobeacklast; // @[MSHR.scala:133:33, :169:{55,74}]
wire _io_status_bits_nestB_T_3 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103, :169:96]
assign _io_status_bits_nestB_T_4 = _io_status_bits_nestB_T_2 & _io_status_bits_nestB_T_3; // @[MSHR.scala:169:{74,93,96}]
assign io_status_bits_nestB_0 = _io_status_bits_nestB_T_4; // @[MSHR.scala:84:7, :169:93]
assign _io_status_bits_blockC_T = ~meta_valid; // @[MSHR.scala:99:27, :168:28, :172:28]
assign io_status_bits_blockC_0 = _io_status_bits_blockC_T; // @[MSHR.scala:84:7, :172:28]
wire _io_status_bits_nestC_T = ~w_rprobeackfirst; // @[MSHR.scala:122:33, :173:43]
wire _io_status_bits_nestC_T_1 = ~w_pprobeackfirst; // @[MSHR.scala:132:33, :173:64]
wire _io_status_bits_nestC_T_2 = _io_status_bits_nestC_T | _io_status_bits_nestC_T_1; // @[MSHR.scala:173:{43,61,64}]
wire _io_status_bits_nestC_T_3 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103, :173:85]
wire _io_status_bits_nestC_T_4 = _io_status_bits_nestC_T_2 | _io_status_bits_nestC_T_3; // @[MSHR.scala:173:{61,82,85}]
assign _io_status_bits_nestC_T_5 = meta_valid & _io_status_bits_nestC_T_4; // @[MSHR.scala:99:27, :173:{39,82}]
assign io_status_bits_nestC_0 = _io_status_bits_nestC_T_5; // @[MSHR.scala:84:7, :173:39]
wire _no_wait_T = w_rprobeacklast & w_releaseack; // @[MSHR.scala:123:33, :125:33, :183:33]
wire _no_wait_T_1 = _no_wait_T & w_grantlast; // @[MSHR.scala:130:33, :183:{33,49}]
wire _no_wait_T_2 = _no_wait_T_1 & w_pprobeacklast; // @[MSHR.scala:133:33, :183:{49,64}]
assign no_wait = _no_wait_T_2 & w_grantack; // @[MSHR.scala:138:33, :183:{64,83}]
assign io_schedule_bits_reload_0 = no_wait; // @[MSHR.scala:84:7, :183:83]
wire _io_schedule_bits_a_valid_T = ~s_acquire; // @[MSHR.scala:127:33, :184:31]
wire _io_schedule_bits_a_valid_T_1 = _io_schedule_bits_a_valid_T & s_release; // @[MSHR.scala:124:33, :184:{31,42}]
assign _io_schedule_bits_a_valid_T_2 = _io_schedule_bits_a_valid_T_1 & s_pprobe; // @[MSHR.scala:126:33, :184:{42,55}]
assign io_schedule_bits_a_valid_0 = _io_schedule_bits_a_valid_T_2; // @[MSHR.scala:84:7, :184:55]
wire _io_schedule_bits_b_valid_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31]
wire _io_schedule_bits_b_valid_T_1 = ~s_pprobe; // @[MSHR.scala:126:33, :185:44]
assign _io_schedule_bits_b_valid_T_2 = _io_schedule_bits_b_valid_T | _io_schedule_bits_b_valid_T_1; // @[MSHR.scala:185:{31,41,44}]
assign io_schedule_bits_b_valid_0 = _io_schedule_bits_b_valid_T_2; // @[MSHR.scala:84:7, :185:41]
wire _io_schedule_bits_c_valid_T = ~s_release; // @[MSHR.scala:124:33, :186:32]
wire _io_schedule_bits_c_valid_T_1 = _io_schedule_bits_c_valid_T & w_rprobeackfirst; // @[MSHR.scala:122:33, :186:{32,43}]
assign _io_schedule_bits_c_valid_T_4 = _io_schedule_bits_c_valid_T_1; // @[MSHR.scala:186:{43,64}]
assign io_schedule_bits_c_valid_0 = _io_schedule_bits_c_valid_T_4; // @[MSHR.scala:84:7, :186:64]
wire _io_schedule_bits_d_valid_T = ~s_execute; // @[MSHR.scala:137:33, :187:31]
wire _io_schedule_bits_d_valid_T_1 = _io_schedule_bits_d_valid_T & w_pprobeack; // @[MSHR.scala:134:33, :187:{31,42}]
assign _io_schedule_bits_d_valid_T_2 = _io_schedule_bits_d_valid_T_1 & w_grant; // @[MSHR.scala:131:33, :187:{42,57}]
assign io_schedule_bits_d_valid_0 = _io_schedule_bits_d_valid_T_2; // @[MSHR.scala:84:7, :187:57]
wire _io_schedule_bits_e_valid_T = ~s_grantack; // @[MSHR.scala:136:33, :188:31]
assign _io_schedule_bits_e_valid_T_1 = _io_schedule_bits_e_valid_T & w_grantfirst; // @[MSHR.scala:129:33, :188:{31,43}]
assign io_schedule_bits_e_valid_0 = _io_schedule_bits_e_valid_T_1; // @[MSHR.scala:84:7, :188:43]
wire _io_schedule_bits_x_valid_T = ~s_flush; // @[MSHR.scala:128:33, :189:31]
assign _io_schedule_bits_x_valid_T_1 = _io_schedule_bits_x_valid_T & w_releaseack; // @[MSHR.scala:125:33, :189:{31,40}]
assign io_schedule_bits_x_valid_0 = _io_schedule_bits_x_valid_T_1; // @[MSHR.scala:84:7, :189:40]
wire _io_schedule_bits_dir_valid_T = ~s_release; // @[MSHR.scala:124:33, :186:32, :190:34]
wire _io_schedule_bits_dir_valid_T_1 = _io_schedule_bits_dir_valid_T & w_rprobeackfirst; // @[MSHR.scala:122:33, :190:{34,45}]
wire _io_schedule_bits_dir_valid_T_2 = ~s_writeback; // @[MSHR.scala:139:33, :190:70]
wire _io_schedule_bits_dir_valid_T_3 = _io_schedule_bits_dir_valid_T_2 & no_wait; // @[MSHR.scala:183:83, :190:{70,83}]
assign _io_schedule_bits_dir_valid_T_4 = _io_schedule_bits_dir_valid_T_1 | _io_schedule_bits_dir_valid_T_3; // @[MSHR.scala:190:{45,66,83}]
assign io_schedule_bits_dir_valid_0 = _io_schedule_bits_dir_valid_T_4; // @[MSHR.scala:84:7, :190:66]
wire _io_schedule_valid_T = io_schedule_bits_a_valid_0 | io_schedule_bits_b_valid_0; // @[MSHR.scala:84:7, :192:49]
wire _io_schedule_valid_T_1 = _io_schedule_valid_T | io_schedule_bits_c_valid_0; // @[MSHR.scala:84:7, :192:{49,77}]
wire _io_schedule_valid_T_2 = _io_schedule_valid_T_1 | io_schedule_bits_d_valid_0; // @[MSHR.scala:84:7, :192:{77,105}]
wire _io_schedule_valid_T_3 = _io_schedule_valid_T_2 | io_schedule_bits_e_valid_0; // @[MSHR.scala:84:7, :192:105, :193:49]
wire _io_schedule_valid_T_4 = _io_schedule_valid_T_3 | io_schedule_bits_x_valid_0; // @[MSHR.scala:84:7, :193:{49,77}]
assign _io_schedule_valid_T_5 = _io_schedule_valid_T_4 | io_schedule_bits_dir_valid_0; // @[MSHR.scala:84:7, :193:{77,105}]
assign io_schedule_valid_0 = _io_schedule_valid_T_5; // @[MSHR.scala:84:7, :193:105]
wire _io_schedule_bits_dir_bits_data_WIRE_dirty = final_meta_writeback_dirty; // @[MSHR.scala:215:38, :310:71]
wire [1:0] _io_schedule_bits_dir_bits_data_WIRE_state = final_meta_writeback_state; // @[MSHR.scala:215:38, :310:71]
wire _io_schedule_bits_dir_bits_data_WIRE_clients = final_meta_writeback_clients; // @[MSHR.scala:215:38, :310:71]
wire after_c = final_meta_writeback_clients; // @[MSHR.scala:215:38, :315:27]
wire prior_c = final_meta_writeback_clients; // @[MSHR.scala:215:38, :315:27]
wire [12:0] _io_schedule_bits_dir_bits_data_WIRE_tag = final_meta_writeback_tag; // @[MSHR.scala:215:38, :310:71]
wire final_meta_writeback_hit; // @[MSHR.scala:215:38]
wire [2:0] req_clientBit_uncommonBits = _req_clientBit_uncommonBits_T[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] _req_clientBit_T = request_source[5:3]; // @[Parameters.scala:54:10]
wire _req_clientBit_T_1 = _req_clientBit_T == 3'h4; // @[Parameters.scala:54:{10,32}]
wire _req_clientBit_T_3 = _req_clientBit_T_1; // @[Parameters.scala:54:{32,67}]
wire _req_clientBit_T_4 = req_clientBit_uncommonBits < 3'h5; // @[Parameters.scala:52:56, :57:20]
wire req_clientBit = _req_clientBit_T_3 & _req_clientBit_T_4; // @[Parameters.scala:54:67, :56:48, :57:20]
wire _req_needT_T = request_opcode[2]; // @[Parameters.scala:269:12]
wire _final_meta_writeback_dirty_T_3 = request_opcode[2]; // @[Parameters.scala:269:12]
wire _req_needT_T_1 = ~_req_needT_T; // @[Parameters.scala:269:{5,12}]
wire _GEN = request_opcode == 3'h5; // @[Parameters.scala:270:13]
wire _req_needT_T_2; // @[Parameters.scala:270:13]
assign _req_needT_T_2 = _GEN; // @[Parameters.scala:270:13]
wire _excluded_client_T_6; // @[Parameters.scala:279:117]
assign _excluded_client_T_6 = _GEN; // @[Parameters.scala:270:13, :279:117]
wire _GEN_0 = request_param == 3'h1; // @[Parameters.scala:270:42]
wire _req_needT_T_3; // @[Parameters.scala:270:42]
assign _req_needT_T_3 = _GEN_0; // @[Parameters.scala:270:42]
wire _final_meta_writeback_clients_T; // @[Parameters.scala:282:11]
assign _final_meta_writeback_clients_T = _GEN_0; // @[Parameters.scala:270:42, :282:11]
wire _io_schedule_bits_d_bits_param_T_7; // @[MSHR.scala:299:79]
assign _io_schedule_bits_d_bits_param_T_7 = _GEN_0; // @[Parameters.scala:270:42]
wire _req_needT_T_4 = _req_needT_T_2 & _req_needT_T_3; // @[Parameters.scala:270:{13,33,42}]
wire _req_needT_T_5 = _req_needT_T_1 | _req_needT_T_4; // @[Parameters.scala:269:{5,16}, :270:33]
wire _GEN_1 = request_opcode == 3'h6; // @[Parameters.scala:271:14]
wire _req_needT_T_6; // @[Parameters.scala:271:14]
assign _req_needT_T_6 = _GEN_1; // @[Parameters.scala:271:14]
wire _req_acquire_T; // @[MSHR.scala:219:36]
assign _req_acquire_T = _GEN_1; // @[Parameters.scala:271:14]
wire _excluded_client_T_1; // @[Parameters.scala:279:12]
assign _excluded_client_T_1 = _GEN_1; // @[Parameters.scala:271:14, :279:12]
wire _req_needT_T_7 = &request_opcode; // @[Parameters.scala:271:52]
wire _req_needT_T_8 = _req_needT_T_6 | _req_needT_T_7; // @[Parameters.scala:271:{14,42,52}]
wire _req_needT_T_9 = |request_param; // @[Parameters.scala:271:89]
wire _req_needT_T_10 = _req_needT_T_8 & _req_needT_T_9; // @[Parameters.scala:271:{42,80,89}]
wire req_needT = _req_needT_T_5 | _req_needT_T_10; // @[Parameters.scala:269:16, :270:70, :271:80]
wire _req_acquire_T_1 = &request_opcode; // @[Parameters.scala:271:52]
wire req_acquire = _req_acquire_T | _req_acquire_T_1; // @[MSHR.scala:219:{36,53,71}]
wire meta_no_clients = ~_meta_no_clients_T; // @[MSHR.scala:220:{25,39}]
wire _req_promoteT_T = &meta_state; // @[MSHR.scala:100:17, :221:81]
wire _req_promoteT_T_1 = meta_no_clients & _req_promoteT_T; // @[MSHR.scala:220:25, :221:{67,81}]
wire _req_promoteT_T_2 = meta_hit ? _req_promoteT_T_1 : gotT; // @[MSHR.scala:100:17, :148:17, :221:{40,67}]
wire req_promoteT = req_acquire & _req_promoteT_T_2; // @[MSHR.scala:219:53, :221:{34,40}]
wire _final_meta_writeback_dirty_T = request_opcode[0]; // @[MSHR.scala:98:20, :224:65]
wire _final_meta_writeback_dirty_T_1 = meta_dirty | _final_meta_writeback_dirty_T; // @[MSHR.scala:100:17, :224:{48,65}]
wire _final_meta_writeback_state_T = request_param != 3'h3; // @[MSHR.scala:98:20, :225:55]
wire _GEN_2 = meta_state == 2'h2; // @[MSHR.scala:100:17, :225:78]
wire _final_meta_writeback_state_T_1; // @[MSHR.scala:225:78]
assign _final_meta_writeback_state_T_1 = _GEN_2; // @[MSHR.scala:225:78]
wire _final_meta_writeback_state_T_12; // @[MSHR.scala:240:70]
assign _final_meta_writeback_state_T_12 = _GEN_2; // @[MSHR.scala:225:78, :240:70]
wire _evict_T_2; // @[MSHR.scala:317:26]
assign _evict_T_2 = _GEN_2; // @[MSHR.scala:225:78, :317:26]
wire _before_T_1; // @[MSHR.scala:317:26]
assign _before_T_1 = _GEN_2; // @[MSHR.scala:225:78, :317:26]
wire _final_meta_writeback_state_T_2 = _final_meta_writeback_state_T & _final_meta_writeback_state_T_1; // @[MSHR.scala:225:{55,64,78}]
wire [1:0] _final_meta_writeback_state_T_3 = _final_meta_writeback_state_T_2 ? 2'h3 : meta_state; // @[MSHR.scala:100:17, :225:{40,64}]
wire _GEN_3 = request_param == 3'h2; // @[Parameters.scala:282:43]
wire _final_meta_writeback_clients_T_1; // @[Parameters.scala:282:43]
assign _final_meta_writeback_clients_T_1 = _GEN_3; // @[Parameters.scala:282:43]
wire _io_schedule_bits_d_bits_param_T_5; // @[MSHR.scala:299:79]
assign _io_schedule_bits_d_bits_param_T_5 = _GEN_3; // @[Parameters.scala:282:43]
wire _final_meta_writeback_clients_T_2 = _final_meta_writeback_clients_T | _final_meta_writeback_clients_T_1; // @[Parameters.scala:282:{11,34,43}]
wire _final_meta_writeback_clients_T_3 = request_param == 3'h5; // @[Parameters.scala:282:75]
wire _final_meta_writeback_clients_T_4 = _final_meta_writeback_clients_T_2 | _final_meta_writeback_clients_T_3; // @[Parameters.scala:282:{34,66,75}]
wire _final_meta_writeback_clients_T_5 = _final_meta_writeback_clients_T_4 & req_clientBit; // @[Parameters.scala:56:48]
wire _final_meta_writeback_clients_T_6 = ~_final_meta_writeback_clients_T_5; // @[MSHR.scala:226:{52,56}]
wire _final_meta_writeback_clients_T_7 = meta_clients & _final_meta_writeback_clients_T_6; // @[MSHR.scala:100:17, :226:{50,52}]
wire _final_meta_writeback_clients_T_8 = ~probes_toN; // @[MSHR.scala:151:23, :232:54]
wire _final_meta_writeback_clients_T_9 = meta_clients & _final_meta_writeback_clients_T_8; // @[MSHR.scala:100:17, :232:{52,54}]
wire _final_meta_writeback_dirty_T_2 = meta_hit & meta_dirty; // @[MSHR.scala:100:17, :236:45]
wire _final_meta_writeback_dirty_T_4 = ~_final_meta_writeback_dirty_T_3; // @[MSHR.scala:236:{63,78}]
wire _final_meta_writeback_dirty_T_5 = _final_meta_writeback_dirty_T_2 | _final_meta_writeback_dirty_T_4; // @[MSHR.scala:236:{45,60,63}]
wire [1:0] _GEN_4 = {1'h1, ~req_acquire}; // @[MSHR.scala:219:53, :238:40]
wire [1:0] _final_meta_writeback_state_T_4; // @[MSHR.scala:238:40]
assign _final_meta_writeback_state_T_4 = _GEN_4; // @[MSHR.scala:238:40]
wire [1:0] _final_meta_writeback_state_T_6; // @[MSHR.scala:239:65]
assign _final_meta_writeback_state_T_6 = _GEN_4; // @[MSHR.scala:238:40, :239:65]
wire _final_meta_writeback_state_T_5 = ~meta_hit; // @[MSHR.scala:100:17, :239:41]
wire [1:0] _final_meta_writeback_state_T_7 = gotT ? _final_meta_writeback_state_T_6 : 2'h1; // @[MSHR.scala:148:17, :239:{55,65}]
wire _final_meta_writeback_state_T_8 = meta_no_clients & req_acquire; // @[MSHR.scala:219:53, :220:25, :244:72]
wire [1:0] _final_meta_writeback_state_T_9 = {1'h1, ~_final_meta_writeback_state_T_8}; // @[MSHR.scala:244:{55,72}]
wire _GEN_5 = meta_state == 2'h1; // @[MSHR.scala:100:17, :240:70]
wire _final_meta_writeback_state_T_10; // @[MSHR.scala:240:70]
assign _final_meta_writeback_state_T_10 = _GEN_5; // @[MSHR.scala:240:70]
wire _io_schedule_bits_c_bits_param_T; // @[MSHR.scala:291:53]
assign _io_schedule_bits_c_bits_param_T = _GEN_5; // @[MSHR.scala:240:70, :291:53]
wire _evict_T_1; // @[MSHR.scala:317:26]
assign _evict_T_1 = _GEN_5; // @[MSHR.scala:240:70, :317:26]
wire _before_T; // @[MSHR.scala:317:26]
assign _before_T = _GEN_5; // @[MSHR.scala:240:70, :317:26]
wire [1:0] _final_meta_writeback_state_T_13 = {_final_meta_writeback_state_T_12, 1'h1}; // @[MSHR.scala:240:70]
wire _final_meta_writeback_state_T_14 = &meta_state; // @[MSHR.scala:100:17, :221:81, :240:70]
wire [1:0] _final_meta_writeback_state_T_15 = _final_meta_writeback_state_T_14 ? _final_meta_writeback_state_T_9 : _final_meta_writeback_state_T_13; // @[MSHR.scala:240:70, :244:55]
wire [1:0] _final_meta_writeback_state_T_16 = _final_meta_writeback_state_T_5 ? _final_meta_writeback_state_T_7 : _final_meta_writeback_state_T_15; // @[MSHR.scala:239:{40,41,55}, :240:70]
wire [1:0] _final_meta_writeback_state_T_17 = req_needT ? _final_meta_writeback_state_T_4 : _final_meta_writeback_state_T_16; // @[Parameters.scala:270:70]
wire _final_meta_writeback_clients_T_10 = ~probes_toN; // @[MSHR.scala:151:23, :232:54, :245:66]
wire _final_meta_writeback_clients_T_11 = meta_clients & _final_meta_writeback_clients_T_10; // @[MSHR.scala:100:17, :245:{64,66}]
wire _final_meta_writeback_clients_T_12 = meta_hit & _final_meta_writeback_clients_T_11; // @[MSHR.scala:100:17, :245:{40,64}]
wire _final_meta_writeback_clients_T_13 = req_acquire & req_clientBit; // @[Parameters.scala:56:48]
wire _final_meta_writeback_clients_T_14 = _final_meta_writeback_clients_T_12 | _final_meta_writeback_clients_T_13; // @[MSHR.scala:245:{40,84}, :246:40]
assign final_meta_writeback_tag = request_prio_2 | request_control ? meta_tag : request_tag; // @[MSHR.scala:98:20, :100:17, :215:38, :223:52, :228:53, :247:30]
wire _final_meta_writeback_clients_T_15 = ~probes_toN; // @[MSHR.scala:151:23, :232:54, :258:54]
wire _final_meta_writeback_clients_T_16 = meta_clients & _final_meta_writeback_clients_T_15; // @[MSHR.scala:100:17, :258:{52,54}]
assign final_meta_writeback_hit = bad_grant ? meta_hit : request_prio_2 | ~request_control; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :227:34, :228:53, :234:30, :248:30, :251:20, :252:21]
assign final_meta_writeback_dirty = ~bad_grant & (request_prio_2 ? _final_meta_writeback_dirty_T_1 : request_control ? ~meta_hit & meta_dirty : _final_meta_writeback_dirty_T_5); // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :224:{34,48}, :228:53, :229:21, :230:36, :236:{32,60}, :251:20, :252:21]
assign final_meta_writeback_state = bad_grant ? {1'h0, meta_hit} : request_prio_2 ? _final_meta_writeback_state_T_3 : request_control ? (meta_hit ? 2'h0 : meta_state) : _final_meta_writeback_state_T_17; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :225:{34,40}, :228:53, :229:21, :231:36, :237:{32,38}, :251:20, :252:21, :257:36, :263:36]
assign final_meta_writeback_clients = bad_grant ? meta_hit & _final_meta_writeback_clients_T_16 : request_prio_2 ? _final_meta_writeback_clients_T_7 : request_control ? (meta_hit ? _final_meta_writeback_clients_T_9 : meta_clients) : _final_meta_writeback_clients_T_14; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :226:{34,50}, :228:53, :229:21, :232:{36,52}, :245:{34,84}, :251:20, :252:21, :258:{36,52}, :264:36]
wire _honour_BtoT_T = meta_clients & req_clientBit; // @[Parameters.scala:56:48]
wire _honour_BtoT_T_1 = _honour_BtoT_T; // @[MSHR.scala:276:{47,64}]
wire honour_BtoT = meta_hit & _honour_BtoT_T_1; // @[MSHR.scala:100:17, :276:{30,64}]
wire _excluded_client_T_2 = &request_opcode; // @[Parameters.scala:271:52, :279:50]
wire _excluded_client_T_3 = _excluded_client_T_1 | _excluded_client_T_2; // @[Parameters.scala:279:{12,40,50}]
wire _excluded_client_T_4 = request_opcode == 3'h4; // @[Parameters.scala:279:87]
wire _excluded_client_T_5 = _excluded_client_T_3 | _excluded_client_T_4; // @[Parameters.scala:279:{40,77,87}]
wire _excluded_client_T_8 = _excluded_client_T_5; // @[Parameters.scala:279:{77,106}]
wire [1:0] _io_schedule_bits_a_bits_param_T = meta_hit ? 2'h2 : 2'h1; // @[MSHR.scala:100:17, :282:56]
wire [1:0] _io_schedule_bits_a_bits_param_T_1 = req_needT ? _io_schedule_bits_a_bits_param_T : 2'h0; // @[Parameters.scala:270:70]
assign io_schedule_bits_a_bits_param_0 = {1'h0, _io_schedule_bits_a_bits_param_T_1}; // @[MSHR.scala:84:7, :282:{35,41}]
wire _io_schedule_bits_a_bits_block_T = request_size != 3'h6; // @[MSHR.scala:98:20, :283:51]
wire _io_schedule_bits_a_bits_block_T_1 = request_opcode == 3'h0; // @[MSHR.scala:98:20, :284:55]
wire _io_schedule_bits_a_bits_block_T_2 = &request_opcode; // @[Parameters.scala:271:52]
wire _io_schedule_bits_a_bits_block_T_3 = _io_schedule_bits_a_bits_block_T_1 | _io_schedule_bits_a_bits_block_T_2; // @[MSHR.scala:284:{55,71,89}]
wire _io_schedule_bits_a_bits_block_T_4 = ~_io_schedule_bits_a_bits_block_T_3; // @[MSHR.scala:284:{38,71}]
assign _io_schedule_bits_a_bits_block_T_5 = _io_schedule_bits_a_bits_block_T | _io_schedule_bits_a_bits_block_T_4; // @[MSHR.scala:283:{51,91}, :284:38]
assign io_schedule_bits_a_bits_block_0 = _io_schedule_bits_a_bits_block_T_5; // @[MSHR.scala:84:7, :283:91]
wire _io_schedule_bits_b_bits_param_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31, :286:42]
wire [1:0] _io_schedule_bits_b_bits_param_T_1 = req_needT ? 2'h2 : 2'h1; // @[Parameters.scala:270:70]
wire [2:0] _io_schedule_bits_b_bits_param_T_2 = {1'h0, _io_schedule_bits_b_bits_param_T_1}; // @[MSHR.scala:286:{61,97}]
assign _io_schedule_bits_b_bits_param_T_3 = _io_schedule_bits_b_bits_param_T ? 3'h2 : _io_schedule_bits_b_bits_param_T_2; // @[MSHR.scala:286:{41,42,61}]
assign io_schedule_bits_b_bits_param_0 = _io_schedule_bits_b_bits_param_T_3; // @[MSHR.scala:84:7, :286:41]
wire _io_schedule_bits_b_bits_tag_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31, :287:42]
assign _io_schedule_bits_b_bits_tag_T_1 = _io_schedule_bits_b_bits_tag_T ? meta_tag : request_tag; // @[MSHR.scala:98:20, :100:17, :287:{41,42}]
assign io_schedule_bits_b_bits_tag_0 = _io_schedule_bits_b_bits_tag_T_1; // @[MSHR.scala:84:7, :287:41]
assign io_schedule_bits_b_bits_clients_0 = _io_schedule_bits_b_bits_clients_T_1; // @[MSHR.scala:84:7, :289:51]
assign _io_schedule_bits_c_bits_opcode_T = {2'h3, meta_dirty}; // @[MSHR.scala:100:17, :290:41]
assign io_schedule_bits_c_bits_opcode_0 = _io_schedule_bits_c_bits_opcode_T; // @[MSHR.scala:84:7, :290:41]
assign _io_schedule_bits_c_bits_param_T_1 = _io_schedule_bits_c_bits_param_T ? 3'h2 : 3'h1; // @[MSHR.scala:291:{41,53}]
assign io_schedule_bits_c_bits_param_0 = _io_schedule_bits_c_bits_param_T_1; // @[MSHR.scala:84:7, :291:41]
wire _io_schedule_bits_d_bits_param_T = ~req_acquire; // @[MSHR.scala:219:53, :298:42]
wire [1:0] _io_schedule_bits_d_bits_param_T_1 = {1'h0, req_promoteT}; // @[MSHR.scala:221:34, :300:53]
wire [1:0] _io_schedule_bits_d_bits_param_T_2 = honour_BtoT ? 2'h2 : 2'h1; // @[MSHR.scala:276:30, :301:53]
wire _io_schedule_bits_d_bits_param_T_3 = ~(|request_param); // @[Parameters.scala:271:89]
wire [2:0] _io_schedule_bits_d_bits_param_T_4 = _io_schedule_bits_d_bits_param_T_3 ? {1'h0, _io_schedule_bits_d_bits_param_T_1} : request_param; // @[MSHR.scala:98:20, :299:79, :300:53]
wire [2:0] _io_schedule_bits_d_bits_param_T_6 = _io_schedule_bits_d_bits_param_T_5 ? {1'h0, _io_schedule_bits_d_bits_param_T_2} : _io_schedule_bits_d_bits_param_T_4; // @[MSHR.scala:299:79, :301:53]
wire [2:0] _io_schedule_bits_d_bits_param_T_8 = _io_schedule_bits_d_bits_param_T_7 ? 3'h1 : _io_schedule_bits_d_bits_param_T_6; // @[MSHR.scala:299:79]
assign _io_schedule_bits_d_bits_param_T_9 = _io_schedule_bits_d_bits_param_T ? request_param : _io_schedule_bits_d_bits_param_T_8; // @[MSHR.scala:98:20, :298:{41,42}, :299:79]
assign io_schedule_bits_d_bits_param_0 = _io_schedule_bits_d_bits_param_T_9; // @[MSHR.scala:84:7, :298:41]
wire _io_schedule_bits_dir_bits_data_T = ~s_release; // @[MSHR.scala:124:33, :186:32, :310:42]
assign _io_schedule_bits_dir_bits_data_T_1_dirty = ~_io_schedule_bits_dir_bits_data_T & _io_schedule_bits_dir_bits_data_WIRE_dirty; // @[MSHR.scala:310:{41,42,71}]
assign _io_schedule_bits_dir_bits_data_T_1_state = _io_schedule_bits_dir_bits_data_T ? 2'h0 : _io_schedule_bits_dir_bits_data_WIRE_state; // @[MSHR.scala:310:{41,42,71}]
assign _io_schedule_bits_dir_bits_data_T_1_clients = ~_io_schedule_bits_dir_bits_data_T & _io_schedule_bits_dir_bits_data_WIRE_clients; // @[MSHR.scala:310:{41,42,71}]
assign _io_schedule_bits_dir_bits_data_T_1_tag = _io_schedule_bits_dir_bits_data_T ? 13'h0 : _io_schedule_bits_dir_bits_data_WIRE_tag; // @[MSHR.scala:310:{41,42,71}]
assign io_schedule_bits_dir_bits_data_dirty_0 = _io_schedule_bits_dir_bits_data_T_1_dirty; // @[MSHR.scala:84:7, :310:41]
assign io_schedule_bits_dir_bits_data_state_0 = _io_schedule_bits_dir_bits_data_T_1_state; // @[MSHR.scala:84:7, :310:41]
assign io_schedule_bits_dir_bits_data_clients_0 = _io_schedule_bits_dir_bits_data_T_1_clients; // @[MSHR.scala:84:7, :310:41]
assign io_schedule_bits_dir_bits_data_tag_0 = _io_schedule_bits_dir_bits_data_T_1_tag; // @[MSHR.scala:84:7, :310:41]
wire _evict_T = ~meta_hit; // @[MSHR.scala:100:17, :239:41, :338:32]
wire [3:0] evict; // @[MSHR.scala:314:26]
wire _evict_out_T = ~evict_c; // @[MSHR.scala:315:27, :318:32]
wire [1:0] _GEN_6 = {1'h1, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32]
wire [1:0] _evict_out_T_1; // @[MSHR.scala:319:32]
assign _evict_out_T_1 = _GEN_6; // @[MSHR.scala:319:32]
wire [1:0] _before_out_T_1; // @[MSHR.scala:319:32]
assign _before_out_T_1 = _GEN_6; // @[MSHR.scala:319:32]
wire _evict_T_3 = &meta_state; // @[MSHR.scala:100:17, :221:81, :317:26]
wire [2:0] _GEN_7 = {2'h2, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32, :320:39]
wire [2:0] _evict_out_T_2; // @[MSHR.scala:320:39]
assign _evict_out_T_2 = _GEN_7; // @[MSHR.scala:320:39]
wire [2:0] _before_out_T_2; // @[MSHR.scala:320:39]
assign _before_out_T_2 = _GEN_7; // @[MSHR.scala:320:39]
wire [2:0] _GEN_8 = {2'h3, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32, :320:76]
wire [2:0] _evict_out_T_3; // @[MSHR.scala:320:76]
assign _evict_out_T_3 = _GEN_8; // @[MSHR.scala:320:76]
wire [2:0] _before_out_T_3; // @[MSHR.scala:320:76]
assign _before_out_T_3 = _GEN_8; // @[MSHR.scala:320:76]
wire [2:0] _evict_out_T_4 = evict_c ? _evict_out_T_2 : _evict_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}]
wire _evict_T_4 = ~(|meta_state); // @[MSHR.scala:100:17, :104:22, :317:26]
wire _evict_T_5 = ~_evict_T; // @[MSHR.scala:323:11, :338:32]
assign evict = _evict_T_5 ? 4'h8 : _evict_T_1 ? {3'h0, _evict_out_T} : _evict_T_2 ? {2'h0, _evict_out_T_1} : _evict_T_3 ? {1'h0, _evict_out_T_4} : {_evict_T_4, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26, :323:{11,17,23}]
wire [3:0] before_0; // @[MSHR.scala:314:26]
wire _before_out_T = ~before_c; // @[MSHR.scala:315:27, :318:32]
wire _before_T_2 = &meta_state; // @[MSHR.scala:100:17, :221:81, :317:26]
wire [2:0] _before_out_T_4 = before_c ? _before_out_T_2 : _before_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}]
wire _before_T_3 = ~(|meta_state); // @[MSHR.scala:100:17, :104:22, :317:26]
wire _before_T_4 = ~meta_hit; // @[MSHR.scala:100:17, :239:41, :323:11]
assign before_0 = _before_T_4 ? 4'h8 : _before_T ? {3'h0, _before_out_T} : _before_T_1 ? {2'h0, _before_out_T_1} : _before_T_2 ? {1'h0, _before_out_T_4} : {_before_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26, :323:{11,17,23}]
wire [3:0] after; // @[MSHR.scala:314:26]
wire _GEN_9 = final_meta_writeback_state == 2'h1; // @[MSHR.scala:215:38, :317:26]
wire _after_T; // @[MSHR.scala:317:26]
assign _after_T = _GEN_9; // @[MSHR.scala:317:26]
wire _prior_T; // @[MSHR.scala:317:26]
assign _prior_T = _GEN_9; // @[MSHR.scala:317:26]
wire _after_out_T = ~after_c; // @[MSHR.scala:315:27, :318:32]
wire _GEN_10 = final_meta_writeback_state == 2'h2; // @[MSHR.scala:215:38, :317:26]
wire _after_T_1; // @[MSHR.scala:317:26]
assign _after_T_1 = _GEN_10; // @[MSHR.scala:317:26]
wire _prior_T_1; // @[MSHR.scala:317:26]
assign _prior_T_1 = _GEN_10; // @[MSHR.scala:317:26]
wire [1:0] _GEN_11 = {1'h1, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32]
wire [1:0] _after_out_T_1; // @[MSHR.scala:319:32]
assign _after_out_T_1 = _GEN_11; // @[MSHR.scala:319:32]
wire [1:0] _prior_out_T_1; // @[MSHR.scala:319:32]
assign _prior_out_T_1 = _GEN_11; // @[MSHR.scala:319:32]
wire _after_T_2 = &final_meta_writeback_state; // @[MSHR.scala:215:38, :317:26]
wire [2:0] _GEN_12 = {2'h2, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32, :320:39]
wire [2:0] _after_out_T_2; // @[MSHR.scala:320:39]
assign _after_out_T_2 = _GEN_12; // @[MSHR.scala:320:39]
wire [2:0] _prior_out_T_2; // @[MSHR.scala:320:39]
assign _prior_out_T_2 = _GEN_12; // @[MSHR.scala:320:39]
wire [2:0] _GEN_13 = {2'h3, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32, :320:76]
wire [2:0] _after_out_T_3; // @[MSHR.scala:320:76]
assign _after_out_T_3 = _GEN_13; // @[MSHR.scala:320:76]
wire [2:0] _prior_out_T_3; // @[MSHR.scala:320:76]
assign _prior_out_T_3 = _GEN_13; // @[MSHR.scala:320:76]
wire [2:0] _after_out_T_4 = after_c ? _after_out_T_2 : _after_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}]
wire _GEN_14 = final_meta_writeback_state == 2'h0; // @[MSHR.scala:215:38, :317:26]
wire _after_T_3; // @[MSHR.scala:317:26]
assign _after_T_3 = _GEN_14; // @[MSHR.scala:317:26]
wire _prior_T_3; // @[MSHR.scala:317:26]
assign _prior_T_3 = _GEN_14; // @[MSHR.scala:317:26]
assign after = _after_T ? {3'h0, _after_out_T} : _after_T_1 ? {2'h0, _after_out_T_1} : _after_T_2 ? {1'h0, _after_out_T_4} : {_after_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26]
wire [2:0] probe_bit_uncommonBits = _probe_bit_uncommonBits_T[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] _probe_bit_T = io_sinkc_bits_source_0[5:3]; // @[Parameters.scala:54:10]
wire _probe_bit_T_1 = _probe_bit_T == 3'h4; // @[Parameters.scala:54:{10,32}]
wire _probe_bit_T_3 = _probe_bit_T_1; // @[Parameters.scala:54:{32,67}]
wire _probe_bit_T_4 = probe_bit_uncommonBits < 3'h5; // @[Parameters.scala:52:56, :57:20]
wire probe_bit = _probe_bit_T_3 & _probe_bit_T_4; // @[Parameters.scala:54:67, :56:48, :57:20]
wire _GEN_15 = probes_done | probe_bit; // @[Parameters.scala:56:48]
wire _last_probe_T; // @[MSHR.scala:459:33]
assign _last_probe_T = _GEN_15; // @[MSHR.scala:459:33]
wire _probes_done_T; // @[MSHR.scala:467:32]
assign _probes_done_T = _GEN_15; // @[MSHR.scala:459:33, :467:32]
wire last_probe = _last_probe_T == _last_probe_T_2; // @[MSHR.scala:459:{33,46,64}]
wire _probe_toN_T = io_sinkc_bits_param_0 == 3'h1; // @[Parameters.scala:282:11]
wire _probe_toN_T_1 = io_sinkc_bits_param_0 == 3'h2; // @[Parameters.scala:282:43]
wire _probe_toN_T_2 = _probe_toN_T | _probe_toN_T_1; // @[Parameters.scala:282:{11,34,43}]
wire _probe_toN_T_3 = io_sinkc_bits_param_0 == 3'h5; // @[Parameters.scala:282:75]
wire probe_toN = _probe_toN_T_2 | _probe_toN_T_3; // @[Parameters.scala:282:{34,66,75}]
wire _probes_toN_T = probe_toN & probe_bit; // @[Parameters.scala:56:48]
wire _probes_toN_T_1 = probes_toN | _probes_toN_T; // @[MSHR.scala:151:23, :468:{30,35}]
wire _probes_noT_T = io_sinkc_bits_param_0 != 3'h3; // @[MSHR.scala:84:7, :469:53]
wire _probes_noT_T_1 = probes_noT | _probes_noT_T; // @[MSHR.scala:152:23, :469:{30,53}]
wire _w_rprobeackfirst_T = w_rprobeackfirst | last_probe; // @[MSHR.scala:122:33, :459:46, :470:42]
wire _GEN_16 = last_probe & io_sinkc_bits_last_0; // @[MSHR.scala:84:7, :459:46, :471:55]
wire _w_rprobeacklast_T; // @[MSHR.scala:471:55]
assign _w_rprobeacklast_T = _GEN_16; // @[MSHR.scala:471:55]
wire _w_pprobeacklast_T; // @[MSHR.scala:473:55]
assign _w_pprobeacklast_T = _GEN_16; // @[MSHR.scala:471:55, :473:55]
wire _w_rprobeacklast_T_1 = w_rprobeacklast | _w_rprobeacklast_T; // @[MSHR.scala:123:33, :471:{40,55}]
wire _w_pprobeackfirst_T = w_pprobeackfirst | last_probe; // @[MSHR.scala:132:33, :459:46, :472:42]
wire _w_pprobeacklast_T_1 = w_pprobeacklast | _w_pprobeacklast_T; // @[MSHR.scala:133:33, :473:{40,55}]
wire _set_pprobeack_T = ~(|request_offset); // @[MSHR.scala:98:20, :475:77]
wire _set_pprobeack_T_1 = io_sinkc_bits_last_0 | _set_pprobeack_T; // @[MSHR.scala:84:7, :475:{59,77}]
wire set_pprobeack = last_probe & _set_pprobeack_T_1; // @[MSHR.scala:459:46, :475:{36,59}]
wire _w_pprobeack_T = w_pprobeack | set_pprobeack; // @[MSHR.scala:134:33, :475:36, :476:32]
wire _w_grant_T = ~(|request_offset); // @[MSHR.scala:98:20, :475:77, :490:33]
wire _w_grant_T_1 = _w_grant_T | io_sinkd_bits_last_0; // @[MSHR.scala:84:7, :490:{33,41}]
wire _gotT_T = io_sinkd_bits_param_0 == 3'h0; // @[MSHR.scala:84:7, :493:35]
wire _new_meta_T = io_allocate_valid_0 & io_allocate_bits_repeat_0; // @[MSHR.scala:84:7, :505:40]
wire new_meta_dirty = _new_meta_T ? final_meta_writeback_dirty : io_directory_bits_dirty_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}]
wire [1:0] new_meta_state = _new_meta_T ? final_meta_writeback_state : io_directory_bits_state_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}]
wire new_meta_clients = _new_meta_T ? final_meta_writeback_clients : io_directory_bits_clients_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}]
wire [12:0] new_meta_tag = _new_meta_T ? final_meta_writeback_tag : io_directory_bits_tag_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}]
wire new_meta_hit = _new_meta_T ? final_meta_writeback_hit : io_directory_bits_hit_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}]
wire [2:0] new_meta_way = _new_meta_T ? final_meta_writeback_way : io_directory_bits_way_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}]
wire new_request_prio_2 = io_allocate_valid_0 ? allocate_as_full_prio_2 : request_prio_2; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire new_request_control = io_allocate_valid_0 ? allocate_as_full_control : request_control; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [2:0] new_request_opcode = io_allocate_valid_0 ? allocate_as_full_opcode : request_opcode; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [2:0] new_request_param = io_allocate_valid_0 ? allocate_as_full_param : request_param; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [2:0] new_request_size = io_allocate_valid_0 ? allocate_as_full_size : request_size; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [5:0] new_request_source = io_allocate_valid_0 ? allocate_as_full_source : request_source; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [12:0] new_request_tag = io_allocate_valid_0 ? allocate_as_full_tag : request_tag; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [5:0] new_request_offset = io_allocate_valid_0 ? allocate_as_full_offset : request_offset; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [5:0] new_request_put = io_allocate_valid_0 ? allocate_as_full_put : request_put; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [9:0] new_request_set = io_allocate_valid_0 ? allocate_as_full_set : request_set; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [5:0] _new_clientBit_uncommonBits_T = new_request_source; // @[Parameters.scala:52:29]
wire _new_needT_T = new_request_opcode[2]; // @[Parameters.scala:269:12]
wire _new_needT_T_1 = ~_new_needT_T; // @[Parameters.scala:269:{5,12}]
wire _GEN_17 = new_request_opcode == 3'h5; // @[Parameters.scala:270:13]
wire _new_needT_T_2; // @[Parameters.scala:270:13]
assign _new_needT_T_2 = _GEN_17; // @[Parameters.scala:270:13]
wire _new_skipProbe_T_5; // @[Parameters.scala:279:117]
assign _new_skipProbe_T_5 = _GEN_17; // @[Parameters.scala:270:13, :279:117]
wire _new_needT_T_3 = new_request_param == 3'h1; // @[Parameters.scala:270:42]
wire _new_needT_T_4 = _new_needT_T_2 & _new_needT_T_3; // @[Parameters.scala:270:{13,33,42}]
wire _new_needT_T_5 = _new_needT_T_1 | _new_needT_T_4; // @[Parameters.scala:269:{5,16}, :270:33]
wire _T_615 = new_request_opcode == 3'h6; // @[Parameters.scala:271:14]
wire _new_needT_T_6; // @[Parameters.scala:271:14]
assign _new_needT_T_6 = _T_615; // @[Parameters.scala:271:14]
wire _new_skipProbe_T; // @[Parameters.scala:279:12]
assign _new_skipProbe_T = _T_615; // @[Parameters.scala:271:14, :279:12]
wire _new_needT_T_7 = &new_request_opcode; // @[Parameters.scala:271:52]
wire _new_needT_T_8 = _new_needT_T_6 | _new_needT_T_7; // @[Parameters.scala:271:{14,42,52}]
wire _new_needT_T_9 = |new_request_param; // @[Parameters.scala:271:89]
wire _new_needT_T_10 = _new_needT_T_8 & _new_needT_T_9; // @[Parameters.scala:271:{42,80,89}]
wire new_needT = _new_needT_T_5 | _new_needT_T_10; // @[Parameters.scala:269:16, :270:70, :271:80]
wire [2:0] new_clientBit_uncommonBits = _new_clientBit_uncommonBits_T[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] _new_clientBit_T = new_request_source[5:3]; // @[Parameters.scala:54:10]
wire _new_clientBit_T_1 = _new_clientBit_T == 3'h4; // @[Parameters.scala:54:{10,32}]
wire _new_clientBit_T_3 = _new_clientBit_T_1; // @[Parameters.scala:54:{32,67}]
wire _new_clientBit_T_4 = new_clientBit_uncommonBits < 3'h5; // @[Parameters.scala:52:56, :57:20]
wire new_clientBit = _new_clientBit_T_3 & _new_clientBit_T_4; // @[Parameters.scala:54:67, :56:48, :57:20]
wire _new_skipProbe_T_1 = &new_request_opcode; // @[Parameters.scala:271:52, :279:50]
wire _new_skipProbe_T_2 = _new_skipProbe_T | _new_skipProbe_T_1; // @[Parameters.scala:279:{12,40,50}]
wire _new_skipProbe_T_3 = new_request_opcode == 3'h4; // @[Parameters.scala:279:87]
wire _new_skipProbe_T_4 = _new_skipProbe_T_2 | _new_skipProbe_T_3; // @[Parameters.scala:279:{40,77,87}]
wire _new_skipProbe_T_7 = _new_skipProbe_T_4; // @[Parameters.scala:279:{77,106}]
wire new_skipProbe = _new_skipProbe_T_7 & new_clientBit; // @[Parameters.scala:56:48]
wire [3:0] prior; // @[MSHR.scala:314:26]
wire _prior_out_T = ~prior_c; // @[MSHR.scala:315:27, :318:32]
wire _prior_T_2 = &final_meta_writeback_state; // @[MSHR.scala:215:38, :317:26]
wire [2:0] _prior_out_T_4 = prior_c ? _prior_out_T_2 : _prior_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}]
assign prior = _prior_T ? {3'h0, _prior_out_T} : _prior_T_1 ? {2'h0, _prior_out_T_1} : _prior_T_2 ? {1'h0, _prior_out_T_4} : {_prior_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26]
wire _T_574 = io_directory_valid_0 | _new_meta_T; // @[MSHR.scala:84:7, :505:40, :539:28] |
Generate the Verilog code corresponding to the following Chisel files.
File util.scala:
//******************************************************************************
// Copyright (c) 2015 - 2019, The Regents of the University of California (Regents).
// All Rights Reserved. See LICENSE and LICENSE.SiFive for license details.
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
// Utility Functions
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
package boom.v4.util
import chisel3._
import chisel3.util._
import freechips.rocketchip.rocket.Instructions._
import freechips.rocketchip.rocket._
import freechips.rocketchip.util.{Str}
import org.chipsalliance.cde.config.{Parameters}
import freechips.rocketchip.tile.{TileKey}
import boom.v4.common.{MicroOp}
import boom.v4.exu.{BrUpdateInfo}
/**
* Object to XOR fold a input register of fullLength into a compressedLength.
*/
object Fold
{
def apply(input: UInt, compressedLength: Int, fullLength: Int): UInt = {
val clen = compressedLength
val hlen = fullLength
if (hlen <= clen) {
input
} else {
var res = 0.U(clen.W)
var remaining = input.asUInt
for (i <- 0 to hlen-1 by clen) {
val len = if (i + clen > hlen ) (hlen - i) else clen
require(len > 0)
res = res(clen-1,0) ^ remaining(len-1,0)
remaining = remaining >> len.U
}
res
}
}
}
/**
* Object to check if MicroOp was killed due to a branch mispredict.
* Uses "Fast" branch masks
*/
object IsKilledByBranch
{
def apply(brupdate: BrUpdateInfo, flush: Bool, uop: MicroOp): Bool = {
return apply(brupdate, flush, uop.br_mask)
}
def apply(brupdate: BrUpdateInfo, flush: Bool, uop_mask: UInt): Bool = {
return maskMatch(brupdate.b1.mispredict_mask, uop_mask) || flush
}
def apply[T <: boom.v4.common.HasBoomUOP](brupdate: BrUpdateInfo, flush: Bool, bundle: T): Bool = {
return apply(brupdate, flush, bundle.uop)
}
def apply[T <: boom.v4.common.HasBoomUOP](brupdate: BrUpdateInfo, flush: Bool, bundle: Valid[T]): Bool = {
return apply(brupdate, flush, bundle.bits)
}
}
/**
* Object to return new MicroOp with a new BR mask given a MicroOp mask
* and old BR mask.
*/
object GetNewUopAndBrMask
{
def apply(uop: MicroOp, brupdate: BrUpdateInfo)
(implicit p: Parameters): MicroOp = {
val newuop = WireInit(uop)
newuop.br_mask := uop.br_mask & ~brupdate.b1.resolve_mask
newuop
}
}
/**
* Object to return a BR mask given a MicroOp mask and old BR mask.
*/
object GetNewBrMask
{
def apply(brupdate: BrUpdateInfo, uop: MicroOp): UInt = {
return uop.br_mask & ~brupdate.b1.resolve_mask
}
def apply(brupdate: BrUpdateInfo, br_mask: UInt): UInt = {
return br_mask & ~brupdate.b1.resolve_mask
}
}
object UpdateBrMask
{
def apply(brupdate: BrUpdateInfo, uop: MicroOp): MicroOp = {
val out = WireInit(uop)
out.br_mask := GetNewBrMask(brupdate, uop)
out
}
def apply[T <: boom.v4.common.HasBoomUOP](brupdate: BrUpdateInfo, bundle: T): T = {
val out = WireInit(bundle)
out.uop.br_mask := GetNewBrMask(brupdate, bundle.uop.br_mask)
out
}
def apply[T <: boom.v4.common.HasBoomUOP](brupdate: BrUpdateInfo, flush: Bool, bundle: Valid[T]): Valid[T] = {
val out = WireInit(bundle)
out.bits.uop.br_mask := GetNewBrMask(brupdate, bundle.bits.uop.br_mask)
out.valid := bundle.valid && !IsKilledByBranch(brupdate, flush, bundle.bits.uop.br_mask)
out
}
}
/**
* Object to check if at least 1 bit matches in two masks
*/
object maskMatch
{
def apply(msk1: UInt, msk2: UInt): Bool = (msk1 & msk2) =/= 0.U
}
/**
* Object to clear one bit in a mask given an index
*/
object clearMaskBit
{
def apply(msk: UInt, idx: UInt): UInt = (msk & ~(1.U << idx))(msk.getWidth-1, 0)
}
/**
* Object to shift a register over by one bit and concat a new one
*/
object PerformShiftRegister
{
def apply(reg_val: UInt, new_bit: Bool): UInt = {
reg_val := Cat(reg_val(reg_val.getWidth-1, 0).asUInt, new_bit.asUInt).asUInt
reg_val
}
}
/**
* Object to shift a register over by one bit, wrapping the top bit around to the bottom
* (XOR'ed with a new-bit), and evicting a bit at index HLEN.
* This is used to simulate a longer HLEN-width shift register that is folded
* down to a compressed CLEN.
*/
object PerformCircularShiftRegister
{
def apply(csr: UInt, new_bit: Bool, evict_bit: Bool, hlen: Int, clen: Int): UInt = {
val carry = csr(clen-1)
val newval = Cat(csr, new_bit ^ carry) ^ (evict_bit << (hlen % clen).U)
newval
}
}
/**
* Object to increment an input value, wrapping it if
* necessary.
*/
object WrapAdd
{
// "n" is the number of increments, so we wrap at n-1.
def apply(value: UInt, amt: UInt, n: Int): UInt = {
if (isPow2(n)) {
(value + amt)(log2Ceil(n)-1,0)
} else {
val sum = Cat(0.U(1.W), value) + Cat(0.U(1.W), amt)
Mux(sum >= n.U,
sum - n.U,
sum)
}
}
}
/**
* Object to decrement an input value, wrapping it if
* necessary.
*/
object WrapSub
{
// "n" is the number of increments, so we wrap to n-1.
def apply(value: UInt, amt: Int, n: Int): UInt = {
if (isPow2(n)) {
(value - amt.U)(log2Ceil(n)-1,0)
} else {
val v = Cat(0.U(1.W), value)
val b = Cat(0.U(1.W), amt.U)
Mux(value >= amt.U,
value - amt.U,
n.U - amt.U + value)
}
}
}
/**
* Object to increment an input value, wrapping it if
* necessary.
*/
object WrapInc
{
// "n" is the number of increments, so we wrap at n-1.
def apply(value: UInt, n: Int): UInt = {
if (isPow2(n)) {
(value + 1.U)(log2Ceil(n)-1,0)
} else {
val wrap = (value === (n-1).U)
Mux(wrap, 0.U, value + 1.U)
}
}
}
/**
* Object to decrement an input value, wrapping it if
* necessary.
*/
object WrapDec
{
// "n" is the number of increments, so we wrap at n-1.
def apply(value: UInt, n: Int): UInt = {
if (isPow2(n)) {
(value - 1.U)(log2Ceil(n)-1,0)
} else {
val wrap = (value === 0.U)
Mux(wrap, (n-1).U, value - 1.U)
}
}
}
/**
* Object to mask off lower bits of a PC to align to a "b"
* Byte boundary.
*/
object AlignPCToBoundary
{
def apply(pc: UInt, b: Int): UInt = {
// Invert for scenario where pc longer than b
// (which would clear all bits above size(b)).
~(~pc | (b-1).U)
}
}
/**
* Object to rotate a signal left by one
*/
object RotateL1
{
def apply(signal: UInt): UInt = {
val w = signal.getWidth
val out = Cat(signal(w-2,0), signal(w-1))
return out
}
}
/**
* Object to sext a value to a particular length.
*/
object Sext
{
def apply(x: UInt, length: Int): UInt = {
if (x.getWidth == length) return x
else return Cat(Fill(length-x.getWidth, x(x.getWidth-1)), x)
}
}
/**
* Object to translate from BOOM's special "packed immediate" to a 32b signed immediate
* Asking for U-type gives it shifted up 12 bits.
*/
object ImmGen
{
import boom.v4.common.{LONGEST_IMM_SZ, IS_B, IS_I, IS_J, IS_S, IS_U, IS_N}
def apply(i: UInt, isel: UInt): UInt = {
val ip = Mux(isel === IS_N, 0.U(LONGEST_IMM_SZ.W), i)
val sign = ip(LONGEST_IMM_SZ-1).asSInt
val i30_20 = Mux(isel === IS_U, ip(18,8).asSInt, sign)
val i19_12 = Mux(isel === IS_U || isel === IS_J, ip(7,0).asSInt, sign)
val i11 = Mux(isel === IS_U, 0.S,
Mux(isel === IS_J || isel === IS_B, ip(8).asSInt, sign))
val i10_5 = Mux(isel === IS_U, 0.S, ip(18,14).asSInt)
val i4_1 = Mux(isel === IS_U, 0.S, ip(13,9).asSInt)
val i0 = Mux(isel === IS_S || isel === IS_I, ip(8).asSInt, 0.S)
return Cat(sign, i30_20, i19_12, i11, i10_5, i4_1, i0)
}
}
/**
* Object to see if an instruction is a JALR.
*/
object DebugIsJALR
{
def apply(inst: UInt): Bool = {
// TODO Chisel not sure why this won't compile
// val is_jalr = rocket.DecodeLogic(inst, List(Bool(false)),
// Array(
// JALR -> Bool(true)))
inst(6,0) === "b1100111".U
}
}
/**
* Object to take an instruction and output its branch or jal target. Only used
* for a debug assert (no where else would we jump straight from instruction
* bits to a target).
*/
object DebugGetBJImm
{
def apply(inst: UInt): UInt = {
// TODO Chisel not sure why this won't compile
//val csignals =
//rocket.DecodeLogic(inst,
// List(Bool(false), Bool(false)),
// Array(
// BEQ -> List(Bool(true ), Bool(false)),
// BNE -> List(Bool(true ), Bool(false)),
// BGE -> List(Bool(true ), Bool(false)),
// BGEU -> List(Bool(true ), Bool(false)),
// BLT -> List(Bool(true ), Bool(false)),
// BLTU -> List(Bool(true ), Bool(false))
// ))
//val is_br :: nothing :: Nil = csignals
val is_br = (inst(6,0) === "b1100011".U)
val br_targ = Cat(Fill(12, inst(31)), Fill(8,inst(31)), inst(7), inst(30,25), inst(11,8), 0.U(1.W))
val jal_targ= Cat(Fill(12, inst(31)), inst(19,12), inst(20), inst(30,25), inst(24,21), 0.U(1.W))
Mux(is_br, br_targ, jal_targ)
}
}
/**
* Object to return the lowest bit position after the head.
*/
object AgePriorityEncoder
{
def apply(in: Seq[Bool], head: UInt): UInt = {
val n = in.size
val width = log2Ceil(in.size)
val n_padded = 1 << width
val temp_vec = (0 until n_padded).map(i => if (i < n) in(i) && i.U >= head else false.B) ++ in
val idx = PriorityEncoder(temp_vec)
idx(width-1, 0) //discard msb
}
}
/**
* Object to determine whether queue
* index i0 is older than index i1.
*/
object IsOlder
{
def apply(i0: UInt, i1: UInt, head: UInt) = ((i0 < i1) ^ (i0 < head) ^ (i1 < head))
}
object IsYoungerMask
{
def apply(i: UInt, head: UInt, n: Integer): UInt = {
val hi_mask = ~MaskLower(UIntToOH(i)(n-1,0))
val lo_mask = ~MaskUpper(UIntToOH(head)(n-1,0))
Mux(i < head, hi_mask & lo_mask, hi_mask | lo_mask)(n-1,0)
}
}
/**
* Set all bits at or below the highest order '1'.
*/
object MaskLower
{
def apply(in: UInt) = {
val n = in.getWidth
(0 until n).map(i => in >> i.U).reduce(_|_)
}
}
/**
* Set all bits at or above the lowest order '1'.
*/
object MaskUpper
{
def apply(in: UInt) = {
val n = in.getWidth
(0 until n).map(i => (in << i.U)(n-1,0)).reduce(_|_)
}
}
/**
* Transpose a matrix of Chisel Vecs.
*/
object Transpose
{
def apply[T <: chisel3.Data](in: Vec[Vec[T]]) = {
val n = in(0).size
VecInit((0 until n).map(i => VecInit(in.map(row => row(i)))))
}
}
/**
* N-wide one-hot priority encoder.
*/
object SelectFirstN
{
def apply(in: UInt, n: Int) = {
val sels = Wire(Vec(n, UInt(in.getWidth.W)))
var mask = in
for (i <- 0 until n) {
sels(i) := PriorityEncoderOH(mask)
mask = mask & ~sels(i)
}
sels
}
}
/**
* Connect the first k of n valid input interfaces to k output interfaces.
*/
class Compactor[T <: chisel3.Data](n: Int, k: Int, gen: T) extends Module
{
require(n >= k)
val io = IO(new Bundle {
val in = Vec(n, Flipped(DecoupledIO(gen)))
val out = Vec(k, DecoupledIO(gen))
})
if (n == k) {
io.out <> io.in
} else {
val counts = io.in.map(_.valid).scanLeft(1.U(k.W)) ((c,e) => Mux(e, (c<<1)(k-1,0), c))
val sels = Transpose(VecInit(counts map (c => VecInit(c.asBools)))) map (col =>
(col zip io.in.map(_.valid)) map {case (c,v) => c && v})
val in_readys = counts map (row => (row.asBools zip io.out.map(_.ready)) map {case (c,r) => c && r} reduce (_||_))
val out_valids = sels map (col => col.reduce(_||_))
val out_data = sels map (s => Mux1H(s, io.in.map(_.bits)))
in_readys zip io.in foreach {case (r,i) => i.ready := r}
out_valids zip out_data zip io.out foreach {case ((v,d),o) => o.valid := v; o.bits := d}
}
}
/**
* Create a queue that can be killed with a branch kill signal.
* Assumption: enq.valid only high if not killed by branch (so don't check IsKilled on io.enq).
*/
class BranchKillableQueue[T <: boom.v4.common.HasBoomUOP](gen: T, entries: Int, flush_fn: boom.v4.common.MicroOp => Bool = u => true.B, fastDeq: Boolean = false)
(implicit p: org.chipsalliance.cde.config.Parameters)
extends boom.v4.common.BoomModule()(p)
with boom.v4.common.HasBoomCoreParameters
{
val io = IO(new Bundle {
val enq = Flipped(Decoupled(gen))
val deq = Decoupled(gen)
val brupdate = Input(new BrUpdateInfo())
val flush = Input(Bool())
val empty = Output(Bool())
val count = Output(UInt(log2Ceil(entries).W))
})
if (fastDeq && entries > 1) {
// Pipeline dequeue selection so the mux gets an entire cycle
val main = Module(new BranchKillableQueue(gen, entries-1, flush_fn, false))
val out_reg = Reg(gen)
val out_valid = RegInit(false.B)
val out_uop = Reg(new MicroOp)
main.io.enq <> io.enq
main.io.brupdate := io.brupdate
main.io.flush := io.flush
io.empty := main.io.empty && !out_valid
io.count := main.io.count + out_valid
io.deq.valid := out_valid
io.deq.bits := out_reg
io.deq.bits.uop := out_uop
out_uop := UpdateBrMask(io.brupdate, out_uop)
out_valid := out_valid && !IsKilledByBranch(io.brupdate, false.B, out_uop) && !(io.flush && flush_fn(out_uop))
main.io.deq.ready := false.B
when (io.deq.fire || !out_valid) {
out_valid := main.io.deq.valid && !IsKilledByBranch(io.brupdate, false.B, main.io.deq.bits.uop) && !(io.flush && flush_fn(main.io.deq.bits.uop))
out_reg := main.io.deq.bits
out_uop := UpdateBrMask(io.brupdate, main.io.deq.bits.uop)
main.io.deq.ready := true.B
}
} else {
val ram = Mem(entries, gen)
val valids = RegInit(VecInit(Seq.fill(entries) {false.B}))
val uops = Reg(Vec(entries, new MicroOp))
val enq_ptr = Counter(entries)
val deq_ptr = Counter(entries)
val maybe_full = RegInit(false.B)
val ptr_match = enq_ptr.value === deq_ptr.value
io.empty := ptr_match && !maybe_full
val full = ptr_match && maybe_full
val do_enq = WireInit(io.enq.fire && !IsKilledByBranch(io.brupdate, false.B, io.enq.bits.uop) && !(io.flush && flush_fn(io.enq.bits.uop)))
val do_deq = WireInit((io.deq.ready || !valids(deq_ptr.value)) && !io.empty)
for (i <- 0 until entries) {
val mask = uops(i).br_mask
val uop = uops(i)
valids(i) := valids(i) && !IsKilledByBranch(io.brupdate, false.B, mask) && !(io.flush && flush_fn(uop))
when (valids(i)) {
uops(i).br_mask := GetNewBrMask(io.brupdate, mask)
}
}
when (do_enq) {
ram(enq_ptr.value) := io.enq.bits
valids(enq_ptr.value) := true.B
uops(enq_ptr.value) := io.enq.bits.uop
uops(enq_ptr.value).br_mask := GetNewBrMask(io.brupdate, io.enq.bits.uop)
enq_ptr.inc()
}
when (do_deq) {
valids(deq_ptr.value) := false.B
deq_ptr.inc()
}
when (do_enq =/= do_deq) {
maybe_full := do_enq
}
io.enq.ready := !full
val out = Wire(gen)
out := ram(deq_ptr.value)
out.uop := uops(deq_ptr.value)
io.deq.valid := !io.empty && valids(deq_ptr.value)
io.deq.bits := out
val ptr_diff = enq_ptr.value - deq_ptr.value
if (isPow2(entries)) {
io.count := Cat(maybe_full && ptr_match, ptr_diff)
}
else {
io.count := Mux(ptr_match,
Mux(maybe_full,
entries.asUInt, 0.U),
Mux(deq_ptr.value > enq_ptr.value,
entries.asUInt + ptr_diff, ptr_diff))
}
}
}
// ------------------------------------------
// Printf helper functions
// ------------------------------------------
object BoolToChar
{
/**
* Take in a Chisel Bool and convert it into a Str
* based on the Chars given
*
* @param c_bool Chisel Bool
* @param trueChar Scala Char if bool is true
* @param falseChar Scala Char if bool is false
* @return UInt ASCII Char for "trueChar" or "falseChar"
*/
def apply(c_bool: Bool, trueChar: Char, falseChar: Char = '-'): UInt = {
Mux(c_bool, Str(trueChar), Str(falseChar))
}
}
object CfiTypeToChars
{
/**
* Get a Vec of Strs that can be used for printing
*
* @param cfi_type specific cfi type
* @return Vec of Strs (must be indexed to get specific char)
*/
def apply(cfi_type: UInt) = {
val strings = Seq("----", "BR ", "JAL ", "JALR")
val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })
multiVec(cfi_type)
}
}
object BpdTypeToChars
{
/**
* Get a Vec of Strs that can be used for printing
*
* @param bpd_type specific bpd type
* @return Vec of Strs (must be indexed to get specific char)
*/
def apply(bpd_type: UInt) = {
val strings = Seq("BR ", "JUMP", "----", "RET ", "----", "CALL", "----", "----")
val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })
multiVec(bpd_type)
}
}
object RobTypeToChars
{
/**
* Get a Vec of Strs that can be used for printing
*
* @param rob_type specific rob type
* @return Vec of Strs (must be indexed to get specific char)
*/
def apply(rob_type: UInt) = {
val strings = Seq("RST", "NML", "RBK", " WT")
val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })
multiVec(rob_type)
}
}
object XRegToChars
{
/**
* Get a Vec of Strs that can be used for printing
*
* @param xreg specific register number
* @return Vec of Strs (must be indexed to get specific char)
*/
def apply(xreg: UInt) = {
val strings = Seq(" x0", " ra", " sp", " gp",
" tp", " t0", " t1", " t2",
" s0", " s1", " a0", " a1",
" a2", " a3", " a4", " a5",
" a6", " a7", " s2", " s3",
" s4", " s5", " s6", " s7",
" s8", " s9", "s10", "s11",
" t3", " t4", " t5", " t6")
val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })
multiVec(xreg)
}
}
object FPRegToChars
{
/**
* Get a Vec of Strs that can be used for printing
*
* @param fpreg specific register number
* @return Vec of Strs (must be indexed to get specific char)
*/
def apply(fpreg: UInt) = {
val strings = Seq(" ft0", " ft1", " ft2", " ft3",
" ft4", " ft5", " ft6", " ft7",
" fs0", " fs1", " fa0", " fa1",
" fa2", " fa3", " fa4", " fa5",
" fa6", " fa7", " fs2", " fs3",
" fs4", " fs5", " fs6", " fs7",
" fs8", " fs9", "fs10", "fs11",
" ft8", " ft9", "ft10", "ft11")
val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })
multiVec(fpreg)
}
}
object BoomCoreStringPrefix
{
/**
* Add prefix to BOOM strings (currently only adds the hartId)
*
* @param strs list of strings
* @return String combining the list with the prefix per line
*/
def apply(strs: String*)(implicit p: Parameters) = {
val prefix = "[C" + s"${p(TileKey).tileId}" + "] "
strs.map(str => prefix + str + "\n").mkString("")
}
}
class BranchKillablePipeline[T <: boom.v4.common.HasBoomUOP](gen: T, stages: Int)
(implicit p: org.chipsalliance.cde.config.Parameters)
extends boom.v4.common.BoomModule()(p)
with boom.v4.common.HasBoomCoreParameters
{
val io = IO(new Bundle {
val req = Input(Valid(gen))
val flush = Input(Bool())
val brupdate = Input(new BrUpdateInfo)
val resp = Output(Vec(stages, Valid(gen)))
})
require(stages > 0)
val uops = Reg(Vec(stages, Valid(gen)))
uops(0).valid := io.req.valid && !IsKilledByBranch(io.brupdate, io.flush, io.req.bits)
uops(0).bits := UpdateBrMask(io.brupdate, io.req.bits)
for (i <- 1 until stages) {
uops(i).valid := uops(i-1).valid && !IsKilledByBranch(io.brupdate, io.flush, uops(i-1).bits)
uops(i).bits := UpdateBrMask(io.brupdate, uops(i-1).bits)
}
for (i <- 0 until stages) { when (reset.asBool) { uops(i).valid := false.B } }
io.resp := uops
}
File issue-slot.scala:
//******************************************************************************
// Copyright (c) 2015 - 2018, The Regents of the University of California (Regents).
// All Rights Reserved. See LICENSE and LICENSE.SiFive for license details.
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
// RISCV Processor Issue Slot Logic
//--------------------------------------------------------------------------
//------------------------------------------------------------------------------
//
// Note: stores (and AMOs) are "broken down" into 2 uops, but stored within a single issue-slot.
// TODO XXX make a separate issueSlot for MemoryIssueSlots, and only they break apart stores.
// TODO Disable ldspec for FP queue.
package boom.v4.exu
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.Parameters
import boom.v4.common._
import boom.v4.util._
class IssueSlotIO(val numWakeupPorts: Int)(implicit p: Parameters) extends BoomBundle
{
val valid = Output(Bool())
val will_be_valid = Output(Bool()) // TODO code review, do we need this signal so explicitely?
val request = Output(Bool())
val grant = Input(Bool())
val iss_uop = Output(new MicroOp())
val in_uop = Input(Valid(new MicroOp())) // if valid, this WILL overwrite an entry!
val out_uop = Output(new MicroOp())
val brupdate = Input(new BrUpdateInfo())
val kill = Input(Bool()) // pipeline flush
val clear = Input(Bool()) // entry being moved elsewhere (not mutually exclusive with grant)
val squash_grant = Input(Bool())
val wakeup_ports = Flipped(Vec(numWakeupPorts, Valid(new Wakeup)))
val pred_wakeup_port = Flipped(Valid(UInt(log2Ceil(ftqSz).W)))
val child_rebusys = Input(UInt(aluWidth.W))
}
class IssueSlot(val numWakeupPorts: Int, val isMem: Boolean, val isFp: Boolean)(implicit p: Parameters)
extends BoomModule
{
val io = IO(new IssueSlotIO(numWakeupPorts))
val slot_valid = RegInit(false.B)
val slot_uop = Reg(new MicroOp())
val next_valid = WireInit(slot_valid)
val next_uop = WireInit(UpdateBrMask(io.brupdate, slot_uop))
val killed = IsKilledByBranch(io.brupdate, io.kill, slot_uop)
io.valid := slot_valid
io.out_uop := next_uop
io.will_be_valid := next_valid && !killed
when (io.kill) {
slot_valid := false.B
} .elsewhen (io.in_uop.valid) {
slot_valid := true.B
} .elsewhen (io.clear) {
slot_valid := false.B
} .otherwise {
slot_valid := next_valid && !killed
}
when (io.in_uop.valid) {
slot_uop := io.in_uop.bits
assert (!slot_valid || io.clear || io.kill)
} .otherwise {
slot_uop := next_uop
}
// Wakeups
next_uop.iw_p1_bypass_hint := false.B
next_uop.iw_p2_bypass_hint := false.B
next_uop.iw_p3_bypass_hint := false.B
next_uop.iw_p1_speculative_child := 0.U
next_uop.iw_p2_speculative_child := 0.U
val rebusied_prs1 = WireInit(false.B)
val rebusied_prs2 = WireInit(false.B)
val rebusied = rebusied_prs1 || rebusied_prs2
val prs1_matches = io.wakeup_ports.map { w => w.bits.uop.pdst === slot_uop.prs1 }
val prs2_matches = io.wakeup_ports.map { w => w.bits.uop.pdst === slot_uop.prs2 }
val prs3_matches = io.wakeup_ports.map { w => w.bits.uop.pdst === slot_uop.prs3 }
val prs1_wakeups = (io.wakeup_ports zip prs1_matches).map { case (w,m) => w.valid && m }
val prs2_wakeups = (io.wakeup_ports zip prs2_matches).map { case (w,m) => w.valid && m }
val prs3_wakeups = (io.wakeup_ports zip prs3_matches).map { case (w,m) => w.valid && m }
val prs1_rebusys = (io.wakeup_ports zip prs1_matches).map { case (w,m) => w.bits.rebusy && m }
val prs2_rebusys = (io.wakeup_ports zip prs2_matches).map { case (w,m) => w.bits.rebusy && m }
val bypassables = io.wakeup_ports.map { w => w.bits.bypassable }
val speculative_masks = io.wakeup_ports.map { w => w.bits.speculative_mask }
when (prs1_wakeups.reduce(_||_)) {
next_uop.prs1_busy := false.B
next_uop.iw_p1_speculative_child := Mux1H(prs1_wakeups, speculative_masks)
next_uop.iw_p1_bypass_hint := Mux1H(prs1_wakeups, bypassables)
}
when ((prs1_rebusys.reduce(_||_) || ((io.child_rebusys & slot_uop.iw_p1_speculative_child) =/= 0.U)) &&
slot_uop.lrs1_rtype === RT_FIX) {
next_uop.prs1_busy := true.B
rebusied_prs1 := true.B
}
when (prs2_wakeups.reduce(_||_)) {
next_uop.prs2_busy := false.B
next_uop.iw_p2_speculative_child := Mux1H(prs2_wakeups, speculative_masks)
next_uop.iw_p2_bypass_hint := Mux1H(prs2_wakeups, bypassables)
}
when ((prs2_rebusys.reduce(_||_) || ((io.child_rebusys & slot_uop.iw_p2_speculative_child) =/= 0.U)) &&
slot_uop.lrs2_rtype === RT_FIX) {
next_uop.prs2_busy := true.B
rebusied_prs2 := true.B
}
when (prs3_wakeups.reduce(_||_)) {
next_uop.prs3_busy := false.B
next_uop.iw_p3_bypass_hint := Mux1H(prs3_wakeups, bypassables)
}
when (io.pred_wakeup_port.valid && io.pred_wakeup_port.bits === slot_uop.ppred) {
next_uop.ppred_busy := false.B
}
val iss_ready = !slot_uop.prs1_busy && !slot_uop.prs2_busy && !(slot_uop.ppred_busy && enableSFBOpt.B) && !(slot_uop.prs3_busy && isFp.B)
val agen_ready = (slot_uop.fu_code(FC_AGEN) && !slot_uop.prs1_busy && !(slot_uop.ppred_busy && enableSFBOpt.B) && isMem.B)
val dgen_ready = (slot_uop.fu_code(FC_DGEN) && !slot_uop.prs2_busy && !(slot_uop.ppred_busy && enableSFBOpt.B) && isMem.B)
io.request := slot_valid && !slot_uop.iw_issued && (
iss_ready || agen_ready || dgen_ready
)
io.iss_uop := slot_uop
// Update state for current micro-op based on grant
next_uop.iw_issued := false.B
next_uop.iw_issued_partial_agen := false.B
next_uop.iw_issued_partial_dgen := false.B
when (io.grant && !io.squash_grant) {
next_uop.iw_issued := true.B
}
if (isMem) {
when (slot_uop.fu_code(FC_AGEN) && slot_uop.fu_code(FC_DGEN)) {
when (agen_ready) {
// Issue the AGEN, next slot entry is a DGEN
when (io.grant && !io.squash_grant) {
next_uop.iw_issued_partial_agen := true.B
}
io.iss_uop.fu_code(FC_AGEN) := true.B
io.iss_uop.fu_code(FC_DGEN) := false.B
} .otherwise {
// Issue the DGEN, next slot entry is the AGEN
when (io.grant && !io.squash_grant) {
next_uop.iw_issued_partial_dgen := true.B
}
io.iss_uop.fu_code(FC_AGEN) := false.B
io.iss_uop.fu_code(FC_DGEN) := true.B
io.iss_uop.imm_sel := IS_N
io.iss_uop.prs1 := slot_uop.prs2
io.iss_uop.lrs1_rtype := slot_uop.lrs2_rtype
io.iss_uop.iw_p1_bypass_hint := slot_uop.iw_p2_bypass_hint
}
} .elsewhen (slot_uop.fu_code(FC_DGEN)) {
io.iss_uop.imm_sel := IS_N
io.iss_uop.prs1 := slot_uop.prs2
io.iss_uop.lrs1_rtype := slot_uop.lrs2_rtype
io.iss_uop.iw_p1_bypass_hint := slot_uop.iw_p2_bypass_hint
}
io.iss_uop.lrs2_rtype := RT_X
io.iss_uop.prs2 := io.iss_uop.prs1 // helps with DCE
}
when (slot_valid && slot_uop.iw_issued) {
next_valid := rebusied
if (isMem) {
when (slot_uop.iw_issued_partial_agen) {
next_valid := true.B
when (!rebusied_prs1) {
next_uop.fu_code(FC_AGEN) := false.B
next_uop.fu_code(FC_DGEN) := true.B
}
} .elsewhen (slot_uop.iw_issued_partial_dgen) {
next_valid := true.B
when (!rebusied_prs2) {
next_uop.fu_code(FC_AGEN) := true.B
next_uop.fu_code(FC_DGEN) := false.B
}
}
}
}
}
| module IssueSlot_28( // @[issue-slot.scala:49:7]
input clock, // @[issue-slot.scala:49:7]
input reset, // @[issue-slot.scala:49:7]
output io_valid, // @[issue-slot.scala:52:14]
output io_will_be_valid, // @[issue-slot.scala:52:14]
output io_request, // @[issue-slot.scala:52:14]
input io_grant, // @[issue-slot.scala:52:14]
output [31:0] io_iss_uop_inst, // @[issue-slot.scala:52:14]
output [31:0] io_iss_uop_debug_inst, // @[issue-slot.scala:52:14]
output io_iss_uop_is_rvc, // @[issue-slot.scala:52:14]
output [39:0] io_iss_uop_debug_pc, // @[issue-slot.scala:52:14]
output io_iss_uop_iq_type_0, // @[issue-slot.scala:52:14]
output io_iss_uop_iq_type_1, // @[issue-slot.scala:52:14]
output io_iss_uop_iq_type_2, // @[issue-slot.scala:52:14]
output io_iss_uop_iq_type_3, // @[issue-slot.scala:52:14]
output io_iss_uop_fu_code_0, // @[issue-slot.scala:52:14]
output io_iss_uop_fu_code_1, // @[issue-slot.scala:52:14]
output io_iss_uop_fu_code_2, // @[issue-slot.scala:52:14]
output io_iss_uop_fu_code_3, // @[issue-slot.scala:52:14]
output io_iss_uop_fu_code_4, // @[issue-slot.scala:52:14]
output io_iss_uop_fu_code_5, // @[issue-slot.scala:52:14]
output io_iss_uop_fu_code_6, // @[issue-slot.scala:52:14]
output io_iss_uop_fu_code_7, // @[issue-slot.scala:52:14]
output io_iss_uop_fu_code_8, // @[issue-slot.scala:52:14]
output io_iss_uop_fu_code_9, // @[issue-slot.scala:52:14]
output io_iss_uop_iw_issued, // @[issue-slot.scala:52:14]
output [1:0] io_iss_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14]
output [1:0] io_iss_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14]
output io_iss_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14]
output io_iss_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14]
output io_iss_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14]
output [1:0] io_iss_uop_dis_col_sel, // @[issue-slot.scala:52:14]
output [11:0] io_iss_uop_br_mask, // @[issue-slot.scala:52:14]
output [3:0] io_iss_uop_br_tag, // @[issue-slot.scala:52:14]
output [3:0] io_iss_uop_br_type, // @[issue-slot.scala:52:14]
output io_iss_uop_is_sfb, // @[issue-slot.scala:52:14]
output io_iss_uop_is_fence, // @[issue-slot.scala:52:14]
output io_iss_uop_is_fencei, // @[issue-slot.scala:52:14]
output io_iss_uop_is_sfence, // @[issue-slot.scala:52:14]
output io_iss_uop_is_amo, // @[issue-slot.scala:52:14]
output io_iss_uop_is_eret, // @[issue-slot.scala:52:14]
output io_iss_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14]
output io_iss_uop_is_rocc, // @[issue-slot.scala:52:14]
output io_iss_uop_is_mov, // @[issue-slot.scala:52:14]
output [4:0] io_iss_uop_ftq_idx, // @[issue-slot.scala:52:14]
output io_iss_uop_edge_inst, // @[issue-slot.scala:52:14]
output [5:0] io_iss_uop_pc_lob, // @[issue-slot.scala:52:14]
output io_iss_uop_taken, // @[issue-slot.scala:52:14]
output io_iss_uop_imm_rename, // @[issue-slot.scala:52:14]
output [2:0] io_iss_uop_imm_sel, // @[issue-slot.scala:52:14]
output [4:0] io_iss_uop_pimm, // @[issue-slot.scala:52:14]
output [19:0] io_iss_uop_imm_packed, // @[issue-slot.scala:52:14]
output [1:0] io_iss_uop_op1_sel, // @[issue-slot.scala:52:14]
output [2:0] io_iss_uop_op2_sel, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14]
output [1:0] io_iss_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14]
output [1:0] io_iss_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_div, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14]
output [5:0] io_iss_uop_rob_idx, // @[issue-slot.scala:52:14]
output [3:0] io_iss_uop_ldq_idx, // @[issue-slot.scala:52:14]
output [3:0] io_iss_uop_stq_idx, // @[issue-slot.scala:52:14]
output [1:0] io_iss_uop_rxq_idx, // @[issue-slot.scala:52:14]
output [6:0] io_iss_uop_pdst, // @[issue-slot.scala:52:14]
output [6:0] io_iss_uop_prs1, // @[issue-slot.scala:52:14]
output [6:0] io_iss_uop_prs2, // @[issue-slot.scala:52:14]
output [6:0] io_iss_uop_prs3, // @[issue-slot.scala:52:14]
output [4:0] io_iss_uop_ppred, // @[issue-slot.scala:52:14]
output io_iss_uop_prs1_busy, // @[issue-slot.scala:52:14]
output io_iss_uop_prs2_busy, // @[issue-slot.scala:52:14]
output io_iss_uop_prs3_busy, // @[issue-slot.scala:52:14]
output io_iss_uop_ppred_busy, // @[issue-slot.scala:52:14]
output [6:0] io_iss_uop_stale_pdst, // @[issue-slot.scala:52:14]
output io_iss_uop_exception, // @[issue-slot.scala:52:14]
output [63:0] io_iss_uop_exc_cause, // @[issue-slot.scala:52:14]
output [4:0] io_iss_uop_mem_cmd, // @[issue-slot.scala:52:14]
output [1:0] io_iss_uop_mem_size, // @[issue-slot.scala:52:14]
output io_iss_uop_mem_signed, // @[issue-slot.scala:52:14]
output io_iss_uop_uses_ldq, // @[issue-slot.scala:52:14]
output io_iss_uop_uses_stq, // @[issue-slot.scala:52:14]
output io_iss_uop_is_unique, // @[issue-slot.scala:52:14]
output io_iss_uop_flush_on_commit, // @[issue-slot.scala:52:14]
output [2:0] io_iss_uop_csr_cmd, // @[issue-slot.scala:52:14]
output io_iss_uop_ldst_is_rs1, // @[issue-slot.scala:52:14]
output [5:0] io_iss_uop_ldst, // @[issue-slot.scala:52:14]
output [5:0] io_iss_uop_lrs1, // @[issue-slot.scala:52:14]
output [5:0] io_iss_uop_lrs2, // @[issue-slot.scala:52:14]
output [5:0] io_iss_uop_lrs3, // @[issue-slot.scala:52:14]
output [1:0] io_iss_uop_dst_rtype, // @[issue-slot.scala:52:14]
output [1:0] io_iss_uop_lrs1_rtype, // @[issue-slot.scala:52:14]
output [1:0] io_iss_uop_lrs2_rtype, // @[issue-slot.scala:52:14]
output io_iss_uop_frs3_en, // @[issue-slot.scala:52:14]
output io_iss_uop_fcn_dw, // @[issue-slot.scala:52:14]
output [4:0] io_iss_uop_fcn_op, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_val, // @[issue-slot.scala:52:14]
output [2:0] io_iss_uop_fp_rm, // @[issue-slot.scala:52:14]
output [1:0] io_iss_uop_fp_typ, // @[issue-slot.scala:52:14]
output io_iss_uop_xcpt_pf_if, // @[issue-slot.scala:52:14]
output io_iss_uop_xcpt_ae_if, // @[issue-slot.scala:52:14]
output io_iss_uop_xcpt_ma_if, // @[issue-slot.scala:52:14]
output io_iss_uop_bp_debug_if, // @[issue-slot.scala:52:14]
output io_iss_uop_bp_xcpt_if, // @[issue-slot.scala:52:14]
output [2:0] io_iss_uop_debug_fsrc, // @[issue-slot.scala:52:14]
output [2:0] io_iss_uop_debug_tsrc, // @[issue-slot.scala:52:14]
input io_in_uop_valid, // @[issue-slot.scala:52:14]
input [31:0] io_in_uop_bits_inst, // @[issue-slot.scala:52:14]
input [31:0] io_in_uop_bits_debug_inst, // @[issue-slot.scala:52:14]
input io_in_uop_bits_is_rvc, // @[issue-slot.scala:52:14]
input [39:0] io_in_uop_bits_debug_pc, // @[issue-slot.scala:52:14]
input io_in_uop_bits_iq_type_0, // @[issue-slot.scala:52:14]
input io_in_uop_bits_iq_type_1, // @[issue-slot.scala:52:14]
input io_in_uop_bits_iq_type_2, // @[issue-slot.scala:52:14]
input io_in_uop_bits_iq_type_3, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fu_code_0, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fu_code_1, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fu_code_2, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fu_code_3, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fu_code_4, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fu_code_5, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fu_code_6, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fu_code_7, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fu_code_8, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fu_code_9, // @[issue-slot.scala:52:14]
input io_in_uop_bits_iw_issued, // @[issue-slot.scala:52:14]
input [1:0] io_in_uop_bits_iw_p1_speculative_child, // @[issue-slot.scala:52:14]
input [1:0] io_in_uop_bits_iw_p2_speculative_child, // @[issue-slot.scala:52:14]
input io_in_uop_bits_iw_p1_bypass_hint, // @[issue-slot.scala:52:14]
input io_in_uop_bits_iw_p2_bypass_hint, // @[issue-slot.scala:52:14]
input io_in_uop_bits_iw_p3_bypass_hint, // @[issue-slot.scala:52:14]
input [1:0] io_in_uop_bits_dis_col_sel, // @[issue-slot.scala:52:14]
input [11:0] io_in_uop_bits_br_mask, // @[issue-slot.scala:52:14]
input [3:0] io_in_uop_bits_br_tag, // @[issue-slot.scala:52:14]
input [3:0] io_in_uop_bits_br_type, // @[issue-slot.scala:52:14]
input io_in_uop_bits_is_sfb, // @[issue-slot.scala:52:14]
input io_in_uop_bits_is_fence, // @[issue-slot.scala:52:14]
input io_in_uop_bits_is_fencei, // @[issue-slot.scala:52:14]
input io_in_uop_bits_is_sfence, // @[issue-slot.scala:52:14]
input io_in_uop_bits_is_amo, // @[issue-slot.scala:52:14]
input io_in_uop_bits_is_eret, // @[issue-slot.scala:52:14]
input io_in_uop_bits_is_sys_pc2epc, // @[issue-slot.scala:52:14]
input io_in_uop_bits_is_rocc, // @[issue-slot.scala:52:14]
input io_in_uop_bits_is_mov, // @[issue-slot.scala:52:14]
input [4:0] io_in_uop_bits_ftq_idx, // @[issue-slot.scala:52:14]
input io_in_uop_bits_edge_inst, // @[issue-slot.scala:52:14]
input [5:0] io_in_uop_bits_pc_lob, // @[issue-slot.scala:52:14]
input io_in_uop_bits_taken, // @[issue-slot.scala:52:14]
input io_in_uop_bits_imm_rename, // @[issue-slot.scala:52:14]
input [2:0] io_in_uop_bits_imm_sel, // @[issue-slot.scala:52:14]
input [4:0] io_in_uop_bits_pimm, // @[issue-slot.scala:52:14]
input [19:0] io_in_uop_bits_imm_packed, // @[issue-slot.scala:52:14]
input [1:0] io_in_uop_bits_op1_sel, // @[issue-slot.scala:52:14]
input [2:0] io_in_uop_bits_op2_sel, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_ldst, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_wen, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_ren1, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_ren2, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_ren3, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_swap12, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_swap23, // @[issue-slot.scala:52:14]
input [1:0] io_in_uop_bits_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14]
input [1:0] io_in_uop_bits_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_fromint, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_toint, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_fma, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_div, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_sqrt, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_wflags, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_vec, // @[issue-slot.scala:52:14]
input [5:0] io_in_uop_bits_rob_idx, // @[issue-slot.scala:52:14]
input [3:0] io_in_uop_bits_ldq_idx, // @[issue-slot.scala:52:14]
input [3:0] io_in_uop_bits_stq_idx, // @[issue-slot.scala:52:14]
input [1:0] io_in_uop_bits_rxq_idx, // @[issue-slot.scala:52:14]
input [6:0] io_in_uop_bits_pdst, // @[issue-slot.scala:52:14]
input [6:0] io_in_uop_bits_prs1, // @[issue-slot.scala:52:14]
input [6:0] io_in_uop_bits_prs2, // @[issue-slot.scala:52:14]
input [6:0] io_in_uop_bits_prs3, // @[issue-slot.scala:52:14]
input [4:0] io_in_uop_bits_ppred, // @[issue-slot.scala:52:14]
input io_in_uop_bits_prs1_busy, // @[issue-slot.scala:52:14]
input io_in_uop_bits_prs2_busy, // @[issue-slot.scala:52:14]
input io_in_uop_bits_prs3_busy, // @[issue-slot.scala:52:14]
input io_in_uop_bits_ppred_busy, // @[issue-slot.scala:52:14]
input [6:0] io_in_uop_bits_stale_pdst, // @[issue-slot.scala:52:14]
input io_in_uop_bits_exception, // @[issue-slot.scala:52:14]
input [63:0] io_in_uop_bits_exc_cause, // @[issue-slot.scala:52:14]
input [4:0] io_in_uop_bits_mem_cmd, // @[issue-slot.scala:52:14]
input [1:0] io_in_uop_bits_mem_size, // @[issue-slot.scala:52:14]
input io_in_uop_bits_mem_signed, // @[issue-slot.scala:52:14]
input io_in_uop_bits_uses_ldq, // @[issue-slot.scala:52:14]
input io_in_uop_bits_uses_stq, // @[issue-slot.scala:52:14]
input io_in_uop_bits_is_unique, // @[issue-slot.scala:52:14]
input io_in_uop_bits_flush_on_commit, // @[issue-slot.scala:52:14]
input [2:0] io_in_uop_bits_csr_cmd, // @[issue-slot.scala:52:14]
input io_in_uop_bits_ldst_is_rs1, // @[issue-slot.scala:52:14]
input [5:0] io_in_uop_bits_ldst, // @[issue-slot.scala:52:14]
input [5:0] io_in_uop_bits_lrs1, // @[issue-slot.scala:52:14]
input [5:0] io_in_uop_bits_lrs2, // @[issue-slot.scala:52:14]
input [5:0] io_in_uop_bits_lrs3, // @[issue-slot.scala:52:14]
input [1:0] io_in_uop_bits_dst_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_in_uop_bits_lrs1_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_in_uop_bits_lrs2_rtype, // @[issue-slot.scala:52:14]
input io_in_uop_bits_frs3_en, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fcn_dw, // @[issue-slot.scala:52:14]
input [4:0] io_in_uop_bits_fcn_op, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_val, // @[issue-slot.scala:52:14]
input [2:0] io_in_uop_bits_fp_rm, // @[issue-slot.scala:52:14]
input [1:0] io_in_uop_bits_fp_typ, // @[issue-slot.scala:52:14]
input io_in_uop_bits_xcpt_pf_if, // @[issue-slot.scala:52:14]
input io_in_uop_bits_xcpt_ae_if, // @[issue-slot.scala:52:14]
input io_in_uop_bits_xcpt_ma_if, // @[issue-slot.scala:52:14]
input io_in_uop_bits_bp_debug_if, // @[issue-slot.scala:52:14]
input io_in_uop_bits_bp_xcpt_if, // @[issue-slot.scala:52:14]
input [2:0] io_in_uop_bits_debug_fsrc, // @[issue-slot.scala:52:14]
input [2:0] io_in_uop_bits_debug_tsrc, // @[issue-slot.scala:52:14]
output [31:0] io_out_uop_inst, // @[issue-slot.scala:52:14]
output [31:0] io_out_uop_debug_inst, // @[issue-slot.scala:52:14]
output io_out_uop_is_rvc, // @[issue-slot.scala:52:14]
output [39:0] io_out_uop_debug_pc, // @[issue-slot.scala:52:14]
output io_out_uop_iq_type_0, // @[issue-slot.scala:52:14]
output io_out_uop_iq_type_1, // @[issue-slot.scala:52:14]
output io_out_uop_iq_type_2, // @[issue-slot.scala:52:14]
output io_out_uop_iq_type_3, // @[issue-slot.scala:52:14]
output io_out_uop_fu_code_0, // @[issue-slot.scala:52:14]
output io_out_uop_fu_code_1, // @[issue-slot.scala:52:14]
output io_out_uop_fu_code_2, // @[issue-slot.scala:52:14]
output io_out_uop_fu_code_3, // @[issue-slot.scala:52:14]
output io_out_uop_fu_code_4, // @[issue-slot.scala:52:14]
output io_out_uop_fu_code_5, // @[issue-slot.scala:52:14]
output io_out_uop_fu_code_6, // @[issue-slot.scala:52:14]
output io_out_uop_fu_code_7, // @[issue-slot.scala:52:14]
output io_out_uop_fu_code_8, // @[issue-slot.scala:52:14]
output io_out_uop_fu_code_9, // @[issue-slot.scala:52:14]
output io_out_uop_iw_issued, // @[issue-slot.scala:52:14]
output [1:0] io_out_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14]
output [1:0] io_out_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14]
output io_out_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14]
output io_out_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14]
output io_out_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14]
output [1:0] io_out_uop_dis_col_sel, // @[issue-slot.scala:52:14]
output [11:0] io_out_uop_br_mask, // @[issue-slot.scala:52:14]
output [3:0] io_out_uop_br_tag, // @[issue-slot.scala:52:14]
output [3:0] io_out_uop_br_type, // @[issue-slot.scala:52:14]
output io_out_uop_is_sfb, // @[issue-slot.scala:52:14]
output io_out_uop_is_fence, // @[issue-slot.scala:52:14]
output io_out_uop_is_fencei, // @[issue-slot.scala:52:14]
output io_out_uop_is_sfence, // @[issue-slot.scala:52:14]
output io_out_uop_is_amo, // @[issue-slot.scala:52:14]
output io_out_uop_is_eret, // @[issue-slot.scala:52:14]
output io_out_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14]
output io_out_uop_is_rocc, // @[issue-slot.scala:52:14]
output io_out_uop_is_mov, // @[issue-slot.scala:52:14]
output [4:0] io_out_uop_ftq_idx, // @[issue-slot.scala:52:14]
output io_out_uop_edge_inst, // @[issue-slot.scala:52:14]
output [5:0] io_out_uop_pc_lob, // @[issue-slot.scala:52:14]
output io_out_uop_taken, // @[issue-slot.scala:52:14]
output io_out_uop_imm_rename, // @[issue-slot.scala:52:14]
output [2:0] io_out_uop_imm_sel, // @[issue-slot.scala:52:14]
output [4:0] io_out_uop_pimm, // @[issue-slot.scala:52:14]
output [19:0] io_out_uop_imm_packed, // @[issue-slot.scala:52:14]
output [1:0] io_out_uop_op1_sel, // @[issue-slot.scala:52:14]
output [2:0] io_out_uop_op2_sel, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14]
output [1:0] io_out_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14]
output [1:0] io_out_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_div, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14]
output [5:0] io_out_uop_rob_idx, // @[issue-slot.scala:52:14]
output [3:0] io_out_uop_ldq_idx, // @[issue-slot.scala:52:14]
output [3:0] io_out_uop_stq_idx, // @[issue-slot.scala:52:14]
output [1:0] io_out_uop_rxq_idx, // @[issue-slot.scala:52:14]
output [6:0] io_out_uop_pdst, // @[issue-slot.scala:52:14]
output [6:0] io_out_uop_prs1, // @[issue-slot.scala:52:14]
output [6:0] io_out_uop_prs2, // @[issue-slot.scala:52:14]
output [6:0] io_out_uop_prs3, // @[issue-slot.scala:52:14]
output [4:0] io_out_uop_ppred, // @[issue-slot.scala:52:14]
output io_out_uop_prs1_busy, // @[issue-slot.scala:52:14]
output io_out_uop_prs2_busy, // @[issue-slot.scala:52:14]
output io_out_uop_prs3_busy, // @[issue-slot.scala:52:14]
output io_out_uop_ppred_busy, // @[issue-slot.scala:52:14]
output [6:0] io_out_uop_stale_pdst, // @[issue-slot.scala:52:14]
output io_out_uop_exception, // @[issue-slot.scala:52:14]
output [63:0] io_out_uop_exc_cause, // @[issue-slot.scala:52:14]
output [4:0] io_out_uop_mem_cmd, // @[issue-slot.scala:52:14]
output [1:0] io_out_uop_mem_size, // @[issue-slot.scala:52:14]
output io_out_uop_mem_signed, // @[issue-slot.scala:52:14]
output io_out_uop_uses_ldq, // @[issue-slot.scala:52:14]
output io_out_uop_uses_stq, // @[issue-slot.scala:52:14]
output io_out_uop_is_unique, // @[issue-slot.scala:52:14]
output io_out_uop_flush_on_commit, // @[issue-slot.scala:52:14]
output [2:0] io_out_uop_csr_cmd, // @[issue-slot.scala:52:14]
output io_out_uop_ldst_is_rs1, // @[issue-slot.scala:52:14]
output [5:0] io_out_uop_ldst, // @[issue-slot.scala:52:14]
output [5:0] io_out_uop_lrs1, // @[issue-slot.scala:52:14]
output [5:0] io_out_uop_lrs2, // @[issue-slot.scala:52:14]
output [5:0] io_out_uop_lrs3, // @[issue-slot.scala:52:14]
output [1:0] io_out_uop_dst_rtype, // @[issue-slot.scala:52:14]
output [1:0] io_out_uop_lrs1_rtype, // @[issue-slot.scala:52:14]
output [1:0] io_out_uop_lrs2_rtype, // @[issue-slot.scala:52:14]
output io_out_uop_frs3_en, // @[issue-slot.scala:52:14]
output io_out_uop_fcn_dw, // @[issue-slot.scala:52:14]
output [4:0] io_out_uop_fcn_op, // @[issue-slot.scala:52:14]
output io_out_uop_fp_val, // @[issue-slot.scala:52:14]
output [2:0] io_out_uop_fp_rm, // @[issue-slot.scala:52:14]
output [1:0] io_out_uop_fp_typ, // @[issue-slot.scala:52:14]
output io_out_uop_xcpt_pf_if, // @[issue-slot.scala:52:14]
output io_out_uop_xcpt_ae_if, // @[issue-slot.scala:52:14]
output io_out_uop_xcpt_ma_if, // @[issue-slot.scala:52:14]
output io_out_uop_bp_debug_if, // @[issue-slot.scala:52:14]
output io_out_uop_bp_xcpt_if, // @[issue-slot.scala:52:14]
output [2:0] io_out_uop_debug_fsrc, // @[issue-slot.scala:52:14]
output [2:0] io_out_uop_debug_tsrc, // @[issue-slot.scala:52:14]
input [11:0] io_brupdate_b1_resolve_mask, // @[issue-slot.scala:52:14]
input [11:0] io_brupdate_b1_mispredict_mask, // @[issue-slot.scala:52:14]
input [31:0] io_brupdate_b2_uop_inst, // @[issue-slot.scala:52:14]
input [31:0] io_brupdate_b2_uop_debug_inst, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_is_rvc, // @[issue-slot.scala:52:14]
input [39:0] io_brupdate_b2_uop_debug_pc, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_iq_type_0, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_iq_type_1, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_iq_type_2, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_iq_type_3, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fu_code_0, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fu_code_1, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fu_code_2, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fu_code_3, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fu_code_4, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fu_code_5, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fu_code_6, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fu_code_7, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fu_code_8, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fu_code_9, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_iw_issued, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_iw_issued_partial_agen, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_iw_issued_partial_dgen, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_uop_dis_col_sel, // @[issue-slot.scala:52:14]
input [11:0] io_brupdate_b2_uop_br_mask, // @[issue-slot.scala:52:14]
input [3:0] io_brupdate_b2_uop_br_tag, // @[issue-slot.scala:52:14]
input [3:0] io_brupdate_b2_uop_br_type, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_is_sfb, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_is_fence, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_is_fencei, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_is_sfence, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_is_amo, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_is_eret, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_is_rocc, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_is_mov, // @[issue-slot.scala:52:14]
input [4:0] io_brupdate_b2_uop_ftq_idx, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_edge_inst, // @[issue-slot.scala:52:14]
input [5:0] io_brupdate_b2_uop_pc_lob, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_taken, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_imm_rename, // @[issue-slot.scala:52:14]
input [2:0] io_brupdate_b2_uop_imm_sel, // @[issue-slot.scala:52:14]
input [4:0] io_brupdate_b2_uop_pimm, // @[issue-slot.scala:52:14]
input [19:0] io_brupdate_b2_uop_imm_packed, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_uop_op1_sel, // @[issue-slot.scala:52:14]
input [2:0] io_brupdate_b2_uop_op2_sel, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_div, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14]
input [5:0] io_brupdate_b2_uop_rob_idx, // @[issue-slot.scala:52:14]
input [3:0] io_brupdate_b2_uop_ldq_idx, // @[issue-slot.scala:52:14]
input [3:0] io_brupdate_b2_uop_stq_idx, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_uop_rxq_idx, // @[issue-slot.scala:52:14]
input [6:0] io_brupdate_b2_uop_pdst, // @[issue-slot.scala:52:14]
input [6:0] io_brupdate_b2_uop_prs1, // @[issue-slot.scala:52:14]
input [6:0] io_brupdate_b2_uop_prs2, // @[issue-slot.scala:52:14]
input [6:0] io_brupdate_b2_uop_prs3, // @[issue-slot.scala:52:14]
input [4:0] io_brupdate_b2_uop_ppred, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_prs1_busy, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_prs2_busy, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_prs3_busy, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_ppred_busy, // @[issue-slot.scala:52:14]
input [6:0] io_brupdate_b2_uop_stale_pdst, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_exception, // @[issue-slot.scala:52:14]
input [63:0] io_brupdate_b2_uop_exc_cause, // @[issue-slot.scala:52:14]
input [4:0] io_brupdate_b2_uop_mem_cmd, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_uop_mem_size, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_mem_signed, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_uses_ldq, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_uses_stq, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_is_unique, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_flush_on_commit, // @[issue-slot.scala:52:14]
input [2:0] io_brupdate_b2_uop_csr_cmd, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_ldst_is_rs1, // @[issue-slot.scala:52:14]
input [5:0] io_brupdate_b2_uop_ldst, // @[issue-slot.scala:52:14]
input [5:0] io_brupdate_b2_uop_lrs1, // @[issue-slot.scala:52:14]
input [5:0] io_brupdate_b2_uop_lrs2, // @[issue-slot.scala:52:14]
input [5:0] io_brupdate_b2_uop_lrs3, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_uop_dst_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_uop_lrs1_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_uop_lrs2_rtype, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_frs3_en, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fcn_dw, // @[issue-slot.scala:52:14]
input [4:0] io_brupdate_b2_uop_fcn_op, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_val, // @[issue-slot.scala:52:14]
input [2:0] io_brupdate_b2_uop_fp_rm, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_uop_fp_typ, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_xcpt_pf_if, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_xcpt_ae_if, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_xcpt_ma_if, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_bp_debug_if, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_bp_xcpt_if, // @[issue-slot.scala:52:14]
input [2:0] io_brupdate_b2_uop_debug_fsrc, // @[issue-slot.scala:52:14]
input [2:0] io_brupdate_b2_uop_debug_tsrc, // @[issue-slot.scala:52:14]
input io_brupdate_b2_mispredict, // @[issue-slot.scala:52:14]
input io_brupdate_b2_taken, // @[issue-slot.scala:52:14]
input [2:0] io_brupdate_b2_cfi_type, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_pc_sel, // @[issue-slot.scala:52:14]
input [39:0] io_brupdate_b2_jalr_target, // @[issue-slot.scala:52:14]
input [20:0] io_brupdate_b2_target_offset, // @[issue-slot.scala:52:14]
input io_kill, // @[issue-slot.scala:52:14]
input io_clear, // @[issue-slot.scala:52:14]
input io_squash_grant, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_valid, // @[issue-slot.scala:52:14]
input [31:0] io_wakeup_ports_0_bits_uop_inst, // @[issue-slot.scala:52:14]
input [31:0] io_wakeup_ports_0_bits_uop_debug_inst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_is_rvc, // @[issue-slot.scala:52:14]
input [39:0] io_wakeup_ports_0_bits_uop_debug_pc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_iq_type_0, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_iq_type_1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_iq_type_2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_iq_type_3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fu_code_0, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fu_code_1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fu_code_2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fu_code_3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fu_code_4, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fu_code_5, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fu_code_6, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fu_code_7, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fu_code_8, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fu_code_9, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_iw_issued, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_iw_issued_partial_agen, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_0_bits_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_0_bits_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_0_bits_uop_dis_col_sel, // @[issue-slot.scala:52:14]
input [11:0] io_wakeup_ports_0_bits_uop_br_mask, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_0_bits_uop_br_tag, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_0_bits_uop_br_type, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_is_sfb, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_is_fence, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_is_fencei, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_is_sfence, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_is_amo, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_is_eret, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_is_rocc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_is_mov, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_0_bits_uop_ftq_idx, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_edge_inst, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_0_bits_uop_pc_lob, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_taken, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_imm_rename, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_0_bits_uop_imm_sel, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_0_bits_uop_pimm, // @[issue-slot.scala:52:14]
input [19:0] io_wakeup_ports_0_bits_uop_imm_packed, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_0_bits_uop_op1_sel, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_0_bits_uop_op2_sel, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_div, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_0_bits_uop_rob_idx, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_0_bits_uop_ldq_idx, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_0_bits_uop_stq_idx, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_0_bits_uop_rxq_idx, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_0_bits_uop_pdst, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_0_bits_uop_prs1, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_0_bits_uop_prs2, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_0_bits_uop_prs3, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_0_bits_uop_ppred, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_prs1_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_prs2_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_prs3_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_ppred_busy, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_0_bits_uop_stale_pdst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_exception, // @[issue-slot.scala:52:14]
input [63:0] io_wakeup_ports_0_bits_uop_exc_cause, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_0_bits_uop_mem_cmd, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_0_bits_uop_mem_size, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_mem_signed, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_uses_ldq, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_uses_stq, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_is_unique, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_flush_on_commit, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_0_bits_uop_csr_cmd, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_ldst_is_rs1, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_0_bits_uop_ldst, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_0_bits_uop_lrs1, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_0_bits_uop_lrs2, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_0_bits_uop_lrs3, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_0_bits_uop_dst_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_0_bits_uop_lrs1_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_0_bits_uop_lrs2_rtype, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_frs3_en, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fcn_dw, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_0_bits_uop_fcn_op, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_val, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_0_bits_uop_fp_rm, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_0_bits_uop_fp_typ, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_xcpt_pf_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_xcpt_ae_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_xcpt_ma_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_bp_debug_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_bp_xcpt_if, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_0_bits_uop_debug_fsrc, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_0_bits_uop_debug_tsrc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_bypassable, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_0_bits_speculative_mask, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_rebusy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_valid, // @[issue-slot.scala:52:14]
input [31:0] io_wakeup_ports_1_bits_uop_inst, // @[issue-slot.scala:52:14]
input [31:0] io_wakeup_ports_1_bits_uop_debug_inst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_is_rvc, // @[issue-slot.scala:52:14]
input [39:0] io_wakeup_ports_1_bits_uop_debug_pc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_iq_type_0, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_iq_type_1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_iq_type_2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_iq_type_3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fu_code_0, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fu_code_1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fu_code_2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fu_code_3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fu_code_4, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fu_code_5, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fu_code_6, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fu_code_7, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fu_code_8, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fu_code_9, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_iw_issued, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_iw_issued_partial_agen, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_1_bits_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_1_bits_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_1_bits_uop_dis_col_sel, // @[issue-slot.scala:52:14]
input [11:0] io_wakeup_ports_1_bits_uop_br_mask, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_1_bits_uop_br_tag, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_1_bits_uop_br_type, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_is_sfb, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_is_fence, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_is_fencei, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_is_sfence, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_is_amo, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_is_eret, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_is_rocc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_is_mov, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_1_bits_uop_ftq_idx, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_edge_inst, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_1_bits_uop_pc_lob, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_taken, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_imm_rename, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_1_bits_uop_imm_sel, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_1_bits_uop_pimm, // @[issue-slot.scala:52:14]
input [19:0] io_wakeup_ports_1_bits_uop_imm_packed, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_1_bits_uop_op1_sel, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_1_bits_uop_op2_sel, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_div, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_1_bits_uop_rob_idx, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_1_bits_uop_ldq_idx, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_1_bits_uop_stq_idx, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_1_bits_uop_rxq_idx, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_1_bits_uop_pdst, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_1_bits_uop_prs1, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_1_bits_uop_prs2, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_1_bits_uop_prs3, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_1_bits_uop_ppred, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_prs1_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_prs2_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_prs3_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_ppred_busy, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_1_bits_uop_stale_pdst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_exception, // @[issue-slot.scala:52:14]
input [63:0] io_wakeup_ports_1_bits_uop_exc_cause, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_1_bits_uop_mem_cmd, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_1_bits_uop_mem_size, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_mem_signed, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_uses_ldq, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_uses_stq, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_is_unique, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_flush_on_commit, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_1_bits_uop_csr_cmd, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_ldst_is_rs1, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_1_bits_uop_ldst, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_1_bits_uop_lrs1, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_1_bits_uop_lrs2, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_1_bits_uop_lrs3, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_1_bits_uop_dst_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_1_bits_uop_lrs1_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_1_bits_uop_lrs2_rtype, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_frs3_en, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fcn_dw, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_1_bits_uop_fcn_op, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_val, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_1_bits_uop_fp_rm, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_1_bits_uop_fp_typ, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_xcpt_pf_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_xcpt_ae_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_xcpt_ma_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_bp_debug_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_bp_xcpt_if, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_1_bits_uop_debug_fsrc, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_1_bits_uop_debug_tsrc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_valid, // @[issue-slot.scala:52:14]
input [31:0] io_wakeup_ports_2_bits_uop_inst, // @[issue-slot.scala:52:14]
input [31:0] io_wakeup_ports_2_bits_uop_debug_inst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_is_rvc, // @[issue-slot.scala:52:14]
input [39:0] io_wakeup_ports_2_bits_uop_debug_pc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_iq_type_0, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_iq_type_1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_iq_type_2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_iq_type_3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fu_code_0, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fu_code_1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fu_code_2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fu_code_3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fu_code_4, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fu_code_5, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fu_code_6, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fu_code_7, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fu_code_8, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fu_code_9, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_iw_issued, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_2_bits_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_2_bits_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_2_bits_uop_dis_col_sel, // @[issue-slot.scala:52:14]
input [11:0] io_wakeup_ports_2_bits_uop_br_mask, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_2_bits_uop_br_tag, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_2_bits_uop_br_type, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_is_sfb, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_is_fence, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_is_fencei, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_is_sfence, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_is_amo, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_is_eret, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_is_rocc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_is_mov, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_2_bits_uop_ftq_idx, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_edge_inst, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_2_bits_uop_pc_lob, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_taken, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_imm_rename, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_2_bits_uop_imm_sel, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_2_bits_uop_pimm, // @[issue-slot.scala:52:14]
input [19:0] io_wakeup_ports_2_bits_uop_imm_packed, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_2_bits_uop_op1_sel, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_2_bits_uop_op2_sel, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_div, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_2_bits_uop_rob_idx, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_2_bits_uop_ldq_idx, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_2_bits_uop_stq_idx, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_2_bits_uop_rxq_idx, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_2_bits_uop_pdst, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_2_bits_uop_prs1, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_2_bits_uop_prs2, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_2_bits_uop_prs3, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_2_bits_uop_ppred, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_prs1_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_prs2_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_prs3_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_ppred_busy, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_2_bits_uop_stale_pdst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_exception, // @[issue-slot.scala:52:14]
input [63:0] io_wakeup_ports_2_bits_uop_exc_cause, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_2_bits_uop_mem_cmd, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_2_bits_uop_mem_size, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_mem_signed, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_uses_ldq, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_uses_stq, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_is_unique, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_flush_on_commit, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_2_bits_uop_csr_cmd, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_ldst_is_rs1, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_2_bits_uop_ldst, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_2_bits_uop_lrs1, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_2_bits_uop_lrs2, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_2_bits_uop_lrs3, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_2_bits_uop_dst_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_2_bits_uop_lrs1_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_2_bits_uop_lrs2_rtype, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_frs3_en, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fcn_dw, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_2_bits_uop_fcn_op, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_val, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_2_bits_uop_fp_rm, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_2_bits_uop_fp_typ, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_xcpt_pf_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_xcpt_ae_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_xcpt_ma_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_bp_debug_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_bp_xcpt_if, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_2_bits_uop_debug_fsrc, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_2_bits_uop_debug_tsrc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_valid, // @[issue-slot.scala:52:14]
input [31:0] io_wakeup_ports_3_bits_uop_inst, // @[issue-slot.scala:52:14]
input [31:0] io_wakeup_ports_3_bits_uop_debug_inst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_is_rvc, // @[issue-slot.scala:52:14]
input [39:0] io_wakeup_ports_3_bits_uop_debug_pc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_iq_type_0, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_iq_type_1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_iq_type_2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_iq_type_3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fu_code_0, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fu_code_1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fu_code_2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fu_code_3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fu_code_4, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fu_code_5, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fu_code_6, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fu_code_7, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fu_code_8, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fu_code_9, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_iw_issued, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_3_bits_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_3_bits_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_3_bits_uop_dis_col_sel, // @[issue-slot.scala:52:14]
input [11:0] io_wakeup_ports_3_bits_uop_br_mask, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_3_bits_uop_br_tag, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_3_bits_uop_br_type, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_is_sfb, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_is_fence, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_is_fencei, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_is_sfence, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_is_amo, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_is_eret, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_is_rocc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_is_mov, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_3_bits_uop_ftq_idx, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_edge_inst, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_3_bits_uop_pc_lob, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_taken, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_imm_rename, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_3_bits_uop_imm_sel, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_3_bits_uop_pimm, // @[issue-slot.scala:52:14]
input [19:0] io_wakeup_ports_3_bits_uop_imm_packed, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_3_bits_uop_op1_sel, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_3_bits_uop_op2_sel, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_div, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_3_bits_uop_rob_idx, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_3_bits_uop_ldq_idx, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_3_bits_uop_stq_idx, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_3_bits_uop_rxq_idx, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_3_bits_uop_pdst, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_3_bits_uop_prs1, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_3_bits_uop_prs2, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_3_bits_uop_prs3, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_3_bits_uop_ppred, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_prs1_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_prs2_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_prs3_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_ppred_busy, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_3_bits_uop_stale_pdst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_exception, // @[issue-slot.scala:52:14]
input [63:0] io_wakeup_ports_3_bits_uop_exc_cause, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_3_bits_uop_mem_cmd, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_3_bits_uop_mem_size, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_mem_signed, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_uses_ldq, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_uses_stq, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_is_unique, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_flush_on_commit, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_3_bits_uop_csr_cmd, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_ldst_is_rs1, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_3_bits_uop_ldst, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_3_bits_uop_lrs1, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_3_bits_uop_lrs2, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_3_bits_uop_lrs3, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_3_bits_uop_dst_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_3_bits_uop_lrs1_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_3_bits_uop_lrs2_rtype, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_frs3_en, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fcn_dw, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_3_bits_uop_fcn_op, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_val, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_3_bits_uop_fp_rm, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_3_bits_uop_fp_typ, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_xcpt_pf_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_xcpt_ae_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_xcpt_ma_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_bp_debug_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_bp_xcpt_if, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_3_bits_uop_debug_fsrc, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_3_bits_uop_debug_tsrc, // @[issue-slot.scala:52:14]
input [1:0] io_child_rebusys // @[issue-slot.scala:52:14]
);
wire [11:0] next_uop_out_br_mask; // @[util.scala:104:23]
wire io_grant_0 = io_grant; // @[issue-slot.scala:49:7]
wire io_in_uop_valid_0 = io_in_uop_valid; // @[issue-slot.scala:49:7]
wire [31:0] io_in_uop_bits_inst_0 = io_in_uop_bits_inst; // @[issue-slot.scala:49:7]
wire [31:0] io_in_uop_bits_debug_inst_0 = io_in_uop_bits_debug_inst; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_is_rvc_0 = io_in_uop_bits_is_rvc; // @[issue-slot.scala:49:7]
wire [39:0] io_in_uop_bits_debug_pc_0 = io_in_uop_bits_debug_pc; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_iq_type_0_0 = io_in_uop_bits_iq_type_0; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_iq_type_1_0 = io_in_uop_bits_iq_type_1; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_iq_type_2_0 = io_in_uop_bits_iq_type_2; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_iq_type_3_0 = io_in_uop_bits_iq_type_3; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fu_code_0_0 = io_in_uop_bits_fu_code_0; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fu_code_1_0 = io_in_uop_bits_fu_code_1; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fu_code_2_0 = io_in_uop_bits_fu_code_2; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fu_code_3_0 = io_in_uop_bits_fu_code_3; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fu_code_4_0 = io_in_uop_bits_fu_code_4; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fu_code_5_0 = io_in_uop_bits_fu_code_5; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fu_code_6_0 = io_in_uop_bits_fu_code_6; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fu_code_7_0 = io_in_uop_bits_fu_code_7; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fu_code_8_0 = io_in_uop_bits_fu_code_8; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fu_code_9_0 = io_in_uop_bits_fu_code_9; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_iw_issued_0 = io_in_uop_bits_iw_issued; // @[issue-slot.scala:49:7]
wire [1:0] io_in_uop_bits_iw_p1_speculative_child_0 = io_in_uop_bits_iw_p1_speculative_child; // @[issue-slot.scala:49:7]
wire [1:0] io_in_uop_bits_iw_p2_speculative_child_0 = io_in_uop_bits_iw_p2_speculative_child; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_iw_p1_bypass_hint_0 = io_in_uop_bits_iw_p1_bypass_hint; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_iw_p2_bypass_hint_0 = io_in_uop_bits_iw_p2_bypass_hint; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_iw_p3_bypass_hint_0 = io_in_uop_bits_iw_p3_bypass_hint; // @[issue-slot.scala:49:7]
wire [1:0] io_in_uop_bits_dis_col_sel_0 = io_in_uop_bits_dis_col_sel; // @[issue-slot.scala:49:7]
wire [11:0] io_in_uop_bits_br_mask_0 = io_in_uop_bits_br_mask; // @[issue-slot.scala:49:7]
wire [3:0] io_in_uop_bits_br_tag_0 = io_in_uop_bits_br_tag; // @[issue-slot.scala:49:7]
wire [3:0] io_in_uop_bits_br_type_0 = io_in_uop_bits_br_type; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_is_sfb_0 = io_in_uop_bits_is_sfb; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_is_fence_0 = io_in_uop_bits_is_fence; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_is_fencei_0 = io_in_uop_bits_is_fencei; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_is_sfence_0 = io_in_uop_bits_is_sfence; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_is_amo_0 = io_in_uop_bits_is_amo; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_is_eret_0 = io_in_uop_bits_is_eret; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_is_sys_pc2epc_0 = io_in_uop_bits_is_sys_pc2epc; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_is_rocc_0 = io_in_uop_bits_is_rocc; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_is_mov_0 = io_in_uop_bits_is_mov; // @[issue-slot.scala:49:7]
wire [4:0] io_in_uop_bits_ftq_idx_0 = io_in_uop_bits_ftq_idx; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_edge_inst_0 = io_in_uop_bits_edge_inst; // @[issue-slot.scala:49:7]
wire [5:0] io_in_uop_bits_pc_lob_0 = io_in_uop_bits_pc_lob; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_taken_0 = io_in_uop_bits_taken; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_imm_rename_0 = io_in_uop_bits_imm_rename; // @[issue-slot.scala:49:7]
wire [2:0] io_in_uop_bits_imm_sel_0 = io_in_uop_bits_imm_sel; // @[issue-slot.scala:49:7]
wire [4:0] io_in_uop_bits_pimm_0 = io_in_uop_bits_pimm; // @[issue-slot.scala:49:7]
wire [19:0] io_in_uop_bits_imm_packed_0 = io_in_uop_bits_imm_packed; // @[issue-slot.scala:49:7]
wire [1:0] io_in_uop_bits_op1_sel_0 = io_in_uop_bits_op1_sel; // @[issue-slot.scala:49:7]
wire [2:0] io_in_uop_bits_op2_sel_0 = io_in_uop_bits_op2_sel; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_ldst_0 = io_in_uop_bits_fp_ctrl_ldst; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_wen_0 = io_in_uop_bits_fp_ctrl_wen; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_ren1_0 = io_in_uop_bits_fp_ctrl_ren1; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_ren2_0 = io_in_uop_bits_fp_ctrl_ren2; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_ren3_0 = io_in_uop_bits_fp_ctrl_ren3; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_swap12_0 = io_in_uop_bits_fp_ctrl_swap12; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_swap23_0 = io_in_uop_bits_fp_ctrl_swap23; // @[issue-slot.scala:49:7]
wire [1:0] io_in_uop_bits_fp_ctrl_typeTagIn_0 = io_in_uop_bits_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7]
wire [1:0] io_in_uop_bits_fp_ctrl_typeTagOut_0 = io_in_uop_bits_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_fromint_0 = io_in_uop_bits_fp_ctrl_fromint; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_toint_0 = io_in_uop_bits_fp_ctrl_toint; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_fastpipe_0 = io_in_uop_bits_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_fma_0 = io_in_uop_bits_fp_ctrl_fma; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_div_0 = io_in_uop_bits_fp_ctrl_div; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_sqrt_0 = io_in_uop_bits_fp_ctrl_sqrt; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_wflags_0 = io_in_uop_bits_fp_ctrl_wflags; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_vec_0 = io_in_uop_bits_fp_ctrl_vec; // @[issue-slot.scala:49:7]
wire [5:0] io_in_uop_bits_rob_idx_0 = io_in_uop_bits_rob_idx; // @[issue-slot.scala:49:7]
wire [3:0] io_in_uop_bits_ldq_idx_0 = io_in_uop_bits_ldq_idx; // @[issue-slot.scala:49:7]
wire [3:0] io_in_uop_bits_stq_idx_0 = io_in_uop_bits_stq_idx; // @[issue-slot.scala:49:7]
wire [1:0] io_in_uop_bits_rxq_idx_0 = io_in_uop_bits_rxq_idx; // @[issue-slot.scala:49:7]
wire [6:0] io_in_uop_bits_pdst_0 = io_in_uop_bits_pdst; // @[issue-slot.scala:49:7]
wire [6:0] io_in_uop_bits_prs1_0 = io_in_uop_bits_prs1; // @[issue-slot.scala:49:7]
wire [6:0] io_in_uop_bits_prs2_0 = io_in_uop_bits_prs2; // @[issue-slot.scala:49:7]
wire [6:0] io_in_uop_bits_prs3_0 = io_in_uop_bits_prs3; // @[issue-slot.scala:49:7]
wire [4:0] io_in_uop_bits_ppred_0 = io_in_uop_bits_ppred; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_prs1_busy_0 = io_in_uop_bits_prs1_busy; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_prs2_busy_0 = io_in_uop_bits_prs2_busy; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_prs3_busy_0 = io_in_uop_bits_prs3_busy; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_ppred_busy_0 = io_in_uop_bits_ppred_busy; // @[issue-slot.scala:49:7]
wire [6:0] io_in_uop_bits_stale_pdst_0 = io_in_uop_bits_stale_pdst; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_exception_0 = io_in_uop_bits_exception; // @[issue-slot.scala:49:7]
wire [63:0] io_in_uop_bits_exc_cause_0 = io_in_uop_bits_exc_cause; // @[issue-slot.scala:49:7]
wire [4:0] io_in_uop_bits_mem_cmd_0 = io_in_uop_bits_mem_cmd; // @[issue-slot.scala:49:7]
wire [1:0] io_in_uop_bits_mem_size_0 = io_in_uop_bits_mem_size; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_mem_signed_0 = io_in_uop_bits_mem_signed; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_uses_ldq_0 = io_in_uop_bits_uses_ldq; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_uses_stq_0 = io_in_uop_bits_uses_stq; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_is_unique_0 = io_in_uop_bits_is_unique; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_flush_on_commit_0 = io_in_uop_bits_flush_on_commit; // @[issue-slot.scala:49:7]
wire [2:0] io_in_uop_bits_csr_cmd_0 = io_in_uop_bits_csr_cmd; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_ldst_is_rs1_0 = io_in_uop_bits_ldst_is_rs1; // @[issue-slot.scala:49:7]
wire [5:0] io_in_uop_bits_ldst_0 = io_in_uop_bits_ldst; // @[issue-slot.scala:49:7]
wire [5:0] io_in_uop_bits_lrs1_0 = io_in_uop_bits_lrs1; // @[issue-slot.scala:49:7]
wire [5:0] io_in_uop_bits_lrs2_0 = io_in_uop_bits_lrs2; // @[issue-slot.scala:49:7]
wire [5:0] io_in_uop_bits_lrs3_0 = io_in_uop_bits_lrs3; // @[issue-slot.scala:49:7]
wire [1:0] io_in_uop_bits_dst_rtype_0 = io_in_uop_bits_dst_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_in_uop_bits_lrs1_rtype_0 = io_in_uop_bits_lrs1_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_in_uop_bits_lrs2_rtype_0 = io_in_uop_bits_lrs2_rtype; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_frs3_en_0 = io_in_uop_bits_frs3_en; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fcn_dw_0 = io_in_uop_bits_fcn_dw; // @[issue-slot.scala:49:7]
wire [4:0] io_in_uop_bits_fcn_op_0 = io_in_uop_bits_fcn_op; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_val_0 = io_in_uop_bits_fp_val; // @[issue-slot.scala:49:7]
wire [2:0] io_in_uop_bits_fp_rm_0 = io_in_uop_bits_fp_rm; // @[issue-slot.scala:49:7]
wire [1:0] io_in_uop_bits_fp_typ_0 = io_in_uop_bits_fp_typ; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_xcpt_pf_if_0 = io_in_uop_bits_xcpt_pf_if; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_xcpt_ae_if_0 = io_in_uop_bits_xcpt_ae_if; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_xcpt_ma_if_0 = io_in_uop_bits_xcpt_ma_if; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_bp_debug_if_0 = io_in_uop_bits_bp_debug_if; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_bp_xcpt_if_0 = io_in_uop_bits_bp_xcpt_if; // @[issue-slot.scala:49:7]
wire [2:0] io_in_uop_bits_debug_fsrc_0 = io_in_uop_bits_debug_fsrc; // @[issue-slot.scala:49:7]
wire [2:0] io_in_uop_bits_debug_tsrc_0 = io_in_uop_bits_debug_tsrc; // @[issue-slot.scala:49:7]
wire [11:0] io_brupdate_b1_resolve_mask_0 = io_brupdate_b1_resolve_mask; // @[issue-slot.scala:49:7]
wire [11:0] io_brupdate_b1_mispredict_mask_0 = io_brupdate_b1_mispredict_mask; // @[issue-slot.scala:49:7]
wire [31:0] io_brupdate_b2_uop_inst_0 = io_brupdate_b2_uop_inst; // @[issue-slot.scala:49:7]
wire [31:0] io_brupdate_b2_uop_debug_inst_0 = io_brupdate_b2_uop_debug_inst; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_is_rvc_0 = io_brupdate_b2_uop_is_rvc; // @[issue-slot.scala:49:7]
wire [39:0] io_brupdate_b2_uop_debug_pc_0 = io_brupdate_b2_uop_debug_pc; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_iq_type_0_0 = io_brupdate_b2_uop_iq_type_0; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_iq_type_1_0 = io_brupdate_b2_uop_iq_type_1; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_iq_type_2_0 = io_brupdate_b2_uop_iq_type_2; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_iq_type_3_0 = io_brupdate_b2_uop_iq_type_3; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fu_code_0_0 = io_brupdate_b2_uop_fu_code_0; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fu_code_1_0 = io_brupdate_b2_uop_fu_code_1; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fu_code_2_0 = io_brupdate_b2_uop_fu_code_2; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fu_code_3_0 = io_brupdate_b2_uop_fu_code_3; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fu_code_4_0 = io_brupdate_b2_uop_fu_code_4; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fu_code_5_0 = io_brupdate_b2_uop_fu_code_5; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fu_code_6_0 = io_brupdate_b2_uop_fu_code_6; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fu_code_7_0 = io_brupdate_b2_uop_fu_code_7; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fu_code_8_0 = io_brupdate_b2_uop_fu_code_8; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fu_code_9_0 = io_brupdate_b2_uop_fu_code_9; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_iw_issued_0 = io_brupdate_b2_uop_iw_issued; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_iw_issued_partial_agen_0 = io_brupdate_b2_uop_iw_issued_partial_agen; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_iw_issued_partial_dgen_0 = io_brupdate_b2_uop_iw_issued_partial_dgen; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_uop_iw_p1_speculative_child_0 = io_brupdate_b2_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_uop_iw_p2_speculative_child_0 = io_brupdate_b2_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_iw_p1_bypass_hint_0 = io_brupdate_b2_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_iw_p2_bypass_hint_0 = io_brupdate_b2_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_iw_p3_bypass_hint_0 = io_brupdate_b2_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_uop_dis_col_sel_0 = io_brupdate_b2_uop_dis_col_sel; // @[issue-slot.scala:49:7]
wire [11:0] io_brupdate_b2_uop_br_mask_0 = io_brupdate_b2_uop_br_mask; // @[issue-slot.scala:49:7]
wire [3:0] io_brupdate_b2_uop_br_tag_0 = io_brupdate_b2_uop_br_tag; // @[issue-slot.scala:49:7]
wire [3:0] io_brupdate_b2_uop_br_type_0 = io_brupdate_b2_uop_br_type; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_is_sfb_0 = io_brupdate_b2_uop_is_sfb; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_is_fence_0 = io_brupdate_b2_uop_is_fence; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_is_fencei_0 = io_brupdate_b2_uop_is_fencei; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_is_sfence_0 = io_brupdate_b2_uop_is_sfence; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_is_amo_0 = io_brupdate_b2_uop_is_amo; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_is_eret_0 = io_brupdate_b2_uop_is_eret; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_is_sys_pc2epc_0 = io_brupdate_b2_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_is_rocc_0 = io_brupdate_b2_uop_is_rocc; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_is_mov_0 = io_brupdate_b2_uop_is_mov; // @[issue-slot.scala:49:7]
wire [4:0] io_brupdate_b2_uop_ftq_idx_0 = io_brupdate_b2_uop_ftq_idx; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_edge_inst_0 = io_brupdate_b2_uop_edge_inst; // @[issue-slot.scala:49:7]
wire [5:0] io_brupdate_b2_uop_pc_lob_0 = io_brupdate_b2_uop_pc_lob; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_taken_0 = io_brupdate_b2_uop_taken; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_imm_rename_0 = io_brupdate_b2_uop_imm_rename; // @[issue-slot.scala:49:7]
wire [2:0] io_brupdate_b2_uop_imm_sel_0 = io_brupdate_b2_uop_imm_sel; // @[issue-slot.scala:49:7]
wire [4:0] io_brupdate_b2_uop_pimm_0 = io_brupdate_b2_uop_pimm; // @[issue-slot.scala:49:7]
wire [19:0] io_brupdate_b2_uop_imm_packed_0 = io_brupdate_b2_uop_imm_packed; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_uop_op1_sel_0 = io_brupdate_b2_uop_op1_sel; // @[issue-slot.scala:49:7]
wire [2:0] io_brupdate_b2_uop_op2_sel_0 = io_brupdate_b2_uop_op2_sel; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_ldst_0 = io_brupdate_b2_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_wen_0 = io_brupdate_b2_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_ren1_0 = io_brupdate_b2_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_ren2_0 = io_brupdate_b2_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_ren3_0 = io_brupdate_b2_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_swap12_0 = io_brupdate_b2_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_swap23_0 = io_brupdate_b2_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagIn_0 = io_brupdate_b2_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagOut_0 = io_brupdate_b2_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_fromint_0 = io_brupdate_b2_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_toint_0 = io_brupdate_b2_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_fastpipe_0 = io_brupdate_b2_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_fma_0 = io_brupdate_b2_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_div_0 = io_brupdate_b2_uop_fp_ctrl_div; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_sqrt_0 = io_brupdate_b2_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_wflags_0 = io_brupdate_b2_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_vec_0 = io_brupdate_b2_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7]
wire [5:0] io_brupdate_b2_uop_rob_idx_0 = io_brupdate_b2_uop_rob_idx; // @[issue-slot.scala:49:7]
wire [3:0] io_brupdate_b2_uop_ldq_idx_0 = io_brupdate_b2_uop_ldq_idx; // @[issue-slot.scala:49:7]
wire [3:0] io_brupdate_b2_uop_stq_idx_0 = io_brupdate_b2_uop_stq_idx; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_uop_rxq_idx_0 = io_brupdate_b2_uop_rxq_idx; // @[issue-slot.scala:49:7]
wire [6:0] io_brupdate_b2_uop_pdst_0 = io_brupdate_b2_uop_pdst; // @[issue-slot.scala:49:7]
wire [6:0] io_brupdate_b2_uop_prs1_0 = io_brupdate_b2_uop_prs1; // @[issue-slot.scala:49:7]
wire [6:0] io_brupdate_b2_uop_prs2_0 = io_brupdate_b2_uop_prs2; // @[issue-slot.scala:49:7]
wire [6:0] io_brupdate_b2_uop_prs3_0 = io_brupdate_b2_uop_prs3; // @[issue-slot.scala:49:7]
wire [4:0] io_brupdate_b2_uop_ppred_0 = io_brupdate_b2_uop_ppred; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_prs1_busy_0 = io_brupdate_b2_uop_prs1_busy; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_prs2_busy_0 = io_brupdate_b2_uop_prs2_busy; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_prs3_busy_0 = io_brupdate_b2_uop_prs3_busy; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_ppred_busy_0 = io_brupdate_b2_uop_ppred_busy; // @[issue-slot.scala:49:7]
wire [6:0] io_brupdate_b2_uop_stale_pdst_0 = io_brupdate_b2_uop_stale_pdst; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_exception_0 = io_brupdate_b2_uop_exception; // @[issue-slot.scala:49:7]
wire [63:0] io_brupdate_b2_uop_exc_cause_0 = io_brupdate_b2_uop_exc_cause; // @[issue-slot.scala:49:7]
wire [4:0] io_brupdate_b2_uop_mem_cmd_0 = io_brupdate_b2_uop_mem_cmd; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_uop_mem_size_0 = io_brupdate_b2_uop_mem_size; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_mem_signed_0 = io_brupdate_b2_uop_mem_signed; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_uses_ldq_0 = io_brupdate_b2_uop_uses_ldq; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_uses_stq_0 = io_brupdate_b2_uop_uses_stq; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_is_unique_0 = io_brupdate_b2_uop_is_unique; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_flush_on_commit_0 = io_brupdate_b2_uop_flush_on_commit; // @[issue-slot.scala:49:7]
wire [2:0] io_brupdate_b2_uop_csr_cmd_0 = io_brupdate_b2_uop_csr_cmd; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_ldst_is_rs1_0 = io_brupdate_b2_uop_ldst_is_rs1; // @[issue-slot.scala:49:7]
wire [5:0] io_brupdate_b2_uop_ldst_0 = io_brupdate_b2_uop_ldst; // @[issue-slot.scala:49:7]
wire [5:0] io_brupdate_b2_uop_lrs1_0 = io_brupdate_b2_uop_lrs1; // @[issue-slot.scala:49:7]
wire [5:0] io_brupdate_b2_uop_lrs2_0 = io_brupdate_b2_uop_lrs2; // @[issue-slot.scala:49:7]
wire [5:0] io_brupdate_b2_uop_lrs3_0 = io_brupdate_b2_uop_lrs3; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_uop_dst_rtype_0 = io_brupdate_b2_uop_dst_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_uop_lrs1_rtype_0 = io_brupdate_b2_uop_lrs1_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_uop_lrs2_rtype_0 = io_brupdate_b2_uop_lrs2_rtype; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_frs3_en_0 = io_brupdate_b2_uop_frs3_en; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fcn_dw_0 = io_brupdate_b2_uop_fcn_dw; // @[issue-slot.scala:49:7]
wire [4:0] io_brupdate_b2_uop_fcn_op_0 = io_brupdate_b2_uop_fcn_op; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_val_0 = io_brupdate_b2_uop_fp_val; // @[issue-slot.scala:49:7]
wire [2:0] io_brupdate_b2_uop_fp_rm_0 = io_brupdate_b2_uop_fp_rm; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_uop_fp_typ_0 = io_brupdate_b2_uop_fp_typ; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_xcpt_pf_if_0 = io_brupdate_b2_uop_xcpt_pf_if; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_xcpt_ae_if_0 = io_brupdate_b2_uop_xcpt_ae_if; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_xcpt_ma_if_0 = io_brupdate_b2_uop_xcpt_ma_if; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_bp_debug_if_0 = io_brupdate_b2_uop_bp_debug_if; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_bp_xcpt_if_0 = io_brupdate_b2_uop_bp_xcpt_if; // @[issue-slot.scala:49:7]
wire [2:0] io_brupdate_b2_uop_debug_fsrc_0 = io_brupdate_b2_uop_debug_fsrc; // @[issue-slot.scala:49:7]
wire [2:0] io_brupdate_b2_uop_debug_tsrc_0 = io_brupdate_b2_uop_debug_tsrc; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_mispredict_0 = io_brupdate_b2_mispredict; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_taken_0 = io_brupdate_b2_taken; // @[issue-slot.scala:49:7]
wire [2:0] io_brupdate_b2_cfi_type_0 = io_brupdate_b2_cfi_type; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_pc_sel_0 = io_brupdate_b2_pc_sel; // @[issue-slot.scala:49:7]
wire [39:0] io_brupdate_b2_jalr_target_0 = io_brupdate_b2_jalr_target; // @[issue-slot.scala:49:7]
wire [20:0] io_brupdate_b2_target_offset_0 = io_brupdate_b2_target_offset; // @[issue-slot.scala:49:7]
wire io_kill_0 = io_kill; // @[issue-slot.scala:49:7]
wire io_clear_0 = io_clear; // @[issue-slot.scala:49:7]
wire io_squash_grant_0 = io_squash_grant; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_valid_0 = io_wakeup_ports_0_valid; // @[issue-slot.scala:49:7]
wire [31:0] io_wakeup_ports_0_bits_uop_inst_0 = io_wakeup_ports_0_bits_uop_inst; // @[issue-slot.scala:49:7]
wire [31:0] io_wakeup_ports_0_bits_uop_debug_inst_0 = io_wakeup_ports_0_bits_uop_debug_inst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_is_rvc_0 = io_wakeup_ports_0_bits_uop_is_rvc; // @[issue-slot.scala:49:7]
wire [39:0] io_wakeup_ports_0_bits_uop_debug_pc_0 = io_wakeup_ports_0_bits_uop_debug_pc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_iq_type_0_0 = io_wakeup_ports_0_bits_uop_iq_type_0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_iq_type_1_0 = io_wakeup_ports_0_bits_uop_iq_type_1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_iq_type_2_0 = io_wakeup_ports_0_bits_uop_iq_type_2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_iq_type_3_0 = io_wakeup_ports_0_bits_uop_iq_type_3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fu_code_0_0 = io_wakeup_ports_0_bits_uop_fu_code_0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fu_code_1_0 = io_wakeup_ports_0_bits_uop_fu_code_1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fu_code_2_0 = io_wakeup_ports_0_bits_uop_fu_code_2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fu_code_3_0 = io_wakeup_ports_0_bits_uop_fu_code_3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fu_code_4_0 = io_wakeup_ports_0_bits_uop_fu_code_4; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fu_code_5_0 = io_wakeup_ports_0_bits_uop_fu_code_5; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fu_code_6_0 = io_wakeup_ports_0_bits_uop_fu_code_6; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fu_code_7_0 = io_wakeup_ports_0_bits_uop_fu_code_7; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fu_code_8_0 = io_wakeup_ports_0_bits_uop_fu_code_8; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fu_code_9_0 = io_wakeup_ports_0_bits_uop_fu_code_9; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_iw_issued_0 = io_wakeup_ports_0_bits_uop_iw_issued; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_iw_issued_partial_agen_0 = io_wakeup_ports_0_bits_uop_iw_issued_partial_agen; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen_0 = io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_0_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_0_bits_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_0_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_0_bits_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_0_bits_uop_dis_col_sel_0 = io_wakeup_ports_0_bits_uop_dis_col_sel; // @[issue-slot.scala:49:7]
wire [11:0] io_wakeup_ports_0_bits_uop_br_mask_0 = io_wakeup_ports_0_bits_uop_br_mask; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_0_bits_uop_br_tag_0 = io_wakeup_ports_0_bits_uop_br_tag; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_0_bits_uop_br_type_0 = io_wakeup_ports_0_bits_uop_br_type; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_is_sfb_0 = io_wakeup_ports_0_bits_uop_is_sfb; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_is_fence_0 = io_wakeup_ports_0_bits_uop_is_fence; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_is_fencei_0 = io_wakeup_ports_0_bits_uop_is_fencei; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_is_sfence_0 = io_wakeup_ports_0_bits_uop_is_sfence; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_is_amo_0 = io_wakeup_ports_0_bits_uop_is_amo; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_is_eret_0 = io_wakeup_ports_0_bits_uop_is_eret; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_0_bits_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_is_rocc_0 = io_wakeup_ports_0_bits_uop_is_rocc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_is_mov_0 = io_wakeup_ports_0_bits_uop_is_mov; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_0_bits_uop_ftq_idx_0 = io_wakeup_ports_0_bits_uop_ftq_idx; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_edge_inst_0 = io_wakeup_ports_0_bits_uop_edge_inst; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_0_bits_uop_pc_lob_0 = io_wakeup_ports_0_bits_uop_pc_lob; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_taken_0 = io_wakeup_ports_0_bits_uop_taken; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_imm_rename_0 = io_wakeup_ports_0_bits_uop_imm_rename; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_0_bits_uop_imm_sel_0 = io_wakeup_ports_0_bits_uop_imm_sel; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_0_bits_uop_pimm_0 = io_wakeup_ports_0_bits_uop_pimm; // @[issue-slot.scala:49:7]
wire [19:0] io_wakeup_ports_0_bits_uop_imm_packed_0 = io_wakeup_ports_0_bits_uop_imm_packed; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_0_bits_uop_op1_sel_0 = io_wakeup_ports_0_bits_uop_op1_sel; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_0_bits_uop_op2_sel_0 = io_wakeup_ports_0_bits_uop_op2_sel; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_div; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_0_bits_uop_rob_idx_0 = io_wakeup_ports_0_bits_uop_rob_idx; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_0_bits_uop_ldq_idx_0 = io_wakeup_ports_0_bits_uop_ldq_idx; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_0_bits_uop_stq_idx_0 = io_wakeup_ports_0_bits_uop_stq_idx; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_0_bits_uop_rxq_idx_0 = io_wakeup_ports_0_bits_uop_rxq_idx; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_0_bits_uop_pdst_0 = io_wakeup_ports_0_bits_uop_pdst; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_0_bits_uop_prs1_0 = io_wakeup_ports_0_bits_uop_prs1; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_0_bits_uop_prs2_0 = io_wakeup_ports_0_bits_uop_prs2; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_0_bits_uop_prs3_0 = io_wakeup_ports_0_bits_uop_prs3; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_0_bits_uop_ppred_0 = io_wakeup_ports_0_bits_uop_ppred; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_prs1_busy_0 = io_wakeup_ports_0_bits_uop_prs1_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_prs2_busy_0 = io_wakeup_ports_0_bits_uop_prs2_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_prs3_busy_0 = io_wakeup_ports_0_bits_uop_prs3_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_ppred_busy_0 = io_wakeup_ports_0_bits_uop_ppred_busy; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_0_bits_uop_stale_pdst_0 = io_wakeup_ports_0_bits_uop_stale_pdst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_exception_0 = io_wakeup_ports_0_bits_uop_exception; // @[issue-slot.scala:49:7]
wire [63:0] io_wakeup_ports_0_bits_uop_exc_cause_0 = io_wakeup_ports_0_bits_uop_exc_cause; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_0_bits_uop_mem_cmd_0 = io_wakeup_ports_0_bits_uop_mem_cmd; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_0_bits_uop_mem_size_0 = io_wakeup_ports_0_bits_uop_mem_size; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_mem_signed_0 = io_wakeup_ports_0_bits_uop_mem_signed; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_uses_ldq_0 = io_wakeup_ports_0_bits_uop_uses_ldq; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_uses_stq_0 = io_wakeup_ports_0_bits_uop_uses_stq; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_is_unique_0 = io_wakeup_ports_0_bits_uop_is_unique; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_flush_on_commit_0 = io_wakeup_ports_0_bits_uop_flush_on_commit; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_0_bits_uop_csr_cmd_0 = io_wakeup_ports_0_bits_uop_csr_cmd; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_0_bits_uop_ldst_is_rs1; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_0_bits_uop_ldst_0 = io_wakeup_ports_0_bits_uop_ldst; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_0_bits_uop_lrs1_0 = io_wakeup_ports_0_bits_uop_lrs1; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_0_bits_uop_lrs2_0 = io_wakeup_ports_0_bits_uop_lrs2; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_0_bits_uop_lrs3_0 = io_wakeup_ports_0_bits_uop_lrs3; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_0_bits_uop_dst_rtype_0 = io_wakeup_ports_0_bits_uop_dst_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_0_bits_uop_lrs1_rtype_0 = io_wakeup_ports_0_bits_uop_lrs1_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_0_bits_uop_lrs2_rtype_0 = io_wakeup_ports_0_bits_uop_lrs2_rtype; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_frs3_en_0 = io_wakeup_ports_0_bits_uop_frs3_en; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fcn_dw_0 = io_wakeup_ports_0_bits_uop_fcn_dw; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_0_bits_uop_fcn_op_0 = io_wakeup_ports_0_bits_uop_fcn_op; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_val_0 = io_wakeup_ports_0_bits_uop_fp_val; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_0_bits_uop_fp_rm_0 = io_wakeup_ports_0_bits_uop_fp_rm; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_0_bits_uop_fp_typ_0 = io_wakeup_ports_0_bits_uop_fp_typ; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_0_bits_uop_xcpt_pf_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_0_bits_uop_xcpt_ae_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_0_bits_uop_xcpt_ma_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_bp_debug_if_0 = io_wakeup_ports_0_bits_uop_bp_debug_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_0_bits_uop_bp_xcpt_if; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_0_bits_uop_debug_fsrc_0 = io_wakeup_ports_0_bits_uop_debug_fsrc; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_0_bits_uop_debug_tsrc_0 = io_wakeup_ports_0_bits_uop_debug_tsrc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_bypassable_0 = io_wakeup_ports_0_bits_bypassable; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_0_bits_speculative_mask_0 = io_wakeup_ports_0_bits_speculative_mask; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_rebusy_0 = io_wakeup_ports_0_bits_rebusy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_valid_0 = io_wakeup_ports_1_valid; // @[issue-slot.scala:49:7]
wire [31:0] io_wakeup_ports_1_bits_uop_inst_0 = io_wakeup_ports_1_bits_uop_inst; // @[issue-slot.scala:49:7]
wire [31:0] io_wakeup_ports_1_bits_uop_debug_inst_0 = io_wakeup_ports_1_bits_uop_debug_inst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_is_rvc_0 = io_wakeup_ports_1_bits_uop_is_rvc; // @[issue-slot.scala:49:7]
wire [39:0] io_wakeup_ports_1_bits_uop_debug_pc_0 = io_wakeup_ports_1_bits_uop_debug_pc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_iq_type_0_0 = io_wakeup_ports_1_bits_uop_iq_type_0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_iq_type_1_0 = io_wakeup_ports_1_bits_uop_iq_type_1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_iq_type_2_0 = io_wakeup_ports_1_bits_uop_iq_type_2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_iq_type_3_0 = io_wakeup_ports_1_bits_uop_iq_type_3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fu_code_0_0 = io_wakeup_ports_1_bits_uop_fu_code_0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fu_code_1_0 = io_wakeup_ports_1_bits_uop_fu_code_1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fu_code_2_0 = io_wakeup_ports_1_bits_uop_fu_code_2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fu_code_3_0 = io_wakeup_ports_1_bits_uop_fu_code_3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fu_code_4_0 = io_wakeup_ports_1_bits_uop_fu_code_4; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fu_code_5_0 = io_wakeup_ports_1_bits_uop_fu_code_5; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fu_code_6_0 = io_wakeup_ports_1_bits_uop_fu_code_6; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fu_code_7_0 = io_wakeup_ports_1_bits_uop_fu_code_7; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fu_code_8_0 = io_wakeup_ports_1_bits_uop_fu_code_8; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fu_code_9_0 = io_wakeup_ports_1_bits_uop_fu_code_9; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_iw_issued_0 = io_wakeup_ports_1_bits_uop_iw_issued; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_iw_issued_partial_agen_0 = io_wakeup_ports_1_bits_uop_iw_issued_partial_agen; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen_0 = io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_1_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_1_bits_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_1_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_1_bits_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_1_bits_uop_dis_col_sel_0 = io_wakeup_ports_1_bits_uop_dis_col_sel; // @[issue-slot.scala:49:7]
wire [11:0] io_wakeup_ports_1_bits_uop_br_mask_0 = io_wakeup_ports_1_bits_uop_br_mask; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_1_bits_uop_br_tag_0 = io_wakeup_ports_1_bits_uop_br_tag; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_1_bits_uop_br_type_0 = io_wakeup_ports_1_bits_uop_br_type; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_is_sfb_0 = io_wakeup_ports_1_bits_uop_is_sfb; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_is_fence_0 = io_wakeup_ports_1_bits_uop_is_fence; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_is_fencei_0 = io_wakeup_ports_1_bits_uop_is_fencei; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_is_sfence_0 = io_wakeup_ports_1_bits_uop_is_sfence; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_is_amo_0 = io_wakeup_ports_1_bits_uop_is_amo; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_is_eret_0 = io_wakeup_ports_1_bits_uop_is_eret; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_1_bits_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_is_rocc_0 = io_wakeup_ports_1_bits_uop_is_rocc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_is_mov_0 = io_wakeup_ports_1_bits_uop_is_mov; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_1_bits_uop_ftq_idx_0 = io_wakeup_ports_1_bits_uop_ftq_idx; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_edge_inst_0 = io_wakeup_ports_1_bits_uop_edge_inst; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_1_bits_uop_pc_lob_0 = io_wakeup_ports_1_bits_uop_pc_lob; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_taken_0 = io_wakeup_ports_1_bits_uop_taken; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_imm_rename_0 = io_wakeup_ports_1_bits_uop_imm_rename; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_1_bits_uop_imm_sel_0 = io_wakeup_ports_1_bits_uop_imm_sel; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_1_bits_uop_pimm_0 = io_wakeup_ports_1_bits_uop_pimm; // @[issue-slot.scala:49:7]
wire [19:0] io_wakeup_ports_1_bits_uop_imm_packed_0 = io_wakeup_ports_1_bits_uop_imm_packed; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_1_bits_uop_op1_sel_0 = io_wakeup_ports_1_bits_uop_op1_sel; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_1_bits_uop_op2_sel_0 = io_wakeup_ports_1_bits_uop_op2_sel; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_div; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_1_bits_uop_rob_idx_0 = io_wakeup_ports_1_bits_uop_rob_idx; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_1_bits_uop_ldq_idx_0 = io_wakeup_ports_1_bits_uop_ldq_idx; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_1_bits_uop_stq_idx_0 = io_wakeup_ports_1_bits_uop_stq_idx; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_1_bits_uop_rxq_idx_0 = io_wakeup_ports_1_bits_uop_rxq_idx; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_1_bits_uop_pdst_0 = io_wakeup_ports_1_bits_uop_pdst; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_1_bits_uop_prs1_0 = io_wakeup_ports_1_bits_uop_prs1; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_1_bits_uop_prs2_0 = io_wakeup_ports_1_bits_uop_prs2; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_1_bits_uop_prs3_0 = io_wakeup_ports_1_bits_uop_prs3; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_1_bits_uop_ppred_0 = io_wakeup_ports_1_bits_uop_ppred; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_prs1_busy_0 = io_wakeup_ports_1_bits_uop_prs1_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_prs2_busy_0 = io_wakeup_ports_1_bits_uop_prs2_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_prs3_busy_0 = io_wakeup_ports_1_bits_uop_prs3_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_ppred_busy_0 = io_wakeup_ports_1_bits_uop_ppred_busy; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_1_bits_uop_stale_pdst_0 = io_wakeup_ports_1_bits_uop_stale_pdst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_exception_0 = io_wakeup_ports_1_bits_uop_exception; // @[issue-slot.scala:49:7]
wire [63:0] io_wakeup_ports_1_bits_uop_exc_cause_0 = io_wakeup_ports_1_bits_uop_exc_cause; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_1_bits_uop_mem_cmd_0 = io_wakeup_ports_1_bits_uop_mem_cmd; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_1_bits_uop_mem_size_0 = io_wakeup_ports_1_bits_uop_mem_size; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_mem_signed_0 = io_wakeup_ports_1_bits_uop_mem_signed; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_uses_ldq_0 = io_wakeup_ports_1_bits_uop_uses_ldq; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_uses_stq_0 = io_wakeup_ports_1_bits_uop_uses_stq; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_is_unique_0 = io_wakeup_ports_1_bits_uop_is_unique; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_flush_on_commit_0 = io_wakeup_ports_1_bits_uop_flush_on_commit; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_1_bits_uop_csr_cmd_0 = io_wakeup_ports_1_bits_uop_csr_cmd; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_1_bits_uop_ldst_is_rs1; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_1_bits_uop_ldst_0 = io_wakeup_ports_1_bits_uop_ldst; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_1_bits_uop_lrs1_0 = io_wakeup_ports_1_bits_uop_lrs1; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_1_bits_uop_lrs2_0 = io_wakeup_ports_1_bits_uop_lrs2; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_1_bits_uop_lrs3_0 = io_wakeup_ports_1_bits_uop_lrs3; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_1_bits_uop_dst_rtype_0 = io_wakeup_ports_1_bits_uop_dst_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_1_bits_uop_lrs1_rtype_0 = io_wakeup_ports_1_bits_uop_lrs1_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_1_bits_uop_lrs2_rtype_0 = io_wakeup_ports_1_bits_uop_lrs2_rtype; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_frs3_en_0 = io_wakeup_ports_1_bits_uop_frs3_en; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fcn_dw_0 = io_wakeup_ports_1_bits_uop_fcn_dw; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_1_bits_uop_fcn_op_0 = io_wakeup_ports_1_bits_uop_fcn_op; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_val_0 = io_wakeup_ports_1_bits_uop_fp_val; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_1_bits_uop_fp_rm_0 = io_wakeup_ports_1_bits_uop_fp_rm; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_1_bits_uop_fp_typ_0 = io_wakeup_ports_1_bits_uop_fp_typ; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_1_bits_uop_xcpt_pf_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_1_bits_uop_xcpt_ae_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_1_bits_uop_xcpt_ma_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_bp_debug_if_0 = io_wakeup_ports_1_bits_uop_bp_debug_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_1_bits_uop_bp_xcpt_if; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_1_bits_uop_debug_fsrc_0 = io_wakeup_ports_1_bits_uop_debug_fsrc; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_1_bits_uop_debug_tsrc_0 = io_wakeup_ports_1_bits_uop_debug_tsrc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_valid_0 = io_wakeup_ports_2_valid; // @[issue-slot.scala:49:7]
wire [31:0] io_wakeup_ports_2_bits_uop_inst_0 = io_wakeup_ports_2_bits_uop_inst; // @[issue-slot.scala:49:7]
wire [31:0] io_wakeup_ports_2_bits_uop_debug_inst_0 = io_wakeup_ports_2_bits_uop_debug_inst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_is_rvc_0 = io_wakeup_ports_2_bits_uop_is_rvc; // @[issue-slot.scala:49:7]
wire [39:0] io_wakeup_ports_2_bits_uop_debug_pc_0 = io_wakeup_ports_2_bits_uop_debug_pc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_iq_type_0_0 = io_wakeup_ports_2_bits_uop_iq_type_0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_iq_type_1_0 = io_wakeup_ports_2_bits_uop_iq_type_1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_iq_type_2_0 = io_wakeup_ports_2_bits_uop_iq_type_2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_iq_type_3_0 = io_wakeup_ports_2_bits_uop_iq_type_3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fu_code_0_0 = io_wakeup_ports_2_bits_uop_fu_code_0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fu_code_1_0 = io_wakeup_ports_2_bits_uop_fu_code_1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fu_code_2_0 = io_wakeup_ports_2_bits_uop_fu_code_2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fu_code_3_0 = io_wakeup_ports_2_bits_uop_fu_code_3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fu_code_4_0 = io_wakeup_ports_2_bits_uop_fu_code_4; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fu_code_5_0 = io_wakeup_ports_2_bits_uop_fu_code_5; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fu_code_6_0 = io_wakeup_ports_2_bits_uop_fu_code_6; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fu_code_7_0 = io_wakeup_ports_2_bits_uop_fu_code_7; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fu_code_8_0 = io_wakeup_ports_2_bits_uop_fu_code_8; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fu_code_9_0 = io_wakeup_ports_2_bits_uop_fu_code_9; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_iw_issued_0 = io_wakeup_ports_2_bits_uop_iw_issued; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_2_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_2_bits_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_2_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_2_bits_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_2_bits_uop_dis_col_sel_0 = io_wakeup_ports_2_bits_uop_dis_col_sel; // @[issue-slot.scala:49:7]
wire [11:0] io_wakeup_ports_2_bits_uop_br_mask_0 = io_wakeup_ports_2_bits_uop_br_mask; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_2_bits_uop_br_tag_0 = io_wakeup_ports_2_bits_uop_br_tag; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_2_bits_uop_br_type_0 = io_wakeup_ports_2_bits_uop_br_type; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_is_sfb_0 = io_wakeup_ports_2_bits_uop_is_sfb; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_is_fence_0 = io_wakeup_ports_2_bits_uop_is_fence; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_is_fencei_0 = io_wakeup_ports_2_bits_uop_is_fencei; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_is_sfence_0 = io_wakeup_ports_2_bits_uop_is_sfence; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_is_amo_0 = io_wakeup_ports_2_bits_uop_is_amo; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_is_eret_0 = io_wakeup_ports_2_bits_uop_is_eret; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_2_bits_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_is_rocc_0 = io_wakeup_ports_2_bits_uop_is_rocc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_is_mov_0 = io_wakeup_ports_2_bits_uop_is_mov; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_2_bits_uop_ftq_idx_0 = io_wakeup_ports_2_bits_uop_ftq_idx; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_edge_inst_0 = io_wakeup_ports_2_bits_uop_edge_inst; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_2_bits_uop_pc_lob_0 = io_wakeup_ports_2_bits_uop_pc_lob; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_taken_0 = io_wakeup_ports_2_bits_uop_taken; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_imm_rename_0 = io_wakeup_ports_2_bits_uop_imm_rename; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_2_bits_uop_imm_sel_0 = io_wakeup_ports_2_bits_uop_imm_sel; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_2_bits_uop_pimm_0 = io_wakeup_ports_2_bits_uop_pimm; // @[issue-slot.scala:49:7]
wire [19:0] io_wakeup_ports_2_bits_uop_imm_packed_0 = io_wakeup_ports_2_bits_uop_imm_packed; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_2_bits_uop_op1_sel_0 = io_wakeup_ports_2_bits_uop_op1_sel; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_2_bits_uop_op2_sel_0 = io_wakeup_ports_2_bits_uop_op2_sel; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_div; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_2_bits_uop_rob_idx_0 = io_wakeup_ports_2_bits_uop_rob_idx; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_2_bits_uop_ldq_idx_0 = io_wakeup_ports_2_bits_uop_ldq_idx; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_2_bits_uop_stq_idx_0 = io_wakeup_ports_2_bits_uop_stq_idx; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_2_bits_uop_rxq_idx_0 = io_wakeup_ports_2_bits_uop_rxq_idx; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_2_bits_uop_pdst_0 = io_wakeup_ports_2_bits_uop_pdst; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_2_bits_uop_prs1_0 = io_wakeup_ports_2_bits_uop_prs1; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_2_bits_uop_prs2_0 = io_wakeup_ports_2_bits_uop_prs2; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_2_bits_uop_prs3_0 = io_wakeup_ports_2_bits_uop_prs3; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_2_bits_uop_ppred_0 = io_wakeup_ports_2_bits_uop_ppred; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_prs1_busy_0 = io_wakeup_ports_2_bits_uop_prs1_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_prs2_busy_0 = io_wakeup_ports_2_bits_uop_prs2_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_prs3_busy_0 = io_wakeup_ports_2_bits_uop_prs3_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_ppred_busy_0 = io_wakeup_ports_2_bits_uop_ppred_busy; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_2_bits_uop_stale_pdst_0 = io_wakeup_ports_2_bits_uop_stale_pdst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_exception_0 = io_wakeup_ports_2_bits_uop_exception; // @[issue-slot.scala:49:7]
wire [63:0] io_wakeup_ports_2_bits_uop_exc_cause_0 = io_wakeup_ports_2_bits_uop_exc_cause; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_2_bits_uop_mem_cmd_0 = io_wakeup_ports_2_bits_uop_mem_cmd; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_2_bits_uop_mem_size_0 = io_wakeup_ports_2_bits_uop_mem_size; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_mem_signed_0 = io_wakeup_ports_2_bits_uop_mem_signed; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_uses_ldq_0 = io_wakeup_ports_2_bits_uop_uses_ldq; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_uses_stq_0 = io_wakeup_ports_2_bits_uop_uses_stq; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_is_unique_0 = io_wakeup_ports_2_bits_uop_is_unique; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_flush_on_commit_0 = io_wakeup_ports_2_bits_uop_flush_on_commit; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_2_bits_uop_csr_cmd_0 = io_wakeup_ports_2_bits_uop_csr_cmd; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_2_bits_uop_ldst_is_rs1; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_2_bits_uop_ldst_0 = io_wakeup_ports_2_bits_uop_ldst; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_2_bits_uop_lrs1_0 = io_wakeup_ports_2_bits_uop_lrs1; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_2_bits_uop_lrs2_0 = io_wakeup_ports_2_bits_uop_lrs2; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_2_bits_uop_lrs3_0 = io_wakeup_ports_2_bits_uop_lrs3; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_2_bits_uop_dst_rtype_0 = io_wakeup_ports_2_bits_uop_dst_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_2_bits_uop_lrs1_rtype_0 = io_wakeup_ports_2_bits_uop_lrs1_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_2_bits_uop_lrs2_rtype_0 = io_wakeup_ports_2_bits_uop_lrs2_rtype; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_frs3_en_0 = io_wakeup_ports_2_bits_uop_frs3_en; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fcn_dw_0 = io_wakeup_ports_2_bits_uop_fcn_dw; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_2_bits_uop_fcn_op_0 = io_wakeup_ports_2_bits_uop_fcn_op; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_val_0 = io_wakeup_ports_2_bits_uop_fp_val; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_2_bits_uop_fp_rm_0 = io_wakeup_ports_2_bits_uop_fp_rm; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_2_bits_uop_fp_typ_0 = io_wakeup_ports_2_bits_uop_fp_typ; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_2_bits_uop_xcpt_pf_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_2_bits_uop_xcpt_ae_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_2_bits_uop_xcpt_ma_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_bp_debug_if_0 = io_wakeup_ports_2_bits_uop_bp_debug_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_2_bits_uop_bp_xcpt_if; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_2_bits_uop_debug_fsrc_0 = io_wakeup_ports_2_bits_uop_debug_fsrc; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_2_bits_uop_debug_tsrc_0 = io_wakeup_ports_2_bits_uop_debug_tsrc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_valid_0 = io_wakeup_ports_3_valid; // @[issue-slot.scala:49:7]
wire [31:0] io_wakeup_ports_3_bits_uop_inst_0 = io_wakeup_ports_3_bits_uop_inst; // @[issue-slot.scala:49:7]
wire [31:0] io_wakeup_ports_3_bits_uop_debug_inst_0 = io_wakeup_ports_3_bits_uop_debug_inst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_is_rvc_0 = io_wakeup_ports_3_bits_uop_is_rvc; // @[issue-slot.scala:49:7]
wire [39:0] io_wakeup_ports_3_bits_uop_debug_pc_0 = io_wakeup_ports_3_bits_uop_debug_pc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_iq_type_0_0 = io_wakeup_ports_3_bits_uop_iq_type_0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_iq_type_1_0 = io_wakeup_ports_3_bits_uop_iq_type_1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_iq_type_2_0 = io_wakeup_ports_3_bits_uop_iq_type_2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_iq_type_3_0 = io_wakeup_ports_3_bits_uop_iq_type_3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fu_code_0_0 = io_wakeup_ports_3_bits_uop_fu_code_0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fu_code_1_0 = io_wakeup_ports_3_bits_uop_fu_code_1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fu_code_2_0 = io_wakeup_ports_3_bits_uop_fu_code_2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fu_code_3_0 = io_wakeup_ports_3_bits_uop_fu_code_3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fu_code_4_0 = io_wakeup_ports_3_bits_uop_fu_code_4; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fu_code_5_0 = io_wakeup_ports_3_bits_uop_fu_code_5; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fu_code_6_0 = io_wakeup_ports_3_bits_uop_fu_code_6; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fu_code_7_0 = io_wakeup_ports_3_bits_uop_fu_code_7; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fu_code_8_0 = io_wakeup_ports_3_bits_uop_fu_code_8; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fu_code_9_0 = io_wakeup_ports_3_bits_uop_fu_code_9; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_iw_issued_0 = io_wakeup_ports_3_bits_uop_iw_issued; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_3_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_3_bits_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_3_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_3_bits_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_3_bits_uop_dis_col_sel_0 = io_wakeup_ports_3_bits_uop_dis_col_sel; // @[issue-slot.scala:49:7]
wire [11:0] io_wakeup_ports_3_bits_uop_br_mask_0 = io_wakeup_ports_3_bits_uop_br_mask; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_3_bits_uop_br_tag_0 = io_wakeup_ports_3_bits_uop_br_tag; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_3_bits_uop_br_type_0 = io_wakeup_ports_3_bits_uop_br_type; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_is_sfb_0 = io_wakeup_ports_3_bits_uop_is_sfb; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_is_fence_0 = io_wakeup_ports_3_bits_uop_is_fence; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_is_fencei_0 = io_wakeup_ports_3_bits_uop_is_fencei; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_is_sfence_0 = io_wakeup_ports_3_bits_uop_is_sfence; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_is_amo_0 = io_wakeup_ports_3_bits_uop_is_amo; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_is_eret_0 = io_wakeup_ports_3_bits_uop_is_eret; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_3_bits_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_is_rocc_0 = io_wakeup_ports_3_bits_uop_is_rocc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_is_mov_0 = io_wakeup_ports_3_bits_uop_is_mov; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_3_bits_uop_ftq_idx_0 = io_wakeup_ports_3_bits_uop_ftq_idx; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_edge_inst_0 = io_wakeup_ports_3_bits_uop_edge_inst; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_3_bits_uop_pc_lob_0 = io_wakeup_ports_3_bits_uop_pc_lob; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_taken_0 = io_wakeup_ports_3_bits_uop_taken; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_imm_rename_0 = io_wakeup_ports_3_bits_uop_imm_rename; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_3_bits_uop_imm_sel_0 = io_wakeup_ports_3_bits_uop_imm_sel; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_3_bits_uop_pimm_0 = io_wakeup_ports_3_bits_uop_pimm; // @[issue-slot.scala:49:7]
wire [19:0] io_wakeup_ports_3_bits_uop_imm_packed_0 = io_wakeup_ports_3_bits_uop_imm_packed; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_3_bits_uop_op1_sel_0 = io_wakeup_ports_3_bits_uop_op1_sel; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_3_bits_uop_op2_sel_0 = io_wakeup_ports_3_bits_uop_op2_sel; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_div; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_3_bits_uop_rob_idx_0 = io_wakeup_ports_3_bits_uop_rob_idx; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_3_bits_uop_ldq_idx_0 = io_wakeup_ports_3_bits_uop_ldq_idx; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_3_bits_uop_stq_idx_0 = io_wakeup_ports_3_bits_uop_stq_idx; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_3_bits_uop_rxq_idx_0 = io_wakeup_ports_3_bits_uop_rxq_idx; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_3_bits_uop_pdst_0 = io_wakeup_ports_3_bits_uop_pdst; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_3_bits_uop_prs1_0 = io_wakeup_ports_3_bits_uop_prs1; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_3_bits_uop_prs2_0 = io_wakeup_ports_3_bits_uop_prs2; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_3_bits_uop_prs3_0 = io_wakeup_ports_3_bits_uop_prs3; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_3_bits_uop_ppred_0 = io_wakeup_ports_3_bits_uop_ppred; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_prs1_busy_0 = io_wakeup_ports_3_bits_uop_prs1_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_prs2_busy_0 = io_wakeup_ports_3_bits_uop_prs2_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_prs3_busy_0 = io_wakeup_ports_3_bits_uop_prs3_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_ppred_busy_0 = io_wakeup_ports_3_bits_uop_ppred_busy; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_3_bits_uop_stale_pdst_0 = io_wakeup_ports_3_bits_uop_stale_pdst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_exception_0 = io_wakeup_ports_3_bits_uop_exception; // @[issue-slot.scala:49:7]
wire [63:0] io_wakeup_ports_3_bits_uop_exc_cause_0 = io_wakeup_ports_3_bits_uop_exc_cause; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_3_bits_uop_mem_cmd_0 = io_wakeup_ports_3_bits_uop_mem_cmd; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_3_bits_uop_mem_size_0 = io_wakeup_ports_3_bits_uop_mem_size; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_mem_signed_0 = io_wakeup_ports_3_bits_uop_mem_signed; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_uses_ldq_0 = io_wakeup_ports_3_bits_uop_uses_ldq; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_uses_stq_0 = io_wakeup_ports_3_bits_uop_uses_stq; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_is_unique_0 = io_wakeup_ports_3_bits_uop_is_unique; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_flush_on_commit_0 = io_wakeup_ports_3_bits_uop_flush_on_commit; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_3_bits_uop_csr_cmd_0 = io_wakeup_ports_3_bits_uop_csr_cmd; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_3_bits_uop_ldst_is_rs1; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_3_bits_uop_ldst_0 = io_wakeup_ports_3_bits_uop_ldst; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_3_bits_uop_lrs1_0 = io_wakeup_ports_3_bits_uop_lrs1; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_3_bits_uop_lrs2_0 = io_wakeup_ports_3_bits_uop_lrs2; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_3_bits_uop_lrs3_0 = io_wakeup_ports_3_bits_uop_lrs3; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_3_bits_uop_dst_rtype_0 = io_wakeup_ports_3_bits_uop_dst_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_3_bits_uop_lrs1_rtype_0 = io_wakeup_ports_3_bits_uop_lrs1_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_3_bits_uop_lrs2_rtype_0 = io_wakeup_ports_3_bits_uop_lrs2_rtype; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_frs3_en_0 = io_wakeup_ports_3_bits_uop_frs3_en; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fcn_dw_0 = io_wakeup_ports_3_bits_uop_fcn_dw; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_3_bits_uop_fcn_op_0 = io_wakeup_ports_3_bits_uop_fcn_op; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_val_0 = io_wakeup_ports_3_bits_uop_fp_val; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_3_bits_uop_fp_rm_0 = io_wakeup_ports_3_bits_uop_fp_rm; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_3_bits_uop_fp_typ_0 = io_wakeup_ports_3_bits_uop_fp_typ; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_3_bits_uop_xcpt_pf_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_3_bits_uop_xcpt_ae_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_3_bits_uop_xcpt_ma_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_bp_debug_if_0 = io_wakeup_ports_3_bits_uop_bp_debug_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_3_bits_uop_bp_xcpt_if; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_3_bits_uop_debug_fsrc_0 = io_wakeup_ports_3_bits_uop_debug_fsrc; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_3_bits_uop_debug_tsrc_0 = io_wakeup_ports_3_bits_uop_debug_tsrc; // @[issue-slot.scala:49:7]
wire [1:0] io_child_rebusys_0 = io_child_rebusys; // @[issue-slot.scala:49:7]
wire io_iss_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7]
wire io_iss_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7]
wire io_out_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7]
wire io_out_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_bypassable = 1'h0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_rebusy = 1'h0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_rebusy = 1'h0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_rebusy = 1'h0; // @[issue-slot.scala:49:7]
wire io_pred_wakeup_port_valid = 1'h0; // @[issue-slot.scala:49:7]
wire next_uop_out_iw_issued_partial_agen = 1'h0; // @[util.scala:104:23]
wire next_uop_out_iw_issued_partial_dgen = 1'h0; // @[util.scala:104:23]
wire next_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:59:28]
wire next_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:59:28]
wire prs1_rebusys_1 = 1'h0; // @[issue-slot.scala:102:91]
wire prs1_rebusys_2 = 1'h0; // @[issue-slot.scala:102:91]
wire prs1_rebusys_3 = 1'h0; // @[issue-slot.scala:102:91]
wire prs2_rebusys_1 = 1'h0; // @[issue-slot.scala:103:91]
wire prs2_rebusys_2 = 1'h0; // @[issue-slot.scala:103:91]
wire prs2_rebusys_3 = 1'h0; // @[issue-slot.scala:103:91]
wire _next_uop_iw_p1_bypass_hint_T_1 = 1'h0; // @[Mux.scala:30:73]
wire _next_uop_iw_p2_bypass_hint_T_1 = 1'h0; // @[Mux.scala:30:73]
wire _next_uop_iw_p3_bypass_hint_T_1 = 1'h0; // @[Mux.scala:30:73]
wire _iss_ready_T_6 = 1'h0; // @[issue-slot.scala:136:131]
wire agen_ready = 1'h0; // @[issue-slot.scala:137:114]
wire dgen_ready = 1'h0; // @[issue-slot.scala:138:114]
wire [1:0] io_wakeup_ports_1_bits_speculative_mask = 2'h0; // @[issue-slot.scala:49:7]
wire [1:0] _next_uop_iw_p1_speculative_child_T_1 = 2'h0; // @[Mux.scala:30:73]
wire [1:0] _next_uop_iw_p2_speculative_child_T_1 = 2'h0; // @[Mux.scala:30:73]
wire io_wakeup_ports_2_bits_bypassable = 1'h1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_bypassable = 1'h1; // @[issue-slot.scala:49:7]
wire _iss_ready_T_7 = 1'h1; // @[issue-slot.scala:136:110]
wire [1:0] io_wakeup_ports_2_bits_speculative_mask = 2'h1; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_3_bits_speculative_mask = 2'h2; // @[issue-slot.scala:49:7]
wire [4:0] io_pred_wakeup_port_bits = 5'h0; // @[issue-slot.scala:49:7]
wire _io_will_be_valid_T_1; // @[issue-slot.scala:65:34]
wire _io_request_T_4; // @[issue-slot.scala:140:51]
wire [31:0] next_uop_inst; // @[issue-slot.scala:59:28]
wire [31:0] next_uop_debug_inst; // @[issue-slot.scala:59:28]
wire next_uop_is_rvc; // @[issue-slot.scala:59:28]
wire [39:0] next_uop_debug_pc; // @[issue-slot.scala:59:28]
wire next_uop_iq_type_0; // @[issue-slot.scala:59:28]
wire next_uop_iq_type_1; // @[issue-slot.scala:59:28]
wire next_uop_iq_type_2; // @[issue-slot.scala:59:28]
wire next_uop_iq_type_3; // @[issue-slot.scala:59:28]
wire next_uop_fu_code_0; // @[issue-slot.scala:59:28]
wire next_uop_fu_code_1; // @[issue-slot.scala:59:28]
wire next_uop_fu_code_2; // @[issue-slot.scala:59:28]
wire next_uop_fu_code_3; // @[issue-slot.scala:59:28]
wire next_uop_fu_code_4; // @[issue-slot.scala:59:28]
wire next_uop_fu_code_5; // @[issue-slot.scala:59:28]
wire next_uop_fu_code_6; // @[issue-slot.scala:59:28]
wire next_uop_fu_code_7; // @[issue-slot.scala:59:28]
wire next_uop_fu_code_8; // @[issue-slot.scala:59:28]
wire next_uop_fu_code_9; // @[issue-slot.scala:59:28]
wire next_uop_iw_issued; // @[issue-slot.scala:59:28]
wire [1:0] next_uop_iw_p1_speculative_child; // @[issue-slot.scala:59:28]
wire [1:0] next_uop_iw_p2_speculative_child; // @[issue-slot.scala:59:28]
wire next_uop_iw_p1_bypass_hint; // @[issue-slot.scala:59:28]
wire next_uop_iw_p2_bypass_hint; // @[issue-slot.scala:59:28]
wire next_uop_iw_p3_bypass_hint; // @[issue-slot.scala:59:28]
wire [1:0] next_uop_dis_col_sel; // @[issue-slot.scala:59:28]
wire [11:0] next_uop_br_mask; // @[issue-slot.scala:59:28]
wire [3:0] next_uop_br_tag; // @[issue-slot.scala:59:28]
wire [3:0] next_uop_br_type; // @[issue-slot.scala:59:28]
wire next_uop_is_sfb; // @[issue-slot.scala:59:28]
wire next_uop_is_fence; // @[issue-slot.scala:59:28]
wire next_uop_is_fencei; // @[issue-slot.scala:59:28]
wire next_uop_is_sfence; // @[issue-slot.scala:59:28]
wire next_uop_is_amo; // @[issue-slot.scala:59:28]
wire next_uop_is_eret; // @[issue-slot.scala:59:28]
wire next_uop_is_sys_pc2epc; // @[issue-slot.scala:59:28]
wire next_uop_is_rocc; // @[issue-slot.scala:59:28]
wire next_uop_is_mov; // @[issue-slot.scala:59:28]
wire [4:0] next_uop_ftq_idx; // @[issue-slot.scala:59:28]
wire next_uop_edge_inst; // @[issue-slot.scala:59:28]
wire [5:0] next_uop_pc_lob; // @[issue-slot.scala:59:28]
wire next_uop_taken; // @[issue-slot.scala:59:28]
wire next_uop_imm_rename; // @[issue-slot.scala:59:28]
wire [2:0] next_uop_imm_sel; // @[issue-slot.scala:59:28]
wire [4:0] next_uop_pimm; // @[issue-slot.scala:59:28]
wire [19:0] next_uop_imm_packed; // @[issue-slot.scala:59:28]
wire [1:0] next_uop_op1_sel; // @[issue-slot.scala:59:28]
wire [2:0] next_uop_op2_sel; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_ldst; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_wen; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_ren1; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_ren2; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_ren3; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_swap12; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_swap23; // @[issue-slot.scala:59:28]
wire [1:0] next_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:59:28]
wire [1:0] next_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_fromint; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_toint; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_fma; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_div; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_sqrt; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_wflags; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_vec; // @[issue-slot.scala:59:28]
wire [5:0] next_uop_rob_idx; // @[issue-slot.scala:59:28]
wire [3:0] next_uop_ldq_idx; // @[issue-slot.scala:59:28]
wire [3:0] next_uop_stq_idx; // @[issue-slot.scala:59:28]
wire [1:0] next_uop_rxq_idx; // @[issue-slot.scala:59:28]
wire [6:0] next_uop_pdst; // @[issue-slot.scala:59:28]
wire [6:0] next_uop_prs1; // @[issue-slot.scala:59:28]
wire [6:0] next_uop_prs2; // @[issue-slot.scala:59:28]
wire [6:0] next_uop_prs3; // @[issue-slot.scala:59:28]
wire [4:0] next_uop_ppred; // @[issue-slot.scala:59:28]
wire next_uop_prs1_busy; // @[issue-slot.scala:59:28]
wire next_uop_prs2_busy; // @[issue-slot.scala:59:28]
wire next_uop_prs3_busy; // @[issue-slot.scala:59:28]
wire next_uop_ppred_busy; // @[issue-slot.scala:59:28]
wire [6:0] next_uop_stale_pdst; // @[issue-slot.scala:59:28]
wire next_uop_exception; // @[issue-slot.scala:59:28]
wire [63:0] next_uop_exc_cause; // @[issue-slot.scala:59:28]
wire [4:0] next_uop_mem_cmd; // @[issue-slot.scala:59:28]
wire [1:0] next_uop_mem_size; // @[issue-slot.scala:59:28]
wire next_uop_mem_signed; // @[issue-slot.scala:59:28]
wire next_uop_uses_ldq; // @[issue-slot.scala:59:28]
wire next_uop_uses_stq; // @[issue-slot.scala:59:28]
wire next_uop_is_unique; // @[issue-slot.scala:59:28]
wire next_uop_flush_on_commit; // @[issue-slot.scala:59:28]
wire [2:0] next_uop_csr_cmd; // @[issue-slot.scala:59:28]
wire next_uop_ldst_is_rs1; // @[issue-slot.scala:59:28]
wire [5:0] next_uop_ldst; // @[issue-slot.scala:59:28]
wire [5:0] next_uop_lrs1; // @[issue-slot.scala:59:28]
wire [5:0] next_uop_lrs2; // @[issue-slot.scala:59:28]
wire [5:0] next_uop_lrs3; // @[issue-slot.scala:59:28]
wire [1:0] next_uop_dst_rtype; // @[issue-slot.scala:59:28]
wire [1:0] next_uop_lrs1_rtype; // @[issue-slot.scala:59:28]
wire [1:0] next_uop_lrs2_rtype; // @[issue-slot.scala:59:28]
wire next_uop_frs3_en; // @[issue-slot.scala:59:28]
wire next_uop_fcn_dw; // @[issue-slot.scala:59:28]
wire [4:0] next_uop_fcn_op; // @[issue-slot.scala:59:28]
wire next_uop_fp_val; // @[issue-slot.scala:59:28]
wire [2:0] next_uop_fp_rm; // @[issue-slot.scala:59:28]
wire [1:0] next_uop_fp_typ; // @[issue-slot.scala:59:28]
wire next_uop_xcpt_pf_if; // @[issue-slot.scala:59:28]
wire next_uop_xcpt_ae_if; // @[issue-slot.scala:59:28]
wire next_uop_xcpt_ma_if; // @[issue-slot.scala:59:28]
wire next_uop_bp_debug_if; // @[issue-slot.scala:59:28]
wire next_uop_bp_xcpt_if; // @[issue-slot.scala:59:28]
wire [2:0] next_uop_debug_fsrc; // @[issue-slot.scala:59:28]
wire [2:0] next_uop_debug_tsrc; // @[issue-slot.scala:59:28]
wire io_iss_uop_iq_type_0_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_iq_type_1_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_iq_type_2_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_iq_type_3_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fu_code_0_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fu_code_1_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fu_code_2_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fu_code_3_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fu_code_4_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fu_code_5_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fu_code_6_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fu_code_7_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fu_code_8_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fu_code_9_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_ldst_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_wen_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_ren1_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_ren2_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_ren3_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_swap12_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_swap23_0; // @[issue-slot.scala:49:7]
wire [1:0] io_iss_uop_fp_ctrl_typeTagIn_0; // @[issue-slot.scala:49:7]
wire [1:0] io_iss_uop_fp_ctrl_typeTagOut_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_fromint_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_toint_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_fastpipe_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_fma_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_div_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_sqrt_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_wflags_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_vec_0; // @[issue-slot.scala:49:7]
wire [31:0] io_iss_uop_inst_0; // @[issue-slot.scala:49:7]
wire [31:0] io_iss_uop_debug_inst_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_is_rvc_0; // @[issue-slot.scala:49:7]
wire [39:0] io_iss_uop_debug_pc_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_iw_issued_0; // @[issue-slot.scala:49:7]
wire [1:0] io_iss_uop_iw_p1_speculative_child_0; // @[issue-slot.scala:49:7]
wire [1:0] io_iss_uop_iw_p2_speculative_child_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_iw_p1_bypass_hint_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_iw_p2_bypass_hint_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_iw_p3_bypass_hint_0; // @[issue-slot.scala:49:7]
wire [1:0] io_iss_uop_dis_col_sel_0; // @[issue-slot.scala:49:7]
wire [11:0] io_iss_uop_br_mask_0; // @[issue-slot.scala:49:7]
wire [3:0] io_iss_uop_br_tag_0; // @[issue-slot.scala:49:7]
wire [3:0] io_iss_uop_br_type_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_is_sfb_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_is_fence_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_is_fencei_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_is_sfence_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_is_amo_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_is_eret_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_is_sys_pc2epc_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_is_rocc_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_is_mov_0; // @[issue-slot.scala:49:7]
wire [4:0] io_iss_uop_ftq_idx_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_edge_inst_0; // @[issue-slot.scala:49:7]
wire [5:0] io_iss_uop_pc_lob_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_taken_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_imm_rename_0; // @[issue-slot.scala:49:7]
wire [2:0] io_iss_uop_imm_sel_0; // @[issue-slot.scala:49:7]
wire [4:0] io_iss_uop_pimm_0; // @[issue-slot.scala:49:7]
wire [19:0] io_iss_uop_imm_packed_0; // @[issue-slot.scala:49:7]
wire [1:0] io_iss_uop_op1_sel_0; // @[issue-slot.scala:49:7]
wire [2:0] io_iss_uop_op2_sel_0; // @[issue-slot.scala:49:7]
wire [5:0] io_iss_uop_rob_idx_0; // @[issue-slot.scala:49:7]
wire [3:0] io_iss_uop_ldq_idx_0; // @[issue-slot.scala:49:7]
wire [3:0] io_iss_uop_stq_idx_0; // @[issue-slot.scala:49:7]
wire [1:0] io_iss_uop_rxq_idx_0; // @[issue-slot.scala:49:7]
wire [6:0] io_iss_uop_pdst_0; // @[issue-slot.scala:49:7]
wire [6:0] io_iss_uop_prs1_0; // @[issue-slot.scala:49:7]
wire [6:0] io_iss_uop_prs2_0; // @[issue-slot.scala:49:7]
wire [6:0] io_iss_uop_prs3_0; // @[issue-slot.scala:49:7]
wire [4:0] io_iss_uop_ppred_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_prs1_busy_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_prs2_busy_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_prs3_busy_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_ppred_busy_0; // @[issue-slot.scala:49:7]
wire [6:0] io_iss_uop_stale_pdst_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_exception_0; // @[issue-slot.scala:49:7]
wire [63:0] io_iss_uop_exc_cause_0; // @[issue-slot.scala:49:7]
wire [4:0] io_iss_uop_mem_cmd_0; // @[issue-slot.scala:49:7]
wire [1:0] io_iss_uop_mem_size_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_mem_signed_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_uses_ldq_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_uses_stq_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_is_unique_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_flush_on_commit_0; // @[issue-slot.scala:49:7]
wire [2:0] io_iss_uop_csr_cmd_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_ldst_is_rs1_0; // @[issue-slot.scala:49:7]
wire [5:0] io_iss_uop_ldst_0; // @[issue-slot.scala:49:7]
wire [5:0] io_iss_uop_lrs1_0; // @[issue-slot.scala:49:7]
wire [5:0] io_iss_uop_lrs2_0; // @[issue-slot.scala:49:7]
wire [5:0] io_iss_uop_lrs3_0; // @[issue-slot.scala:49:7]
wire [1:0] io_iss_uop_dst_rtype_0; // @[issue-slot.scala:49:7]
wire [1:0] io_iss_uop_lrs1_rtype_0; // @[issue-slot.scala:49:7]
wire [1:0] io_iss_uop_lrs2_rtype_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_frs3_en_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fcn_dw_0; // @[issue-slot.scala:49:7]
wire [4:0] io_iss_uop_fcn_op_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_val_0; // @[issue-slot.scala:49:7]
wire [2:0] io_iss_uop_fp_rm_0; // @[issue-slot.scala:49:7]
wire [1:0] io_iss_uop_fp_typ_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_xcpt_pf_if_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_xcpt_ae_if_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_xcpt_ma_if_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_bp_debug_if_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_bp_xcpt_if_0; // @[issue-slot.scala:49:7]
wire [2:0] io_iss_uop_debug_fsrc_0; // @[issue-slot.scala:49:7]
wire [2:0] io_iss_uop_debug_tsrc_0; // @[issue-slot.scala:49:7]
wire io_out_uop_iq_type_0_0; // @[issue-slot.scala:49:7]
wire io_out_uop_iq_type_1_0; // @[issue-slot.scala:49:7]
wire io_out_uop_iq_type_2_0; // @[issue-slot.scala:49:7]
wire io_out_uop_iq_type_3_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fu_code_0_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fu_code_1_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fu_code_2_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fu_code_3_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fu_code_4_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fu_code_5_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fu_code_6_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fu_code_7_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fu_code_8_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fu_code_9_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_ldst_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_wen_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_ren1_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_ren2_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_ren3_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_swap12_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_swap23_0; // @[issue-slot.scala:49:7]
wire [1:0] io_out_uop_fp_ctrl_typeTagIn_0; // @[issue-slot.scala:49:7]
wire [1:0] io_out_uop_fp_ctrl_typeTagOut_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_fromint_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_toint_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_fastpipe_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_fma_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_div_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_sqrt_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_wflags_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_vec_0; // @[issue-slot.scala:49:7]
wire [31:0] io_out_uop_inst_0; // @[issue-slot.scala:49:7]
wire [31:0] io_out_uop_debug_inst_0; // @[issue-slot.scala:49:7]
wire io_out_uop_is_rvc_0; // @[issue-slot.scala:49:7]
wire [39:0] io_out_uop_debug_pc_0; // @[issue-slot.scala:49:7]
wire io_out_uop_iw_issued_0; // @[issue-slot.scala:49:7]
wire [1:0] io_out_uop_iw_p1_speculative_child_0; // @[issue-slot.scala:49:7]
wire [1:0] io_out_uop_iw_p2_speculative_child_0; // @[issue-slot.scala:49:7]
wire io_out_uop_iw_p1_bypass_hint_0; // @[issue-slot.scala:49:7]
wire io_out_uop_iw_p2_bypass_hint_0; // @[issue-slot.scala:49:7]
wire io_out_uop_iw_p3_bypass_hint_0; // @[issue-slot.scala:49:7]
wire [1:0] io_out_uop_dis_col_sel_0; // @[issue-slot.scala:49:7]
wire [11:0] io_out_uop_br_mask_0; // @[issue-slot.scala:49:7]
wire [3:0] io_out_uop_br_tag_0; // @[issue-slot.scala:49:7]
wire [3:0] io_out_uop_br_type_0; // @[issue-slot.scala:49:7]
wire io_out_uop_is_sfb_0; // @[issue-slot.scala:49:7]
wire io_out_uop_is_fence_0; // @[issue-slot.scala:49:7]
wire io_out_uop_is_fencei_0; // @[issue-slot.scala:49:7]
wire io_out_uop_is_sfence_0; // @[issue-slot.scala:49:7]
wire io_out_uop_is_amo_0; // @[issue-slot.scala:49:7]
wire io_out_uop_is_eret_0; // @[issue-slot.scala:49:7]
wire io_out_uop_is_sys_pc2epc_0; // @[issue-slot.scala:49:7]
wire io_out_uop_is_rocc_0; // @[issue-slot.scala:49:7]
wire io_out_uop_is_mov_0; // @[issue-slot.scala:49:7]
wire [4:0] io_out_uop_ftq_idx_0; // @[issue-slot.scala:49:7]
wire io_out_uop_edge_inst_0; // @[issue-slot.scala:49:7]
wire [5:0] io_out_uop_pc_lob_0; // @[issue-slot.scala:49:7]
wire io_out_uop_taken_0; // @[issue-slot.scala:49:7]
wire io_out_uop_imm_rename_0; // @[issue-slot.scala:49:7]
wire [2:0] io_out_uop_imm_sel_0; // @[issue-slot.scala:49:7]
wire [4:0] io_out_uop_pimm_0; // @[issue-slot.scala:49:7]
wire [19:0] io_out_uop_imm_packed_0; // @[issue-slot.scala:49:7]
wire [1:0] io_out_uop_op1_sel_0; // @[issue-slot.scala:49:7]
wire [2:0] io_out_uop_op2_sel_0; // @[issue-slot.scala:49:7]
wire [5:0] io_out_uop_rob_idx_0; // @[issue-slot.scala:49:7]
wire [3:0] io_out_uop_ldq_idx_0; // @[issue-slot.scala:49:7]
wire [3:0] io_out_uop_stq_idx_0; // @[issue-slot.scala:49:7]
wire [1:0] io_out_uop_rxq_idx_0; // @[issue-slot.scala:49:7]
wire [6:0] io_out_uop_pdst_0; // @[issue-slot.scala:49:7]
wire [6:0] io_out_uop_prs1_0; // @[issue-slot.scala:49:7]
wire [6:0] io_out_uop_prs2_0; // @[issue-slot.scala:49:7]
wire [6:0] io_out_uop_prs3_0; // @[issue-slot.scala:49:7]
wire [4:0] io_out_uop_ppred_0; // @[issue-slot.scala:49:7]
wire io_out_uop_prs1_busy_0; // @[issue-slot.scala:49:7]
wire io_out_uop_prs2_busy_0; // @[issue-slot.scala:49:7]
wire io_out_uop_prs3_busy_0; // @[issue-slot.scala:49:7]
wire io_out_uop_ppred_busy_0; // @[issue-slot.scala:49:7]
wire [6:0] io_out_uop_stale_pdst_0; // @[issue-slot.scala:49:7]
wire io_out_uop_exception_0; // @[issue-slot.scala:49:7]
wire [63:0] io_out_uop_exc_cause_0; // @[issue-slot.scala:49:7]
wire [4:0] io_out_uop_mem_cmd_0; // @[issue-slot.scala:49:7]
wire [1:0] io_out_uop_mem_size_0; // @[issue-slot.scala:49:7]
wire io_out_uop_mem_signed_0; // @[issue-slot.scala:49:7]
wire io_out_uop_uses_ldq_0; // @[issue-slot.scala:49:7]
wire io_out_uop_uses_stq_0; // @[issue-slot.scala:49:7]
wire io_out_uop_is_unique_0; // @[issue-slot.scala:49:7]
wire io_out_uop_flush_on_commit_0; // @[issue-slot.scala:49:7]
wire [2:0] io_out_uop_csr_cmd_0; // @[issue-slot.scala:49:7]
wire io_out_uop_ldst_is_rs1_0; // @[issue-slot.scala:49:7]
wire [5:0] io_out_uop_ldst_0; // @[issue-slot.scala:49:7]
wire [5:0] io_out_uop_lrs1_0; // @[issue-slot.scala:49:7]
wire [5:0] io_out_uop_lrs2_0; // @[issue-slot.scala:49:7]
wire [5:0] io_out_uop_lrs3_0; // @[issue-slot.scala:49:7]
wire [1:0] io_out_uop_dst_rtype_0; // @[issue-slot.scala:49:7]
wire [1:0] io_out_uop_lrs1_rtype_0; // @[issue-slot.scala:49:7]
wire [1:0] io_out_uop_lrs2_rtype_0; // @[issue-slot.scala:49:7]
wire io_out_uop_frs3_en_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fcn_dw_0; // @[issue-slot.scala:49:7]
wire [4:0] io_out_uop_fcn_op_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_val_0; // @[issue-slot.scala:49:7]
wire [2:0] io_out_uop_fp_rm_0; // @[issue-slot.scala:49:7]
wire [1:0] io_out_uop_fp_typ_0; // @[issue-slot.scala:49:7]
wire io_out_uop_xcpt_pf_if_0; // @[issue-slot.scala:49:7]
wire io_out_uop_xcpt_ae_if_0; // @[issue-slot.scala:49:7]
wire io_out_uop_xcpt_ma_if_0; // @[issue-slot.scala:49:7]
wire io_out_uop_bp_debug_if_0; // @[issue-slot.scala:49:7]
wire io_out_uop_bp_xcpt_if_0; // @[issue-slot.scala:49:7]
wire [2:0] io_out_uop_debug_fsrc_0; // @[issue-slot.scala:49:7]
wire [2:0] io_out_uop_debug_tsrc_0; // @[issue-slot.scala:49:7]
wire io_valid_0; // @[issue-slot.scala:49:7]
wire io_will_be_valid_0; // @[issue-slot.scala:49:7]
wire io_request_0; // @[issue-slot.scala:49:7]
reg slot_valid; // @[issue-slot.scala:55:27]
assign io_valid_0 = slot_valid; // @[issue-slot.scala:49:7, :55:27]
reg [31:0] slot_uop_inst; // @[issue-slot.scala:56:21]
assign io_iss_uop_inst_0 = slot_uop_inst; // @[issue-slot.scala:49:7, :56:21]
wire [31:0] next_uop_out_inst = slot_uop_inst; // @[util.scala:104:23]
reg [31:0] slot_uop_debug_inst; // @[issue-slot.scala:56:21]
assign io_iss_uop_debug_inst_0 = slot_uop_debug_inst; // @[issue-slot.scala:49:7, :56:21]
wire [31:0] next_uop_out_debug_inst = slot_uop_debug_inst; // @[util.scala:104:23]
reg slot_uop_is_rvc; // @[issue-slot.scala:56:21]
assign io_iss_uop_is_rvc_0 = slot_uop_is_rvc; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_is_rvc = slot_uop_is_rvc; // @[util.scala:104:23]
reg [39:0] slot_uop_debug_pc; // @[issue-slot.scala:56:21]
assign io_iss_uop_debug_pc_0 = slot_uop_debug_pc; // @[issue-slot.scala:49:7, :56:21]
wire [39:0] next_uop_out_debug_pc = slot_uop_debug_pc; // @[util.scala:104:23]
reg slot_uop_iq_type_0; // @[issue-slot.scala:56:21]
assign io_iss_uop_iq_type_0_0 = slot_uop_iq_type_0; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_iq_type_0 = slot_uop_iq_type_0; // @[util.scala:104:23]
reg slot_uop_iq_type_1; // @[issue-slot.scala:56:21]
assign io_iss_uop_iq_type_1_0 = slot_uop_iq_type_1; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_iq_type_1 = slot_uop_iq_type_1; // @[util.scala:104:23]
reg slot_uop_iq_type_2; // @[issue-slot.scala:56:21]
assign io_iss_uop_iq_type_2_0 = slot_uop_iq_type_2; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_iq_type_2 = slot_uop_iq_type_2; // @[util.scala:104:23]
reg slot_uop_iq_type_3; // @[issue-slot.scala:56:21]
assign io_iss_uop_iq_type_3_0 = slot_uop_iq_type_3; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_iq_type_3 = slot_uop_iq_type_3; // @[util.scala:104:23]
reg slot_uop_fu_code_0; // @[issue-slot.scala:56:21]
assign io_iss_uop_fu_code_0_0 = slot_uop_fu_code_0; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fu_code_0 = slot_uop_fu_code_0; // @[util.scala:104:23]
reg slot_uop_fu_code_1; // @[issue-slot.scala:56:21]
assign io_iss_uop_fu_code_1_0 = slot_uop_fu_code_1; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fu_code_1 = slot_uop_fu_code_1; // @[util.scala:104:23]
reg slot_uop_fu_code_2; // @[issue-slot.scala:56:21]
assign io_iss_uop_fu_code_2_0 = slot_uop_fu_code_2; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fu_code_2 = slot_uop_fu_code_2; // @[util.scala:104:23]
reg slot_uop_fu_code_3; // @[issue-slot.scala:56:21]
assign io_iss_uop_fu_code_3_0 = slot_uop_fu_code_3; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fu_code_3 = slot_uop_fu_code_3; // @[util.scala:104:23]
reg slot_uop_fu_code_4; // @[issue-slot.scala:56:21]
assign io_iss_uop_fu_code_4_0 = slot_uop_fu_code_4; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fu_code_4 = slot_uop_fu_code_4; // @[util.scala:104:23]
reg slot_uop_fu_code_5; // @[issue-slot.scala:56:21]
assign io_iss_uop_fu_code_5_0 = slot_uop_fu_code_5; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fu_code_5 = slot_uop_fu_code_5; // @[util.scala:104:23]
reg slot_uop_fu_code_6; // @[issue-slot.scala:56:21]
assign io_iss_uop_fu_code_6_0 = slot_uop_fu_code_6; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fu_code_6 = slot_uop_fu_code_6; // @[util.scala:104:23]
reg slot_uop_fu_code_7; // @[issue-slot.scala:56:21]
assign io_iss_uop_fu_code_7_0 = slot_uop_fu_code_7; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fu_code_7 = slot_uop_fu_code_7; // @[util.scala:104:23]
reg slot_uop_fu_code_8; // @[issue-slot.scala:56:21]
assign io_iss_uop_fu_code_8_0 = slot_uop_fu_code_8; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fu_code_8 = slot_uop_fu_code_8; // @[util.scala:104:23]
reg slot_uop_fu_code_9; // @[issue-slot.scala:56:21]
assign io_iss_uop_fu_code_9_0 = slot_uop_fu_code_9; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fu_code_9 = slot_uop_fu_code_9; // @[util.scala:104:23]
reg slot_uop_iw_issued; // @[issue-slot.scala:56:21]
assign io_iss_uop_iw_issued_0 = slot_uop_iw_issued; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_iw_issued = slot_uop_iw_issued; // @[util.scala:104:23]
reg [1:0] slot_uop_iw_p1_speculative_child; // @[issue-slot.scala:56:21]
assign io_iss_uop_iw_p1_speculative_child_0 = slot_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7, :56:21]
wire [1:0] next_uop_out_iw_p1_speculative_child = slot_uop_iw_p1_speculative_child; // @[util.scala:104:23]
reg [1:0] slot_uop_iw_p2_speculative_child; // @[issue-slot.scala:56:21]
assign io_iss_uop_iw_p2_speculative_child_0 = slot_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7, :56:21]
wire [1:0] next_uop_out_iw_p2_speculative_child = slot_uop_iw_p2_speculative_child; // @[util.scala:104:23]
reg slot_uop_iw_p1_bypass_hint; // @[issue-slot.scala:56:21]
assign io_iss_uop_iw_p1_bypass_hint_0 = slot_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_iw_p1_bypass_hint = slot_uop_iw_p1_bypass_hint; // @[util.scala:104:23]
reg slot_uop_iw_p2_bypass_hint; // @[issue-slot.scala:56:21]
assign io_iss_uop_iw_p2_bypass_hint_0 = slot_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_iw_p2_bypass_hint = slot_uop_iw_p2_bypass_hint; // @[util.scala:104:23]
reg slot_uop_iw_p3_bypass_hint; // @[issue-slot.scala:56:21]
assign io_iss_uop_iw_p3_bypass_hint_0 = slot_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_iw_p3_bypass_hint = slot_uop_iw_p3_bypass_hint; // @[util.scala:104:23]
reg [1:0] slot_uop_dis_col_sel; // @[issue-slot.scala:56:21]
assign io_iss_uop_dis_col_sel_0 = slot_uop_dis_col_sel; // @[issue-slot.scala:49:7, :56:21]
wire [1:0] next_uop_out_dis_col_sel = slot_uop_dis_col_sel; // @[util.scala:104:23]
reg [11:0] slot_uop_br_mask; // @[issue-slot.scala:56:21]
assign io_iss_uop_br_mask_0 = slot_uop_br_mask; // @[issue-slot.scala:49:7, :56:21]
reg [3:0] slot_uop_br_tag; // @[issue-slot.scala:56:21]
assign io_iss_uop_br_tag_0 = slot_uop_br_tag; // @[issue-slot.scala:49:7, :56:21]
wire [3:0] next_uop_out_br_tag = slot_uop_br_tag; // @[util.scala:104:23]
reg [3:0] slot_uop_br_type; // @[issue-slot.scala:56:21]
assign io_iss_uop_br_type_0 = slot_uop_br_type; // @[issue-slot.scala:49:7, :56:21]
wire [3:0] next_uop_out_br_type = slot_uop_br_type; // @[util.scala:104:23]
reg slot_uop_is_sfb; // @[issue-slot.scala:56:21]
assign io_iss_uop_is_sfb_0 = slot_uop_is_sfb; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_is_sfb = slot_uop_is_sfb; // @[util.scala:104:23]
reg slot_uop_is_fence; // @[issue-slot.scala:56:21]
assign io_iss_uop_is_fence_0 = slot_uop_is_fence; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_is_fence = slot_uop_is_fence; // @[util.scala:104:23]
reg slot_uop_is_fencei; // @[issue-slot.scala:56:21]
assign io_iss_uop_is_fencei_0 = slot_uop_is_fencei; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_is_fencei = slot_uop_is_fencei; // @[util.scala:104:23]
reg slot_uop_is_sfence; // @[issue-slot.scala:56:21]
assign io_iss_uop_is_sfence_0 = slot_uop_is_sfence; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_is_sfence = slot_uop_is_sfence; // @[util.scala:104:23]
reg slot_uop_is_amo; // @[issue-slot.scala:56:21]
assign io_iss_uop_is_amo_0 = slot_uop_is_amo; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_is_amo = slot_uop_is_amo; // @[util.scala:104:23]
reg slot_uop_is_eret; // @[issue-slot.scala:56:21]
assign io_iss_uop_is_eret_0 = slot_uop_is_eret; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_is_eret = slot_uop_is_eret; // @[util.scala:104:23]
reg slot_uop_is_sys_pc2epc; // @[issue-slot.scala:56:21]
assign io_iss_uop_is_sys_pc2epc_0 = slot_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_is_sys_pc2epc = slot_uop_is_sys_pc2epc; // @[util.scala:104:23]
reg slot_uop_is_rocc; // @[issue-slot.scala:56:21]
assign io_iss_uop_is_rocc_0 = slot_uop_is_rocc; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_is_rocc = slot_uop_is_rocc; // @[util.scala:104:23]
reg slot_uop_is_mov; // @[issue-slot.scala:56:21]
assign io_iss_uop_is_mov_0 = slot_uop_is_mov; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_is_mov = slot_uop_is_mov; // @[util.scala:104:23]
reg [4:0] slot_uop_ftq_idx; // @[issue-slot.scala:56:21]
assign io_iss_uop_ftq_idx_0 = slot_uop_ftq_idx; // @[issue-slot.scala:49:7, :56:21]
wire [4:0] next_uop_out_ftq_idx = slot_uop_ftq_idx; // @[util.scala:104:23]
reg slot_uop_edge_inst; // @[issue-slot.scala:56:21]
assign io_iss_uop_edge_inst_0 = slot_uop_edge_inst; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_edge_inst = slot_uop_edge_inst; // @[util.scala:104:23]
reg [5:0] slot_uop_pc_lob; // @[issue-slot.scala:56:21]
assign io_iss_uop_pc_lob_0 = slot_uop_pc_lob; // @[issue-slot.scala:49:7, :56:21]
wire [5:0] next_uop_out_pc_lob = slot_uop_pc_lob; // @[util.scala:104:23]
reg slot_uop_taken; // @[issue-slot.scala:56:21]
assign io_iss_uop_taken_0 = slot_uop_taken; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_taken = slot_uop_taken; // @[util.scala:104:23]
reg slot_uop_imm_rename; // @[issue-slot.scala:56:21]
assign io_iss_uop_imm_rename_0 = slot_uop_imm_rename; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_imm_rename = slot_uop_imm_rename; // @[util.scala:104:23]
reg [2:0] slot_uop_imm_sel; // @[issue-slot.scala:56:21]
assign io_iss_uop_imm_sel_0 = slot_uop_imm_sel; // @[issue-slot.scala:49:7, :56:21]
wire [2:0] next_uop_out_imm_sel = slot_uop_imm_sel; // @[util.scala:104:23]
reg [4:0] slot_uop_pimm; // @[issue-slot.scala:56:21]
assign io_iss_uop_pimm_0 = slot_uop_pimm; // @[issue-slot.scala:49:7, :56:21]
wire [4:0] next_uop_out_pimm = slot_uop_pimm; // @[util.scala:104:23]
reg [19:0] slot_uop_imm_packed; // @[issue-slot.scala:56:21]
assign io_iss_uop_imm_packed_0 = slot_uop_imm_packed; // @[issue-slot.scala:49:7, :56:21]
wire [19:0] next_uop_out_imm_packed = slot_uop_imm_packed; // @[util.scala:104:23]
reg [1:0] slot_uop_op1_sel; // @[issue-slot.scala:56:21]
assign io_iss_uop_op1_sel_0 = slot_uop_op1_sel; // @[issue-slot.scala:49:7, :56:21]
wire [1:0] next_uop_out_op1_sel = slot_uop_op1_sel; // @[util.scala:104:23]
reg [2:0] slot_uop_op2_sel; // @[issue-slot.scala:56:21]
assign io_iss_uop_op2_sel_0 = slot_uop_op2_sel; // @[issue-slot.scala:49:7, :56:21]
wire [2:0] next_uop_out_op2_sel = slot_uop_op2_sel; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_ldst; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_ldst_0 = slot_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_ldst = slot_uop_fp_ctrl_ldst; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_wen; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_wen_0 = slot_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_wen = slot_uop_fp_ctrl_wen; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_ren1; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_ren1_0 = slot_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_ren1 = slot_uop_fp_ctrl_ren1; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_ren2; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_ren2_0 = slot_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_ren2 = slot_uop_fp_ctrl_ren2; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_ren3; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_ren3_0 = slot_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_ren3 = slot_uop_fp_ctrl_ren3; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_swap12; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_swap12_0 = slot_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_swap12 = slot_uop_fp_ctrl_swap12; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_swap23; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_swap23_0 = slot_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_swap23 = slot_uop_fp_ctrl_swap23; // @[util.scala:104:23]
reg [1:0] slot_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_typeTagIn_0 = slot_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7, :56:21]
wire [1:0] next_uop_out_fp_ctrl_typeTagIn = slot_uop_fp_ctrl_typeTagIn; // @[util.scala:104:23]
reg [1:0] slot_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_typeTagOut_0 = slot_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7, :56:21]
wire [1:0] next_uop_out_fp_ctrl_typeTagOut = slot_uop_fp_ctrl_typeTagOut; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_fromint; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_fromint_0 = slot_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_fromint = slot_uop_fp_ctrl_fromint; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_toint; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_toint_0 = slot_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_toint = slot_uop_fp_ctrl_toint; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_fastpipe_0 = slot_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_fastpipe = slot_uop_fp_ctrl_fastpipe; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_fma; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_fma_0 = slot_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_fma = slot_uop_fp_ctrl_fma; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_div; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_div_0 = slot_uop_fp_ctrl_div; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_div = slot_uop_fp_ctrl_div; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_sqrt; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_sqrt_0 = slot_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_sqrt = slot_uop_fp_ctrl_sqrt; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_wflags; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_wflags_0 = slot_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_wflags = slot_uop_fp_ctrl_wflags; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_vec; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_vec_0 = slot_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_vec = slot_uop_fp_ctrl_vec; // @[util.scala:104:23]
reg [5:0] slot_uop_rob_idx; // @[issue-slot.scala:56:21]
assign io_iss_uop_rob_idx_0 = slot_uop_rob_idx; // @[issue-slot.scala:49:7, :56:21]
wire [5:0] next_uop_out_rob_idx = slot_uop_rob_idx; // @[util.scala:104:23]
reg [3:0] slot_uop_ldq_idx; // @[issue-slot.scala:56:21]
assign io_iss_uop_ldq_idx_0 = slot_uop_ldq_idx; // @[issue-slot.scala:49:7, :56:21]
wire [3:0] next_uop_out_ldq_idx = slot_uop_ldq_idx; // @[util.scala:104:23]
reg [3:0] slot_uop_stq_idx; // @[issue-slot.scala:56:21]
assign io_iss_uop_stq_idx_0 = slot_uop_stq_idx; // @[issue-slot.scala:49:7, :56:21]
wire [3:0] next_uop_out_stq_idx = slot_uop_stq_idx; // @[util.scala:104:23]
reg [1:0] slot_uop_rxq_idx; // @[issue-slot.scala:56:21]
assign io_iss_uop_rxq_idx_0 = slot_uop_rxq_idx; // @[issue-slot.scala:49:7, :56:21]
wire [1:0] next_uop_out_rxq_idx = slot_uop_rxq_idx; // @[util.scala:104:23]
reg [6:0] slot_uop_pdst; // @[issue-slot.scala:56:21]
assign io_iss_uop_pdst_0 = slot_uop_pdst; // @[issue-slot.scala:49:7, :56:21]
wire [6:0] next_uop_out_pdst = slot_uop_pdst; // @[util.scala:104:23]
reg [6:0] slot_uop_prs1; // @[issue-slot.scala:56:21]
assign io_iss_uop_prs1_0 = slot_uop_prs1; // @[issue-slot.scala:49:7, :56:21]
wire [6:0] next_uop_out_prs1 = slot_uop_prs1; // @[util.scala:104:23]
reg [6:0] slot_uop_prs2; // @[issue-slot.scala:56:21]
assign io_iss_uop_prs2_0 = slot_uop_prs2; // @[issue-slot.scala:49:7, :56:21]
wire [6:0] next_uop_out_prs2 = slot_uop_prs2; // @[util.scala:104:23]
reg [6:0] slot_uop_prs3; // @[issue-slot.scala:56:21]
assign io_iss_uop_prs3_0 = slot_uop_prs3; // @[issue-slot.scala:49:7, :56:21]
wire [6:0] next_uop_out_prs3 = slot_uop_prs3; // @[util.scala:104:23]
reg [4:0] slot_uop_ppred; // @[issue-slot.scala:56:21]
assign io_iss_uop_ppred_0 = slot_uop_ppred; // @[issue-slot.scala:49:7, :56:21]
wire [4:0] next_uop_out_ppred = slot_uop_ppred; // @[util.scala:104:23]
reg slot_uop_prs1_busy; // @[issue-slot.scala:56:21]
assign io_iss_uop_prs1_busy_0 = slot_uop_prs1_busy; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_prs1_busy = slot_uop_prs1_busy; // @[util.scala:104:23]
reg slot_uop_prs2_busy; // @[issue-slot.scala:56:21]
assign io_iss_uop_prs2_busy_0 = slot_uop_prs2_busy; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_prs2_busy = slot_uop_prs2_busy; // @[util.scala:104:23]
reg slot_uop_prs3_busy; // @[issue-slot.scala:56:21]
assign io_iss_uop_prs3_busy_0 = slot_uop_prs3_busy; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_prs3_busy = slot_uop_prs3_busy; // @[util.scala:104:23]
reg slot_uop_ppred_busy; // @[issue-slot.scala:56:21]
assign io_iss_uop_ppred_busy_0 = slot_uop_ppred_busy; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_ppred_busy = slot_uop_ppred_busy; // @[util.scala:104:23]
wire _iss_ready_T_3 = slot_uop_ppred_busy; // @[issue-slot.scala:56:21, :136:88]
wire _agen_ready_T_2 = slot_uop_ppred_busy; // @[issue-slot.scala:56:21, :137:95]
wire _dgen_ready_T_2 = slot_uop_ppred_busy; // @[issue-slot.scala:56:21, :138:95]
reg [6:0] slot_uop_stale_pdst; // @[issue-slot.scala:56:21]
assign io_iss_uop_stale_pdst_0 = slot_uop_stale_pdst; // @[issue-slot.scala:49:7, :56:21]
wire [6:0] next_uop_out_stale_pdst = slot_uop_stale_pdst; // @[util.scala:104:23]
reg slot_uop_exception; // @[issue-slot.scala:56:21]
assign io_iss_uop_exception_0 = slot_uop_exception; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_exception = slot_uop_exception; // @[util.scala:104:23]
reg [63:0] slot_uop_exc_cause; // @[issue-slot.scala:56:21]
assign io_iss_uop_exc_cause_0 = slot_uop_exc_cause; // @[issue-slot.scala:49:7, :56:21]
wire [63:0] next_uop_out_exc_cause = slot_uop_exc_cause; // @[util.scala:104:23]
reg [4:0] slot_uop_mem_cmd; // @[issue-slot.scala:56:21]
assign io_iss_uop_mem_cmd_0 = slot_uop_mem_cmd; // @[issue-slot.scala:49:7, :56:21]
wire [4:0] next_uop_out_mem_cmd = slot_uop_mem_cmd; // @[util.scala:104:23]
reg [1:0] slot_uop_mem_size; // @[issue-slot.scala:56:21]
assign io_iss_uop_mem_size_0 = slot_uop_mem_size; // @[issue-slot.scala:49:7, :56:21]
wire [1:0] next_uop_out_mem_size = slot_uop_mem_size; // @[util.scala:104:23]
reg slot_uop_mem_signed; // @[issue-slot.scala:56:21]
assign io_iss_uop_mem_signed_0 = slot_uop_mem_signed; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_mem_signed = slot_uop_mem_signed; // @[util.scala:104:23]
reg slot_uop_uses_ldq; // @[issue-slot.scala:56:21]
assign io_iss_uop_uses_ldq_0 = slot_uop_uses_ldq; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_uses_ldq = slot_uop_uses_ldq; // @[util.scala:104:23]
reg slot_uop_uses_stq; // @[issue-slot.scala:56:21]
assign io_iss_uop_uses_stq_0 = slot_uop_uses_stq; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_uses_stq = slot_uop_uses_stq; // @[util.scala:104:23]
reg slot_uop_is_unique; // @[issue-slot.scala:56:21]
assign io_iss_uop_is_unique_0 = slot_uop_is_unique; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_is_unique = slot_uop_is_unique; // @[util.scala:104:23]
reg slot_uop_flush_on_commit; // @[issue-slot.scala:56:21]
assign io_iss_uop_flush_on_commit_0 = slot_uop_flush_on_commit; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_flush_on_commit = slot_uop_flush_on_commit; // @[util.scala:104:23]
reg [2:0] slot_uop_csr_cmd; // @[issue-slot.scala:56:21]
assign io_iss_uop_csr_cmd_0 = slot_uop_csr_cmd; // @[issue-slot.scala:49:7, :56:21]
wire [2:0] next_uop_out_csr_cmd = slot_uop_csr_cmd; // @[util.scala:104:23]
reg slot_uop_ldst_is_rs1; // @[issue-slot.scala:56:21]
assign io_iss_uop_ldst_is_rs1_0 = slot_uop_ldst_is_rs1; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_ldst_is_rs1 = slot_uop_ldst_is_rs1; // @[util.scala:104:23]
reg [5:0] slot_uop_ldst; // @[issue-slot.scala:56:21]
assign io_iss_uop_ldst_0 = slot_uop_ldst; // @[issue-slot.scala:49:7, :56:21]
wire [5:0] next_uop_out_ldst = slot_uop_ldst; // @[util.scala:104:23]
reg [5:0] slot_uop_lrs1; // @[issue-slot.scala:56:21]
assign io_iss_uop_lrs1_0 = slot_uop_lrs1; // @[issue-slot.scala:49:7, :56:21]
wire [5:0] next_uop_out_lrs1 = slot_uop_lrs1; // @[util.scala:104:23]
reg [5:0] slot_uop_lrs2; // @[issue-slot.scala:56:21]
assign io_iss_uop_lrs2_0 = slot_uop_lrs2; // @[issue-slot.scala:49:7, :56:21]
wire [5:0] next_uop_out_lrs2 = slot_uop_lrs2; // @[util.scala:104:23]
reg [5:0] slot_uop_lrs3; // @[issue-slot.scala:56:21]
assign io_iss_uop_lrs3_0 = slot_uop_lrs3; // @[issue-slot.scala:49:7, :56:21]
wire [5:0] next_uop_out_lrs3 = slot_uop_lrs3; // @[util.scala:104:23]
reg [1:0] slot_uop_dst_rtype; // @[issue-slot.scala:56:21]
assign io_iss_uop_dst_rtype_0 = slot_uop_dst_rtype; // @[issue-slot.scala:49:7, :56:21]
wire [1:0] next_uop_out_dst_rtype = slot_uop_dst_rtype; // @[util.scala:104:23]
reg [1:0] slot_uop_lrs1_rtype; // @[issue-slot.scala:56:21]
assign io_iss_uop_lrs1_rtype_0 = slot_uop_lrs1_rtype; // @[issue-slot.scala:49:7, :56:21]
wire [1:0] next_uop_out_lrs1_rtype = slot_uop_lrs1_rtype; // @[util.scala:104:23]
reg [1:0] slot_uop_lrs2_rtype; // @[issue-slot.scala:56:21]
assign io_iss_uop_lrs2_rtype_0 = slot_uop_lrs2_rtype; // @[issue-slot.scala:49:7, :56:21]
wire [1:0] next_uop_out_lrs2_rtype = slot_uop_lrs2_rtype; // @[util.scala:104:23]
reg slot_uop_frs3_en; // @[issue-slot.scala:56:21]
assign io_iss_uop_frs3_en_0 = slot_uop_frs3_en; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_frs3_en = slot_uop_frs3_en; // @[util.scala:104:23]
reg slot_uop_fcn_dw; // @[issue-slot.scala:56:21]
assign io_iss_uop_fcn_dw_0 = slot_uop_fcn_dw; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fcn_dw = slot_uop_fcn_dw; // @[util.scala:104:23]
reg [4:0] slot_uop_fcn_op; // @[issue-slot.scala:56:21]
assign io_iss_uop_fcn_op_0 = slot_uop_fcn_op; // @[issue-slot.scala:49:7, :56:21]
wire [4:0] next_uop_out_fcn_op = slot_uop_fcn_op; // @[util.scala:104:23]
reg slot_uop_fp_val; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_val_0 = slot_uop_fp_val; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_val = slot_uop_fp_val; // @[util.scala:104:23]
reg [2:0] slot_uop_fp_rm; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_rm_0 = slot_uop_fp_rm; // @[issue-slot.scala:49:7, :56:21]
wire [2:0] next_uop_out_fp_rm = slot_uop_fp_rm; // @[util.scala:104:23]
reg [1:0] slot_uop_fp_typ; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_typ_0 = slot_uop_fp_typ; // @[issue-slot.scala:49:7, :56:21]
wire [1:0] next_uop_out_fp_typ = slot_uop_fp_typ; // @[util.scala:104:23]
reg slot_uop_xcpt_pf_if; // @[issue-slot.scala:56:21]
assign io_iss_uop_xcpt_pf_if_0 = slot_uop_xcpt_pf_if; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_xcpt_pf_if = slot_uop_xcpt_pf_if; // @[util.scala:104:23]
reg slot_uop_xcpt_ae_if; // @[issue-slot.scala:56:21]
assign io_iss_uop_xcpt_ae_if_0 = slot_uop_xcpt_ae_if; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_xcpt_ae_if = slot_uop_xcpt_ae_if; // @[util.scala:104:23]
reg slot_uop_xcpt_ma_if; // @[issue-slot.scala:56:21]
assign io_iss_uop_xcpt_ma_if_0 = slot_uop_xcpt_ma_if; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_xcpt_ma_if = slot_uop_xcpt_ma_if; // @[util.scala:104:23]
reg slot_uop_bp_debug_if; // @[issue-slot.scala:56:21]
assign io_iss_uop_bp_debug_if_0 = slot_uop_bp_debug_if; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_bp_debug_if = slot_uop_bp_debug_if; // @[util.scala:104:23]
reg slot_uop_bp_xcpt_if; // @[issue-slot.scala:56:21]
assign io_iss_uop_bp_xcpt_if_0 = slot_uop_bp_xcpt_if; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_bp_xcpt_if = slot_uop_bp_xcpt_if; // @[util.scala:104:23]
reg [2:0] slot_uop_debug_fsrc; // @[issue-slot.scala:56:21]
assign io_iss_uop_debug_fsrc_0 = slot_uop_debug_fsrc; // @[issue-slot.scala:49:7, :56:21]
wire [2:0] next_uop_out_debug_fsrc = slot_uop_debug_fsrc; // @[util.scala:104:23]
reg [2:0] slot_uop_debug_tsrc; // @[issue-slot.scala:56:21]
assign io_iss_uop_debug_tsrc_0 = slot_uop_debug_tsrc; // @[issue-slot.scala:49:7, :56:21]
wire [2:0] next_uop_out_debug_tsrc = slot_uop_debug_tsrc; // @[util.scala:104:23]
wire next_valid; // @[issue-slot.scala:58:28]
assign next_uop_inst = next_uop_out_inst; // @[util.scala:104:23]
assign next_uop_debug_inst = next_uop_out_debug_inst; // @[util.scala:104:23]
assign next_uop_is_rvc = next_uop_out_is_rvc; // @[util.scala:104:23]
assign next_uop_debug_pc = next_uop_out_debug_pc; // @[util.scala:104:23]
assign next_uop_iq_type_0 = next_uop_out_iq_type_0; // @[util.scala:104:23]
assign next_uop_iq_type_1 = next_uop_out_iq_type_1; // @[util.scala:104:23]
assign next_uop_iq_type_2 = next_uop_out_iq_type_2; // @[util.scala:104:23]
assign next_uop_iq_type_3 = next_uop_out_iq_type_3; // @[util.scala:104:23]
assign next_uop_fu_code_0 = next_uop_out_fu_code_0; // @[util.scala:104:23]
assign next_uop_fu_code_1 = next_uop_out_fu_code_1; // @[util.scala:104:23]
assign next_uop_fu_code_2 = next_uop_out_fu_code_2; // @[util.scala:104:23]
assign next_uop_fu_code_3 = next_uop_out_fu_code_3; // @[util.scala:104:23]
assign next_uop_fu_code_4 = next_uop_out_fu_code_4; // @[util.scala:104:23]
assign next_uop_fu_code_5 = next_uop_out_fu_code_5; // @[util.scala:104:23]
assign next_uop_fu_code_6 = next_uop_out_fu_code_6; // @[util.scala:104:23]
assign next_uop_fu_code_7 = next_uop_out_fu_code_7; // @[util.scala:104:23]
assign next_uop_fu_code_8 = next_uop_out_fu_code_8; // @[util.scala:104:23]
assign next_uop_fu_code_9 = next_uop_out_fu_code_9; // @[util.scala:104:23]
wire [11:0] _next_uop_out_br_mask_T_1; // @[util.scala:93:25]
assign next_uop_dis_col_sel = next_uop_out_dis_col_sel; // @[util.scala:104:23]
assign next_uop_br_mask = next_uop_out_br_mask; // @[util.scala:104:23]
assign next_uop_br_tag = next_uop_out_br_tag; // @[util.scala:104:23]
assign next_uop_br_type = next_uop_out_br_type; // @[util.scala:104:23]
assign next_uop_is_sfb = next_uop_out_is_sfb; // @[util.scala:104:23]
assign next_uop_is_fence = next_uop_out_is_fence; // @[util.scala:104:23]
assign next_uop_is_fencei = next_uop_out_is_fencei; // @[util.scala:104:23]
assign next_uop_is_sfence = next_uop_out_is_sfence; // @[util.scala:104:23]
assign next_uop_is_amo = next_uop_out_is_amo; // @[util.scala:104:23]
assign next_uop_is_eret = next_uop_out_is_eret; // @[util.scala:104:23]
assign next_uop_is_sys_pc2epc = next_uop_out_is_sys_pc2epc; // @[util.scala:104:23]
assign next_uop_is_rocc = next_uop_out_is_rocc; // @[util.scala:104:23]
assign next_uop_is_mov = next_uop_out_is_mov; // @[util.scala:104:23]
assign next_uop_ftq_idx = next_uop_out_ftq_idx; // @[util.scala:104:23]
assign next_uop_edge_inst = next_uop_out_edge_inst; // @[util.scala:104:23]
assign next_uop_pc_lob = next_uop_out_pc_lob; // @[util.scala:104:23]
assign next_uop_taken = next_uop_out_taken; // @[util.scala:104:23]
assign next_uop_imm_rename = next_uop_out_imm_rename; // @[util.scala:104:23]
assign next_uop_imm_sel = next_uop_out_imm_sel; // @[util.scala:104:23]
assign next_uop_pimm = next_uop_out_pimm; // @[util.scala:104:23]
assign next_uop_imm_packed = next_uop_out_imm_packed; // @[util.scala:104:23]
assign next_uop_op1_sel = next_uop_out_op1_sel; // @[util.scala:104:23]
assign next_uop_op2_sel = next_uop_out_op2_sel; // @[util.scala:104:23]
assign next_uop_fp_ctrl_ldst = next_uop_out_fp_ctrl_ldst; // @[util.scala:104:23]
assign next_uop_fp_ctrl_wen = next_uop_out_fp_ctrl_wen; // @[util.scala:104:23]
assign next_uop_fp_ctrl_ren1 = next_uop_out_fp_ctrl_ren1; // @[util.scala:104:23]
assign next_uop_fp_ctrl_ren2 = next_uop_out_fp_ctrl_ren2; // @[util.scala:104:23]
assign next_uop_fp_ctrl_ren3 = next_uop_out_fp_ctrl_ren3; // @[util.scala:104:23]
assign next_uop_fp_ctrl_swap12 = next_uop_out_fp_ctrl_swap12; // @[util.scala:104:23]
assign next_uop_fp_ctrl_swap23 = next_uop_out_fp_ctrl_swap23; // @[util.scala:104:23]
assign next_uop_fp_ctrl_typeTagIn = next_uop_out_fp_ctrl_typeTagIn; // @[util.scala:104:23]
assign next_uop_fp_ctrl_typeTagOut = next_uop_out_fp_ctrl_typeTagOut; // @[util.scala:104:23]
assign next_uop_fp_ctrl_fromint = next_uop_out_fp_ctrl_fromint; // @[util.scala:104:23]
assign next_uop_fp_ctrl_toint = next_uop_out_fp_ctrl_toint; // @[util.scala:104:23]
assign next_uop_fp_ctrl_fastpipe = next_uop_out_fp_ctrl_fastpipe; // @[util.scala:104:23]
assign next_uop_fp_ctrl_fma = next_uop_out_fp_ctrl_fma; // @[util.scala:104:23]
assign next_uop_fp_ctrl_div = next_uop_out_fp_ctrl_div; // @[util.scala:104:23]
assign next_uop_fp_ctrl_sqrt = next_uop_out_fp_ctrl_sqrt; // @[util.scala:104:23]
assign next_uop_fp_ctrl_wflags = next_uop_out_fp_ctrl_wflags; // @[util.scala:104:23]
assign next_uop_fp_ctrl_vec = next_uop_out_fp_ctrl_vec; // @[util.scala:104:23]
assign next_uop_rob_idx = next_uop_out_rob_idx; // @[util.scala:104:23]
assign next_uop_ldq_idx = next_uop_out_ldq_idx; // @[util.scala:104:23]
assign next_uop_stq_idx = next_uop_out_stq_idx; // @[util.scala:104:23]
assign next_uop_rxq_idx = next_uop_out_rxq_idx; // @[util.scala:104:23]
assign next_uop_pdst = next_uop_out_pdst; // @[util.scala:104:23]
assign next_uop_prs1 = next_uop_out_prs1; // @[util.scala:104:23]
assign next_uop_prs2 = next_uop_out_prs2; // @[util.scala:104:23]
assign next_uop_prs3 = next_uop_out_prs3; // @[util.scala:104:23]
assign next_uop_ppred = next_uop_out_ppred; // @[util.scala:104:23]
assign next_uop_ppred_busy = next_uop_out_ppred_busy; // @[util.scala:104:23]
assign next_uop_stale_pdst = next_uop_out_stale_pdst; // @[util.scala:104:23]
assign next_uop_exception = next_uop_out_exception; // @[util.scala:104:23]
assign next_uop_exc_cause = next_uop_out_exc_cause; // @[util.scala:104:23]
assign next_uop_mem_cmd = next_uop_out_mem_cmd; // @[util.scala:104:23]
assign next_uop_mem_size = next_uop_out_mem_size; // @[util.scala:104:23]
assign next_uop_mem_signed = next_uop_out_mem_signed; // @[util.scala:104:23]
assign next_uop_uses_ldq = next_uop_out_uses_ldq; // @[util.scala:104:23]
assign next_uop_uses_stq = next_uop_out_uses_stq; // @[util.scala:104:23]
assign next_uop_is_unique = next_uop_out_is_unique; // @[util.scala:104:23]
assign next_uop_flush_on_commit = next_uop_out_flush_on_commit; // @[util.scala:104:23]
assign next_uop_csr_cmd = next_uop_out_csr_cmd; // @[util.scala:104:23]
assign next_uop_ldst_is_rs1 = next_uop_out_ldst_is_rs1; // @[util.scala:104:23]
assign next_uop_ldst = next_uop_out_ldst; // @[util.scala:104:23]
assign next_uop_lrs1 = next_uop_out_lrs1; // @[util.scala:104:23]
assign next_uop_lrs2 = next_uop_out_lrs2; // @[util.scala:104:23]
assign next_uop_lrs3 = next_uop_out_lrs3; // @[util.scala:104:23]
assign next_uop_dst_rtype = next_uop_out_dst_rtype; // @[util.scala:104:23]
assign next_uop_lrs1_rtype = next_uop_out_lrs1_rtype; // @[util.scala:104:23]
assign next_uop_lrs2_rtype = next_uop_out_lrs2_rtype; // @[util.scala:104:23]
assign next_uop_frs3_en = next_uop_out_frs3_en; // @[util.scala:104:23]
assign next_uop_fcn_dw = next_uop_out_fcn_dw; // @[util.scala:104:23]
assign next_uop_fcn_op = next_uop_out_fcn_op; // @[util.scala:104:23]
assign next_uop_fp_val = next_uop_out_fp_val; // @[util.scala:104:23]
assign next_uop_fp_rm = next_uop_out_fp_rm; // @[util.scala:104:23]
assign next_uop_fp_typ = next_uop_out_fp_typ; // @[util.scala:104:23]
assign next_uop_xcpt_pf_if = next_uop_out_xcpt_pf_if; // @[util.scala:104:23]
assign next_uop_xcpt_ae_if = next_uop_out_xcpt_ae_if; // @[util.scala:104:23]
assign next_uop_xcpt_ma_if = next_uop_out_xcpt_ma_if; // @[util.scala:104:23]
assign next_uop_bp_debug_if = next_uop_out_bp_debug_if; // @[util.scala:104:23]
assign next_uop_bp_xcpt_if = next_uop_out_bp_xcpt_if; // @[util.scala:104:23]
assign next_uop_debug_fsrc = next_uop_out_debug_fsrc; // @[util.scala:104:23]
assign next_uop_debug_tsrc = next_uop_out_debug_tsrc; // @[util.scala:104:23]
wire [11:0] _next_uop_out_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:93:27]
assign _next_uop_out_br_mask_T_1 = slot_uop_br_mask & _next_uop_out_br_mask_T; // @[util.scala:93:{25,27}]
assign next_uop_out_br_mask = _next_uop_out_br_mask_T_1; // @[util.scala:93:25, :104:23]
assign io_out_uop_inst_0 = next_uop_inst; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_debug_inst_0 = next_uop_debug_inst; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_is_rvc_0 = next_uop_is_rvc; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_debug_pc_0 = next_uop_debug_pc; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_iq_type_0_0 = next_uop_iq_type_0; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_iq_type_1_0 = next_uop_iq_type_1; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_iq_type_2_0 = next_uop_iq_type_2; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_iq_type_3_0 = next_uop_iq_type_3; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fu_code_0_0 = next_uop_fu_code_0; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fu_code_1_0 = next_uop_fu_code_1; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fu_code_2_0 = next_uop_fu_code_2; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fu_code_3_0 = next_uop_fu_code_3; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fu_code_4_0 = next_uop_fu_code_4; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fu_code_5_0 = next_uop_fu_code_5; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fu_code_6_0 = next_uop_fu_code_6; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fu_code_7_0 = next_uop_fu_code_7; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fu_code_8_0 = next_uop_fu_code_8; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fu_code_9_0 = next_uop_fu_code_9; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_iw_issued_0 = next_uop_iw_issued; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_iw_p1_speculative_child_0 = next_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_iw_p2_speculative_child_0 = next_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_iw_p1_bypass_hint_0 = next_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_iw_p2_bypass_hint_0 = next_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_iw_p3_bypass_hint_0 = next_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_dis_col_sel_0 = next_uop_dis_col_sel; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_br_mask_0 = next_uop_br_mask; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_br_tag_0 = next_uop_br_tag; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_br_type_0 = next_uop_br_type; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_is_sfb_0 = next_uop_is_sfb; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_is_fence_0 = next_uop_is_fence; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_is_fencei_0 = next_uop_is_fencei; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_is_sfence_0 = next_uop_is_sfence; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_is_amo_0 = next_uop_is_amo; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_is_eret_0 = next_uop_is_eret; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_is_sys_pc2epc_0 = next_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_is_rocc_0 = next_uop_is_rocc; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_is_mov_0 = next_uop_is_mov; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_ftq_idx_0 = next_uop_ftq_idx; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_edge_inst_0 = next_uop_edge_inst; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_pc_lob_0 = next_uop_pc_lob; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_taken_0 = next_uop_taken; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_imm_rename_0 = next_uop_imm_rename; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_imm_sel_0 = next_uop_imm_sel; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_pimm_0 = next_uop_pimm; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_imm_packed_0 = next_uop_imm_packed; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_op1_sel_0 = next_uop_op1_sel; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_op2_sel_0 = next_uop_op2_sel; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_ldst_0 = next_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_wen_0 = next_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_ren1_0 = next_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_ren2_0 = next_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_ren3_0 = next_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_swap12_0 = next_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_swap23_0 = next_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_typeTagIn_0 = next_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_typeTagOut_0 = next_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_fromint_0 = next_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_toint_0 = next_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_fastpipe_0 = next_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_fma_0 = next_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_div_0 = next_uop_fp_ctrl_div; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_sqrt_0 = next_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_wflags_0 = next_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_vec_0 = next_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_rob_idx_0 = next_uop_rob_idx; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_ldq_idx_0 = next_uop_ldq_idx; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_stq_idx_0 = next_uop_stq_idx; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_rxq_idx_0 = next_uop_rxq_idx; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_pdst_0 = next_uop_pdst; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_prs1_0 = next_uop_prs1; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_prs2_0 = next_uop_prs2; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_prs3_0 = next_uop_prs3; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_ppred_0 = next_uop_ppred; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_prs1_busy_0 = next_uop_prs1_busy; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_prs2_busy_0 = next_uop_prs2_busy; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_prs3_busy_0 = next_uop_prs3_busy; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_ppred_busy_0 = next_uop_ppred_busy; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_stale_pdst_0 = next_uop_stale_pdst; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_exception_0 = next_uop_exception; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_exc_cause_0 = next_uop_exc_cause; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_mem_cmd_0 = next_uop_mem_cmd; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_mem_size_0 = next_uop_mem_size; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_mem_signed_0 = next_uop_mem_signed; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_uses_ldq_0 = next_uop_uses_ldq; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_uses_stq_0 = next_uop_uses_stq; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_is_unique_0 = next_uop_is_unique; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_flush_on_commit_0 = next_uop_flush_on_commit; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_csr_cmd_0 = next_uop_csr_cmd; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_ldst_is_rs1_0 = next_uop_ldst_is_rs1; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_ldst_0 = next_uop_ldst; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_lrs1_0 = next_uop_lrs1; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_lrs2_0 = next_uop_lrs2; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_lrs3_0 = next_uop_lrs3; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_dst_rtype_0 = next_uop_dst_rtype; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_lrs1_rtype_0 = next_uop_lrs1_rtype; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_lrs2_rtype_0 = next_uop_lrs2_rtype; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_frs3_en_0 = next_uop_frs3_en; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fcn_dw_0 = next_uop_fcn_dw; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fcn_op_0 = next_uop_fcn_op; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_val_0 = next_uop_fp_val; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_rm_0 = next_uop_fp_rm; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_typ_0 = next_uop_fp_typ; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_xcpt_pf_if_0 = next_uop_xcpt_pf_if; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_xcpt_ae_if_0 = next_uop_xcpt_ae_if; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_xcpt_ma_if_0 = next_uop_xcpt_ma_if; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_bp_debug_if_0 = next_uop_bp_debug_if; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_bp_xcpt_if_0 = next_uop_bp_xcpt_if; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_debug_fsrc_0 = next_uop_debug_fsrc; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_debug_tsrc_0 = next_uop_debug_tsrc; // @[issue-slot.scala:49:7, :59:28]
wire [11:0] _killed_T = io_brupdate_b1_mispredict_mask_0 & slot_uop_br_mask; // @[util.scala:126:51]
wire _killed_T_1 = |_killed_T; // @[util.scala:126:{51,59}]
wire killed = _killed_T_1 | io_kill_0; // @[util.scala:61:61, :126:59]
wire _io_will_be_valid_T = ~killed; // @[util.scala:61:61]
assign _io_will_be_valid_T_1 = next_valid & _io_will_be_valid_T; // @[issue-slot.scala:58:28, :65:{34,37}]
assign io_will_be_valid_0 = _io_will_be_valid_T_1; // @[issue-slot.scala:49:7, :65:34]
wire _slot_valid_T = ~killed; // @[util.scala:61:61]
wire _slot_valid_T_1 = next_valid & _slot_valid_T; // @[issue-slot.scala:58:28, :74:{30,33}] |
Generate the Verilog code corresponding to the following Chisel files.
File Tile.scala:
// See README.md for license details.
package gemmini
import chisel3._
import chisel3.util._
import Util._
/**
* A Tile is a purely combinational 2D array of passThrough PEs.
* a, b, s, and in_propag are broadcast across the entire array and are passed through to the Tile's outputs
* @param width The data width of each PE in bits
* @param rows Number of PEs on each row
* @param columns Number of PEs on each column
*/
class Tile[T <: Data](inputType: T, outputType: T, accType: T, df: Dataflow.Value, tree_reduction: Boolean, max_simultaneous_matmuls: Int, val rows: Int, val columns: Int)(implicit ev: Arithmetic[T]) extends Module {
val io = IO(new Bundle {
val in_a = Input(Vec(rows, inputType))
val in_b = Input(Vec(columns, outputType)) // This is the output of the tile next to it
val in_d = Input(Vec(columns, outputType))
val in_control = Input(Vec(columns, new PEControl(accType)))
val in_id = Input(Vec(columns, UInt(log2Up(max_simultaneous_matmuls).W)))
val in_last = Input(Vec(columns, Bool()))
val out_a = Output(Vec(rows, inputType))
val out_c = Output(Vec(columns, outputType))
val out_b = Output(Vec(columns, outputType))
val out_control = Output(Vec(columns, new PEControl(accType)))
val out_id = Output(Vec(columns, UInt(log2Up(max_simultaneous_matmuls).W)))
val out_last = Output(Vec(columns, Bool()))
val in_valid = Input(Vec(columns, Bool()))
val out_valid = Output(Vec(columns, Bool()))
val bad_dataflow = Output(Bool())
})
import ev._
val tile = Seq.fill(rows, columns)(Module(new PE(inputType, outputType, accType, df, max_simultaneous_matmuls)))
val tileT = tile.transpose
// TODO: abstract hori/vert broadcast, all these connections look the same
// Broadcast 'a' horizontally across the Tile
for (r <- 0 until rows) {
tile(r).foldLeft(io.in_a(r)) {
case (in_a, pe) =>
pe.io.in_a := in_a
pe.io.out_a
}
}
// Broadcast 'b' vertically across the Tile
for (c <- 0 until columns) {
tileT(c).foldLeft(io.in_b(c)) {
case (in_b, pe) =>
pe.io.in_b := (if (tree_reduction) in_b.zero else in_b)
pe.io.out_b
}
}
// Broadcast 'd' vertically across the Tile
for (c <- 0 until columns) {
tileT(c).foldLeft(io.in_d(c)) {
case (in_d, pe) =>
pe.io.in_d := in_d
pe.io.out_c
}
}
// Broadcast 'control' vertically across the Tile
for (c <- 0 until columns) {
tileT(c).foldLeft(io.in_control(c)) {
case (in_ctrl, pe) =>
pe.io.in_control := in_ctrl
pe.io.out_control
}
}
// Broadcast 'garbage' vertically across the Tile
for (c <- 0 until columns) {
tileT(c).foldLeft(io.in_valid(c)) {
case (v, pe) =>
pe.io.in_valid := v
pe.io.out_valid
}
}
// Broadcast 'id' vertically across the Tile
for (c <- 0 until columns) {
tileT(c).foldLeft(io.in_id(c)) {
case (id, pe) =>
pe.io.in_id := id
pe.io.out_id
}
}
// Broadcast 'last' vertically across the Tile
for (c <- 0 until columns) {
tileT(c).foldLeft(io.in_last(c)) {
case (last, pe) =>
pe.io.in_last := last
pe.io.out_last
}
}
// Drive the Tile's bottom IO
for (c <- 0 until columns) {
io.out_c(c) := tile(rows-1)(c).io.out_c
io.out_control(c) := tile(rows-1)(c).io.out_control
io.out_id(c) := tile(rows-1)(c).io.out_id
io.out_last(c) := tile(rows-1)(c).io.out_last
io.out_valid(c) := tile(rows-1)(c).io.out_valid
io.out_b(c) := {
if (tree_reduction) {
val prods = tileT(c).map(_.io.out_b)
accumulateTree(prods :+ io.in_b(c))
} else {
tile(rows - 1)(c).io.out_b
}
}
}
io.bad_dataflow := tile.map(_.map(_.io.bad_dataflow).reduce(_||_)).reduce(_||_)
// Drive the Tile's right IO
for (r <- 0 until rows) {
io.out_a(r) := tile(r)(columns-1).io.out_a
}
}
| module Tile_9( // @[Tile.scala:16:7]
input clock, // @[Tile.scala:16:7]
input reset, // @[Tile.scala:16:7]
input [31:0] io_in_a_0_bits, // @[Tile.scala:17:14]
input [31:0] io_in_b_0_bits, // @[Tile.scala:17:14]
input [31:0] io_in_d_0_bits, // @[Tile.scala:17:14]
input io_in_control_0_dataflow, // @[Tile.scala:17:14]
input io_in_control_0_propagate, // @[Tile.scala:17:14]
input [4:0] io_in_control_0_shift, // @[Tile.scala:17:14]
input [3:0] io_in_id_0, // @[Tile.scala:17:14]
input io_in_last_0, // @[Tile.scala:17:14]
output [31:0] io_out_a_0_bits, // @[Tile.scala:17:14]
output [31:0] io_out_c_0_bits, // @[Tile.scala:17:14]
output [31:0] io_out_b_0_bits, // @[Tile.scala:17:14]
output io_out_control_0_dataflow, // @[Tile.scala:17:14]
output io_out_control_0_propagate, // @[Tile.scala:17:14]
output [4:0] io_out_control_0_shift, // @[Tile.scala:17:14]
output [3:0] io_out_id_0, // @[Tile.scala:17:14]
output io_out_last_0, // @[Tile.scala:17:14]
input io_in_valid_0, // @[Tile.scala:17:14]
output io_out_valid_0, // @[Tile.scala:17:14]
output io_bad_dataflow // @[Tile.scala:17:14]
);
wire [31:0] io_in_a_0_bits_0 = io_in_a_0_bits; // @[Tile.scala:16:7]
wire [31:0] io_in_b_0_bits_0 = io_in_b_0_bits; // @[Tile.scala:16:7]
wire [31:0] io_in_d_0_bits_0 = io_in_d_0_bits; // @[Tile.scala:16:7]
wire io_in_control_0_dataflow_0 = io_in_control_0_dataflow; // @[Tile.scala:16:7]
wire io_in_control_0_propagate_0 = io_in_control_0_propagate; // @[Tile.scala:16:7]
wire [4:0] io_in_control_0_shift_0 = io_in_control_0_shift; // @[Tile.scala:16:7]
wire [3:0] io_in_id_0_0 = io_in_id_0; // @[Tile.scala:16:7]
wire io_in_last_0_0 = io_in_last_0; // @[Tile.scala:16:7]
wire io_in_valid_0_0 = io_in_valid_0; // @[Tile.scala:16:7]
wire [31:0] io_out_a_0_bits_0; // @[Tile.scala:16:7]
wire [31:0] io_out_c_0_bits_0; // @[Tile.scala:16:7]
wire [31:0] io_out_b_0_bits_0; // @[Tile.scala:16:7]
wire io_out_control_0_dataflow_0; // @[Tile.scala:16:7]
wire io_out_control_0_propagate_0; // @[Tile.scala:16:7]
wire [4:0] io_out_control_0_shift_0; // @[Tile.scala:16:7]
wire [3:0] io_out_id_0_0; // @[Tile.scala:16:7]
wire io_out_last_0_0; // @[Tile.scala:16:7]
wire io_out_valid_0_0; // @[Tile.scala:16:7]
wire io_bad_dataflow_0; // @[Tile.scala:16:7]
PE_25 tile_0_0 ( // @[Tile.scala:42:44]
.clock (clock),
.reset (reset),
.io_in_a_bits (io_in_a_0_bits_0), // @[Tile.scala:16:7]
.io_in_b_bits (io_in_b_0_bits_0), // @[Tile.scala:16:7]
.io_in_d_bits (io_in_d_0_bits_0), // @[Tile.scala:16:7]
.io_out_a_bits (io_out_a_0_bits_0),
.io_out_b_bits (io_out_b_0_bits_0),
.io_out_c_bits (io_out_c_0_bits_0),
.io_in_control_dataflow (io_in_control_0_dataflow_0), // @[Tile.scala:16:7]
.io_in_control_propagate (io_in_control_0_propagate_0), // @[Tile.scala:16:7]
.io_in_control_shift (io_in_control_0_shift_0), // @[Tile.scala:16:7]
.io_out_control_dataflow (io_out_control_0_dataflow_0),
.io_out_control_propagate (io_out_control_0_propagate_0),
.io_out_control_shift (io_out_control_0_shift_0),
.io_in_id (io_in_id_0_0), // @[Tile.scala:16:7]
.io_out_id (io_out_id_0_0),
.io_in_last (io_in_last_0_0), // @[Tile.scala:16:7]
.io_out_last (io_out_last_0_0),
.io_in_valid (io_in_valid_0_0), // @[Tile.scala:16:7]
.io_out_valid (io_out_valid_0_0),
.io_bad_dataflow (io_bad_dataflow_0)
); // @[Tile.scala:42:44]
assign io_out_a_0_bits = io_out_a_0_bits_0; // @[Tile.scala:16:7]
assign io_out_c_0_bits = io_out_c_0_bits_0; // @[Tile.scala:16:7]
assign io_out_b_0_bits = io_out_b_0_bits_0; // @[Tile.scala:16:7]
assign io_out_control_0_dataflow = io_out_control_0_dataflow_0; // @[Tile.scala:16:7]
assign io_out_control_0_propagate = io_out_control_0_propagate_0; // @[Tile.scala:16:7]
assign io_out_control_0_shift = io_out_control_0_shift_0; // @[Tile.scala:16:7]
assign io_out_id_0 = io_out_id_0_0; // @[Tile.scala:16:7]
assign io_out_last_0 = io_out_last_0_0; // @[Tile.scala:16:7]
assign io_out_valid_0 = io_out_valid_0_0; // @[Tile.scala:16:7]
assign io_bad_dataflow = io_bad_dataflow_0; // @[Tile.scala:16:7]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File PE.scala:
// See README.md for license details.
package gemmini
import chisel3._
import chisel3.util._
class PEControl[T <: Data : Arithmetic](accType: T) extends Bundle {
val dataflow = UInt(1.W) // TODO make this an Enum
val propagate = UInt(1.W) // Which register should be propagated (and which should be accumulated)?
val shift = UInt(log2Up(accType.getWidth).W) // TODO this isn't correct for Floats
}
class MacUnit[T <: Data](inputType: T, cType: T, dType: T) (implicit ev: Arithmetic[T]) extends Module {
import ev._
val io = IO(new Bundle {
val in_a = Input(inputType)
val in_b = Input(inputType)
val in_c = Input(cType)
val out_d = Output(dType)
})
io.out_d := io.in_c.mac(io.in_a, io.in_b)
}
// TODO update documentation
/**
* A PE implementing a MAC operation. Configured as fully combinational when integrated into a Mesh.
* @param width Data width of operands
*/
class PE[T <: Data](inputType: T, outputType: T, accType: T, df: Dataflow.Value, max_simultaneous_matmuls: Int)
(implicit ev: Arithmetic[T]) extends Module { // Debugging variables
import ev._
val io = IO(new Bundle {
val in_a = Input(inputType)
val in_b = Input(outputType)
val in_d = Input(outputType)
val out_a = Output(inputType)
val out_b = Output(outputType)
val out_c = Output(outputType)
val in_control = Input(new PEControl(accType))
val out_control = Output(new PEControl(accType))
val in_id = Input(UInt(log2Up(max_simultaneous_matmuls).W))
val out_id = Output(UInt(log2Up(max_simultaneous_matmuls).W))
val in_last = Input(Bool())
val out_last = Output(Bool())
val in_valid = Input(Bool())
val out_valid = Output(Bool())
val bad_dataflow = Output(Bool())
})
val cType = if (df == Dataflow.WS) inputType else accType
// When creating PEs that support multiple dataflows, the
// elaboration/synthesis tools often fail to consolidate and de-duplicate
// MAC units. To force mac circuitry to be re-used, we create a "mac_unit"
// module here which just performs a single MAC operation
val mac_unit = Module(new MacUnit(inputType,
if (df == Dataflow.WS) outputType else accType, outputType))
val a = io.in_a
val b = io.in_b
val d = io.in_d
val c1 = Reg(cType)
val c2 = Reg(cType)
val dataflow = io.in_control.dataflow
val prop = io.in_control.propagate
val shift = io.in_control.shift
val id = io.in_id
val last = io.in_last
val valid = io.in_valid
io.out_a := a
io.out_control.dataflow := dataflow
io.out_control.propagate := prop
io.out_control.shift := shift
io.out_id := id
io.out_last := last
io.out_valid := valid
mac_unit.io.in_a := a
val last_s = RegEnable(prop, valid)
val flip = last_s =/= prop
val shift_offset = Mux(flip, shift, 0.U)
// Which dataflow are we using?
val OUTPUT_STATIONARY = Dataflow.OS.id.U(1.W)
val WEIGHT_STATIONARY = Dataflow.WS.id.U(1.W)
// Is c1 being computed on, or propagated forward (in the output-stationary dataflow)?
val COMPUTE = 0.U(1.W)
val PROPAGATE = 1.U(1.W)
io.bad_dataflow := false.B
when ((df == Dataflow.OS).B || ((df == Dataflow.BOTH).B && dataflow === OUTPUT_STATIONARY)) {
when(prop === PROPAGATE) {
io.out_c := (c1 >> shift_offset).clippedToWidthOf(outputType)
io.out_b := b
mac_unit.io.in_b := b.asTypeOf(inputType)
mac_unit.io.in_c := c2
c2 := mac_unit.io.out_d
c1 := d.withWidthOf(cType)
}.otherwise {
io.out_c := (c2 >> shift_offset).clippedToWidthOf(outputType)
io.out_b := b
mac_unit.io.in_b := b.asTypeOf(inputType)
mac_unit.io.in_c := c1
c1 := mac_unit.io.out_d
c2 := d.withWidthOf(cType)
}
}.elsewhen ((df == Dataflow.WS).B || ((df == Dataflow.BOTH).B && dataflow === WEIGHT_STATIONARY)) {
when(prop === PROPAGATE) {
io.out_c := c1
mac_unit.io.in_b := c2.asTypeOf(inputType)
mac_unit.io.in_c := b
io.out_b := mac_unit.io.out_d
c1 := d
}.otherwise {
io.out_c := c2
mac_unit.io.in_b := c1.asTypeOf(inputType)
mac_unit.io.in_c := b
io.out_b := mac_unit.io.out_d
c2 := d
}
}.otherwise {
io.bad_dataflow := true.B
//assert(false.B, "unknown dataflow")
io.out_c := DontCare
io.out_b := DontCare
mac_unit.io.in_b := b.asTypeOf(inputType)
mac_unit.io.in_c := c2
}
when (!valid) {
c1 := c1
c2 := c2
mac_unit.io.in_b := DontCare
mac_unit.io.in_c := DontCare
}
}
File Arithmetic.scala:
// A simple type class for Chisel datatypes that can add and multiply. To add your own type, simply create your own:
// implicit MyTypeArithmetic extends Arithmetic[MyType] { ... }
package gemmini
import chisel3._
import chisel3.util._
import hardfloat._
// Bundles that represent the raw bits of custom datatypes
case class Float(expWidth: Int, sigWidth: Int) extends Bundle {
val bits = UInt((expWidth + sigWidth).W)
val bias: Int = (1 << (expWidth-1)) - 1
}
case class DummySInt(w: Int) extends Bundle {
val bits = UInt(w.W)
def dontCare: DummySInt = {
val o = Wire(new DummySInt(w))
o.bits := 0.U
o
}
}
// The Arithmetic typeclass which implements various arithmetic operations on custom datatypes
abstract class Arithmetic[T <: Data] {
implicit def cast(t: T): ArithmeticOps[T]
}
abstract class ArithmeticOps[T <: Data](self: T) {
def *(t: T): T
def mac(m1: T, m2: T): T // Returns (m1 * m2 + self)
def +(t: T): T
def -(t: T): T
def >>(u: UInt): T // This is a rounding shift! Rounds away from 0
def >(t: T): Bool
def identity: T
def withWidthOf(t: T): T
def clippedToWidthOf(t: T): T // Like "withWidthOf", except that it saturates
def relu: T
def zero: T
def minimum: T
// Optional parameters, which only need to be defined if you want to enable various optimizations for transformers
def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[T])] = None
def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[T])] = None
def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = None
def mult_with_reciprocal[U <: Data](reciprocal: U) = self
}
object Arithmetic {
implicit object UIntArithmetic extends Arithmetic[UInt] {
override implicit def cast(self: UInt) = new ArithmeticOps(self) {
override def *(t: UInt) = self * t
override def mac(m1: UInt, m2: UInt) = m1 * m2 + self
override def +(t: UInt) = self + t
override def -(t: UInt) = self - t
override def >>(u: UInt) = {
// The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm
// TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here?
val point_five = Mux(u === 0.U, 0.U, self(u - 1.U))
val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U
val ones_digit = self(u)
val r = point_five & (zeros | ones_digit)
(self >> u).asUInt + r
}
override def >(t: UInt): Bool = self > t
override def withWidthOf(t: UInt) = self.asTypeOf(t)
override def clippedToWidthOf(t: UInt) = {
val sat = ((1 << (t.getWidth-1))-1).U
Mux(self > sat, sat, self)(t.getWidth-1, 0)
}
override def relu: UInt = self
override def zero: UInt = 0.U
override def identity: UInt = 1.U
override def minimum: UInt = 0.U
}
}
implicit object SIntArithmetic extends Arithmetic[SInt] {
override implicit def cast(self: SInt) = new ArithmeticOps(self) {
override def *(t: SInt) = self * t
override def mac(m1: SInt, m2: SInt) = m1 * m2 + self
override def +(t: SInt) = self + t
override def -(t: SInt) = self - t
override def >>(u: UInt) = {
// The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm
// TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here?
val point_five = Mux(u === 0.U, 0.U, self(u - 1.U))
val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U
val ones_digit = self(u)
val r = (point_five & (zeros | ones_digit)).asBool
(self >> u).asSInt + Mux(r, 1.S, 0.S)
}
override def >(t: SInt): Bool = self > t
override def withWidthOf(t: SInt) = {
if (self.getWidth >= t.getWidth)
self(t.getWidth-1, 0).asSInt
else {
val sign_bits = t.getWidth - self.getWidth
val sign = self(self.getWidth-1)
Cat(Cat(Seq.fill(sign_bits)(sign)), self).asTypeOf(t)
}
}
override def clippedToWidthOf(t: SInt): SInt = {
val maxsat = ((1 << (t.getWidth-1))-1).S
val minsat = (-(1 << (t.getWidth-1))).S
MuxCase(self, Seq((self > maxsat) -> maxsat, (self < minsat) -> minsat))(t.getWidth-1, 0).asSInt
}
override def relu: SInt = Mux(self >= 0.S, self, 0.S)
override def zero: SInt = 0.S
override def identity: SInt = 1.S
override def minimum: SInt = (-(1 << (self.getWidth-1))).S
override def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = {
// TODO this uses a floating point divider, but we should use an integer divider instead
val input = Wire(Decoupled(denom_t.cloneType))
val output = Wire(Decoupled(self.cloneType))
// We translate our integer to floating-point form so that we can use the hardfloat divider
val expWidth = log2Up(self.getWidth) + 1
val sigWidth = self.getWidth
def sin_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def uin_to_float(x: UInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := false.B
in_to_rec_fn.io.in := x
in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def float_to_in(x: UInt) = {
val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth))
rec_fn_to_in.io.signedOut := true.B
rec_fn_to_in.io.in := x
rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
rec_fn_to_in.io.out.asSInt
}
val self_rec = sin_to_float(self)
val denom_rec = uin_to_float(input.bits)
// Instantiate the hardloat divider
val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options))
input.ready := divider.io.inReady
divider.io.inValid := input.valid
divider.io.sqrtOp := false.B
divider.io.a := self_rec
divider.io.b := denom_rec
divider.io.roundingMode := consts.round_minMag
divider.io.detectTininess := consts.tininess_afterRounding
output.valid := divider.io.outValid_div
output.bits := float_to_in(divider.io.out)
assert(!output.valid || output.ready)
Some((input, output))
}
override def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = {
// TODO this uses a floating point divider, but we should use an integer divider instead
val input = Wire(Decoupled(UInt(0.W)))
val output = Wire(Decoupled(self.cloneType))
input.bits := DontCare
// We translate our integer to floating-point form so that we can use the hardfloat divider
val expWidth = log2Up(self.getWidth) + 1
val sigWidth = self.getWidth
def in_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def float_to_in(x: UInt) = {
val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth))
rec_fn_to_in.io.signedOut := true.B
rec_fn_to_in.io.in := x
rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
rec_fn_to_in.io.out.asSInt
}
val self_rec = in_to_float(self)
// Instantiate the hardloat sqrt
val sqrter = Module(new DivSqrtRecFN_small(expWidth, sigWidth, 0))
input.ready := sqrter.io.inReady
sqrter.io.inValid := input.valid
sqrter.io.sqrtOp := true.B
sqrter.io.a := self_rec
sqrter.io.b := DontCare
sqrter.io.roundingMode := consts.round_minMag
sqrter.io.detectTininess := consts.tininess_afterRounding
output.valid := sqrter.io.outValid_sqrt
output.bits := float_to_in(sqrter.io.out)
assert(!output.valid || output.ready)
Some((input, output))
}
override def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = u match {
case Float(expWidth, sigWidth) =>
val input = Wire(Decoupled(UInt(0.W)))
val output = Wire(Decoupled(u.cloneType))
input.bits := DontCare
// We translate our integer to floating-point form so that we can use the hardfloat divider
def in_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
val self_rec = in_to_float(self)
val one_rec = in_to_float(1.S)
// Instantiate the hardloat divider
val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options))
input.ready := divider.io.inReady
divider.io.inValid := input.valid
divider.io.sqrtOp := false.B
divider.io.a := one_rec
divider.io.b := self_rec
divider.io.roundingMode := consts.round_near_even
divider.io.detectTininess := consts.tininess_afterRounding
output.valid := divider.io.outValid_div
output.bits := fNFromRecFN(expWidth, sigWidth, divider.io.out).asTypeOf(u)
assert(!output.valid || output.ready)
Some((input, output))
case _ => None
}
override def mult_with_reciprocal[U <: Data](reciprocal: U): SInt = reciprocal match {
case recip @ Float(expWidth, sigWidth) =>
def in_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def float_to_in(x: UInt) = {
val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth))
rec_fn_to_in.io.signedOut := true.B
rec_fn_to_in.io.in := x
rec_fn_to_in.io.roundingMode := consts.round_minMag
rec_fn_to_in.io.out.asSInt
}
val self_rec = in_to_float(self)
val reciprocal_rec = recFNFromFN(expWidth, sigWidth, recip.bits)
// Instantiate the hardloat divider
val muladder = Module(new MulRecFN(expWidth, sigWidth))
muladder.io.roundingMode := consts.round_near_even
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := self_rec
muladder.io.b := reciprocal_rec
float_to_in(muladder.io.out)
case _ => self
}
}
}
implicit object FloatArithmetic extends Arithmetic[Float] {
// TODO Floating point arithmetic currently switches between recoded and standard formats for every operation. However, it should stay in the recoded format as it travels through the systolic array
override implicit def cast(self: Float): ArithmeticOps[Float] = new ArithmeticOps(self) {
override def *(t: Float): Float = {
val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth))
t_resizer.io.in := t_rec
t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
t_resizer.io.detectTininess := consts.tininess_afterRounding
val t_rec_resized = t_resizer.io.out
val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth))
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := self_rec
muladder.io.b := t_rec_resized
val out = Wire(Float(self.expWidth, self.sigWidth))
out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
out
}
override def mac(m1: Float, m2: Float): Float = {
// Recode all operands
val m1_rec = recFNFromFN(m1.expWidth, m1.sigWidth, m1.bits)
val m2_rec = recFNFromFN(m2.expWidth, m2.sigWidth, m2.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Resize m1 to self's width
val m1_resizer = Module(new RecFNToRecFN(m1.expWidth, m1.sigWidth, self.expWidth, self.sigWidth))
m1_resizer.io.in := m1_rec
m1_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
m1_resizer.io.detectTininess := consts.tininess_afterRounding
val m1_rec_resized = m1_resizer.io.out
// Resize m2 to self's width
val m2_resizer = Module(new RecFNToRecFN(m2.expWidth, m2.sigWidth, self.expWidth, self.sigWidth))
m2_resizer.io.in := m2_rec
m2_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
m2_resizer.io.detectTininess := consts.tininess_afterRounding
val m2_rec_resized = m2_resizer.io.out
// Perform multiply-add
val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth))
muladder.io.op := 0.U
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := m1_rec_resized
muladder.io.b := m2_rec_resized
muladder.io.c := self_rec
// Convert result to standard format // TODO remove these intermediate recodings
val out = Wire(Float(self.expWidth, self.sigWidth))
out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
out
}
override def +(t: Float): Float = {
require(self.getWidth >= t.getWidth) // This just makes it easier to write the resizing code
// Recode all operands
val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Generate 1 as a float
val in_to_rec_fn = Module(new INToRecFN(1, self.expWidth, self.sigWidth))
in_to_rec_fn.io.signedIn := false.B
in_to_rec_fn.io.in := 1.U
in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
val one_rec = in_to_rec_fn.io.out
// Resize t
val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth))
t_resizer.io.in := t_rec
t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
t_resizer.io.detectTininess := consts.tininess_afterRounding
val t_rec_resized = t_resizer.io.out
// Perform addition
val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth))
muladder.io.op := 0.U
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := t_rec_resized
muladder.io.b := one_rec
muladder.io.c := self_rec
val result = Wire(Float(self.expWidth, self.sigWidth))
result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
result
}
override def -(t: Float): Float = {
val t_sgn = t.bits(t.getWidth-1)
val neg_t = Cat(~t_sgn, t.bits(t.getWidth-2,0)).asTypeOf(t)
self + neg_t
}
override def >>(u: UInt): Float = {
// Recode self
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Get 2^(-u) as a recoded float
val shift_exp = Wire(UInt(self.expWidth.W))
shift_exp := self.bias.U - u
val shift_fn = Cat(0.U(1.W), shift_exp, 0.U((self.sigWidth-1).W))
val shift_rec = recFNFromFN(self.expWidth, self.sigWidth, shift_fn)
assert(shift_exp =/= 0.U, "scaling by denormalized numbers is not currently supported")
// Multiply self and 2^(-u)
val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth))
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := self_rec
muladder.io.b := shift_rec
val result = Wire(Float(self.expWidth, self.sigWidth))
result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
result
}
override def >(t: Float): Bool = {
// Recode all operands
val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Resize t to self's width
val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth))
t_resizer.io.in := t_rec
t_resizer.io.roundingMode := consts.round_near_even
t_resizer.io.detectTininess := consts.tininess_afterRounding
val t_rec_resized = t_resizer.io.out
val comparator = Module(new CompareRecFN(self.expWidth, self.sigWidth))
comparator.io.a := self_rec
comparator.io.b := t_rec_resized
comparator.io.signaling := false.B
comparator.io.gt
}
override def withWidthOf(t: Float): Float = {
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth))
resizer.io.in := self_rec
resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
resizer.io.detectTininess := consts.tininess_afterRounding
val result = Wire(Float(t.expWidth, t.sigWidth))
result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out)
result
}
override def clippedToWidthOf(t: Float): Float = {
// TODO check for overflow. Right now, we just assume that overflow doesn't happen
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth))
resizer.io.in := self_rec
resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
resizer.io.detectTininess := consts.tininess_afterRounding
val result = Wire(Float(t.expWidth, t.sigWidth))
result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out)
result
}
override def relu: Float = {
val raw = rawFloatFromFN(self.expWidth, self.sigWidth, self.bits)
val result = Wire(Float(self.expWidth, self.sigWidth))
result.bits := Mux(!raw.isZero && raw.sign, 0.U, self.bits)
result
}
override def zero: Float = 0.U.asTypeOf(self)
override def identity: Float = Cat(0.U(2.W), ~(0.U((self.expWidth-1).W)), 0.U((self.sigWidth-1).W)).asTypeOf(self)
override def minimum: Float = Cat(1.U, ~(0.U(self.expWidth.W)), 0.U((self.sigWidth-1).W)).asTypeOf(self)
}
}
implicit object DummySIntArithmetic extends Arithmetic[DummySInt] {
override implicit def cast(self: DummySInt) = new ArithmeticOps(self) {
override def *(t: DummySInt) = self.dontCare
override def mac(m1: DummySInt, m2: DummySInt) = self.dontCare
override def +(t: DummySInt) = self.dontCare
override def -(t: DummySInt) = self.dontCare
override def >>(t: UInt) = self.dontCare
override def >(t: DummySInt): Bool = false.B
override def identity = self.dontCare
override def withWidthOf(t: DummySInt) = self.dontCare
override def clippedToWidthOf(t: DummySInt) = self.dontCare
override def relu = self.dontCare
override def zero = self.dontCare
override def minimum: DummySInt = self.dontCare
}
}
}
| module MacUnit_50( // @[PE.scala:14:7]
input clock, // @[PE.scala:14:7]
input reset, // @[PE.scala:14:7]
input [7:0] io_in_a, // @[PE.scala:16:14]
input [7:0] io_in_b, // @[PE.scala:16:14]
input [31:0] io_in_c, // @[PE.scala:16:14]
output [19:0] io_out_d // @[PE.scala:16:14]
);
wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:14:7]
wire [7:0] io_in_b_0 = io_in_b; // @[PE.scala:14:7]
wire [31:0] io_in_c_0 = io_in_c; // @[PE.scala:14:7]
wire [19:0] io_out_d_0; // @[PE.scala:14:7]
wire [15:0] _io_out_d_T = {{8{io_in_a_0[7]}}, io_in_a_0} * {{8{io_in_b_0[7]}}, io_in_b_0}; // @[PE.scala:14:7]
wire [32:0] _io_out_d_T_1 = {{17{_io_out_d_T[15]}}, _io_out_d_T} + {io_in_c_0[31], io_in_c_0}; // @[PE.scala:14:7]
wire [31:0] _io_out_d_T_2 = _io_out_d_T_1[31:0]; // @[Arithmetic.scala:93:54]
wire [31:0] _io_out_d_T_3 = _io_out_d_T_2; // @[Arithmetic.scala:93:54]
assign io_out_d_0 = _io_out_d_T_3[19:0]; // @[PE.scala:14:7, :23:12]
assign io_out_d = io_out_d_0; // @[PE.scala:14:7]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File EgressUnit.scala:
package constellation.router
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.{Field, Parameters}
import freechips.rocketchip.util._
import constellation.channel._
import constellation.routing.{FlowRoutingBundle}
class EgressUnit(coupleSAVA: Boolean, combineSAST: Boolean, inParams: Seq[ChannelParams], ingressParams: Seq[IngressChannelParams], cParam: EgressChannelParams)
(implicit p: Parameters) extends AbstractOutputUnit(inParams, ingressParams, cParam)(p) {
class EgressUnitIO extends AbstractOutputUnitIO(inParams, ingressParams, cParam) {
val out = Decoupled(new EgressFlit(cParam.payloadBits))
}
val io = IO(new EgressUnitIO)
val channel_empty = RegInit(true.B)
val flow = Reg(new FlowRoutingBundle)
val q = Module(new Queue(new EgressFlit(cParam.payloadBits), 3 - (if (combineSAST) 1 else 0), flow=true))
q.io.enq.valid := io.in(0).valid
q.io.enq.bits.head := io.in(0).bits.head
q.io.enq.bits.tail := io.in(0).bits.tail
val flows = cParam.possibleFlows.toSeq
if (flows.size == 0) {
q.io.enq.bits.ingress_id := 0.U(1.W)
} else {
q.io.enq.bits.ingress_id := Mux1H(
flows.map(f => (f.ingressNode.U === io.in(0).bits.flow.ingress_node &&
f.ingressNodeId.U === io.in(0).bits.flow.ingress_node_id)),
flows.map(f => f.ingressId.U(ingressIdBits.W))
)
}
q.io.enq.bits.payload := io.in(0).bits.payload
io.out <> q.io.deq
assert(!(q.io.enq.valid && !q.io.enq.ready))
io.credit_available(0) := q.io.count === 0.U
io.channel_status(0).occupied := !channel_empty
io.channel_status(0).flow := flow
when (io.credit_alloc(0).alloc && io.credit_alloc(0).tail) {
channel_empty := true.B
if (coupleSAVA) io.channel_status(0).occupied := false.B
}
when (io.allocs(0).alloc) {
channel_empty := false.B
flow := io.allocs(0).flow
}
}
| module EgressUnit_5( // @[EgressUnit.scala:12:7]
input clock, // @[EgressUnit.scala:12:7]
input reset, // @[EgressUnit.scala:12:7]
input io_in_0_valid, // @[EgressUnit.scala:18:14]
input io_in_0_bits_head, // @[EgressUnit.scala:18:14]
input io_in_0_bits_tail, // @[EgressUnit.scala:18:14]
input [72:0] io_in_0_bits_payload, // @[EgressUnit.scala:18:14]
input [3:0] io_in_0_bits_flow_ingress_node, // @[EgressUnit.scala:18:14]
input [1:0] io_in_0_bits_flow_ingress_node_id, // @[EgressUnit.scala:18:14]
output io_credit_available_0, // @[EgressUnit.scala:18:14]
output io_channel_status_0_occupied, // @[EgressUnit.scala:18:14]
input io_allocs_0_alloc, // @[EgressUnit.scala:18:14]
input io_credit_alloc_0_alloc, // @[EgressUnit.scala:18:14]
input io_credit_alloc_0_tail, // @[EgressUnit.scala:18:14]
input io_out_ready, // @[EgressUnit.scala:18:14]
output io_out_valid, // @[EgressUnit.scala:18:14]
output io_out_bits_head, // @[EgressUnit.scala:18:14]
output io_out_bits_tail, // @[EgressUnit.scala:18:14]
output [72:0] io_out_bits_payload // @[EgressUnit.scala:18:14]
);
wire _q_io_enq_ready; // @[EgressUnit.scala:22:17]
wire [1:0] _q_io_count; // @[EgressUnit.scala:22:17]
reg channel_empty; // @[EgressUnit.scala:20:30]
wire _q_io_enq_bits_ingress_id_T_13 = io_in_0_bits_flow_ingress_node_id == 2'h0; // @[EgressUnit.scala:32:27] |
Generate the Verilog code corresponding to the following Chisel files.
File DescribedSRAM.scala:
// See LICENSE.Berkeley for license details.
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3.{Data, SyncReadMem, Vec}
import chisel3.util.log2Ceil
object DescribedSRAM {
def apply[T <: Data](
name: String,
desc: String,
size: BigInt, // depth
data: T
): SyncReadMem[T] = {
val mem = SyncReadMem(size, data)
mem.suggestName(name)
val granWidth = data match {
case v: Vec[_] => v.head.getWidth
case d => d.getWidth
}
val uid = 0
Annotated.srams(
component = mem,
name = name,
address_width = log2Ceil(size),
data_width = data.getWidth,
depth = size,
description = desc,
write_mask_granularity = granWidth
)
mem
}
}
| module array_1_0_0( // @[DescribedSRAM.scala:17:26]
input [6:0] R0_addr,
input R0_en,
input R0_clk,
output [63:0] R0_data,
input [6:0] W0_addr,
input W0_en,
input W0_clk,
input [63:0] W0_data
);
array_0_0_0_ext array_0_0_0_ext ( // @[DescribedSRAM.scala:17:26]
.R0_addr (R0_addr),
.R0_en (R0_en),
.R0_clk (R0_clk),
.R0_data (R0_data),
.W0_addr (W0_addr),
.W0_en (W0_en),
.W0_clk (W0_clk),
.W0_data (W0_data)
); // @[DescribedSRAM.scala:17:26]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File PE.scala:
// See README.md for license details.
package gemmini
import chisel3._
import chisel3.util._
class PEControl[T <: Data : Arithmetic](accType: T) extends Bundle {
val dataflow = UInt(1.W) // TODO make this an Enum
val propagate = UInt(1.W) // Which register should be propagated (and which should be accumulated)?
val shift = UInt(log2Up(accType.getWidth).W) // TODO this isn't correct for Floats
}
class MacUnit[T <: Data](inputType: T, cType: T, dType: T) (implicit ev: Arithmetic[T]) extends Module {
import ev._
val io = IO(new Bundle {
val in_a = Input(inputType)
val in_b = Input(inputType)
val in_c = Input(cType)
val out_d = Output(dType)
})
io.out_d := io.in_c.mac(io.in_a, io.in_b)
}
// TODO update documentation
/**
* A PE implementing a MAC operation. Configured as fully combinational when integrated into a Mesh.
* @param width Data width of operands
*/
class PE[T <: Data](inputType: T, outputType: T, accType: T, df: Dataflow.Value, max_simultaneous_matmuls: Int)
(implicit ev: Arithmetic[T]) extends Module { // Debugging variables
import ev._
val io = IO(new Bundle {
val in_a = Input(inputType)
val in_b = Input(outputType)
val in_d = Input(outputType)
val out_a = Output(inputType)
val out_b = Output(outputType)
val out_c = Output(outputType)
val in_control = Input(new PEControl(accType))
val out_control = Output(new PEControl(accType))
val in_id = Input(UInt(log2Up(max_simultaneous_matmuls).W))
val out_id = Output(UInt(log2Up(max_simultaneous_matmuls).W))
val in_last = Input(Bool())
val out_last = Output(Bool())
val in_valid = Input(Bool())
val out_valid = Output(Bool())
val bad_dataflow = Output(Bool())
})
val cType = if (df == Dataflow.WS) inputType else accType
// When creating PEs that support multiple dataflows, the
// elaboration/synthesis tools often fail to consolidate and de-duplicate
// MAC units. To force mac circuitry to be re-used, we create a "mac_unit"
// module here which just performs a single MAC operation
val mac_unit = Module(new MacUnit(inputType,
if (df == Dataflow.WS) outputType else accType, outputType))
val a = io.in_a
val b = io.in_b
val d = io.in_d
val c1 = Reg(cType)
val c2 = Reg(cType)
val dataflow = io.in_control.dataflow
val prop = io.in_control.propagate
val shift = io.in_control.shift
val id = io.in_id
val last = io.in_last
val valid = io.in_valid
io.out_a := a
io.out_control.dataflow := dataflow
io.out_control.propagate := prop
io.out_control.shift := shift
io.out_id := id
io.out_last := last
io.out_valid := valid
mac_unit.io.in_a := a
val last_s = RegEnable(prop, valid)
val flip = last_s =/= prop
val shift_offset = Mux(flip, shift, 0.U)
// Which dataflow are we using?
val OUTPUT_STATIONARY = Dataflow.OS.id.U(1.W)
val WEIGHT_STATIONARY = Dataflow.WS.id.U(1.W)
// Is c1 being computed on, or propagated forward (in the output-stationary dataflow)?
val COMPUTE = 0.U(1.W)
val PROPAGATE = 1.U(1.W)
io.bad_dataflow := false.B
when ((df == Dataflow.OS).B || ((df == Dataflow.BOTH).B && dataflow === OUTPUT_STATIONARY)) {
when(prop === PROPAGATE) {
io.out_c := (c1 >> shift_offset).clippedToWidthOf(outputType)
io.out_b := b
mac_unit.io.in_b := b.asTypeOf(inputType)
mac_unit.io.in_c := c2
c2 := mac_unit.io.out_d
c1 := d.withWidthOf(cType)
}.otherwise {
io.out_c := (c2 >> shift_offset).clippedToWidthOf(outputType)
io.out_b := b
mac_unit.io.in_b := b.asTypeOf(inputType)
mac_unit.io.in_c := c1
c1 := mac_unit.io.out_d
c2 := d.withWidthOf(cType)
}
}.elsewhen ((df == Dataflow.WS).B || ((df == Dataflow.BOTH).B && dataflow === WEIGHT_STATIONARY)) {
when(prop === PROPAGATE) {
io.out_c := c1
mac_unit.io.in_b := c2.asTypeOf(inputType)
mac_unit.io.in_c := b
io.out_b := mac_unit.io.out_d
c1 := d
}.otherwise {
io.out_c := c2
mac_unit.io.in_b := c1.asTypeOf(inputType)
mac_unit.io.in_c := b
io.out_b := mac_unit.io.out_d
c2 := d
}
}.otherwise {
io.bad_dataflow := true.B
//assert(false.B, "unknown dataflow")
io.out_c := DontCare
io.out_b := DontCare
mac_unit.io.in_b := b.asTypeOf(inputType)
mac_unit.io.in_c := c2
}
when (!valid) {
c1 := c1
c2 := c2
mac_unit.io.in_b := DontCare
mac_unit.io.in_c := DontCare
}
}
File Arithmetic.scala:
// A simple type class for Chisel datatypes that can add and multiply. To add your own type, simply create your own:
// implicit MyTypeArithmetic extends Arithmetic[MyType] { ... }
package gemmini
import chisel3._
import chisel3.util._
import hardfloat._
// Bundles that represent the raw bits of custom datatypes
case class Float(expWidth: Int, sigWidth: Int) extends Bundle {
val bits = UInt((expWidth + sigWidth).W)
val bias: Int = (1 << (expWidth-1)) - 1
}
case class DummySInt(w: Int) extends Bundle {
val bits = UInt(w.W)
def dontCare: DummySInt = {
val o = Wire(new DummySInt(w))
o.bits := 0.U
o
}
}
// The Arithmetic typeclass which implements various arithmetic operations on custom datatypes
abstract class Arithmetic[T <: Data] {
implicit def cast(t: T): ArithmeticOps[T]
}
abstract class ArithmeticOps[T <: Data](self: T) {
def *(t: T): T
def mac(m1: T, m2: T): T // Returns (m1 * m2 + self)
def +(t: T): T
def -(t: T): T
def >>(u: UInt): T // This is a rounding shift! Rounds away from 0
def >(t: T): Bool
def identity: T
def withWidthOf(t: T): T
def clippedToWidthOf(t: T): T // Like "withWidthOf", except that it saturates
def relu: T
def zero: T
def minimum: T
// Optional parameters, which only need to be defined if you want to enable various optimizations for transformers
def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[T])] = None
def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[T])] = None
def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = None
def mult_with_reciprocal[U <: Data](reciprocal: U) = self
}
object Arithmetic {
implicit object UIntArithmetic extends Arithmetic[UInt] {
override implicit def cast(self: UInt) = new ArithmeticOps(self) {
override def *(t: UInt) = self * t
override def mac(m1: UInt, m2: UInt) = m1 * m2 + self
override def +(t: UInt) = self + t
override def -(t: UInt) = self - t
override def >>(u: UInt) = {
// The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm
// TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here?
val point_five = Mux(u === 0.U, 0.U, self(u - 1.U))
val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U
val ones_digit = self(u)
val r = point_five & (zeros | ones_digit)
(self >> u).asUInt + r
}
override def >(t: UInt): Bool = self > t
override def withWidthOf(t: UInt) = self.asTypeOf(t)
override def clippedToWidthOf(t: UInt) = {
val sat = ((1 << (t.getWidth-1))-1).U
Mux(self > sat, sat, self)(t.getWidth-1, 0)
}
override def relu: UInt = self
override def zero: UInt = 0.U
override def identity: UInt = 1.U
override def minimum: UInt = 0.U
}
}
implicit object SIntArithmetic extends Arithmetic[SInt] {
override implicit def cast(self: SInt) = new ArithmeticOps(self) {
override def *(t: SInt) = self * t
override def mac(m1: SInt, m2: SInt) = m1 * m2 + self
override def +(t: SInt) = self + t
override def -(t: SInt) = self - t
override def >>(u: UInt) = {
// The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm
// TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here?
val point_five = Mux(u === 0.U, 0.U, self(u - 1.U))
val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U
val ones_digit = self(u)
val r = (point_five & (zeros | ones_digit)).asBool
(self >> u).asSInt + Mux(r, 1.S, 0.S)
}
override def >(t: SInt): Bool = self > t
override def withWidthOf(t: SInt) = {
if (self.getWidth >= t.getWidth)
self(t.getWidth-1, 0).asSInt
else {
val sign_bits = t.getWidth - self.getWidth
val sign = self(self.getWidth-1)
Cat(Cat(Seq.fill(sign_bits)(sign)), self).asTypeOf(t)
}
}
override def clippedToWidthOf(t: SInt): SInt = {
val maxsat = ((1 << (t.getWidth-1))-1).S
val minsat = (-(1 << (t.getWidth-1))).S
MuxCase(self, Seq((self > maxsat) -> maxsat, (self < minsat) -> minsat))(t.getWidth-1, 0).asSInt
}
override def relu: SInt = Mux(self >= 0.S, self, 0.S)
override def zero: SInt = 0.S
override def identity: SInt = 1.S
override def minimum: SInt = (-(1 << (self.getWidth-1))).S
override def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = {
// TODO this uses a floating point divider, but we should use an integer divider instead
val input = Wire(Decoupled(denom_t.cloneType))
val output = Wire(Decoupled(self.cloneType))
// We translate our integer to floating-point form so that we can use the hardfloat divider
val expWidth = log2Up(self.getWidth) + 1
val sigWidth = self.getWidth
def sin_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def uin_to_float(x: UInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := false.B
in_to_rec_fn.io.in := x
in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def float_to_in(x: UInt) = {
val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth))
rec_fn_to_in.io.signedOut := true.B
rec_fn_to_in.io.in := x
rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
rec_fn_to_in.io.out.asSInt
}
val self_rec = sin_to_float(self)
val denom_rec = uin_to_float(input.bits)
// Instantiate the hardloat divider
val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options))
input.ready := divider.io.inReady
divider.io.inValid := input.valid
divider.io.sqrtOp := false.B
divider.io.a := self_rec
divider.io.b := denom_rec
divider.io.roundingMode := consts.round_minMag
divider.io.detectTininess := consts.tininess_afterRounding
output.valid := divider.io.outValid_div
output.bits := float_to_in(divider.io.out)
assert(!output.valid || output.ready)
Some((input, output))
}
override def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = {
// TODO this uses a floating point divider, but we should use an integer divider instead
val input = Wire(Decoupled(UInt(0.W)))
val output = Wire(Decoupled(self.cloneType))
input.bits := DontCare
// We translate our integer to floating-point form so that we can use the hardfloat divider
val expWidth = log2Up(self.getWidth) + 1
val sigWidth = self.getWidth
def in_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def float_to_in(x: UInt) = {
val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth))
rec_fn_to_in.io.signedOut := true.B
rec_fn_to_in.io.in := x
rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
rec_fn_to_in.io.out.asSInt
}
val self_rec = in_to_float(self)
// Instantiate the hardloat sqrt
val sqrter = Module(new DivSqrtRecFN_small(expWidth, sigWidth, 0))
input.ready := sqrter.io.inReady
sqrter.io.inValid := input.valid
sqrter.io.sqrtOp := true.B
sqrter.io.a := self_rec
sqrter.io.b := DontCare
sqrter.io.roundingMode := consts.round_minMag
sqrter.io.detectTininess := consts.tininess_afterRounding
output.valid := sqrter.io.outValid_sqrt
output.bits := float_to_in(sqrter.io.out)
assert(!output.valid || output.ready)
Some((input, output))
}
override def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = u match {
case Float(expWidth, sigWidth) =>
val input = Wire(Decoupled(UInt(0.W)))
val output = Wire(Decoupled(u.cloneType))
input.bits := DontCare
// We translate our integer to floating-point form so that we can use the hardfloat divider
def in_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
val self_rec = in_to_float(self)
val one_rec = in_to_float(1.S)
// Instantiate the hardloat divider
val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options))
input.ready := divider.io.inReady
divider.io.inValid := input.valid
divider.io.sqrtOp := false.B
divider.io.a := one_rec
divider.io.b := self_rec
divider.io.roundingMode := consts.round_near_even
divider.io.detectTininess := consts.tininess_afterRounding
output.valid := divider.io.outValid_div
output.bits := fNFromRecFN(expWidth, sigWidth, divider.io.out).asTypeOf(u)
assert(!output.valid || output.ready)
Some((input, output))
case _ => None
}
override def mult_with_reciprocal[U <: Data](reciprocal: U): SInt = reciprocal match {
case recip @ Float(expWidth, sigWidth) =>
def in_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def float_to_in(x: UInt) = {
val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth))
rec_fn_to_in.io.signedOut := true.B
rec_fn_to_in.io.in := x
rec_fn_to_in.io.roundingMode := consts.round_minMag
rec_fn_to_in.io.out.asSInt
}
val self_rec = in_to_float(self)
val reciprocal_rec = recFNFromFN(expWidth, sigWidth, recip.bits)
// Instantiate the hardloat divider
val muladder = Module(new MulRecFN(expWidth, sigWidth))
muladder.io.roundingMode := consts.round_near_even
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := self_rec
muladder.io.b := reciprocal_rec
float_to_in(muladder.io.out)
case _ => self
}
}
}
implicit object FloatArithmetic extends Arithmetic[Float] {
// TODO Floating point arithmetic currently switches between recoded and standard formats for every operation. However, it should stay in the recoded format as it travels through the systolic array
override implicit def cast(self: Float): ArithmeticOps[Float] = new ArithmeticOps(self) {
override def *(t: Float): Float = {
val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth))
t_resizer.io.in := t_rec
t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
t_resizer.io.detectTininess := consts.tininess_afterRounding
val t_rec_resized = t_resizer.io.out
val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth))
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := self_rec
muladder.io.b := t_rec_resized
val out = Wire(Float(self.expWidth, self.sigWidth))
out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
out
}
override def mac(m1: Float, m2: Float): Float = {
// Recode all operands
val m1_rec = recFNFromFN(m1.expWidth, m1.sigWidth, m1.bits)
val m2_rec = recFNFromFN(m2.expWidth, m2.sigWidth, m2.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Resize m1 to self's width
val m1_resizer = Module(new RecFNToRecFN(m1.expWidth, m1.sigWidth, self.expWidth, self.sigWidth))
m1_resizer.io.in := m1_rec
m1_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
m1_resizer.io.detectTininess := consts.tininess_afterRounding
val m1_rec_resized = m1_resizer.io.out
// Resize m2 to self's width
val m2_resizer = Module(new RecFNToRecFN(m2.expWidth, m2.sigWidth, self.expWidth, self.sigWidth))
m2_resizer.io.in := m2_rec
m2_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
m2_resizer.io.detectTininess := consts.tininess_afterRounding
val m2_rec_resized = m2_resizer.io.out
// Perform multiply-add
val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth))
muladder.io.op := 0.U
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := m1_rec_resized
muladder.io.b := m2_rec_resized
muladder.io.c := self_rec
// Convert result to standard format // TODO remove these intermediate recodings
val out = Wire(Float(self.expWidth, self.sigWidth))
out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
out
}
override def +(t: Float): Float = {
require(self.getWidth >= t.getWidth) // This just makes it easier to write the resizing code
// Recode all operands
val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Generate 1 as a float
val in_to_rec_fn = Module(new INToRecFN(1, self.expWidth, self.sigWidth))
in_to_rec_fn.io.signedIn := false.B
in_to_rec_fn.io.in := 1.U
in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
val one_rec = in_to_rec_fn.io.out
// Resize t
val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth))
t_resizer.io.in := t_rec
t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
t_resizer.io.detectTininess := consts.tininess_afterRounding
val t_rec_resized = t_resizer.io.out
// Perform addition
val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth))
muladder.io.op := 0.U
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := t_rec_resized
muladder.io.b := one_rec
muladder.io.c := self_rec
val result = Wire(Float(self.expWidth, self.sigWidth))
result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
result
}
override def -(t: Float): Float = {
val t_sgn = t.bits(t.getWidth-1)
val neg_t = Cat(~t_sgn, t.bits(t.getWidth-2,0)).asTypeOf(t)
self + neg_t
}
override def >>(u: UInt): Float = {
// Recode self
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Get 2^(-u) as a recoded float
val shift_exp = Wire(UInt(self.expWidth.W))
shift_exp := self.bias.U - u
val shift_fn = Cat(0.U(1.W), shift_exp, 0.U((self.sigWidth-1).W))
val shift_rec = recFNFromFN(self.expWidth, self.sigWidth, shift_fn)
assert(shift_exp =/= 0.U, "scaling by denormalized numbers is not currently supported")
// Multiply self and 2^(-u)
val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth))
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := self_rec
muladder.io.b := shift_rec
val result = Wire(Float(self.expWidth, self.sigWidth))
result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
result
}
override def >(t: Float): Bool = {
// Recode all operands
val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Resize t to self's width
val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth))
t_resizer.io.in := t_rec
t_resizer.io.roundingMode := consts.round_near_even
t_resizer.io.detectTininess := consts.tininess_afterRounding
val t_rec_resized = t_resizer.io.out
val comparator = Module(new CompareRecFN(self.expWidth, self.sigWidth))
comparator.io.a := self_rec
comparator.io.b := t_rec_resized
comparator.io.signaling := false.B
comparator.io.gt
}
override def withWidthOf(t: Float): Float = {
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth))
resizer.io.in := self_rec
resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
resizer.io.detectTininess := consts.tininess_afterRounding
val result = Wire(Float(t.expWidth, t.sigWidth))
result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out)
result
}
override def clippedToWidthOf(t: Float): Float = {
// TODO check for overflow. Right now, we just assume that overflow doesn't happen
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth))
resizer.io.in := self_rec
resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
resizer.io.detectTininess := consts.tininess_afterRounding
val result = Wire(Float(t.expWidth, t.sigWidth))
result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out)
result
}
override def relu: Float = {
val raw = rawFloatFromFN(self.expWidth, self.sigWidth, self.bits)
val result = Wire(Float(self.expWidth, self.sigWidth))
result.bits := Mux(!raw.isZero && raw.sign, 0.U, self.bits)
result
}
override def zero: Float = 0.U.asTypeOf(self)
override def identity: Float = Cat(0.U(2.W), ~(0.U((self.expWidth-1).W)), 0.U((self.sigWidth-1).W)).asTypeOf(self)
override def minimum: Float = Cat(1.U, ~(0.U(self.expWidth.W)), 0.U((self.sigWidth-1).W)).asTypeOf(self)
}
}
implicit object DummySIntArithmetic extends Arithmetic[DummySInt] {
override implicit def cast(self: DummySInt) = new ArithmeticOps(self) {
override def *(t: DummySInt) = self.dontCare
override def mac(m1: DummySInt, m2: DummySInt) = self.dontCare
override def +(t: DummySInt) = self.dontCare
override def -(t: DummySInt) = self.dontCare
override def >>(t: UInt) = self.dontCare
override def >(t: DummySInt): Bool = false.B
override def identity = self.dontCare
override def withWidthOf(t: DummySInt) = self.dontCare
override def clippedToWidthOf(t: DummySInt) = self.dontCare
override def relu = self.dontCare
override def zero = self.dontCare
override def minimum: DummySInt = self.dontCare
}
}
}
| module MacUnit_147( // @[PE.scala:14:7]
input clock, // @[PE.scala:14:7]
input reset, // @[PE.scala:14:7]
input [7:0] io_in_a, // @[PE.scala:16:14]
input [7:0] io_in_b, // @[PE.scala:16:14]
input [19:0] io_in_c, // @[PE.scala:16:14]
output [19:0] io_out_d // @[PE.scala:16:14]
);
wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:14:7]
wire [7:0] io_in_b_0 = io_in_b; // @[PE.scala:14:7]
wire [19:0] io_in_c_0 = io_in_c; // @[PE.scala:14:7]
wire [19:0] _io_out_d_T_3; // @[Arithmetic.scala:93:54]
wire [19:0] io_out_d_0; // @[PE.scala:14:7]
wire [15:0] _io_out_d_T = {{8{io_in_a_0[7]}}, io_in_a_0} * {{8{io_in_b_0[7]}}, io_in_b_0}; // @[PE.scala:14:7]
wire [20:0] _io_out_d_T_1 = {{5{_io_out_d_T[15]}}, _io_out_d_T} + {io_in_c_0[19], io_in_c_0}; // @[PE.scala:14:7]
wire [19:0] _io_out_d_T_2 = _io_out_d_T_1[19:0]; // @[Arithmetic.scala:93:54]
assign _io_out_d_T_3 = _io_out_d_T_2; // @[Arithmetic.scala:93:54]
assign io_out_d_0 = _io_out_d_T_3; // @[PE.scala:14:7]
assign io_out_d = io_out_d_0; // @[PE.scala:14:7]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File ShiftReg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
// Similar to the Chisel ShiftRegister but allows the user to suggest a
// name to the registers that get instantiated, and
// to provide a reset value.
object ShiftRegInit {
def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T =
(0 until n).foldRight(in) {
case (i, next) => {
val r = RegNext(next, init)
name.foreach { na => r.suggestName(s"${na}_${i}") }
r
}
}
}
/** These wrap behavioral
* shift registers into specific modules to allow for
* backend flows to replace or constrain
* them properly when used for CDC synchronization,
* rather than buffering.
*
* The different types vary in their reset behavior:
* AsyncResetShiftReg -- Asynchronously reset register array
* A W(width) x D(depth) sized array is constructed from D instantiations of a
* W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg,
* but only used for timing applications
*/
abstract class AbstractPipelineReg(w: Int = 1) extends Module {
val io = IO(new Bundle {
val d = Input(UInt(w.W))
val q = Output(UInt(w.W))
}
)
}
object AbstractPipelineReg {
def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = {
val chain = Module(gen)
name.foreach{ chain.suggestName(_) }
chain.io.d := in.asUInt
chain.io.q.asTypeOf(in)
}
}
class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) {
require(depth > 0, "Depth must be greater than 0.")
override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}"
val chain = List.tabulate(depth) { i =>
Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}")
}
chain.last.io.d := io.d
chain.last.io.en := true.B
(chain.init zip chain.tail).foreach { case (sink, source) =>
sink.io.d := source.io.q
sink.io.en := true.B
}
io.q := chain.head.io.q
}
object AsyncResetShiftReg {
def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T =
AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name)
def apply [T <: Data](in: T, depth: Int, name: Option[String]): T =
apply(in, depth, 0, name)
def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T =
apply(in, depth, init.litValue.toInt, name)
def apply [T <: Data](in: T, depth: Int, init: T): T =
apply (in, depth, init.litValue.toInt, None)
}
File SynchronizerReg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util.{RegEnable, Cat}
/** These wrap behavioral
* shift and next registers into specific modules to allow for
* backend flows to replace or constrain
* them properly when used for CDC synchronization,
* rather than buffering.
*
*
* These are built up of *ResetSynchronizerPrimitiveShiftReg,
* intended to be replaced by the integrator's metastable flops chains or replaced
* at this level if they have a multi-bit wide synchronizer primitive.
* The different types vary in their reset behavior:
* NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin
* AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep
* 1-bit-wide shift registers.
* SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg
*
* [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference.
*
* ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross
* Clock Domains.
*/
object SynchronizerResetType extends Enumeration {
val NonSync, Inferred, Sync, Async = Value
}
// Note: this should not be used directly.
// Use the companion object to generate this with the correct reset type mixin.
private class SynchronizerPrimitiveShiftReg(
sync: Int,
init: Boolean,
resetType: SynchronizerResetType.Value)
extends AbstractPipelineReg(1) {
val initInt = if (init) 1 else 0
val initPostfix = resetType match {
case SynchronizerResetType.NonSync => ""
case _ => s"_i${initInt}"
}
override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}"
val chain = List.tabulate(sync) { i =>
val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B)
reg.suggestName(s"sync_$i")
}
chain.last := io.d.asBool
(chain.init zip chain.tail).foreach { case (sink, source) =>
sink := source
}
io.q := chain.head.asUInt
}
private object SynchronizerPrimitiveShiftReg {
def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = {
val gen: () => SynchronizerPrimitiveShiftReg = resetType match {
case SynchronizerResetType.NonSync =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType)
case SynchronizerResetType.Async =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset
case SynchronizerResetType.Sync =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset
case SynchronizerResetType.Inferred =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType)
}
AbstractPipelineReg(gen(), in)
}
}
// Note: This module may end up with a non-AsyncReset type reset.
// But the Primitives within will always have AsyncReset type.
class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int)
extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
withReset(reset.asAsyncReset){
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async)
}
}
io.q := Cat(output.reverse)
}
object AsyncResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
// Note: This module may end up with a non-Bool type reset.
// But the Primitives within will always have Bool reset type.
@deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2")
class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
withReset(reset.asBool){
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync)
}
}
io.q := Cat(output.reverse)
}
object SyncResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred)
}
io.q := Cat(output.reverse)
}
object ResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}"
val output = Seq.tabulate(w) { i =>
SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync)
}
io.q := Cat(output.reverse)
}
object SynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T =
if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, None)
def apply [T <: Data](in: T): T =
apply (in, 3, None)
}
class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module {
override def desiredName = s"ClockCrossingReg_w${w}"
val io = IO(new Bundle{
val d = Input(UInt(w.W))
val q = Output(UInt(w.W))
val en = Input(Bool())
})
val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en)
io.q := cdc_reg
}
object ClockCrossingReg {
def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = {
val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit))
name.foreach{ cdc_reg.suggestName(_) }
cdc_reg.io.d := in.asUInt
cdc_reg.io.en := en
cdc_reg.io.q.asTypeOf(in)
}
}
| module AsyncResetSynchronizerShiftReg_w1_d3_i0_136( // @[SynchronizerReg.scala:80:7]
input clock, // @[SynchronizerReg.scala:80:7]
input reset, // @[SynchronizerReg.scala:80:7]
input io_d, // @[ShiftReg.scala:36:14]
output io_q // @[ShiftReg.scala:36:14]
);
wire io_d_0 = io_d; // @[SynchronizerReg.scala:80:7]
wire _output_T = reset; // @[SynchronizerReg.scala:86:21]
wire _output_T_1 = io_d_0; // @[SynchronizerReg.scala:80:7, :87:41]
wire output_0; // @[ShiftReg.scala:48:24]
wire io_q_0; // @[SynchronizerReg.scala:80:7]
assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7]
AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_232 output_chain ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (_output_T), // @[SynchronizerReg.scala:86:21]
.io_d (_output_T_1), // @[SynchronizerReg.scala:87:41]
.io_q (output_0)
); // @[ShiftReg.scala:45:23]
assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File package.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip
import chisel3._
import chisel3.util._
import scala.math.min
import scala.collection.{immutable, mutable}
package object util {
implicit class UnzippableOption[S, T](val x: Option[(S, T)]) {
def unzip = (x.map(_._1), x.map(_._2))
}
implicit class UIntIsOneOf(private val x: UInt) extends AnyVal {
def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR
def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq)
}
implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal {
/** Like Vec.apply(idx), but tolerates indices of mismatched width */
def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0))
}
implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal {
def apply(idx: UInt): T = {
if (x.size <= 1) {
x.head
} else if (!isPow2(x.size)) {
// For non-power-of-2 seqs, reflect elements to simplify decoder
(x ++ x.takeRight(x.size & -x.size)).toSeq(idx)
} else {
// Ignore MSBs of idx
val truncIdx =
if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx
else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0)
x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) }
}
}
def extract(idx: UInt): T = VecInit(x).extract(idx)
def asUInt: UInt = Cat(x.map(_.asUInt).reverse)
def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n)
def rotate(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n)
def rotateRight(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
}
// allow bitwise ops on Seq[Bool] just like UInt
implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal {
def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b }
def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b }
def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b }
def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x
def >> (n: Int): Seq[Bool] = x drop n
def unary_~ : Seq[Bool] = x.map(!_)
def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_)
def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_)
def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_)
private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B)
}
implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal {
def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable))
def getElements: Seq[Element] = x match {
case e: Element => Seq(e)
case a: Aggregate => a.getElements.flatMap(_.getElements)
}
}
/** Any Data subtype that has a Bool member named valid. */
type DataCanBeValid = Data { val valid: Bool }
implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal {
def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable)
}
implicit class StringToAugmentedString(private val x: String) extends AnyVal {
/** converts from camel case to to underscores, also removing all spaces */
def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") {
case (acc, c) if c.isUpper => acc + "_" + c.toLower
case (acc, c) if c == ' ' => acc
case (acc, c) => acc + c
}
/** converts spaces or underscores to hyphens, also lowering case */
def kebab: String = x.toLowerCase map {
case ' ' => '-'
case '_' => '-'
case c => c
}
def named(name: Option[String]): String = {
x + name.map("_named_" + _ ).getOrElse("_with_no_name")
}
def named(name: String): String = named(Some(name))
}
implicit def uintToBitPat(x: UInt): BitPat = BitPat(x)
implicit def wcToUInt(c: WideCounter): UInt = c.value
implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal {
def sextTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x)
}
def padTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(0.U((n - x.getWidth).W), x)
}
// shifts left by n if n >= 0, or right by -n if n < 0
def << (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << n(w-1, 0)
Mux(n(w), shifted >> (1 << w), shifted)
}
// shifts right by n if n >= 0, or left by -n if n < 0
def >> (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << (1 << w) >> n(w-1, 0)
Mux(n(w), shifted, shifted >> (1 << w))
}
// Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts
def extract(hi: Int, lo: Int): UInt = {
require(hi >= lo-1)
if (hi == lo-1) 0.U
else x(hi, lo)
}
// Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts
def extractOption(hi: Int, lo: Int): Option[UInt] = {
require(hi >= lo-1)
if (hi == lo-1) None
else Some(x(hi, lo))
}
// like x & ~y, but first truncate or zero-extend y to x's width
def andNot(y: UInt): UInt = x & ~(y | (x & 0.U))
def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n)
def rotateRight(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r))
}
}
def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n))
def rotateLeft(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r))
}
}
// compute (this + y) % n, given (this < n) and (y < n)
def addWrap(y: UInt, n: Int): UInt = {
val z = x +& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0)
}
// compute (this - y) % n, given (this < n) and (y < n)
def subWrap(y: UInt, n: Int): UInt = {
val z = x -& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0)
}
def grouped(width: Int): Seq[UInt] =
(0 until x.getWidth by width).map(base => x(base + width - 1, base))
def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds
def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x)
// Like >=, but prevents x-prop for ('x >= 0)
def >== (y: UInt): Bool = x >= y || y === 0.U
}
implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal {
def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y)
def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y)
}
implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal {
def toInt: Int = if (x) 1 else 0
// this one's snagged from scalaz
def option[T](z: => T): Option[T] = if (x) Some(z) else None
}
implicit class IntToAugmentedInt(private val x: Int) extends AnyVal {
// exact log2
def log2: Int = {
require(isPow2(x))
log2Ceil(x)
}
}
def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x)
def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x))
def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0)
def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1)
def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None
// Fill 1s from low bits to high bits
def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth)
def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0))
helper(1, x)(width-1, 0)
}
// Fill 1s form high bits to low bits
def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth)
def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x >> s))
helper(1, x)(width-1, 0)
}
def OptimizationBarrier[T <: Data](in: T): T = {
val barrier = Module(new Module {
val io = IO(new Bundle {
val x = Input(chiselTypeOf(in))
val y = Output(chiselTypeOf(in))
})
io.y := io.x
override def desiredName = s"OptimizationBarrier_${in.typeName}"
})
barrier.io.x := in
barrier.io.y
}
/** Similar to Seq.groupBy except this returns a Seq instead of a Map
* Useful for deterministic code generation
*/
def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = {
val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]]
for (x <- xs) {
val key = f(x)
val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A])
l += x
}
map.view.map({ case (k, vs) => k -> vs.toList }).toList
}
def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match {
case 1 => List.fill(n)(in.head)
case x if x == n => in
case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in")
}
// HeterogeneousBag moved to standalond diplomacy
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts)
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag
}
File PMP.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.rocket
import chisel3._
import chisel3.util.{Cat, log2Ceil}
import org.chipsalliance.cde.config._
import freechips.rocketchip.tile._
import freechips.rocketchip.util._
class PMPConfig extends Bundle {
val l = Bool()
val res = UInt(2.W)
val a = UInt(2.W)
val x = Bool()
val w = Bool()
val r = Bool()
}
object PMP {
def lgAlign = 2
def apply(reg: PMPReg): PMP = {
val pmp = Wire(new PMP()(reg.p))
pmp.cfg := reg.cfg
pmp.addr := reg.addr
pmp.mask := pmp.computeMask
pmp
}
}
class PMPReg(implicit p: Parameters) extends CoreBundle()(p) {
val cfg = new PMPConfig
val addr = UInt((paddrBits - PMP.lgAlign).W)
def reset(): Unit = {
cfg.a := 0.U
cfg.l := 0.U
}
def readAddr = if (pmpGranularity.log2 == PMP.lgAlign) addr else {
val mask = ((BigInt(1) << (pmpGranularity.log2 - PMP.lgAlign)) - 1).U
Mux(napot, addr | (mask >> 1), ~(~addr | mask))
}
def napot = cfg.a(1)
def torNotNAPOT = cfg.a(0)
def tor = !napot && torNotNAPOT
def cfgLocked = cfg.l
def addrLocked(next: PMPReg) = cfgLocked || next.cfgLocked && next.tor
}
class PMP(implicit p: Parameters) extends PMPReg {
val mask = UInt(paddrBits.W)
import PMP._
def computeMask = {
val base = Cat(addr, cfg.a(0)) | ((pmpGranularity - 1).U >> lgAlign)
Cat(base & ~(base + 1.U), ((1 << lgAlign) - 1).U)
}
private def comparand = ~(~(addr << lgAlign) | (pmpGranularity - 1).U)
private def pow2Match(x: UInt, lgSize: UInt, lgMaxSize: Int) = {
def eval(a: UInt, b: UInt, m: UInt) = ((a ^ b) & ~m) === 0.U
if (lgMaxSize <= pmpGranularity.log2) {
eval(x, comparand, mask)
} else {
// break up the circuit; the MSB part will be CSE'd
val lsbMask = mask | UIntToOH1(lgSize, lgMaxSize)
val msbMatch = eval(x >> lgMaxSize, comparand >> lgMaxSize, mask >> lgMaxSize)
val lsbMatch = eval(x(lgMaxSize-1, 0), comparand(lgMaxSize-1, 0), lsbMask(lgMaxSize-1, 0))
msbMatch && lsbMatch
}
}
private def boundMatch(x: UInt, lsbMask: UInt, lgMaxSize: Int) = {
if (lgMaxSize <= pmpGranularity.log2) {
x < comparand
} else {
// break up the circuit; the MSB part will be CSE'd
val msbsLess = (x >> lgMaxSize) < (comparand >> lgMaxSize)
val msbsEqual = ((x >> lgMaxSize) ^ (comparand >> lgMaxSize)) === 0.U
val lsbsLess = (x(lgMaxSize-1, 0) | lsbMask) < comparand(lgMaxSize-1, 0)
msbsLess || (msbsEqual && lsbsLess)
}
}
private def lowerBoundMatch(x: UInt, lgSize: UInt, lgMaxSize: Int) =
!boundMatch(x, UIntToOH1(lgSize, lgMaxSize), lgMaxSize)
private def upperBoundMatch(x: UInt, lgMaxSize: Int) =
boundMatch(x, 0.U, lgMaxSize)
private def rangeMatch(x: UInt, lgSize: UInt, lgMaxSize: Int, prev: PMP) =
prev.lowerBoundMatch(x, lgSize, lgMaxSize) && upperBoundMatch(x, lgMaxSize)
private def pow2Homogeneous(x: UInt, pgLevel: UInt) = {
val maskHomogeneous = pgLevelMap { idxBits => if (idxBits > paddrBits) false.B else mask(idxBits - 1) } (pgLevel)
maskHomogeneous || (pgLevelMap { idxBits => ((x ^ comparand) >> idxBits) =/= 0.U } (pgLevel))
}
private def pgLevelMap[T](f: Int => T) = (0 until pgLevels).map { i =>
f(pgIdxBits + (pgLevels - 1 - i) * pgLevelBits)
}
private def rangeHomogeneous(x: UInt, pgLevel: UInt, prev: PMP) = {
val beginsAfterLower = !(x < prev.comparand)
val beginsAfterUpper = !(x < comparand)
val pgMask = pgLevelMap { idxBits => (((BigInt(1) << paddrBits) - (BigInt(1) << idxBits)) max 0).U } (pgLevel)
val endsBeforeLower = (x & pgMask) < (prev.comparand & pgMask)
val endsBeforeUpper = (x & pgMask) < (comparand & pgMask)
endsBeforeLower || beginsAfterUpper || (beginsAfterLower && endsBeforeUpper)
}
// returns whether this PMP completely contains, or contains none of, a page
def homogeneous(x: UInt, pgLevel: UInt, prev: PMP): Bool =
Mux(napot, pow2Homogeneous(x, pgLevel), !torNotNAPOT || rangeHomogeneous(x, pgLevel, prev))
// returns whether this matching PMP fully contains the access
def aligned(x: UInt, lgSize: UInt, lgMaxSize: Int, prev: PMP): Bool = if (lgMaxSize <= pmpGranularity.log2) true.B else {
val lsbMask = UIntToOH1(lgSize, lgMaxSize)
val straddlesLowerBound = ((x >> lgMaxSize) ^ (prev.comparand >> lgMaxSize)) === 0.U && (prev.comparand(lgMaxSize-1, 0) & ~x(lgMaxSize-1, 0)) =/= 0.U
val straddlesUpperBound = ((x >> lgMaxSize) ^ (comparand >> lgMaxSize)) === 0.U && (comparand(lgMaxSize-1, 0) & (x(lgMaxSize-1, 0) | lsbMask)) =/= 0.U
val rangeAligned = !(straddlesLowerBound || straddlesUpperBound)
val pow2Aligned = (lsbMask & ~mask(lgMaxSize-1, 0)) === 0.U
Mux(napot, pow2Aligned, rangeAligned)
}
// returns whether this PMP matches at least one byte of the access
def hit(x: UInt, lgSize: UInt, lgMaxSize: Int, prev: PMP): Bool =
Mux(napot, pow2Match(x, lgSize, lgMaxSize), torNotNAPOT && rangeMatch(x, lgSize, lgMaxSize, prev))
}
class PMPHomogeneityChecker(pmps: Seq[PMP])(implicit p: Parameters) {
def apply(addr: UInt, pgLevel: UInt): Bool = {
pmps.foldLeft((true.B, 0.U.asTypeOf(new PMP))) { case ((h, prev), pmp) =>
(h && pmp.homogeneous(addr, pgLevel, prev), pmp)
}._1
}
}
class PMPChecker(lgMaxSize: Int)(implicit val p: Parameters) extends Module
with HasCoreParameters {
override def desiredName = s"PMPChecker_s${lgMaxSize}"
val io = IO(new Bundle {
val prv = Input(UInt(PRV.SZ.W))
val pmp = Input(Vec(nPMPs, new PMP))
val addr = Input(UInt(paddrBits.W))
val size = Input(UInt(log2Ceil(lgMaxSize + 1).W))
val r = Output(Bool())
val w = Output(Bool())
val x = Output(Bool())
})
val default = if (io.pmp.isEmpty) true.B else io.prv > PRV.S.U
val pmp0 = WireInit(0.U.asTypeOf(new PMP))
pmp0.cfg.r := default
pmp0.cfg.w := default
pmp0.cfg.x := default
val res = (io.pmp zip (pmp0 +: io.pmp)).reverse.foldLeft(pmp0) { case (prev, (pmp, prevPMP)) =>
val hit = pmp.hit(io.addr, io.size, lgMaxSize, prevPMP)
val ignore = default && !pmp.cfg.l
val aligned = pmp.aligned(io.addr, io.size, lgMaxSize, prevPMP)
for ((name, idx) <- Seq("no", "TOR", if (pmpGranularity <= 4) "NA4" else "", "NAPOT").zipWithIndex; if name.nonEmpty)
property.cover(pmp.cfg.a === idx.U, s"The cfg access is set to ${name} access ", "Cover PMP access mode setting")
property.cover(pmp.cfg.l === 0x1.U, s"The cfg lock is set to high ", "Cover PMP lock mode setting")
// Not including Write and no Read permission as the combination is reserved
for ((name, idx) <- Seq("no", "RO", "", "RW", "X", "RX", "", "RWX").zipWithIndex; if name.nonEmpty)
property.cover((Cat(pmp.cfg.x, pmp.cfg.w, pmp.cfg.r) === idx.U), s"The permission is set to ${name} access ", "Cover PMP access permission setting")
for ((name, idx) <- Seq("", "TOR", if (pmpGranularity <= 4) "NA4" else "", "NAPOT").zipWithIndex; if name.nonEmpty) {
property.cover(!ignore && hit && aligned && pmp.cfg.a === idx.U, s"The access matches ${name} mode ", "Cover PMP access")
property.cover(pmp.cfg.l && hit && aligned && pmp.cfg.a === idx.U, s"The access matches ${name} mode with lock bit high", "Cover PMP access with lock bit")
}
val cur = WireInit(pmp)
cur.cfg.r := aligned && (pmp.cfg.r || ignore)
cur.cfg.w := aligned && (pmp.cfg.w || ignore)
cur.cfg.x := aligned && (pmp.cfg.x || ignore)
Mux(hit, cur, prev)
}
io.r := res.cfg.r
io.w := res.cfg.w
io.x := res.cfg.x
}
| module PMPChecker_s3_8( // @[PMP.scala:143:7]
input clock, // @[PMP.scala:143:7]
input reset, // @[PMP.scala:143:7]
input [1:0] io_prv, // @[PMP.scala:146:14]
input io_pmp_0_cfg_l, // @[PMP.scala:146:14]
input [1:0] io_pmp_0_cfg_a, // @[PMP.scala:146:14]
input io_pmp_0_cfg_x, // @[PMP.scala:146:14]
input io_pmp_0_cfg_w, // @[PMP.scala:146:14]
input io_pmp_0_cfg_r, // @[PMP.scala:146:14]
input [29:0] io_pmp_0_addr, // @[PMP.scala:146:14]
input [31:0] io_pmp_0_mask, // @[PMP.scala:146:14]
input io_pmp_1_cfg_l, // @[PMP.scala:146:14]
input [1:0] io_pmp_1_cfg_a, // @[PMP.scala:146:14]
input io_pmp_1_cfg_x, // @[PMP.scala:146:14]
input io_pmp_1_cfg_w, // @[PMP.scala:146:14]
input io_pmp_1_cfg_r, // @[PMP.scala:146:14]
input [29:0] io_pmp_1_addr, // @[PMP.scala:146:14]
input [31:0] io_pmp_1_mask, // @[PMP.scala:146:14]
input io_pmp_2_cfg_l, // @[PMP.scala:146:14]
input [1:0] io_pmp_2_cfg_a, // @[PMP.scala:146:14]
input io_pmp_2_cfg_x, // @[PMP.scala:146:14]
input io_pmp_2_cfg_w, // @[PMP.scala:146:14]
input io_pmp_2_cfg_r, // @[PMP.scala:146:14]
input [29:0] io_pmp_2_addr, // @[PMP.scala:146:14]
input [31:0] io_pmp_2_mask, // @[PMP.scala:146:14]
input io_pmp_3_cfg_l, // @[PMP.scala:146:14]
input [1:0] io_pmp_3_cfg_a, // @[PMP.scala:146:14]
input io_pmp_3_cfg_x, // @[PMP.scala:146:14]
input io_pmp_3_cfg_w, // @[PMP.scala:146:14]
input io_pmp_3_cfg_r, // @[PMP.scala:146:14]
input [29:0] io_pmp_3_addr, // @[PMP.scala:146:14]
input [31:0] io_pmp_3_mask, // @[PMP.scala:146:14]
input io_pmp_4_cfg_l, // @[PMP.scala:146:14]
input [1:0] io_pmp_4_cfg_a, // @[PMP.scala:146:14]
input io_pmp_4_cfg_x, // @[PMP.scala:146:14]
input io_pmp_4_cfg_w, // @[PMP.scala:146:14]
input io_pmp_4_cfg_r, // @[PMP.scala:146:14]
input [29:0] io_pmp_4_addr, // @[PMP.scala:146:14]
input [31:0] io_pmp_4_mask, // @[PMP.scala:146:14]
input io_pmp_5_cfg_l, // @[PMP.scala:146:14]
input [1:0] io_pmp_5_cfg_a, // @[PMP.scala:146:14]
input io_pmp_5_cfg_x, // @[PMP.scala:146:14]
input io_pmp_5_cfg_w, // @[PMP.scala:146:14]
input io_pmp_5_cfg_r, // @[PMP.scala:146:14]
input [29:0] io_pmp_5_addr, // @[PMP.scala:146:14]
input [31:0] io_pmp_5_mask, // @[PMP.scala:146:14]
input io_pmp_6_cfg_l, // @[PMP.scala:146:14]
input [1:0] io_pmp_6_cfg_a, // @[PMP.scala:146:14]
input io_pmp_6_cfg_x, // @[PMP.scala:146:14]
input io_pmp_6_cfg_w, // @[PMP.scala:146:14]
input io_pmp_6_cfg_r, // @[PMP.scala:146:14]
input [29:0] io_pmp_6_addr, // @[PMP.scala:146:14]
input [31:0] io_pmp_6_mask, // @[PMP.scala:146:14]
input io_pmp_7_cfg_l, // @[PMP.scala:146:14]
input [1:0] io_pmp_7_cfg_a, // @[PMP.scala:146:14]
input io_pmp_7_cfg_x, // @[PMP.scala:146:14]
input io_pmp_7_cfg_w, // @[PMP.scala:146:14]
input io_pmp_7_cfg_r, // @[PMP.scala:146:14]
input [29:0] io_pmp_7_addr, // @[PMP.scala:146:14]
input [31:0] io_pmp_7_mask, // @[PMP.scala:146:14]
input [31:0] io_addr, // @[PMP.scala:146:14]
input [1:0] io_size, // @[PMP.scala:146:14]
output io_r, // @[PMP.scala:146:14]
output io_w, // @[PMP.scala:146:14]
output io_x // @[PMP.scala:146:14]
);
wire [1:0] io_prv_0 = io_prv; // @[PMP.scala:143:7]
wire io_pmp_0_cfg_l_0 = io_pmp_0_cfg_l; // @[PMP.scala:143:7]
wire [1:0] io_pmp_0_cfg_a_0 = io_pmp_0_cfg_a; // @[PMP.scala:143:7]
wire io_pmp_0_cfg_x_0 = io_pmp_0_cfg_x; // @[PMP.scala:143:7]
wire io_pmp_0_cfg_w_0 = io_pmp_0_cfg_w; // @[PMP.scala:143:7]
wire io_pmp_0_cfg_r_0 = io_pmp_0_cfg_r; // @[PMP.scala:143:7]
wire [29:0] io_pmp_0_addr_0 = io_pmp_0_addr; // @[PMP.scala:143:7]
wire [31:0] io_pmp_0_mask_0 = io_pmp_0_mask; // @[PMP.scala:143:7]
wire io_pmp_1_cfg_l_0 = io_pmp_1_cfg_l; // @[PMP.scala:143:7]
wire [1:0] io_pmp_1_cfg_a_0 = io_pmp_1_cfg_a; // @[PMP.scala:143:7]
wire io_pmp_1_cfg_x_0 = io_pmp_1_cfg_x; // @[PMP.scala:143:7]
wire io_pmp_1_cfg_w_0 = io_pmp_1_cfg_w; // @[PMP.scala:143:7]
wire io_pmp_1_cfg_r_0 = io_pmp_1_cfg_r; // @[PMP.scala:143:7]
wire [29:0] io_pmp_1_addr_0 = io_pmp_1_addr; // @[PMP.scala:143:7]
wire [31:0] io_pmp_1_mask_0 = io_pmp_1_mask; // @[PMP.scala:143:7]
wire io_pmp_2_cfg_l_0 = io_pmp_2_cfg_l; // @[PMP.scala:143:7]
wire [1:0] io_pmp_2_cfg_a_0 = io_pmp_2_cfg_a; // @[PMP.scala:143:7]
wire io_pmp_2_cfg_x_0 = io_pmp_2_cfg_x; // @[PMP.scala:143:7]
wire io_pmp_2_cfg_w_0 = io_pmp_2_cfg_w; // @[PMP.scala:143:7]
wire io_pmp_2_cfg_r_0 = io_pmp_2_cfg_r; // @[PMP.scala:143:7]
wire [29:0] io_pmp_2_addr_0 = io_pmp_2_addr; // @[PMP.scala:143:7]
wire [31:0] io_pmp_2_mask_0 = io_pmp_2_mask; // @[PMP.scala:143:7]
wire io_pmp_3_cfg_l_0 = io_pmp_3_cfg_l; // @[PMP.scala:143:7]
wire [1:0] io_pmp_3_cfg_a_0 = io_pmp_3_cfg_a; // @[PMP.scala:143:7]
wire io_pmp_3_cfg_x_0 = io_pmp_3_cfg_x; // @[PMP.scala:143:7]
wire io_pmp_3_cfg_w_0 = io_pmp_3_cfg_w; // @[PMP.scala:143:7]
wire io_pmp_3_cfg_r_0 = io_pmp_3_cfg_r; // @[PMP.scala:143:7]
wire [29:0] io_pmp_3_addr_0 = io_pmp_3_addr; // @[PMP.scala:143:7]
wire [31:0] io_pmp_3_mask_0 = io_pmp_3_mask; // @[PMP.scala:143:7]
wire io_pmp_4_cfg_l_0 = io_pmp_4_cfg_l; // @[PMP.scala:143:7]
wire [1:0] io_pmp_4_cfg_a_0 = io_pmp_4_cfg_a; // @[PMP.scala:143:7]
wire io_pmp_4_cfg_x_0 = io_pmp_4_cfg_x; // @[PMP.scala:143:7]
wire io_pmp_4_cfg_w_0 = io_pmp_4_cfg_w; // @[PMP.scala:143:7]
wire io_pmp_4_cfg_r_0 = io_pmp_4_cfg_r; // @[PMP.scala:143:7]
wire [29:0] io_pmp_4_addr_0 = io_pmp_4_addr; // @[PMP.scala:143:7]
wire [31:0] io_pmp_4_mask_0 = io_pmp_4_mask; // @[PMP.scala:143:7]
wire io_pmp_5_cfg_l_0 = io_pmp_5_cfg_l; // @[PMP.scala:143:7]
wire [1:0] io_pmp_5_cfg_a_0 = io_pmp_5_cfg_a; // @[PMP.scala:143:7]
wire io_pmp_5_cfg_x_0 = io_pmp_5_cfg_x; // @[PMP.scala:143:7]
wire io_pmp_5_cfg_w_0 = io_pmp_5_cfg_w; // @[PMP.scala:143:7]
wire io_pmp_5_cfg_r_0 = io_pmp_5_cfg_r; // @[PMP.scala:143:7]
wire [29:0] io_pmp_5_addr_0 = io_pmp_5_addr; // @[PMP.scala:143:7]
wire [31:0] io_pmp_5_mask_0 = io_pmp_5_mask; // @[PMP.scala:143:7]
wire io_pmp_6_cfg_l_0 = io_pmp_6_cfg_l; // @[PMP.scala:143:7]
wire [1:0] io_pmp_6_cfg_a_0 = io_pmp_6_cfg_a; // @[PMP.scala:143:7]
wire io_pmp_6_cfg_x_0 = io_pmp_6_cfg_x; // @[PMP.scala:143:7]
wire io_pmp_6_cfg_w_0 = io_pmp_6_cfg_w; // @[PMP.scala:143:7]
wire io_pmp_6_cfg_r_0 = io_pmp_6_cfg_r; // @[PMP.scala:143:7]
wire [29:0] io_pmp_6_addr_0 = io_pmp_6_addr; // @[PMP.scala:143:7]
wire [31:0] io_pmp_6_mask_0 = io_pmp_6_mask; // @[PMP.scala:143:7]
wire io_pmp_7_cfg_l_0 = io_pmp_7_cfg_l; // @[PMP.scala:143:7]
wire [1:0] io_pmp_7_cfg_a_0 = io_pmp_7_cfg_a; // @[PMP.scala:143:7]
wire io_pmp_7_cfg_x_0 = io_pmp_7_cfg_x; // @[PMP.scala:143:7]
wire io_pmp_7_cfg_w_0 = io_pmp_7_cfg_w; // @[PMP.scala:143:7]
wire io_pmp_7_cfg_r_0 = io_pmp_7_cfg_r; // @[PMP.scala:143:7]
wire [29:0] io_pmp_7_addr_0 = io_pmp_7_addr; // @[PMP.scala:143:7]
wire [31:0] io_pmp_7_mask_0 = io_pmp_7_mask; // @[PMP.scala:143:7]
wire [31:0] io_addr_0 = io_addr; // @[PMP.scala:143:7]
wire [1:0] io_size_0 = io_size; // @[PMP.scala:143:7]
wire [29:0] _pmp0_WIRE_addr = 30'h0; // @[PMP.scala:157:35]
wire [29:0] pmp0_addr = 30'h0; // @[PMP.scala:157:22]
wire _res_hit_T_99 = 1'h1; // @[PMP.scala:88:5]
wire [28:0] _res_hit_msbsLess_T_89 = 29'h0; // @[PMP.scala:80:52, :81:54, :123:67]
wire [28:0] _res_hit_msbsEqual_T_103 = 29'h0; // @[PMP.scala:80:52, :81:54, :123:67]
wire [28:0] _res_aligned_straddlesLowerBound_T_124 = 29'h0; // @[PMP.scala:80:52, :81:54, :123:67]
wire [31:0] _res_hit_msbsLess_T_86 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbsLess_T_87 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbsEqual_T_100 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbsEqual_T_101 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_lsbsLess_T_101 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_lsbsLess_T_102 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_aligned_straddlesLowerBound_T_121 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_aligned_straddlesLowerBound_T_122 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_aligned_straddlesLowerBound_T_128 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_aligned_straddlesLowerBound_T_129 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}]
wire [31:0] _pmp0_WIRE_mask = 32'h0; // @[PMP.scala:157:35]
wire [31:0] pmp0_mask = 32'h0; // @[PMP.scala:157:22]
wire [31:0] _res_hit_msbsLess_T_85 = 32'h0; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbsLess_T_88 = 32'h0; // @[PMP.scala:60:27]
wire [31:0] _res_hit_msbsEqual_T_99 = 32'h0; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbsEqual_T_102 = 32'h0; // @[PMP.scala:60:27]
wire [31:0] _res_hit_lsbsLess_T_100 = 32'h0; // @[PMP.scala:60:36]
wire [31:0] _res_hit_lsbsLess_T_103 = 32'h0; // @[PMP.scala:60:27]
wire [31:0] _res_aligned_straddlesLowerBound_T_120 = 32'h0; // @[PMP.scala:60:36]
wire [31:0] _res_aligned_straddlesLowerBound_T_123 = 32'h0; // @[PMP.scala:60:27]
wire [31:0] _res_aligned_straddlesLowerBound_T_127 = 32'h0; // @[PMP.scala:60:36]
wire [31:0] _res_aligned_straddlesLowerBound_T_130 = 32'h0; // @[PMP.scala:60:27]
wire [2:0] _res_hit_lsbsLess_T_104 = 3'h0; // @[PMP.scala:82:64, :123:{108,125}]
wire [2:0] _res_aligned_straddlesLowerBound_T_131 = 3'h0; // @[PMP.scala:82:64, :123:{108,125}]
wire [2:0] _res_aligned_straddlesLowerBound_T_134 = 3'h0; // @[PMP.scala:82:64, :123:{108,125}]
wire _pmp0_WIRE_cfg_l = 1'h0; // @[PMP.scala:157:35]
wire _pmp0_WIRE_cfg_x = 1'h0; // @[PMP.scala:157:35]
wire _pmp0_WIRE_cfg_w = 1'h0; // @[PMP.scala:157:35]
wire _pmp0_WIRE_cfg_r = 1'h0; // @[PMP.scala:157:35]
wire pmp0_cfg_l = 1'h0; // @[PMP.scala:157:22]
wire res_hit_msbsLess_14 = 1'h0; // @[PMP.scala:80:39]
wire res_hit_lsbsLess_14 = 1'h0; // @[PMP.scala:82:53]
wire _res_hit_T_97 = 1'h0; // @[PMP.scala:83:30]
wire _res_hit_T_98 = 1'h0; // @[PMP.scala:83:16]
wire _res_aligned_straddlesLowerBound_T_135 = 1'h0; // @[PMP.scala:123:147]
wire res_aligned_straddlesLowerBound_7 = 1'h0; // @[PMP.scala:123:90]
wire [1:0] io_pmp_0_cfg_res = 2'h0; // @[PMP.scala:143:7]
wire [1:0] io_pmp_1_cfg_res = 2'h0; // @[PMP.scala:143:7]
wire [1:0] io_pmp_2_cfg_res = 2'h0; // @[PMP.scala:143:7]
wire [1:0] io_pmp_3_cfg_res = 2'h0; // @[PMP.scala:143:7]
wire [1:0] io_pmp_4_cfg_res = 2'h0; // @[PMP.scala:143:7]
wire [1:0] io_pmp_5_cfg_res = 2'h0; // @[PMP.scala:143:7]
wire [1:0] io_pmp_6_cfg_res = 2'h0; // @[PMP.scala:143:7]
wire [1:0] io_pmp_7_cfg_res = 2'h0; // @[PMP.scala:143:7]
wire [1:0] _pmp0_WIRE_cfg_res = 2'h0; // @[PMP.scala:157:35]
wire [1:0] _pmp0_WIRE_cfg_a = 2'h0; // @[PMP.scala:157:35]
wire [1:0] pmp0_cfg_res = 2'h0; // @[PMP.scala:157:22]
wire [1:0] pmp0_cfg_a = 2'h0; // @[PMP.scala:157:22]
wire [1:0] res_cur_cfg_res = 2'h0; // @[PMP.scala:181:23]
wire [1:0] _res_T_44_cfg_res = 2'h0; // @[PMP.scala:185:8]
wire [1:0] res_cur_1_cfg_res = 2'h0; // @[PMP.scala:181:23]
wire [1:0] _res_T_89_cfg_res = 2'h0; // @[PMP.scala:185:8]
wire [1:0] res_cur_2_cfg_res = 2'h0; // @[PMP.scala:181:23]
wire [1:0] _res_T_134_cfg_res = 2'h0; // @[PMP.scala:185:8]
wire [1:0] res_cur_3_cfg_res = 2'h0; // @[PMP.scala:181:23]
wire [1:0] _res_T_179_cfg_res = 2'h0; // @[PMP.scala:185:8]
wire [1:0] res_cur_4_cfg_res = 2'h0; // @[PMP.scala:181:23]
wire [1:0] _res_T_224_cfg_res = 2'h0; // @[PMP.scala:185:8]
wire [1:0] res_cur_5_cfg_res = 2'h0; // @[PMP.scala:181:23]
wire [1:0] _res_T_269_cfg_res = 2'h0; // @[PMP.scala:185:8]
wire [1:0] res_cur_6_cfg_res = 2'h0; // @[PMP.scala:181:23]
wire [1:0] _res_T_314_cfg_res = 2'h0; // @[PMP.scala:185:8]
wire [1:0] res_cur_7_cfg_res = 2'h0; // @[PMP.scala:181:23]
wire [1:0] res_cfg_res = 2'h0; // @[PMP.scala:185:8]
wire _res_T_319 = io_pmp_0_cfg_l_0; // @[PMP.scala:143:7, :170:30]
wire res_cur_7_cfg_l = io_pmp_0_cfg_l_0; // @[PMP.scala:143:7, :181:23]
wire [1:0] res_cur_7_cfg_a = io_pmp_0_cfg_a_0; // @[PMP.scala:143:7, :181:23]
wire [29:0] res_cur_7_addr = io_pmp_0_addr_0; // @[PMP.scala:143:7, :181:23]
wire [31:0] res_cur_7_mask = io_pmp_0_mask_0; // @[PMP.scala:143:7, :181:23]
wire _res_T_274 = io_pmp_1_cfg_l_0; // @[PMP.scala:143:7, :170:30]
wire res_cur_6_cfg_l = io_pmp_1_cfg_l_0; // @[PMP.scala:143:7, :181:23]
wire [1:0] res_cur_6_cfg_a = io_pmp_1_cfg_a_0; // @[PMP.scala:143:7, :181:23]
wire [29:0] res_cur_6_addr = io_pmp_1_addr_0; // @[PMP.scala:143:7, :181:23]
wire [31:0] res_cur_6_mask = io_pmp_1_mask_0; // @[PMP.scala:143:7, :181:23]
wire _res_T_229 = io_pmp_2_cfg_l_0; // @[PMP.scala:143:7, :170:30]
wire res_cur_5_cfg_l = io_pmp_2_cfg_l_0; // @[PMP.scala:143:7, :181:23]
wire [1:0] res_cur_5_cfg_a = io_pmp_2_cfg_a_0; // @[PMP.scala:143:7, :181:23]
wire [29:0] res_cur_5_addr = io_pmp_2_addr_0; // @[PMP.scala:143:7, :181:23]
wire [31:0] res_cur_5_mask = io_pmp_2_mask_0; // @[PMP.scala:143:7, :181:23]
wire _res_T_184 = io_pmp_3_cfg_l_0; // @[PMP.scala:143:7, :170:30]
wire res_cur_4_cfg_l = io_pmp_3_cfg_l_0; // @[PMP.scala:143:7, :181:23]
wire [1:0] res_cur_4_cfg_a = io_pmp_3_cfg_a_0; // @[PMP.scala:143:7, :181:23]
wire [29:0] res_cur_4_addr = io_pmp_3_addr_0; // @[PMP.scala:143:7, :181:23]
wire [31:0] res_cur_4_mask = io_pmp_3_mask_0; // @[PMP.scala:143:7, :181:23]
wire _res_T_139 = io_pmp_4_cfg_l_0; // @[PMP.scala:143:7, :170:30]
wire res_cur_3_cfg_l = io_pmp_4_cfg_l_0; // @[PMP.scala:143:7, :181:23]
wire [1:0] res_cur_3_cfg_a = io_pmp_4_cfg_a_0; // @[PMP.scala:143:7, :181:23]
wire [29:0] res_cur_3_addr = io_pmp_4_addr_0; // @[PMP.scala:143:7, :181:23]
wire [31:0] res_cur_3_mask = io_pmp_4_mask_0; // @[PMP.scala:143:7, :181:23]
wire _res_T_94 = io_pmp_5_cfg_l_0; // @[PMP.scala:143:7, :170:30]
wire res_cur_2_cfg_l = io_pmp_5_cfg_l_0; // @[PMP.scala:143:7, :181:23]
wire [1:0] res_cur_2_cfg_a = io_pmp_5_cfg_a_0; // @[PMP.scala:143:7, :181:23]
wire [29:0] res_cur_2_addr = io_pmp_5_addr_0; // @[PMP.scala:143:7, :181:23]
wire [31:0] res_cur_2_mask = io_pmp_5_mask_0; // @[PMP.scala:143:7, :181:23]
wire _res_T_49 = io_pmp_6_cfg_l_0; // @[PMP.scala:143:7, :170:30]
wire res_cur_1_cfg_l = io_pmp_6_cfg_l_0; // @[PMP.scala:143:7, :181:23]
wire [1:0] res_cur_1_cfg_a = io_pmp_6_cfg_a_0; // @[PMP.scala:143:7, :181:23]
wire [29:0] res_cur_1_addr = io_pmp_6_addr_0; // @[PMP.scala:143:7, :181:23]
wire [31:0] res_cur_1_mask = io_pmp_6_mask_0; // @[PMP.scala:143:7, :181:23]
wire _res_T_4 = io_pmp_7_cfg_l_0; // @[PMP.scala:143:7, :170:30]
wire res_cur_cfg_l = io_pmp_7_cfg_l_0; // @[PMP.scala:143:7, :181:23]
wire [1:0] res_cur_cfg_a = io_pmp_7_cfg_a_0; // @[PMP.scala:143:7, :181:23]
wire [29:0] res_cur_addr = io_pmp_7_addr_0; // @[PMP.scala:143:7, :181:23]
wire [31:0] res_cur_mask = io_pmp_7_mask_0; // @[PMP.scala:143:7, :181:23]
wire res_cfg_r; // @[PMP.scala:185:8]
wire res_cfg_w; // @[PMP.scala:185:8]
wire res_cfg_x; // @[PMP.scala:185:8]
wire io_r_0; // @[PMP.scala:143:7]
wire io_w_0; // @[PMP.scala:143:7]
wire io_x_0; // @[PMP.scala:143:7]
wire default_0 = io_prv_0[1]; // @[PMP.scala:143:7, :156:56]
wire pmp0_cfg_x = default_0; // @[PMP.scala:156:56, :157:22]
wire pmp0_cfg_w = default_0; // @[PMP.scala:156:56, :157:22]
wire pmp0_cfg_r = default_0; // @[PMP.scala:156:56, :157:22]
wire _res_hit_T = io_pmp_7_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7]
wire _res_aligned_T = io_pmp_7_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7]
wire [5:0] _GEN = 6'h7 << io_size_0; // @[package.scala:243:71]
wire [5:0] _res_hit_lsbMask_T; // @[package.scala:243:71]
assign _res_hit_lsbMask_T = _GEN; // @[package.scala:243:71]
wire [5:0] _res_hit_T_3; // @[package.scala:243:71]
assign _res_hit_T_3 = _GEN; // @[package.scala:243:71]
wire [5:0] _res_aligned_lsbMask_T; // @[package.scala:243:71]
assign _res_aligned_lsbMask_T = _GEN; // @[package.scala:243:71]
wire [5:0] _res_hit_lsbMask_T_3; // @[package.scala:243:71]
assign _res_hit_lsbMask_T_3 = _GEN; // @[package.scala:243:71]
wire [5:0] _res_hit_T_16; // @[package.scala:243:71]
assign _res_hit_T_16 = _GEN; // @[package.scala:243:71]
wire [5:0] _res_aligned_lsbMask_T_2; // @[package.scala:243:71]
assign _res_aligned_lsbMask_T_2 = _GEN; // @[package.scala:243:71]
wire [5:0] _res_hit_lsbMask_T_6; // @[package.scala:243:71]
assign _res_hit_lsbMask_T_6 = _GEN; // @[package.scala:243:71]
wire [5:0] _res_hit_T_29; // @[package.scala:243:71]
assign _res_hit_T_29 = _GEN; // @[package.scala:243:71]
wire [5:0] _res_aligned_lsbMask_T_4; // @[package.scala:243:71]
assign _res_aligned_lsbMask_T_4 = _GEN; // @[package.scala:243:71]
wire [5:0] _res_hit_lsbMask_T_9; // @[package.scala:243:71]
assign _res_hit_lsbMask_T_9 = _GEN; // @[package.scala:243:71]
wire [5:0] _res_hit_T_42; // @[package.scala:243:71]
assign _res_hit_T_42 = _GEN; // @[package.scala:243:71]
wire [5:0] _res_aligned_lsbMask_T_6; // @[package.scala:243:71]
assign _res_aligned_lsbMask_T_6 = _GEN; // @[package.scala:243:71]
wire [5:0] _res_hit_lsbMask_T_12; // @[package.scala:243:71]
assign _res_hit_lsbMask_T_12 = _GEN; // @[package.scala:243:71]
wire [5:0] _res_hit_T_55; // @[package.scala:243:71]
assign _res_hit_T_55 = _GEN; // @[package.scala:243:71]
wire [5:0] _res_aligned_lsbMask_T_8; // @[package.scala:243:71]
assign _res_aligned_lsbMask_T_8 = _GEN; // @[package.scala:243:71]
wire [5:0] _res_hit_lsbMask_T_15; // @[package.scala:243:71]
assign _res_hit_lsbMask_T_15 = _GEN; // @[package.scala:243:71]
wire [5:0] _res_hit_T_68; // @[package.scala:243:71]
assign _res_hit_T_68 = _GEN; // @[package.scala:243:71]
wire [5:0] _res_aligned_lsbMask_T_10; // @[package.scala:243:71]
assign _res_aligned_lsbMask_T_10 = _GEN; // @[package.scala:243:71]
wire [5:0] _res_hit_lsbMask_T_18; // @[package.scala:243:71]
assign _res_hit_lsbMask_T_18 = _GEN; // @[package.scala:243:71]
wire [5:0] _res_hit_T_81; // @[package.scala:243:71]
assign _res_hit_T_81 = _GEN; // @[package.scala:243:71]
wire [5:0] _res_aligned_lsbMask_T_12; // @[package.scala:243:71]
assign _res_aligned_lsbMask_T_12 = _GEN; // @[package.scala:243:71]
wire [5:0] _res_hit_lsbMask_T_21; // @[package.scala:243:71]
assign _res_hit_lsbMask_T_21 = _GEN; // @[package.scala:243:71]
wire [5:0] _res_hit_T_94; // @[package.scala:243:71]
assign _res_hit_T_94 = _GEN; // @[package.scala:243:71]
wire [5:0] _res_aligned_lsbMask_T_14; // @[package.scala:243:71]
assign _res_aligned_lsbMask_T_14 = _GEN; // @[package.scala:243:71]
wire [2:0] _res_hit_lsbMask_T_1 = _res_hit_lsbMask_T[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] _res_hit_lsbMask_T_2 = ~_res_hit_lsbMask_T_1; // @[package.scala:243:{46,76}]
wire [28:0] _res_hit_msbMatch_T_6 = io_pmp_7_mask_0[31:3]; // @[PMP.scala:68:26, :69:72, :143:7]
wire [2:0] _res_aligned_pow2Aligned_T = io_pmp_7_mask_0[2:0]; // @[PMP.scala:68:26, :126:39, :143:7]
wire [31:0] res_hit_lsbMask = {_res_hit_msbMatch_T_6, _res_aligned_pow2Aligned_T | _res_hit_lsbMask_T_2}; // @[package.scala:243:46]
wire [28:0] _res_hit_msbMatch_T = io_addr_0[31:3]; // @[PMP.scala:69:29, :143:7]
wire [28:0] _res_hit_msbsLess_T = io_addr_0[31:3]; // @[PMP.scala:69:29, :80:25, :143:7]
wire [28:0] _res_hit_msbsEqual_T = io_addr_0[31:3]; // @[PMP.scala:69:29, :81:27, :143:7]
wire [28:0] _res_hit_msbsLess_T_6 = io_addr_0[31:3]; // @[PMP.scala:69:29, :80:25, :143:7]
wire [28:0] _res_hit_msbsEqual_T_7 = io_addr_0[31:3]; // @[PMP.scala:69:29, :81:27, :143:7]
wire [28:0] _res_aligned_straddlesLowerBound_T = io_addr_0[31:3]; // @[PMP.scala:69:29, :123:35, :143:7]
wire [28:0] _res_aligned_straddlesUpperBound_T = io_addr_0[31:3]; // @[PMP.scala:69:29, :124:35, :143:7]
wire [28:0] _res_hit_msbMatch_T_10 = io_addr_0[31:3]; // @[PMP.scala:69:29, :143:7]
wire [28:0] _res_hit_msbsLess_T_12 = io_addr_0[31:3]; // @[PMP.scala:69:29, :80:25, :143:7]
wire [28:0] _res_hit_msbsEqual_T_14 = io_addr_0[31:3]; // @[PMP.scala:69:29, :81:27, :143:7]
wire [28:0] _res_hit_msbsLess_T_18 = io_addr_0[31:3]; // @[PMP.scala:69:29, :80:25, :143:7]
wire [28:0] _res_hit_msbsEqual_T_21 = io_addr_0[31:3]; // @[PMP.scala:69:29, :81:27, :143:7]
wire [28:0] _res_aligned_straddlesLowerBound_T_17 = io_addr_0[31:3]; // @[PMP.scala:69:29, :123:35, :143:7]
wire [28:0] _res_aligned_straddlesUpperBound_T_17 = io_addr_0[31:3]; // @[PMP.scala:69:29, :124:35, :143:7]
wire [28:0] _res_hit_msbMatch_T_20 = io_addr_0[31:3]; // @[PMP.scala:69:29, :143:7]
wire [28:0] _res_hit_msbsLess_T_24 = io_addr_0[31:3]; // @[PMP.scala:69:29, :80:25, :143:7]
wire [28:0] _res_hit_msbsEqual_T_28 = io_addr_0[31:3]; // @[PMP.scala:69:29, :81:27, :143:7]
wire [28:0] _res_hit_msbsLess_T_30 = io_addr_0[31:3]; // @[PMP.scala:69:29, :80:25, :143:7]
wire [28:0] _res_hit_msbsEqual_T_35 = io_addr_0[31:3]; // @[PMP.scala:69:29, :81:27, :143:7]
wire [28:0] _res_aligned_straddlesLowerBound_T_34 = io_addr_0[31:3]; // @[PMP.scala:69:29, :123:35, :143:7]
wire [28:0] _res_aligned_straddlesUpperBound_T_34 = io_addr_0[31:3]; // @[PMP.scala:69:29, :124:35, :143:7]
wire [28:0] _res_hit_msbMatch_T_30 = io_addr_0[31:3]; // @[PMP.scala:69:29, :143:7]
wire [28:0] _res_hit_msbsLess_T_36 = io_addr_0[31:3]; // @[PMP.scala:69:29, :80:25, :143:7]
wire [28:0] _res_hit_msbsEqual_T_42 = io_addr_0[31:3]; // @[PMP.scala:69:29, :81:27, :143:7]
wire [28:0] _res_hit_msbsLess_T_42 = io_addr_0[31:3]; // @[PMP.scala:69:29, :80:25, :143:7]
wire [28:0] _res_hit_msbsEqual_T_49 = io_addr_0[31:3]; // @[PMP.scala:69:29, :81:27, :143:7]
wire [28:0] _res_aligned_straddlesLowerBound_T_51 = io_addr_0[31:3]; // @[PMP.scala:69:29, :123:35, :143:7]
wire [28:0] _res_aligned_straddlesUpperBound_T_51 = io_addr_0[31:3]; // @[PMP.scala:69:29, :124:35, :143:7]
wire [28:0] _res_hit_msbMatch_T_40 = io_addr_0[31:3]; // @[PMP.scala:69:29, :143:7]
wire [28:0] _res_hit_msbsLess_T_48 = io_addr_0[31:3]; // @[PMP.scala:69:29, :80:25, :143:7]
wire [28:0] _res_hit_msbsEqual_T_56 = io_addr_0[31:3]; // @[PMP.scala:69:29, :81:27, :143:7]
wire [28:0] _res_hit_msbsLess_T_54 = io_addr_0[31:3]; // @[PMP.scala:69:29, :80:25, :143:7]
wire [28:0] _res_hit_msbsEqual_T_63 = io_addr_0[31:3]; // @[PMP.scala:69:29, :81:27, :143:7]
wire [28:0] _res_aligned_straddlesLowerBound_T_68 = io_addr_0[31:3]; // @[PMP.scala:69:29, :123:35, :143:7]
wire [28:0] _res_aligned_straddlesUpperBound_T_68 = io_addr_0[31:3]; // @[PMP.scala:69:29, :124:35, :143:7]
wire [28:0] _res_hit_msbMatch_T_50 = io_addr_0[31:3]; // @[PMP.scala:69:29, :143:7]
wire [28:0] _res_hit_msbsLess_T_60 = io_addr_0[31:3]; // @[PMP.scala:69:29, :80:25, :143:7]
wire [28:0] _res_hit_msbsEqual_T_70 = io_addr_0[31:3]; // @[PMP.scala:69:29, :81:27, :143:7]
wire [28:0] _res_hit_msbsLess_T_66 = io_addr_0[31:3]; // @[PMP.scala:69:29, :80:25, :143:7]
wire [28:0] _res_hit_msbsEqual_T_77 = io_addr_0[31:3]; // @[PMP.scala:69:29, :81:27, :143:7]
wire [28:0] _res_aligned_straddlesLowerBound_T_85 = io_addr_0[31:3]; // @[PMP.scala:69:29, :123:35, :143:7]
wire [28:0] _res_aligned_straddlesUpperBound_T_85 = io_addr_0[31:3]; // @[PMP.scala:69:29, :124:35, :143:7]
wire [28:0] _res_hit_msbMatch_T_60 = io_addr_0[31:3]; // @[PMP.scala:69:29, :143:7]
wire [28:0] _res_hit_msbsLess_T_72 = io_addr_0[31:3]; // @[PMP.scala:69:29, :80:25, :143:7]
wire [28:0] _res_hit_msbsEqual_T_84 = io_addr_0[31:3]; // @[PMP.scala:69:29, :81:27, :143:7]
wire [28:0] _res_hit_msbsLess_T_78 = io_addr_0[31:3]; // @[PMP.scala:69:29, :80:25, :143:7]
wire [28:0] _res_hit_msbsEqual_T_91 = io_addr_0[31:3]; // @[PMP.scala:69:29, :81:27, :143:7]
wire [28:0] _res_aligned_straddlesLowerBound_T_102 = io_addr_0[31:3]; // @[PMP.scala:69:29, :123:35, :143:7]
wire [28:0] _res_aligned_straddlesUpperBound_T_102 = io_addr_0[31:3]; // @[PMP.scala:69:29, :124:35, :143:7]
wire [28:0] _res_hit_msbMatch_T_70 = io_addr_0[31:3]; // @[PMP.scala:69:29, :143:7]
wire [28:0] _res_hit_msbsLess_T_84 = io_addr_0[31:3]; // @[PMP.scala:69:29, :80:25, :143:7]
wire [28:0] _res_hit_msbsEqual_T_98 = io_addr_0[31:3]; // @[PMP.scala:69:29, :81:27, :143:7]
wire [28:0] _res_hit_msbsLess_T_90 = io_addr_0[31:3]; // @[PMP.scala:69:29, :80:25, :143:7]
wire [28:0] _res_hit_msbsEqual_T_105 = io_addr_0[31:3]; // @[PMP.scala:69:29, :81:27, :143:7]
wire [28:0] _res_aligned_straddlesLowerBound_T_119 = io_addr_0[31:3]; // @[PMP.scala:69:29, :123:35, :143:7]
wire [28:0] _res_aligned_straddlesUpperBound_T_119 = io_addr_0[31:3]; // @[PMP.scala:69:29, :124:35, :143:7]
wire [31:0] _GEN_0 = {io_pmp_7_addr_0, 2'h0}; // @[PMP.scala:60:36, :143:7]
wire [31:0] _res_hit_msbMatch_T_1; // @[PMP.scala:60:36]
assign _res_hit_msbMatch_T_1 = _GEN_0; // @[PMP.scala:60:36]
wire [31:0] _res_hit_lsbMatch_T_1; // @[PMP.scala:60:36]
assign _res_hit_lsbMatch_T_1 = _GEN_0; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbsLess_T_7; // @[PMP.scala:60:36]
assign _res_hit_msbsLess_T_7 = _GEN_0; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbsEqual_T_8; // @[PMP.scala:60:36]
assign _res_hit_msbsEqual_T_8 = _GEN_0; // @[PMP.scala:60:36]
wire [31:0] _res_hit_lsbsLess_T_9; // @[PMP.scala:60:36]
assign _res_hit_lsbsLess_T_9 = _GEN_0; // @[PMP.scala:60:36]
wire [31:0] _res_aligned_straddlesUpperBound_T_1; // @[PMP.scala:60:36]
assign _res_aligned_straddlesUpperBound_T_1 = _GEN_0; // @[PMP.scala:60:36]
wire [31:0] _res_aligned_straddlesUpperBound_T_8; // @[PMP.scala:60:36]
assign _res_aligned_straddlesUpperBound_T_8 = _GEN_0; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbMatch_T_2 = ~_res_hit_msbMatch_T_1; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_msbMatch_T_3 = {_res_hit_msbMatch_T_2[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbMatch_T_4 = ~_res_hit_msbMatch_T_3; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_hit_msbMatch_T_5 = _res_hit_msbMatch_T_4[31:3]; // @[PMP.scala:60:27, :69:53]
wire [28:0] _res_hit_msbMatch_T_7 = _res_hit_msbMatch_T ^ _res_hit_msbMatch_T_5; // @[PMP.scala:63:47, :69:{29,53}]
wire [28:0] _res_hit_msbMatch_T_8 = ~_res_hit_msbMatch_T_6; // @[PMP.scala:63:54, :69:72]
wire [28:0] _res_hit_msbMatch_T_9 = _res_hit_msbMatch_T_7 & _res_hit_msbMatch_T_8; // @[PMP.scala:63:{47,52,54}]
wire res_hit_msbMatch = _res_hit_msbMatch_T_9 == 29'h0; // @[PMP.scala:63:{52,58}, :80:52, :81:54, :123:67]
wire [2:0] _res_hit_lsbMatch_T = io_addr_0[2:0]; // @[PMP.scala:70:28, :143:7]
wire [2:0] _res_hit_lsbsLess_T = io_addr_0[2:0]; // @[PMP.scala:70:28, :82:25, :143:7]
wire [2:0] _res_hit_lsbsLess_T_7 = io_addr_0[2:0]; // @[PMP.scala:70:28, :82:25, :143:7]
wire [2:0] _res_aligned_straddlesLowerBound_T_13 = io_addr_0[2:0]; // @[PMP.scala:70:28, :123:129, :143:7]
wire [2:0] _res_aligned_straddlesUpperBound_T_13 = io_addr_0[2:0]; // @[PMP.scala:70:28, :124:119, :143:7]
wire [2:0] _res_hit_lsbMatch_T_10 = io_addr_0[2:0]; // @[PMP.scala:70:28, :143:7]
wire [2:0] _res_hit_lsbsLess_T_14 = io_addr_0[2:0]; // @[PMP.scala:70:28, :82:25, :143:7]
wire [2:0] _res_hit_lsbsLess_T_21 = io_addr_0[2:0]; // @[PMP.scala:70:28, :82:25, :143:7]
wire [2:0] _res_aligned_straddlesLowerBound_T_30 = io_addr_0[2:0]; // @[PMP.scala:70:28, :123:129, :143:7]
wire [2:0] _res_aligned_straddlesUpperBound_T_30 = io_addr_0[2:0]; // @[PMP.scala:70:28, :124:119, :143:7]
wire [2:0] _res_hit_lsbMatch_T_20 = io_addr_0[2:0]; // @[PMP.scala:70:28, :143:7]
wire [2:0] _res_hit_lsbsLess_T_28 = io_addr_0[2:0]; // @[PMP.scala:70:28, :82:25, :143:7]
wire [2:0] _res_hit_lsbsLess_T_35 = io_addr_0[2:0]; // @[PMP.scala:70:28, :82:25, :143:7]
wire [2:0] _res_aligned_straddlesLowerBound_T_47 = io_addr_0[2:0]; // @[PMP.scala:70:28, :123:129, :143:7]
wire [2:0] _res_aligned_straddlesUpperBound_T_47 = io_addr_0[2:0]; // @[PMP.scala:70:28, :124:119, :143:7]
wire [2:0] _res_hit_lsbMatch_T_30 = io_addr_0[2:0]; // @[PMP.scala:70:28, :143:7]
wire [2:0] _res_hit_lsbsLess_T_42 = io_addr_0[2:0]; // @[PMP.scala:70:28, :82:25, :143:7]
wire [2:0] _res_hit_lsbsLess_T_49 = io_addr_0[2:0]; // @[PMP.scala:70:28, :82:25, :143:7]
wire [2:0] _res_aligned_straddlesLowerBound_T_64 = io_addr_0[2:0]; // @[PMP.scala:70:28, :123:129, :143:7]
wire [2:0] _res_aligned_straddlesUpperBound_T_64 = io_addr_0[2:0]; // @[PMP.scala:70:28, :124:119, :143:7]
wire [2:0] _res_hit_lsbMatch_T_40 = io_addr_0[2:0]; // @[PMP.scala:70:28, :143:7]
wire [2:0] _res_hit_lsbsLess_T_56 = io_addr_0[2:0]; // @[PMP.scala:70:28, :82:25, :143:7]
wire [2:0] _res_hit_lsbsLess_T_63 = io_addr_0[2:0]; // @[PMP.scala:70:28, :82:25, :143:7]
wire [2:0] _res_aligned_straddlesLowerBound_T_81 = io_addr_0[2:0]; // @[PMP.scala:70:28, :123:129, :143:7]
wire [2:0] _res_aligned_straddlesUpperBound_T_81 = io_addr_0[2:0]; // @[PMP.scala:70:28, :124:119, :143:7]
wire [2:0] _res_hit_lsbMatch_T_50 = io_addr_0[2:0]; // @[PMP.scala:70:28, :143:7]
wire [2:0] _res_hit_lsbsLess_T_70 = io_addr_0[2:0]; // @[PMP.scala:70:28, :82:25, :143:7]
wire [2:0] _res_hit_lsbsLess_T_77 = io_addr_0[2:0]; // @[PMP.scala:70:28, :82:25, :143:7]
wire [2:0] _res_aligned_straddlesLowerBound_T_98 = io_addr_0[2:0]; // @[PMP.scala:70:28, :123:129, :143:7]
wire [2:0] _res_aligned_straddlesUpperBound_T_98 = io_addr_0[2:0]; // @[PMP.scala:70:28, :124:119, :143:7]
wire [2:0] _res_hit_lsbMatch_T_60 = io_addr_0[2:0]; // @[PMP.scala:70:28, :143:7]
wire [2:0] _res_hit_lsbsLess_T_84 = io_addr_0[2:0]; // @[PMP.scala:70:28, :82:25, :143:7]
wire [2:0] _res_hit_lsbsLess_T_91 = io_addr_0[2:0]; // @[PMP.scala:70:28, :82:25, :143:7]
wire [2:0] _res_aligned_straddlesLowerBound_T_115 = io_addr_0[2:0]; // @[PMP.scala:70:28, :123:129, :143:7]
wire [2:0] _res_aligned_straddlesUpperBound_T_115 = io_addr_0[2:0]; // @[PMP.scala:70:28, :124:119, :143:7]
wire [2:0] _res_hit_lsbMatch_T_70 = io_addr_0[2:0]; // @[PMP.scala:70:28, :143:7]
wire [2:0] _res_hit_lsbsLess_T_98 = io_addr_0[2:0]; // @[PMP.scala:70:28, :82:25, :143:7]
wire [2:0] _res_hit_lsbsLess_T_105 = io_addr_0[2:0]; // @[PMP.scala:70:28, :82:25, :143:7]
wire [2:0] _res_aligned_straddlesLowerBound_T_132 = io_addr_0[2:0]; // @[PMP.scala:70:28, :123:129, :143:7]
wire [2:0] _res_aligned_straddlesUpperBound_T_132 = io_addr_0[2:0]; // @[PMP.scala:70:28, :124:119, :143:7]
wire [31:0] _res_hit_lsbMatch_T_2 = ~_res_hit_lsbMatch_T_1; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_lsbMatch_T_3 = {_res_hit_lsbMatch_T_2[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_lsbMatch_T_4 = ~_res_hit_lsbMatch_T_3; // @[PMP.scala:60:{27,48}]
wire [2:0] _res_hit_lsbMatch_T_5 = _res_hit_lsbMatch_T_4[2:0]; // @[PMP.scala:60:27, :70:55]
wire [2:0] _res_hit_lsbMatch_T_6 = res_hit_lsbMask[2:0]; // @[PMP.scala:68:26, :70:80]
wire [2:0] _res_hit_lsbMatch_T_7 = _res_hit_lsbMatch_T ^ _res_hit_lsbMatch_T_5; // @[PMP.scala:63:47, :70:{28,55}]
wire [2:0] _res_hit_lsbMatch_T_8 = ~_res_hit_lsbMatch_T_6; // @[PMP.scala:63:54, :70:80]
wire [2:0] _res_hit_lsbMatch_T_9 = _res_hit_lsbMatch_T_7 & _res_hit_lsbMatch_T_8; // @[PMP.scala:63:{47,52,54}]
wire res_hit_lsbMatch = _res_hit_lsbMatch_T_9 == 3'h0; // @[PMP.scala:63:{52,58}, :82:64, :123:{108,125}]
wire _res_hit_T_1 = res_hit_msbMatch & res_hit_lsbMatch; // @[PMP.scala:63:58, :71:16]
wire _res_hit_T_2 = io_pmp_7_cfg_a_0[0]; // @[PMP.scala:46:26, :143:7]
wire [2:0] _res_hit_T_4 = _res_hit_T_3[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] _res_hit_T_5 = ~_res_hit_T_4; // @[package.scala:243:{46,76}]
wire [31:0] _GEN_1 = {io_pmp_6_addr_0, 2'h0}; // @[PMP.scala:60:36, :143:7]
wire [31:0] _res_hit_msbsLess_T_1; // @[PMP.scala:60:36]
assign _res_hit_msbsLess_T_1 = _GEN_1; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbsEqual_T_1; // @[PMP.scala:60:36]
assign _res_hit_msbsEqual_T_1 = _GEN_1; // @[PMP.scala:60:36]
wire [31:0] _res_hit_lsbsLess_T_2; // @[PMP.scala:60:36]
assign _res_hit_lsbsLess_T_2 = _GEN_1; // @[PMP.scala:60:36]
wire [31:0] _res_aligned_straddlesLowerBound_T_1; // @[PMP.scala:60:36]
assign _res_aligned_straddlesLowerBound_T_1 = _GEN_1; // @[PMP.scala:60:36]
wire [31:0] _res_aligned_straddlesLowerBound_T_8; // @[PMP.scala:60:36]
assign _res_aligned_straddlesLowerBound_T_8 = _GEN_1; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbMatch_T_11; // @[PMP.scala:60:36]
assign _res_hit_msbMatch_T_11 = _GEN_1; // @[PMP.scala:60:36]
wire [31:0] _res_hit_lsbMatch_T_11; // @[PMP.scala:60:36]
assign _res_hit_lsbMatch_T_11 = _GEN_1; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbsLess_T_19; // @[PMP.scala:60:36]
assign _res_hit_msbsLess_T_19 = _GEN_1; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbsEqual_T_22; // @[PMP.scala:60:36]
assign _res_hit_msbsEqual_T_22 = _GEN_1; // @[PMP.scala:60:36]
wire [31:0] _res_hit_lsbsLess_T_23; // @[PMP.scala:60:36]
assign _res_hit_lsbsLess_T_23 = _GEN_1; // @[PMP.scala:60:36]
wire [31:0] _res_aligned_straddlesUpperBound_T_18; // @[PMP.scala:60:36]
assign _res_aligned_straddlesUpperBound_T_18 = _GEN_1; // @[PMP.scala:60:36]
wire [31:0] _res_aligned_straddlesUpperBound_T_25; // @[PMP.scala:60:36]
assign _res_aligned_straddlesUpperBound_T_25 = _GEN_1; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbsLess_T_2 = ~_res_hit_msbsLess_T_1; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_msbsLess_T_3 = {_res_hit_msbsLess_T_2[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbsLess_T_4 = ~_res_hit_msbsLess_T_3; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_hit_msbsLess_T_5 = _res_hit_msbsLess_T_4[31:3]; // @[PMP.scala:60:27, :80:52]
wire res_hit_msbsLess = _res_hit_msbsLess_T < _res_hit_msbsLess_T_5; // @[PMP.scala:80:{25,39,52}]
wire [31:0] _res_hit_msbsEqual_T_2 = ~_res_hit_msbsEqual_T_1; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_msbsEqual_T_3 = {_res_hit_msbsEqual_T_2[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbsEqual_T_4 = ~_res_hit_msbsEqual_T_3; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_hit_msbsEqual_T_5 = _res_hit_msbsEqual_T_4[31:3]; // @[PMP.scala:60:27, :81:54]
wire [28:0] _res_hit_msbsEqual_T_6 = _res_hit_msbsEqual_T ^ _res_hit_msbsEqual_T_5; // @[PMP.scala:81:{27,41,54}]
wire res_hit_msbsEqual = _res_hit_msbsEqual_T_6 == 29'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67]
wire [2:0] _res_hit_lsbsLess_T_1 = _res_hit_lsbsLess_T | _res_hit_T_5; // @[package.scala:243:46]
wire [31:0] _res_hit_lsbsLess_T_3 = ~_res_hit_lsbsLess_T_2; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_lsbsLess_T_4 = {_res_hit_lsbsLess_T_3[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_lsbsLess_T_5 = ~_res_hit_lsbsLess_T_4; // @[PMP.scala:60:{27,48}]
wire [2:0] _res_hit_lsbsLess_T_6 = _res_hit_lsbsLess_T_5[2:0]; // @[PMP.scala:60:27, :82:64]
wire res_hit_lsbsLess = _res_hit_lsbsLess_T_1 < _res_hit_lsbsLess_T_6; // @[PMP.scala:82:{42,53,64}]
wire _res_hit_T_6 = res_hit_msbsEqual & res_hit_lsbsLess; // @[PMP.scala:81:69, :82:53, :83:30]
wire _res_hit_T_7 = res_hit_msbsLess | _res_hit_T_6; // @[PMP.scala:80:39, :83:{16,30}]
wire _res_hit_T_8 = ~_res_hit_T_7; // @[PMP.scala:83:16, :88:5]
wire [31:0] _res_hit_msbsLess_T_8 = ~_res_hit_msbsLess_T_7; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_msbsLess_T_9 = {_res_hit_msbsLess_T_8[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbsLess_T_10 = ~_res_hit_msbsLess_T_9; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_hit_msbsLess_T_11 = _res_hit_msbsLess_T_10[31:3]; // @[PMP.scala:60:27, :80:52]
wire res_hit_msbsLess_1 = _res_hit_msbsLess_T_6 < _res_hit_msbsLess_T_11; // @[PMP.scala:80:{25,39,52}]
wire [31:0] _res_hit_msbsEqual_T_9 = ~_res_hit_msbsEqual_T_8; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_msbsEqual_T_10 = {_res_hit_msbsEqual_T_9[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbsEqual_T_11 = ~_res_hit_msbsEqual_T_10; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_hit_msbsEqual_T_12 = _res_hit_msbsEqual_T_11[31:3]; // @[PMP.scala:60:27, :81:54]
wire [28:0] _res_hit_msbsEqual_T_13 = _res_hit_msbsEqual_T_7 ^ _res_hit_msbsEqual_T_12; // @[PMP.scala:81:{27,41,54}]
wire res_hit_msbsEqual_1 = _res_hit_msbsEqual_T_13 == 29'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67]
wire [2:0] _res_hit_lsbsLess_T_8 = _res_hit_lsbsLess_T_7; // @[PMP.scala:82:{25,42}]
wire [31:0] _res_hit_lsbsLess_T_10 = ~_res_hit_lsbsLess_T_9; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_lsbsLess_T_11 = {_res_hit_lsbsLess_T_10[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_lsbsLess_T_12 = ~_res_hit_lsbsLess_T_11; // @[PMP.scala:60:{27,48}]
wire [2:0] _res_hit_lsbsLess_T_13 = _res_hit_lsbsLess_T_12[2:0]; // @[PMP.scala:60:27, :82:64]
wire res_hit_lsbsLess_1 = _res_hit_lsbsLess_T_8 < _res_hit_lsbsLess_T_13; // @[PMP.scala:82:{42,53,64}]
wire _res_hit_T_9 = res_hit_msbsEqual_1 & res_hit_lsbsLess_1; // @[PMP.scala:81:69, :82:53, :83:30]
wire _res_hit_T_10 = res_hit_msbsLess_1 | _res_hit_T_9; // @[PMP.scala:80:39, :83:{16,30}]
wire _res_hit_T_11 = _res_hit_T_8 & _res_hit_T_10; // @[PMP.scala:83:16, :88:5, :94:48]
wire _res_hit_T_12 = _res_hit_T_2 & _res_hit_T_11; // @[PMP.scala:46:26, :94:48, :132:61]
wire res_hit = _res_hit_T ? _res_hit_T_1 : _res_hit_T_12; // @[PMP.scala:45:20, :71:16, :132:{8,61}]
wire _res_ignore_T = ~io_pmp_7_cfg_l_0; // @[PMP.scala:143:7, :164:29]
wire res_ignore = default_0 & _res_ignore_T; // @[PMP.scala:156:56, :164:{26,29}]
wire [2:0] _res_aligned_lsbMask_T_1 = _res_aligned_lsbMask_T[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] res_aligned_lsbMask = ~_res_aligned_lsbMask_T_1; // @[package.scala:243:{46,76}]
wire [31:0] _res_aligned_straddlesLowerBound_T_2 = ~_res_aligned_straddlesLowerBound_T_1; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_aligned_straddlesLowerBound_T_3 = {_res_aligned_straddlesLowerBound_T_2[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_aligned_straddlesLowerBound_T_4 = ~_res_aligned_straddlesLowerBound_T_3; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_aligned_straddlesLowerBound_T_5 = _res_aligned_straddlesLowerBound_T_4[31:3]; // @[PMP.scala:60:27, :123:67]
wire [28:0] _res_aligned_straddlesLowerBound_T_6 = _res_aligned_straddlesLowerBound_T ^ _res_aligned_straddlesLowerBound_T_5; // @[PMP.scala:123:{35,49,67}]
wire _res_aligned_straddlesLowerBound_T_7 = _res_aligned_straddlesLowerBound_T_6 == 29'h0; // @[PMP.scala:80:52, :81:54, :123:{49,67,82}]
wire [31:0] _res_aligned_straddlesLowerBound_T_9 = ~_res_aligned_straddlesLowerBound_T_8; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_aligned_straddlesLowerBound_T_10 = {_res_aligned_straddlesLowerBound_T_9[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_aligned_straddlesLowerBound_T_11 = ~_res_aligned_straddlesLowerBound_T_10; // @[PMP.scala:60:{27,48}]
wire [2:0] _res_aligned_straddlesLowerBound_T_12 = _res_aligned_straddlesLowerBound_T_11[2:0]; // @[PMP.scala:60:27, :123:108]
wire [2:0] _res_aligned_straddlesLowerBound_T_14 = ~_res_aligned_straddlesLowerBound_T_13; // @[PMP.scala:123:{127,129}]
wire [2:0] _res_aligned_straddlesLowerBound_T_15 = _res_aligned_straddlesLowerBound_T_12 & _res_aligned_straddlesLowerBound_T_14; // @[PMP.scala:123:{108,125,127}]
wire _res_aligned_straddlesLowerBound_T_16 = |_res_aligned_straddlesLowerBound_T_15; // @[PMP.scala:123:{125,147}]
wire res_aligned_straddlesLowerBound = _res_aligned_straddlesLowerBound_T_7 & _res_aligned_straddlesLowerBound_T_16; // @[PMP.scala:123:{82,90,147}]
wire [31:0] _res_aligned_straddlesUpperBound_T_2 = ~_res_aligned_straddlesUpperBound_T_1; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_aligned_straddlesUpperBound_T_3 = {_res_aligned_straddlesUpperBound_T_2[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_aligned_straddlesUpperBound_T_4 = ~_res_aligned_straddlesUpperBound_T_3; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_aligned_straddlesUpperBound_T_5 = _res_aligned_straddlesUpperBound_T_4[31:3]; // @[PMP.scala:60:27, :124:62]
wire [28:0] _res_aligned_straddlesUpperBound_T_6 = _res_aligned_straddlesUpperBound_T ^ _res_aligned_straddlesUpperBound_T_5; // @[PMP.scala:124:{35,49,62}]
wire _res_aligned_straddlesUpperBound_T_7 = _res_aligned_straddlesUpperBound_T_6 == 29'h0; // @[PMP.scala:80:52, :81:54, :123:67, :124:{49,77}]
wire [31:0] _res_aligned_straddlesUpperBound_T_9 = ~_res_aligned_straddlesUpperBound_T_8; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_aligned_straddlesUpperBound_T_10 = {_res_aligned_straddlesUpperBound_T_9[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_aligned_straddlesUpperBound_T_11 = ~_res_aligned_straddlesUpperBound_T_10; // @[PMP.scala:60:{27,48}]
wire [2:0] _res_aligned_straddlesUpperBound_T_12 = _res_aligned_straddlesUpperBound_T_11[2:0]; // @[PMP.scala:60:27, :124:98]
wire [2:0] _res_aligned_straddlesUpperBound_T_14 = _res_aligned_straddlesUpperBound_T_13 | res_aligned_lsbMask; // @[package.scala:243:46]
wire [2:0] _res_aligned_straddlesUpperBound_T_15 = _res_aligned_straddlesUpperBound_T_12 & _res_aligned_straddlesUpperBound_T_14; // @[PMP.scala:124:{98,115,136}]
wire _res_aligned_straddlesUpperBound_T_16 = |_res_aligned_straddlesUpperBound_T_15; // @[PMP.scala:124:{115,148}]
wire res_aligned_straddlesUpperBound = _res_aligned_straddlesUpperBound_T_7 & _res_aligned_straddlesUpperBound_T_16; // @[PMP.scala:124:{77,85,148}]
wire _res_aligned_rangeAligned_T = res_aligned_straddlesLowerBound | res_aligned_straddlesUpperBound; // @[PMP.scala:123:90, :124:85, :125:46]
wire res_aligned_rangeAligned = ~_res_aligned_rangeAligned_T; // @[PMP.scala:125:{24,46}]
wire [2:0] _res_aligned_pow2Aligned_T_1 = ~_res_aligned_pow2Aligned_T; // @[PMP.scala:126:{34,39}]
wire [2:0] _res_aligned_pow2Aligned_T_2 = res_aligned_lsbMask & _res_aligned_pow2Aligned_T_1; // @[package.scala:243:46]
wire res_aligned_pow2Aligned = _res_aligned_pow2Aligned_T_2 == 3'h0; // @[PMP.scala:82:64, :123:{108,125}, :126:{32,57}]
wire res_aligned = _res_aligned_T ? res_aligned_pow2Aligned : res_aligned_rangeAligned; // @[PMP.scala:45:20, :125:24, :126:57, :127:8]
wire _res_T = io_pmp_7_cfg_a_0 == 2'h0; // @[PMP.scala:143:7, :168:32]
wire _GEN_2 = io_pmp_7_cfg_a_0 == 2'h1; // @[PMP.scala:143:7, :168:32]
wire _res_T_1; // @[PMP.scala:168:32]
assign _res_T_1 = _GEN_2; // @[PMP.scala:168:32]
wire _res_T_20; // @[PMP.scala:177:61]
assign _res_T_20 = _GEN_2; // @[PMP.scala:168:32, :177:61]
wire _res_T_24; // @[PMP.scala:178:63]
assign _res_T_24 = _GEN_2; // @[PMP.scala:168:32, :178:63]
wire _GEN_3 = io_pmp_7_cfg_a_0 == 2'h2; // @[PMP.scala:143:7, :168:32]
wire _res_T_2; // @[PMP.scala:168:32]
assign _res_T_2 = _GEN_3; // @[PMP.scala:168:32]
wire _res_T_29; // @[PMP.scala:177:61]
assign _res_T_29 = _GEN_3; // @[PMP.scala:168:32, :177:61]
wire _res_T_33; // @[PMP.scala:178:63]
assign _res_T_33 = _GEN_3; // @[PMP.scala:168:32, :178:63]
wire _res_T_3 = &io_pmp_7_cfg_a_0; // @[PMP.scala:143:7, :168:32]
wire [1:0] _GEN_4 = {io_pmp_7_cfg_x_0, io_pmp_7_cfg_w_0}; // @[PMP.scala:143:7, :174:26]
wire [1:0] res_hi; // @[PMP.scala:174:26]
assign res_hi = _GEN_4; // @[PMP.scala:174:26]
wire [1:0] res_hi_1; // @[PMP.scala:174:26]
assign res_hi_1 = _GEN_4; // @[PMP.scala:174:26]
wire [1:0] res_hi_2; // @[PMP.scala:174:26]
assign res_hi_2 = _GEN_4; // @[PMP.scala:174:26]
wire [1:0] res_hi_3; // @[PMP.scala:174:26]
assign res_hi_3 = _GEN_4; // @[PMP.scala:174:26]
wire [1:0] res_hi_4; // @[PMP.scala:174:26]
assign res_hi_4 = _GEN_4; // @[PMP.scala:174:26]
wire [1:0] res_hi_5; // @[PMP.scala:174:26]
assign res_hi_5 = _GEN_4; // @[PMP.scala:174:26]
wire [2:0] _res_T_5 = {res_hi, io_pmp_7_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_6 = _res_T_5 == 3'h0; // @[PMP.scala:82:64, :123:{108,125}, :174:{26,60}]
wire [2:0] _res_T_7 = {res_hi_1, io_pmp_7_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_8 = _res_T_7 == 3'h1; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_9 = {res_hi_2, io_pmp_7_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_10 = _res_T_9 == 3'h3; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_11 = {res_hi_3, io_pmp_7_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_12 = _res_T_11 == 3'h4; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_13 = {res_hi_4, io_pmp_7_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_14 = _res_T_13 == 3'h5; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_15 = {res_hi_5, io_pmp_7_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_16 = &_res_T_15; // @[PMP.scala:174:{26,60}]
wire _res_T_17 = ~res_ignore; // @[PMP.scala:164:26, :177:22]
wire _res_T_18 = _res_T_17 & res_hit; // @[PMP.scala:132:8, :177:{22,30}]
wire _res_T_19 = _res_T_18 & res_aligned; // @[PMP.scala:127:8, :177:{30,37}]
wire _res_T_21 = _res_T_19 & _res_T_20; // @[PMP.scala:177:{37,48,61}]
wire _GEN_5 = io_pmp_7_cfg_l_0 & res_hit; // @[PMP.scala:132:8, :143:7, :178:32]
wire _res_T_22; // @[PMP.scala:178:32]
assign _res_T_22 = _GEN_5; // @[PMP.scala:178:32]
wire _res_T_31; // @[PMP.scala:178:32]
assign _res_T_31 = _GEN_5; // @[PMP.scala:178:32]
wire _res_T_40; // @[PMP.scala:178:32]
assign _res_T_40 = _GEN_5; // @[PMP.scala:178:32]
wire _res_T_23 = _res_T_22 & res_aligned; // @[PMP.scala:127:8, :178:{32,39}]
wire _res_T_25 = _res_T_23 & _res_T_24; // @[PMP.scala:178:{39,50,63}]
wire _res_T_26 = ~res_ignore; // @[PMP.scala:164:26, :177:22]
wire _res_T_27 = _res_T_26 & res_hit; // @[PMP.scala:132:8, :177:{22,30}]
wire _res_T_28 = _res_T_27 & res_aligned; // @[PMP.scala:127:8, :177:{30,37}]
wire _res_T_30 = _res_T_28 & _res_T_29; // @[PMP.scala:177:{37,48,61}]
wire _res_T_32 = _res_T_31 & res_aligned; // @[PMP.scala:127:8, :178:{32,39}]
wire _res_T_34 = _res_T_32 & _res_T_33; // @[PMP.scala:178:{39,50,63}]
wire _res_T_35 = ~res_ignore; // @[PMP.scala:164:26, :177:22]
wire _res_T_36 = _res_T_35 & res_hit; // @[PMP.scala:132:8, :177:{22,30}]
wire _res_T_37 = _res_T_36 & res_aligned; // @[PMP.scala:127:8, :177:{30,37}]
wire _res_T_38 = &io_pmp_7_cfg_a_0; // @[PMP.scala:143:7, :168:32, :177:61]
wire _res_T_39 = _res_T_37 & _res_T_38; // @[PMP.scala:177:{37,48,61}]
wire _res_T_41 = _res_T_40 & res_aligned; // @[PMP.scala:127:8, :178:{32,39}]
wire _res_T_42 = &io_pmp_7_cfg_a_0; // @[PMP.scala:143:7, :168:32, :178:63]
wire _res_T_43 = _res_T_41 & _res_T_42; // @[PMP.scala:178:{39,50,63}]
wire _res_cur_cfg_x_T_1; // @[PMP.scala:184:26]
wire _res_cur_cfg_w_T_1; // @[PMP.scala:183:26]
wire _res_cur_cfg_r_T_1; // @[PMP.scala:182:26]
wire res_cur_cfg_x; // @[PMP.scala:181:23]
wire res_cur_cfg_w; // @[PMP.scala:181:23]
wire res_cur_cfg_r; // @[PMP.scala:181:23]
wire _res_cur_cfg_r_T = io_pmp_7_cfg_r_0 | res_ignore; // @[PMP.scala:143:7, :164:26, :182:40]
assign _res_cur_cfg_r_T_1 = res_aligned & _res_cur_cfg_r_T; // @[PMP.scala:127:8, :182:{26,40}]
assign res_cur_cfg_r = _res_cur_cfg_r_T_1; // @[PMP.scala:181:23, :182:26]
wire _res_cur_cfg_w_T = io_pmp_7_cfg_w_0 | res_ignore; // @[PMP.scala:143:7, :164:26, :183:40]
assign _res_cur_cfg_w_T_1 = res_aligned & _res_cur_cfg_w_T; // @[PMP.scala:127:8, :183:{26,40}]
assign res_cur_cfg_w = _res_cur_cfg_w_T_1; // @[PMP.scala:181:23, :183:26]
wire _res_cur_cfg_x_T = io_pmp_7_cfg_x_0 | res_ignore; // @[PMP.scala:143:7, :164:26, :184:40]
assign _res_cur_cfg_x_T_1 = res_aligned & _res_cur_cfg_x_T; // @[PMP.scala:127:8, :184:{26,40}]
assign res_cur_cfg_x = _res_cur_cfg_x_T_1; // @[PMP.scala:181:23, :184:26]
wire _res_T_44_cfg_l = res_hit & res_cur_cfg_l; // @[PMP.scala:132:8, :181:23, :185:8]
wire [1:0] _res_T_44_cfg_a = res_hit ? res_cur_cfg_a : 2'h0; // @[PMP.scala:132:8, :181:23, :185:8]
wire _res_T_44_cfg_x = res_hit ? res_cur_cfg_x : pmp0_cfg_x; // @[PMP.scala:132:8, :157:22, :181:23, :185:8]
wire _res_T_44_cfg_w = res_hit ? res_cur_cfg_w : pmp0_cfg_w; // @[PMP.scala:132:8, :157:22, :181:23, :185:8]
wire _res_T_44_cfg_r = res_hit ? res_cur_cfg_r : pmp0_cfg_r; // @[PMP.scala:132:8, :157:22, :181:23, :185:8]
wire [29:0] _res_T_44_addr = res_hit ? res_cur_addr : 30'h0; // @[PMP.scala:132:8, :181:23, :185:8]
wire [31:0] _res_T_44_mask = res_hit ? res_cur_mask : 32'h0; // @[PMP.scala:132:8, :181:23, :185:8]
wire _res_hit_T_13 = io_pmp_6_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7]
wire _res_aligned_T_1 = io_pmp_6_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7]
wire [2:0] _res_hit_lsbMask_T_4 = _res_hit_lsbMask_T_3[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] _res_hit_lsbMask_T_5 = ~_res_hit_lsbMask_T_4; // @[package.scala:243:{46,76}]
wire [28:0] _res_hit_msbMatch_T_16 = io_pmp_6_mask_0[31:3]; // @[PMP.scala:68:26, :69:72, :143:7]
wire [2:0] _res_aligned_pow2Aligned_T_3 = io_pmp_6_mask_0[2:0]; // @[PMP.scala:68:26, :126:39, :143:7]
wire [31:0] res_hit_lsbMask_1 = {_res_hit_msbMatch_T_16, _res_aligned_pow2Aligned_T_3 | _res_hit_lsbMask_T_5}; // @[package.scala:243:46]
wire [31:0] _res_hit_msbMatch_T_12 = ~_res_hit_msbMatch_T_11; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_msbMatch_T_13 = {_res_hit_msbMatch_T_12[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbMatch_T_14 = ~_res_hit_msbMatch_T_13; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_hit_msbMatch_T_15 = _res_hit_msbMatch_T_14[31:3]; // @[PMP.scala:60:27, :69:53]
wire [28:0] _res_hit_msbMatch_T_17 = _res_hit_msbMatch_T_10 ^ _res_hit_msbMatch_T_15; // @[PMP.scala:63:47, :69:{29,53}]
wire [28:0] _res_hit_msbMatch_T_18 = ~_res_hit_msbMatch_T_16; // @[PMP.scala:63:54, :69:72]
wire [28:0] _res_hit_msbMatch_T_19 = _res_hit_msbMatch_T_17 & _res_hit_msbMatch_T_18; // @[PMP.scala:63:{47,52,54}]
wire res_hit_msbMatch_1 = _res_hit_msbMatch_T_19 == 29'h0; // @[PMP.scala:63:{52,58}, :80:52, :81:54, :123:67]
wire [31:0] _res_hit_lsbMatch_T_12 = ~_res_hit_lsbMatch_T_11; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_lsbMatch_T_13 = {_res_hit_lsbMatch_T_12[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_lsbMatch_T_14 = ~_res_hit_lsbMatch_T_13; // @[PMP.scala:60:{27,48}]
wire [2:0] _res_hit_lsbMatch_T_15 = _res_hit_lsbMatch_T_14[2:0]; // @[PMP.scala:60:27, :70:55]
wire [2:0] _res_hit_lsbMatch_T_16 = res_hit_lsbMask_1[2:0]; // @[PMP.scala:68:26, :70:80]
wire [2:0] _res_hit_lsbMatch_T_17 = _res_hit_lsbMatch_T_10 ^ _res_hit_lsbMatch_T_15; // @[PMP.scala:63:47, :70:{28,55}]
wire [2:0] _res_hit_lsbMatch_T_18 = ~_res_hit_lsbMatch_T_16; // @[PMP.scala:63:54, :70:80]
wire [2:0] _res_hit_lsbMatch_T_19 = _res_hit_lsbMatch_T_17 & _res_hit_lsbMatch_T_18; // @[PMP.scala:63:{47,52,54}]
wire res_hit_lsbMatch_1 = _res_hit_lsbMatch_T_19 == 3'h0; // @[PMP.scala:63:{52,58}, :82:64, :123:{108,125}]
wire _res_hit_T_14 = res_hit_msbMatch_1 & res_hit_lsbMatch_1; // @[PMP.scala:63:58, :71:16]
wire _res_hit_T_15 = io_pmp_6_cfg_a_0[0]; // @[PMP.scala:46:26, :143:7]
wire [2:0] _res_hit_T_17 = _res_hit_T_16[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] _res_hit_T_18 = ~_res_hit_T_17; // @[package.scala:243:{46,76}]
wire [31:0] _GEN_6 = {io_pmp_5_addr_0, 2'h0}; // @[PMP.scala:60:36, :143:7]
wire [31:0] _res_hit_msbsLess_T_13; // @[PMP.scala:60:36]
assign _res_hit_msbsLess_T_13 = _GEN_6; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbsEqual_T_15; // @[PMP.scala:60:36]
assign _res_hit_msbsEqual_T_15 = _GEN_6; // @[PMP.scala:60:36]
wire [31:0] _res_hit_lsbsLess_T_16; // @[PMP.scala:60:36]
assign _res_hit_lsbsLess_T_16 = _GEN_6; // @[PMP.scala:60:36]
wire [31:0] _res_aligned_straddlesLowerBound_T_18; // @[PMP.scala:60:36]
assign _res_aligned_straddlesLowerBound_T_18 = _GEN_6; // @[PMP.scala:60:36]
wire [31:0] _res_aligned_straddlesLowerBound_T_25; // @[PMP.scala:60:36]
assign _res_aligned_straddlesLowerBound_T_25 = _GEN_6; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbMatch_T_21; // @[PMP.scala:60:36]
assign _res_hit_msbMatch_T_21 = _GEN_6; // @[PMP.scala:60:36]
wire [31:0] _res_hit_lsbMatch_T_21; // @[PMP.scala:60:36]
assign _res_hit_lsbMatch_T_21 = _GEN_6; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbsLess_T_31; // @[PMP.scala:60:36]
assign _res_hit_msbsLess_T_31 = _GEN_6; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbsEqual_T_36; // @[PMP.scala:60:36]
assign _res_hit_msbsEqual_T_36 = _GEN_6; // @[PMP.scala:60:36]
wire [31:0] _res_hit_lsbsLess_T_37; // @[PMP.scala:60:36]
assign _res_hit_lsbsLess_T_37 = _GEN_6; // @[PMP.scala:60:36]
wire [31:0] _res_aligned_straddlesUpperBound_T_35; // @[PMP.scala:60:36]
assign _res_aligned_straddlesUpperBound_T_35 = _GEN_6; // @[PMP.scala:60:36]
wire [31:0] _res_aligned_straddlesUpperBound_T_42; // @[PMP.scala:60:36]
assign _res_aligned_straddlesUpperBound_T_42 = _GEN_6; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbsLess_T_14 = ~_res_hit_msbsLess_T_13; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_msbsLess_T_15 = {_res_hit_msbsLess_T_14[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbsLess_T_16 = ~_res_hit_msbsLess_T_15; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_hit_msbsLess_T_17 = _res_hit_msbsLess_T_16[31:3]; // @[PMP.scala:60:27, :80:52]
wire res_hit_msbsLess_2 = _res_hit_msbsLess_T_12 < _res_hit_msbsLess_T_17; // @[PMP.scala:80:{25,39,52}]
wire [31:0] _res_hit_msbsEqual_T_16 = ~_res_hit_msbsEqual_T_15; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_msbsEqual_T_17 = {_res_hit_msbsEqual_T_16[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbsEqual_T_18 = ~_res_hit_msbsEqual_T_17; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_hit_msbsEqual_T_19 = _res_hit_msbsEqual_T_18[31:3]; // @[PMP.scala:60:27, :81:54]
wire [28:0] _res_hit_msbsEqual_T_20 = _res_hit_msbsEqual_T_14 ^ _res_hit_msbsEqual_T_19; // @[PMP.scala:81:{27,41,54}]
wire res_hit_msbsEqual_2 = _res_hit_msbsEqual_T_20 == 29'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67]
wire [2:0] _res_hit_lsbsLess_T_15 = _res_hit_lsbsLess_T_14 | _res_hit_T_18; // @[package.scala:243:46]
wire [31:0] _res_hit_lsbsLess_T_17 = ~_res_hit_lsbsLess_T_16; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_lsbsLess_T_18 = {_res_hit_lsbsLess_T_17[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_lsbsLess_T_19 = ~_res_hit_lsbsLess_T_18; // @[PMP.scala:60:{27,48}]
wire [2:0] _res_hit_lsbsLess_T_20 = _res_hit_lsbsLess_T_19[2:0]; // @[PMP.scala:60:27, :82:64]
wire res_hit_lsbsLess_2 = _res_hit_lsbsLess_T_15 < _res_hit_lsbsLess_T_20; // @[PMP.scala:82:{42,53,64}]
wire _res_hit_T_19 = res_hit_msbsEqual_2 & res_hit_lsbsLess_2; // @[PMP.scala:81:69, :82:53, :83:30]
wire _res_hit_T_20 = res_hit_msbsLess_2 | _res_hit_T_19; // @[PMP.scala:80:39, :83:{16,30}]
wire _res_hit_T_21 = ~_res_hit_T_20; // @[PMP.scala:83:16, :88:5]
wire [31:0] _res_hit_msbsLess_T_20 = ~_res_hit_msbsLess_T_19; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_msbsLess_T_21 = {_res_hit_msbsLess_T_20[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbsLess_T_22 = ~_res_hit_msbsLess_T_21; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_hit_msbsLess_T_23 = _res_hit_msbsLess_T_22[31:3]; // @[PMP.scala:60:27, :80:52]
wire res_hit_msbsLess_3 = _res_hit_msbsLess_T_18 < _res_hit_msbsLess_T_23; // @[PMP.scala:80:{25,39,52}]
wire [31:0] _res_hit_msbsEqual_T_23 = ~_res_hit_msbsEqual_T_22; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_msbsEqual_T_24 = {_res_hit_msbsEqual_T_23[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbsEqual_T_25 = ~_res_hit_msbsEqual_T_24; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_hit_msbsEqual_T_26 = _res_hit_msbsEqual_T_25[31:3]; // @[PMP.scala:60:27, :81:54]
wire [28:0] _res_hit_msbsEqual_T_27 = _res_hit_msbsEqual_T_21 ^ _res_hit_msbsEqual_T_26; // @[PMP.scala:81:{27,41,54}]
wire res_hit_msbsEqual_3 = _res_hit_msbsEqual_T_27 == 29'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67]
wire [2:0] _res_hit_lsbsLess_T_22 = _res_hit_lsbsLess_T_21; // @[PMP.scala:82:{25,42}]
wire [31:0] _res_hit_lsbsLess_T_24 = ~_res_hit_lsbsLess_T_23; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_lsbsLess_T_25 = {_res_hit_lsbsLess_T_24[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_lsbsLess_T_26 = ~_res_hit_lsbsLess_T_25; // @[PMP.scala:60:{27,48}]
wire [2:0] _res_hit_lsbsLess_T_27 = _res_hit_lsbsLess_T_26[2:0]; // @[PMP.scala:60:27, :82:64]
wire res_hit_lsbsLess_3 = _res_hit_lsbsLess_T_22 < _res_hit_lsbsLess_T_27; // @[PMP.scala:82:{42,53,64}]
wire _res_hit_T_22 = res_hit_msbsEqual_3 & res_hit_lsbsLess_3; // @[PMP.scala:81:69, :82:53, :83:30]
wire _res_hit_T_23 = res_hit_msbsLess_3 | _res_hit_T_22; // @[PMP.scala:80:39, :83:{16,30}]
wire _res_hit_T_24 = _res_hit_T_21 & _res_hit_T_23; // @[PMP.scala:83:16, :88:5, :94:48]
wire _res_hit_T_25 = _res_hit_T_15 & _res_hit_T_24; // @[PMP.scala:46:26, :94:48, :132:61]
wire res_hit_1 = _res_hit_T_13 ? _res_hit_T_14 : _res_hit_T_25; // @[PMP.scala:45:20, :71:16, :132:{8,61}]
wire _res_ignore_T_1 = ~io_pmp_6_cfg_l_0; // @[PMP.scala:143:7, :164:29]
wire res_ignore_1 = default_0 & _res_ignore_T_1; // @[PMP.scala:156:56, :164:{26,29}]
wire [2:0] _res_aligned_lsbMask_T_3 = _res_aligned_lsbMask_T_2[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] res_aligned_lsbMask_1 = ~_res_aligned_lsbMask_T_3; // @[package.scala:243:{46,76}]
wire [31:0] _res_aligned_straddlesLowerBound_T_19 = ~_res_aligned_straddlesLowerBound_T_18; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_aligned_straddlesLowerBound_T_20 = {_res_aligned_straddlesLowerBound_T_19[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_aligned_straddlesLowerBound_T_21 = ~_res_aligned_straddlesLowerBound_T_20; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_aligned_straddlesLowerBound_T_22 = _res_aligned_straddlesLowerBound_T_21[31:3]; // @[PMP.scala:60:27, :123:67]
wire [28:0] _res_aligned_straddlesLowerBound_T_23 = _res_aligned_straddlesLowerBound_T_17 ^ _res_aligned_straddlesLowerBound_T_22; // @[PMP.scala:123:{35,49,67}]
wire _res_aligned_straddlesLowerBound_T_24 = _res_aligned_straddlesLowerBound_T_23 == 29'h0; // @[PMP.scala:80:52, :81:54, :123:{49,67,82}]
wire [31:0] _res_aligned_straddlesLowerBound_T_26 = ~_res_aligned_straddlesLowerBound_T_25; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_aligned_straddlesLowerBound_T_27 = {_res_aligned_straddlesLowerBound_T_26[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_aligned_straddlesLowerBound_T_28 = ~_res_aligned_straddlesLowerBound_T_27; // @[PMP.scala:60:{27,48}]
wire [2:0] _res_aligned_straddlesLowerBound_T_29 = _res_aligned_straddlesLowerBound_T_28[2:0]; // @[PMP.scala:60:27, :123:108]
wire [2:0] _res_aligned_straddlesLowerBound_T_31 = ~_res_aligned_straddlesLowerBound_T_30; // @[PMP.scala:123:{127,129}]
wire [2:0] _res_aligned_straddlesLowerBound_T_32 = _res_aligned_straddlesLowerBound_T_29 & _res_aligned_straddlesLowerBound_T_31; // @[PMP.scala:123:{108,125,127}]
wire _res_aligned_straddlesLowerBound_T_33 = |_res_aligned_straddlesLowerBound_T_32; // @[PMP.scala:123:{125,147}]
wire res_aligned_straddlesLowerBound_1 = _res_aligned_straddlesLowerBound_T_24 & _res_aligned_straddlesLowerBound_T_33; // @[PMP.scala:123:{82,90,147}]
wire [31:0] _res_aligned_straddlesUpperBound_T_19 = ~_res_aligned_straddlesUpperBound_T_18; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_aligned_straddlesUpperBound_T_20 = {_res_aligned_straddlesUpperBound_T_19[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_aligned_straddlesUpperBound_T_21 = ~_res_aligned_straddlesUpperBound_T_20; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_aligned_straddlesUpperBound_T_22 = _res_aligned_straddlesUpperBound_T_21[31:3]; // @[PMP.scala:60:27, :124:62]
wire [28:0] _res_aligned_straddlesUpperBound_T_23 = _res_aligned_straddlesUpperBound_T_17 ^ _res_aligned_straddlesUpperBound_T_22; // @[PMP.scala:124:{35,49,62}]
wire _res_aligned_straddlesUpperBound_T_24 = _res_aligned_straddlesUpperBound_T_23 == 29'h0; // @[PMP.scala:80:52, :81:54, :123:67, :124:{49,77}]
wire [31:0] _res_aligned_straddlesUpperBound_T_26 = ~_res_aligned_straddlesUpperBound_T_25; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_aligned_straddlesUpperBound_T_27 = {_res_aligned_straddlesUpperBound_T_26[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_aligned_straddlesUpperBound_T_28 = ~_res_aligned_straddlesUpperBound_T_27; // @[PMP.scala:60:{27,48}]
wire [2:0] _res_aligned_straddlesUpperBound_T_29 = _res_aligned_straddlesUpperBound_T_28[2:0]; // @[PMP.scala:60:27, :124:98]
wire [2:0] _res_aligned_straddlesUpperBound_T_31 = _res_aligned_straddlesUpperBound_T_30 | res_aligned_lsbMask_1; // @[package.scala:243:46]
wire [2:0] _res_aligned_straddlesUpperBound_T_32 = _res_aligned_straddlesUpperBound_T_29 & _res_aligned_straddlesUpperBound_T_31; // @[PMP.scala:124:{98,115,136}]
wire _res_aligned_straddlesUpperBound_T_33 = |_res_aligned_straddlesUpperBound_T_32; // @[PMP.scala:124:{115,148}]
wire res_aligned_straddlesUpperBound_1 = _res_aligned_straddlesUpperBound_T_24 & _res_aligned_straddlesUpperBound_T_33; // @[PMP.scala:124:{77,85,148}]
wire _res_aligned_rangeAligned_T_1 = res_aligned_straddlesLowerBound_1 | res_aligned_straddlesUpperBound_1; // @[PMP.scala:123:90, :124:85, :125:46]
wire res_aligned_rangeAligned_1 = ~_res_aligned_rangeAligned_T_1; // @[PMP.scala:125:{24,46}]
wire [2:0] _res_aligned_pow2Aligned_T_4 = ~_res_aligned_pow2Aligned_T_3; // @[PMP.scala:126:{34,39}]
wire [2:0] _res_aligned_pow2Aligned_T_5 = res_aligned_lsbMask_1 & _res_aligned_pow2Aligned_T_4; // @[package.scala:243:46]
wire res_aligned_pow2Aligned_1 = _res_aligned_pow2Aligned_T_5 == 3'h0; // @[PMP.scala:82:64, :123:{108,125}, :126:{32,57}]
wire res_aligned_1 = _res_aligned_T_1 ? res_aligned_pow2Aligned_1 : res_aligned_rangeAligned_1; // @[PMP.scala:45:20, :125:24, :126:57, :127:8]
wire _res_T_45 = io_pmp_6_cfg_a_0 == 2'h0; // @[PMP.scala:143:7, :168:32]
wire _GEN_7 = io_pmp_6_cfg_a_0 == 2'h1; // @[PMP.scala:143:7, :168:32]
wire _res_T_46; // @[PMP.scala:168:32]
assign _res_T_46 = _GEN_7; // @[PMP.scala:168:32]
wire _res_T_65; // @[PMP.scala:177:61]
assign _res_T_65 = _GEN_7; // @[PMP.scala:168:32, :177:61]
wire _res_T_69; // @[PMP.scala:178:63]
assign _res_T_69 = _GEN_7; // @[PMP.scala:168:32, :178:63]
wire _GEN_8 = io_pmp_6_cfg_a_0 == 2'h2; // @[PMP.scala:143:7, :168:32]
wire _res_T_47; // @[PMP.scala:168:32]
assign _res_T_47 = _GEN_8; // @[PMP.scala:168:32]
wire _res_T_74; // @[PMP.scala:177:61]
assign _res_T_74 = _GEN_8; // @[PMP.scala:168:32, :177:61]
wire _res_T_78; // @[PMP.scala:178:63]
assign _res_T_78 = _GEN_8; // @[PMP.scala:168:32, :178:63]
wire _res_T_48 = &io_pmp_6_cfg_a_0; // @[PMP.scala:143:7, :168:32]
wire [1:0] _GEN_9 = {io_pmp_6_cfg_x_0, io_pmp_6_cfg_w_0}; // @[PMP.scala:143:7, :174:26]
wire [1:0] res_hi_6; // @[PMP.scala:174:26]
assign res_hi_6 = _GEN_9; // @[PMP.scala:174:26]
wire [1:0] res_hi_7; // @[PMP.scala:174:26]
assign res_hi_7 = _GEN_9; // @[PMP.scala:174:26]
wire [1:0] res_hi_8; // @[PMP.scala:174:26]
assign res_hi_8 = _GEN_9; // @[PMP.scala:174:26]
wire [1:0] res_hi_9; // @[PMP.scala:174:26]
assign res_hi_9 = _GEN_9; // @[PMP.scala:174:26]
wire [1:0] res_hi_10; // @[PMP.scala:174:26]
assign res_hi_10 = _GEN_9; // @[PMP.scala:174:26]
wire [1:0] res_hi_11; // @[PMP.scala:174:26]
assign res_hi_11 = _GEN_9; // @[PMP.scala:174:26]
wire [2:0] _res_T_50 = {res_hi_6, io_pmp_6_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_51 = _res_T_50 == 3'h0; // @[PMP.scala:82:64, :123:{108,125}, :174:{26,60}]
wire [2:0] _res_T_52 = {res_hi_7, io_pmp_6_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_53 = _res_T_52 == 3'h1; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_54 = {res_hi_8, io_pmp_6_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_55 = _res_T_54 == 3'h3; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_56 = {res_hi_9, io_pmp_6_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_57 = _res_T_56 == 3'h4; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_58 = {res_hi_10, io_pmp_6_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_59 = _res_T_58 == 3'h5; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_60 = {res_hi_11, io_pmp_6_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_61 = &_res_T_60; // @[PMP.scala:174:{26,60}]
wire _res_T_62 = ~res_ignore_1; // @[PMP.scala:164:26, :177:22]
wire _res_T_63 = _res_T_62 & res_hit_1; // @[PMP.scala:132:8, :177:{22,30}]
wire _res_T_64 = _res_T_63 & res_aligned_1; // @[PMP.scala:127:8, :177:{30,37}]
wire _res_T_66 = _res_T_64 & _res_T_65; // @[PMP.scala:177:{37,48,61}]
wire _GEN_10 = io_pmp_6_cfg_l_0 & res_hit_1; // @[PMP.scala:132:8, :143:7, :178:32]
wire _res_T_67; // @[PMP.scala:178:32]
assign _res_T_67 = _GEN_10; // @[PMP.scala:178:32]
wire _res_T_76; // @[PMP.scala:178:32]
assign _res_T_76 = _GEN_10; // @[PMP.scala:178:32]
wire _res_T_85; // @[PMP.scala:178:32]
assign _res_T_85 = _GEN_10; // @[PMP.scala:178:32]
wire _res_T_68 = _res_T_67 & res_aligned_1; // @[PMP.scala:127:8, :178:{32,39}]
wire _res_T_70 = _res_T_68 & _res_T_69; // @[PMP.scala:178:{39,50,63}]
wire _res_T_71 = ~res_ignore_1; // @[PMP.scala:164:26, :177:22]
wire _res_T_72 = _res_T_71 & res_hit_1; // @[PMP.scala:132:8, :177:{22,30}]
wire _res_T_73 = _res_T_72 & res_aligned_1; // @[PMP.scala:127:8, :177:{30,37}]
wire _res_T_75 = _res_T_73 & _res_T_74; // @[PMP.scala:177:{37,48,61}]
wire _res_T_77 = _res_T_76 & res_aligned_1; // @[PMP.scala:127:8, :178:{32,39}]
wire _res_T_79 = _res_T_77 & _res_T_78; // @[PMP.scala:178:{39,50,63}]
wire _res_T_80 = ~res_ignore_1; // @[PMP.scala:164:26, :177:22]
wire _res_T_81 = _res_T_80 & res_hit_1; // @[PMP.scala:132:8, :177:{22,30}]
wire _res_T_82 = _res_T_81 & res_aligned_1; // @[PMP.scala:127:8, :177:{30,37}]
wire _res_T_83 = &io_pmp_6_cfg_a_0; // @[PMP.scala:143:7, :168:32, :177:61]
wire _res_T_84 = _res_T_82 & _res_T_83; // @[PMP.scala:177:{37,48,61}]
wire _res_T_86 = _res_T_85 & res_aligned_1; // @[PMP.scala:127:8, :178:{32,39}]
wire _res_T_87 = &io_pmp_6_cfg_a_0; // @[PMP.scala:143:7, :168:32, :178:63]
wire _res_T_88 = _res_T_86 & _res_T_87; // @[PMP.scala:178:{39,50,63}]
wire _res_cur_cfg_x_T_3; // @[PMP.scala:184:26]
wire _res_cur_cfg_w_T_3; // @[PMP.scala:183:26]
wire _res_cur_cfg_r_T_3; // @[PMP.scala:182:26]
wire res_cur_1_cfg_x; // @[PMP.scala:181:23]
wire res_cur_1_cfg_w; // @[PMP.scala:181:23]
wire res_cur_1_cfg_r; // @[PMP.scala:181:23]
wire _res_cur_cfg_r_T_2 = io_pmp_6_cfg_r_0 | res_ignore_1; // @[PMP.scala:143:7, :164:26, :182:40]
assign _res_cur_cfg_r_T_3 = res_aligned_1 & _res_cur_cfg_r_T_2; // @[PMP.scala:127:8, :182:{26,40}]
assign res_cur_1_cfg_r = _res_cur_cfg_r_T_3; // @[PMP.scala:181:23, :182:26]
wire _res_cur_cfg_w_T_2 = io_pmp_6_cfg_w_0 | res_ignore_1; // @[PMP.scala:143:7, :164:26, :183:40]
assign _res_cur_cfg_w_T_3 = res_aligned_1 & _res_cur_cfg_w_T_2; // @[PMP.scala:127:8, :183:{26,40}]
assign res_cur_1_cfg_w = _res_cur_cfg_w_T_3; // @[PMP.scala:181:23, :183:26]
wire _res_cur_cfg_x_T_2 = io_pmp_6_cfg_x_0 | res_ignore_1; // @[PMP.scala:143:7, :164:26, :184:40]
assign _res_cur_cfg_x_T_3 = res_aligned_1 & _res_cur_cfg_x_T_2; // @[PMP.scala:127:8, :184:{26,40}]
assign res_cur_1_cfg_x = _res_cur_cfg_x_T_3; // @[PMP.scala:181:23, :184:26]
wire _res_T_89_cfg_l = res_hit_1 ? res_cur_1_cfg_l : _res_T_44_cfg_l; // @[PMP.scala:132:8, :181:23, :185:8]
wire [1:0] _res_T_89_cfg_a = res_hit_1 ? res_cur_1_cfg_a : _res_T_44_cfg_a; // @[PMP.scala:132:8, :181:23, :185:8]
wire _res_T_89_cfg_x = res_hit_1 ? res_cur_1_cfg_x : _res_T_44_cfg_x; // @[PMP.scala:132:8, :181:23, :185:8]
wire _res_T_89_cfg_w = res_hit_1 ? res_cur_1_cfg_w : _res_T_44_cfg_w; // @[PMP.scala:132:8, :181:23, :185:8]
wire _res_T_89_cfg_r = res_hit_1 ? res_cur_1_cfg_r : _res_T_44_cfg_r; // @[PMP.scala:132:8, :181:23, :185:8]
wire [29:0] _res_T_89_addr = res_hit_1 ? res_cur_1_addr : _res_T_44_addr; // @[PMP.scala:132:8, :181:23, :185:8]
wire [31:0] _res_T_89_mask = res_hit_1 ? res_cur_1_mask : _res_T_44_mask; // @[PMP.scala:132:8, :181:23, :185:8]
wire _res_hit_T_26 = io_pmp_5_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7]
wire _res_aligned_T_2 = io_pmp_5_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7]
wire [2:0] _res_hit_lsbMask_T_7 = _res_hit_lsbMask_T_6[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] _res_hit_lsbMask_T_8 = ~_res_hit_lsbMask_T_7; // @[package.scala:243:{46,76}]
wire [28:0] _res_hit_msbMatch_T_26 = io_pmp_5_mask_0[31:3]; // @[PMP.scala:68:26, :69:72, :143:7]
wire [2:0] _res_aligned_pow2Aligned_T_6 = io_pmp_5_mask_0[2:0]; // @[PMP.scala:68:26, :126:39, :143:7]
wire [31:0] res_hit_lsbMask_2 = {_res_hit_msbMatch_T_26, _res_aligned_pow2Aligned_T_6 | _res_hit_lsbMask_T_8}; // @[package.scala:243:46]
wire [31:0] _res_hit_msbMatch_T_22 = ~_res_hit_msbMatch_T_21; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_msbMatch_T_23 = {_res_hit_msbMatch_T_22[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbMatch_T_24 = ~_res_hit_msbMatch_T_23; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_hit_msbMatch_T_25 = _res_hit_msbMatch_T_24[31:3]; // @[PMP.scala:60:27, :69:53]
wire [28:0] _res_hit_msbMatch_T_27 = _res_hit_msbMatch_T_20 ^ _res_hit_msbMatch_T_25; // @[PMP.scala:63:47, :69:{29,53}]
wire [28:0] _res_hit_msbMatch_T_28 = ~_res_hit_msbMatch_T_26; // @[PMP.scala:63:54, :69:72]
wire [28:0] _res_hit_msbMatch_T_29 = _res_hit_msbMatch_T_27 & _res_hit_msbMatch_T_28; // @[PMP.scala:63:{47,52,54}]
wire res_hit_msbMatch_2 = _res_hit_msbMatch_T_29 == 29'h0; // @[PMP.scala:63:{52,58}, :80:52, :81:54, :123:67]
wire [31:0] _res_hit_lsbMatch_T_22 = ~_res_hit_lsbMatch_T_21; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_lsbMatch_T_23 = {_res_hit_lsbMatch_T_22[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_lsbMatch_T_24 = ~_res_hit_lsbMatch_T_23; // @[PMP.scala:60:{27,48}]
wire [2:0] _res_hit_lsbMatch_T_25 = _res_hit_lsbMatch_T_24[2:0]; // @[PMP.scala:60:27, :70:55]
wire [2:0] _res_hit_lsbMatch_T_26 = res_hit_lsbMask_2[2:0]; // @[PMP.scala:68:26, :70:80]
wire [2:0] _res_hit_lsbMatch_T_27 = _res_hit_lsbMatch_T_20 ^ _res_hit_lsbMatch_T_25; // @[PMP.scala:63:47, :70:{28,55}]
wire [2:0] _res_hit_lsbMatch_T_28 = ~_res_hit_lsbMatch_T_26; // @[PMP.scala:63:54, :70:80]
wire [2:0] _res_hit_lsbMatch_T_29 = _res_hit_lsbMatch_T_27 & _res_hit_lsbMatch_T_28; // @[PMP.scala:63:{47,52,54}]
wire res_hit_lsbMatch_2 = _res_hit_lsbMatch_T_29 == 3'h0; // @[PMP.scala:63:{52,58}, :82:64, :123:{108,125}]
wire _res_hit_T_27 = res_hit_msbMatch_2 & res_hit_lsbMatch_2; // @[PMP.scala:63:58, :71:16]
wire _res_hit_T_28 = io_pmp_5_cfg_a_0[0]; // @[PMP.scala:46:26, :143:7]
wire [2:0] _res_hit_T_30 = _res_hit_T_29[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] _res_hit_T_31 = ~_res_hit_T_30; // @[package.scala:243:{46,76}]
wire [31:0] _GEN_11 = {io_pmp_4_addr_0, 2'h0}; // @[PMP.scala:60:36, :143:7]
wire [31:0] _res_hit_msbsLess_T_25; // @[PMP.scala:60:36]
assign _res_hit_msbsLess_T_25 = _GEN_11; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbsEqual_T_29; // @[PMP.scala:60:36]
assign _res_hit_msbsEqual_T_29 = _GEN_11; // @[PMP.scala:60:36]
wire [31:0] _res_hit_lsbsLess_T_30; // @[PMP.scala:60:36]
assign _res_hit_lsbsLess_T_30 = _GEN_11; // @[PMP.scala:60:36]
wire [31:0] _res_aligned_straddlesLowerBound_T_35; // @[PMP.scala:60:36]
assign _res_aligned_straddlesLowerBound_T_35 = _GEN_11; // @[PMP.scala:60:36]
wire [31:0] _res_aligned_straddlesLowerBound_T_42; // @[PMP.scala:60:36]
assign _res_aligned_straddlesLowerBound_T_42 = _GEN_11; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbMatch_T_31; // @[PMP.scala:60:36]
assign _res_hit_msbMatch_T_31 = _GEN_11; // @[PMP.scala:60:36]
wire [31:0] _res_hit_lsbMatch_T_31; // @[PMP.scala:60:36]
assign _res_hit_lsbMatch_T_31 = _GEN_11; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbsLess_T_43; // @[PMP.scala:60:36]
assign _res_hit_msbsLess_T_43 = _GEN_11; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbsEqual_T_50; // @[PMP.scala:60:36]
assign _res_hit_msbsEqual_T_50 = _GEN_11; // @[PMP.scala:60:36]
wire [31:0] _res_hit_lsbsLess_T_51; // @[PMP.scala:60:36]
assign _res_hit_lsbsLess_T_51 = _GEN_11; // @[PMP.scala:60:36]
wire [31:0] _res_aligned_straddlesUpperBound_T_52; // @[PMP.scala:60:36]
assign _res_aligned_straddlesUpperBound_T_52 = _GEN_11; // @[PMP.scala:60:36]
wire [31:0] _res_aligned_straddlesUpperBound_T_59; // @[PMP.scala:60:36]
assign _res_aligned_straddlesUpperBound_T_59 = _GEN_11; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbsLess_T_26 = ~_res_hit_msbsLess_T_25; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_msbsLess_T_27 = {_res_hit_msbsLess_T_26[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbsLess_T_28 = ~_res_hit_msbsLess_T_27; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_hit_msbsLess_T_29 = _res_hit_msbsLess_T_28[31:3]; // @[PMP.scala:60:27, :80:52]
wire res_hit_msbsLess_4 = _res_hit_msbsLess_T_24 < _res_hit_msbsLess_T_29; // @[PMP.scala:80:{25,39,52}]
wire [31:0] _res_hit_msbsEqual_T_30 = ~_res_hit_msbsEqual_T_29; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_msbsEqual_T_31 = {_res_hit_msbsEqual_T_30[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbsEqual_T_32 = ~_res_hit_msbsEqual_T_31; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_hit_msbsEqual_T_33 = _res_hit_msbsEqual_T_32[31:3]; // @[PMP.scala:60:27, :81:54]
wire [28:0] _res_hit_msbsEqual_T_34 = _res_hit_msbsEqual_T_28 ^ _res_hit_msbsEqual_T_33; // @[PMP.scala:81:{27,41,54}]
wire res_hit_msbsEqual_4 = _res_hit_msbsEqual_T_34 == 29'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67]
wire [2:0] _res_hit_lsbsLess_T_29 = _res_hit_lsbsLess_T_28 | _res_hit_T_31; // @[package.scala:243:46]
wire [31:0] _res_hit_lsbsLess_T_31 = ~_res_hit_lsbsLess_T_30; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_lsbsLess_T_32 = {_res_hit_lsbsLess_T_31[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_lsbsLess_T_33 = ~_res_hit_lsbsLess_T_32; // @[PMP.scala:60:{27,48}]
wire [2:0] _res_hit_lsbsLess_T_34 = _res_hit_lsbsLess_T_33[2:0]; // @[PMP.scala:60:27, :82:64]
wire res_hit_lsbsLess_4 = _res_hit_lsbsLess_T_29 < _res_hit_lsbsLess_T_34; // @[PMP.scala:82:{42,53,64}]
wire _res_hit_T_32 = res_hit_msbsEqual_4 & res_hit_lsbsLess_4; // @[PMP.scala:81:69, :82:53, :83:30]
wire _res_hit_T_33 = res_hit_msbsLess_4 | _res_hit_T_32; // @[PMP.scala:80:39, :83:{16,30}]
wire _res_hit_T_34 = ~_res_hit_T_33; // @[PMP.scala:83:16, :88:5]
wire [31:0] _res_hit_msbsLess_T_32 = ~_res_hit_msbsLess_T_31; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_msbsLess_T_33 = {_res_hit_msbsLess_T_32[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbsLess_T_34 = ~_res_hit_msbsLess_T_33; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_hit_msbsLess_T_35 = _res_hit_msbsLess_T_34[31:3]; // @[PMP.scala:60:27, :80:52]
wire res_hit_msbsLess_5 = _res_hit_msbsLess_T_30 < _res_hit_msbsLess_T_35; // @[PMP.scala:80:{25,39,52}]
wire [31:0] _res_hit_msbsEqual_T_37 = ~_res_hit_msbsEqual_T_36; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_msbsEqual_T_38 = {_res_hit_msbsEqual_T_37[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbsEqual_T_39 = ~_res_hit_msbsEqual_T_38; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_hit_msbsEqual_T_40 = _res_hit_msbsEqual_T_39[31:3]; // @[PMP.scala:60:27, :81:54]
wire [28:0] _res_hit_msbsEqual_T_41 = _res_hit_msbsEqual_T_35 ^ _res_hit_msbsEqual_T_40; // @[PMP.scala:81:{27,41,54}]
wire res_hit_msbsEqual_5 = _res_hit_msbsEqual_T_41 == 29'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67]
wire [2:0] _res_hit_lsbsLess_T_36 = _res_hit_lsbsLess_T_35; // @[PMP.scala:82:{25,42}]
wire [31:0] _res_hit_lsbsLess_T_38 = ~_res_hit_lsbsLess_T_37; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_lsbsLess_T_39 = {_res_hit_lsbsLess_T_38[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_lsbsLess_T_40 = ~_res_hit_lsbsLess_T_39; // @[PMP.scala:60:{27,48}]
wire [2:0] _res_hit_lsbsLess_T_41 = _res_hit_lsbsLess_T_40[2:0]; // @[PMP.scala:60:27, :82:64]
wire res_hit_lsbsLess_5 = _res_hit_lsbsLess_T_36 < _res_hit_lsbsLess_T_41; // @[PMP.scala:82:{42,53,64}]
wire _res_hit_T_35 = res_hit_msbsEqual_5 & res_hit_lsbsLess_5; // @[PMP.scala:81:69, :82:53, :83:30]
wire _res_hit_T_36 = res_hit_msbsLess_5 | _res_hit_T_35; // @[PMP.scala:80:39, :83:{16,30}]
wire _res_hit_T_37 = _res_hit_T_34 & _res_hit_T_36; // @[PMP.scala:83:16, :88:5, :94:48]
wire _res_hit_T_38 = _res_hit_T_28 & _res_hit_T_37; // @[PMP.scala:46:26, :94:48, :132:61]
wire res_hit_2 = _res_hit_T_26 ? _res_hit_T_27 : _res_hit_T_38; // @[PMP.scala:45:20, :71:16, :132:{8,61}]
wire _res_ignore_T_2 = ~io_pmp_5_cfg_l_0; // @[PMP.scala:143:7, :164:29]
wire res_ignore_2 = default_0 & _res_ignore_T_2; // @[PMP.scala:156:56, :164:{26,29}]
wire [2:0] _res_aligned_lsbMask_T_5 = _res_aligned_lsbMask_T_4[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] res_aligned_lsbMask_2 = ~_res_aligned_lsbMask_T_5; // @[package.scala:243:{46,76}]
wire [31:0] _res_aligned_straddlesLowerBound_T_36 = ~_res_aligned_straddlesLowerBound_T_35; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_aligned_straddlesLowerBound_T_37 = {_res_aligned_straddlesLowerBound_T_36[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_aligned_straddlesLowerBound_T_38 = ~_res_aligned_straddlesLowerBound_T_37; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_aligned_straddlesLowerBound_T_39 = _res_aligned_straddlesLowerBound_T_38[31:3]; // @[PMP.scala:60:27, :123:67]
wire [28:0] _res_aligned_straddlesLowerBound_T_40 = _res_aligned_straddlesLowerBound_T_34 ^ _res_aligned_straddlesLowerBound_T_39; // @[PMP.scala:123:{35,49,67}]
wire _res_aligned_straddlesLowerBound_T_41 = _res_aligned_straddlesLowerBound_T_40 == 29'h0; // @[PMP.scala:80:52, :81:54, :123:{49,67,82}]
wire [31:0] _res_aligned_straddlesLowerBound_T_43 = ~_res_aligned_straddlesLowerBound_T_42; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_aligned_straddlesLowerBound_T_44 = {_res_aligned_straddlesLowerBound_T_43[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_aligned_straddlesLowerBound_T_45 = ~_res_aligned_straddlesLowerBound_T_44; // @[PMP.scala:60:{27,48}]
wire [2:0] _res_aligned_straddlesLowerBound_T_46 = _res_aligned_straddlesLowerBound_T_45[2:0]; // @[PMP.scala:60:27, :123:108]
wire [2:0] _res_aligned_straddlesLowerBound_T_48 = ~_res_aligned_straddlesLowerBound_T_47; // @[PMP.scala:123:{127,129}]
wire [2:0] _res_aligned_straddlesLowerBound_T_49 = _res_aligned_straddlesLowerBound_T_46 & _res_aligned_straddlesLowerBound_T_48; // @[PMP.scala:123:{108,125,127}]
wire _res_aligned_straddlesLowerBound_T_50 = |_res_aligned_straddlesLowerBound_T_49; // @[PMP.scala:123:{125,147}]
wire res_aligned_straddlesLowerBound_2 = _res_aligned_straddlesLowerBound_T_41 & _res_aligned_straddlesLowerBound_T_50; // @[PMP.scala:123:{82,90,147}]
wire [31:0] _res_aligned_straddlesUpperBound_T_36 = ~_res_aligned_straddlesUpperBound_T_35; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_aligned_straddlesUpperBound_T_37 = {_res_aligned_straddlesUpperBound_T_36[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_aligned_straddlesUpperBound_T_38 = ~_res_aligned_straddlesUpperBound_T_37; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_aligned_straddlesUpperBound_T_39 = _res_aligned_straddlesUpperBound_T_38[31:3]; // @[PMP.scala:60:27, :124:62]
wire [28:0] _res_aligned_straddlesUpperBound_T_40 = _res_aligned_straddlesUpperBound_T_34 ^ _res_aligned_straddlesUpperBound_T_39; // @[PMP.scala:124:{35,49,62}]
wire _res_aligned_straddlesUpperBound_T_41 = _res_aligned_straddlesUpperBound_T_40 == 29'h0; // @[PMP.scala:80:52, :81:54, :123:67, :124:{49,77}]
wire [31:0] _res_aligned_straddlesUpperBound_T_43 = ~_res_aligned_straddlesUpperBound_T_42; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_aligned_straddlesUpperBound_T_44 = {_res_aligned_straddlesUpperBound_T_43[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_aligned_straddlesUpperBound_T_45 = ~_res_aligned_straddlesUpperBound_T_44; // @[PMP.scala:60:{27,48}]
wire [2:0] _res_aligned_straddlesUpperBound_T_46 = _res_aligned_straddlesUpperBound_T_45[2:0]; // @[PMP.scala:60:27, :124:98]
wire [2:0] _res_aligned_straddlesUpperBound_T_48 = _res_aligned_straddlesUpperBound_T_47 | res_aligned_lsbMask_2; // @[package.scala:243:46]
wire [2:0] _res_aligned_straddlesUpperBound_T_49 = _res_aligned_straddlesUpperBound_T_46 & _res_aligned_straddlesUpperBound_T_48; // @[PMP.scala:124:{98,115,136}]
wire _res_aligned_straddlesUpperBound_T_50 = |_res_aligned_straddlesUpperBound_T_49; // @[PMP.scala:124:{115,148}]
wire res_aligned_straddlesUpperBound_2 = _res_aligned_straddlesUpperBound_T_41 & _res_aligned_straddlesUpperBound_T_50; // @[PMP.scala:124:{77,85,148}]
wire _res_aligned_rangeAligned_T_2 = res_aligned_straddlesLowerBound_2 | res_aligned_straddlesUpperBound_2; // @[PMP.scala:123:90, :124:85, :125:46]
wire res_aligned_rangeAligned_2 = ~_res_aligned_rangeAligned_T_2; // @[PMP.scala:125:{24,46}]
wire [2:0] _res_aligned_pow2Aligned_T_7 = ~_res_aligned_pow2Aligned_T_6; // @[PMP.scala:126:{34,39}]
wire [2:0] _res_aligned_pow2Aligned_T_8 = res_aligned_lsbMask_2 & _res_aligned_pow2Aligned_T_7; // @[package.scala:243:46]
wire res_aligned_pow2Aligned_2 = _res_aligned_pow2Aligned_T_8 == 3'h0; // @[PMP.scala:82:64, :123:{108,125}, :126:{32,57}]
wire res_aligned_2 = _res_aligned_T_2 ? res_aligned_pow2Aligned_2 : res_aligned_rangeAligned_2; // @[PMP.scala:45:20, :125:24, :126:57, :127:8]
wire _res_T_90 = io_pmp_5_cfg_a_0 == 2'h0; // @[PMP.scala:143:7, :168:32]
wire _GEN_12 = io_pmp_5_cfg_a_0 == 2'h1; // @[PMP.scala:143:7, :168:32]
wire _res_T_91; // @[PMP.scala:168:32]
assign _res_T_91 = _GEN_12; // @[PMP.scala:168:32]
wire _res_T_110; // @[PMP.scala:177:61]
assign _res_T_110 = _GEN_12; // @[PMP.scala:168:32, :177:61]
wire _res_T_114; // @[PMP.scala:178:63]
assign _res_T_114 = _GEN_12; // @[PMP.scala:168:32, :178:63]
wire _GEN_13 = io_pmp_5_cfg_a_0 == 2'h2; // @[PMP.scala:143:7, :168:32]
wire _res_T_92; // @[PMP.scala:168:32]
assign _res_T_92 = _GEN_13; // @[PMP.scala:168:32]
wire _res_T_119; // @[PMP.scala:177:61]
assign _res_T_119 = _GEN_13; // @[PMP.scala:168:32, :177:61]
wire _res_T_123; // @[PMP.scala:178:63]
assign _res_T_123 = _GEN_13; // @[PMP.scala:168:32, :178:63]
wire _res_T_93 = &io_pmp_5_cfg_a_0; // @[PMP.scala:143:7, :168:32]
wire [1:0] _GEN_14 = {io_pmp_5_cfg_x_0, io_pmp_5_cfg_w_0}; // @[PMP.scala:143:7, :174:26]
wire [1:0] res_hi_12; // @[PMP.scala:174:26]
assign res_hi_12 = _GEN_14; // @[PMP.scala:174:26]
wire [1:0] res_hi_13; // @[PMP.scala:174:26]
assign res_hi_13 = _GEN_14; // @[PMP.scala:174:26]
wire [1:0] res_hi_14; // @[PMP.scala:174:26]
assign res_hi_14 = _GEN_14; // @[PMP.scala:174:26]
wire [1:0] res_hi_15; // @[PMP.scala:174:26]
assign res_hi_15 = _GEN_14; // @[PMP.scala:174:26]
wire [1:0] res_hi_16; // @[PMP.scala:174:26]
assign res_hi_16 = _GEN_14; // @[PMP.scala:174:26]
wire [1:0] res_hi_17; // @[PMP.scala:174:26]
assign res_hi_17 = _GEN_14; // @[PMP.scala:174:26]
wire [2:0] _res_T_95 = {res_hi_12, io_pmp_5_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_96 = _res_T_95 == 3'h0; // @[PMP.scala:82:64, :123:{108,125}, :174:{26,60}]
wire [2:0] _res_T_97 = {res_hi_13, io_pmp_5_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_98 = _res_T_97 == 3'h1; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_99 = {res_hi_14, io_pmp_5_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_100 = _res_T_99 == 3'h3; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_101 = {res_hi_15, io_pmp_5_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_102 = _res_T_101 == 3'h4; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_103 = {res_hi_16, io_pmp_5_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_104 = _res_T_103 == 3'h5; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_105 = {res_hi_17, io_pmp_5_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_106 = &_res_T_105; // @[PMP.scala:174:{26,60}]
wire _res_T_107 = ~res_ignore_2; // @[PMP.scala:164:26, :177:22]
wire _res_T_108 = _res_T_107 & res_hit_2; // @[PMP.scala:132:8, :177:{22,30}]
wire _res_T_109 = _res_T_108 & res_aligned_2; // @[PMP.scala:127:8, :177:{30,37}]
wire _res_T_111 = _res_T_109 & _res_T_110; // @[PMP.scala:177:{37,48,61}]
wire _GEN_15 = io_pmp_5_cfg_l_0 & res_hit_2; // @[PMP.scala:132:8, :143:7, :178:32]
wire _res_T_112; // @[PMP.scala:178:32]
assign _res_T_112 = _GEN_15; // @[PMP.scala:178:32]
wire _res_T_121; // @[PMP.scala:178:32]
assign _res_T_121 = _GEN_15; // @[PMP.scala:178:32]
wire _res_T_130; // @[PMP.scala:178:32]
assign _res_T_130 = _GEN_15; // @[PMP.scala:178:32]
wire _res_T_113 = _res_T_112 & res_aligned_2; // @[PMP.scala:127:8, :178:{32,39}]
wire _res_T_115 = _res_T_113 & _res_T_114; // @[PMP.scala:178:{39,50,63}]
wire _res_T_116 = ~res_ignore_2; // @[PMP.scala:164:26, :177:22]
wire _res_T_117 = _res_T_116 & res_hit_2; // @[PMP.scala:132:8, :177:{22,30}]
wire _res_T_118 = _res_T_117 & res_aligned_2; // @[PMP.scala:127:8, :177:{30,37}]
wire _res_T_120 = _res_T_118 & _res_T_119; // @[PMP.scala:177:{37,48,61}]
wire _res_T_122 = _res_T_121 & res_aligned_2; // @[PMP.scala:127:8, :178:{32,39}]
wire _res_T_124 = _res_T_122 & _res_T_123; // @[PMP.scala:178:{39,50,63}]
wire _res_T_125 = ~res_ignore_2; // @[PMP.scala:164:26, :177:22]
wire _res_T_126 = _res_T_125 & res_hit_2; // @[PMP.scala:132:8, :177:{22,30}]
wire _res_T_127 = _res_T_126 & res_aligned_2; // @[PMP.scala:127:8, :177:{30,37}]
wire _res_T_128 = &io_pmp_5_cfg_a_0; // @[PMP.scala:143:7, :168:32, :177:61]
wire _res_T_129 = _res_T_127 & _res_T_128; // @[PMP.scala:177:{37,48,61}]
wire _res_T_131 = _res_T_130 & res_aligned_2; // @[PMP.scala:127:8, :178:{32,39}]
wire _res_T_132 = &io_pmp_5_cfg_a_0; // @[PMP.scala:143:7, :168:32, :178:63]
wire _res_T_133 = _res_T_131 & _res_T_132; // @[PMP.scala:178:{39,50,63}]
wire _res_cur_cfg_x_T_5; // @[PMP.scala:184:26]
wire _res_cur_cfg_w_T_5; // @[PMP.scala:183:26]
wire _res_cur_cfg_r_T_5; // @[PMP.scala:182:26]
wire res_cur_2_cfg_x; // @[PMP.scala:181:23]
wire res_cur_2_cfg_w; // @[PMP.scala:181:23]
wire res_cur_2_cfg_r; // @[PMP.scala:181:23]
wire _res_cur_cfg_r_T_4 = io_pmp_5_cfg_r_0 | res_ignore_2; // @[PMP.scala:143:7, :164:26, :182:40]
assign _res_cur_cfg_r_T_5 = res_aligned_2 & _res_cur_cfg_r_T_4; // @[PMP.scala:127:8, :182:{26,40}]
assign res_cur_2_cfg_r = _res_cur_cfg_r_T_5; // @[PMP.scala:181:23, :182:26]
wire _res_cur_cfg_w_T_4 = io_pmp_5_cfg_w_0 | res_ignore_2; // @[PMP.scala:143:7, :164:26, :183:40]
assign _res_cur_cfg_w_T_5 = res_aligned_2 & _res_cur_cfg_w_T_4; // @[PMP.scala:127:8, :183:{26,40}]
assign res_cur_2_cfg_w = _res_cur_cfg_w_T_5; // @[PMP.scala:181:23, :183:26]
wire _res_cur_cfg_x_T_4 = io_pmp_5_cfg_x_0 | res_ignore_2; // @[PMP.scala:143:7, :164:26, :184:40]
assign _res_cur_cfg_x_T_5 = res_aligned_2 & _res_cur_cfg_x_T_4; // @[PMP.scala:127:8, :184:{26,40}]
assign res_cur_2_cfg_x = _res_cur_cfg_x_T_5; // @[PMP.scala:181:23, :184:26]
wire _res_T_134_cfg_l = res_hit_2 ? res_cur_2_cfg_l : _res_T_89_cfg_l; // @[PMP.scala:132:8, :181:23, :185:8]
wire [1:0] _res_T_134_cfg_a = res_hit_2 ? res_cur_2_cfg_a : _res_T_89_cfg_a; // @[PMP.scala:132:8, :181:23, :185:8]
wire _res_T_134_cfg_x = res_hit_2 ? res_cur_2_cfg_x : _res_T_89_cfg_x; // @[PMP.scala:132:8, :181:23, :185:8]
wire _res_T_134_cfg_w = res_hit_2 ? res_cur_2_cfg_w : _res_T_89_cfg_w; // @[PMP.scala:132:8, :181:23, :185:8]
wire _res_T_134_cfg_r = res_hit_2 ? res_cur_2_cfg_r : _res_T_89_cfg_r; // @[PMP.scala:132:8, :181:23, :185:8]
wire [29:0] _res_T_134_addr = res_hit_2 ? res_cur_2_addr : _res_T_89_addr; // @[PMP.scala:132:8, :181:23, :185:8]
wire [31:0] _res_T_134_mask = res_hit_2 ? res_cur_2_mask : _res_T_89_mask; // @[PMP.scala:132:8, :181:23, :185:8]
wire _res_hit_T_39 = io_pmp_4_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7]
wire _res_aligned_T_3 = io_pmp_4_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7]
wire [2:0] _res_hit_lsbMask_T_10 = _res_hit_lsbMask_T_9[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] _res_hit_lsbMask_T_11 = ~_res_hit_lsbMask_T_10; // @[package.scala:243:{46,76}]
wire [28:0] _res_hit_msbMatch_T_36 = io_pmp_4_mask_0[31:3]; // @[PMP.scala:68:26, :69:72, :143:7]
wire [2:0] _res_aligned_pow2Aligned_T_9 = io_pmp_4_mask_0[2:0]; // @[PMP.scala:68:26, :126:39, :143:7]
wire [31:0] res_hit_lsbMask_3 = {_res_hit_msbMatch_T_36, _res_aligned_pow2Aligned_T_9 | _res_hit_lsbMask_T_11}; // @[package.scala:243:46]
wire [31:0] _res_hit_msbMatch_T_32 = ~_res_hit_msbMatch_T_31; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_msbMatch_T_33 = {_res_hit_msbMatch_T_32[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbMatch_T_34 = ~_res_hit_msbMatch_T_33; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_hit_msbMatch_T_35 = _res_hit_msbMatch_T_34[31:3]; // @[PMP.scala:60:27, :69:53]
wire [28:0] _res_hit_msbMatch_T_37 = _res_hit_msbMatch_T_30 ^ _res_hit_msbMatch_T_35; // @[PMP.scala:63:47, :69:{29,53}]
wire [28:0] _res_hit_msbMatch_T_38 = ~_res_hit_msbMatch_T_36; // @[PMP.scala:63:54, :69:72]
wire [28:0] _res_hit_msbMatch_T_39 = _res_hit_msbMatch_T_37 & _res_hit_msbMatch_T_38; // @[PMP.scala:63:{47,52,54}]
wire res_hit_msbMatch_3 = _res_hit_msbMatch_T_39 == 29'h0; // @[PMP.scala:63:{52,58}, :80:52, :81:54, :123:67]
wire [31:0] _res_hit_lsbMatch_T_32 = ~_res_hit_lsbMatch_T_31; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_lsbMatch_T_33 = {_res_hit_lsbMatch_T_32[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_lsbMatch_T_34 = ~_res_hit_lsbMatch_T_33; // @[PMP.scala:60:{27,48}]
wire [2:0] _res_hit_lsbMatch_T_35 = _res_hit_lsbMatch_T_34[2:0]; // @[PMP.scala:60:27, :70:55]
wire [2:0] _res_hit_lsbMatch_T_36 = res_hit_lsbMask_3[2:0]; // @[PMP.scala:68:26, :70:80]
wire [2:0] _res_hit_lsbMatch_T_37 = _res_hit_lsbMatch_T_30 ^ _res_hit_lsbMatch_T_35; // @[PMP.scala:63:47, :70:{28,55}]
wire [2:0] _res_hit_lsbMatch_T_38 = ~_res_hit_lsbMatch_T_36; // @[PMP.scala:63:54, :70:80]
wire [2:0] _res_hit_lsbMatch_T_39 = _res_hit_lsbMatch_T_37 & _res_hit_lsbMatch_T_38; // @[PMP.scala:63:{47,52,54}]
wire res_hit_lsbMatch_3 = _res_hit_lsbMatch_T_39 == 3'h0; // @[PMP.scala:63:{52,58}, :82:64, :123:{108,125}]
wire _res_hit_T_40 = res_hit_msbMatch_3 & res_hit_lsbMatch_3; // @[PMP.scala:63:58, :71:16]
wire _res_hit_T_41 = io_pmp_4_cfg_a_0[0]; // @[PMP.scala:46:26, :143:7]
wire [2:0] _res_hit_T_43 = _res_hit_T_42[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] _res_hit_T_44 = ~_res_hit_T_43; // @[package.scala:243:{46,76}]
wire [31:0] _GEN_16 = {io_pmp_3_addr_0, 2'h0}; // @[PMP.scala:60:36, :143:7]
wire [31:0] _res_hit_msbsLess_T_37; // @[PMP.scala:60:36]
assign _res_hit_msbsLess_T_37 = _GEN_16; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbsEqual_T_43; // @[PMP.scala:60:36]
assign _res_hit_msbsEqual_T_43 = _GEN_16; // @[PMP.scala:60:36]
wire [31:0] _res_hit_lsbsLess_T_44; // @[PMP.scala:60:36]
assign _res_hit_lsbsLess_T_44 = _GEN_16; // @[PMP.scala:60:36]
wire [31:0] _res_aligned_straddlesLowerBound_T_52; // @[PMP.scala:60:36]
assign _res_aligned_straddlesLowerBound_T_52 = _GEN_16; // @[PMP.scala:60:36]
wire [31:0] _res_aligned_straddlesLowerBound_T_59; // @[PMP.scala:60:36]
assign _res_aligned_straddlesLowerBound_T_59 = _GEN_16; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbMatch_T_41; // @[PMP.scala:60:36]
assign _res_hit_msbMatch_T_41 = _GEN_16; // @[PMP.scala:60:36]
wire [31:0] _res_hit_lsbMatch_T_41; // @[PMP.scala:60:36]
assign _res_hit_lsbMatch_T_41 = _GEN_16; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbsLess_T_55; // @[PMP.scala:60:36]
assign _res_hit_msbsLess_T_55 = _GEN_16; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbsEqual_T_64; // @[PMP.scala:60:36]
assign _res_hit_msbsEqual_T_64 = _GEN_16; // @[PMP.scala:60:36]
wire [31:0] _res_hit_lsbsLess_T_65; // @[PMP.scala:60:36]
assign _res_hit_lsbsLess_T_65 = _GEN_16; // @[PMP.scala:60:36]
wire [31:0] _res_aligned_straddlesUpperBound_T_69; // @[PMP.scala:60:36]
assign _res_aligned_straddlesUpperBound_T_69 = _GEN_16; // @[PMP.scala:60:36]
wire [31:0] _res_aligned_straddlesUpperBound_T_76; // @[PMP.scala:60:36]
assign _res_aligned_straddlesUpperBound_T_76 = _GEN_16; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbsLess_T_38 = ~_res_hit_msbsLess_T_37; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_msbsLess_T_39 = {_res_hit_msbsLess_T_38[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbsLess_T_40 = ~_res_hit_msbsLess_T_39; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_hit_msbsLess_T_41 = _res_hit_msbsLess_T_40[31:3]; // @[PMP.scala:60:27, :80:52]
wire res_hit_msbsLess_6 = _res_hit_msbsLess_T_36 < _res_hit_msbsLess_T_41; // @[PMP.scala:80:{25,39,52}]
wire [31:0] _res_hit_msbsEqual_T_44 = ~_res_hit_msbsEqual_T_43; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_msbsEqual_T_45 = {_res_hit_msbsEqual_T_44[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbsEqual_T_46 = ~_res_hit_msbsEqual_T_45; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_hit_msbsEqual_T_47 = _res_hit_msbsEqual_T_46[31:3]; // @[PMP.scala:60:27, :81:54]
wire [28:0] _res_hit_msbsEqual_T_48 = _res_hit_msbsEqual_T_42 ^ _res_hit_msbsEqual_T_47; // @[PMP.scala:81:{27,41,54}]
wire res_hit_msbsEqual_6 = _res_hit_msbsEqual_T_48 == 29'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67]
wire [2:0] _res_hit_lsbsLess_T_43 = _res_hit_lsbsLess_T_42 | _res_hit_T_44; // @[package.scala:243:46]
wire [31:0] _res_hit_lsbsLess_T_45 = ~_res_hit_lsbsLess_T_44; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_lsbsLess_T_46 = {_res_hit_lsbsLess_T_45[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_lsbsLess_T_47 = ~_res_hit_lsbsLess_T_46; // @[PMP.scala:60:{27,48}]
wire [2:0] _res_hit_lsbsLess_T_48 = _res_hit_lsbsLess_T_47[2:0]; // @[PMP.scala:60:27, :82:64]
wire res_hit_lsbsLess_6 = _res_hit_lsbsLess_T_43 < _res_hit_lsbsLess_T_48; // @[PMP.scala:82:{42,53,64}]
wire _res_hit_T_45 = res_hit_msbsEqual_6 & res_hit_lsbsLess_6; // @[PMP.scala:81:69, :82:53, :83:30]
wire _res_hit_T_46 = res_hit_msbsLess_6 | _res_hit_T_45; // @[PMP.scala:80:39, :83:{16,30}]
wire _res_hit_T_47 = ~_res_hit_T_46; // @[PMP.scala:83:16, :88:5]
wire [31:0] _res_hit_msbsLess_T_44 = ~_res_hit_msbsLess_T_43; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_msbsLess_T_45 = {_res_hit_msbsLess_T_44[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbsLess_T_46 = ~_res_hit_msbsLess_T_45; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_hit_msbsLess_T_47 = _res_hit_msbsLess_T_46[31:3]; // @[PMP.scala:60:27, :80:52]
wire res_hit_msbsLess_7 = _res_hit_msbsLess_T_42 < _res_hit_msbsLess_T_47; // @[PMP.scala:80:{25,39,52}]
wire [31:0] _res_hit_msbsEqual_T_51 = ~_res_hit_msbsEqual_T_50; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_msbsEqual_T_52 = {_res_hit_msbsEqual_T_51[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbsEqual_T_53 = ~_res_hit_msbsEqual_T_52; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_hit_msbsEqual_T_54 = _res_hit_msbsEqual_T_53[31:3]; // @[PMP.scala:60:27, :81:54]
wire [28:0] _res_hit_msbsEqual_T_55 = _res_hit_msbsEqual_T_49 ^ _res_hit_msbsEqual_T_54; // @[PMP.scala:81:{27,41,54}]
wire res_hit_msbsEqual_7 = _res_hit_msbsEqual_T_55 == 29'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67]
wire [2:0] _res_hit_lsbsLess_T_50 = _res_hit_lsbsLess_T_49; // @[PMP.scala:82:{25,42}]
wire [31:0] _res_hit_lsbsLess_T_52 = ~_res_hit_lsbsLess_T_51; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_lsbsLess_T_53 = {_res_hit_lsbsLess_T_52[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_lsbsLess_T_54 = ~_res_hit_lsbsLess_T_53; // @[PMP.scala:60:{27,48}]
wire [2:0] _res_hit_lsbsLess_T_55 = _res_hit_lsbsLess_T_54[2:0]; // @[PMP.scala:60:27, :82:64]
wire res_hit_lsbsLess_7 = _res_hit_lsbsLess_T_50 < _res_hit_lsbsLess_T_55; // @[PMP.scala:82:{42,53,64}]
wire _res_hit_T_48 = res_hit_msbsEqual_7 & res_hit_lsbsLess_7; // @[PMP.scala:81:69, :82:53, :83:30]
wire _res_hit_T_49 = res_hit_msbsLess_7 | _res_hit_T_48; // @[PMP.scala:80:39, :83:{16,30}]
wire _res_hit_T_50 = _res_hit_T_47 & _res_hit_T_49; // @[PMP.scala:83:16, :88:5, :94:48]
wire _res_hit_T_51 = _res_hit_T_41 & _res_hit_T_50; // @[PMP.scala:46:26, :94:48, :132:61]
wire res_hit_3 = _res_hit_T_39 ? _res_hit_T_40 : _res_hit_T_51; // @[PMP.scala:45:20, :71:16, :132:{8,61}]
wire _res_ignore_T_3 = ~io_pmp_4_cfg_l_0; // @[PMP.scala:143:7, :164:29]
wire res_ignore_3 = default_0 & _res_ignore_T_3; // @[PMP.scala:156:56, :164:{26,29}]
wire [2:0] _res_aligned_lsbMask_T_7 = _res_aligned_lsbMask_T_6[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] res_aligned_lsbMask_3 = ~_res_aligned_lsbMask_T_7; // @[package.scala:243:{46,76}]
wire [31:0] _res_aligned_straddlesLowerBound_T_53 = ~_res_aligned_straddlesLowerBound_T_52; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_aligned_straddlesLowerBound_T_54 = {_res_aligned_straddlesLowerBound_T_53[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_aligned_straddlesLowerBound_T_55 = ~_res_aligned_straddlesLowerBound_T_54; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_aligned_straddlesLowerBound_T_56 = _res_aligned_straddlesLowerBound_T_55[31:3]; // @[PMP.scala:60:27, :123:67]
wire [28:0] _res_aligned_straddlesLowerBound_T_57 = _res_aligned_straddlesLowerBound_T_51 ^ _res_aligned_straddlesLowerBound_T_56; // @[PMP.scala:123:{35,49,67}]
wire _res_aligned_straddlesLowerBound_T_58 = _res_aligned_straddlesLowerBound_T_57 == 29'h0; // @[PMP.scala:80:52, :81:54, :123:{49,67,82}]
wire [31:0] _res_aligned_straddlesLowerBound_T_60 = ~_res_aligned_straddlesLowerBound_T_59; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_aligned_straddlesLowerBound_T_61 = {_res_aligned_straddlesLowerBound_T_60[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_aligned_straddlesLowerBound_T_62 = ~_res_aligned_straddlesLowerBound_T_61; // @[PMP.scala:60:{27,48}]
wire [2:0] _res_aligned_straddlesLowerBound_T_63 = _res_aligned_straddlesLowerBound_T_62[2:0]; // @[PMP.scala:60:27, :123:108]
wire [2:0] _res_aligned_straddlesLowerBound_T_65 = ~_res_aligned_straddlesLowerBound_T_64; // @[PMP.scala:123:{127,129}]
wire [2:0] _res_aligned_straddlesLowerBound_T_66 = _res_aligned_straddlesLowerBound_T_63 & _res_aligned_straddlesLowerBound_T_65; // @[PMP.scala:123:{108,125,127}]
wire _res_aligned_straddlesLowerBound_T_67 = |_res_aligned_straddlesLowerBound_T_66; // @[PMP.scala:123:{125,147}]
wire res_aligned_straddlesLowerBound_3 = _res_aligned_straddlesLowerBound_T_58 & _res_aligned_straddlesLowerBound_T_67; // @[PMP.scala:123:{82,90,147}]
wire [31:0] _res_aligned_straddlesUpperBound_T_53 = ~_res_aligned_straddlesUpperBound_T_52; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_aligned_straddlesUpperBound_T_54 = {_res_aligned_straddlesUpperBound_T_53[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_aligned_straddlesUpperBound_T_55 = ~_res_aligned_straddlesUpperBound_T_54; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_aligned_straddlesUpperBound_T_56 = _res_aligned_straddlesUpperBound_T_55[31:3]; // @[PMP.scala:60:27, :124:62]
wire [28:0] _res_aligned_straddlesUpperBound_T_57 = _res_aligned_straddlesUpperBound_T_51 ^ _res_aligned_straddlesUpperBound_T_56; // @[PMP.scala:124:{35,49,62}]
wire _res_aligned_straddlesUpperBound_T_58 = _res_aligned_straddlesUpperBound_T_57 == 29'h0; // @[PMP.scala:80:52, :81:54, :123:67, :124:{49,77}]
wire [31:0] _res_aligned_straddlesUpperBound_T_60 = ~_res_aligned_straddlesUpperBound_T_59; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_aligned_straddlesUpperBound_T_61 = {_res_aligned_straddlesUpperBound_T_60[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_aligned_straddlesUpperBound_T_62 = ~_res_aligned_straddlesUpperBound_T_61; // @[PMP.scala:60:{27,48}]
wire [2:0] _res_aligned_straddlesUpperBound_T_63 = _res_aligned_straddlesUpperBound_T_62[2:0]; // @[PMP.scala:60:27, :124:98]
wire [2:0] _res_aligned_straddlesUpperBound_T_65 = _res_aligned_straddlesUpperBound_T_64 | res_aligned_lsbMask_3; // @[package.scala:243:46]
wire [2:0] _res_aligned_straddlesUpperBound_T_66 = _res_aligned_straddlesUpperBound_T_63 & _res_aligned_straddlesUpperBound_T_65; // @[PMP.scala:124:{98,115,136}]
wire _res_aligned_straddlesUpperBound_T_67 = |_res_aligned_straddlesUpperBound_T_66; // @[PMP.scala:124:{115,148}]
wire res_aligned_straddlesUpperBound_3 = _res_aligned_straddlesUpperBound_T_58 & _res_aligned_straddlesUpperBound_T_67; // @[PMP.scala:124:{77,85,148}]
wire _res_aligned_rangeAligned_T_3 = res_aligned_straddlesLowerBound_3 | res_aligned_straddlesUpperBound_3; // @[PMP.scala:123:90, :124:85, :125:46]
wire res_aligned_rangeAligned_3 = ~_res_aligned_rangeAligned_T_3; // @[PMP.scala:125:{24,46}]
wire [2:0] _res_aligned_pow2Aligned_T_10 = ~_res_aligned_pow2Aligned_T_9; // @[PMP.scala:126:{34,39}]
wire [2:0] _res_aligned_pow2Aligned_T_11 = res_aligned_lsbMask_3 & _res_aligned_pow2Aligned_T_10; // @[package.scala:243:46]
wire res_aligned_pow2Aligned_3 = _res_aligned_pow2Aligned_T_11 == 3'h0; // @[PMP.scala:82:64, :123:{108,125}, :126:{32,57}]
wire res_aligned_3 = _res_aligned_T_3 ? res_aligned_pow2Aligned_3 : res_aligned_rangeAligned_3; // @[PMP.scala:45:20, :125:24, :126:57, :127:8]
wire _res_T_135 = io_pmp_4_cfg_a_0 == 2'h0; // @[PMP.scala:143:7, :168:32]
wire _GEN_17 = io_pmp_4_cfg_a_0 == 2'h1; // @[PMP.scala:143:7, :168:32]
wire _res_T_136; // @[PMP.scala:168:32]
assign _res_T_136 = _GEN_17; // @[PMP.scala:168:32]
wire _res_T_155; // @[PMP.scala:177:61]
assign _res_T_155 = _GEN_17; // @[PMP.scala:168:32, :177:61]
wire _res_T_159; // @[PMP.scala:178:63]
assign _res_T_159 = _GEN_17; // @[PMP.scala:168:32, :178:63]
wire _GEN_18 = io_pmp_4_cfg_a_0 == 2'h2; // @[PMP.scala:143:7, :168:32]
wire _res_T_137; // @[PMP.scala:168:32]
assign _res_T_137 = _GEN_18; // @[PMP.scala:168:32]
wire _res_T_164; // @[PMP.scala:177:61]
assign _res_T_164 = _GEN_18; // @[PMP.scala:168:32, :177:61]
wire _res_T_168; // @[PMP.scala:178:63]
assign _res_T_168 = _GEN_18; // @[PMP.scala:168:32, :178:63]
wire _res_T_138 = &io_pmp_4_cfg_a_0; // @[PMP.scala:143:7, :168:32]
wire [1:0] _GEN_19 = {io_pmp_4_cfg_x_0, io_pmp_4_cfg_w_0}; // @[PMP.scala:143:7, :174:26]
wire [1:0] res_hi_18; // @[PMP.scala:174:26]
assign res_hi_18 = _GEN_19; // @[PMP.scala:174:26]
wire [1:0] res_hi_19; // @[PMP.scala:174:26]
assign res_hi_19 = _GEN_19; // @[PMP.scala:174:26]
wire [1:0] res_hi_20; // @[PMP.scala:174:26]
assign res_hi_20 = _GEN_19; // @[PMP.scala:174:26]
wire [1:0] res_hi_21; // @[PMP.scala:174:26]
assign res_hi_21 = _GEN_19; // @[PMP.scala:174:26]
wire [1:0] res_hi_22; // @[PMP.scala:174:26]
assign res_hi_22 = _GEN_19; // @[PMP.scala:174:26]
wire [1:0] res_hi_23; // @[PMP.scala:174:26]
assign res_hi_23 = _GEN_19; // @[PMP.scala:174:26]
wire [2:0] _res_T_140 = {res_hi_18, io_pmp_4_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_141 = _res_T_140 == 3'h0; // @[PMP.scala:82:64, :123:{108,125}, :174:{26,60}]
wire [2:0] _res_T_142 = {res_hi_19, io_pmp_4_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_143 = _res_T_142 == 3'h1; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_144 = {res_hi_20, io_pmp_4_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_145 = _res_T_144 == 3'h3; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_146 = {res_hi_21, io_pmp_4_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_147 = _res_T_146 == 3'h4; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_148 = {res_hi_22, io_pmp_4_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_149 = _res_T_148 == 3'h5; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_150 = {res_hi_23, io_pmp_4_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_151 = &_res_T_150; // @[PMP.scala:174:{26,60}]
wire _res_T_152 = ~res_ignore_3; // @[PMP.scala:164:26, :177:22]
wire _res_T_153 = _res_T_152 & res_hit_3; // @[PMP.scala:132:8, :177:{22,30}]
wire _res_T_154 = _res_T_153 & res_aligned_3; // @[PMP.scala:127:8, :177:{30,37}]
wire _res_T_156 = _res_T_154 & _res_T_155; // @[PMP.scala:177:{37,48,61}]
wire _GEN_20 = io_pmp_4_cfg_l_0 & res_hit_3; // @[PMP.scala:132:8, :143:7, :178:32]
wire _res_T_157; // @[PMP.scala:178:32]
assign _res_T_157 = _GEN_20; // @[PMP.scala:178:32]
wire _res_T_166; // @[PMP.scala:178:32]
assign _res_T_166 = _GEN_20; // @[PMP.scala:178:32]
wire _res_T_175; // @[PMP.scala:178:32]
assign _res_T_175 = _GEN_20; // @[PMP.scala:178:32]
wire _res_T_158 = _res_T_157 & res_aligned_3; // @[PMP.scala:127:8, :178:{32,39}]
wire _res_T_160 = _res_T_158 & _res_T_159; // @[PMP.scala:178:{39,50,63}]
wire _res_T_161 = ~res_ignore_3; // @[PMP.scala:164:26, :177:22]
wire _res_T_162 = _res_T_161 & res_hit_3; // @[PMP.scala:132:8, :177:{22,30}]
wire _res_T_163 = _res_T_162 & res_aligned_3; // @[PMP.scala:127:8, :177:{30,37}]
wire _res_T_165 = _res_T_163 & _res_T_164; // @[PMP.scala:177:{37,48,61}]
wire _res_T_167 = _res_T_166 & res_aligned_3; // @[PMP.scala:127:8, :178:{32,39}]
wire _res_T_169 = _res_T_167 & _res_T_168; // @[PMP.scala:178:{39,50,63}]
wire _res_T_170 = ~res_ignore_3; // @[PMP.scala:164:26, :177:22]
wire _res_T_171 = _res_T_170 & res_hit_3; // @[PMP.scala:132:8, :177:{22,30}]
wire _res_T_172 = _res_T_171 & res_aligned_3; // @[PMP.scala:127:8, :177:{30,37}]
wire _res_T_173 = &io_pmp_4_cfg_a_0; // @[PMP.scala:143:7, :168:32, :177:61]
wire _res_T_174 = _res_T_172 & _res_T_173; // @[PMP.scala:177:{37,48,61}]
wire _res_T_176 = _res_T_175 & res_aligned_3; // @[PMP.scala:127:8, :178:{32,39}]
wire _res_T_177 = &io_pmp_4_cfg_a_0; // @[PMP.scala:143:7, :168:32, :178:63]
wire _res_T_178 = _res_T_176 & _res_T_177; // @[PMP.scala:178:{39,50,63}]
wire _res_cur_cfg_x_T_7; // @[PMP.scala:184:26]
wire _res_cur_cfg_w_T_7; // @[PMP.scala:183:26]
wire _res_cur_cfg_r_T_7; // @[PMP.scala:182:26]
wire res_cur_3_cfg_x; // @[PMP.scala:181:23]
wire res_cur_3_cfg_w; // @[PMP.scala:181:23]
wire res_cur_3_cfg_r; // @[PMP.scala:181:23]
wire _res_cur_cfg_r_T_6 = io_pmp_4_cfg_r_0 | res_ignore_3; // @[PMP.scala:143:7, :164:26, :182:40]
assign _res_cur_cfg_r_T_7 = res_aligned_3 & _res_cur_cfg_r_T_6; // @[PMP.scala:127:8, :182:{26,40}]
assign res_cur_3_cfg_r = _res_cur_cfg_r_T_7; // @[PMP.scala:181:23, :182:26]
wire _res_cur_cfg_w_T_6 = io_pmp_4_cfg_w_0 | res_ignore_3; // @[PMP.scala:143:7, :164:26, :183:40]
assign _res_cur_cfg_w_T_7 = res_aligned_3 & _res_cur_cfg_w_T_6; // @[PMP.scala:127:8, :183:{26,40}]
assign res_cur_3_cfg_w = _res_cur_cfg_w_T_7; // @[PMP.scala:181:23, :183:26]
wire _res_cur_cfg_x_T_6 = io_pmp_4_cfg_x_0 | res_ignore_3; // @[PMP.scala:143:7, :164:26, :184:40]
assign _res_cur_cfg_x_T_7 = res_aligned_3 & _res_cur_cfg_x_T_6; // @[PMP.scala:127:8, :184:{26,40}]
assign res_cur_3_cfg_x = _res_cur_cfg_x_T_7; // @[PMP.scala:181:23, :184:26]
wire _res_T_179_cfg_l = res_hit_3 ? res_cur_3_cfg_l : _res_T_134_cfg_l; // @[PMP.scala:132:8, :181:23, :185:8]
wire [1:0] _res_T_179_cfg_a = res_hit_3 ? res_cur_3_cfg_a : _res_T_134_cfg_a; // @[PMP.scala:132:8, :181:23, :185:8]
wire _res_T_179_cfg_x = res_hit_3 ? res_cur_3_cfg_x : _res_T_134_cfg_x; // @[PMP.scala:132:8, :181:23, :185:8]
wire _res_T_179_cfg_w = res_hit_3 ? res_cur_3_cfg_w : _res_T_134_cfg_w; // @[PMP.scala:132:8, :181:23, :185:8]
wire _res_T_179_cfg_r = res_hit_3 ? res_cur_3_cfg_r : _res_T_134_cfg_r; // @[PMP.scala:132:8, :181:23, :185:8]
wire [29:0] _res_T_179_addr = res_hit_3 ? res_cur_3_addr : _res_T_134_addr; // @[PMP.scala:132:8, :181:23, :185:8]
wire [31:0] _res_T_179_mask = res_hit_3 ? res_cur_3_mask : _res_T_134_mask; // @[PMP.scala:132:8, :181:23, :185:8]
wire _res_hit_T_52 = io_pmp_3_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7]
wire _res_aligned_T_4 = io_pmp_3_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7]
wire [2:0] _res_hit_lsbMask_T_13 = _res_hit_lsbMask_T_12[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] _res_hit_lsbMask_T_14 = ~_res_hit_lsbMask_T_13; // @[package.scala:243:{46,76}]
wire [28:0] _res_hit_msbMatch_T_46 = io_pmp_3_mask_0[31:3]; // @[PMP.scala:68:26, :69:72, :143:7]
wire [2:0] _res_aligned_pow2Aligned_T_12 = io_pmp_3_mask_0[2:0]; // @[PMP.scala:68:26, :126:39, :143:7]
wire [31:0] res_hit_lsbMask_4 = {_res_hit_msbMatch_T_46, _res_aligned_pow2Aligned_T_12 | _res_hit_lsbMask_T_14}; // @[package.scala:243:46]
wire [31:0] _res_hit_msbMatch_T_42 = ~_res_hit_msbMatch_T_41; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_msbMatch_T_43 = {_res_hit_msbMatch_T_42[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbMatch_T_44 = ~_res_hit_msbMatch_T_43; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_hit_msbMatch_T_45 = _res_hit_msbMatch_T_44[31:3]; // @[PMP.scala:60:27, :69:53]
wire [28:0] _res_hit_msbMatch_T_47 = _res_hit_msbMatch_T_40 ^ _res_hit_msbMatch_T_45; // @[PMP.scala:63:47, :69:{29,53}]
wire [28:0] _res_hit_msbMatch_T_48 = ~_res_hit_msbMatch_T_46; // @[PMP.scala:63:54, :69:72]
wire [28:0] _res_hit_msbMatch_T_49 = _res_hit_msbMatch_T_47 & _res_hit_msbMatch_T_48; // @[PMP.scala:63:{47,52,54}]
wire res_hit_msbMatch_4 = _res_hit_msbMatch_T_49 == 29'h0; // @[PMP.scala:63:{52,58}, :80:52, :81:54, :123:67]
wire [31:0] _res_hit_lsbMatch_T_42 = ~_res_hit_lsbMatch_T_41; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_lsbMatch_T_43 = {_res_hit_lsbMatch_T_42[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_lsbMatch_T_44 = ~_res_hit_lsbMatch_T_43; // @[PMP.scala:60:{27,48}]
wire [2:0] _res_hit_lsbMatch_T_45 = _res_hit_lsbMatch_T_44[2:0]; // @[PMP.scala:60:27, :70:55]
wire [2:0] _res_hit_lsbMatch_T_46 = res_hit_lsbMask_4[2:0]; // @[PMP.scala:68:26, :70:80]
wire [2:0] _res_hit_lsbMatch_T_47 = _res_hit_lsbMatch_T_40 ^ _res_hit_lsbMatch_T_45; // @[PMP.scala:63:47, :70:{28,55}]
wire [2:0] _res_hit_lsbMatch_T_48 = ~_res_hit_lsbMatch_T_46; // @[PMP.scala:63:54, :70:80]
wire [2:0] _res_hit_lsbMatch_T_49 = _res_hit_lsbMatch_T_47 & _res_hit_lsbMatch_T_48; // @[PMP.scala:63:{47,52,54}]
wire res_hit_lsbMatch_4 = _res_hit_lsbMatch_T_49 == 3'h0; // @[PMP.scala:63:{52,58}, :82:64, :123:{108,125}]
wire _res_hit_T_53 = res_hit_msbMatch_4 & res_hit_lsbMatch_4; // @[PMP.scala:63:58, :71:16]
wire _res_hit_T_54 = io_pmp_3_cfg_a_0[0]; // @[PMP.scala:46:26, :143:7]
wire [2:0] _res_hit_T_56 = _res_hit_T_55[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] _res_hit_T_57 = ~_res_hit_T_56; // @[package.scala:243:{46,76}]
wire [31:0] _GEN_21 = {io_pmp_2_addr_0, 2'h0}; // @[PMP.scala:60:36, :143:7]
wire [31:0] _res_hit_msbsLess_T_49; // @[PMP.scala:60:36]
assign _res_hit_msbsLess_T_49 = _GEN_21; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbsEqual_T_57; // @[PMP.scala:60:36]
assign _res_hit_msbsEqual_T_57 = _GEN_21; // @[PMP.scala:60:36]
wire [31:0] _res_hit_lsbsLess_T_58; // @[PMP.scala:60:36]
assign _res_hit_lsbsLess_T_58 = _GEN_21; // @[PMP.scala:60:36]
wire [31:0] _res_aligned_straddlesLowerBound_T_69; // @[PMP.scala:60:36]
assign _res_aligned_straddlesLowerBound_T_69 = _GEN_21; // @[PMP.scala:60:36]
wire [31:0] _res_aligned_straddlesLowerBound_T_76; // @[PMP.scala:60:36]
assign _res_aligned_straddlesLowerBound_T_76 = _GEN_21; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbMatch_T_51; // @[PMP.scala:60:36]
assign _res_hit_msbMatch_T_51 = _GEN_21; // @[PMP.scala:60:36]
wire [31:0] _res_hit_lsbMatch_T_51; // @[PMP.scala:60:36]
assign _res_hit_lsbMatch_T_51 = _GEN_21; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbsLess_T_67; // @[PMP.scala:60:36]
assign _res_hit_msbsLess_T_67 = _GEN_21; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbsEqual_T_78; // @[PMP.scala:60:36]
assign _res_hit_msbsEqual_T_78 = _GEN_21; // @[PMP.scala:60:36]
wire [31:0] _res_hit_lsbsLess_T_79; // @[PMP.scala:60:36]
assign _res_hit_lsbsLess_T_79 = _GEN_21; // @[PMP.scala:60:36]
wire [31:0] _res_aligned_straddlesUpperBound_T_86; // @[PMP.scala:60:36]
assign _res_aligned_straddlesUpperBound_T_86 = _GEN_21; // @[PMP.scala:60:36]
wire [31:0] _res_aligned_straddlesUpperBound_T_93; // @[PMP.scala:60:36]
assign _res_aligned_straddlesUpperBound_T_93 = _GEN_21; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbsLess_T_50 = ~_res_hit_msbsLess_T_49; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_msbsLess_T_51 = {_res_hit_msbsLess_T_50[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbsLess_T_52 = ~_res_hit_msbsLess_T_51; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_hit_msbsLess_T_53 = _res_hit_msbsLess_T_52[31:3]; // @[PMP.scala:60:27, :80:52]
wire res_hit_msbsLess_8 = _res_hit_msbsLess_T_48 < _res_hit_msbsLess_T_53; // @[PMP.scala:80:{25,39,52}]
wire [31:0] _res_hit_msbsEqual_T_58 = ~_res_hit_msbsEqual_T_57; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_msbsEqual_T_59 = {_res_hit_msbsEqual_T_58[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbsEqual_T_60 = ~_res_hit_msbsEqual_T_59; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_hit_msbsEqual_T_61 = _res_hit_msbsEqual_T_60[31:3]; // @[PMP.scala:60:27, :81:54]
wire [28:0] _res_hit_msbsEqual_T_62 = _res_hit_msbsEqual_T_56 ^ _res_hit_msbsEqual_T_61; // @[PMP.scala:81:{27,41,54}]
wire res_hit_msbsEqual_8 = _res_hit_msbsEqual_T_62 == 29'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67]
wire [2:0] _res_hit_lsbsLess_T_57 = _res_hit_lsbsLess_T_56 | _res_hit_T_57; // @[package.scala:243:46]
wire [31:0] _res_hit_lsbsLess_T_59 = ~_res_hit_lsbsLess_T_58; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_lsbsLess_T_60 = {_res_hit_lsbsLess_T_59[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_lsbsLess_T_61 = ~_res_hit_lsbsLess_T_60; // @[PMP.scala:60:{27,48}]
wire [2:0] _res_hit_lsbsLess_T_62 = _res_hit_lsbsLess_T_61[2:0]; // @[PMP.scala:60:27, :82:64]
wire res_hit_lsbsLess_8 = _res_hit_lsbsLess_T_57 < _res_hit_lsbsLess_T_62; // @[PMP.scala:82:{42,53,64}]
wire _res_hit_T_58 = res_hit_msbsEqual_8 & res_hit_lsbsLess_8; // @[PMP.scala:81:69, :82:53, :83:30]
wire _res_hit_T_59 = res_hit_msbsLess_8 | _res_hit_T_58; // @[PMP.scala:80:39, :83:{16,30}]
wire _res_hit_T_60 = ~_res_hit_T_59; // @[PMP.scala:83:16, :88:5]
wire [31:0] _res_hit_msbsLess_T_56 = ~_res_hit_msbsLess_T_55; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_msbsLess_T_57 = {_res_hit_msbsLess_T_56[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbsLess_T_58 = ~_res_hit_msbsLess_T_57; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_hit_msbsLess_T_59 = _res_hit_msbsLess_T_58[31:3]; // @[PMP.scala:60:27, :80:52]
wire res_hit_msbsLess_9 = _res_hit_msbsLess_T_54 < _res_hit_msbsLess_T_59; // @[PMP.scala:80:{25,39,52}]
wire [31:0] _res_hit_msbsEqual_T_65 = ~_res_hit_msbsEqual_T_64; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_msbsEqual_T_66 = {_res_hit_msbsEqual_T_65[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbsEqual_T_67 = ~_res_hit_msbsEqual_T_66; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_hit_msbsEqual_T_68 = _res_hit_msbsEqual_T_67[31:3]; // @[PMP.scala:60:27, :81:54]
wire [28:0] _res_hit_msbsEqual_T_69 = _res_hit_msbsEqual_T_63 ^ _res_hit_msbsEqual_T_68; // @[PMP.scala:81:{27,41,54}]
wire res_hit_msbsEqual_9 = _res_hit_msbsEqual_T_69 == 29'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67]
wire [2:0] _res_hit_lsbsLess_T_64 = _res_hit_lsbsLess_T_63; // @[PMP.scala:82:{25,42}]
wire [31:0] _res_hit_lsbsLess_T_66 = ~_res_hit_lsbsLess_T_65; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_lsbsLess_T_67 = {_res_hit_lsbsLess_T_66[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_lsbsLess_T_68 = ~_res_hit_lsbsLess_T_67; // @[PMP.scala:60:{27,48}]
wire [2:0] _res_hit_lsbsLess_T_69 = _res_hit_lsbsLess_T_68[2:0]; // @[PMP.scala:60:27, :82:64]
wire res_hit_lsbsLess_9 = _res_hit_lsbsLess_T_64 < _res_hit_lsbsLess_T_69; // @[PMP.scala:82:{42,53,64}]
wire _res_hit_T_61 = res_hit_msbsEqual_9 & res_hit_lsbsLess_9; // @[PMP.scala:81:69, :82:53, :83:30]
wire _res_hit_T_62 = res_hit_msbsLess_9 | _res_hit_T_61; // @[PMP.scala:80:39, :83:{16,30}]
wire _res_hit_T_63 = _res_hit_T_60 & _res_hit_T_62; // @[PMP.scala:83:16, :88:5, :94:48]
wire _res_hit_T_64 = _res_hit_T_54 & _res_hit_T_63; // @[PMP.scala:46:26, :94:48, :132:61]
wire res_hit_4 = _res_hit_T_52 ? _res_hit_T_53 : _res_hit_T_64; // @[PMP.scala:45:20, :71:16, :132:{8,61}]
wire _res_ignore_T_4 = ~io_pmp_3_cfg_l_0; // @[PMP.scala:143:7, :164:29]
wire res_ignore_4 = default_0 & _res_ignore_T_4; // @[PMP.scala:156:56, :164:{26,29}]
wire [2:0] _res_aligned_lsbMask_T_9 = _res_aligned_lsbMask_T_8[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] res_aligned_lsbMask_4 = ~_res_aligned_lsbMask_T_9; // @[package.scala:243:{46,76}]
wire [31:0] _res_aligned_straddlesLowerBound_T_70 = ~_res_aligned_straddlesLowerBound_T_69; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_aligned_straddlesLowerBound_T_71 = {_res_aligned_straddlesLowerBound_T_70[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_aligned_straddlesLowerBound_T_72 = ~_res_aligned_straddlesLowerBound_T_71; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_aligned_straddlesLowerBound_T_73 = _res_aligned_straddlesLowerBound_T_72[31:3]; // @[PMP.scala:60:27, :123:67]
wire [28:0] _res_aligned_straddlesLowerBound_T_74 = _res_aligned_straddlesLowerBound_T_68 ^ _res_aligned_straddlesLowerBound_T_73; // @[PMP.scala:123:{35,49,67}]
wire _res_aligned_straddlesLowerBound_T_75 = _res_aligned_straddlesLowerBound_T_74 == 29'h0; // @[PMP.scala:80:52, :81:54, :123:{49,67,82}]
wire [31:0] _res_aligned_straddlesLowerBound_T_77 = ~_res_aligned_straddlesLowerBound_T_76; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_aligned_straddlesLowerBound_T_78 = {_res_aligned_straddlesLowerBound_T_77[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_aligned_straddlesLowerBound_T_79 = ~_res_aligned_straddlesLowerBound_T_78; // @[PMP.scala:60:{27,48}]
wire [2:0] _res_aligned_straddlesLowerBound_T_80 = _res_aligned_straddlesLowerBound_T_79[2:0]; // @[PMP.scala:60:27, :123:108]
wire [2:0] _res_aligned_straddlesLowerBound_T_82 = ~_res_aligned_straddlesLowerBound_T_81; // @[PMP.scala:123:{127,129}]
wire [2:0] _res_aligned_straddlesLowerBound_T_83 = _res_aligned_straddlesLowerBound_T_80 & _res_aligned_straddlesLowerBound_T_82; // @[PMP.scala:123:{108,125,127}]
wire _res_aligned_straddlesLowerBound_T_84 = |_res_aligned_straddlesLowerBound_T_83; // @[PMP.scala:123:{125,147}]
wire res_aligned_straddlesLowerBound_4 = _res_aligned_straddlesLowerBound_T_75 & _res_aligned_straddlesLowerBound_T_84; // @[PMP.scala:123:{82,90,147}]
wire [31:0] _res_aligned_straddlesUpperBound_T_70 = ~_res_aligned_straddlesUpperBound_T_69; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_aligned_straddlesUpperBound_T_71 = {_res_aligned_straddlesUpperBound_T_70[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_aligned_straddlesUpperBound_T_72 = ~_res_aligned_straddlesUpperBound_T_71; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_aligned_straddlesUpperBound_T_73 = _res_aligned_straddlesUpperBound_T_72[31:3]; // @[PMP.scala:60:27, :124:62]
wire [28:0] _res_aligned_straddlesUpperBound_T_74 = _res_aligned_straddlesUpperBound_T_68 ^ _res_aligned_straddlesUpperBound_T_73; // @[PMP.scala:124:{35,49,62}]
wire _res_aligned_straddlesUpperBound_T_75 = _res_aligned_straddlesUpperBound_T_74 == 29'h0; // @[PMP.scala:80:52, :81:54, :123:67, :124:{49,77}]
wire [31:0] _res_aligned_straddlesUpperBound_T_77 = ~_res_aligned_straddlesUpperBound_T_76; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_aligned_straddlesUpperBound_T_78 = {_res_aligned_straddlesUpperBound_T_77[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_aligned_straddlesUpperBound_T_79 = ~_res_aligned_straddlesUpperBound_T_78; // @[PMP.scala:60:{27,48}]
wire [2:0] _res_aligned_straddlesUpperBound_T_80 = _res_aligned_straddlesUpperBound_T_79[2:0]; // @[PMP.scala:60:27, :124:98]
wire [2:0] _res_aligned_straddlesUpperBound_T_82 = _res_aligned_straddlesUpperBound_T_81 | res_aligned_lsbMask_4; // @[package.scala:243:46]
wire [2:0] _res_aligned_straddlesUpperBound_T_83 = _res_aligned_straddlesUpperBound_T_80 & _res_aligned_straddlesUpperBound_T_82; // @[PMP.scala:124:{98,115,136}]
wire _res_aligned_straddlesUpperBound_T_84 = |_res_aligned_straddlesUpperBound_T_83; // @[PMP.scala:124:{115,148}]
wire res_aligned_straddlesUpperBound_4 = _res_aligned_straddlesUpperBound_T_75 & _res_aligned_straddlesUpperBound_T_84; // @[PMP.scala:124:{77,85,148}]
wire _res_aligned_rangeAligned_T_4 = res_aligned_straddlesLowerBound_4 | res_aligned_straddlesUpperBound_4; // @[PMP.scala:123:90, :124:85, :125:46]
wire res_aligned_rangeAligned_4 = ~_res_aligned_rangeAligned_T_4; // @[PMP.scala:125:{24,46}]
wire [2:0] _res_aligned_pow2Aligned_T_13 = ~_res_aligned_pow2Aligned_T_12; // @[PMP.scala:126:{34,39}]
wire [2:0] _res_aligned_pow2Aligned_T_14 = res_aligned_lsbMask_4 & _res_aligned_pow2Aligned_T_13; // @[package.scala:243:46]
wire res_aligned_pow2Aligned_4 = _res_aligned_pow2Aligned_T_14 == 3'h0; // @[PMP.scala:82:64, :123:{108,125}, :126:{32,57}]
wire res_aligned_4 = _res_aligned_T_4 ? res_aligned_pow2Aligned_4 : res_aligned_rangeAligned_4; // @[PMP.scala:45:20, :125:24, :126:57, :127:8]
wire _res_T_180 = io_pmp_3_cfg_a_0 == 2'h0; // @[PMP.scala:143:7, :168:32]
wire _GEN_22 = io_pmp_3_cfg_a_0 == 2'h1; // @[PMP.scala:143:7, :168:32]
wire _res_T_181; // @[PMP.scala:168:32]
assign _res_T_181 = _GEN_22; // @[PMP.scala:168:32]
wire _res_T_200; // @[PMP.scala:177:61]
assign _res_T_200 = _GEN_22; // @[PMP.scala:168:32, :177:61]
wire _res_T_204; // @[PMP.scala:178:63]
assign _res_T_204 = _GEN_22; // @[PMP.scala:168:32, :178:63]
wire _GEN_23 = io_pmp_3_cfg_a_0 == 2'h2; // @[PMP.scala:143:7, :168:32]
wire _res_T_182; // @[PMP.scala:168:32]
assign _res_T_182 = _GEN_23; // @[PMP.scala:168:32]
wire _res_T_209; // @[PMP.scala:177:61]
assign _res_T_209 = _GEN_23; // @[PMP.scala:168:32, :177:61]
wire _res_T_213; // @[PMP.scala:178:63]
assign _res_T_213 = _GEN_23; // @[PMP.scala:168:32, :178:63]
wire _res_T_183 = &io_pmp_3_cfg_a_0; // @[PMP.scala:143:7, :168:32]
wire [1:0] _GEN_24 = {io_pmp_3_cfg_x_0, io_pmp_3_cfg_w_0}; // @[PMP.scala:143:7, :174:26]
wire [1:0] res_hi_24; // @[PMP.scala:174:26]
assign res_hi_24 = _GEN_24; // @[PMP.scala:174:26]
wire [1:0] res_hi_25; // @[PMP.scala:174:26]
assign res_hi_25 = _GEN_24; // @[PMP.scala:174:26]
wire [1:0] res_hi_26; // @[PMP.scala:174:26]
assign res_hi_26 = _GEN_24; // @[PMP.scala:174:26]
wire [1:0] res_hi_27; // @[PMP.scala:174:26]
assign res_hi_27 = _GEN_24; // @[PMP.scala:174:26]
wire [1:0] res_hi_28; // @[PMP.scala:174:26]
assign res_hi_28 = _GEN_24; // @[PMP.scala:174:26]
wire [1:0] res_hi_29; // @[PMP.scala:174:26]
assign res_hi_29 = _GEN_24; // @[PMP.scala:174:26]
wire [2:0] _res_T_185 = {res_hi_24, io_pmp_3_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_186 = _res_T_185 == 3'h0; // @[PMP.scala:82:64, :123:{108,125}, :174:{26,60}]
wire [2:0] _res_T_187 = {res_hi_25, io_pmp_3_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_188 = _res_T_187 == 3'h1; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_189 = {res_hi_26, io_pmp_3_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_190 = _res_T_189 == 3'h3; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_191 = {res_hi_27, io_pmp_3_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_192 = _res_T_191 == 3'h4; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_193 = {res_hi_28, io_pmp_3_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_194 = _res_T_193 == 3'h5; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_195 = {res_hi_29, io_pmp_3_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_196 = &_res_T_195; // @[PMP.scala:174:{26,60}]
wire _res_T_197 = ~res_ignore_4; // @[PMP.scala:164:26, :177:22]
wire _res_T_198 = _res_T_197 & res_hit_4; // @[PMP.scala:132:8, :177:{22,30}]
wire _res_T_199 = _res_T_198 & res_aligned_4; // @[PMP.scala:127:8, :177:{30,37}]
wire _res_T_201 = _res_T_199 & _res_T_200; // @[PMP.scala:177:{37,48,61}]
wire _GEN_25 = io_pmp_3_cfg_l_0 & res_hit_4; // @[PMP.scala:132:8, :143:7, :178:32]
wire _res_T_202; // @[PMP.scala:178:32]
assign _res_T_202 = _GEN_25; // @[PMP.scala:178:32]
wire _res_T_211; // @[PMP.scala:178:32]
assign _res_T_211 = _GEN_25; // @[PMP.scala:178:32]
wire _res_T_220; // @[PMP.scala:178:32]
assign _res_T_220 = _GEN_25; // @[PMP.scala:178:32]
wire _res_T_203 = _res_T_202 & res_aligned_4; // @[PMP.scala:127:8, :178:{32,39}]
wire _res_T_205 = _res_T_203 & _res_T_204; // @[PMP.scala:178:{39,50,63}]
wire _res_T_206 = ~res_ignore_4; // @[PMP.scala:164:26, :177:22]
wire _res_T_207 = _res_T_206 & res_hit_4; // @[PMP.scala:132:8, :177:{22,30}]
wire _res_T_208 = _res_T_207 & res_aligned_4; // @[PMP.scala:127:8, :177:{30,37}]
wire _res_T_210 = _res_T_208 & _res_T_209; // @[PMP.scala:177:{37,48,61}]
wire _res_T_212 = _res_T_211 & res_aligned_4; // @[PMP.scala:127:8, :178:{32,39}]
wire _res_T_214 = _res_T_212 & _res_T_213; // @[PMP.scala:178:{39,50,63}]
wire _res_T_215 = ~res_ignore_4; // @[PMP.scala:164:26, :177:22]
wire _res_T_216 = _res_T_215 & res_hit_4; // @[PMP.scala:132:8, :177:{22,30}]
wire _res_T_217 = _res_T_216 & res_aligned_4; // @[PMP.scala:127:8, :177:{30,37}]
wire _res_T_218 = &io_pmp_3_cfg_a_0; // @[PMP.scala:143:7, :168:32, :177:61]
wire _res_T_219 = _res_T_217 & _res_T_218; // @[PMP.scala:177:{37,48,61}]
wire _res_T_221 = _res_T_220 & res_aligned_4; // @[PMP.scala:127:8, :178:{32,39}]
wire _res_T_222 = &io_pmp_3_cfg_a_0; // @[PMP.scala:143:7, :168:32, :178:63]
wire _res_T_223 = _res_T_221 & _res_T_222; // @[PMP.scala:178:{39,50,63}]
wire _res_cur_cfg_x_T_9; // @[PMP.scala:184:26]
wire _res_cur_cfg_w_T_9; // @[PMP.scala:183:26]
wire _res_cur_cfg_r_T_9; // @[PMP.scala:182:26]
wire res_cur_4_cfg_x; // @[PMP.scala:181:23]
wire res_cur_4_cfg_w; // @[PMP.scala:181:23]
wire res_cur_4_cfg_r; // @[PMP.scala:181:23]
wire _res_cur_cfg_r_T_8 = io_pmp_3_cfg_r_0 | res_ignore_4; // @[PMP.scala:143:7, :164:26, :182:40]
assign _res_cur_cfg_r_T_9 = res_aligned_4 & _res_cur_cfg_r_T_8; // @[PMP.scala:127:8, :182:{26,40}]
assign res_cur_4_cfg_r = _res_cur_cfg_r_T_9; // @[PMP.scala:181:23, :182:26]
wire _res_cur_cfg_w_T_8 = io_pmp_3_cfg_w_0 | res_ignore_4; // @[PMP.scala:143:7, :164:26, :183:40]
assign _res_cur_cfg_w_T_9 = res_aligned_4 & _res_cur_cfg_w_T_8; // @[PMP.scala:127:8, :183:{26,40}]
assign res_cur_4_cfg_w = _res_cur_cfg_w_T_9; // @[PMP.scala:181:23, :183:26]
wire _res_cur_cfg_x_T_8 = io_pmp_3_cfg_x_0 | res_ignore_4; // @[PMP.scala:143:7, :164:26, :184:40]
assign _res_cur_cfg_x_T_9 = res_aligned_4 & _res_cur_cfg_x_T_8; // @[PMP.scala:127:8, :184:{26,40}]
assign res_cur_4_cfg_x = _res_cur_cfg_x_T_9; // @[PMP.scala:181:23, :184:26]
wire _res_T_224_cfg_l = res_hit_4 ? res_cur_4_cfg_l : _res_T_179_cfg_l; // @[PMP.scala:132:8, :181:23, :185:8]
wire [1:0] _res_T_224_cfg_a = res_hit_4 ? res_cur_4_cfg_a : _res_T_179_cfg_a; // @[PMP.scala:132:8, :181:23, :185:8]
wire _res_T_224_cfg_x = res_hit_4 ? res_cur_4_cfg_x : _res_T_179_cfg_x; // @[PMP.scala:132:8, :181:23, :185:8]
wire _res_T_224_cfg_w = res_hit_4 ? res_cur_4_cfg_w : _res_T_179_cfg_w; // @[PMP.scala:132:8, :181:23, :185:8]
wire _res_T_224_cfg_r = res_hit_4 ? res_cur_4_cfg_r : _res_T_179_cfg_r; // @[PMP.scala:132:8, :181:23, :185:8]
wire [29:0] _res_T_224_addr = res_hit_4 ? res_cur_4_addr : _res_T_179_addr; // @[PMP.scala:132:8, :181:23, :185:8]
wire [31:0] _res_T_224_mask = res_hit_4 ? res_cur_4_mask : _res_T_179_mask; // @[PMP.scala:132:8, :181:23, :185:8]
wire _res_hit_T_65 = io_pmp_2_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7]
wire _res_aligned_T_5 = io_pmp_2_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7]
wire [2:0] _res_hit_lsbMask_T_16 = _res_hit_lsbMask_T_15[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] _res_hit_lsbMask_T_17 = ~_res_hit_lsbMask_T_16; // @[package.scala:243:{46,76}]
wire [28:0] _res_hit_msbMatch_T_56 = io_pmp_2_mask_0[31:3]; // @[PMP.scala:68:26, :69:72, :143:7]
wire [2:0] _res_aligned_pow2Aligned_T_15 = io_pmp_2_mask_0[2:0]; // @[PMP.scala:68:26, :126:39, :143:7]
wire [31:0] res_hit_lsbMask_5 = {_res_hit_msbMatch_T_56, _res_aligned_pow2Aligned_T_15 | _res_hit_lsbMask_T_17}; // @[package.scala:243:46]
wire [31:0] _res_hit_msbMatch_T_52 = ~_res_hit_msbMatch_T_51; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_msbMatch_T_53 = {_res_hit_msbMatch_T_52[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbMatch_T_54 = ~_res_hit_msbMatch_T_53; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_hit_msbMatch_T_55 = _res_hit_msbMatch_T_54[31:3]; // @[PMP.scala:60:27, :69:53]
wire [28:0] _res_hit_msbMatch_T_57 = _res_hit_msbMatch_T_50 ^ _res_hit_msbMatch_T_55; // @[PMP.scala:63:47, :69:{29,53}]
wire [28:0] _res_hit_msbMatch_T_58 = ~_res_hit_msbMatch_T_56; // @[PMP.scala:63:54, :69:72]
wire [28:0] _res_hit_msbMatch_T_59 = _res_hit_msbMatch_T_57 & _res_hit_msbMatch_T_58; // @[PMP.scala:63:{47,52,54}]
wire res_hit_msbMatch_5 = _res_hit_msbMatch_T_59 == 29'h0; // @[PMP.scala:63:{52,58}, :80:52, :81:54, :123:67]
wire [31:0] _res_hit_lsbMatch_T_52 = ~_res_hit_lsbMatch_T_51; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_lsbMatch_T_53 = {_res_hit_lsbMatch_T_52[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_lsbMatch_T_54 = ~_res_hit_lsbMatch_T_53; // @[PMP.scala:60:{27,48}]
wire [2:0] _res_hit_lsbMatch_T_55 = _res_hit_lsbMatch_T_54[2:0]; // @[PMP.scala:60:27, :70:55]
wire [2:0] _res_hit_lsbMatch_T_56 = res_hit_lsbMask_5[2:0]; // @[PMP.scala:68:26, :70:80]
wire [2:0] _res_hit_lsbMatch_T_57 = _res_hit_lsbMatch_T_50 ^ _res_hit_lsbMatch_T_55; // @[PMP.scala:63:47, :70:{28,55}]
wire [2:0] _res_hit_lsbMatch_T_58 = ~_res_hit_lsbMatch_T_56; // @[PMP.scala:63:54, :70:80]
wire [2:0] _res_hit_lsbMatch_T_59 = _res_hit_lsbMatch_T_57 & _res_hit_lsbMatch_T_58; // @[PMP.scala:63:{47,52,54}]
wire res_hit_lsbMatch_5 = _res_hit_lsbMatch_T_59 == 3'h0; // @[PMP.scala:63:{52,58}, :82:64, :123:{108,125}]
wire _res_hit_T_66 = res_hit_msbMatch_5 & res_hit_lsbMatch_5; // @[PMP.scala:63:58, :71:16]
wire _res_hit_T_67 = io_pmp_2_cfg_a_0[0]; // @[PMP.scala:46:26, :143:7]
wire [2:0] _res_hit_T_69 = _res_hit_T_68[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] _res_hit_T_70 = ~_res_hit_T_69; // @[package.scala:243:{46,76}]
wire [31:0] _GEN_26 = {io_pmp_1_addr_0, 2'h0}; // @[PMP.scala:60:36, :143:7]
wire [31:0] _res_hit_msbsLess_T_61; // @[PMP.scala:60:36]
assign _res_hit_msbsLess_T_61 = _GEN_26; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbsEqual_T_71; // @[PMP.scala:60:36]
assign _res_hit_msbsEqual_T_71 = _GEN_26; // @[PMP.scala:60:36]
wire [31:0] _res_hit_lsbsLess_T_72; // @[PMP.scala:60:36]
assign _res_hit_lsbsLess_T_72 = _GEN_26; // @[PMP.scala:60:36]
wire [31:0] _res_aligned_straddlesLowerBound_T_86; // @[PMP.scala:60:36]
assign _res_aligned_straddlesLowerBound_T_86 = _GEN_26; // @[PMP.scala:60:36]
wire [31:0] _res_aligned_straddlesLowerBound_T_93; // @[PMP.scala:60:36]
assign _res_aligned_straddlesLowerBound_T_93 = _GEN_26; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbMatch_T_61; // @[PMP.scala:60:36]
assign _res_hit_msbMatch_T_61 = _GEN_26; // @[PMP.scala:60:36]
wire [31:0] _res_hit_lsbMatch_T_61; // @[PMP.scala:60:36]
assign _res_hit_lsbMatch_T_61 = _GEN_26; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbsLess_T_79; // @[PMP.scala:60:36]
assign _res_hit_msbsLess_T_79 = _GEN_26; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbsEqual_T_92; // @[PMP.scala:60:36]
assign _res_hit_msbsEqual_T_92 = _GEN_26; // @[PMP.scala:60:36]
wire [31:0] _res_hit_lsbsLess_T_93; // @[PMP.scala:60:36]
assign _res_hit_lsbsLess_T_93 = _GEN_26; // @[PMP.scala:60:36]
wire [31:0] _res_aligned_straddlesUpperBound_T_103; // @[PMP.scala:60:36]
assign _res_aligned_straddlesUpperBound_T_103 = _GEN_26; // @[PMP.scala:60:36]
wire [31:0] _res_aligned_straddlesUpperBound_T_110; // @[PMP.scala:60:36]
assign _res_aligned_straddlesUpperBound_T_110 = _GEN_26; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbsLess_T_62 = ~_res_hit_msbsLess_T_61; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_msbsLess_T_63 = {_res_hit_msbsLess_T_62[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbsLess_T_64 = ~_res_hit_msbsLess_T_63; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_hit_msbsLess_T_65 = _res_hit_msbsLess_T_64[31:3]; // @[PMP.scala:60:27, :80:52]
wire res_hit_msbsLess_10 = _res_hit_msbsLess_T_60 < _res_hit_msbsLess_T_65; // @[PMP.scala:80:{25,39,52}]
wire [31:0] _res_hit_msbsEqual_T_72 = ~_res_hit_msbsEqual_T_71; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_msbsEqual_T_73 = {_res_hit_msbsEqual_T_72[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbsEqual_T_74 = ~_res_hit_msbsEqual_T_73; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_hit_msbsEqual_T_75 = _res_hit_msbsEqual_T_74[31:3]; // @[PMP.scala:60:27, :81:54]
wire [28:0] _res_hit_msbsEqual_T_76 = _res_hit_msbsEqual_T_70 ^ _res_hit_msbsEqual_T_75; // @[PMP.scala:81:{27,41,54}]
wire res_hit_msbsEqual_10 = _res_hit_msbsEqual_T_76 == 29'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67]
wire [2:0] _res_hit_lsbsLess_T_71 = _res_hit_lsbsLess_T_70 | _res_hit_T_70; // @[package.scala:243:46]
wire [31:0] _res_hit_lsbsLess_T_73 = ~_res_hit_lsbsLess_T_72; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_lsbsLess_T_74 = {_res_hit_lsbsLess_T_73[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_lsbsLess_T_75 = ~_res_hit_lsbsLess_T_74; // @[PMP.scala:60:{27,48}]
wire [2:0] _res_hit_lsbsLess_T_76 = _res_hit_lsbsLess_T_75[2:0]; // @[PMP.scala:60:27, :82:64]
wire res_hit_lsbsLess_10 = _res_hit_lsbsLess_T_71 < _res_hit_lsbsLess_T_76; // @[PMP.scala:82:{42,53,64}]
wire _res_hit_T_71 = res_hit_msbsEqual_10 & res_hit_lsbsLess_10; // @[PMP.scala:81:69, :82:53, :83:30]
wire _res_hit_T_72 = res_hit_msbsLess_10 | _res_hit_T_71; // @[PMP.scala:80:39, :83:{16,30}]
wire _res_hit_T_73 = ~_res_hit_T_72; // @[PMP.scala:83:16, :88:5]
wire [31:0] _res_hit_msbsLess_T_68 = ~_res_hit_msbsLess_T_67; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_msbsLess_T_69 = {_res_hit_msbsLess_T_68[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbsLess_T_70 = ~_res_hit_msbsLess_T_69; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_hit_msbsLess_T_71 = _res_hit_msbsLess_T_70[31:3]; // @[PMP.scala:60:27, :80:52]
wire res_hit_msbsLess_11 = _res_hit_msbsLess_T_66 < _res_hit_msbsLess_T_71; // @[PMP.scala:80:{25,39,52}]
wire [31:0] _res_hit_msbsEqual_T_79 = ~_res_hit_msbsEqual_T_78; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_msbsEqual_T_80 = {_res_hit_msbsEqual_T_79[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbsEqual_T_81 = ~_res_hit_msbsEqual_T_80; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_hit_msbsEqual_T_82 = _res_hit_msbsEqual_T_81[31:3]; // @[PMP.scala:60:27, :81:54]
wire [28:0] _res_hit_msbsEqual_T_83 = _res_hit_msbsEqual_T_77 ^ _res_hit_msbsEqual_T_82; // @[PMP.scala:81:{27,41,54}]
wire res_hit_msbsEqual_11 = _res_hit_msbsEqual_T_83 == 29'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67]
wire [2:0] _res_hit_lsbsLess_T_78 = _res_hit_lsbsLess_T_77; // @[PMP.scala:82:{25,42}]
wire [31:0] _res_hit_lsbsLess_T_80 = ~_res_hit_lsbsLess_T_79; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_lsbsLess_T_81 = {_res_hit_lsbsLess_T_80[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_lsbsLess_T_82 = ~_res_hit_lsbsLess_T_81; // @[PMP.scala:60:{27,48}]
wire [2:0] _res_hit_lsbsLess_T_83 = _res_hit_lsbsLess_T_82[2:0]; // @[PMP.scala:60:27, :82:64]
wire res_hit_lsbsLess_11 = _res_hit_lsbsLess_T_78 < _res_hit_lsbsLess_T_83; // @[PMP.scala:82:{42,53,64}]
wire _res_hit_T_74 = res_hit_msbsEqual_11 & res_hit_lsbsLess_11; // @[PMP.scala:81:69, :82:53, :83:30]
wire _res_hit_T_75 = res_hit_msbsLess_11 | _res_hit_T_74; // @[PMP.scala:80:39, :83:{16,30}]
wire _res_hit_T_76 = _res_hit_T_73 & _res_hit_T_75; // @[PMP.scala:83:16, :88:5, :94:48]
wire _res_hit_T_77 = _res_hit_T_67 & _res_hit_T_76; // @[PMP.scala:46:26, :94:48, :132:61]
wire res_hit_5 = _res_hit_T_65 ? _res_hit_T_66 : _res_hit_T_77; // @[PMP.scala:45:20, :71:16, :132:{8,61}]
wire _res_ignore_T_5 = ~io_pmp_2_cfg_l_0; // @[PMP.scala:143:7, :164:29]
wire res_ignore_5 = default_0 & _res_ignore_T_5; // @[PMP.scala:156:56, :164:{26,29}]
wire [2:0] _res_aligned_lsbMask_T_11 = _res_aligned_lsbMask_T_10[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] res_aligned_lsbMask_5 = ~_res_aligned_lsbMask_T_11; // @[package.scala:243:{46,76}]
wire [31:0] _res_aligned_straddlesLowerBound_T_87 = ~_res_aligned_straddlesLowerBound_T_86; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_aligned_straddlesLowerBound_T_88 = {_res_aligned_straddlesLowerBound_T_87[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_aligned_straddlesLowerBound_T_89 = ~_res_aligned_straddlesLowerBound_T_88; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_aligned_straddlesLowerBound_T_90 = _res_aligned_straddlesLowerBound_T_89[31:3]; // @[PMP.scala:60:27, :123:67]
wire [28:0] _res_aligned_straddlesLowerBound_T_91 = _res_aligned_straddlesLowerBound_T_85 ^ _res_aligned_straddlesLowerBound_T_90; // @[PMP.scala:123:{35,49,67}]
wire _res_aligned_straddlesLowerBound_T_92 = _res_aligned_straddlesLowerBound_T_91 == 29'h0; // @[PMP.scala:80:52, :81:54, :123:{49,67,82}]
wire [31:0] _res_aligned_straddlesLowerBound_T_94 = ~_res_aligned_straddlesLowerBound_T_93; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_aligned_straddlesLowerBound_T_95 = {_res_aligned_straddlesLowerBound_T_94[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_aligned_straddlesLowerBound_T_96 = ~_res_aligned_straddlesLowerBound_T_95; // @[PMP.scala:60:{27,48}]
wire [2:0] _res_aligned_straddlesLowerBound_T_97 = _res_aligned_straddlesLowerBound_T_96[2:0]; // @[PMP.scala:60:27, :123:108]
wire [2:0] _res_aligned_straddlesLowerBound_T_99 = ~_res_aligned_straddlesLowerBound_T_98; // @[PMP.scala:123:{127,129}]
wire [2:0] _res_aligned_straddlesLowerBound_T_100 = _res_aligned_straddlesLowerBound_T_97 & _res_aligned_straddlesLowerBound_T_99; // @[PMP.scala:123:{108,125,127}]
wire _res_aligned_straddlesLowerBound_T_101 = |_res_aligned_straddlesLowerBound_T_100; // @[PMP.scala:123:{125,147}]
wire res_aligned_straddlesLowerBound_5 = _res_aligned_straddlesLowerBound_T_92 & _res_aligned_straddlesLowerBound_T_101; // @[PMP.scala:123:{82,90,147}]
wire [31:0] _res_aligned_straddlesUpperBound_T_87 = ~_res_aligned_straddlesUpperBound_T_86; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_aligned_straddlesUpperBound_T_88 = {_res_aligned_straddlesUpperBound_T_87[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_aligned_straddlesUpperBound_T_89 = ~_res_aligned_straddlesUpperBound_T_88; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_aligned_straddlesUpperBound_T_90 = _res_aligned_straddlesUpperBound_T_89[31:3]; // @[PMP.scala:60:27, :124:62]
wire [28:0] _res_aligned_straddlesUpperBound_T_91 = _res_aligned_straddlesUpperBound_T_85 ^ _res_aligned_straddlesUpperBound_T_90; // @[PMP.scala:124:{35,49,62}]
wire _res_aligned_straddlesUpperBound_T_92 = _res_aligned_straddlesUpperBound_T_91 == 29'h0; // @[PMP.scala:80:52, :81:54, :123:67, :124:{49,77}]
wire [31:0] _res_aligned_straddlesUpperBound_T_94 = ~_res_aligned_straddlesUpperBound_T_93; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_aligned_straddlesUpperBound_T_95 = {_res_aligned_straddlesUpperBound_T_94[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_aligned_straddlesUpperBound_T_96 = ~_res_aligned_straddlesUpperBound_T_95; // @[PMP.scala:60:{27,48}]
wire [2:0] _res_aligned_straddlesUpperBound_T_97 = _res_aligned_straddlesUpperBound_T_96[2:0]; // @[PMP.scala:60:27, :124:98]
wire [2:0] _res_aligned_straddlesUpperBound_T_99 = _res_aligned_straddlesUpperBound_T_98 | res_aligned_lsbMask_5; // @[package.scala:243:46]
wire [2:0] _res_aligned_straddlesUpperBound_T_100 = _res_aligned_straddlesUpperBound_T_97 & _res_aligned_straddlesUpperBound_T_99; // @[PMP.scala:124:{98,115,136}]
wire _res_aligned_straddlesUpperBound_T_101 = |_res_aligned_straddlesUpperBound_T_100; // @[PMP.scala:124:{115,148}]
wire res_aligned_straddlesUpperBound_5 = _res_aligned_straddlesUpperBound_T_92 & _res_aligned_straddlesUpperBound_T_101; // @[PMP.scala:124:{77,85,148}]
wire _res_aligned_rangeAligned_T_5 = res_aligned_straddlesLowerBound_5 | res_aligned_straddlesUpperBound_5; // @[PMP.scala:123:90, :124:85, :125:46]
wire res_aligned_rangeAligned_5 = ~_res_aligned_rangeAligned_T_5; // @[PMP.scala:125:{24,46}]
wire [2:0] _res_aligned_pow2Aligned_T_16 = ~_res_aligned_pow2Aligned_T_15; // @[PMP.scala:126:{34,39}]
wire [2:0] _res_aligned_pow2Aligned_T_17 = res_aligned_lsbMask_5 & _res_aligned_pow2Aligned_T_16; // @[package.scala:243:46]
wire res_aligned_pow2Aligned_5 = _res_aligned_pow2Aligned_T_17 == 3'h0; // @[PMP.scala:82:64, :123:{108,125}, :126:{32,57}]
wire res_aligned_5 = _res_aligned_T_5 ? res_aligned_pow2Aligned_5 : res_aligned_rangeAligned_5; // @[PMP.scala:45:20, :125:24, :126:57, :127:8]
wire _res_T_225 = io_pmp_2_cfg_a_0 == 2'h0; // @[PMP.scala:143:7, :168:32]
wire _GEN_27 = io_pmp_2_cfg_a_0 == 2'h1; // @[PMP.scala:143:7, :168:32]
wire _res_T_226; // @[PMP.scala:168:32]
assign _res_T_226 = _GEN_27; // @[PMP.scala:168:32]
wire _res_T_245; // @[PMP.scala:177:61]
assign _res_T_245 = _GEN_27; // @[PMP.scala:168:32, :177:61]
wire _res_T_249; // @[PMP.scala:178:63]
assign _res_T_249 = _GEN_27; // @[PMP.scala:168:32, :178:63]
wire _GEN_28 = io_pmp_2_cfg_a_0 == 2'h2; // @[PMP.scala:143:7, :168:32]
wire _res_T_227; // @[PMP.scala:168:32]
assign _res_T_227 = _GEN_28; // @[PMP.scala:168:32]
wire _res_T_254; // @[PMP.scala:177:61]
assign _res_T_254 = _GEN_28; // @[PMP.scala:168:32, :177:61]
wire _res_T_258; // @[PMP.scala:178:63]
assign _res_T_258 = _GEN_28; // @[PMP.scala:168:32, :178:63]
wire _res_T_228 = &io_pmp_2_cfg_a_0; // @[PMP.scala:143:7, :168:32]
wire [1:0] _GEN_29 = {io_pmp_2_cfg_x_0, io_pmp_2_cfg_w_0}; // @[PMP.scala:143:7, :174:26]
wire [1:0] res_hi_30; // @[PMP.scala:174:26]
assign res_hi_30 = _GEN_29; // @[PMP.scala:174:26]
wire [1:0] res_hi_31; // @[PMP.scala:174:26]
assign res_hi_31 = _GEN_29; // @[PMP.scala:174:26]
wire [1:0] res_hi_32; // @[PMP.scala:174:26]
assign res_hi_32 = _GEN_29; // @[PMP.scala:174:26]
wire [1:0] res_hi_33; // @[PMP.scala:174:26]
assign res_hi_33 = _GEN_29; // @[PMP.scala:174:26]
wire [1:0] res_hi_34; // @[PMP.scala:174:26]
assign res_hi_34 = _GEN_29; // @[PMP.scala:174:26]
wire [1:0] res_hi_35; // @[PMP.scala:174:26]
assign res_hi_35 = _GEN_29; // @[PMP.scala:174:26]
wire [2:0] _res_T_230 = {res_hi_30, io_pmp_2_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_231 = _res_T_230 == 3'h0; // @[PMP.scala:82:64, :123:{108,125}, :174:{26,60}]
wire [2:0] _res_T_232 = {res_hi_31, io_pmp_2_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_233 = _res_T_232 == 3'h1; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_234 = {res_hi_32, io_pmp_2_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_235 = _res_T_234 == 3'h3; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_236 = {res_hi_33, io_pmp_2_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_237 = _res_T_236 == 3'h4; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_238 = {res_hi_34, io_pmp_2_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_239 = _res_T_238 == 3'h5; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_240 = {res_hi_35, io_pmp_2_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_241 = &_res_T_240; // @[PMP.scala:174:{26,60}]
wire _res_T_242 = ~res_ignore_5; // @[PMP.scala:164:26, :177:22]
wire _res_T_243 = _res_T_242 & res_hit_5; // @[PMP.scala:132:8, :177:{22,30}]
wire _res_T_244 = _res_T_243 & res_aligned_5; // @[PMP.scala:127:8, :177:{30,37}]
wire _res_T_246 = _res_T_244 & _res_T_245; // @[PMP.scala:177:{37,48,61}]
wire _GEN_30 = io_pmp_2_cfg_l_0 & res_hit_5; // @[PMP.scala:132:8, :143:7, :178:32]
wire _res_T_247; // @[PMP.scala:178:32]
assign _res_T_247 = _GEN_30; // @[PMP.scala:178:32]
wire _res_T_256; // @[PMP.scala:178:32]
assign _res_T_256 = _GEN_30; // @[PMP.scala:178:32]
wire _res_T_265; // @[PMP.scala:178:32]
assign _res_T_265 = _GEN_30; // @[PMP.scala:178:32]
wire _res_T_248 = _res_T_247 & res_aligned_5; // @[PMP.scala:127:8, :178:{32,39}]
wire _res_T_250 = _res_T_248 & _res_T_249; // @[PMP.scala:178:{39,50,63}]
wire _res_T_251 = ~res_ignore_5; // @[PMP.scala:164:26, :177:22]
wire _res_T_252 = _res_T_251 & res_hit_5; // @[PMP.scala:132:8, :177:{22,30}]
wire _res_T_253 = _res_T_252 & res_aligned_5; // @[PMP.scala:127:8, :177:{30,37}]
wire _res_T_255 = _res_T_253 & _res_T_254; // @[PMP.scala:177:{37,48,61}]
wire _res_T_257 = _res_T_256 & res_aligned_5; // @[PMP.scala:127:8, :178:{32,39}]
wire _res_T_259 = _res_T_257 & _res_T_258; // @[PMP.scala:178:{39,50,63}]
wire _res_T_260 = ~res_ignore_5; // @[PMP.scala:164:26, :177:22]
wire _res_T_261 = _res_T_260 & res_hit_5; // @[PMP.scala:132:8, :177:{22,30}]
wire _res_T_262 = _res_T_261 & res_aligned_5; // @[PMP.scala:127:8, :177:{30,37}]
wire _res_T_263 = &io_pmp_2_cfg_a_0; // @[PMP.scala:143:7, :168:32, :177:61]
wire _res_T_264 = _res_T_262 & _res_T_263; // @[PMP.scala:177:{37,48,61}]
wire _res_T_266 = _res_T_265 & res_aligned_5; // @[PMP.scala:127:8, :178:{32,39}]
wire _res_T_267 = &io_pmp_2_cfg_a_0; // @[PMP.scala:143:7, :168:32, :178:63]
wire _res_T_268 = _res_T_266 & _res_T_267; // @[PMP.scala:178:{39,50,63}]
wire _res_cur_cfg_x_T_11; // @[PMP.scala:184:26]
wire _res_cur_cfg_w_T_11; // @[PMP.scala:183:26]
wire _res_cur_cfg_r_T_11; // @[PMP.scala:182:26]
wire res_cur_5_cfg_x; // @[PMP.scala:181:23]
wire res_cur_5_cfg_w; // @[PMP.scala:181:23]
wire res_cur_5_cfg_r; // @[PMP.scala:181:23]
wire _res_cur_cfg_r_T_10 = io_pmp_2_cfg_r_0 | res_ignore_5; // @[PMP.scala:143:7, :164:26, :182:40]
assign _res_cur_cfg_r_T_11 = res_aligned_5 & _res_cur_cfg_r_T_10; // @[PMP.scala:127:8, :182:{26,40}]
assign res_cur_5_cfg_r = _res_cur_cfg_r_T_11; // @[PMP.scala:181:23, :182:26]
wire _res_cur_cfg_w_T_10 = io_pmp_2_cfg_w_0 | res_ignore_5; // @[PMP.scala:143:7, :164:26, :183:40]
assign _res_cur_cfg_w_T_11 = res_aligned_5 & _res_cur_cfg_w_T_10; // @[PMP.scala:127:8, :183:{26,40}]
assign res_cur_5_cfg_w = _res_cur_cfg_w_T_11; // @[PMP.scala:181:23, :183:26]
wire _res_cur_cfg_x_T_10 = io_pmp_2_cfg_x_0 | res_ignore_5; // @[PMP.scala:143:7, :164:26, :184:40]
assign _res_cur_cfg_x_T_11 = res_aligned_5 & _res_cur_cfg_x_T_10; // @[PMP.scala:127:8, :184:{26,40}]
assign res_cur_5_cfg_x = _res_cur_cfg_x_T_11; // @[PMP.scala:181:23, :184:26]
wire _res_T_269_cfg_l = res_hit_5 ? res_cur_5_cfg_l : _res_T_224_cfg_l; // @[PMP.scala:132:8, :181:23, :185:8]
wire [1:0] _res_T_269_cfg_a = res_hit_5 ? res_cur_5_cfg_a : _res_T_224_cfg_a; // @[PMP.scala:132:8, :181:23, :185:8]
wire _res_T_269_cfg_x = res_hit_5 ? res_cur_5_cfg_x : _res_T_224_cfg_x; // @[PMP.scala:132:8, :181:23, :185:8]
wire _res_T_269_cfg_w = res_hit_5 ? res_cur_5_cfg_w : _res_T_224_cfg_w; // @[PMP.scala:132:8, :181:23, :185:8]
wire _res_T_269_cfg_r = res_hit_5 ? res_cur_5_cfg_r : _res_T_224_cfg_r; // @[PMP.scala:132:8, :181:23, :185:8]
wire [29:0] _res_T_269_addr = res_hit_5 ? res_cur_5_addr : _res_T_224_addr; // @[PMP.scala:132:8, :181:23, :185:8]
wire [31:0] _res_T_269_mask = res_hit_5 ? res_cur_5_mask : _res_T_224_mask; // @[PMP.scala:132:8, :181:23, :185:8]
wire _res_hit_T_78 = io_pmp_1_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7]
wire _res_aligned_T_6 = io_pmp_1_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7]
wire [2:0] _res_hit_lsbMask_T_19 = _res_hit_lsbMask_T_18[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] _res_hit_lsbMask_T_20 = ~_res_hit_lsbMask_T_19; // @[package.scala:243:{46,76}]
wire [28:0] _res_hit_msbMatch_T_66 = io_pmp_1_mask_0[31:3]; // @[PMP.scala:68:26, :69:72, :143:7]
wire [2:0] _res_aligned_pow2Aligned_T_18 = io_pmp_1_mask_0[2:0]; // @[PMP.scala:68:26, :126:39, :143:7]
wire [31:0] res_hit_lsbMask_6 = {_res_hit_msbMatch_T_66, _res_aligned_pow2Aligned_T_18 | _res_hit_lsbMask_T_20}; // @[package.scala:243:46]
wire [31:0] _res_hit_msbMatch_T_62 = ~_res_hit_msbMatch_T_61; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_msbMatch_T_63 = {_res_hit_msbMatch_T_62[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbMatch_T_64 = ~_res_hit_msbMatch_T_63; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_hit_msbMatch_T_65 = _res_hit_msbMatch_T_64[31:3]; // @[PMP.scala:60:27, :69:53]
wire [28:0] _res_hit_msbMatch_T_67 = _res_hit_msbMatch_T_60 ^ _res_hit_msbMatch_T_65; // @[PMP.scala:63:47, :69:{29,53}]
wire [28:0] _res_hit_msbMatch_T_68 = ~_res_hit_msbMatch_T_66; // @[PMP.scala:63:54, :69:72]
wire [28:0] _res_hit_msbMatch_T_69 = _res_hit_msbMatch_T_67 & _res_hit_msbMatch_T_68; // @[PMP.scala:63:{47,52,54}]
wire res_hit_msbMatch_6 = _res_hit_msbMatch_T_69 == 29'h0; // @[PMP.scala:63:{52,58}, :80:52, :81:54, :123:67]
wire [31:0] _res_hit_lsbMatch_T_62 = ~_res_hit_lsbMatch_T_61; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_lsbMatch_T_63 = {_res_hit_lsbMatch_T_62[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_lsbMatch_T_64 = ~_res_hit_lsbMatch_T_63; // @[PMP.scala:60:{27,48}]
wire [2:0] _res_hit_lsbMatch_T_65 = _res_hit_lsbMatch_T_64[2:0]; // @[PMP.scala:60:27, :70:55]
wire [2:0] _res_hit_lsbMatch_T_66 = res_hit_lsbMask_6[2:0]; // @[PMP.scala:68:26, :70:80]
wire [2:0] _res_hit_lsbMatch_T_67 = _res_hit_lsbMatch_T_60 ^ _res_hit_lsbMatch_T_65; // @[PMP.scala:63:47, :70:{28,55}]
wire [2:0] _res_hit_lsbMatch_T_68 = ~_res_hit_lsbMatch_T_66; // @[PMP.scala:63:54, :70:80]
wire [2:0] _res_hit_lsbMatch_T_69 = _res_hit_lsbMatch_T_67 & _res_hit_lsbMatch_T_68; // @[PMP.scala:63:{47,52,54}]
wire res_hit_lsbMatch_6 = _res_hit_lsbMatch_T_69 == 3'h0; // @[PMP.scala:63:{52,58}, :82:64, :123:{108,125}]
wire _res_hit_T_79 = res_hit_msbMatch_6 & res_hit_lsbMatch_6; // @[PMP.scala:63:58, :71:16]
wire _res_hit_T_80 = io_pmp_1_cfg_a_0[0]; // @[PMP.scala:46:26, :143:7]
wire [2:0] _res_hit_T_82 = _res_hit_T_81[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] _res_hit_T_83 = ~_res_hit_T_82; // @[package.scala:243:{46,76}]
wire [31:0] _GEN_31 = {io_pmp_0_addr_0, 2'h0}; // @[PMP.scala:60:36, :143:7]
wire [31:0] _res_hit_msbsLess_T_73; // @[PMP.scala:60:36]
assign _res_hit_msbsLess_T_73 = _GEN_31; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbsEqual_T_85; // @[PMP.scala:60:36]
assign _res_hit_msbsEqual_T_85 = _GEN_31; // @[PMP.scala:60:36]
wire [31:0] _res_hit_lsbsLess_T_86; // @[PMP.scala:60:36]
assign _res_hit_lsbsLess_T_86 = _GEN_31; // @[PMP.scala:60:36]
wire [31:0] _res_aligned_straddlesLowerBound_T_103; // @[PMP.scala:60:36]
assign _res_aligned_straddlesLowerBound_T_103 = _GEN_31; // @[PMP.scala:60:36]
wire [31:0] _res_aligned_straddlesLowerBound_T_110; // @[PMP.scala:60:36]
assign _res_aligned_straddlesLowerBound_T_110 = _GEN_31; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbMatch_T_71; // @[PMP.scala:60:36]
assign _res_hit_msbMatch_T_71 = _GEN_31; // @[PMP.scala:60:36]
wire [31:0] _res_hit_lsbMatch_T_71; // @[PMP.scala:60:36]
assign _res_hit_lsbMatch_T_71 = _GEN_31; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbsLess_T_91; // @[PMP.scala:60:36]
assign _res_hit_msbsLess_T_91 = _GEN_31; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbsEqual_T_106; // @[PMP.scala:60:36]
assign _res_hit_msbsEqual_T_106 = _GEN_31; // @[PMP.scala:60:36]
wire [31:0] _res_hit_lsbsLess_T_107; // @[PMP.scala:60:36]
assign _res_hit_lsbsLess_T_107 = _GEN_31; // @[PMP.scala:60:36]
wire [31:0] _res_aligned_straddlesUpperBound_T_120; // @[PMP.scala:60:36]
assign _res_aligned_straddlesUpperBound_T_120 = _GEN_31; // @[PMP.scala:60:36]
wire [31:0] _res_aligned_straddlesUpperBound_T_127; // @[PMP.scala:60:36]
assign _res_aligned_straddlesUpperBound_T_127 = _GEN_31; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbsLess_T_74 = ~_res_hit_msbsLess_T_73; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_msbsLess_T_75 = {_res_hit_msbsLess_T_74[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbsLess_T_76 = ~_res_hit_msbsLess_T_75; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_hit_msbsLess_T_77 = _res_hit_msbsLess_T_76[31:3]; // @[PMP.scala:60:27, :80:52]
wire res_hit_msbsLess_12 = _res_hit_msbsLess_T_72 < _res_hit_msbsLess_T_77; // @[PMP.scala:80:{25,39,52}]
wire [31:0] _res_hit_msbsEqual_T_86 = ~_res_hit_msbsEqual_T_85; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_msbsEqual_T_87 = {_res_hit_msbsEqual_T_86[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbsEqual_T_88 = ~_res_hit_msbsEqual_T_87; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_hit_msbsEqual_T_89 = _res_hit_msbsEqual_T_88[31:3]; // @[PMP.scala:60:27, :81:54]
wire [28:0] _res_hit_msbsEqual_T_90 = _res_hit_msbsEqual_T_84 ^ _res_hit_msbsEqual_T_89; // @[PMP.scala:81:{27,41,54}]
wire res_hit_msbsEqual_12 = _res_hit_msbsEqual_T_90 == 29'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67]
wire [2:0] _res_hit_lsbsLess_T_85 = _res_hit_lsbsLess_T_84 | _res_hit_T_83; // @[package.scala:243:46]
wire [31:0] _res_hit_lsbsLess_T_87 = ~_res_hit_lsbsLess_T_86; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_lsbsLess_T_88 = {_res_hit_lsbsLess_T_87[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_lsbsLess_T_89 = ~_res_hit_lsbsLess_T_88; // @[PMP.scala:60:{27,48}]
wire [2:0] _res_hit_lsbsLess_T_90 = _res_hit_lsbsLess_T_89[2:0]; // @[PMP.scala:60:27, :82:64]
wire res_hit_lsbsLess_12 = _res_hit_lsbsLess_T_85 < _res_hit_lsbsLess_T_90; // @[PMP.scala:82:{42,53,64}]
wire _res_hit_T_84 = res_hit_msbsEqual_12 & res_hit_lsbsLess_12; // @[PMP.scala:81:69, :82:53, :83:30]
wire _res_hit_T_85 = res_hit_msbsLess_12 | _res_hit_T_84; // @[PMP.scala:80:39, :83:{16,30}]
wire _res_hit_T_86 = ~_res_hit_T_85; // @[PMP.scala:83:16, :88:5]
wire [31:0] _res_hit_msbsLess_T_80 = ~_res_hit_msbsLess_T_79; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_msbsLess_T_81 = {_res_hit_msbsLess_T_80[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbsLess_T_82 = ~_res_hit_msbsLess_T_81; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_hit_msbsLess_T_83 = _res_hit_msbsLess_T_82[31:3]; // @[PMP.scala:60:27, :80:52]
wire res_hit_msbsLess_13 = _res_hit_msbsLess_T_78 < _res_hit_msbsLess_T_83; // @[PMP.scala:80:{25,39,52}]
wire [31:0] _res_hit_msbsEqual_T_93 = ~_res_hit_msbsEqual_T_92; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_msbsEqual_T_94 = {_res_hit_msbsEqual_T_93[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbsEqual_T_95 = ~_res_hit_msbsEqual_T_94; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_hit_msbsEqual_T_96 = _res_hit_msbsEqual_T_95[31:3]; // @[PMP.scala:60:27, :81:54]
wire [28:0] _res_hit_msbsEqual_T_97 = _res_hit_msbsEqual_T_91 ^ _res_hit_msbsEqual_T_96; // @[PMP.scala:81:{27,41,54}]
wire res_hit_msbsEqual_13 = _res_hit_msbsEqual_T_97 == 29'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67]
wire [2:0] _res_hit_lsbsLess_T_92 = _res_hit_lsbsLess_T_91; // @[PMP.scala:82:{25,42}]
wire [31:0] _res_hit_lsbsLess_T_94 = ~_res_hit_lsbsLess_T_93; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_lsbsLess_T_95 = {_res_hit_lsbsLess_T_94[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_lsbsLess_T_96 = ~_res_hit_lsbsLess_T_95; // @[PMP.scala:60:{27,48}]
wire [2:0] _res_hit_lsbsLess_T_97 = _res_hit_lsbsLess_T_96[2:0]; // @[PMP.scala:60:27, :82:64]
wire res_hit_lsbsLess_13 = _res_hit_lsbsLess_T_92 < _res_hit_lsbsLess_T_97; // @[PMP.scala:82:{42,53,64}]
wire _res_hit_T_87 = res_hit_msbsEqual_13 & res_hit_lsbsLess_13; // @[PMP.scala:81:69, :82:53, :83:30]
wire _res_hit_T_88 = res_hit_msbsLess_13 | _res_hit_T_87; // @[PMP.scala:80:39, :83:{16,30}]
wire _res_hit_T_89 = _res_hit_T_86 & _res_hit_T_88; // @[PMP.scala:83:16, :88:5, :94:48]
wire _res_hit_T_90 = _res_hit_T_80 & _res_hit_T_89; // @[PMP.scala:46:26, :94:48, :132:61]
wire res_hit_6 = _res_hit_T_78 ? _res_hit_T_79 : _res_hit_T_90; // @[PMP.scala:45:20, :71:16, :132:{8,61}]
wire _res_ignore_T_6 = ~io_pmp_1_cfg_l_0; // @[PMP.scala:143:7, :164:29]
wire res_ignore_6 = default_0 & _res_ignore_T_6; // @[PMP.scala:156:56, :164:{26,29}]
wire [2:0] _res_aligned_lsbMask_T_13 = _res_aligned_lsbMask_T_12[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] res_aligned_lsbMask_6 = ~_res_aligned_lsbMask_T_13; // @[package.scala:243:{46,76}]
wire [31:0] _res_aligned_straddlesLowerBound_T_104 = ~_res_aligned_straddlesLowerBound_T_103; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_aligned_straddlesLowerBound_T_105 = {_res_aligned_straddlesLowerBound_T_104[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_aligned_straddlesLowerBound_T_106 = ~_res_aligned_straddlesLowerBound_T_105; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_aligned_straddlesLowerBound_T_107 = _res_aligned_straddlesLowerBound_T_106[31:3]; // @[PMP.scala:60:27, :123:67]
wire [28:0] _res_aligned_straddlesLowerBound_T_108 = _res_aligned_straddlesLowerBound_T_102 ^ _res_aligned_straddlesLowerBound_T_107; // @[PMP.scala:123:{35,49,67}]
wire _res_aligned_straddlesLowerBound_T_109 = _res_aligned_straddlesLowerBound_T_108 == 29'h0; // @[PMP.scala:80:52, :81:54, :123:{49,67,82}]
wire [31:0] _res_aligned_straddlesLowerBound_T_111 = ~_res_aligned_straddlesLowerBound_T_110; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_aligned_straddlesLowerBound_T_112 = {_res_aligned_straddlesLowerBound_T_111[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_aligned_straddlesLowerBound_T_113 = ~_res_aligned_straddlesLowerBound_T_112; // @[PMP.scala:60:{27,48}]
wire [2:0] _res_aligned_straddlesLowerBound_T_114 = _res_aligned_straddlesLowerBound_T_113[2:0]; // @[PMP.scala:60:27, :123:108]
wire [2:0] _res_aligned_straddlesLowerBound_T_116 = ~_res_aligned_straddlesLowerBound_T_115; // @[PMP.scala:123:{127,129}]
wire [2:0] _res_aligned_straddlesLowerBound_T_117 = _res_aligned_straddlesLowerBound_T_114 & _res_aligned_straddlesLowerBound_T_116; // @[PMP.scala:123:{108,125,127}]
wire _res_aligned_straddlesLowerBound_T_118 = |_res_aligned_straddlesLowerBound_T_117; // @[PMP.scala:123:{125,147}]
wire res_aligned_straddlesLowerBound_6 = _res_aligned_straddlesLowerBound_T_109 & _res_aligned_straddlesLowerBound_T_118; // @[PMP.scala:123:{82,90,147}]
wire [31:0] _res_aligned_straddlesUpperBound_T_104 = ~_res_aligned_straddlesUpperBound_T_103; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_aligned_straddlesUpperBound_T_105 = {_res_aligned_straddlesUpperBound_T_104[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_aligned_straddlesUpperBound_T_106 = ~_res_aligned_straddlesUpperBound_T_105; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_aligned_straddlesUpperBound_T_107 = _res_aligned_straddlesUpperBound_T_106[31:3]; // @[PMP.scala:60:27, :124:62]
wire [28:0] _res_aligned_straddlesUpperBound_T_108 = _res_aligned_straddlesUpperBound_T_102 ^ _res_aligned_straddlesUpperBound_T_107; // @[PMP.scala:124:{35,49,62}]
wire _res_aligned_straddlesUpperBound_T_109 = _res_aligned_straddlesUpperBound_T_108 == 29'h0; // @[PMP.scala:80:52, :81:54, :123:67, :124:{49,77}]
wire [31:0] _res_aligned_straddlesUpperBound_T_111 = ~_res_aligned_straddlesUpperBound_T_110; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_aligned_straddlesUpperBound_T_112 = {_res_aligned_straddlesUpperBound_T_111[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_aligned_straddlesUpperBound_T_113 = ~_res_aligned_straddlesUpperBound_T_112; // @[PMP.scala:60:{27,48}]
wire [2:0] _res_aligned_straddlesUpperBound_T_114 = _res_aligned_straddlesUpperBound_T_113[2:0]; // @[PMP.scala:60:27, :124:98]
wire [2:0] _res_aligned_straddlesUpperBound_T_116 = _res_aligned_straddlesUpperBound_T_115 | res_aligned_lsbMask_6; // @[package.scala:243:46]
wire [2:0] _res_aligned_straddlesUpperBound_T_117 = _res_aligned_straddlesUpperBound_T_114 & _res_aligned_straddlesUpperBound_T_116; // @[PMP.scala:124:{98,115,136}]
wire _res_aligned_straddlesUpperBound_T_118 = |_res_aligned_straddlesUpperBound_T_117; // @[PMP.scala:124:{115,148}]
wire res_aligned_straddlesUpperBound_6 = _res_aligned_straddlesUpperBound_T_109 & _res_aligned_straddlesUpperBound_T_118; // @[PMP.scala:124:{77,85,148}]
wire _res_aligned_rangeAligned_T_6 = res_aligned_straddlesLowerBound_6 | res_aligned_straddlesUpperBound_6; // @[PMP.scala:123:90, :124:85, :125:46]
wire res_aligned_rangeAligned_6 = ~_res_aligned_rangeAligned_T_6; // @[PMP.scala:125:{24,46}]
wire [2:0] _res_aligned_pow2Aligned_T_19 = ~_res_aligned_pow2Aligned_T_18; // @[PMP.scala:126:{34,39}]
wire [2:0] _res_aligned_pow2Aligned_T_20 = res_aligned_lsbMask_6 & _res_aligned_pow2Aligned_T_19; // @[package.scala:243:46]
wire res_aligned_pow2Aligned_6 = _res_aligned_pow2Aligned_T_20 == 3'h0; // @[PMP.scala:82:64, :123:{108,125}, :126:{32,57}]
wire res_aligned_6 = _res_aligned_T_6 ? res_aligned_pow2Aligned_6 : res_aligned_rangeAligned_6; // @[PMP.scala:45:20, :125:24, :126:57, :127:8]
wire _res_T_270 = io_pmp_1_cfg_a_0 == 2'h0; // @[PMP.scala:143:7, :168:32]
wire _GEN_32 = io_pmp_1_cfg_a_0 == 2'h1; // @[PMP.scala:143:7, :168:32]
wire _res_T_271; // @[PMP.scala:168:32]
assign _res_T_271 = _GEN_32; // @[PMP.scala:168:32]
wire _res_T_290; // @[PMP.scala:177:61]
assign _res_T_290 = _GEN_32; // @[PMP.scala:168:32, :177:61]
wire _res_T_294; // @[PMP.scala:178:63]
assign _res_T_294 = _GEN_32; // @[PMP.scala:168:32, :178:63]
wire _GEN_33 = io_pmp_1_cfg_a_0 == 2'h2; // @[PMP.scala:143:7, :168:32]
wire _res_T_272; // @[PMP.scala:168:32]
assign _res_T_272 = _GEN_33; // @[PMP.scala:168:32]
wire _res_T_299; // @[PMP.scala:177:61]
assign _res_T_299 = _GEN_33; // @[PMP.scala:168:32, :177:61]
wire _res_T_303; // @[PMP.scala:178:63]
assign _res_T_303 = _GEN_33; // @[PMP.scala:168:32, :178:63]
wire _res_T_273 = &io_pmp_1_cfg_a_0; // @[PMP.scala:143:7, :168:32]
wire [1:0] _GEN_34 = {io_pmp_1_cfg_x_0, io_pmp_1_cfg_w_0}; // @[PMP.scala:143:7, :174:26]
wire [1:0] res_hi_36; // @[PMP.scala:174:26]
assign res_hi_36 = _GEN_34; // @[PMP.scala:174:26]
wire [1:0] res_hi_37; // @[PMP.scala:174:26]
assign res_hi_37 = _GEN_34; // @[PMP.scala:174:26]
wire [1:0] res_hi_38; // @[PMP.scala:174:26]
assign res_hi_38 = _GEN_34; // @[PMP.scala:174:26]
wire [1:0] res_hi_39; // @[PMP.scala:174:26]
assign res_hi_39 = _GEN_34; // @[PMP.scala:174:26]
wire [1:0] res_hi_40; // @[PMP.scala:174:26]
assign res_hi_40 = _GEN_34; // @[PMP.scala:174:26]
wire [1:0] res_hi_41; // @[PMP.scala:174:26]
assign res_hi_41 = _GEN_34; // @[PMP.scala:174:26]
wire [2:0] _res_T_275 = {res_hi_36, io_pmp_1_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_276 = _res_T_275 == 3'h0; // @[PMP.scala:82:64, :123:{108,125}, :174:{26,60}]
wire [2:0] _res_T_277 = {res_hi_37, io_pmp_1_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_278 = _res_T_277 == 3'h1; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_279 = {res_hi_38, io_pmp_1_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_280 = _res_T_279 == 3'h3; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_281 = {res_hi_39, io_pmp_1_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_282 = _res_T_281 == 3'h4; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_283 = {res_hi_40, io_pmp_1_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_284 = _res_T_283 == 3'h5; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_285 = {res_hi_41, io_pmp_1_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_286 = &_res_T_285; // @[PMP.scala:174:{26,60}]
wire _res_T_287 = ~res_ignore_6; // @[PMP.scala:164:26, :177:22]
wire _res_T_288 = _res_T_287 & res_hit_6; // @[PMP.scala:132:8, :177:{22,30}]
wire _res_T_289 = _res_T_288 & res_aligned_6; // @[PMP.scala:127:8, :177:{30,37}]
wire _res_T_291 = _res_T_289 & _res_T_290; // @[PMP.scala:177:{37,48,61}]
wire _GEN_35 = io_pmp_1_cfg_l_0 & res_hit_6; // @[PMP.scala:132:8, :143:7, :178:32]
wire _res_T_292; // @[PMP.scala:178:32]
assign _res_T_292 = _GEN_35; // @[PMP.scala:178:32]
wire _res_T_301; // @[PMP.scala:178:32]
assign _res_T_301 = _GEN_35; // @[PMP.scala:178:32]
wire _res_T_310; // @[PMP.scala:178:32]
assign _res_T_310 = _GEN_35; // @[PMP.scala:178:32]
wire _res_T_293 = _res_T_292 & res_aligned_6; // @[PMP.scala:127:8, :178:{32,39}]
wire _res_T_295 = _res_T_293 & _res_T_294; // @[PMP.scala:178:{39,50,63}]
wire _res_T_296 = ~res_ignore_6; // @[PMP.scala:164:26, :177:22]
wire _res_T_297 = _res_T_296 & res_hit_6; // @[PMP.scala:132:8, :177:{22,30}]
wire _res_T_298 = _res_T_297 & res_aligned_6; // @[PMP.scala:127:8, :177:{30,37}]
wire _res_T_300 = _res_T_298 & _res_T_299; // @[PMP.scala:177:{37,48,61}]
wire _res_T_302 = _res_T_301 & res_aligned_6; // @[PMP.scala:127:8, :178:{32,39}]
wire _res_T_304 = _res_T_302 & _res_T_303; // @[PMP.scala:178:{39,50,63}]
wire _res_T_305 = ~res_ignore_6; // @[PMP.scala:164:26, :177:22]
wire _res_T_306 = _res_T_305 & res_hit_6; // @[PMP.scala:132:8, :177:{22,30}]
wire _res_T_307 = _res_T_306 & res_aligned_6; // @[PMP.scala:127:8, :177:{30,37}]
wire _res_T_308 = &io_pmp_1_cfg_a_0; // @[PMP.scala:143:7, :168:32, :177:61]
wire _res_T_309 = _res_T_307 & _res_T_308; // @[PMP.scala:177:{37,48,61}]
wire _res_T_311 = _res_T_310 & res_aligned_6; // @[PMP.scala:127:8, :178:{32,39}]
wire _res_T_312 = &io_pmp_1_cfg_a_0; // @[PMP.scala:143:7, :168:32, :178:63]
wire _res_T_313 = _res_T_311 & _res_T_312; // @[PMP.scala:178:{39,50,63}]
wire _res_cur_cfg_x_T_13; // @[PMP.scala:184:26]
wire _res_cur_cfg_w_T_13; // @[PMP.scala:183:26]
wire _res_cur_cfg_r_T_13; // @[PMP.scala:182:26]
wire res_cur_6_cfg_x; // @[PMP.scala:181:23]
wire res_cur_6_cfg_w; // @[PMP.scala:181:23]
wire res_cur_6_cfg_r; // @[PMP.scala:181:23]
wire _res_cur_cfg_r_T_12 = io_pmp_1_cfg_r_0 | res_ignore_6; // @[PMP.scala:143:7, :164:26, :182:40]
assign _res_cur_cfg_r_T_13 = res_aligned_6 & _res_cur_cfg_r_T_12; // @[PMP.scala:127:8, :182:{26,40}]
assign res_cur_6_cfg_r = _res_cur_cfg_r_T_13; // @[PMP.scala:181:23, :182:26]
wire _res_cur_cfg_w_T_12 = io_pmp_1_cfg_w_0 | res_ignore_6; // @[PMP.scala:143:7, :164:26, :183:40]
assign _res_cur_cfg_w_T_13 = res_aligned_6 & _res_cur_cfg_w_T_12; // @[PMP.scala:127:8, :183:{26,40}]
assign res_cur_6_cfg_w = _res_cur_cfg_w_T_13; // @[PMP.scala:181:23, :183:26]
wire _res_cur_cfg_x_T_12 = io_pmp_1_cfg_x_0 | res_ignore_6; // @[PMP.scala:143:7, :164:26, :184:40]
assign _res_cur_cfg_x_T_13 = res_aligned_6 & _res_cur_cfg_x_T_12; // @[PMP.scala:127:8, :184:{26,40}]
assign res_cur_6_cfg_x = _res_cur_cfg_x_T_13; // @[PMP.scala:181:23, :184:26]
wire _res_T_314_cfg_l = res_hit_6 ? res_cur_6_cfg_l : _res_T_269_cfg_l; // @[PMP.scala:132:8, :181:23, :185:8]
wire [1:0] _res_T_314_cfg_a = res_hit_6 ? res_cur_6_cfg_a : _res_T_269_cfg_a; // @[PMP.scala:132:8, :181:23, :185:8]
wire _res_T_314_cfg_x = res_hit_6 ? res_cur_6_cfg_x : _res_T_269_cfg_x; // @[PMP.scala:132:8, :181:23, :185:8]
wire _res_T_314_cfg_w = res_hit_6 ? res_cur_6_cfg_w : _res_T_269_cfg_w; // @[PMP.scala:132:8, :181:23, :185:8]
wire _res_T_314_cfg_r = res_hit_6 ? res_cur_6_cfg_r : _res_T_269_cfg_r; // @[PMP.scala:132:8, :181:23, :185:8]
wire [29:0] _res_T_314_addr = res_hit_6 ? res_cur_6_addr : _res_T_269_addr; // @[PMP.scala:132:8, :181:23, :185:8]
wire [31:0] _res_T_314_mask = res_hit_6 ? res_cur_6_mask : _res_T_269_mask; // @[PMP.scala:132:8, :181:23, :185:8]
wire _res_hit_T_91 = io_pmp_0_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7]
wire _res_aligned_T_7 = io_pmp_0_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7]
wire [2:0] _res_hit_lsbMask_T_22 = _res_hit_lsbMask_T_21[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] _res_hit_lsbMask_T_23 = ~_res_hit_lsbMask_T_22; // @[package.scala:243:{46,76}]
wire [28:0] _res_hit_msbMatch_T_76 = io_pmp_0_mask_0[31:3]; // @[PMP.scala:68:26, :69:72, :143:7]
wire [2:0] _res_aligned_pow2Aligned_T_21 = io_pmp_0_mask_0[2:0]; // @[PMP.scala:68:26, :126:39, :143:7]
wire [31:0] res_hit_lsbMask_7 = {_res_hit_msbMatch_T_76, _res_aligned_pow2Aligned_T_21 | _res_hit_lsbMask_T_23}; // @[package.scala:243:46]
wire [31:0] _res_hit_msbMatch_T_72 = ~_res_hit_msbMatch_T_71; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_msbMatch_T_73 = {_res_hit_msbMatch_T_72[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbMatch_T_74 = ~_res_hit_msbMatch_T_73; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_hit_msbMatch_T_75 = _res_hit_msbMatch_T_74[31:3]; // @[PMP.scala:60:27, :69:53]
wire [28:0] _res_hit_msbMatch_T_77 = _res_hit_msbMatch_T_70 ^ _res_hit_msbMatch_T_75; // @[PMP.scala:63:47, :69:{29,53}]
wire [28:0] _res_hit_msbMatch_T_78 = ~_res_hit_msbMatch_T_76; // @[PMP.scala:63:54, :69:72]
wire [28:0] _res_hit_msbMatch_T_79 = _res_hit_msbMatch_T_77 & _res_hit_msbMatch_T_78; // @[PMP.scala:63:{47,52,54}]
wire res_hit_msbMatch_7 = _res_hit_msbMatch_T_79 == 29'h0; // @[PMP.scala:63:{52,58}, :80:52, :81:54, :123:67]
wire [31:0] _res_hit_lsbMatch_T_72 = ~_res_hit_lsbMatch_T_71; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_lsbMatch_T_73 = {_res_hit_lsbMatch_T_72[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_lsbMatch_T_74 = ~_res_hit_lsbMatch_T_73; // @[PMP.scala:60:{27,48}]
wire [2:0] _res_hit_lsbMatch_T_75 = _res_hit_lsbMatch_T_74[2:0]; // @[PMP.scala:60:27, :70:55]
wire [2:0] _res_hit_lsbMatch_T_76 = res_hit_lsbMask_7[2:0]; // @[PMP.scala:68:26, :70:80]
wire [2:0] _res_hit_lsbMatch_T_77 = _res_hit_lsbMatch_T_70 ^ _res_hit_lsbMatch_T_75; // @[PMP.scala:63:47, :70:{28,55}]
wire [2:0] _res_hit_lsbMatch_T_78 = ~_res_hit_lsbMatch_T_76; // @[PMP.scala:63:54, :70:80]
wire [2:0] _res_hit_lsbMatch_T_79 = _res_hit_lsbMatch_T_77 & _res_hit_lsbMatch_T_78; // @[PMP.scala:63:{47,52,54}]
wire res_hit_lsbMatch_7 = _res_hit_lsbMatch_T_79 == 3'h0; // @[PMP.scala:63:{52,58}, :82:64, :123:{108,125}]
wire _res_hit_T_92 = res_hit_msbMatch_7 & res_hit_lsbMatch_7; // @[PMP.scala:63:58, :71:16]
wire _res_hit_T_93 = io_pmp_0_cfg_a_0[0]; // @[PMP.scala:46:26, :143:7]
wire [2:0] _res_hit_T_95 = _res_hit_T_94[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] _res_hit_T_96 = ~_res_hit_T_95; // @[package.scala:243:{46,76}]
wire [28:0] _res_hit_msbsEqual_T_104 = _res_hit_msbsEqual_T_98; // @[PMP.scala:81:{27,41}]
wire res_hit_msbsEqual_14 = _res_hit_msbsEqual_T_104 == 29'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67]
wire [2:0] _res_hit_lsbsLess_T_99 = _res_hit_lsbsLess_T_98 | _res_hit_T_96; // @[package.scala:243:46]
wire [31:0] _res_hit_msbsLess_T_92 = ~_res_hit_msbsLess_T_91; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_msbsLess_T_93 = {_res_hit_msbsLess_T_92[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbsLess_T_94 = ~_res_hit_msbsLess_T_93; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_hit_msbsLess_T_95 = _res_hit_msbsLess_T_94[31:3]; // @[PMP.scala:60:27, :80:52]
wire res_hit_msbsLess_15 = _res_hit_msbsLess_T_90 < _res_hit_msbsLess_T_95; // @[PMP.scala:80:{25,39,52}]
wire [31:0] _res_hit_msbsEqual_T_107 = ~_res_hit_msbsEqual_T_106; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_msbsEqual_T_108 = {_res_hit_msbsEqual_T_107[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbsEqual_T_109 = ~_res_hit_msbsEqual_T_108; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_hit_msbsEqual_T_110 = _res_hit_msbsEqual_T_109[31:3]; // @[PMP.scala:60:27, :81:54]
wire [28:0] _res_hit_msbsEqual_T_111 = _res_hit_msbsEqual_T_105 ^ _res_hit_msbsEqual_T_110; // @[PMP.scala:81:{27,41,54}]
wire res_hit_msbsEqual_15 = _res_hit_msbsEqual_T_111 == 29'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67]
wire [2:0] _res_hit_lsbsLess_T_106 = _res_hit_lsbsLess_T_105; // @[PMP.scala:82:{25,42}]
wire [31:0] _res_hit_lsbsLess_T_108 = ~_res_hit_lsbsLess_T_107; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_lsbsLess_T_109 = {_res_hit_lsbsLess_T_108[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_lsbsLess_T_110 = ~_res_hit_lsbsLess_T_109; // @[PMP.scala:60:{27,48}]
wire [2:0] _res_hit_lsbsLess_T_111 = _res_hit_lsbsLess_T_110[2:0]; // @[PMP.scala:60:27, :82:64]
wire res_hit_lsbsLess_15 = _res_hit_lsbsLess_T_106 < _res_hit_lsbsLess_T_111; // @[PMP.scala:82:{42,53,64}]
wire _res_hit_T_100 = res_hit_msbsEqual_15 & res_hit_lsbsLess_15; // @[PMP.scala:81:69, :82:53, :83:30]
wire _res_hit_T_101 = res_hit_msbsLess_15 | _res_hit_T_100; // @[PMP.scala:80:39, :83:{16,30}]
wire _res_hit_T_102 = _res_hit_T_101; // @[PMP.scala:83:16, :94:48]
wire _res_hit_T_103 = _res_hit_T_93 & _res_hit_T_102; // @[PMP.scala:46:26, :94:48, :132:61]
wire res_hit_7 = _res_hit_T_91 ? _res_hit_T_92 : _res_hit_T_103; // @[PMP.scala:45:20, :71:16, :132:{8,61}]
wire _res_ignore_T_7 = ~io_pmp_0_cfg_l_0; // @[PMP.scala:143:7, :164:29]
wire res_ignore_7 = default_0 & _res_ignore_T_7; // @[PMP.scala:156:56, :164:{26,29}]
wire [2:0] _res_aligned_lsbMask_T_15 = _res_aligned_lsbMask_T_14[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] res_aligned_lsbMask_7 = ~_res_aligned_lsbMask_T_15; // @[package.scala:243:{46,76}]
wire [28:0] _res_aligned_straddlesLowerBound_T_125 = _res_aligned_straddlesLowerBound_T_119; // @[PMP.scala:123:{35,49}]
wire _res_aligned_straddlesLowerBound_T_126 = _res_aligned_straddlesLowerBound_T_125 == 29'h0; // @[PMP.scala:80:52, :81:54, :123:{49,67,82}]
wire [2:0] _res_aligned_straddlesLowerBound_T_133 = ~_res_aligned_straddlesLowerBound_T_132; // @[PMP.scala:123:{127,129}]
wire [31:0] _res_aligned_straddlesUpperBound_T_121 = ~_res_aligned_straddlesUpperBound_T_120; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_aligned_straddlesUpperBound_T_122 = {_res_aligned_straddlesUpperBound_T_121[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_aligned_straddlesUpperBound_T_123 = ~_res_aligned_straddlesUpperBound_T_122; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_aligned_straddlesUpperBound_T_124 = _res_aligned_straddlesUpperBound_T_123[31:3]; // @[PMP.scala:60:27, :124:62]
wire [28:0] _res_aligned_straddlesUpperBound_T_125 = _res_aligned_straddlesUpperBound_T_119 ^ _res_aligned_straddlesUpperBound_T_124; // @[PMP.scala:124:{35,49,62}]
wire _res_aligned_straddlesUpperBound_T_126 = _res_aligned_straddlesUpperBound_T_125 == 29'h0; // @[PMP.scala:80:52, :81:54, :123:67, :124:{49,77}]
wire [31:0] _res_aligned_straddlesUpperBound_T_128 = ~_res_aligned_straddlesUpperBound_T_127; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_aligned_straddlesUpperBound_T_129 = {_res_aligned_straddlesUpperBound_T_128[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_aligned_straddlesUpperBound_T_130 = ~_res_aligned_straddlesUpperBound_T_129; // @[PMP.scala:60:{27,48}]
wire [2:0] _res_aligned_straddlesUpperBound_T_131 = _res_aligned_straddlesUpperBound_T_130[2:0]; // @[PMP.scala:60:27, :124:98]
wire [2:0] _res_aligned_straddlesUpperBound_T_133 = _res_aligned_straddlesUpperBound_T_132 | res_aligned_lsbMask_7; // @[package.scala:243:46]
wire [2:0] _res_aligned_straddlesUpperBound_T_134 = _res_aligned_straddlesUpperBound_T_131 & _res_aligned_straddlesUpperBound_T_133; // @[PMP.scala:124:{98,115,136}]
wire _res_aligned_straddlesUpperBound_T_135 = |_res_aligned_straddlesUpperBound_T_134; // @[PMP.scala:124:{115,148}]
wire res_aligned_straddlesUpperBound_7 = _res_aligned_straddlesUpperBound_T_126 & _res_aligned_straddlesUpperBound_T_135; // @[PMP.scala:124:{77,85,148}]
wire _res_aligned_rangeAligned_T_7 = res_aligned_straddlesUpperBound_7; // @[PMP.scala:124:85, :125:46]
wire res_aligned_rangeAligned_7 = ~_res_aligned_rangeAligned_T_7; // @[PMP.scala:125:{24,46}]
wire [2:0] _res_aligned_pow2Aligned_T_22 = ~_res_aligned_pow2Aligned_T_21; // @[PMP.scala:126:{34,39}]
wire [2:0] _res_aligned_pow2Aligned_T_23 = res_aligned_lsbMask_7 & _res_aligned_pow2Aligned_T_22; // @[package.scala:243:46]
wire res_aligned_pow2Aligned_7 = _res_aligned_pow2Aligned_T_23 == 3'h0; // @[PMP.scala:82:64, :123:{108,125}, :126:{32,57}]
wire res_aligned_7 = _res_aligned_T_7 ? res_aligned_pow2Aligned_7 : res_aligned_rangeAligned_7; // @[PMP.scala:45:20, :125:24, :126:57, :127:8]
wire _res_T_315 = io_pmp_0_cfg_a_0 == 2'h0; // @[PMP.scala:143:7, :168:32]
wire _GEN_36 = io_pmp_0_cfg_a_0 == 2'h1; // @[PMP.scala:143:7, :168:32]
wire _res_T_316; // @[PMP.scala:168:32]
assign _res_T_316 = _GEN_36; // @[PMP.scala:168:32]
wire _res_T_335; // @[PMP.scala:177:61]
assign _res_T_335 = _GEN_36; // @[PMP.scala:168:32, :177:61]
wire _res_T_339; // @[PMP.scala:178:63]
assign _res_T_339 = _GEN_36; // @[PMP.scala:168:32, :178:63]
wire _GEN_37 = io_pmp_0_cfg_a_0 == 2'h2; // @[PMP.scala:143:7, :168:32]
wire _res_T_317; // @[PMP.scala:168:32]
assign _res_T_317 = _GEN_37; // @[PMP.scala:168:32]
wire _res_T_344; // @[PMP.scala:177:61]
assign _res_T_344 = _GEN_37; // @[PMP.scala:168:32, :177:61]
wire _res_T_348; // @[PMP.scala:178:63]
assign _res_T_348 = _GEN_37; // @[PMP.scala:168:32, :178:63]
wire _res_T_318 = &io_pmp_0_cfg_a_0; // @[PMP.scala:143:7, :168:32]
wire [1:0] _GEN_38 = {io_pmp_0_cfg_x_0, io_pmp_0_cfg_w_0}; // @[PMP.scala:143:7, :174:26]
wire [1:0] res_hi_42; // @[PMP.scala:174:26]
assign res_hi_42 = _GEN_38; // @[PMP.scala:174:26]
wire [1:0] res_hi_43; // @[PMP.scala:174:26]
assign res_hi_43 = _GEN_38; // @[PMP.scala:174:26]
wire [1:0] res_hi_44; // @[PMP.scala:174:26]
assign res_hi_44 = _GEN_38; // @[PMP.scala:174:26]
wire [1:0] res_hi_45; // @[PMP.scala:174:26]
assign res_hi_45 = _GEN_38; // @[PMP.scala:174:26]
wire [1:0] res_hi_46; // @[PMP.scala:174:26]
assign res_hi_46 = _GEN_38; // @[PMP.scala:174:26]
wire [1:0] res_hi_47; // @[PMP.scala:174:26]
assign res_hi_47 = _GEN_38; // @[PMP.scala:174:26]
wire [2:0] _res_T_320 = {res_hi_42, io_pmp_0_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_321 = _res_T_320 == 3'h0; // @[PMP.scala:82:64, :123:{108,125}, :174:{26,60}]
wire [2:0] _res_T_322 = {res_hi_43, io_pmp_0_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_323 = _res_T_322 == 3'h1; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_324 = {res_hi_44, io_pmp_0_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_325 = _res_T_324 == 3'h3; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_326 = {res_hi_45, io_pmp_0_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_327 = _res_T_326 == 3'h4; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_328 = {res_hi_46, io_pmp_0_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_329 = _res_T_328 == 3'h5; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_330 = {res_hi_47, io_pmp_0_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_331 = &_res_T_330; // @[PMP.scala:174:{26,60}]
wire _res_T_332 = ~res_ignore_7; // @[PMP.scala:164:26, :177:22]
wire _res_T_333 = _res_T_332 & res_hit_7; // @[PMP.scala:132:8, :177:{22,30}]
wire _res_T_334 = _res_T_333 & res_aligned_7; // @[PMP.scala:127:8, :177:{30,37}]
wire _res_T_336 = _res_T_334 & _res_T_335; // @[PMP.scala:177:{37,48,61}]
wire _GEN_39 = io_pmp_0_cfg_l_0 & res_hit_7; // @[PMP.scala:132:8, :143:7, :178:32]
wire _res_T_337; // @[PMP.scala:178:32]
assign _res_T_337 = _GEN_39; // @[PMP.scala:178:32]
wire _res_T_346; // @[PMP.scala:178:32]
assign _res_T_346 = _GEN_39; // @[PMP.scala:178:32]
wire _res_T_355; // @[PMP.scala:178:32]
assign _res_T_355 = _GEN_39; // @[PMP.scala:178:32]
wire _res_T_338 = _res_T_337 & res_aligned_7; // @[PMP.scala:127:8, :178:{32,39}]
wire _res_T_340 = _res_T_338 & _res_T_339; // @[PMP.scala:178:{39,50,63}]
wire _res_T_341 = ~res_ignore_7; // @[PMP.scala:164:26, :177:22]
wire _res_T_342 = _res_T_341 & res_hit_7; // @[PMP.scala:132:8, :177:{22,30}]
wire _res_T_343 = _res_T_342 & res_aligned_7; // @[PMP.scala:127:8, :177:{30,37}]
wire _res_T_345 = _res_T_343 & _res_T_344; // @[PMP.scala:177:{37,48,61}]
wire _res_T_347 = _res_T_346 & res_aligned_7; // @[PMP.scala:127:8, :178:{32,39}]
wire _res_T_349 = _res_T_347 & _res_T_348; // @[PMP.scala:178:{39,50,63}]
wire _res_T_350 = ~res_ignore_7; // @[PMP.scala:164:26, :177:22]
wire _res_T_351 = _res_T_350 & res_hit_7; // @[PMP.scala:132:8, :177:{22,30}]
wire _res_T_352 = _res_T_351 & res_aligned_7; // @[PMP.scala:127:8, :177:{30,37}]
wire _res_T_353 = &io_pmp_0_cfg_a_0; // @[PMP.scala:143:7, :168:32, :177:61]
wire _res_T_354 = _res_T_352 & _res_T_353; // @[PMP.scala:177:{37,48,61}]
wire _res_T_356 = _res_T_355 & res_aligned_7; // @[PMP.scala:127:8, :178:{32,39}]
wire _res_T_357 = &io_pmp_0_cfg_a_0; // @[PMP.scala:143:7, :168:32, :178:63]
wire _res_T_358 = _res_T_356 & _res_T_357; // @[PMP.scala:178:{39,50,63}]
wire _res_cur_cfg_x_T_15; // @[PMP.scala:184:26]
wire _res_cur_cfg_w_T_15; // @[PMP.scala:183:26]
wire _res_cur_cfg_r_T_15; // @[PMP.scala:182:26]
wire res_cur_7_cfg_x; // @[PMP.scala:181:23]
wire res_cur_7_cfg_w; // @[PMP.scala:181:23]
wire res_cur_7_cfg_r; // @[PMP.scala:181:23]
wire _res_cur_cfg_r_T_14 = io_pmp_0_cfg_r_0 | res_ignore_7; // @[PMP.scala:143:7, :164:26, :182:40]
assign _res_cur_cfg_r_T_15 = res_aligned_7 & _res_cur_cfg_r_T_14; // @[PMP.scala:127:8, :182:{26,40}]
assign res_cur_7_cfg_r = _res_cur_cfg_r_T_15; // @[PMP.scala:181:23, :182:26]
wire _res_cur_cfg_w_T_14 = io_pmp_0_cfg_w_0 | res_ignore_7; // @[PMP.scala:143:7, :164:26, :183:40]
assign _res_cur_cfg_w_T_15 = res_aligned_7 & _res_cur_cfg_w_T_14; // @[PMP.scala:127:8, :183:{26,40}]
assign res_cur_7_cfg_w = _res_cur_cfg_w_T_15; // @[PMP.scala:181:23, :183:26]
wire _res_cur_cfg_x_T_14 = io_pmp_0_cfg_x_0 | res_ignore_7; // @[PMP.scala:143:7, :164:26, :184:40]
assign _res_cur_cfg_x_T_15 = res_aligned_7 & _res_cur_cfg_x_T_14; // @[PMP.scala:127:8, :184:{26,40}]
assign res_cur_7_cfg_x = _res_cur_cfg_x_T_15; // @[PMP.scala:181:23, :184:26]
wire res_cfg_l = res_hit_7 ? res_cur_7_cfg_l : _res_T_314_cfg_l; // @[PMP.scala:132:8, :181:23, :185:8]
wire [1:0] res_cfg_a = res_hit_7 ? res_cur_7_cfg_a : _res_T_314_cfg_a; // @[PMP.scala:132:8, :181:23, :185:8]
assign res_cfg_x = res_hit_7 ? res_cur_7_cfg_x : _res_T_314_cfg_x; // @[PMP.scala:132:8, :181:23, :185:8]
assign res_cfg_w = res_hit_7 ? res_cur_7_cfg_w : _res_T_314_cfg_w; // @[PMP.scala:132:8, :181:23, :185:8]
assign res_cfg_r = res_hit_7 ? res_cur_7_cfg_r : _res_T_314_cfg_r; // @[PMP.scala:132:8, :181:23, :185:8]
wire [29:0] res_addr = res_hit_7 ? res_cur_7_addr : _res_T_314_addr; // @[PMP.scala:132:8, :181:23, :185:8]
wire [31:0] res_mask = res_hit_7 ? res_cur_7_mask : _res_T_314_mask; // @[PMP.scala:132:8, :181:23, :185:8]
assign io_x_0 = res_cfg_x; // @[PMP.scala:143:7, :185:8]
assign io_w_0 = res_cfg_w; // @[PMP.scala:143:7, :185:8]
assign io_r_0 = res_cfg_r; // @[PMP.scala:143:7, :185:8]
assign io_r = io_r_0; // @[PMP.scala:143:7]
assign io_w = io_w_0; // @[PMP.scala:143:7]
assign io_x = io_x_0; // @[PMP.scala:143:7]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File ShiftReg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
// Similar to the Chisel ShiftRegister but allows the user to suggest a
// name to the registers that get instantiated, and
// to provide a reset value.
object ShiftRegInit {
def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T =
(0 until n).foldRight(in) {
case (i, next) => {
val r = RegNext(next, init)
name.foreach { na => r.suggestName(s"${na}_${i}") }
r
}
}
}
/** These wrap behavioral
* shift registers into specific modules to allow for
* backend flows to replace or constrain
* them properly when used for CDC synchronization,
* rather than buffering.
*
* The different types vary in their reset behavior:
* AsyncResetShiftReg -- Asynchronously reset register array
* A W(width) x D(depth) sized array is constructed from D instantiations of a
* W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg,
* but only used for timing applications
*/
abstract class AbstractPipelineReg(w: Int = 1) extends Module {
val io = IO(new Bundle {
val d = Input(UInt(w.W))
val q = Output(UInt(w.W))
}
)
}
object AbstractPipelineReg {
def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = {
val chain = Module(gen)
name.foreach{ chain.suggestName(_) }
chain.io.d := in.asUInt
chain.io.q.asTypeOf(in)
}
}
class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) {
require(depth > 0, "Depth must be greater than 0.")
override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}"
val chain = List.tabulate(depth) { i =>
Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}")
}
chain.last.io.d := io.d
chain.last.io.en := true.B
(chain.init zip chain.tail).foreach { case (sink, source) =>
sink.io.d := source.io.q
sink.io.en := true.B
}
io.q := chain.head.io.q
}
object AsyncResetShiftReg {
def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T =
AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name)
def apply [T <: Data](in: T, depth: Int, name: Option[String]): T =
apply(in, depth, 0, name)
def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T =
apply(in, depth, init.litValue.toInt, name)
def apply [T <: Data](in: T, depth: Int, init: T): T =
apply (in, depth, init.litValue.toInt, None)
}
File AsyncQueue.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util._
case class AsyncQueueParams(
depth: Int = 8,
sync: Int = 3,
safe: Boolean = true,
// If safe is true, then effort is made to resynchronize the crossing indices when either side is reset.
// This makes it safe/possible to reset one side of the crossing (but not the other) when the queue is empty.
narrow: Boolean = false)
// If narrow is true then the read mux is moved to the source side of the crossing.
// This reduces the number of level shifters in the case where the clock crossing is also a voltage crossing,
// at the expense of a combinational path from the sink to the source and back to the sink.
{
require (depth > 0 && isPow2(depth))
require (sync >= 2)
val bits = log2Ceil(depth)
val wires = if (narrow) 1 else depth
}
object AsyncQueueParams {
// When there is only one entry, we don't need narrow.
def singleton(sync: Int = 3, safe: Boolean = true) = AsyncQueueParams(1, sync, safe, false)
}
class AsyncBundleSafety extends Bundle {
val ridx_valid = Input (Bool())
val widx_valid = Output(Bool())
val source_reset_n = Output(Bool())
val sink_reset_n = Input (Bool())
}
class AsyncBundle[T <: Data](private val gen: T, val params: AsyncQueueParams = AsyncQueueParams()) extends Bundle {
// Data-path synchronization
val mem = Output(Vec(params.wires, gen))
val ridx = Input (UInt((params.bits+1).W))
val widx = Output(UInt((params.bits+1).W))
val index = params.narrow.option(Input(UInt(params.bits.W)))
// Signals used to self-stabilize a safe AsyncQueue
val safe = params.safe.option(new AsyncBundleSafety)
}
object GrayCounter {
def apply(bits: Int, increment: Bool = true.B, clear: Bool = false.B, name: String = "binary"): UInt = {
val incremented = Wire(UInt(bits.W))
val binary = RegNext(next=incremented, init=0.U).suggestName(name)
incremented := Mux(clear, 0.U, binary + increment.asUInt)
incremented ^ (incremented >> 1)
}
}
class AsyncValidSync(sync: Int, desc: String) extends RawModule {
val io = IO(new Bundle {
val in = Input(Bool())
val out = Output(Bool())
})
val clock = IO(Input(Clock()))
val reset = IO(Input(AsyncReset()))
withClockAndReset(clock, reset){
io.out := AsyncResetSynchronizerShiftReg(io.in, sync, Some(desc))
}
}
class AsyncQueueSource[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module {
override def desiredName = s"AsyncQueueSource_${gen.typeName}"
val io = IO(new Bundle {
// These come from the source domain
val enq = Flipped(Decoupled(gen))
// These cross to the sink clock domain
val async = new AsyncBundle(gen, params)
})
val bits = params.bits
val sink_ready = WireInit(true.B)
val mem = Reg(Vec(params.depth, gen)) // This does NOT need to be reset at all.
val widx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.enq.fire, !sink_ready, "widx_bin"))
val ridx = AsyncResetSynchronizerShiftReg(io.async.ridx, params.sync, Some("ridx_gray"))
val ready = sink_ready && widx =/= (ridx ^ (params.depth | params.depth >> 1).U)
val index = if (bits == 0) 0.U else io.async.widx(bits-1, 0) ^ (io.async.widx(bits, bits) << (bits-1))
when (io.enq.fire) { mem(index) := io.enq.bits }
val ready_reg = withReset(reset.asAsyncReset)(RegNext(next=ready, init=false.B).suggestName("ready_reg"))
io.enq.ready := ready_reg && sink_ready
val widx_reg = withReset(reset.asAsyncReset)(RegNext(next=widx, init=0.U).suggestName("widx_gray"))
io.async.widx := widx_reg
io.async.index match {
case Some(index) => io.async.mem(0) := mem(index)
case None => io.async.mem := mem
}
io.async.safe.foreach { sio =>
val source_valid_0 = Module(new AsyncValidSync(params.sync, "source_valid_0"))
val source_valid_1 = Module(new AsyncValidSync(params.sync, "source_valid_1"))
val sink_extend = Module(new AsyncValidSync(params.sync, "sink_extend"))
val sink_valid = Module(new AsyncValidSync(params.sync, "sink_valid"))
source_valid_0.reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset
source_valid_1.reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset
sink_extend .reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset
sink_valid .reset := reset.asAsyncReset
source_valid_0.clock := clock
source_valid_1.clock := clock
sink_extend .clock := clock
sink_valid .clock := clock
source_valid_0.io.in := true.B
source_valid_1.io.in := source_valid_0.io.out
sio.widx_valid := source_valid_1.io.out
sink_extend.io.in := sio.ridx_valid
sink_valid.io.in := sink_extend.io.out
sink_ready := sink_valid.io.out
sio.source_reset_n := !reset.asBool
// Assert that if there is stuff in the queue, then reset cannot happen
// Impossible to write because dequeue can occur on the receiving side,
// then reset allowed to happen, but write side cannot know that dequeue
// occurred.
// TODO: write some sort of sanity check assertion for users
// that denote don't reset when there is activity
// assert (!(reset || !sio.sink_reset_n) || !io.enq.valid, "Enqueue while sink is reset and AsyncQueueSource is unprotected")
// assert (!reset_rise || prev_idx_match.asBool, "Sink reset while AsyncQueueSource not empty")
}
}
class AsyncQueueSink[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module {
override def desiredName = s"AsyncQueueSink_${gen.typeName}"
val io = IO(new Bundle {
// These come from the sink domain
val deq = Decoupled(gen)
// These cross to the source clock domain
val async = Flipped(new AsyncBundle(gen, params))
})
val bits = params.bits
val source_ready = WireInit(true.B)
val ridx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.deq.fire, !source_ready, "ridx_bin"))
val widx = AsyncResetSynchronizerShiftReg(io.async.widx, params.sync, Some("widx_gray"))
val valid = source_ready && ridx =/= widx
// The mux is safe because timing analysis ensures ridx has reached the register
// On an ASIC, changes to the unread location cannot affect the selected value
// On an FPGA, only one input changes at a time => mem updates don't cause glitches
// The register only latches when the selected valued is not being written
val index = if (bits == 0) 0.U else ridx(bits-1, 0) ^ (ridx(bits, bits) << (bits-1))
io.async.index.foreach { _ := index }
// This register does not NEED to be reset, as its contents will not
// be considered unless the asynchronously reset deq valid register is set.
// It is possible that bits latches when the source domain is reset / has power cut
// This is safe, because isolation gates brought mem low before the zeroed widx reached us
val deq_bits_nxt = io.async.mem(if (params.narrow) 0.U else index)
io.deq.bits := ClockCrossingReg(deq_bits_nxt, en = valid, doInit = false, name = Some("deq_bits_reg"))
val valid_reg = withReset(reset.asAsyncReset)(RegNext(next=valid, init=false.B).suggestName("valid_reg"))
io.deq.valid := valid_reg && source_ready
val ridx_reg = withReset(reset.asAsyncReset)(RegNext(next=ridx, init=0.U).suggestName("ridx_gray"))
io.async.ridx := ridx_reg
io.async.safe.foreach { sio =>
val sink_valid_0 = Module(new AsyncValidSync(params.sync, "sink_valid_0"))
val sink_valid_1 = Module(new AsyncValidSync(params.sync, "sink_valid_1"))
val source_extend = Module(new AsyncValidSync(params.sync, "source_extend"))
val source_valid = Module(new AsyncValidSync(params.sync, "source_valid"))
sink_valid_0 .reset := (reset.asBool || !sio.source_reset_n).asAsyncReset
sink_valid_1 .reset := (reset.asBool || !sio.source_reset_n).asAsyncReset
source_extend.reset := (reset.asBool || !sio.source_reset_n).asAsyncReset
source_valid .reset := reset.asAsyncReset
sink_valid_0 .clock := clock
sink_valid_1 .clock := clock
source_extend.clock := clock
source_valid .clock := clock
sink_valid_0.io.in := true.B
sink_valid_1.io.in := sink_valid_0.io.out
sio.ridx_valid := sink_valid_1.io.out
source_extend.io.in := sio.widx_valid
source_valid.io.in := source_extend.io.out
source_ready := source_valid.io.out
sio.sink_reset_n := !reset.asBool
// TODO: write some sort of sanity check assertion for users
// that denote don't reset when there is activity
//
// val reset_and_extend = !source_ready || !sio.source_reset_n || reset.asBool
// val reset_and_extend_prev = RegNext(reset_and_extend, true.B)
// val reset_rise = !reset_and_extend_prev && reset_and_extend
// val prev_idx_match = AsyncResetReg(updateData=(io.async.widx===io.async.ridx), resetData=0)
// assert (!reset_rise || prev_idx_match.asBool, "Source reset while AsyncQueueSink not empty")
}
}
object FromAsyncBundle
{
// Sometimes it makes sense for the sink to have different sync than the source
def apply[T <: Data](x: AsyncBundle[T]): DecoupledIO[T] = apply(x, x.params.sync)
def apply[T <: Data](x: AsyncBundle[T], sync: Int): DecoupledIO[T] = {
val sink = Module(new AsyncQueueSink(chiselTypeOf(x.mem(0)), x.params.copy(sync = sync)))
sink.io.async <> x
sink.io.deq
}
}
object ToAsyncBundle
{
def apply[T <: Data](x: ReadyValidIO[T], params: AsyncQueueParams = AsyncQueueParams()): AsyncBundle[T] = {
val source = Module(new AsyncQueueSource(chiselTypeOf(x.bits), params))
source.io.enq <> x
source.io.async
}
}
class AsyncQueue[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Crossing[T] {
val io = IO(new CrossingIO(gen))
val source = withClockAndReset(io.enq_clock, io.enq_reset) { Module(new AsyncQueueSource(gen, params)) }
val sink = withClockAndReset(io.deq_clock, io.deq_reset) { Module(new AsyncQueueSink (gen, params)) }
source.io.enq <> io.enq
io.deq <> sink.io.deq
sink.io.async <> source.io.async
}
| module AsyncValidSync_147( // @[AsyncQueue.scala:58:7]
input io_in, // @[AsyncQueue.scala:59:14]
output io_out, // @[AsyncQueue.scala:59:14]
input clock, // @[AsyncQueue.scala:63:17]
input reset // @[AsyncQueue.scala:64:17]
);
wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7]
wire _io_out_WIRE; // @[ShiftReg.scala:48:24]
wire io_out_0; // @[AsyncQueue.scala:58:7]
assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24]
AsyncResetSynchronizerShiftReg_w1_d3_i0_168 io_out_sink_valid ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (reset),
.io_d (io_in_0), // @[AsyncQueue.scala:58:7]
.io_q (_io_out_WIRE)
); // @[ShiftReg.scala:45:23]
assign io_out = io_out_0; // @[AsyncQueue.scala:58:7]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File UnsafeAXI4ToTL.scala:
package ara
import chisel3._
import chisel3.util._
import freechips.rocketchip.amba._
import freechips.rocketchip.amba.axi4._
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.tilelink._
import freechips.rocketchip.util._
class ReorderData(val dataWidth: Int, val respWidth: Int, val userFields: Seq[BundleFieldBase]) extends Bundle {
val data = UInt(dataWidth.W)
val resp = UInt(respWidth.W)
val last = Bool()
val user = BundleMap(userFields)
}
/** Parameters for [[BaseReservableListBuffer]] and all child classes.
*
* @param numEntries Total number of elements that can be stored in the 'data' RAM
* @param numLists Maximum number of linked lists
* @param numBeats Maximum number of beats per entry
*/
case class ReservableListBufferParameters(numEntries: Int, numLists: Int, numBeats: Int) {
// Avoid zero-width wires when we call 'log2Ceil'
val entryBits = if (numEntries == 1) 1 else log2Ceil(numEntries)
val listBits = if (numLists == 1) 1 else log2Ceil(numLists)
val beatBits = if (numBeats == 1) 1 else log2Ceil(numBeats)
}
case class UnsafeAXI4ToTLNode(numTlTxns: Int, wcorrupt: Boolean)(implicit valName: ValName)
extends MixedAdapterNode(AXI4Imp, TLImp)(
dFn = { case mp =>
TLMasterPortParameters.v2(
masters = mp.masters.zipWithIndex.map { case (m, i) =>
// Support 'numTlTxns' read requests and 'numTlTxns' write requests at once.
val numSourceIds = numTlTxns * 2
TLMasterParameters.v2(
name = m.name,
sourceId = IdRange(i * numSourceIds, (i + 1) * numSourceIds),
nodePath = m.nodePath
)
},
echoFields = mp.echoFields,
requestFields = AMBAProtField() +: mp.requestFields,
responseKeys = mp.responseKeys
)
},
uFn = { mp =>
AXI4SlavePortParameters(
slaves = mp.managers.map { m =>
val maxXfer = TransferSizes(1, mp.beatBytes * (1 << AXI4Parameters.lenBits))
AXI4SlaveParameters(
address = m.address,
resources = m.resources,
regionType = m.regionType,
executable = m.executable,
nodePath = m.nodePath,
supportsWrite = m.supportsPutPartial.intersect(maxXfer),
supportsRead = m.supportsGet.intersect(maxXfer),
interleavedId = Some(0) // TL2 never interleaves D beats
)
},
beatBytes = mp.beatBytes,
minLatency = mp.minLatency,
responseFields = mp.responseFields,
requestKeys = (if (wcorrupt) Seq(AMBACorrupt) else Seq()) ++ mp.requestKeys.filter(_ != AMBAProt)
)
}
)
class UnsafeAXI4ToTL(numTlTxns: Int, wcorrupt: Boolean)(implicit p: Parameters) extends LazyModule {
require(numTlTxns >= 1)
require(isPow2(numTlTxns), s"Number of TileLink transactions ($numTlTxns) must be a power of 2")
val node = UnsafeAXI4ToTLNode(numTlTxns, wcorrupt)
lazy val module = new LazyModuleImp(this) {
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
edgeIn.master.masters.foreach { m =>
require(m.aligned, "AXI4ToTL requires aligned requests")
}
val numIds = edgeIn.master.endId
val beatBytes = edgeOut.slave.beatBytes
val maxTransfer = edgeOut.slave.maxTransfer
val maxBeats = maxTransfer / beatBytes
// Look for an Error device to redirect bad requests
val errorDevs = edgeOut.slave.managers.filter(_.nodePath.last.lazyModule.className == "TLError")
require(!errorDevs.isEmpty, "There is no TLError reachable from AXI4ToTL. One must be instantiated.")
val errorDev = errorDevs.maxBy(_.maxTransfer)
val errorDevAddr = errorDev.address.head.base
require(
errorDev.supportsPutPartial.contains(maxTransfer),
s"Error device supports ${errorDev.supportsPutPartial} PutPartial but must support $maxTransfer"
)
require(
errorDev.supportsGet.contains(maxTransfer),
s"Error device supports ${errorDev.supportsGet} Get but must support $maxTransfer"
)
// All of the read-response reordering logic.
val listBufData = new ReorderData(beatBytes * 8, edgeIn.bundle.respBits, out.d.bits.user.fields)
val listBufParams = ReservableListBufferParameters(numTlTxns, numIds, maxBeats)
val listBuffer = if (numTlTxns > 1) {
Module(new ReservableListBuffer(listBufData, listBufParams))
} else {
Module(new PassthroughListBuffer(listBufData, listBufParams))
}
// To differentiate between read and write transaction IDs, we will set the MSB of the TileLink 'source' field to
// 0 for read requests and 1 for write requests.
val isReadSourceBit = 0.U(1.W)
val isWriteSourceBit = 1.U(1.W)
/* Read request logic */
val rOut = Wire(Decoupled(new TLBundleA(edgeOut.bundle)))
val rBytes1 = in.ar.bits.bytes1()
val rSize = OH1ToUInt(rBytes1)
val rOk = edgeOut.slave.supportsGetSafe(in.ar.bits.addr, rSize)
val rId = if (numTlTxns > 1) {
Cat(isReadSourceBit, listBuffer.ioReservedIndex)
} else {
isReadSourceBit
}
val rAddr = Mux(rOk, in.ar.bits.addr, errorDevAddr.U | in.ar.bits.addr(log2Ceil(beatBytes) - 1, 0))
// Indicates if there are still valid TileLink source IDs left to use.
val canIssueR = listBuffer.ioReserve.ready
listBuffer.ioReserve.bits := in.ar.bits.id
listBuffer.ioReserve.valid := in.ar.valid && rOut.ready
in.ar.ready := rOut.ready && canIssueR
rOut.valid := in.ar.valid && canIssueR
rOut.bits :<= edgeOut.Get(rId, rAddr, rSize)._2
rOut.bits.user :<= in.ar.bits.user
rOut.bits.user.lift(AMBAProt).foreach { rProt =>
rProt.privileged := in.ar.bits.prot(0)
rProt.secure := !in.ar.bits.prot(1)
rProt.fetch := in.ar.bits.prot(2)
rProt.bufferable := in.ar.bits.cache(0)
rProt.modifiable := in.ar.bits.cache(1)
rProt.readalloc := in.ar.bits.cache(2)
rProt.writealloc := in.ar.bits.cache(3)
}
/* Write request logic */
// Strip off the MSB, which identifies the transaction as read vs write.
val strippedResponseSourceId = if (numTlTxns > 1) {
out.d.bits.source((out.d.bits.source).getWidth - 2, 0)
} else {
// When there's only 1 TileLink transaction allowed for read/write, then this field is always 0.
0.U(1.W)
}
// Track when a write request burst is in progress.
val writeBurstBusy = RegInit(false.B)
when(in.w.fire) {
writeBurstBusy := !in.w.bits.last
}
val usedWriteIds = RegInit(0.U(numTlTxns.W))
val canIssueW = !usedWriteIds.andR
val usedWriteIdsSet = WireDefault(0.U(numTlTxns.W))
val usedWriteIdsClr = WireDefault(0.U(numTlTxns.W))
usedWriteIds := (usedWriteIds & ~usedWriteIdsClr) | usedWriteIdsSet
// Since write responses can show up in the middle of a write burst, we need to ensure the write burst ID doesn't
// change mid-burst.
val freeWriteIdOHRaw = Wire(UInt(numTlTxns.W))
val freeWriteIdOH = freeWriteIdOHRaw holdUnless !writeBurstBusy
val freeWriteIdIndex = OHToUInt(freeWriteIdOH)
freeWriteIdOHRaw := ~(leftOR(~usedWriteIds) << 1) & ~usedWriteIds
val wOut = Wire(Decoupled(new TLBundleA(edgeOut.bundle)))
val wBytes1 = in.aw.bits.bytes1()
val wSize = OH1ToUInt(wBytes1)
val wOk = edgeOut.slave.supportsPutPartialSafe(in.aw.bits.addr, wSize)
val wId = if (numTlTxns > 1) {
Cat(isWriteSourceBit, freeWriteIdIndex)
} else {
isWriteSourceBit
}
val wAddr = Mux(wOk, in.aw.bits.addr, errorDevAddr.U | in.aw.bits.addr(log2Ceil(beatBytes) - 1, 0))
// Here, we're taking advantage of the Irrevocable behavior of AXI4 (once 'valid' is asserted it must remain
// asserted until the handshake occurs). We will only accept W-channel beats when we have a valid AW beat, but
// the AW-channel beat won't fire until the final W-channel beat fires. So, we have stable address/size/strb
// bits during a W-channel burst.
in.aw.ready := wOut.ready && in.w.valid && in.w.bits.last && canIssueW
in.w.ready := wOut.ready && in.aw.valid && canIssueW
wOut.valid := in.aw.valid && in.w.valid && canIssueW
wOut.bits :<= edgeOut.Put(wId, wAddr, wSize, in.w.bits.data, in.w.bits.strb)._2
in.w.bits.user.lift(AMBACorrupt).foreach { wOut.bits.corrupt := _ }
wOut.bits.user :<= in.aw.bits.user
wOut.bits.user.lift(AMBAProt).foreach { wProt =>
wProt.privileged := in.aw.bits.prot(0)
wProt.secure := !in.aw.bits.prot(1)
wProt.fetch := in.aw.bits.prot(2)
wProt.bufferable := in.aw.bits.cache(0)
wProt.modifiable := in.aw.bits.cache(1)
wProt.readalloc := in.aw.bits.cache(2)
wProt.writealloc := in.aw.bits.cache(3)
}
// Merge the AXI4 read/write requests into the TL-A channel.
TLArbiter(TLArbiter.roundRobin)(out.a, (0.U, rOut), (in.aw.bits.len, wOut))
/* Read/write response logic */
val okB = Wire(Irrevocable(new AXI4BundleB(edgeIn.bundle)))
val okR = Wire(Irrevocable(new AXI4BundleR(edgeIn.bundle)))
val dResp = Mux(out.d.bits.denied || out.d.bits.corrupt, AXI4Parameters.RESP_SLVERR, AXI4Parameters.RESP_OKAY)
val dHasData = edgeOut.hasData(out.d.bits)
val (_dFirst, dLast, _dDone, dCount) = edgeOut.count(out.d)
val dNumBeats1 = edgeOut.numBeats1(out.d.bits)
// Handle cases where writeack arrives before write is done
val writeEarlyAck = (UIntToOH(strippedResponseSourceId) & usedWriteIds) === 0.U
out.d.ready := Mux(dHasData, listBuffer.ioResponse.ready, okB.ready && !writeEarlyAck)
listBuffer.ioDataOut.ready := okR.ready
okR.valid := listBuffer.ioDataOut.valid
okB.valid := out.d.valid && !dHasData && !writeEarlyAck
listBuffer.ioResponse.valid := out.d.valid && dHasData
listBuffer.ioResponse.bits.index := strippedResponseSourceId
listBuffer.ioResponse.bits.data.data := out.d.bits.data
listBuffer.ioResponse.bits.data.resp := dResp
listBuffer.ioResponse.bits.data.last := dLast
listBuffer.ioResponse.bits.data.user :<= out.d.bits.user
listBuffer.ioResponse.bits.count := dCount
listBuffer.ioResponse.bits.numBeats1 := dNumBeats1
okR.bits.id := listBuffer.ioDataOut.bits.listIndex
okR.bits.data := listBuffer.ioDataOut.bits.payload.data
okR.bits.resp := listBuffer.ioDataOut.bits.payload.resp
okR.bits.last := listBuffer.ioDataOut.bits.payload.last
okR.bits.user :<= listBuffer.ioDataOut.bits.payload.user
// Upon the final beat in a write request, record a mapping from TileLink source ID to AXI write ID. Upon a write
// response, mark the write transaction as complete.
val writeIdMap = Mem(numTlTxns, UInt(log2Ceil(numIds).W))
val writeResponseId = writeIdMap.read(strippedResponseSourceId)
when(wOut.fire) {
writeIdMap.write(freeWriteIdIndex, in.aw.bits.id)
}
when(edgeOut.done(wOut)) {
usedWriteIdsSet := freeWriteIdOH
}
when(okB.fire) {
usedWriteIdsClr := UIntToOH(strippedResponseSourceId, numTlTxns)
}
okB.bits.id := writeResponseId
okB.bits.resp := dResp
okB.bits.user :<= out.d.bits.user
// AXI4 needs irrevocable behaviour
in.r <> Queue.irrevocable(okR, 1, flow = true)
in.b <> Queue.irrevocable(okB, 1, flow = true)
// Unused channels
out.b.ready := true.B
out.c.valid := false.B
out.e.valid := false.B
/* Alignment constraints. The AXI4Fragmenter should guarantee all of these constraints. */
def checkRequest[T <: AXI4BundleA](a: IrrevocableIO[T], reqType: String): Unit = {
val lReqType = reqType.toLowerCase
when(a.valid) {
assert(a.bits.len < maxBeats.U, s"$reqType burst length (%d) must be less than $maxBeats", a.bits.len + 1.U)
// Narrow transfers and FIXED bursts must be single-beat bursts.
when(a.bits.len =/= 0.U) {
assert(
a.bits.size === log2Ceil(beatBytes).U,
s"Narrow $lReqType transfers (%d < $beatBytes bytes) can't be multi-beat bursts (%d beats)",
1.U << a.bits.size,
a.bits.len + 1.U
)
assert(
a.bits.burst =/= AXI4Parameters.BURST_FIXED,
s"Fixed $lReqType bursts can't be multi-beat bursts (%d beats)",
a.bits.len + 1.U
)
}
// Furthermore, the transfer size (a.bits.bytes1() + 1.U) must be naturally-aligned to the address (in
// particular, during both WRAP and INCR bursts), but this constraint is already checked by TileLink
// Monitors. Note that this alignment requirement means that WRAP bursts are identical to INCR bursts.
}
}
checkRequest(in.ar, "Read")
checkRequest(in.aw, "Write")
}
}
}
object UnsafeAXI4ToTL {
def apply(numTlTxns: Int = 1, wcorrupt: Boolean = true)(implicit p: Parameters) = {
val axi42tl = LazyModule(new UnsafeAXI4ToTL(numTlTxns, wcorrupt))
axi42tl.node
}
}
/* ReservableListBuffer logic, and associated classes. */
class ResponsePayload[T <: Data](val data: T, val params: ReservableListBufferParameters) extends Bundle {
val index = UInt(params.entryBits.W)
val count = UInt(params.beatBits.W)
val numBeats1 = UInt(params.beatBits.W)
}
class DataOutPayload[T <: Data](val payload: T, val params: ReservableListBufferParameters) extends Bundle {
val listIndex = UInt(params.listBits.W)
}
/** Abstract base class to unify [[ReservableListBuffer]] and [[PassthroughListBuffer]]. */
abstract class BaseReservableListBuffer[T <: Data](gen: T, params: ReservableListBufferParameters)
extends Module {
require(params.numEntries > 0)
require(params.numLists > 0)
val ioReserve = IO(Flipped(Decoupled(UInt(params.listBits.W))))
val ioReservedIndex = IO(Output(UInt(params.entryBits.W)))
val ioResponse = IO(Flipped(Decoupled(new ResponsePayload(gen, params))))
val ioDataOut = IO(Decoupled(new DataOutPayload(gen, params)))
}
/** A modified version of 'ListBuffer' from 'sifive/block-inclusivecache-sifive'. This module forces users to reserve
* linked list entries (through the 'ioReserve' port) before writing data into those linked lists (through the
* 'ioResponse' port). Each response is tagged to indicate which linked list it is written into. The responses for a
* given linked list can come back out-of-order, but they will be read out through the 'ioDataOut' port in-order.
*
* ==Constructor==
* @param gen Chisel type of linked list data element
* @param params Other parameters
*
* ==Module IO==
* @param ioReserve Index of list to reserve a new element in
* @param ioReservedIndex Index of the entry that was reserved in the linked list, valid when 'ioReserve.fire'
* @param ioResponse Payload containing response data and linked-list-entry index
* @param ioDataOut Payload containing data read from response linked list and linked list index
*/
class ReservableListBuffer[T <: Data](gen: T, params: ReservableListBufferParameters)
extends BaseReservableListBuffer(gen, params) {
val valid = RegInit(0.U(params.numLists.W))
val head = Mem(params.numLists, UInt(params.entryBits.W))
val tail = Mem(params.numLists, UInt(params.entryBits.W))
val used = RegInit(0.U(params.numEntries.W))
val next = Mem(params.numEntries, UInt(params.entryBits.W))
val map = Mem(params.numEntries, UInt(params.listBits.W))
val dataMems = Seq.fill(params.numBeats) { SyncReadMem(params.numEntries, gen) }
val dataIsPresent = RegInit(0.U(params.numEntries.W))
val beats = Mem(params.numEntries, UInt(params.beatBits.W))
// The 'data' SRAM should be single-ported (read-or-write), since dual-ported SRAMs are significantly slower.
val dataMemReadEnable = WireDefault(false.B)
val dataMemWriteEnable = WireDefault(false.B)
assert(!(dataMemReadEnable && dataMemWriteEnable))
// 'freeOH' has a single bit set, which is the least-significant bit that is cleared in 'used'. So, it's the
// lowest-index entry in the 'data' RAM which is free.
val freeOH = Wire(UInt(params.numEntries.W))
val freeIndex = OHToUInt(freeOH)
freeOH := ~(leftOR(~used) << 1) & ~used
ioReservedIndex := freeIndex
val validSet = WireDefault(0.U(params.numLists.W))
val validClr = WireDefault(0.U(params.numLists.W))
val usedSet = WireDefault(0.U(params.numEntries.W))
val usedClr = WireDefault(0.U(params.numEntries.W))
val dataIsPresentSet = WireDefault(0.U(params.numEntries.W))
val dataIsPresentClr = WireDefault(0.U(params.numEntries.W))
valid := (valid & ~validClr) | validSet
used := (used & ~usedClr) | usedSet
dataIsPresent := (dataIsPresent & ~dataIsPresentClr) | dataIsPresentSet
/* Reservation logic signals */
val reserveTail = Wire(UInt(params.entryBits.W))
val reserveIsValid = Wire(Bool())
/* Response logic signals */
val responseIndex = Wire(UInt(params.entryBits.W))
val responseListIndex = Wire(UInt(params.listBits.W))
val responseHead = Wire(UInt(params.entryBits.W))
val responseTail = Wire(UInt(params.entryBits.W))
val nextResponseHead = Wire(UInt(params.entryBits.W))
val nextDataIsPresent = Wire(Bool())
val isResponseInOrder = Wire(Bool())
val isEndOfList = Wire(Bool())
val isLastBeat = Wire(Bool())
val isLastResponseBeat = Wire(Bool())
val isLastUnwindBeat = Wire(Bool())
/* Reservation logic */
reserveTail := tail.read(ioReserve.bits)
reserveIsValid := valid(ioReserve.bits)
ioReserve.ready := !used.andR
// When we want to append-to and destroy the same linked list on the same cycle, we need to take special care that we
// actually start a new list, rather than appending to a list that's about to disappear.
val reserveResponseSameList = ioReserve.bits === responseListIndex
val appendToAndDestroyList =
ioReserve.fire && ioDataOut.fire && reserveResponseSameList && isEndOfList && isLastBeat
when(ioReserve.fire) {
validSet := UIntToOH(ioReserve.bits, params.numLists)
usedSet := freeOH
when(reserveIsValid && !appendToAndDestroyList) {
next.write(reserveTail, freeIndex)
}.otherwise {
head.write(ioReserve.bits, freeIndex)
}
tail.write(ioReserve.bits, freeIndex)
map.write(freeIndex, ioReserve.bits)
}
/* Response logic */
// The majority of the response logic (reading from and writing to the various RAMs) is common between the
// response-from-IO case (ioResponse.fire) and the response-from-unwind case (unwindDataIsValid).
// The read from the 'next' RAM should be performed at the address given by 'responseHead'. However, we only use the
// 'nextResponseHead' signal when 'isResponseInOrder' is asserted (both in the response-from-IO and
// response-from-unwind cases), which implies that 'responseHead' equals 'responseIndex'. 'responseHead' comes after
// two back-to-back RAM reads, so indexing into the 'next' RAM with 'responseIndex' is much quicker.
responseHead := head.read(responseListIndex)
responseTail := tail.read(responseListIndex)
nextResponseHead := next.read(responseIndex)
nextDataIsPresent := dataIsPresent(nextResponseHead)
// Note that when 'isEndOfList' is asserted, 'nextResponseHead' (and therefore 'nextDataIsPresent') is invalid, since
// there isn't a next element in the linked list.
isResponseInOrder := responseHead === responseIndex
isEndOfList := responseHead === responseTail
isLastResponseBeat := ioResponse.bits.count === ioResponse.bits.numBeats1
// When a response's last beat is sent to the output channel, mark it as completed. This can happen in two
// situations:
// 1. We receive an in-order response, which travels straight from 'ioResponse' to 'ioDataOut'. The 'data' SRAM
// reservation was never needed.
// 2. An entry is read out of the 'data' SRAM (within the unwind FSM).
when(ioDataOut.fire && isLastBeat) {
// Mark the reservation as no-longer-used.
usedClr := UIntToOH(responseIndex, params.numEntries)
// If the response is in-order, then we're popping an element from this linked list.
when(isEndOfList) {
// Once we pop the last element from a linked list, mark it as no-longer-present.
validClr := UIntToOH(responseListIndex, params.numLists)
}.otherwise {
// Move the linked list's head pointer to the new head pointer.
head.write(responseListIndex, nextResponseHead)
}
}
// If we get an out-of-order response, then stash it in the 'data' SRAM for later unwinding.
when(ioResponse.fire && !isResponseInOrder) {
dataMemWriteEnable := true.B
when(isLastResponseBeat) {
dataIsPresentSet := UIntToOH(ioResponse.bits.index, params.numEntries)
beats.write(ioResponse.bits.index, ioResponse.bits.numBeats1)
}
}
// Use the 'ioResponse.bits.count' index (AKA the beat number) to select which 'data' SRAM to write to.
val responseCountOH = UIntToOH(ioResponse.bits.count, params.numBeats)
(responseCountOH.asBools zip dataMems) foreach { case (select, seqMem) =>
when(select && dataMemWriteEnable) {
seqMem.write(ioResponse.bits.index, ioResponse.bits.data)
}
}
/* Response unwind logic */
// Unwind FSM state definitions
val sIdle :: sUnwinding :: Nil = Enum(2)
val unwindState = RegInit(sIdle)
val busyUnwinding = unwindState === sUnwinding
val startUnwind = Wire(Bool())
val stopUnwind = Wire(Bool())
when(startUnwind) {
unwindState := sUnwinding
}.elsewhen(stopUnwind) {
unwindState := sIdle
}
assert(!(startUnwind && stopUnwind))
// Start the unwind FSM when there is an old out-of-order response stored in the 'data' SRAM that is now about to
// become the next in-order response. As noted previously, when 'isEndOfList' is asserted, 'nextDataIsPresent' is
// invalid.
//
// Note that since an in-order response from 'ioResponse' to 'ioDataOut' starts the unwind FSM, we don't have to
// worry about overwriting the 'data' SRAM's output when we start the unwind FSM.
startUnwind := ioResponse.fire && isResponseInOrder && isLastResponseBeat && !isEndOfList && nextDataIsPresent
// Stop the unwind FSM when the output channel consumes the final beat of an element from the unwind FSM, and one of
// two things happens:
// 1. We're still waiting for the next in-order response for this list (!nextDataIsPresent)
// 2. There are no more outstanding responses in this list (isEndOfList)
//
// Including 'busyUnwinding' ensures this is a single-cycle pulse, and it never fires while in-order transactions are
// passing from 'ioResponse' to 'ioDataOut'.
stopUnwind := busyUnwinding && ioDataOut.fire && isLastUnwindBeat && (!nextDataIsPresent || isEndOfList)
val isUnwindBurstOver = Wire(Bool())
val startNewBurst = startUnwind || (isUnwindBurstOver && dataMemReadEnable)
// Track the number of beats left to unwind for each list entry. At the start of a new burst, we flop the number of
// beats in this burst (minus 1) into 'unwindBeats1', and we reset the 'beatCounter' counter. With each beat, we
// increment 'beatCounter' until it reaches 'unwindBeats1'.
val unwindBeats1 = Reg(UInt(params.beatBits.W))
val nextBeatCounter = Wire(UInt(params.beatBits.W))
val beatCounter = RegNext(nextBeatCounter)
isUnwindBurstOver := beatCounter === unwindBeats1
when(startNewBurst) {
unwindBeats1 := beats.read(nextResponseHead)
nextBeatCounter := 0.U
}.elsewhen(dataMemReadEnable) {
nextBeatCounter := beatCounter + 1.U
}.otherwise {
nextBeatCounter := beatCounter
}
// When unwinding, feed the next linked-list head pointer (read out of the 'next' RAM) back so we can unwind the next
// entry in this linked list. Only update the pointer when we're actually moving to the next 'data' SRAM entry (which
// happens at the start of reading a new stored burst).
val unwindResponseIndex = RegEnable(nextResponseHead, startNewBurst)
responseIndex := Mux(busyUnwinding, unwindResponseIndex, ioResponse.bits.index)
// Hold 'nextResponseHead' static while we're in the middle of unwinding a multi-beat burst entry. We don't want the
// SRAM read address to shift while reading beats from a burst. Note that this is identical to 'nextResponseHead
// holdUnless startNewBurst', but 'unwindResponseIndex' already implements the 'RegEnable' signal in 'holdUnless'.
val unwindReadAddress = Mux(startNewBurst, nextResponseHead, unwindResponseIndex)
// The 'data' SRAM's output is valid if we read from the SRAM on the previous cycle. The SRAM's output stays valid
// until it is consumed by the output channel (and if we don't read from the SRAM again on that same cycle).
val unwindDataIsValid = RegInit(false.B)
when(dataMemReadEnable) {
unwindDataIsValid := true.B
}.elsewhen(ioDataOut.fire) {
unwindDataIsValid := false.B
}
isLastUnwindBeat := isUnwindBurstOver && unwindDataIsValid
// Indicates if this is the last beat for both 'ioResponse'-to-'ioDataOut' and unwind-to-'ioDataOut' beats.
isLastBeat := Mux(busyUnwinding, isLastUnwindBeat, isLastResponseBeat)
// Select which SRAM to read from based on the beat counter.
val dataOutputVec = Wire(Vec(params.numBeats, gen))
val nextBeatCounterOH = UIntToOH(nextBeatCounter, params.numBeats)
(nextBeatCounterOH.asBools zip dataMems).zipWithIndex foreach { case ((select, seqMem), i) =>
dataOutputVec(i) := seqMem.read(unwindReadAddress, select && dataMemReadEnable)
}
// Select the current 'data' SRAM output beat, and save the output in a register in case we're being back-pressured
// by 'ioDataOut'. This implements the functionality of 'readAndHold', but only on the single SRAM we're reading
// from.
val dataOutput = dataOutputVec(beatCounter) holdUnless RegNext(dataMemReadEnable)
// Mark 'data' burst entries as no-longer-present as they get read out of the SRAM.
when(dataMemReadEnable) {
dataIsPresentClr := UIntToOH(unwindReadAddress, params.numEntries)
}
// As noted above, when starting the unwind FSM, we know the 'data' SRAM's output isn't valid, so it's safe to issue
// a read command. Otherwise, only issue an SRAM read when the next 'unwindState' is 'sUnwinding', and if we know
// we're not going to overwrite the SRAM's current output (the SRAM output is already valid, and it's not going to be
// consumed by the output channel).
val dontReadFromDataMem = unwindDataIsValid && !ioDataOut.ready
dataMemReadEnable := startUnwind || (busyUnwinding && !stopUnwind && !dontReadFromDataMem)
// While unwinding, prevent new reservations from overwriting the current 'map' entry that we're using. We need
// 'responseListIndex' to be coherent for the entire unwind process.
val rawResponseListIndex = map.read(responseIndex)
val unwindResponseListIndex = RegEnable(rawResponseListIndex, startNewBurst)
responseListIndex := Mux(busyUnwinding, unwindResponseListIndex, rawResponseListIndex)
// Accept responses either when they can be passed through to the output channel, or if they're out-of-order and are
// just going to be stashed in the 'data' SRAM. Never accept a response payload when we're busy unwinding, since that
// could result in reading from and writing to the 'data' SRAM in the same cycle, and we want that SRAM to be
// single-ported.
ioResponse.ready := (ioDataOut.ready || !isResponseInOrder) && !busyUnwinding
// Either pass an in-order response to the output channel, or data read from the unwind FSM.
ioDataOut.valid := Mux(busyUnwinding, unwindDataIsValid, ioResponse.valid && isResponseInOrder)
ioDataOut.bits.listIndex := responseListIndex
ioDataOut.bits.payload := Mux(busyUnwinding, dataOutput, ioResponse.bits.data)
// It's an error to get a response that isn't associated with a valid linked list.
when(ioResponse.fire || unwindDataIsValid) {
assert(
valid(responseListIndex),
"No linked list exists at index %d, mapped from %d",
responseListIndex,
responseIndex
)
}
when(busyUnwinding && dataMemReadEnable) {
assert(isResponseInOrder, "Unwind FSM must read entries from SRAM in order")
}
}
/** Specialized version of [[ReservableListBuffer]] for the case of numEntries == 1.
*
* Much of the complex logic in [[ReservableListBuffer]] can disappear in this case. For instance, we don't have to
* reorder any responses, or store any linked lists.
*/
class PassthroughListBuffer[T <: Data](gen: T, params: ReservableListBufferParameters)
extends BaseReservableListBuffer(gen, params) {
require(params.numEntries == 1, s"PassthroughListBuffer is only valid when 'numEntries' (${params.numEntries}) is 1")
val used = RegInit(0.U(params.numEntries.W))
val map = Mem(params.numEntries, UInt(params.listBits.W))
val usedSet = WireDefault(0.U(params.numEntries.W))
val usedClr = WireDefault(0.U(params.numEntries.W))
used := (used & ~usedClr) | usedSet
ioReserve.ready := used === 0.U
// Store which list index was reserved, we need to return this value when we get a response.
when(ioReserve.fire) {
usedSet := 1.U
map.write(0.U, ioReserve.bits)
}
// There's only one valid linked list entry, which is at index 0.
ioReservedIndex := 0.U
val isLastResponseBeat = ioResponse.bits.count === ioResponse.bits.numBeats1
// Mark the linked list as empty when we get the last beat in a response.
// Note that 'ioResponse.fire === ioDataOut.fire'.
when(ioResponse.fire && isLastResponseBeat) {
usedClr := 1.U
}
// Always pass the response data straight through, since we never need to reorder the response data.
ioDataOut.bits.listIndex := map.read(0.U)
ioDataOut.bits.payload := ioResponse.bits.data
ioDataOut.valid := ioResponse.valid
ioResponse.ready := ioDataOut.ready
}
| module dataMems_242( // @[UnsafeAXI4ToTL.scala:365:62]
input [4:0] R0_addr,
input R0_en,
input R0_clk,
output [66:0] R0_data,
input [4:0] W0_addr,
input W0_en,
input W0_clk,
input [66:0] W0_data
);
dataMems_0_ext dataMems_0_ext ( // @[UnsafeAXI4ToTL.scala:365:62]
.R0_addr (R0_addr),
.R0_en (R0_en),
.R0_clk (R0_clk),
.R0_data (R0_data),
.W0_addr (W0_addr),
.W0_en (W0_en),
.W0_clk (W0_clk),
.W0_data (W0_data)
); // @[UnsafeAXI4ToTL.scala:365:62]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File PE.scala:
// See README.md for license details.
package gemmini
import chisel3._
import chisel3.util._
class PEControl[T <: Data : Arithmetic](accType: T) extends Bundle {
val dataflow = UInt(1.W) // TODO make this an Enum
val propagate = UInt(1.W) // Which register should be propagated (and which should be accumulated)?
val shift = UInt(log2Up(accType.getWidth).W) // TODO this isn't correct for Floats
}
class MacUnit[T <: Data](inputType: T, cType: T, dType: T) (implicit ev: Arithmetic[T]) extends Module {
import ev._
val io = IO(new Bundle {
val in_a = Input(inputType)
val in_b = Input(inputType)
val in_c = Input(cType)
val out_d = Output(dType)
})
io.out_d := io.in_c.mac(io.in_a, io.in_b)
}
// TODO update documentation
/**
* A PE implementing a MAC operation. Configured as fully combinational when integrated into a Mesh.
* @param width Data width of operands
*/
class PE[T <: Data](inputType: T, outputType: T, accType: T, df: Dataflow.Value, max_simultaneous_matmuls: Int)
(implicit ev: Arithmetic[T]) extends Module { // Debugging variables
import ev._
val io = IO(new Bundle {
val in_a = Input(inputType)
val in_b = Input(outputType)
val in_d = Input(outputType)
val out_a = Output(inputType)
val out_b = Output(outputType)
val out_c = Output(outputType)
val in_control = Input(new PEControl(accType))
val out_control = Output(new PEControl(accType))
val in_id = Input(UInt(log2Up(max_simultaneous_matmuls).W))
val out_id = Output(UInt(log2Up(max_simultaneous_matmuls).W))
val in_last = Input(Bool())
val out_last = Output(Bool())
val in_valid = Input(Bool())
val out_valid = Output(Bool())
val bad_dataflow = Output(Bool())
})
val cType = if (df == Dataflow.WS) inputType else accType
// When creating PEs that support multiple dataflows, the
// elaboration/synthesis tools often fail to consolidate and de-duplicate
// MAC units. To force mac circuitry to be re-used, we create a "mac_unit"
// module here which just performs a single MAC operation
val mac_unit = Module(new MacUnit(inputType,
if (df == Dataflow.WS) outputType else accType, outputType))
val a = io.in_a
val b = io.in_b
val d = io.in_d
val c1 = Reg(cType)
val c2 = Reg(cType)
val dataflow = io.in_control.dataflow
val prop = io.in_control.propagate
val shift = io.in_control.shift
val id = io.in_id
val last = io.in_last
val valid = io.in_valid
io.out_a := a
io.out_control.dataflow := dataflow
io.out_control.propagate := prop
io.out_control.shift := shift
io.out_id := id
io.out_last := last
io.out_valid := valid
mac_unit.io.in_a := a
val last_s = RegEnable(prop, valid)
val flip = last_s =/= prop
val shift_offset = Mux(flip, shift, 0.U)
// Which dataflow are we using?
val OUTPUT_STATIONARY = Dataflow.OS.id.U(1.W)
val WEIGHT_STATIONARY = Dataflow.WS.id.U(1.W)
// Is c1 being computed on, or propagated forward (in the output-stationary dataflow)?
val COMPUTE = 0.U(1.W)
val PROPAGATE = 1.U(1.W)
io.bad_dataflow := false.B
when ((df == Dataflow.OS).B || ((df == Dataflow.BOTH).B && dataflow === OUTPUT_STATIONARY)) {
when(prop === PROPAGATE) {
io.out_c := (c1 >> shift_offset).clippedToWidthOf(outputType)
io.out_b := b
mac_unit.io.in_b := b.asTypeOf(inputType)
mac_unit.io.in_c := c2
c2 := mac_unit.io.out_d
c1 := d.withWidthOf(cType)
}.otherwise {
io.out_c := (c2 >> shift_offset).clippedToWidthOf(outputType)
io.out_b := b
mac_unit.io.in_b := b.asTypeOf(inputType)
mac_unit.io.in_c := c1
c1 := mac_unit.io.out_d
c2 := d.withWidthOf(cType)
}
}.elsewhen ((df == Dataflow.WS).B || ((df == Dataflow.BOTH).B && dataflow === WEIGHT_STATIONARY)) {
when(prop === PROPAGATE) {
io.out_c := c1
mac_unit.io.in_b := c2.asTypeOf(inputType)
mac_unit.io.in_c := b
io.out_b := mac_unit.io.out_d
c1 := d
}.otherwise {
io.out_c := c2
mac_unit.io.in_b := c1.asTypeOf(inputType)
mac_unit.io.in_c := b
io.out_b := mac_unit.io.out_d
c2 := d
}
}.otherwise {
io.bad_dataflow := true.B
//assert(false.B, "unknown dataflow")
io.out_c := DontCare
io.out_b := DontCare
mac_unit.io.in_b := b.asTypeOf(inputType)
mac_unit.io.in_c := c2
}
when (!valid) {
c1 := c1
c2 := c2
mac_unit.io.in_b := DontCare
mac_unit.io.in_c := DontCare
}
}
File Arithmetic.scala:
// A simple type class for Chisel datatypes that can add and multiply. To add your own type, simply create your own:
// implicit MyTypeArithmetic extends Arithmetic[MyType] { ... }
package gemmini
import chisel3._
import chisel3.util._
import hardfloat._
// Bundles that represent the raw bits of custom datatypes
case class Float(expWidth: Int, sigWidth: Int) extends Bundle {
val bits = UInt((expWidth + sigWidth).W)
val bias: Int = (1 << (expWidth-1)) - 1
}
case class DummySInt(w: Int) extends Bundle {
val bits = UInt(w.W)
def dontCare: DummySInt = {
val o = Wire(new DummySInt(w))
o.bits := 0.U
o
}
}
// The Arithmetic typeclass which implements various arithmetic operations on custom datatypes
abstract class Arithmetic[T <: Data] {
implicit def cast(t: T): ArithmeticOps[T]
}
abstract class ArithmeticOps[T <: Data](self: T) {
def *(t: T): T
def mac(m1: T, m2: T): T // Returns (m1 * m2 + self)
def +(t: T): T
def -(t: T): T
def >>(u: UInt): T // This is a rounding shift! Rounds away from 0
def >(t: T): Bool
def identity: T
def withWidthOf(t: T): T
def clippedToWidthOf(t: T): T // Like "withWidthOf", except that it saturates
def relu: T
def zero: T
def minimum: T
// Optional parameters, which only need to be defined if you want to enable various optimizations for transformers
def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[T])] = None
def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[T])] = None
def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = None
def mult_with_reciprocal[U <: Data](reciprocal: U) = self
}
object Arithmetic {
implicit object UIntArithmetic extends Arithmetic[UInt] {
override implicit def cast(self: UInt) = new ArithmeticOps(self) {
override def *(t: UInt) = self * t
override def mac(m1: UInt, m2: UInt) = m1 * m2 + self
override def +(t: UInt) = self + t
override def -(t: UInt) = self - t
override def >>(u: UInt) = {
// The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm
// TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here?
val point_five = Mux(u === 0.U, 0.U, self(u - 1.U))
val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U
val ones_digit = self(u)
val r = point_five & (zeros | ones_digit)
(self >> u).asUInt + r
}
override def >(t: UInt): Bool = self > t
override def withWidthOf(t: UInt) = self.asTypeOf(t)
override def clippedToWidthOf(t: UInt) = {
val sat = ((1 << (t.getWidth-1))-1).U
Mux(self > sat, sat, self)(t.getWidth-1, 0)
}
override def relu: UInt = self
override def zero: UInt = 0.U
override def identity: UInt = 1.U
override def minimum: UInt = 0.U
}
}
implicit object SIntArithmetic extends Arithmetic[SInt] {
override implicit def cast(self: SInt) = new ArithmeticOps(self) {
override def *(t: SInt) = self * t
override def mac(m1: SInt, m2: SInt) = m1 * m2 + self
override def +(t: SInt) = self + t
override def -(t: SInt) = self - t
override def >>(u: UInt) = {
// The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm
// TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here?
val point_five = Mux(u === 0.U, 0.U, self(u - 1.U))
val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U
val ones_digit = self(u)
val r = (point_five & (zeros | ones_digit)).asBool
(self >> u).asSInt + Mux(r, 1.S, 0.S)
}
override def >(t: SInt): Bool = self > t
override def withWidthOf(t: SInt) = {
if (self.getWidth >= t.getWidth)
self(t.getWidth-1, 0).asSInt
else {
val sign_bits = t.getWidth - self.getWidth
val sign = self(self.getWidth-1)
Cat(Cat(Seq.fill(sign_bits)(sign)), self).asTypeOf(t)
}
}
override def clippedToWidthOf(t: SInt): SInt = {
val maxsat = ((1 << (t.getWidth-1))-1).S
val minsat = (-(1 << (t.getWidth-1))).S
MuxCase(self, Seq((self > maxsat) -> maxsat, (self < minsat) -> minsat))(t.getWidth-1, 0).asSInt
}
override def relu: SInt = Mux(self >= 0.S, self, 0.S)
override def zero: SInt = 0.S
override def identity: SInt = 1.S
override def minimum: SInt = (-(1 << (self.getWidth-1))).S
override def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = {
// TODO this uses a floating point divider, but we should use an integer divider instead
val input = Wire(Decoupled(denom_t.cloneType))
val output = Wire(Decoupled(self.cloneType))
// We translate our integer to floating-point form so that we can use the hardfloat divider
val expWidth = log2Up(self.getWidth) + 1
val sigWidth = self.getWidth
def sin_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def uin_to_float(x: UInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := false.B
in_to_rec_fn.io.in := x
in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def float_to_in(x: UInt) = {
val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth))
rec_fn_to_in.io.signedOut := true.B
rec_fn_to_in.io.in := x
rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
rec_fn_to_in.io.out.asSInt
}
val self_rec = sin_to_float(self)
val denom_rec = uin_to_float(input.bits)
// Instantiate the hardloat divider
val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options))
input.ready := divider.io.inReady
divider.io.inValid := input.valid
divider.io.sqrtOp := false.B
divider.io.a := self_rec
divider.io.b := denom_rec
divider.io.roundingMode := consts.round_minMag
divider.io.detectTininess := consts.tininess_afterRounding
output.valid := divider.io.outValid_div
output.bits := float_to_in(divider.io.out)
assert(!output.valid || output.ready)
Some((input, output))
}
override def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = {
// TODO this uses a floating point divider, but we should use an integer divider instead
val input = Wire(Decoupled(UInt(0.W)))
val output = Wire(Decoupled(self.cloneType))
input.bits := DontCare
// We translate our integer to floating-point form so that we can use the hardfloat divider
val expWidth = log2Up(self.getWidth) + 1
val sigWidth = self.getWidth
def in_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def float_to_in(x: UInt) = {
val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth))
rec_fn_to_in.io.signedOut := true.B
rec_fn_to_in.io.in := x
rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
rec_fn_to_in.io.out.asSInt
}
val self_rec = in_to_float(self)
// Instantiate the hardloat sqrt
val sqrter = Module(new DivSqrtRecFN_small(expWidth, sigWidth, 0))
input.ready := sqrter.io.inReady
sqrter.io.inValid := input.valid
sqrter.io.sqrtOp := true.B
sqrter.io.a := self_rec
sqrter.io.b := DontCare
sqrter.io.roundingMode := consts.round_minMag
sqrter.io.detectTininess := consts.tininess_afterRounding
output.valid := sqrter.io.outValid_sqrt
output.bits := float_to_in(sqrter.io.out)
assert(!output.valid || output.ready)
Some((input, output))
}
override def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = u match {
case Float(expWidth, sigWidth) =>
val input = Wire(Decoupled(UInt(0.W)))
val output = Wire(Decoupled(u.cloneType))
input.bits := DontCare
// We translate our integer to floating-point form so that we can use the hardfloat divider
def in_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
val self_rec = in_to_float(self)
val one_rec = in_to_float(1.S)
// Instantiate the hardloat divider
val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options))
input.ready := divider.io.inReady
divider.io.inValid := input.valid
divider.io.sqrtOp := false.B
divider.io.a := one_rec
divider.io.b := self_rec
divider.io.roundingMode := consts.round_near_even
divider.io.detectTininess := consts.tininess_afterRounding
output.valid := divider.io.outValid_div
output.bits := fNFromRecFN(expWidth, sigWidth, divider.io.out).asTypeOf(u)
assert(!output.valid || output.ready)
Some((input, output))
case _ => None
}
override def mult_with_reciprocal[U <: Data](reciprocal: U): SInt = reciprocal match {
case recip @ Float(expWidth, sigWidth) =>
def in_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def float_to_in(x: UInt) = {
val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth))
rec_fn_to_in.io.signedOut := true.B
rec_fn_to_in.io.in := x
rec_fn_to_in.io.roundingMode := consts.round_minMag
rec_fn_to_in.io.out.asSInt
}
val self_rec = in_to_float(self)
val reciprocal_rec = recFNFromFN(expWidth, sigWidth, recip.bits)
// Instantiate the hardloat divider
val muladder = Module(new MulRecFN(expWidth, sigWidth))
muladder.io.roundingMode := consts.round_near_even
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := self_rec
muladder.io.b := reciprocal_rec
float_to_in(muladder.io.out)
case _ => self
}
}
}
implicit object FloatArithmetic extends Arithmetic[Float] {
// TODO Floating point arithmetic currently switches between recoded and standard formats for every operation. However, it should stay in the recoded format as it travels through the systolic array
override implicit def cast(self: Float): ArithmeticOps[Float] = new ArithmeticOps(self) {
override def *(t: Float): Float = {
val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth))
t_resizer.io.in := t_rec
t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
t_resizer.io.detectTininess := consts.tininess_afterRounding
val t_rec_resized = t_resizer.io.out
val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth))
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := self_rec
muladder.io.b := t_rec_resized
val out = Wire(Float(self.expWidth, self.sigWidth))
out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
out
}
override def mac(m1: Float, m2: Float): Float = {
// Recode all operands
val m1_rec = recFNFromFN(m1.expWidth, m1.sigWidth, m1.bits)
val m2_rec = recFNFromFN(m2.expWidth, m2.sigWidth, m2.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Resize m1 to self's width
val m1_resizer = Module(new RecFNToRecFN(m1.expWidth, m1.sigWidth, self.expWidth, self.sigWidth))
m1_resizer.io.in := m1_rec
m1_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
m1_resizer.io.detectTininess := consts.tininess_afterRounding
val m1_rec_resized = m1_resizer.io.out
// Resize m2 to self's width
val m2_resizer = Module(new RecFNToRecFN(m2.expWidth, m2.sigWidth, self.expWidth, self.sigWidth))
m2_resizer.io.in := m2_rec
m2_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
m2_resizer.io.detectTininess := consts.tininess_afterRounding
val m2_rec_resized = m2_resizer.io.out
// Perform multiply-add
val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth))
muladder.io.op := 0.U
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := m1_rec_resized
muladder.io.b := m2_rec_resized
muladder.io.c := self_rec
// Convert result to standard format // TODO remove these intermediate recodings
val out = Wire(Float(self.expWidth, self.sigWidth))
out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
out
}
override def +(t: Float): Float = {
require(self.getWidth >= t.getWidth) // This just makes it easier to write the resizing code
// Recode all operands
val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Generate 1 as a float
val in_to_rec_fn = Module(new INToRecFN(1, self.expWidth, self.sigWidth))
in_to_rec_fn.io.signedIn := false.B
in_to_rec_fn.io.in := 1.U
in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
val one_rec = in_to_rec_fn.io.out
// Resize t
val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth))
t_resizer.io.in := t_rec
t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
t_resizer.io.detectTininess := consts.tininess_afterRounding
val t_rec_resized = t_resizer.io.out
// Perform addition
val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth))
muladder.io.op := 0.U
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := t_rec_resized
muladder.io.b := one_rec
muladder.io.c := self_rec
val result = Wire(Float(self.expWidth, self.sigWidth))
result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
result
}
override def -(t: Float): Float = {
val t_sgn = t.bits(t.getWidth-1)
val neg_t = Cat(~t_sgn, t.bits(t.getWidth-2,0)).asTypeOf(t)
self + neg_t
}
override def >>(u: UInt): Float = {
// Recode self
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Get 2^(-u) as a recoded float
val shift_exp = Wire(UInt(self.expWidth.W))
shift_exp := self.bias.U - u
val shift_fn = Cat(0.U(1.W), shift_exp, 0.U((self.sigWidth-1).W))
val shift_rec = recFNFromFN(self.expWidth, self.sigWidth, shift_fn)
assert(shift_exp =/= 0.U, "scaling by denormalized numbers is not currently supported")
// Multiply self and 2^(-u)
val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth))
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := self_rec
muladder.io.b := shift_rec
val result = Wire(Float(self.expWidth, self.sigWidth))
result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
result
}
override def >(t: Float): Bool = {
// Recode all operands
val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Resize t to self's width
val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth))
t_resizer.io.in := t_rec
t_resizer.io.roundingMode := consts.round_near_even
t_resizer.io.detectTininess := consts.tininess_afterRounding
val t_rec_resized = t_resizer.io.out
val comparator = Module(new CompareRecFN(self.expWidth, self.sigWidth))
comparator.io.a := self_rec
comparator.io.b := t_rec_resized
comparator.io.signaling := false.B
comparator.io.gt
}
override def withWidthOf(t: Float): Float = {
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth))
resizer.io.in := self_rec
resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
resizer.io.detectTininess := consts.tininess_afterRounding
val result = Wire(Float(t.expWidth, t.sigWidth))
result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out)
result
}
override def clippedToWidthOf(t: Float): Float = {
// TODO check for overflow. Right now, we just assume that overflow doesn't happen
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth))
resizer.io.in := self_rec
resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
resizer.io.detectTininess := consts.tininess_afterRounding
val result = Wire(Float(t.expWidth, t.sigWidth))
result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out)
result
}
override def relu: Float = {
val raw = rawFloatFromFN(self.expWidth, self.sigWidth, self.bits)
val result = Wire(Float(self.expWidth, self.sigWidth))
result.bits := Mux(!raw.isZero && raw.sign, 0.U, self.bits)
result
}
override def zero: Float = 0.U.asTypeOf(self)
override def identity: Float = Cat(0.U(2.W), ~(0.U((self.expWidth-1).W)), 0.U((self.sigWidth-1).W)).asTypeOf(self)
override def minimum: Float = Cat(1.U, ~(0.U(self.expWidth.W)), 0.U((self.sigWidth-1).W)).asTypeOf(self)
}
}
implicit object DummySIntArithmetic extends Arithmetic[DummySInt] {
override implicit def cast(self: DummySInt) = new ArithmeticOps(self) {
override def *(t: DummySInt) = self.dontCare
override def mac(m1: DummySInt, m2: DummySInt) = self.dontCare
override def +(t: DummySInt) = self.dontCare
override def -(t: DummySInt) = self.dontCare
override def >>(t: UInt) = self.dontCare
override def >(t: DummySInt): Bool = false.B
override def identity = self.dontCare
override def withWidthOf(t: DummySInt) = self.dontCare
override def clippedToWidthOf(t: DummySInt) = self.dontCare
override def relu = self.dontCare
override def zero = self.dontCare
override def minimum: DummySInt = self.dontCare
}
}
}
| module MacUnit_33( // @[PE.scala:14:7]
input clock, // @[PE.scala:14:7]
input reset, // @[PE.scala:14:7]
input [7:0] io_in_a, // @[PE.scala:16:14]
input [7:0] io_in_b, // @[PE.scala:16:14]
input [19:0] io_in_c, // @[PE.scala:16:14]
output [19:0] io_out_d // @[PE.scala:16:14]
);
wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:14:7]
wire [7:0] io_in_b_0 = io_in_b; // @[PE.scala:14:7]
wire [19:0] io_in_c_0 = io_in_c; // @[PE.scala:14:7]
wire [19:0] _io_out_d_T_3; // @[Arithmetic.scala:93:54]
wire [19:0] io_out_d_0; // @[PE.scala:14:7]
wire [15:0] _io_out_d_T = {{8{io_in_a_0[7]}}, io_in_a_0} * {{8{io_in_b_0[7]}}, io_in_b_0}; // @[PE.scala:14:7]
wire [20:0] _io_out_d_T_1 = {{5{_io_out_d_T[15]}}, _io_out_d_T} + {io_in_c_0[19], io_in_c_0}; // @[PE.scala:14:7]
wire [19:0] _io_out_d_T_2 = _io_out_d_T_1[19:0]; // @[Arithmetic.scala:93:54]
assign _io_out_d_T_3 = _io_out_d_T_2; // @[Arithmetic.scala:93:54]
assign io_out_d_0 = _io_out_d_T_3; // @[PE.scala:14:7]
assign io_out_d = io_out_d_0; // @[PE.scala:14:7]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File Buffer.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import org.chipsalliance.diplomacy.lazymodule._
import freechips.rocketchip.diplomacy.BufferParams
class TLBufferNode (
a: BufferParams,
b: BufferParams,
c: BufferParams,
d: BufferParams,
e: BufferParams)(implicit valName: ValName) extends TLAdapterNode(
clientFn = { p => p.v1copy(minLatency = p.minLatency + b.latency + c.latency) },
managerFn = { p => p.v1copy(minLatency = p.minLatency + a.latency + d.latency) }
) {
override lazy val nodedebugstring = s"a:${a.toString}, b:${b.toString}, c:${c.toString}, d:${d.toString}, e:${e.toString}"
override def circuitIdentity = List(a,b,c,d,e).forall(_ == BufferParams.none)
}
class TLBuffer(
a: BufferParams,
b: BufferParams,
c: BufferParams,
d: BufferParams,
e: BufferParams)(implicit p: Parameters) extends LazyModule
{
def this(ace: BufferParams, bd: BufferParams)(implicit p: Parameters) = this(ace, bd, ace, bd, ace)
def this(abcde: BufferParams)(implicit p: Parameters) = this(abcde, abcde)
def this()(implicit p: Parameters) = this(BufferParams.default)
val node = new TLBufferNode(a, b, c, d, e)
lazy val module = new Impl
class Impl extends LazyModuleImp(this) {
def headBundle = node.out.head._2.bundle
override def desiredName = (Seq("TLBuffer") ++ node.out.headOption.map(_._2.bundle.shortName)).mkString("_")
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
out.a <> a(in .a)
in .d <> d(out.d)
if (edgeOut.manager.anySupportAcquireB && edgeOut.client.anySupportProbe) {
in .b <> b(out.b)
out.c <> c(in .c)
out.e <> e(in .e)
} else {
in.b.valid := false.B
in.c.ready := true.B
in.e.ready := true.B
out.b.ready := true.B
out.c.valid := false.B
out.e.valid := false.B
}
}
}
}
object TLBuffer
{
def apply() (implicit p: Parameters): TLNode = apply(BufferParams.default)
def apply(abcde: BufferParams) (implicit p: Parameters): TLNode = apply(abcde, abcde)
def apply(ace: BufferParams, bd: BufferParams)(implicit p: Parameters): TLNode = apply(ace, bd, ace, bd, ace)
def apply(
a: BufferParams,
b: BufferParams,
c: BufferParams,
d: BufferParams,
e: BufferParams)(implicit p: Parameters): TLNode =
{
val buffer = LazyModule(new TLBuffer(a, b, c, d, e))
buffer.node
}
def chain(depth: Int, name: Option[String] = None)(implicit p: Parameters): Seq[TLNode] = {
val buffers = Seq.fill(depth) { LazyModule(new TLBuffer()) }
name.foreach { n => buffers.zipWithIndex.foreach { case (b, i) => b.suggestName(s"${n}_${i}") } }
buffers.map(_.node)
}
def chainNode(depth: Int, name: Option[String] = None)(implicit p: Parameters): TLNode = {
chain(depth, name)
.reduceLeftOption(_ :*=* _)
.getOrElse(TLNameNode("no_buffer"))
}
}
File Crossing.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.interrupts
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy.lazymodule._
import freechips.rocketchip.util.{SynchronizerShiftReg, AsyncResetReg}
@deprecated("IntXing does not ensure interrupt source is glitch free. Use IntSyncSource and IntSyncSink", "rocket-chip 1.2")
class IntXing(sync: Int = 3)(implicit p: Parameters) extends LazyModule
{
val intnode = IntAdapterNode()
lazy val module = new Impl
class Impl extends LazyModuleImp(this) {
(intnode.in zip intnode.out) foreach { case ((in, _), (out, _)) =>
out := SynchronizerShiftReg(in, sync)
}
}
}
object IntSyncCrossingSource
{
def apply(alreadyRegistered: Boolean = false)(implicit p: Parameters) =
{
val intsource = LazyModule(new IntSyncCrossingSource(alreadyRegistered))
intsource.node
}
}
class IntSyncCrossingSource(alreadyRegistered: Boolean = false)(implicit p: Parameters) extends LazyModule
{
val node = IntSyncSourceNode(alreadyRegistered)
lazy val module = if (alreadyRegistered) (new ImplRegistered) else (new Impl)
class Impl extends LazyModuleImp(this) {
def outSize = node.out.headOption.map(_._1.sync.size).getOrElse(0)
override def desiredName = s"IntSyncCrossingSource_n${node.out.size}x${outSize}"
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
out.sync := AsyncResetReg(Cat(in.reverse)).asBools
}
}
class ImplRegistered extends LazyRawModuleImp(this) {
def outSize = node.out.headOption.map(_._1.sync.size).getOrElse(0)
override def desiredName = s"IntSyncCrossingSource_n${node.out.size}x${outSize}_Registered"
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
out.sync := in
}
}
}
object IntSyncCrossingSink
{
@deprecated("IntSyncCrossingSink which used the `sync` parameter to determine crossing type is deprecated. Use IntSyncAsyncCrossingSink, IntSyncRationalCrossingSink, or IntSyncSyncCrossingSink instead for > 1, 1, and 0 sync values respectively", "rocket-chip 1.2")
def apply(sync: Int = 3)(implicit p: Parameters) =
{
val intsink = LazyModule(new IntSyncAsyncCrossingSink(sync))
intsink.node
}
}
class IntSyncAsyncCrossingSink(sync: Int = 3)(implicit p: Parameters) extends LazyModule
{
val node = IntSyncSinkNode(sync)
lazy val module = new Impl
class Impl extends LazyModuleImp(this) {
override def desiredName = s"IntSyncAsyncCrossingSink_n${node.out.size}x${node.out.head._1.size}"
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
out := SynchronizerShiftReg(in.sync, sync)
}
}
}
object IntSyncAsyncCrossingSink
{
def apply(sync: Int = 3)(implicit p: Parameters) =
{
val intsink = LazyModule(new IntSyncAsyncCrossingSink(sync))
intsink.node
}
}
class IntSyncSyncCrossingSink()(implicit p: Parameters) extends LazyModule
{
val node = IntSyncSinkNode(0)
lazy val module = new Impl
class Impl extends LazyRawModuleImp(this) {
def outSize = node.out.headOption.map(_._1.size).getOrElse(0)
override def desiredName = s"IntSyncSyncCrossingSink_n${node.out.size}x${outSize}"
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
out := in.sync
}
}
}
object IntSyncSyncCrossingSink
{
def apply()(implicit p: Parameters) =
{
val intsink = LazyModule(new IntSyncSyncCrossingSink())
intsink.node
}
}
class IntSyncRationalCrossingSink()(implicit p: Parameters) extends LazyModule
{
val node = IntSyncSinkNode(1)
lazy val module = new Impl
class Impl extends LazyModuleImp(this) {
def outSize = node.out.headOption.map(_._1.size).getOrElse(0)
override def desiredName = s"IntSyncRationalCrossingSink_n${node.out.size}x${outSize}"
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
out := RegNext(in.sync)
}
}
}
object IntSyncRationalCrossingSink
{
def apply()(implicit p: Parameters) =
{
val intsink = LazyModule(new IntSyncRationalCrossingSink())
intsink.node
}
}
File ClockDomain.scala:
package freechips.rocketchip.prci
import chisel3._
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy.lazymodule._
abstract class Domain(implicit p: Parameters) extends LazyModule with HasDomainCrossing
{
def clockBundle: ClockBundle
lazy val module = new Impl
class Impl extends LazyRawModuleImp(this) {
childClock := clockBundle.clock
childReset := clockBundle.reset
override def provideImplicitClockToLazyChildren = true
// these are just for backwards compatibility with external devices
// that were manually wiring themselves to the domain's clock/reset input:
val clock = IO(Output(chiselTypeOf(clockBundle.clock)))
val reset = IO(Output(chiselTypeOf(clockBundle.reset)))
clock := clockBundle.clock
reset := clockBundle.reset
}
}
abstract class ClockDomain(implicit p: Parameters) extends Domain with HasClockDomainCrossing
class ClockSinkDomain(val clockSinkParams: ClockSinkParameters)(implicit p: Parameters) extends ClockDomain
{
def this(take: Option[ClockParameters] = None, name: Option[String] = None)(implicit p: Parameters) = this(ClockSinkParameters(take = take, name = name))
val clockNode = ClockSinkNode(Seq(clockSinkParams))
def clockBundle = clockNode.in.head._1
override lazy val desiredName = (clockSinkParams.name.toSeq :+ "ClockSinkDomain").mkString
}
class ClockSourceDomain(val clockSourceParams: ClockSourceParameters)(implicit p: Parameters) extends ClockDomain
{
def this(give: Option[ClockParameters] = None, name: Option[String] = None)(implicit p: Parameters) = this(ClockSourceParameters(give = give, name = name))
val clockNode = ClockSourceNode(Seq(clockSourceParams))
def clockBundle = clockNode.out.head._1
override lazy val desiredName = (clockSourceParams.name.toSeq :+ "ClockSourceDomain").mkString
}
abstract class ResetDomain(implicit p: Parameters) extends Domain with HasResetDomainCrossing
File HasTiles.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.subsystem
import chisel3._
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy.bundlebridge._
import org.chipsalliance.diplomacy.lazymodule._
import freechips.rocketchip.devices.debug.TLDebugModule
import freechips.rocketchip.diplomacy.{DisableMonitors, FlipRendering}
import freechips.rocketchip.interrupts.{IntXbar, IntSinkNode, IntSinkPortSimple, IntSyncAsyncCrossingSink}
import freechips.rocketchip.tile.{MaxHartIdBits, BaseTile, InstantiableTileParams, TileParams, TilePRCIDomain, TraceBundle, PriorityMuxHartIdFromSeq}
import freechips.rocketchip.tilelink.TLWidthWidget
import freechips.rocketchip.prci.{ClockGroup, BundleBridgeBlockDuringReset, NoCrossing, SynchronousCrossing, CreditedCrossing, RationalCrossing, AsynchronousCrossing}
import freechips.rocketchip.rocket.TracedInstruction
import freechips.rocketchip.util.TraceCoreInterface
import scala.collection.immutable.SortedMap
/** Entry point for Config-uring the presence of Tiles */
case class TilesLocated(loc: HierarchicalLocation) extends Field[Seq[CanAttachTile]](Nil)
/** List of HierarchicalLocations which might contain a Tile */
case object PossibleTileLocations extends Field[Seq[HierarchicalLocation]](Nil)
/** For determining static tile id */
case object NumTiles extends Field[Int](0)
/** Whether to add timing-closure registers along the path of the hart id
* as it propagates through the subsystem and into the tile.
*
* These are typically only desirable when a dynamically programmable prefix is being combined
* with the static hart id via [[freechips.rocketchip.subsystem.HasTiles.tileHartIdNexusNode]].
*/
case object InsertTimingClosureRegistersOnHartIds extends Field[Boolean](false)
/** Whether per-tile hart ids are going to be driven as inputs into a HasTiles block,
* and if so, what their width should be.
*/
case object HasTilesExternalHartIdWidthKey extends Field[Option[Int]](None)
/** Whether per-tile reset vectors are going to be driven as inputs into a HasTiles block.
*
* Unlike the hart ids, the reset vector width is determined by the sinks within the tiles,
* based on the size of the address map visible to the tiles.
*/
case object HasTilesExternalResetVectorKey extends Field[Boolean](true)
/** These are sources of "constants" that are driven into the tile.
*
* While they are not expected to change dyanmically while the tile is executing code,
* they may be either tied to a contant value or programmed during boot or reset.
* They need to be instantiated before tiles are attached within the subsystem containing them.
*/
trait HasTileInputConstants { this: LazyModule with Attachable with InstantiatesHierarchicalElements =>
/** tileHartIdNode is used to collect publishers and subscribers of hartids. */
val tileHartIdNodes: SortedMap[Int, BundleBridgeEphemeralNode[UInt]] = (0 until nTotalTiles).map { i =>
(i, BundleBridgeEphemeralNode[UInt]())
}.to(SortedMap)
/** tileHartIdNexusNode is a BundleBridgeNexus that collects dynamic hart prefixes.
*
* Each "prefix" input is actually the same full width as the outer hart id; the expected usage
* is that each prefix source would set only some non-overlapping portion of the bits to non-zero values.
* This node orReduces them, and further combines the reduction with the static ids assigned to each tile,
* producing a unique, dynamic hart id for each tile.
*
* If p(InsertTimingClosureRegistersOnHartIds) is set, the input and output values are registered.
*
* The output values are [[dontTouch]]'d to prevent constant propagation from pulling the values into
* the tiles if they are constant, which would ruin deduplication of tiles that are otherwise homogeneous.
*/
val tileHartIdNexusNode = LazyModule(new BundleBridgeNexus[UInt](
inputFn = BundleBridgeNexus.orReduction[UInt](registered = p(InsertTimingClosureRegistersOnHartIds)) _,
outputFn = (prefix: UInt, n: Int) => Seq.tabulate(n) { i =>
val y = dontTouch(prefix | totalTileIdList(i).U(p(MaxHartIdBits).W)) // dontTouch to keep constant prop from breaking tile dedup
if (p(InsertTimingClosureRegistersOnHartIds)) BundleBridgeNexus.safeRegNext(y) else y
},
default = Some(() => 0.U(p(MaxHartIdBits).W)),
inputRequiresOutput = true, // guard against this being driven but then ignored in tileHartIdIONodes below
shouldBeInlined = false // can't inline something whose output we are are dontTouching
)).node
// TODO: Replace the DebugModuleHartSelFuncs config key with logic to consume the dynamic hart IDs
/** tileResetVectorNode is used to collect publishers and subscribers of tile reset vector addresses. */
val tileResetVectorNodes: SortedMap[Int, BundleBridgeEphemeralNode[UInt]] = (0 until nTotalTiles).map { i =>
(i, BundleBridgeEphemeralNode[UInt]())
}.to(SortedMap)
/** tileResetVectorNexusNode is a BundleBridgeNexus that accepts a single reset vector source, and broadcasts it to all tiles. */
val tileResetVectorNexusNode = BundleBroadcast[UInt](
inputRequiresOutput = true // guard against this being driven but ignored in tileResetVectorIONodes below
)
/** tileHartIdIONodes may generate subsystem IOs, one per tile, allowing the parent to assign unique hart ids.
*
* Or, if such IOs are not configured to exist, tileHartIdNexusNode is used to supply an id to each tile.
*/
val tileHartIdIONodes: Seq[BundleBridgeSource[UInt]] = p(HasTilesExternalHartIdWidthKey) match {
case Some(w) => (0 until nTotalTiles).map { i =>
val hartIdSource = BundleBridgeSource(() => UInt(w.W))
tileHartIdNodes(i) := hartIdSource
hartIdSource
}
case None => {
(0 until nTotalTiles).map { i => tileHartIdNodes(i) :*= tileHartIdNexusNode }
Nil
}
}
/** tileResetVectorIONodes may generate subsystem IOs, one per tile, allowing the parent to assign unique reset vectors.
*
* Or, if such IOs are not configured to exist, tileResetVectorNexusNode is used to supply a single reset vector to every tile.
*/
val tileResetVectorIONodes: Seq[BundleBridgeSource[UInt]] = p(HasTilesExternalResetVectorKey) match {
case true => (0 until nTotalTiles).map { i =>
val resetVectorSource = BundleBridgeSource[UInt]()
tileResetVectorNodes(i) := resetVectorSource
resetVectorSource
}
case false => {
(0 until nTotalTiles).map { i => tileResetVectorNodes(i) :*= tileResetVectorNexusNode }
Nil
}
}
}
/** These are sinks of notifications that are driven out from the tile.
*
* They need to be instantiated before tiles are attached to the subsystem containing them.
*/
trait HasTileNotificationSinks { this: LazyModule =>
val tileHaltXbarNode = IntXbar()
val tileHaltSinkNode = IntSinkNode(IntSinkPortSimple())
tileHaltSinkNode := tileHaltXbarNode
val tileWFIXbarNode = IntXbar()
val tileWFISinkNode = IntSinkNode(IntSinkPortSimple())
tileWFISinkNode := tileWFIXbarNode
val tileCeaseXbarNode = IntXbar()
val tileCeaseSinkNode = IntSinkNode(IntSinkPortSimple())
tileCeaseSinkNode := tileCeaseXbarNode
}
/** Standardized interface by which parameterized tiles can be attached to contexts containing interconnect resources.
*
* Sub-classes of this trait can optionally override the individual connect functions in order to specialize
* their attachment behaviors, but most use cases should be be handled simply by changing the implementation
* of the injectNode functions in crossingParams.
*/
trait CanAttachTile {
type TileType <: BaseTile
type TileContextType <: DefaultHierarchicalElementContextType
def tileParams: InstantiableTileParams[TileType]
def crossingParams: HierarchicalElementCrossingParamsLike
/** Narrow waist through which all tiles are intended to pass while being instantiated. */
def instantiate(allTileParams: Seq[TileParams], instantiatedTiles: SortedMap[Int, TilePRCIDomain[_]])(implicit p: Parameters): TilePRCIDomain[TileType] = {
val clockSinkParams = tileParams.clockSinkParams.copy(name = Some(tileParams.uniqueName))
val tile_prci_domain = LazyModule(new TilePRCIDomain[TileType](clockSinkParams, crossingParams) { self =>
val element = self.element_reset_domain { LazyModule(tileParams.instantiate(crossingParams, PriorityMuxHartIdFromSeq(allTileParams))) }
})
tile_prci_domain
}
/** A default set of connections that need to occur for most tile types */
def connect(domain: TilePRCIDomain[TileType], context: TileContextType): Unit = {
connectMasterPorts(domain, context)
connectSlavePorts(domain, context)
connectInterrupts(domain, context)
connectPRC(domain, context)
connectOutputNotifications(domain, context)
connectInputConstants(domain, context)
connectTrace(domain, context)
}
/** Connect the port where the tile is the master to a TileLink interconnect. */
def connectMasterPorts(domain: TilePRCIDomain[TileType], context: Attachable): Unit = {
implicit val p = context.p
val dataBus = context.locateTLBusWrapper(crossingParams.master.where)
dataBus.coupleFrom(tileParams.baseName) { bus =>
bus :=* crossingParams.master.injectNode(context) :=* domain.crossMasterPort(crossingParams.crossingType)
}
}
/** Connect the port where the tile is the slave to a TileLink interconnect. */
def connectSlavePorts(domain: TilePRCIDomain[TileType], context: Attachable): Unit = {
implicit val p = context.p
DisableMonitors { implicit p =>
val controlBus = context.locateTLBusWrapper(crossingParams.slave.where)
controlBus.coupleTo(tileParams.baseName) { bus =>
domain.crossSlavePort(crossingParams.crossingType) :*= crossingParams.slave.injectNode(context) :*= TLWidthWidget(controlBus.beatBytes) :*= bus
}
}
}
/** Connect the various interrupts sent to and and raised by the tile. */
def connectInterrupts(domain: TilePRCIDomain[TileType], context: TileContextType): Unit = {
implicit val p = context.p
// NOTE: The order of calls to := matters! They must match how interrupts
// are decoded from tile.intInwardNode inside the tile. For this reason,
// we stub out missing interrupts with constant sources here.
// 1. Debug interrupt is definitely asynchronous in all cases.
domain.element.intInwardNode := domain { IntSyncAsyncCrossingSink(3) } :=
context.debugNodes(domain.element.tileId)
// 2. The CLINT and PLIC output interrupts are synchronous to the CLINT/PLIC respectively,
// so might need to be synchronized depending on the Tile's crossing type.
// From CLINT: "msip" and "mtip"
context.msipDomain {
domain.crossIntIn(crossingParams.crossingType, domain.element.intInwardNode) :=
context.msipNodes(domain.element.tileId)
}
// From PLIC: "meip"
context.meipDomain {
domain.crossIntIn(crossingParams.crossingType, domain.element.intInwardNode) :=
context.meipNodes(domain.element.tileId)
}
// From PLIC: "seip" (only if supervisor mode is enabled)
if (domain.element.tileParams.core.hasSupervisorMode) {
context.seipDomain {
domain.crossIntIn(crossingParams.crossingType, domain.element.intInwardNode) :=
context.seipNodes(domain.element.tileId)
}
}
// 3. Local Interrupts ("lip") are required to already be synchronous to the Tile's clock.
// (they are connected to domain.element.intInwardNode in a seperate trait)
// 4. Interrupts coming out of the tile are sent to the PLIC,
// so might need to be synchronized depending on the Tile's crossing type.
context.tileToPlicNodes.get(domain.element.tileId).foreach { node =>
FlipRendering { implicit p => domain.element.intOutwardNode.foreach { out =>
context.toPlicDomain { node := domain.crossIntOut(crossingParams.crossingType, out) }
}}
}
// 5. Connect NMI inputs to the tile. These inputs are synchronous to the respective core_clock.
domain.element.nmiNode.foreach(_ := context.nmiNodes(domain.element.tileId))
}
/** Notifications of tile status are connected to be broadcast without needing to be clock-crossed. */
def connectOutputNotifications(domain: TilePRCIDomain[TileType], context: TileContextType): Unit = {
implicit val p = context.p
domain {
context.tileHaltXbarNode :=* domain.crossIntOut(NoCrossing, domain.element.haltNode)
context.tileWFIXbarNode :=* domain.crossIntOut(NoCrossing, domain.element.wfiNode)
context.tileCeaseXbarNode :=* domain.crossIntOut(NoCrossing, domain.element.ceaseNode)
}
// TODO should context be forced to have a trace sink connected here?
// for now this just ensures domain.trace[Core]Node has been crossed without connecting it externally
}
/** Connect inputs to the tile that are assumed to be constant during normal operation, and so are not clock-crossed. */
def connectInputConstants(domain: TilePRCIDomain[TileType], context: TileContextType): Unit = {
implicit val p = context.p
val tlBusToGetPrefixFrom = context.locateTLBusWrapper(crossingParams.mmioBaseAddressPrefixWhere)
domain.element.hartIdNode := context.tileHartIdNodes(domain.element.tileId)
domain.element.resetVectorNode := context.tileResetVectorNodes(domain.element.tileId)
tlBusToGetPrefixFrom.prefixNode.foreach { domain.element.mmioAddressPrefixNode := _ }
}
/** Connect power/reset/clock resources. */
def connectPRC(domain: TilePRCIDomain[TileType], context: TileContextType): Unit = {
implicit val p = context.p
val tlBusToGetClockDriverFrom = context.locateTLBusWrapper(crossingParams.master.where)
(crossingParams.crossingType match {
case _: SynchronousCrossing | _: CreditedCrossing =>
if (crossingParams.forceSeparateClockReset) {
domain.clockNode := tlBusToGetClockDriverFrom.clockNode
} else {
domain.clockNode := tlBusToGetClockDriverFrom.fixedClockNode
}
case _: RationalCrossing => domain.clockNode := tlBusToGetClockDriverFrom.clockNode
case _: AsynchronousCrossing => {
val tileClockGroup = ClockGroup()
tileClockGroup := context.allClockGroupsNode
domain.clockNode := tileClockGroup
}
})
domain {
domain.element_reset_domain.clockNode := crossingParams.resetCrossingType.injectClockNode := domain.clockNode
}
}
/** Function to handle all trace crossings when tile is instantiated inside domains */
def connectTrace(domain: TilePRCIDomain[TileType], context: TileContextType): Unit = {
implicit val p = context.p
val traceCrossingNode = BundleBridgeBlockDuringReset[TraceBundle](
resetCrossingType = crossingParams.resetCrossingType)
context.traceNodes(domain.element.tileId) := traceCrossingNode := domain.element.traceNode
val traceCoreCrossingNode = BundleBridgeBlockDuringReset[TraceCoreInterface](
resetCrossingType = crossingParams.resetCrossingType)
context.traceCoreNodes(domain.element.tileId) :*= traceCoreCrossingNode := domain.element.traceCoreNode
}
}
case class CloneTileAttachParams(
sourceTileId: Int,
cloneParams: CanAttachTile
) extends CanAttachTile {
type TileType = cloneParams.TileType
type TileContextType = cloneParams.TileContextType
def tileParams = cloneParams.tileParams
def crossingParams = cloneParams.crossingParams
override def instantiate(allTileParams: Seq[TileParams], instantiatedTiles: SortedMap[Int, TilePRCIDomain[_]])(implicit p: Parameters): TilePRCIDomain[TileType] = {
require(instantiatedTiles.contains(sourceTileId))
val clockSinkParams = tileParams.clockSinkParams.copy(name = Some(tileParams.uniqueName))
val tile_prci_domain = CloneLazyModule(
new TilePRCIDomain[TileType](clockSinkParams, crossingParams) { self =>
val element = self.element_reset_domain { LazyModule(tileParams.instantiate(crossingParams, PriorityMuxHartIdFromSeq(allTileParams))) }
},
instantiatedTiles(sourceTileId).asInstanceOf[TilePRCIDomain[TileType]]
)
tile_prci_domain
}
}
File ClockGroup.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.prci
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import org.chipsalliance.diplomacy.lazymodule._
import org.chipsalliance.diplomacy.nodes._
import freechips.rocketchip.resources.FixedClockResource
case class ClockGroupingNode(groupName: String)(implicit valName: ValName)
extends MixedNexusNode(ClockGroupImp, ClockImp)(
dFn = { _ => ClockSourceParameters() },
uFn = { seq => ClockGroupSinkParameters(name = groupName, members = seq) })
{
override def circuitIdentity = outputs.size == 1
}
class ClockGroup(groupName: String)(implicit p: Parameters) extends LazyModule
{
val node = ClockGroupingNode(groupName)
lazy val module = new Impl
class Impl extends LazyRawModuleImp(this) {
val (in, _) = node.in(0)
val (out, _) = node.out.unzip
require (node.in.size == 1)
require (in.member.size == out.size)
(in.member.data zip out) foreach { case (i, o) => o := i }
}
}
object ClockGroup
{
def apply()(implicit p: Parameters, valName: ValName) = LazyModule(new ClockGroup(valName.name)).node
}
case class ClockGroupAggregateNode(groupName: String)(implicit valName: ValName)
extends NexusNode(ClockGroupImp)(
dFn = { _ => ClockGroupSourceParameters() },
uFn = { seq => ClockGroupSinkParameters(name = groupName, members = seq.flatMap(_.members))})
{
override def circuitIdentity = outputs.size == 1
}
class ClockGroupAggregator(groupName: String)(implicit p: Parameters) extends LazyModule
{
val node = ClockGroupAggregateNode(groupName)
override lazy val desiredName = s"ClockGroupAggregator_$groupName"
lazy val module = new Impl
class Impl extends LazyRawModuleImp(this) {
val (in, _) = node.in.unzip
val (out, _) = node.out.unzip
val outputs = out.flatMap(_.member.data)
require (node.in.size == 1, s"Aggregator for groupName: ${groupName} had ${node.in.size} inward edges instead of 1")
require (in.head.member.size == outputs.size)
in.head.member.data.zip(outputs).foreach { case (i, o) => o := i }
}
}
object ClockGroupAggregator
{
def apply()(implicit p: Parameters, valName: ValName) = LazyModule(new ClockGroupAggregator(valName.name)).node
}
class SimpleClockGroupSource(numSources: Int = 1)(implicit p: Parameters) extends LazyModule
{
val node = ClockGroupSourceNode(List.fill(numSources) { ClockGroupSourceParameters() })
lazy val module = new Impl
class Impl extends LazyModuleImp(this) {
val (out, _) = node.out.unzip
out.map { out: ClockGroupBundle =>
out.member.data.foreach { o =>
o.clock := clock; o.reset := reset }
}
}
}
object SimpleClockGroupSource
{
def apply(num: Int = 1)(implicit p: Parameters, valName: ValName) = LazyModule(new SimpleClockGroupSource(num)).node
}
case class FixedClockBroadcastNode(fixedClockOpt: Option[ClockParameters])(implicit valName: ValName)
extends NexusNode(ClockImp)(
dFn = { seq => fixedClockOpt.map(_ => ClockSourceParameters(give = fixedClockOpt)).orElse(seq.headOption).getOrElse(ClockSourceParameters()) },
uFn = { seq => fixedClockOpt.map(_ => ClockSinkParameters(take = fixedClockOpt)).orElse(seq.headOption).getOrElse(ClockSinkParameters()) },
inputRequiresOutput = false) {
def fixedClockResources(name: String, prefix: String = "soc/"): Seq[Option[FixedClockResource]] = Seq(fixedClockOpt.map(t => new FixedClockResource(name, t.freqMHz, prefix)))
}
class FixedClockBroadcast(fixedClockOpt: Option[ClockParameters])(implicit p: Parameters) extends LazyModule
{
val node = new FixedClockBroadcastNode(fixedClockOpt) {
override def circuitIdentity = outputs.size == 1
}
lazy val module = new Impl
class Impl extends LazyRawModuleImp(this) {
val (in, _) = node.in(0)
val (out, _) = node.out.unzip
override def desiredName = s"FixedClockBroadcast_${out.size}"
require (node.in.size == 1, "FixedClockBroadcast can only broadcast a single clock")
out.foreach { _ := in }
}
}
object FixedClockBroadcast
{
def apply(fixedClockOpt: Option[ClockParameters] = None)(implicit p: Parameters, valName: ValName) = LazyModule(new FixedClockBroadcast(fixedClockOpt)).node
}
case class PRCIClockGroupNode()(implicit valName: ValName)
extends NexusNode(ClockGroupImp)(
dFn = { _ => ClockGroupSourceParameters() },
uFn = { _ => ClockGroupSinkParameters("prci", Nil) },
outputRequiresInput = false)
File LazyModuleImp.scala:
package org.chipsalliance.diplomacy.lazymodule
import chisel3.{withClockAndReset, Module, RawModule, Reset, _}
import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo}
import firrtl.passes.InlineAnnotation
import org.chipsalliance.cde.config.Parameters
import org.chipsalliance.diplomacy.nodes.Dangle
import scala.collection.immutable.SortedMap
/** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]].
*
* This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy.
*/
sealed trait LazyModuleImpLike extends RawModule {
/** [[LazyModule]] that contains this instance. */
val wrapper: LazyModule
/** IOs that will be automatically "punched" for this instance. */
val auto: AutoBundle
/** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */
protected[diplomacy] val dangles: Seq[Dangle]
// [[wrapper.module]] had better not be accessed while LazyModules are still being built!
require(
LazyModule.scope.isEmpty,
s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}"
)
/** Set module name. Defaults to the containing LazyModule's desiredName. */
override def desiredName: String = wrapper.desiredName
suggestName(wrapper.suggestedName)
/** [[Parameters]] for chisel [[Module]]s. */
implicit val p: Parameters = wrapper.p
/** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and
* submodules.
*/
protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = {
// 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]],
// 2. return [[Dangle]]s from each module.
val childDangles = wrapper.children.reverse.flatMap { c =>
implicit val sourceInfo: SourceInfo = c.info
c.cloneProto.map { cp =>
// If the child is a clone, then recursively set cloneProto of its children as well
def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = {
require(bases.size == clones.size)
(bases.zip(clones)).map { case (l, r) =>
require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}")
l.cloneProto = Some(r)
assignCloneProtos(l.children, r.children)
}
}
assignCloneProtos(c.children, cp.children)
// Clone the child module as a record, and get its [[AutoBundle]]
val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName)
val clonedAuto = clone("auto").asInstanceOf[AutoBundle]
// Get the empty [[Dangle]]'s of the cloned child
val rawDangles = c.cloneDangles()
require(rawDangles.size == clonedAuto.elements.size)
// Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s
val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) }
dangles
}.getOrElse {
// For non-clones, instantiate the child module
val mod = try {
Module(c.module)
} catch {
case e: ChiselException => {
println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}")
throw e
}
}
mod.dangles
}
}
// Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]].
// This will result in a sequence of [[Dangle]] from these [[BaseNode]]s.
val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate())
// Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]]
val allDangles = nodeDangles ++ childDangles
// Group [[allDangles]] by their [[source]].
val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*)
// For each [[source]] set of [[Dangle]]s of size 2, ensure that these
// can be connected as a source-sink pair (have opposite flipped value).
// Make the connection and mark them as [[done]].
val done = Set() ++ pairing.values.filter(_.size == 2).map {
case Seq(a, b) =>
require(a.flipped != b.flipped)
// @todo <> in chisel3 makes directionless connection.
if (a.flipped) {
a.data <> b.data
} else {
b.data <> a.data
}
a.source
case _ => None
}
// Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module.
val forward = allDangles.filter(d => !done(d.source))
// Generate [[AutoBundle]] IO from [[forward]].
val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*))
// Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]]
val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) =>
if (d.flipped) {
d.data <> io
} else {
io <> d.data
}
d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name)
}
// Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]].
wrapper.inModuleBody.reverse.foreach {
_()
}
if (wrapper.shouldBeInlined) {
chisel3.experimental.annotate(new ChiselAnnotation {
def toFirrtl = InlineAnnotation(toNamed)
})
}
// Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]].
(auto, dangles)
}
}
/** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike {
/** Instantiate hardware of this `Module`. */
val (auto, dangles) = instantiate()
}
/** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike {
// These wires are the default clock+reset for all LazyModule children.
// It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the
// [[LazyRawModuleImp]] children.
// Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly.
/** drive clock explicitly. */
val childClock: Clock = Wire(Clock())
/** drive reset explicitly. */
val childReset: Reset = Wire(Reset())
// the default is that these are disabled
childClock := false.B.asClock
childReset := chisel3.DontCare
def provideImplicitClockToLazyChildren: Boolean = false
val (auto, dangles) =
if (provideImplicitClockToLazyChildren) {
withClockAndReset(childClock, childReset) { instantiate() }
} else {
instantiate()
}
}
File MixedNode.scala:
package org.chipsalliance.diplomacy.nodes
import chisel3.{Data, DontCare, Wire}
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.{Field, Parameters}
import org.chipsalliance.diplomacy.ValName
import org.chipsalliance.diplomacy.sourceLine
/** One side metadata of a [[Dangle]].
*
* Describes one side of an edge going into or out of a [[BaseNode]].
*
* @param serial
* the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to.
* @param index
* the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to.
*/
case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] {
import scala.math.Ordered.orderingToOrdered
def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that))
}
/** [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]]
* connects.
*
* [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] ,
* [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]].
*
* @param source
* the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within
* that [[BaseNode]].
* @param sink
* sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that
* [[BaseNode]].
* @param flipped
* flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to
* `danglesIn`.
* @param dataOpt
* actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module
*/
case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) {
def data = dataOpt.get
}
/** [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often
* derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually
* implement the protocol.
*/
case class Edges[EI, EO](in: Seq[EI], out: Seq[EO])
/** A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. */
case object MonitorsEnabled extends Field[Boolean](true)
/** When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented.
*
* For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but
* [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink
* nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the
* [[LazyModule]].
*/
case object RenderFlipped extends Field[Boolean](false)
/** The sealed node class in the package, all node are derived from it.
*
* @param inner
* Sink interface implementation.
* @param outer
* Source interface implementation.
* @param valName
* val name of this node.
* @tparam DI
* Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters
* describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected
* [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port
* parameters.
* @tparam UI
* Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing
* the protocol parameters of a sink. For an [[InwardNode]], it is determined itself.
* @tparam EI
* Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers
* specified for a sink according to protocol.
* @tparam BI
* Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface.
* It should extends from [[chisel3.Data]], which represents the real hardware.
* @tparam DO
* Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters
* describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself.
* @tparam UO
* Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing
* the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]].
* Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters.
* @tparam EO
* Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers
* specified for a source according to protocol.
* @tparam BO
* Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source
* interface. It should extends from [[chisel3.Data]], which represents the real hardware.
*
* @note
* Call Graph of [[MixedNode]]
* - line `─`: source is process by a function and generate pass to others
* - Arrow `→`: target of arrow is generated by source
*
* {{{
* (from the other node)
* ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐
* ↓ │
* (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │
* [[InwardNode.accPI]] │ │ │
* │ │ (based on protocol) │
* │ │ [[MixedNode.inner.edgeI]] │
* │ │ ↓ │
* ↓ │ │ │
* (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │
* [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │
* │ │ ↑ │ │ │
* │ │ │ [[OutwardNode.doParams]] │ │
* │ │ │ (from the other node) │ │
* │ │ │ │ │ │
* │ │ │ │ │ │
* │ │ │ └────────┬──────────────┤ │
* │ │ │ │ │ │
* │ │ │ │ (based on protocol) │
* │ │ │ │ [[MixedNode.inner.edgeI]] │
* │ │ │ │ │ │
* │ │ (from the other node) │ ↓ │
* │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │
* │ ↑ ↑ │ │ ↓ │
* │ │ │ │ │ [[MixedNode.in]] │
* │ │ │ │ ↓ ↑ │
* │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │
* ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │
* │ │ │ [[MixedNode.bundleOut]]─┐ │ │
* │ │ │ ↑ ↓ │ │
* │ │ │ │ [[MixedNode.out]] │ │
* │ ↓ ↓ │ ↑ │ │
* │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │
* │ │ (from the other node) ↑ │ │
* │ │ │ │ │ │
* │ │ │ [[MixedNode.outer.edgeO]] │ │
* │ │ │ (based on protocol) │ │
* │ │ │ │ │ │
* │ │ │ ┌────────────────────────────────────────┤ │ │
* │ │ │ │ │ │ │
* │ │ │ │ │ │ │
* │ │ │ │ │ │ │
* (immobilize after elaboration)│ ↓ │ │ │ │
* [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │
* ↑ (inward port from [[OutwardNode]]) │ │ │ │
* │ ┌─────────────────────────────────────────┤ │ │ │
* │ │ │ │ │ │
* │ │ │ │ │ │
* [[OutwardNode.accPO]] │ ↓ │ │ │
* (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │
* │ ↑ │ │
* │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │
* └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘
* }}}
*/
abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data](
val inner: InwardNodeImp[DI, UI, EI, BI],
val outer: OutwardNodeImp[DO, UO, EO, BO]
)(
implicit valName: ValName)
extends BaseNode
with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO]
with InwardNode[DI, UI, BI]
with OutwardNode[DO, UO, BO] {
// Generate a [[NodeHandle]] with inward and outward node are both this node.
val inward = this
val outward = this
/** Debug info of nodes binding. */
def bindingInfo: String = s"""$iBindingInfo
|$oBindingInfo
|""".stripMargin
/** Debug info of ports connecting. */
def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}]
|${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}]
|""".stripMargin
/** Debug info of parameters propagations. */
def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}]
|${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}]
|${diParams.size} downstream inward parameters: [${diParams.mkString(",")}]
|${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}]
|""".stripMargin
/** For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and
* [[MixedNode.iPortMapping]].
*
* Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward
* stars and outward stars.
*
* This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type
* of node.
*
* @param iKnown
* Number of known-size ([[BIND_ONCE]]) input bindings.
* @param oKnown
* Number of known-size ([[BIND_ONCE]]) output bindings.
* @param iStar
* Number of unknown size ([[BIND_STAR]]) input bindings.
* @param oStar
* Number of unknown size ([[BIND_STAR]]) output bindings.
* @return
* A Tuple of the resolved number of input and output connections.
*/
protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int)
/** Function to generate downward-flowing outward params from the downward-flowing input params and the current output
* ports.
*
* @param n
* The size of the output sequence to generate.
* @param p
* Sequence of downward-flowing input parameters of this node.
* @return
* A `n`-sized sequence of downward-flowing output edge parameters.
*/
protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO]
/** Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]].
*
* @param n
* Size of the output sequence.
* @param p
* Upward-flowing output edge parameters.
* @return
* A n-sized sequence of upward-flowing input edge parameters.
*/
protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI]
/** @return
* The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with
* [[BIND_STAR]].
*/
protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR)
/** @return
* The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of
* output bindings bound with [[BIND_STAR]].
*/
protected[diplomacy] lazy val sourceCard: Int =
iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR)
/** @return list of nodes involved in flex bindings with this node. */
protected[diplomacy] lazy val flexes: Seq[BaseNode] =
oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2)
/** Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin
* greedily taking up the remaining connections.
*
* @return
* A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return
* value is not relevant.
*/
protected[diplomacy] lazy val flexOffset: Int = {
/** Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex
* operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a
* connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of
* each node in the current set and decide whether they should be added to the set or not.
*
* @return
* the mapping of [[BaseNode]] indexed by their serial numbers.
*/
def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = {
if (visited.contains(v.serial) || !v.flexibleArityDirection) {
visited
} else {
v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum))
}
}
/** Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node.
*
* @example
* {{{
* a :*=* b :*=* c
* d :*=* b
* e :*=* f
* }}}
*
* `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)`
*/
val flexSet = DFS(this, Map()).values
/** The total number of :*= operators where we're on the left. */
val allSink = flexSet.map(_.sinkCard).sum
/** The total number of :=* operators used when we're on the right. */
val allSource = flexSet.map(_.sourceCard).sum
require(
allSink == 0 || allSource == 0,
s"The nodes ${flexSet.map(_.name)} which are inter-connected by :*=* have ${allSink} :*= operators and ${allSource} :=* operators connected to them, making it impossible to determine cardinality inference direction."
)
allSink - allSource
}
/** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. */
protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = {
if (flexibleArityDirection) flexOffset
else if (n.flexibleArityDirection) n.flexOffset
else 0
}
/** For a node which is connected between two nodes, select the one that will influence the direction of the flex
* resolution.
*/
protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = {
val dir = edgeArityDirection(n)
if (dir < 0) l
else if (dir > 0) r
else 1
}
/** Ensure that the same node is not visited twice in resolving `:*=`, etc operators. */
private var starCycleGuard = false
/** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star"
* connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also
* need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct
* edge parameters and later build up correct bundle connections.
*
* [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding
* operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort
* (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N :*= foo` or `N :*=* foo :*=
* bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo :*=* N`
*/
protected[diplomacy] lazy val (
oPortMapping: Seq[(Int, Int)],
iPortMapping: Seq[(Int, Int)],
oStar: Int,
iStar: Int
) = {
try {
if (starCycleGuard) throw StarCycleException()
starCycleGuard = true
// For a given node N...
// Number of foo :=* N
// + Number of bar :=* foo :*=* N
val oStars = oBindings.count { case (_, n, b, _, _) =>
b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) < 0)
}
// Number of N :*= foo
// + Number of N :*=* foo :*= bar
val iStars = iBindings.count { case (_, n, b, _, _) =>
b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) > 0)
}
// 1 for foo := N
// + bar.iStar for bar :*= foo :*=* N
// + foo.iStar for foo :*= N
// + 0 for foo :=* N
val oKnown = oBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, 0, n.iStar)
case BIND_QUERY => n.iStar
case BIND_STAR => 0
}
}.sum
// 1 for N := foo
// + bar.oStar for N :*=* foo :=* bar
// + foo.oStar for N :=* foo
// + 0 for N :*= foo
val iKnown = iBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, n.oStar, 0)
case BIND_QUERY => n.oStar
case BIND_STAR => 0
}
}.sum
// Resolve star depends on the node subclass to implement the algorithm for this.
val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars)
// Cumulative list of resolved outward binding range starting points
val oSum = oBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar)
case BIND_QUERY => n.iStar
case BIND_STAR => oStar
}
}.scanLeft(0)(_ + _)
// Cumulative list of resolved inward binding range starting points
val iSum = iBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar)
case BIND_QUERY => n.oStar
case BIND_STAR => iStar
}
}.scanLeft(0)(_ + _)
// Create ranges for each binding based on the running sums and return
// those along with resolved values for the star operations.
(oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar)
} catch {
case c: StarCycleException => throw c.copy(loop = context +: c.loop)
}
}
/** Sequence of inward ports.
*
* This should be called after all star bindings are resolved.
*
* Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding.
* `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this
* connection was made in the source code.
*/
protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] =
oBindings.flatMap { case (i, n, _, p, s) =>
// for each binding operator in this node, look at what it connects to
val (start, end) = n.iPortMapping(i)
(start until end).map { j => (j, n, p, s) }
}
/** Sequence of outward ports.
*
* This should be called after all star bindings are resolved.
*
* `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of
* outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection
* was made in the source code.
*/
protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] =
iBindings.flatMap { case (i, n, _, p, s) =>
// query this port index range of this node in the other side of node.
val (start, end) = n.oPortMapping(i)
(start until end).map { j => (j, n, p, s) }
}
// Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree
// Thus, there must exist an Eulerian path and the below algorithms terminate
@scala.annotation.tailrec
private def oTrace(
tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)
): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match {
case (i, n, p, s) => n.iForward(i) match {
case None => (i, n, p, s)
case Some((j, m)) => oTrace((j, m, p, s))
}
}
@scala.annotation.tailrec
private def iTrace(
tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)
): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match {
case (i, n, p, s) => n.oForward(i) match {
case None => (i, n, p, s)
case Some((j, m)) => iTrace((j, m, p, s))
}
}
/** Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved.
*
* Each Port is a tuple of:
* - Numeric index of this binding in the [[InwardNode]] on the other end.
* - [[InwardNode]] on the other end of this binding.
* - A view of [[Parameters]] where the binding occurred.
* - [[SourceInfo]] for source-level error reporting.
*/
lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace)
/** Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved.
*
* Each Port is a tuple of:
* - numeric index of this binding in [[OutwardNode]] on the other end.
* - [[OutwardNode]] on the other end of this binding.
* - a view of [[Parameters]] where the binding occurred.
* - [[SourceInfo]] for source-level error reporting.
*/
lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace)
private var oParamsCycleGuard = false
protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) }
protected[diplomacy] lazy val doParams: Seq[DO] = {
try {
if (oParamsCycleGuard) throw DownwardCycleException()
oParamsCycleGuard = true
val o = mapParamsD(oPorts.size, diParams)
require(
o.size == oPorts.size,
s"""Diplomacy has detected a problem with your graph:
|At the following node, the number of outward ports should equal the number of produced outward parameters.
|$context
|$connectedPortsInfo
|Downstreamed inward parameters: [${diParams.mkString(",")}]
|Produced outward parameters: [${o.mkString(",")}]
|""".stripMargin
)
o.map(outer.mixO(_, this))
} catch {
case c: DownwardCycleException => throw c.copy(loop = context +: c.loop)
}
}
private var iParamsCycleGuard = false
protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) }
protected[diplomacy] lazy val uiParams: Seq[UI] = {
try {
if (iParamsCycleGuard) throw UpwardCycleException()
iParamsCycleGuard = true
val i = mapParamsU(iPorts.size, uoParams)
require(
i.size == iPorts.size,
s"""Diplomacy has detected a problem with your graph:
|At the following node, the number of inward ports should equal the number of produced inward parameters.
|$context
|$connectedPortsInfo
|Upstreamed outward parameters: [${uoParams.mkString(",")}]
|Produced inward parameters: [${i.mkString(",")}]
|""".stripMargin
)
i.map(inner.mixI(_, this))
} catch {
case c: UpwardCycleException => throw c.copy(loop = context +: c.loop)
}
}
/** Outward edge parameters. */
protected[diplomacy] lazy val edgesOut: Seq[EO] =
(oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) }
/** Inward edge parameters. */
protected[diplomacy] lazy val edgesIn: Seq[EI] =
(iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) }
/** A tuple of the input edge parameters and output edge parameters for the edges bound to this node.
*
* If you need to access to the edges of a foreign Node, use this method (in/out create bundles).
*/
lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut)
/** Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. */
protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e =>
val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out")
// TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue,
// In the future, we should add an option to decide whether allowing unconnected in the LazyModule
x := DontCare
x
}
/** Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. */
protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e =>
val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In")
// TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue,
// In the future, we should add an option to decide whether allowing unconnected in the LazyModule
x := DontCare
x
}
private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) =>
Dangle(
source = HalfEdge(serial, i),
sink = HalfEdge(n.serial, j),
flipped = false,
name = wirePrefix + "out",
dataOpt = None
)
}
private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) =>
Dangle(
source = HalfEdge(n.serial, j),
sink = HalfEdge(serial, i),
flipped = true,
name = wirePrefix + "in",
dataOpt = None
)
}
/** Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. */
protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) =>
d.copy(dataOpt = Some(bundleOut(i)))
}
/** Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. */
protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) =>
d.copy(dataOpt = Some(bundleIn(i)))
}
private[diplomacy] var instantiated = false
/** Gather Bundle and edge parameters of outward ports.
*
* Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within
* [[LazyModuleImp]] code or after its instantiation has completed.
*/
def out: Seq[(BO, EO)] = {
require(
instantiated,
s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun"
)
bundleOut.zip(edgesOut)
}
/** Gather Bundle and edge parameters of inward ports.
*
* Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within
* [[LazyModuleImp]] code or after its instantiation has completed.
*/
def in: Seq[(BI, EI)] = {
require(
instantiated,
s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun"
)
bundleIn.zip(edgesIn)
}
/** Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires,
* instantiate monitors on all input ports if appropriate, and return all the dangles of this node.
*/
protected[diplomacy] def instantiate(): Seq[Dangle] = {
instantiated = true
if (!circuitIdentity) {
(iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) }
}
danglesOut ++ danglesIn
}
protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn
/** Connects the outward part of a node with the inward part of this node. */
protected[diplomacy] def bind(
h: OutwardNode[DI, UI, BI],
binding: NodeBinding
)(
implicit p: Parameters,
sourceInfo: SourceInfo
): Unit = {
val x = this // x := y
val y = h
sourceLine(sourceInfo, " at ", "")
val i = x.iPushed
val o = y.oPushed
y.oPush(
i,
x,
binding match {
case BIND_ONCE => BIND_ONCE
case BIND_FLEX => BIND_FLEX
case BIND_STAR => BIND_QUERY
case BIND_QUERY => BIND_STAR
}
)
x.iPush(o, y, binding)
}
/* Metadata for printing the node graph. */
def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) =>
val re = inner.render(e)
(n, re.copy(flipped = re.flipped != p(RenderFlipped)))
}
/** Metadata for printing the node graph */
def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) }
}
| module TilePRCIDomain_4( // @[ClockDomain.scala:14:9]
output auto_intsink_out_1_0, // @[LazyModuleImp.scala:107:25]
input auto_intsink_in_sync_0, // @[LazyModuleImp.scala:107:25]
output auto_element_reset_domain_rockettile_trace_source_out_insns_0_valid, // @[LazyModuleImp.scala:107:25]
output [39:0] auto_element_reset_domain_rockettile_trace_source_out_insns_0_iaddr, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_element_reset_domain_rockettile_trace_source_out_insns_0_insn, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_element_reset_domain_rockettile_trace_source_out_insns_0_priv, // @[LazyModuleImp.scala:107:25]
output auto_element_reset_domain_rockettile_trace_source_out_insns_0_exception, // @[LazyModuleImp.scala:107:25]
output auto_element_reset_domain_rockettile_trace_source_out_insns_0_interrupt, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_element_reset_domain_rockettile_trace_source_out_insns_0_cause, // @[LazyModuleImp.scala:107:25]
output [39:0] auto_element_reset_domain_rockettile_trace_source_out_insns_0_tval, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_element_reset_domain_rockettile_trace_source_out_time, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_element_reset_domain_rockettile_hartid_in, // @[LazyModuleImp.scala:107:25]
input auto_int_in_clock_xing_in_2_sync_0, // @[LazyModuleImp.scala:107:25]
input auto_int_in_clock_xing_in_1_sync_0, // @[LazyModuleImp.scala:107:25]
input auto_int_in_clock_xing_in_0_sync_0, // @[LazyModuleImp.scala:107:25]
input auto_int_in_clock_xing_in_0_sync_1, // @[LazyModuleImp.scala:107:25]
input auto_tl_master_clock_xing_out_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_tl_master_clock_xing_out_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_tl_master_clock_xing_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_tl_master_clock_xing_out_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_tl_master_clock_xing_out_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_tl_master_clock_xing_out_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_tl_master_clock_xing_out_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_tl_master_clock_xing_out_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_tl_master_clock_xing_out_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_tl_master_clock_xing_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_tl_master_clock_xing_out_b_ready, // @[LazyModuleImp.scala:107:25]
input auto_tl_master_clock_xing_out_b_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_tl_master_clock_xing_out_b_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_tl_master_clock_xing_out_b_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_tl_master_clock_xing_out_b_bits_size, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_tl_master_clock_xing_out_b_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_tl_master_clock_xing_out_b_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_tl_master_clock_xing_out_b_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_tl_master_clock_xing_out_b_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_tl_master_clock_xing_out_b_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_tl_master_clock_xing_out_c_ready, // @[LazyModuleImp.scala:107:25]
output auto_tl_master_clock_xing_out_c_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_tl_master_clock_xing_out_c_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_tl_master_clock_xing_out_c_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_tl_master_clock_xing_out_c_bits_size, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_tl_master_clock_xing_out_c_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_tl_master_clock_xing_out_c_bits_address, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_tl_master_clock_xing_out_c_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_tl_master_clock_xing_out_c_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_tl_master_clock_xing_out_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_tl_master_clock_xing_out_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_tl_master_clock_xing_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_tl_master_clock_xing_out_d_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_tl_master_clock_xing_out_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_tl_master_clock_xing_out_d_bits_source, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_tl_master_clock_xing_out_d_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_tl_master_clock_xing_out_d_bits_denied, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_tl_master_clock_xing_out_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_tl_master_clock_xing_out_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_tl_master_clock_xing_out_e_ready, // @[LazyModuleImp.scala:107:25]
output auto_tl_master_clock_xing_out_e_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_tl_master_clock_xing_out_e_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_tap_clock_in_clock, // @[LazyModuleImp.scala:107:25]
input auto_tap_clock_in_reset // @[LazyModuleImp.scala:107:25]
);
wire clockNode_auto_anon_in_reset; // @[ClockGroup.scala:104:9]
wire clockNode_auto_anon_in_clock; // @[ClockGroup.scala:104:9]
wire element_reset_domain_auto_clock_in_reset; // @[ClockDomain.scala:14:9]
wire element_reset_domain_auto_clock_in_clock; // @[ClockDomain.scala:14:9]
wire auto_intsink_in_sync_0_0 = auto_intsink_in_sync_0; // @[ClockDomain.scala:14:9]
wire [2:0] auto_element_reset_domain_rockettile_hartid_in_0 = auto_element_reset_domain_rockettile_hartid_in; // @[ClockDomain.scala:14:9]
wire auto_int_in_clock_xing_in_2_sync_0_0 = auto_int_in_clock_xing_in_2_sync_0; // @[ClockDomain.scala:14:9]
wire auto_int_in_clock_xing_in_1_sync_0_0 = auto_int_in_clock_xing_in_1_sync_0; // @[ClockDomain.scala:14:9]
wire auto_int_in_clock_xing_in_0_sync_0_0 = auto_int_in_clock_xing_in_0_sync_0; // @[ClockDomain.scala:14:9]
wire auto_int_in_clock_xing_in_0_sync_1_0 = auto_int_in_clock_xing_in_0_sync_1; // @[ClockDomain.scala:14:9]
wire auto_tl_master_clock_xing_out_a_ready_0 = auto_tl_master_clock_xing_out_a_ready; // @[ClockDomain.scala:14:9]
wire auto_tl_master_clock_xing_out_b_valid_0 = auto_tl_master_clock_xing_out_b_valid; // @[ClockDomain.scala:14:9]
wire [2:0] auto_tl_master_clock_xing_out_b_bits_opcode_0 = auto_tl_master_clock_xing_out_b_bits_opcode; // @[ClockDomain.scala:14:9]
wire [1:0] auto_tl_master_clock_xing_out_b_bits_param_0 = auto_tl_master_clock_xing_out_b_bits_param; // @[ClockDomain.scala:14:9]
wire [3:0] auto_tl_master_clock_xing_out_b_bits_size_0 = auto_tl_master_clock_xing_out_b_bits_size; // @[ClockDomain.scala:14:9]
wire [1:0] auto_tl_master_clock_xing_out_b_bits_source_0 = auto_tl_master_clock_xing_out_b_bits_source; // @[ClockDomain.scala:14:9]
wire [31:0] auto_tl_master_clock_xing_out_b_bits_address_0 = auto_tl_master_clock_xing_out_b_bits_address; // @[ClockDomain.scala:14:9]
wire [7:0] auto_tl_master_clock_xing_out_b_bits_mask_0 = auto_tl_master_clock_xing_out_b_bits_mask; // @[ClockDomain.scala:14:9]
wire [63:0] auto_tl_master_clock_xing_out_b_bits_data_0 = auto_tl_master_clock_xing_out_b_bits_data; // @[ClockDomain.scala:14:9]
wire auto_tl_master_clock_xing_out_b_bits_corrupt_0 = auto_tl_master_clock_xing_out_b_bits_corrupt; // @[ClockDomain.scala:14:9]
wire auto_tl_master_clock_xing_out_c_ready_0 = auto_tl_master_clock_xing_out_c_ready; // @[ClockDomain.scala:14:9]
wire auto_tl_master_clock_xing_out_d_valid_0 = auto_tl_master_clock_xing_out_d_valid; // @[ClockDomain.scala:14:9]
wire [2:0] auto_tl_master_clock_xing_out_d_bits_opcode_0 = auto_tl_master_clock_xing_out_d_bits_opcode; // @[ClockDomain.scala:14:9]
wire [1:0] auto_tl_master_clock_xing_out_d_bits_param_0 = auto_tl_master_clock_xing_out_d_bits_param; // @[ClockDomain.scala:14:9]
wire [3:0] auto_tl_master_clock_xing_out_d_bits_size_0 = auto_tl_master_clock_xing_out_d_bits_size; // @[ClockDomain.scala:14:9]
wire [1:0] auto_tl_master_clock_xing_out_d_bits_source_0 = auto_tl_master_clock_xing_out_d_bits_source; // @[ClockDomain.scala:14:9]
wire [2:0] auto_tl_master_clock_xing_out_d_bits_sink_0 = auto_tl_master_clock_xing_out_d_bits_sink; // @[ClockDomain.scala:14:9]
wire auto_tl_master_clock_xing_out_d_bits_denied_0 = auto_tl_master_clock_xing_out_d_bits_denied; // @[ClockDomain.scala:14:9]
wire [63:0] auto_tl_master_clock_xing_out_d_bits_data_0 = auto_tl_master_clock_xing_out_d_bits_data; // @[ClockDomain.scala:14:9]
wire auto_tl_master_clock_xing_out_d_bits_corrupt_0 = auto_tl_master_clock_xing_out_d_bits_corrupt; // @[ClockDomain.scala:14:9]
wire auto_tl_master_clock_xing_out_e_ready_0 = auto_tl_master_clock_xing_out_e_ready; // @[ClockDomain.scala:14:9]
wire auto_tap_clock_in_clock_0 = auto_tap_clock_in_clock; // @[ClockDomain.scala:14:9]
wire auto_tap_clock_in_reset_0 = auto_tap_clock_in_reset; // @[ClockDomain.scala:14:9]
wire [31:0] auto_element_reset_domain_rockettile_trace_core_source_out_group_0_iaddr = 32'h0; // @[ClockDomain.scala:14:9]
wire [31:0] auto_element_reset_domain_rockettile_trace_core_source_out_tval = 32'h0; // @[ClockDomain.scala:14:9]
wire [31:0] auto_element_reset_domain_rockettile_trace_core_source_out_cause = 32'h0; // @[ClockDomain.scala:14:9]
wire [31:0] element_reset_domain_auto_rockettile_trace_core_source_out_group_0_iaddr = 32'h0; // @[ClockDomain.scala:14:9]
wire [31:0] element_reset_domain_auto_rockettile_trace_core_source_out_tval = 32'h0; // @[ClockDomain.scala:14:9]
wire [31:0] element_reset_domain_auto_rockettile_trace_core_source_out_cause = 32'h0; // @[ClockDomain.scala:14:9]
wire [3:0] auto_element_reset_domain_rockettile_trace_core_source_out_group_0_itype = 4'h0; // @[ClockDomain.scala:14:9]
wire [3:0] auto_element_reset_domain_rockettile_trace_core_source_out_priv = 4'h0; // @[ClockDomain.scala:14:9]
wire [3:0] element_reset_domain_auto_rockettile_trace_core_source_out_group_0_itype = 4'h0; // @[ClockDomain.scala:14:9]
wire [3:0] element_reset_domain_auto_rockettile_trace_core_source_out_priv = 4'h0; // @[ClockDomain.scala:14:9]
wire [31:0] auto_element_reset_domain_rockettile_reset_vector_in = 32'h10000; // @[ClockDomain.scala:14:9]
wire [31:0] element_reset_domain_auto_rockettile_reset_vector_in = 32'h10000; // @[ClockDomain.scala:14:9]
wire auto_intsink_out_2_0 = 1'h0; // @[ClockDomain.scala:14:9]
wire auto_intsink_out_0_0 = 1'h0; // @[ClockDomain.scala:14:9]
wire auto_element_reset_domain_rockettile_trace_core_source_out_group_0_iretire = 1'h0; // @[ClockDomain.scala:14:9]
wire auto_element_reset_domain_rockettile_trace_core_source_out_group_0_ilastsize = 1'h0; // @[ClockDomain.scala:14:9]
wire _childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25]
wire element_reset_domain_auto_rockettile_buffer_out_a_bits_corrupt = 1'h0; // @[ClockDomain.scala:14:9]
wire element_reset_domain_auto_rockettile_buffer_out_c_bits_corrupt = 1'h0; // @[ClockDomain.scala:14:9]
wire element_reset_domain_auto_rockettile_cease_out_0 = 1'h0; // @[ClockDomain.scala:14:9]
wire element_reset_domain_auto_rockettile_halt_out_0 = 1'h0; // @[ClockDomain.scala:14:9]
wire element_reset_domain_auto_rockettile_trace_core_source_out_group_0_iretire = 1'h0; // @[ClockDomain.scala:14:9]
wire element_reset_domain_auto_rockettile_trace_core_source_out_group_0_ilastsize = 1'h0; // @[ClockDomain.scala:14:9]
wire element_reset_domain__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25]
wire clockNode_childClock = 1'h0; // @[LazyModuleImp.scala:155:31]
wire clockNode_childReset = 1'h0; // @[LazyModuleImp.scala:158:31]
wire clockNode__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25]
wire intOutClockXingOut_sync_0 = 1'h0; // @[MixedNode.scala:542:17]
wire intOutClockXingIn_sync_0 = 1'h0; // @[MixedNode.scala:551:17]
wire intOutClockXingOut_1_sync_0 = 1'h0; // @[MixedNode.scala:542:17]
wire intOutClockXingIn_1_sync_0 = 1'h0; // @[MixedNode.scala:551:17]
wire intOutClockXingOut_4_sync_0 = 1'h0; // @[MixedNode.scala:542:17]
wire intOutClockXingIn_4_sync_0 = 1'h0; // @[MixedNode.scala:551:17]
wire intOutClockXingOut_5_sync_0 = 1'h0; // @[MixedNode.scala:542:17]
wire intOutClockXingIn_5_sync_0 = 1'h0; // @[MixedNode.scala:551:17]
wire element_reset_domain_auto_rockettile_trace_source_out_insns_0_valid; // @[ClockDomain.scala:14:9]
wire [39:0] element_reset_domain_auto_rockettile_trace_source_out_insns_0_iaddr; // @[ClockDomain.scala:14:9]
wire [31:0] element_reset_domain_auto_rockettile_trace_source_out_insns_0_insn; // @[ClockDomain.scala:14:9]
wire [2:0] element_reset_domain_auto_rockettile_trace_source_out_insns_0_priv; // @[ClockDomain.scala:14:9]
wire element_reset_domain_auto_rockettile_trace_source_out_insns_0_exception; // @[ClockDomain.scala:14:9]
wire element_reset_domain_auto_rockettile_trace_source_out_insns_0_interrupt; // @[ClockDomain.scala:14:9]
wire [63:0] element_reset_domain_auto_rockettile_trace_source_out_insns_0_cause; // @[ClockDomain.scala:14:9]
wire [39:0] element_reset_domain_auto_rockettile_trace_source_out_insns_0_tval; // @[ClockDomain.scala:14:9]
wire [63:0] element_reset_domain_auto_rockettile_trace_source_out_time; // @[ClockDomain.scala:14:9]
wire [2:0] element_reset_domain_auto_rockettile_hartid_in = auto_element_reset_domain_rockettile_hartid_in_0; // @[ClockDomain.scala:14:9]
wire intInClockXingIn_2_sync_0 = auto_int_in_clock_xing_in_2_sync_0_0; // @[ClockDomain.scala:14:9]
wire intInClockXingIn_1_sync_0 = auto_int_in_clock_xing_in_1_sync_0_0; // @[ClockDomain.scala:14:9]
wire intInClockXingIn_sync_0 = auto_int_in_clock_xing_in_0_sync_0_0; // @[ClockDomain.scala:14:9]
wire intInClockXingIn_sync_1 = auto_int_in_clock_xing_in_0_sync_1_0; // @[ClockDomain.scala:14:9]
wire tlMasterClockXingOut_a_ready = auto_tl_master_clock_xing_out_a_ready_0; // @[ClockDomain.scala:14:9]
wire tlMasterClockXingOut_a_valid; // @[MixedNode.scala:542:17]
wire [2:0] tlMasterClockXingOut_a_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] tlMasterClockXingOut_a_bits_param; // @[MixedNode.scala:542:17]
wire [3:0] tlMasterClockXingOut_a_bits_size; // @[MixedNode.scala:542:17]
wire [1:0] tlMasterClockXingOut_a_bits_source; // @[MixedNode.scala:542:17]
wire [31:0] tlMasterClockXingOut_a_bits_address; // @[MixedNode.scala:542:17]
wire [7:0] tlMasterClockXingOut_a_bits_mask; // @[MixedNode.scala:542:17]
wire [63:0] tlMasterClockXingOut_a_bits_data; // @[MixedNode.scala:542:17]
wire tlMasterClockXingOut_a_bits_corrupt; // @[MixedNode.scala:542:17]
wire tlMasterClockXingOut_b_ready; // @[MixedNode.scala:542:17]
wire tlMasterClockXingOut_b_valid = auto_tl_master_clock_xing_out_b_valid_0; // @[ClockDomain.scala:14:9]
wire [2:0] tlMasterClockXingOut_b_bits_opcode = auto_tl_master_clock_xing_out_b_bits_opcode_0; // @[ClockDomain.scala:14:9]
wire [1:0] tlMasterClockXingOut_b_bits_param = auto_tl_master_clock_xing_out_b_bits_param_0; // @[ClockDomain.scala:14:9]
wire [3:0] tlMasterClockXingOut_b_bits_size = auto_tl_master_clock_xing_out_b_bits_size_0; // @[ClockDomain.scala:14:9]
wire [1:0] tlMasterClockXingOut_b_bits_source = auto_tl_master_clock_xing_out_b_bits_source_0; // @[ClockDomain.scala:14:9]
wire [31:0] tlMasterClockXingOut_b_bits_address = auto_tl_master_clock_xing_out_b_bits_address_0; // @[ClockDomain.scala:14:9]
wire [7:0] tlMasterClockXingOut_b_bits_mask = auto_tl_master_clock_xing_out_b_bits_mask_0; // @[ClockDomain.scala:14:9]
wire [63:0] tlMasterClockXingOut_b_bits_data = auto_tl_master_clock_xing_out_b_bits_data_0; // @[ClockDomain.scala:14:9]
wire tlMasterClockXingOut_b_bits_corrupt = auto_tl_master_clock_xing_out_b_bits_corrupt_0; // @[ClockDomain.scala:14:9]
wire tlMasterClockXingOut_c_ready = auto_tl_master_clock_xing_out_c_ready_0; // @[ClockDomain.scala:14:9]
wire tlMasterClockXingOut_c_valid; // @[MixedNode.scala:542:17]
wire [2:0] tlMasterClockXingOut_c_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] tlMasterClockXingOut_c_bits_param; // @[MixedNode.scala:542:17]
wire [3:0] tlMasterClockXingOut_c_bits_size; // @[MixedNode.scala:542:17]
wire [1:0] tlMasterClockXingOut_c_bits_source; // @[MixedNode.scala:542:17]
wire [31:0] tlMasterClockXingOut_c_bits_address; // @[MixedNode.scala:542:17]
wire [63:0] tlMasterClockXingOut_c_bits_data; // @[MixedNode.scala:542:17]
wire tlMasterClockXingOut_c_bits_corrupt; // @[MixedNode.scala:542:17]
wire tlMasterClockXingOut_d_ready; // @[MixedNode.scala:542:17]
wire tlMasterClockXingOut_d_valid = auto_tl_master_clock_xing_out_d_valid_0; // @[ClockDomain.scala:14:9]
wire [2:0] tlMasterClockXingOut_d_bits_opcode = auto_tl_master_clock_xing_out_d_bits_opcode_0; // @[ClockDomain.scala:14:9]
wire [1:0] tlMasterClockXingOut_d_bits_param = auto_tl_master_clock_xing_out_d_bits_param_0; // @[ClockDomain.scala:14:9]
wire [3:0] tlMasterClockXingOut_d_bits_size = auto_tl_master_clock_xing_out_d_bits_size_0; // @[ClockDomain.scala:14:9]
wire [1:0] tlMasterClockXingOut_d_bits_source = auto_tl_master_clock_xing_out_d_bits_source_0; // @[ClockDomain.scala:14:9]
wire [2:0] tlMasterClockXingOut_d_bits_sink = auto_tl_master_clock_xing_out_d_bits_sink_0; // @[ClockDomain.scala:14:9]
wire tlMasterClockXingOut_d_bits_denied = auto_tl_master_clock_xing_out_d_bits_denied_0; // @[ClockDomain.scala:14:9]
wire [63:0] tlMasterClockXingOut_d_bits_data = auto_tl_master_clock_xing_out_d_bits_data_0; // @[ClockDomain.scala:14:9]
wire tlMasterClockXingOut_d_bits_corrupt = auto_tl_master_clock_xing_out_d_bits_corrupt_0; // @[ClockDomain.scala:14:9]
wire tlMasterClockXingOut_e_ready = auto_tl_master_clock_xing_out_e_ready_0; // @[ClockDomain.scala:14:9]
wire tlMasterClockXingOut_e_valid; // @[MixedNode.scala:542:17]
wire [2:0] tlMasterClockXingOut_e_bits_sink; // @[MixedNode.scala:542:17]
wire tapClockNodeIn_clock = auto_tap_clock_in_clock_0; // @[ClockDomain.scala:14:9]
wire tapClockNodeIn_reset = auto_tap_clock_in_reset_0; // @[ClockDomain.scala:14:9]
wire auto_intsink_out_1_0_0; // @[ClockDomain.scala:14:9]
wire auto_element_reset_domain_rockettile_trace_source_out_insns_0_valid_0; // @[ClockDomain.scala:14:9]
wire [39:0] auto_element_reset_domain_rockettile_trace_source_out_insns_0_iaddr_0; // @[ClockDomain.scala:14:9]
wire [31:0] auto_element_reset_domain_rockettile_trace_source_out_insns_0_insn_0; // @[ClockDomain.scala:14:9]
wire [2:0] auto_element_reset_domain_rockettile_trace_source_out_insns_0_priv_0; // @[ClockDomain.scala:14:9]
wire auto_element_reset_domain_rockettile_trace_source_out_insns_0_exception_0; // @[ClockDomain.scala:14:9]
wire auto_element_reset_domain_rockettile_trace_source_out_insns_0_interrupt_0; // @[ClockDomain.scala:14:9]
wire [63:0] auto_element_reset_domain_rockettile_trace_source_out_insns_0_cause_0; // @[ClockDomain.scala:14:9]
wire [39:0] auto_element_reset_domain_rockettile_trace_source_out_insns_0_tval_0; // @[ClockDomain.scala:14:9]
wire [63:0] auto_element_reset_domain_rockettile_trace_source_out_time_0; // @[ClockDomain.scala:14:9]
wire [2:0] auto_tl_master_clock_xing_out_a_bits_opcode_0; // @[ClockDomain.scala:14:9]
wire [2:0] auto_tl_master_clock_xing_out_a_bits_param_0; // @[ClockDomain.scala:14:9]
wire [3:0] auto_tl_master_clock_xing_out_a_bits_size_0; // @[ClockDomain.scala:14:9]
wire [1:0] auto_tl_master_clock_xing_out_a_bits_source_0; // @[ClockDomain.scala:14:9]
wire [31:0] auto_tl_master_clock_xing_out_a_bits_address_0; // @[ClockDomain.scala:14:9]
wire [7:0] auto_tl_master_clock_xing_out_a_bits_mask_0; // @[ClockDomain.scala:14:9]
wire [63:0] auto_tl_master_clock_xing_out_a_bits_data_0; // @[ClockDomain.scala:14:9]
wire auto_tl_master_clock_xing_out_a_bits_corrupt_0; // @[ClockDomain.scala:14:9]
wire auto_tl_master_clock_xing_out_a_valid_0; // @[ClockDomain.scala:14:9]
wire auto_tl_master_clock_xing_out_b_ready_0; // @[ClockDomain.scala:14:9]
wire [2:0] auto_tl_master_clock_xing_out_c_bits_opcode_0; // @[ClockDomain.scala:14:9]
wire [2:0] auto_tl_master_clock_xing_out_c_bits_param_0; // @[ClockDomain.scala:14:9]
wire [3:0] auto_tl_master_clock_xing_out_c_bits_size_0; // @[ClockDomain.scala:14:9]
wire [1:0] auto_tl_master_clock_xing_out_c_bits_source_0; // @[ClockDomain.scala:14:9]
wire [31:0] auto_tl_master_clock_xing_out_c_bits_address_0; // @[ClockDomain.scala:14:9]
wire [63:0] auto_tl_master_clock_xing_out_c_bits_data_0; // @[ClockDomain.scala:14:9]
wire auto_tl_master_clock_xing_out_c_bits_corrupt_0; // @[ClockDomain.scala:14:9]
wire auto_tl_master_clock_xing_out_c_valid_0; // @[ClockDomain.scala:14:9]
wire auto_tl_master_clock_xing_out_d_ready_0; // @[ClockDomain.scala:14:9]
wire [2:0] auto_tl_master_clock_xing_out_e_bits_sink_0; // @[ClockDomain.scala:14:9]
wire auto_tl_master_clock_xing_out_e_valid_0; // @[ClockDomain.scala:14:9]
wire childClock; // @[LazyModuleImp.scala:155:31]
wire childReset; // @[LazyModuleImp.scala:158:31]
assign auto_element_reset_domain_rockettile_trace_source_out_insns_0_valid_0 = element_reset_domain_auto_rockettile_trace_source_out_insns_0_valid; // @[ClockDomain.scala:14:9]
assign auto_element_reset_domain_rockettile_trace_source_out_insns_0_iaddr_0 = element_reset_domain_auto_rockettile_trace_source_out_insns_0_iaddr; // @[ClockDomain.scala:14:9]
assign auto_element_reset_domain_rockettile_trace_source_out_insns_0_insn_0 = element_reset_domain_auto_rockettile_trace_source_out_insns_0_insn; // @[ClockDomain.scala:14:9]
assign auto_element_reset_domain_rockettile_trace_source_out_insns_0_priv_0 = element_reset_domain_auto_rockettile_trace_source_out_insns_0_priv; // @[ClockDomain.scala:14:9]
assign auto_element_reset_domain_rockettile_trace_source_out_insns_0_exception_0 = element_reset_domain_auto_rockettile_trace_source_out_insns_0_exception; // @[ClockDomain.scala:14:9]
assign auto_element_reset_domain_rockettile_trace_source_out_insns_0_interrupt_0 = element_reset_domain_auto_rockettile_trace_source_out_insns_0_interrupt; // @[ClockDomain.scala:14:9]
assign auto_element_reset_domain_rockettile_trace_source_out_insns_0_cause_0 = element_reset_domain_auto_rockettile_trace_source_out_insns_0_cause; // @[ClockDomain.scala:14:9]
assign auto_element_reset_domain_rockettile_trace_source_out_insns_0_tval_0 = element_reset_domain_auto_rockettile_trace_source_out_insns_0_tval; // @[ClockDomain.scala:14:9]
assign auto_element_reset_domain_rockettile_trace_source_out_time_0 = element_reset_domain_auto_rockettile_trace_source_out_time; // @[ClockDomain.scala:14:9]
wire clockNode_auto_anon_out_clock; // @[ClockGroup.scala:104:9]
wire element_reset_domain_clockNodeIn_clock = element_reset_domain_auto_clock_in_clock; // @[ClockDomain.scala:14:9]
wire clockNode_auto_anon_out_reset; // @[ClockGroup.scala:104:9]
wire [2:0] element_reset_domain_auto_rockettile_buffer_out_a_bits_opcode; // @[ClockDomain.scala:14:9]
wire [2:0] element_reset_domain_auto_rockettile_buffer_out_a_bits_param; // @[ClockDomain.scala:14:9]
wire [3:0] element_reset_domain_auto_rockettile_buffer_out_a_bits_size; // @[ClockDomain.scala:14:9]
wire [1:0] element_reset_domain_auto_rockettile_buffer_out_a_bits_source; // @[ClockDomain.scala:14:9]
wire [31:0] element_reset_domain_auto_rockettile_buffer_out_a_bits_address; // @[ClockDomain.scala:14:9]
wire [7:0] element_reset_domain_auto_rockettile_buffer_out_a_bits_mask; // @[ClockDomain.scala:14:9]
wire [63:0] element_reset_domain_auto_rockettile_buffer_out_a_bits_data; // @[ClockDomain.scala:14:9]
wire element_reset_domain_clockNodeIn_reset = element_reset_domain_auto_clock_in_reset; // @[ClockDomain.scala:14:9]
wire element_reset_domain_auto_rockettile_buffer_out_a_ready; // @[ClockDomain.scala:14:9]
wire element_reset_domain_auto_rockettile_buffer_out_a_valid; // @[ClockDomain.scala:14:9]
wire [2:0] element_reset_domain_auto_rockettile_buffer_out_b_bits_opcode; // @[ClockDomain.scala:14:9]
wire [1:0] element_reset_domain_auto_rockettile_buffer_out_b_bits_param; // @[ClockDomain.scala:14:9]
wire [3:0] element_reset_domain_auto_rockettile_buffer_out_b_bits_size; // @[ClockDomain.scala:14:9]
wire [1:0] element_reset_domain_auto_rockettile_buffer_out_b_bits_source; // @[ClockDomain.scala:14:9]
wire [31:0] element_reset_domain_auto_rockettile_buffer_out_b_bits_address; // @[ClockDomain.scala:14:9]
wire [7:0] element_reset_domain_auto_rockettile_buffer_out_b_bits_mask; // @[ClockDomain.scala:14:9]
wire [63:0] element_reset_domain_auto_rockettile_buffer_out_b_bits_data; // @[ClockDomain.scala:14:9]
wire element_reset_domain_auto_rockettile_buffer_out_b_bits_corrupt; // @[ClockDomain.scala:14:9]
wire element_reset_domain_auto_rockettile_buffer_out_b_ready; // @[ClockDomain.scala:14:9]
wire element_reset_domain_auto_rockettile_buffer_out_b_valid; // @[ClockDomain.scala:14:9]
wire [2:0] element_reset_domain_auto_rockettile_buffer_out_c_bits_opcode; // @[ClockDomain.scala:14:9]
wire [2:0] element_reset_domain_auto_rockettile_buffer_out_c_bits_param; // @[ClockDomain.scala:14:9]
wire [3:0] element_reset_domain_auto_rockettile_buffer_out_c_bits_size; // @[ClockDomain.scala:14:9]
wire [1:0] element_reset_domain_auto_rockettile_buffer_out_c_bits_source; // @[ClockDomain.scala:14:9]
wire [31:0] element_reset_domain_auto_rockettile_buffer_out_c_bits_address; // @[ClockDomain.scala:14:9]
wire [63:0] element_reset_domain_auto_rockettile_buffer_out_c_bits_data; // @[ClockDomain.scala:14:9]
wire element_reset_domain_auto_rockettile_buffer_out_c_ready; // @[ClockDomain.scala:14:9]
wire element_reset_domain_auto_rockettile_buffer_out_c_valid; // @[ClockDomain.scala:14:9]
wire [2:0] element_reset_domain_auto_rockettile_buffer_out_d_bits_opcode; // @[ClockDomain.scala:14:9]
wire [1:0] element_reset_domain_auto_rockettile_buffer_out_d_bits_param; // @[ClockDomain.scala:14:9]
wire [3:0] element_reset_domain_auto_rockettile_buffer_out_d_bits_size; // @[ClockDomain.scala:14:9]
wire [1:0] element_reset_domain_auto_rockettile_buffer_out_d_bits_source; // @[ClockDomain.scala:14:9]
wire [2:0] element_reset_domain_auto_rockettile_buffer_out_d_bits_sink; // @[ClockDomain.scala:14:9]
wire element_reset_domain_auto_rockettile_buffer_out_d_bits_denied; // @[ClockDomain.scala:14:9]
wire [63:0] element_reset_domain_auto_rockettile_buffer_out_d_bits_data; // @[ClockDomain.scala:14:9]
wire element_reset_domain_auto_rockettile_buffer_out_d_bits_corrupt; // @[ClockDomain.scala:14:9]
wire element_reset_domain_auto_rockettile_buffer_out_d_ready; // @[ClockDomain.scala:14:9]
wire element_reset_domain_auto_rockettile_buffer_out_d_valid; // @[ClockDomain.scala:14:9]
wire [2:0] element_reset_domain_auto_rockettile_buffer_out_e_bits_sink; // @[ClockDomain.scala:14:9]
wire element_reset_domain_auto_rockettile_buffer_out_e_ready; // @[ClockDomain.scala:14:9]
wire element_reset_domain_auto_rockettile_buffer_out_e_valid; // @[ClockDomain.scala:14:9]
wire element_reset_domain_auto_rockettile_wfi_out_0; // @[ClockDomain.scala:14:9]
wire element_reset_domain_auto_rockettile_int_local_in_3_0; // @[ClockDomain.scala:14:9]
wire element_reset_domain_auto_rockettile_int_local_in_2_0; // @[ClockDomain.scala:14:9]
wire element_reset_domain_auto_rockettile_int_local_in_1_0; // @[ClockDomain.scala:14:9]
wire element_reset_domain_auto_rockettile_int_local_in_1_1; // @[ClockDomain.scala:14:9]
wire element_reset_domain_auto_rockettile_int_local_in_0_0; // @[ClockDomain.scala:14:9]
wire element_reset_domain_childClock; // @[LazyModuleImp.scala:155:31]
wire element_reset_domain_childReset; // @[LazyModuleImp.scala:158:31]
assign element_reset_domain_childClock = element_reset_domain_clockNodeIn_clock; // @[MixedNode.scala:551:17]
assign element_reset_domain_childReset = element_reset_domain_clockNodeIn_reset; // @[MixedNode.scala:551:17]
wire tapClockNodeOut_clock; // @[MixedNode.scala:542:17]
wire clockNode_anonIn_clock = clockNode_auto_anon_in_clock; // @[ClockGroup.scala:104:9]
wire tapClockNodeOut_reset; // @[MixedNode.scala:542:17]
wire clockNode_anonOut_clock; // @[MixedNode.scala:542:17]
wire clockNode_anonIn_reset = clockNode_auto_anon_in_reset; // @[ClockGroup.scala:104:9]
assign element_reset_domain_auto_clock_in_clock = clockNode_auto_anon_out_clock; // @[ClockGroup.scala:104:9]
wire clockNode_anonOut_reset; // @[MixedNode.scala:542:17]
assign element_reset_domain_auto_clock_in_reset = clockNode_auto_anon_out_reset; // @[ClockGroup.scala:104:9]
assign clockNode_auto_anon_out_clock = clockNode_anonOut_clock; // @[ClockGroup.scala:104:9]
assign clockNode_auto_anon_out_reset = clockNode_anonOut_reset; // @[ClockGroup.scala:104:9]
assign clockNode_anonOut_clock = clockNode_anonIn_clock; // @[MixedNode.scala:542:17, :551:17]
assign clockNode_anonOut_reset = clockNode_anonIn_reset; // @[MixedNode.scala:542:17, :551:17]
assign clockNode_auto_anon_in_clock = tapClockNodeOut_clock; // @[ClockGroup.scala:104:9]
assign clockNode_auto_anon_in_reset = tapClockNodeOut_reset; // @[ClockGroup.scala:104:9]
assign childClock = tapClockNodeIn_clock; // @[MixedNode.scala:551:17]
assign tapClockNodeOut_clock = tapClockNodeIn_clock; // @[MixedNode.scala:542:17, :551:17]
assign childReset = tapClockNodeIn_reset; // @[MixedNode.scala:551:17]
assign tapClockNodeOut_reset = tapClockNodeIn_reset; // @[MixedNode.scala:542:17, :551:17]
wire tlMasterClockXingIn_a_ready = tlMasterClockXingOut_a_ready; // @[MixedNode.scala:542:17, :551:17]
wire tlMasterClockXingIn_a_valid; // @[MixedNode.scala:551:17]
assign auto_tl_master_clock_xing_out_a_valid_0 = tlMasterClockXingOut_a_valid; // @[ClockDomain.scala:14:9]
wire [2:0] tlMasterClockXingIn_a_bits_opcode; // @[MixedNode.scala:551:17]
assign auto_tl_master_clock_xing_out_a_bits_opcode_0 = tlMasterClockXingOut_a_bits_opcode; // @[ClockDomain.scala:14:9]
wire [2:0] tlMasterClockXingIn_a_bits_param; // @[MixedNode.scala:551:17]
assign auto_tl_master_clock_xing_out_a_bits_param_0 = tlMasterClockXingOut_a_bits_param; // @[ClockDomain.scala:14:9]
wire [3:0] tlMasterClockXingIn_a_bits_size; // @[MixedNode.scala:551:17]
assign auto_tl_master_clock_xing_out_a_bits_size_0 = tlMasterClockXingOut_a_bits_size; // @[ClockDomain.scala:14:9]
wire [1:0] tlMasterClockXingIn_a_bits_source; // @[MixedNode.scala:551:17]
assign auto_tl_master_clock_xing_out_a_bits_source_0 = tlMasterClockXingOut_a_bits_source; // @[ClockDomain.scala:14:9]
wire [31:0] tlMasterClockXingIn_a_bits_address; // @[MixedNode.scala:551:17]
assign auto_tl_master_clock_xing_out_a_bits_address_0 = tlMasterClockXingOut_a_bits_address; // @[ClockDomain.scala:14:9]
wire [7:0] tlMasterClockXingIn_a_bits_mask; // @[MixedNode.scala:551:17]
assign auto_tl_master_clock_xing_out_a_bits_mask_0 = tlMasterClockXingOut_a_bits_mask; // @[ClockDomain.scala:14:9]
wire [63:0] tlMasterClockXingIn_a_bits_data; // @[MixedNode.scala:551:17]
assign auto_tl_master_clock_xing_out_a_bits_data_0 = tlMasterClockXingOut_a_bits_data; // @[ClockDomain.scala:14:9]
wire tlMasterClockXingIn_a_bits_corrupt; // @[MixedNode.scala:551:17]
assign auto_tl_master_clock_xing_out_a_bits_corrupt_0 = tlMasterClockXingOut_a_bits_corrupt; // @[ClockDomain.scala:14:9]
wire tlMasterClockXingIn_b_ready; // @[MixedNode.scala:551:17]
assign auto_tl_master_clock_xing_out_b_ready_0 = tlMasterClockXingOut_b_ready; // @[ClockDomain.scala:14:9]
wire tlMasterClockXingIn_b_valid = tlMasterClockXingOut_b_valid; // @[MixedNode.scala:542:17, :551:17]
wire [2:0] tlMasterClockXingIn_b_bits_opcode = tlMasterClockXingOut_b_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
wire [1:0] tlMasterClockXingIn_b_bits_param = tlMasterClockXingOut_b_bits_param; // @[MixedNode.scala:542:17, :551:17]
wire [3:0] tlMasterClockXingIn_b_bits_size = tlMasterClockXingOut_b_bits_size; // @[MixedNode.scala:542:17, :551:17]
wire [1:0] tlMasterClockXingIn_b_bits_source = tlMasterClockXingOut_b_bits_source; // @[MixedNode.scala:542:17, :551:17]
wire [31:0] tlMasterClockXingIn_b_bits_address = tlMasterClockXingOut_b_bits_address; // @[MixedNode.scala:542:17, :551:17]
wire [7:0] tlMasterClockXingIn_b_bits_mask = tlMasterClockXingOut_b_bits_mask; // @[MixedNode.scala:542:17, :551:17]
wire [63:0] tlMasterClockXingIn_b_bits_data = tlMasterClockXingOut_b_bits_data; // @[MixedNode.scala:542:17, :551:17]
wire tlMasterClockXingIn_b_bits_corrupt = tlMasterClockXingOut_b_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
wire tlMasterClockXingIn_c_ready = tlMasterClockXingOut_c_ready; // @[MixedNode.scala:542:17, :551:17]
wire tlMasterClockXingIn_c_valid; // @[MixedNode.scala:551:17]
assign auto_tl_master_clock_xing_out_c_valid_0 = tlMasterClockXingOut_c_valid; // @[ClockDomain.scala:14:9]
wire [2:0] tlMasterClockXingIn_c_bits_opcode; // @[MixedNode.scala:551:17]
assign auto_tl_master_clock_xing_out_c_bits_opcode_0 = tlMasterClockXingOut_c_bits_opcode; // @[ClockDomain.scala:14:9]
wire [2:0] tlMasterClockXingIn_c_bits_param; // @[MixedNode.scala:551:17]
assign auto_tl_master_clock_xing_out_c_bits_param_0 = tlMasterClockXingOut_c_bits_param; // @[ClockDomain.scala:14:9]
wire [3:0] tlMasterClockXingIn_c_bits_size; // @[MixedNode.scala:551:17]
assign auto_tl_master_clock_xing_out_c_bits_size_0 = tlMasterClockXingOut_c_bits_size; // @[ClockDomain.scala:14:9]
wire [1:0] tlMasterClockXingIn_c_bits_source; // @[MixedNode.scala:551:17]
assign auto_tl_master_clock_xing_out_c_bits_source_0 = tlMasterClockXingOut_c_bits_source; // @[ClockDomain.scala:14:9]
wire [31:0] tlMasterClockXingIn_c_bits_address; // @[MixedNode.scala:551:17]
assign auto_tl_master_clock_xing_out_c_bits_address_0 = tlMasterClockXingOut_c_bits_address; // @[ClockDomain.scala:14:9]
wire [63:0] tlMasterClockXingIn_c_bits_data; // @[MixedNode.scala:551:17]
assign auto_tl_master_clock_xing_out_c_bits_data_0 = tlMasterClockXingOut_c_bits_data; // @[ClockDomain.scala:14:9]
wire tlMasterClockXingIn_c_bits_corrupt; // @[MixedNode.scala:551:17]
assign auto_tl_master_clock_xing_out_c_bits_corrupt_0 = tlMasterClockXingOut_c_bits_corrupt; // @[ClockDomain.scala:14:9]
wire tlMasterClockXingIn_d_ready; // @[MixedNode.scala:551:17]
assign auto_tl_master_clock_xing_out_d_ready_0 = tlMasterClockXingOut_d_ready; // @[ClockDomain.scala:14:9]
wire tlMasterClockXingIn_d_valid = tlMasterClockXingOut_d_valid; // @[MixedNode.scala:542:17, :551:17]
wire [2:0] tlMasterClockXingIn_d_bits_opcode = tlMasterClockXingOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
wire [1:0] tlMasterClockXingIn_d_bits_param = tlMasterClockXingOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17]
wire [3:0] tlMasterClockXingIn_d_bits_size = tlMasterClockXingOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17]
wire [1:0] tlMasterClockXingIn_d_bits_source = tlMasterClockXingOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17]
wire [2:0] tlMasterClockXingIn_d_bits_sink = tlMasterClockXingOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17]
wire tlMasterClockXingIn_d_bits_denied = tlMasterClockXingOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17]
wire [63:0] tlMasterClockXingIn_d_bits_data = tlMasterClockXingOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17]
wire tlMasterClockXingIn_d_bits_corrupt = tlMasterClockXingOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
wire tlMasterClockXingIn_e_ready = tlMasterClockXingOut_e_ready; // @[MixedNode.scala:542:17, :551:17]
wire tlMasterClockXingIn_e_valid; // @[MixedNode.scala:551:17]
assign auto_tl_master_clock_xing_out_e_valid_0 = tlMasterClockXingOut_e_valid; // @[ClockDomain.scala:14:9]
wire [2:0] tlMasterClockXingIn_e_bits_sink; // @[MixedNode.scala:551:17]
assign auto_tl_master_clock_xing_out_e_bits_sink_0 = tlMasterClockXingOut_e_bits_sink; // @[ClockDomain.scala:14:9]
assign tlMasterClockXingOut_a_valid = tlMasterClockXingIn_a_valid; // @[MixedNode.scala:542:17, :551:17]
assign tlMasterClockXingOut_a_bits_opcode = tlMasterClockXingIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign tlMasterClockXingOut_a_bits_param = tlMasterClockXingIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign tlMasterClockXingOut_a_bits_size = tlMasterClockXingIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign tlMasterClockXingOut_a_bits_source = tlMasterClockXingIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign tlMasterClockXingOut_a_bits_address = tlMasterClockXingIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17]
assign tlMasterClockXingOut_a_bits_mask = tlMasterClockXingIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17]
assign tlMasterClockXingOut_a_bits_data = tlMasterClockXingIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign tlMasterClockXingOut_a_bits_corrupt = tlMasterClockXingIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign tlMasterClockXingOut_b_ready = tlMasterClockXingIn_b_ready; // @[MixedNode.scala:542:17, :551:17]
assign tlMasterClockXingOut_c_valid = tlMasterClockXingIn_c_valid; // @[MixedNode.scala:542:17, :551:17]
assign tlMasterClockXingOut_c_bits_opcode = tlMasterClockXingIn_c_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign tlMasterClockXingOut_c_bits_param = tlMasterClockXingIn_c_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign tlMasterClockXingOut_c_bits_size = tlMasterClockXingIn_c_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign tlMasterClockXingOut_c_bits_source = tlMasterClockXingIn_c_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign tlMasterClockXingOut_c_bits_address = tlMasterClockXingIn_c_bits_address; // @[MixedNode.scala:542:17, :551:17]
assign tlMasterClockXingOut_c_bits_data = tlMasterClockXingIn_c_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign tlMasterClockXingOut_c_bits_corrupt = tlMasterClockXingIn_c_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign tlMasterClockXingOut_d_ready = tlMasterClockXingIn_d_ready; // @[MixedNode.scala:542:17, :551:17]
assign tlMasterClockXingOut_e_valid = tlMasterClockXingIn_e_valid; // @[MixedNode.scala:542:17, :551:17]
assign tlMasterClockXingOut_e_bits_sink = tlMasterClockXingIn_e_bits_sink; // @[MixedNode.scala:542:17, :551:17]
wire intInClockXingOut_sync_0; // @[MixedNode.scala:542:17]
wire intInClockXingOut_sync_1; // @[MixedNode.scala:542:17]
assign intInClockXingOut_sync_0 = intInClockXingIn_sync_0; // @[MixedNode.scala:542:17, :551:17]
assign intInClockXingOut_sync_1 = intInClockXingIn_sync_1; // @[MixedNode.scala:542:17, :551:17]
wire intInClockXingOut_1_sync_0; // @[MixedNode.scala:542:17]
assign intInClockXingOut_1_sync_0 = intInClockXingIn_1_sync_0; // @[MixedNode.scala:542:17, :551:17]
wire intInClockXingOut_2_sync_0; // @[MixedNode.scala:542:17]
assign intInClockXingOut_2_sync_0 = intInClockXingIn_2_sync_0; // @[MixedNode.scala:542:17, :551:17]
wire intOutClockXingIn_2_sync_0; // @[MixedNode.scala:551:17]
wire intOutClockXingOut_2_sync_0; // @[MixedNode.scala:542:17]
wire intOutClockXingOut_3_sync_0; // @[MixedNode.scala:542:17]
assign intOutClockXingOut_2_sync_0 = intOutClockXingIn_2_sync_0; // @[MixedNode.scala:542:17, :551:17]
wire intOutClockXingIn_3_sync_0; // @[MixedNode.scala:551:17]
assign intOutClockXingIn_2_sync_0 = intOutClockXingOut_3_sync_0; // @[MixedNode.scala:542:17, :551:17]
assign intOutClockXingOut_3_sync_0 = intOutClockXingIn_3_sync_0; // @[MixedNode.scala:542:17, :551:17]
RocketTile_4 element_reset_domain_rockettile ( // @[HasTiles.scala:164:59]
.clock (element_reset_domain_childClock), // @[LazyModuleImp.scala:155:31]
.reset (element_reset_domain_childReset), // @[LazyModuleImp.scala:158:31]
.auto_buffer_out_a_ready (element_reset_domain_auto_rockettile_buffer_out_a_ready), // @[ClockDomain.scala:14:9]
.auto_buffer_out_a_valid (element_reset_domain_auto_rockettile_buffer_out_a_valid),
.auto_buffer_out_a_bits_opcode (element_reset_domain_auto_rockettile_buffer_out_a_bits_opcode),
.auto_buffer_out_a_bits_param (element_reset_domain_auto_rockettile_buffer_out_a_bits_param),
.auto_buffer_out_a_bits_size (element_reset_domain_auto_rockettile_buffer_out_a_bits_size),
.auto_buffer_out_a_bits_source (element_reset_domain_auto_rockettile_buffer_out_a_bits_source),
.auto_buffer_out_a_bits_address (element_reset_domain_auto_rockettile_buffer_out_a_bits_address),
.auto_buffer_out_a_bits_mask (element_reset_domain_auto_rockettile_buffer_out_a_bits_mask),
.auto_buffer_out_a_bits_data (element_reset_domain_auto_rockettile_buffer_out_a_bits_data),
.auto_buffer_out_b_ready (element_reset_domain_auto_rockettile_buffer_out_b_ready),
.auto_buffer_out_b_valid (element_reset_domain_auto_rockettile_buffer_out_b_valid), // @[ClockDomain.scala:14:9]
.auto_buffer_out_b_bits_opcode (element_reset_domain_auto_rockettile_buffer_out_b_bits_opcode), // @[ClockDomain.scala:14:9]
.auto_buffer_out_b_bits_param (element_reset_domain_auto_rockettile_buffer_out_b_bits_param), // @[ClockDomain.scala:14:9]
.auto_buffer_out_b_bits_size (element_reset_domain_auto_rockettile_buffer_out_b_bits_size), // @[ClockDomain.scala:14:9]
.auto_buffer_out_b_bits_source (element_reset_domain_auto_rockettile_buffer_out_b_bits_source), // @[ClockDomain.scala:14:9]
.auto_buffer_out_b_bits_address (element_reset_domain_auto_rockettile_buffer_out_b_bits_address), // @[ClockDomain.scala:14:9]
.auto_buffer_out_b_bits_mask (element_reset_domain_auto_rockettile_buffer_out_b_bits_mask), // @[ClockDomain.scala:14:9]
.auto_buffer_out_b_bits_data (element_reset_domain_auto_rockettile_buffer_out_b_bits_data), // @[ClockDomain.scala:14:9]
.auto_buffer_out_b_bits_corrupt (element_reset_domain_auto_rockettile_buffer_out_b_bits_corrupt), // @[ClockDomain.scala:14:9]
.auto_buffer_out_c_ready (element_reset_domain_auto_rockettile_buffer_out_c_ready), // @[ClockDomain.scala:14:9]
.auto_buffer_out_c_valid (element_reset_domain_auto_rockettile_buffer_out_c_valid),
.auto_buffer_out_c_bits_opcode (element_reset_domain_auto_rockettile_buffer_out_c_bits_opcode),
.auto_buffer_out_c_bits_param (element_reset_domain_auto_rockettile_buffer_out_c_bits_param),
.auto_buffer_out_c_bits_size (element_reset_domain_auto_rockettile_buffer_out_c_bits_size),
.auto_buffer_out_c_bits_source (element_reset_domain_auto_rockettile_buffer_out_c_bits_source),
.auto_buffer_out_c_bits_address (element_reset_domain_auto_rockettile_buffer_out_c_bits_address),
.auto_buffer_out_c_bits_data (element_reset_domain_auto_rockettile_buffer_out_c_bits_data),
.auto_buffer_out_d_ready (element_reset_domain_auto_rockettile_buffer_out_d_ready),
.auto_buffer_out_d_valid (element_reset_domain_auto_rockettile_buffer_out_d_valid), // @[ClockDomain.scala:14:9]
.auto_buffer_out_d_bits_opcode (element_reset_domain_auto_rockettile_buffer_out_d_bits_opcode), // @[ClockDomain.scala:14:9]
.auto_buffer_out_d_bits_param (element_reset_domain_auto_rockettile_buffer_out_d_bits_param), // @[ClockDomain.scala:14:9]
.auto_buffer_out_d_bits_size (element_reset_domain_auto_rockettile_buffer_out_d_bits_size), // @[ClockDomain.scala:14:9]
.auto_buffer_out_d_bits_source (element_reset_domain_auto_rockettile_buffer_out_d_bits_source), // @[ClockDomain.scala:14:9]
.auto_buffer_out_d_bits_sink (element_reset_domain_auto_rockettile_buffer_out_d_bits_sink), // @[ClockDomain.scala:14:9]
.auto_buffer_out_d_bits_denied (element_reset_domain_auto_rockettile_buffer_out_d_bits_denied), // @[ClockDomain.scala:14:9]
.auto_buffer_out_d_bits_data (element_reset_domain_auto_rockettile_buffer_out_d_bits_data), // @[ClockDomain.scala:14:9]
.auto_buffer_out_d_bits_corrupt (element_reset_domain_auto_rockettile_buffer_out_d_bits_corrupt), // @[ClockDomain.scala:14:9]
.auto_buffer_out_e_ready (element_reset_domain_auto_rockettile_buffer_out_e_ready), // @[ClockDomain.scala:14:9]
.auto_buffer_out_e_valid (element_reset_domain_auto_rockettile_buffer_out_e_valid),
.auto_buffer_out_e_bits_sink (element_reset_domain_auto_rockettile_buffer_out_e_bits_sink),
.auto_wfi_out_0 (element_reset_domain_auto_rockettile_wfi_out_0),
.auto_int_local_in_3_0 (element_reset_domain_auto_rockettile_int_local_in_3_0), // @[ClockDomain.scala:14:9]
.auto_int_local_in_2_0 (element_reset_domain_auto_rockettile_int_local_in_2_0), // @[ClockDomain.scala:14:9]
.auto_int_local_in_1_0 (element_reset_domain_auto_rockettile_int_local_in_1_0), // @[ClockDomain.scala:14:9]
.auto_int_local_in_1_1 (element_reset_domain_auto_rockettile_int_local_in_1_1), // @[ClockDomain.scala:14:9]
.auto_int_local_in_0_0 (element_reset_domain_auto_rockettile_int_local_in_0_0), // @[ClockDomain.scala:14:9]
.auto_trace_source_out_insns_0_valid (element_reset_domain_auto_rockettile_trace_source_out_insns_0_valid),
.auto_trace_source_out_insns_0_iaddr (element_reset_domain_auto_rockettile_trace_source_out_insns_0_iaddr),
.auto_trace_source_out_insns_0_insn (element_reset_domain_auto_rockettile_trace_source_out_insns_0_insn),
.auto_trace_source_out_insns_0_priv (element_reset_domain_auto_rockettile_trace_source_out_insns_0_priv),
.auto_trace_source_out_insns_0_exception (element_reset_domain_auto_rockettile_trace_source_out_insns_0_exception),
.auto_trace_source_out_insns_0_interrupt (element_reset_domain_auto_rockettile_trace_source_out_insns_0_interrupt),
.auto_trace_source_out_insns_0_cause (element_reset_domain_auto_rockettile_trace_source_out_insns_0_cause),
.auto_trace_source_out_insns_0_tval (element_reset_domain_auto_rockettile_trace_source_out_insns_0_tval),
.auto_trace_source_out_time (element_reset_domain_auto_rockettile_trace_source_out_time),
.auto_hartid_in (element_reset_domain_auto_rockettile_hartid_in) // @[ClockDomain.scala:14:9]
); // @[HasTiles.scala:164:59]
TLBuffer_a32d64s2k3z4c_9 buffer ( // @[Buffer.scala:75:28]
.clock (childClock), // @[LazyModuleImp.scala:155:31]
.reset (childReset), // @[LazyModuleImp.scala:158:31]
.auto_in_a_ready (element_reset_domain_auto_rockettile_buffer_out_a_ready),
.auto_in_a_valid (element_reset_domain_auto_rockettile_buffer_out_a_valid), // @[ClockDomain.scala:14:9]
.auto_in_a_bits_opcode (element_reset_domain_auto_rockettile_buffer_out_a_bits_opcode), // @[ClockDomain.scala:14:9]
.auto_in_a_bits_param (element_reset_domain_auto_rockettile_buffer_out_a_bits_param), // @[ClockDomain.scala:14:9]
.auto_in_a_bits_size (element_reset_domain_auto_rockettile_buffer_out_a_bits_size), // @[ClockDomain.scala:14:9]
.auto_in_a_bits_source (element_reset_domain_auto_rockettile_buffer_out_a_bits_source), // @[ClockDomain.scala:14:9]
.auto_in_a_bits_address (element_reset_domain_auto_rockettile_buffer_out_a_bits_address), // @[ClockDomain.scala:14:9]
.auto_in_a_bits_mask (element_reset_domain_auto_rockettile_buffer_out_a_bits_mask), // @[ClockDomain.scala:14:9]
.auto_in_a_bits_data (element_reset_domain_auto_rockettile_buffer_out_a_bits_data), // @[ClockDomain.scala:14:9]
.auto_in_b_ready (element_reset_domain_auto_rockettile_buffer_out_b_ready), // @[ClockDomain.scala:14:9]
.auto_in_b_valid (element_reset_domain_auto_rockettile_buffer_out_b_valid),
.auto_in_b_bits_opcode (element_reset_domain_auto_rockettile_buffer_out_b_bits_opcode),
.auto_in_b_bits_param (element_reset_domain_auto_rockettile_buffer_out_b_bits_param),
.auto_in_b_bits_size (element_reset_domain_auto_rockettile_buffer_out_b_bits_size),
.auto_in_b_bits_source (element_reset_domain_auto_rockettile_buffer_out_b_bits_source),
.auto_in_b_bits_address (element_reset_domain_auto_rockettile_buffer_out_b_bits_address),
.auto_in_b_bits_mask (element_reset_domain_auto_rockettile_buffer_out_b_bits_mask),
.auto_in_b_bits_data (element_reset_domain_auto_rockettile_buffer_out_b_bits_data),
.auto_in_b_bits_corrupt (element_reset_domain_auto_rockettile_buffer_out_b_bits_corrupt),
.auto_in_c_ready (element_reset_domain_auto_rockettile_buffer_out_c_ready),
.auto_in_c_valid (element_reset_domain_auto_rockettile_buffer_out_c_valid), // @[ClockDomain.scala:14:9]
.auto_in_c_bits_opcode (element_reset_domain_auto_rockettile_buffer_out_c_bits_opcode), // @[ClockDomain.scala:14:9]
.auto_in_c_bits_param (element_reset_domain_auto_rockettile_buffer_out_c_bits_param), // @[ClockDomain.scala:14:9]
.auto_in_c_bits_size (element_reset_domain_auto_rockettile_buffer_out_c_bits_size), // @[ClockDomain.scala:14:9]
.auto_in_c_bits_source (element_reset_domain_auto_rockettile_buffer_out_c_bits_source), // @[ClockDomain.scala:14:9]
.auto_in_c_bits_address (element_reset_domain_auto_rockettile_buffer_out_c_bits_address), // @[ClockDomain.scala:14:9]
.auto_in_c_bits_data (element_reset_domain_auto_rockettile_buffer_out_c_bits_data), // @[ClockDomain.scala:14:9]
.auto_in_d_ready (element_reset_domain_auto_rockettile_buffer_out_d_ready), // @[ClockDomain.scala:14:9]
.auto_in_d_valid (element_reset_domain_auto_rockettile_buffer_out_d_valid),
.auto_in_d_bits_opcode (element_reset_domain_auto_rockettile_buffer_out_d_bits_opcode),
.auto_in_d_bits_param (element_reset_domain_auto_rockettile_buffer_out_d_bits_param),
.auto_in_d_bits_size (element_reset_domain_auto_rockettile_buffer_out_d_bits_size),
.auto_in_d_bits_source (element_reset_domain_auto_rockettile_buffer_out_d_bits_source),
.auto_in_d_bits_sink (element_reset_domain_auto_rockettile_buffer_out_d_bits_sink),
.auto_in_d_bits_denied (element_reset_domain_auto_rockettile_buffer_out_d_bits_denied),
.auto_in_d_bits_data (element_reset_domain_auto_rockettile_buffer_out_d_bits_data),
.auto_in_d_bits_corrupt (element_reset_domain_auto_rockettile_buffer_out_d_bits_corrupt),
.auto_in_e_ready (element_reset_domain_auto_rockettile_buffer_out_e_ready),
.auto_in_e_valid (element_reset_domain_auto_rockettile_buffer_out_e_valid), // @[ClockDomain.scala:14:9]
.auto_in_e_bits_sink (element_reset_domain_auto_rockettile_buffer_out_e_bits_sink), // @[ClockDomain.scala:14:9]
.auto_out_a_ready (tlMasterClockXingIn_a_ready), // @[MixedNode.scala:551:17]
.auto_out_a_valid (tlMasterClockXingIn_a_valid),
.auto_out_a_bits_opcode (tlMasterClockXingIn_a_bits_opcode),
.auto_out_a_bits_param (tlMasterClockXingIn_a_bits_param),
.auto_out_a_bits_size (tlMasterClockXingIn_a_bits_size),
.auto_out_a_bits_source (tlMasterClockXingIn_a_bits_source),
.auto_out_a_bits_address (tlMasterClockXingIn_a_bits_address),
.auto_out_a_bits_mask (tlMasterClockXingIn_a_bits_mask),
.auto_out_a_bits_data (tlMasterClockXingIn_a_bits_data),
.auto_out_a_bits_corrupt (tlMasterClockXingIn_a_bits_corrupt),
.auto_out_b_ready (tlMasterClockXingIn_b_ready),
.auto_out_b_valid (tlMasterClockXingIn_b_valid), // @[MixedNode.scala:551:17]
.auto_out_b_bits_opcode (tlMasterClockXingIn_b_bits_opcode), // @[MixedNode.scala:551:17]
.auto_out_b_bits_param (tlMasterClockXingIn_b_bits_param), // @[MixedNode.scala:551:17]
.auto_out_b_bits_size (tlMasterClockXingIn_b_bits_size), // @[MixedNode.scala:551:17]
.auto_out_b_bits_source (tlMasterClockXingIn_b_bits_source), // @[MixedNode.scala:551:17]
.auto_out_b_bits_address (tlMasterClockXingIn_b_bits_address), // @[MixedNode.scala:551:17]
.auto_out_b_bits_mask (tlMasterClockXingIn_b_bits_mask), // @[MixedNode.scala:551:17]
.auto_out_b_bits_data (tlMasterClockXingIn_b_bits_data), // @[MixedNode.scala:551:17]
.auto_out_b_bits_corrupt (tlMasterClockXingIn_b_bits_corrupt), // @[MixedNode.scala:551:17]
.auto_out_c_ready (tlMasterClockXingIn_c_ready), // @[MixedNode.scala:551:17]
.auto_out_c_valid (tlMasterClockXingIn_c_valid),
.auto_out_c_bits_opcode (tlMasterClockXingIn_c_bits_opcode),
.auto_out_c_bits_param (tlMasterClockXingIn_c_bits_param),
.auto_out_c_bits_size (tlMasterClockXingIn_c_bits_size),
.auto_out_c_bits_source (tlMasterClockXingIn_c_bits_source),
.auto_out_c_bits_address (tlMasterClockXingIn_c_bits_address),
.auto_out_c_bits_data (tlMasterClockXingIn_c_bits_data),
.auto_out_c_bits_corrupt (tlMasterClockXingIn_c_bits_corrupt),
.auto_out_d_ready (tlMasterClockXingIn_d_ready),
.auto_out_d_valid (tlMasterClockXingIn_d_valid), // @[MixedNode.scala:551:17]
.auto_out_d_bits_opcode (tlMasterClockXingIn_d_bits_opcode), // @[MixedNode.scala:551:17]
.auto_out_d_bits_param (tlMasterClockXingIn_d_bits_param), // @[MixedNode.scala:551:17]
.auto_out_d_bits_size (tlMasterClockXingIn_d_bits_size), // @[MixedNode.scala:551:17]
.auto_out_d_bits_source (tlMasterClockXingIn_d_bits_source), // @[MixedNode.scala:551:17]
.auto_out_d_bits_sink (tlMasterClockXingIn_d_bits_sink), // @[MixedNode.scala:551:17]
.auto_out_d_bits_denied (tlMasterClockXingIn_d_bits_denied), // @[MixedNode.scala:551:17]
.auto_out_d_bits_data (tlMasterClockXingIn_d_bits_data), // @[MixedNode.scala:551:17]
.auto_out_d_bits_corrupt (tlMasterClockXingIn_d_bits_corrupt), // @[MixedNode.scala:551:17]
.auto_out_e_ready (tlMasterClockXingIn_e_ready), // @[MixedNode.scala:551:17]
.auto_out_e_valid (tlMasterClockXingIn_e_valid),
.auto_out_e_bits_sink (tlMasterClockXingIn_e_bits_sink)
); // @[Buffer.scala:75:28]
TLBuffer_14 buffer_1 ( // @[Buffer.scala:75:28]
.clock (childClock), // @[LazyModuleImp.scala:155:31]
.reset (childReset) // @[LazyModuleImp.scala:158:31]
); // @[Buffer.scala:75:28]
IntSyncAsyncCrossingSink_n1x1_4 intsink ( // @[Crossing.scala:86:29]
.clock (childClock), // @[LazyModuleImp.scala:155:31]
.reset (childReset), // @[LazyModuleImp.scala:158:31]
.auto_in_sync_0 (auto_intsink_in_sync_0_0), // @[ClockDomain.scala:14:9]
.auto_out_0 (element_reset_domain_auto_rockettile_int_local_in_0_0)
); // @[Crossing.scala:86:29]
IntSyncSyncCrossingSink_n1x2_8 intsink_1 ( // @[Crossing.scala:109:29]
.auto_in_sync_0 (intInClockXingOut_sync_0), // @[MixedNode.scala:542:17]
.auto_in_sync_1 (intInClockXingOut_sync_1), // @[MixedNode.scala:542:17]
.auto_out_0 (element_reset_domain_auto_rockettile_int_local_in_1_0),
.auto_out_1 (element_reset_domain_auto_rockettile_int_local_in_1_1)
); // @[Crossing.scala:109:29]
IntSyncSyncCrossingSink_n1x1_28 intsink_2 ( // @[Crossing.scala:109:29]
.auto_in_sync_0 (intInClockXingOut_1_sync_0), // @[MixedNode.scala:542:17]
.auto_out_0 (element_reset_domain_auto_rockettile_int_local_in_2_0)
); // @[Crossing.scala:109:29]
IntSyncSyncCrossingSink_n1x1_29 intsink_3 ( // @[Crossing.scala:109:29]
.auto_in_sync_0 (intInClockXingOut_2_sync_0), // @[MixedNode.scala:542:17]
.auto_out_0 (element_reset_domain_auto_rockettile_int_local_in_3_0)
); // @[Crossing.scala:109:29]
IntSyncSyncCrossingSink_n1x1_30 intsink_4 (); // @[Crossing.scala:109:29]
IntSyncCrossingSource_n1x1_20 intsource ( // @[Crossing.scala:29:31]
.clock (childClock), // @[LazyModuleImp.scala:155:31]
.reset (childReset) // @[LazyModuleImp.scala:158:31]
); // @[Crossing.scala:29:31]
IntSyncSyncCrossingSink_n1x1_31 intsink_5 ( // @[Crossing.scala:109:29]
.auto_in_sync_0 (intOutClockXingOut_2_sync_0), // @[MixedNode.scala:542:17]
.auto_out_0 (auto_intsink_out_1_0_0)
); // @[Crossing.scala:109:29]
IntSyncCrossingSource_n1x1_21 intsource_1 ( // @[Crossing.scala:29:31]
.clock (childClock), // @[LazyModuleImp.scala:155:31]
.reset (childReset), // @[LazyModuleImp.scala:158:31]
.auto_in_0 (element_reset_domain_auto_rockettile_wfi_out_0), // @[ClockDomain.scala:14:9]
.auto_out_sync_0 (intOutClockXingIn_3_sync_0)
); // @[Crossing.scala:29:31]
IntSyncSyncCrossingSink_n1x1_32 intsink_6 (); // @[Crossing.scala:109:29]
IntSyncCrossingSource_n1x1_22 intsource_2 ( // @[Crossing.scala:29:31]
.clock (childClock), // @[LazyModuleImp.scala:155:31]
.reset (childReset) // @[LazyModuleImp.scala:158:31]
); // @[Crossing.scala:29:31]
assign auto_intsink_out_1_0 = auto_intsink_out_1_0_0; // @[ClockDomain.scala:14:9]
assign auto_element_reset_domain_rockettile_trace_source_out_insns_0_valid = auto_element_reset_domain_rockettile_trace_source_out_insns_0_valid_0; // @[ClockDomain.scala:14:9]
assign auto_element_reset_domain_rockettile_trace_source_out_insns_0_iaddr = auto_element_reset_domain_rockettile_trace_source_out_insns_0_iaddr_0; // @[ClockDomain.scala:14:9]
assign auto_element_reset_domain_rockettile_trace_source_out_insns_0_insn = auto_element_reset_domain_rockettile_trace_source_out_insns_0_insn_0; // @[ClockDomain.scala:14:9]
assign auto_element_reset_domain_rockettile_trace_source_out_insns_0_priv = auto_element_reset_domain_rockettile_trace_source_out_insns_0_priv_0; // @[ClockDomain.scala:14:9]
assign auto_element_reset_domain_rockettile_trace_source_out_insns_0_exception = auto_element_reset_domain_rockettile_trace_source_out_insns_0_exception_0; // @[ClockDomain.scala:14:9]
assign auto_element_reset_domain_rockettile_trace_source_out_insns_0_interrupt = auto_element_reset_domain_rockettile_trace_source_out_insns_0_interrupt_0; // @[ClockDomain.scala:14:9]
assign auto_element_reset_domain_rockettile_trace_source_out_insns_0_cause = auto_element_reset_domain_rockettile_trace_source_out_insns_0_cause_0; // @[ClockDomain.scala:14:9]
assign auto_element_reset_domain_rockettile_trace_source_out_insns_0_tval = auto_element_reset_domain_rockettile_trace_source_out_insns_0_tval_0; // @[ClockDomain.scala:14:9]
assign auto_element_reset_domain_rockettile_trace_source_out_time = auto_element_reset_domain_rockettile_trace_source_out_time_0; // @[ClockDomain.scala:14:9]
assign auto_tl_master_clock_xing_out_a_valid = auto_tl_master_clock_xing_out_a_valid_0; // @[ClockDomain.scala:14:9]
assign auto_tl_master_clock_xing_out_a_bits_opcode = auto_tl_master_clock_xing_out_a_bits_opcode_0; // @[ClockDomain.scala:14:9]
assign auto_tl_master_clock_xing_out_a_bits_param = auto_tl_master_clock_xing_out_a_bits_param_0; // @[ClockDomain.scala:14:9]
assign auto_tl_master_clock_xing_out_a_bits_size = auto_tl_master_clock_xing_out_a_bits_size_0; // @[ClockDomain.scala:14:9]
assign auto_tl_master_clock_xing_out_a_bits_source = auto_tl_master_clock_xing_out_a_bits_source_0; // @[ClockDomain.scala:14:9]
assign auto_tl_master_clock_xing_out_a_bits_address = auto_tl_master_clock_xing_out_a_bits_address_0; // @[ClockDomain.scala:14:9]
assign auto_tl_master_clock_xing_out_a_bits_mask = auto_tl_master_clock_xing_out_a_bits_mask_0; // @[ClockDomain.scala:14:9]
assign auto_tl_master_clock_xing_out_a_bits_data = auto_tl_master_clock_xing_out_a_bits_data_0; // @[ClockDomain.scala:14:9]
assign auto_tl_master_clock_xing_out_a_bits_corrupt = auto_tl_master_clock_xing_out_a_bits_corrupt_0; // @[ClockDomain.scala:14:9]
assign auto_tl_master_clock_xing_out_b_ready = auto_tl_master_clock_xing_out_b_ready_0; // @[ClockDomain.scala:14:9]
assign auto_tl_master_clock_xing_out_c_valid = auto_tl_master_clock_xing_out_c_valid_0; // @[ClockDomain.scala:14:9]
assign auto_tl_master_clock_xing_out_c_bits_opcode = auto_tl_master_clock_xing_out_c_bits_opcode_0; // @[ClockDomain.scala:14:9]
assign auto_tl_master_clock_xing_out_c_bits_param = auto_tl_master_clock_xing_out_c_bits_param_0; // @[ClockDomain.scala:14:9]
assign auto_tl_master_clock_xing_out_c_bits_size = auto_tl_master_clock_xing_out_c_bits_size_0; // @[ClockDomain.scala:14:9]
assign auto_tl_master_clock_xing_out_c_bits_source = auto_tl_master_clock_xing_out_c_bits_source_0; // @[ClockDomain.scala:14:9]
assign auto_tl_master_clock_xing_out_c_bits_address = auto_tl_master_clock_xing_out_c_bits_address_0; // @[ClockDomain.scala:14:9]
assign auto_tl_master_clock_xing_out_c_bits_data = auto_tl_master_clock_xing_out_c_bits_data_0; // @[ClockDomain.scala:14:9]
assign auto_tl_master_clock_xing_out_c_bits_corrupt = auto_tl_master_clock_xing_out_c_bits_corrupt_0; // @[ClockDomain.scala:14:9]
assign auto_tl_master_clock_xing_out_d_ready = auto_tl_master_clock_xing_out_d_ready_0; // @[ClockDomain.scala:14:9]
assign auto_tl_master_clock_xing_out_e_valid = auto_tl_master_clock_xing_out_e_valid_0; // @[ClockDomain.scala:14:9]
assign auto_tl_master_clock_xing_out_e_bits_sink = auto_tl_master_clock_xing_out_e_bits_sink_0; // @[ClockDomain.scala:14:9]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File Periphery.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.devices.debug
import chisel3._
import chisel3.experimental.{noPrefix, IntParam}
import chisel3.util._
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy.lazymodule._
import freechips.rocketchip.amba.apb.{APBBundle, APBBundleParameters, APBMasterNode, APBMasterParameters, APBMasterPortParameters}
import freechips.rocketchip.interrupts.{IntSyncXbar, NullIntSyncSource}
import freechips.rocketchip.jtag.JTAGIO
import freechips.rocketchip.prci.{ClockSinkNode, ClockSinkParameters}
import freechips.rocketchip.subsystem.{BaseSubsystem, CBUS, FBUS, ResetSynchronous, SubsystemResetSchemeKey, TLBusWrapperLocation}
import freechips.rocketchip.tilelink.{TLFragmenter, TLWidthWidget}
import freechips.rocketchip.util.{AsyncResetSynchronizerShiftReg, CanHavePSDTestModeIO, ClockGate, PSDTestMode, PlusArg, ResetSynchronizerShiftReg}
import freechips.rocketchip.util.BooleanToAugmentedBoolean
/** Protocols used for communicating with external debugging tools */
sealed trait DebugExportProtocol
case object DMI extends DebugExportProtocol
case object JTAG extends DebugExportProtocol
case object CJTAG extends DebugExportProtocol
case object APB extends DebugExportProtocol
/** Options for possible debug interfaces */
case class DebugAttachParams(
protocols: Set[DebugExportProtocol] = Set(DMI),
externalDisable: Boolean = false,
masterWhere: TLBusWrapperLocation = FBUS,
slaveWhere: TLBusWrapperLocation = CBUS
) {
def dmi = protocols.contains(DMI)
def jtag = protocols.contains(JTAG)
def cjtag = protocols.contains(CJTAG)
def apb = protocols.contains(APB)
}
case object ExportDebug extends Field(DebugAttachParams())
class ClockedAPBBundle(params: APBBundleParameters) extends APBBundle(params) {
val clock = Clock()
val reset = Reset()
}
class DebugIO(implicit val p: Parameters) extends Bundle {
val clock = Input(Clock())
val reset = Input(Reset())
val clockeddmi = p(ExportDebug).dmi.option(Flipped(new ClockedDMIIO()))
val systemjtag = p(ExportDebug).jtag.option(new SystemJTAGIO)
val apb = p(ExportDebug).apb.option(Flipped(new ClockedAPBBundle(APBBundleParameters(addrBits=12, dataBits=32))))
//------------------------------
val ndreset = Output(Bool())
val dmactive = Output(Bool())
val dmactiveAck = Input(Bool())
val extTrigger = (p(DebugModuleKey).get.nExtTriggers > 0).option(new DebugExtTriggerIO())
val disableDebug = p(ExportDebug).externalDisable.option(Input(Bool()))
}
class PSDIO(implicit val p: Parameters) extends Bundle with CanHavePSDTestModeIO {
}
class ResetCtrlIO(val nComponents: Int)(implicit val p: Parameters) extends Bundle {
val hartResetReq = (p(DebugModuleKey).exists(x=>x.hasHartResets)).option(Output(Vec(nComponents, Bool())))
val hartIsInReset = Input(Vec(nComponents, Bool()))
}
/** Either adds a JTAG DTM to system, and exports a JTAG interface,
* or exports the Debug Module Interface (DMI), or exports and hooks up APB,
* based on a global parameter.
*/
trait HasPeripheryDebug { this: BaseSubsystem =>
private lazy val tlbus = locateTLBusWrapper(p(ExportDebug).slaveWhere)
lazy val debugCustomXbarOpt = p(DebugModuleKey).map(params => LazyModule( new DebugCustomXbar(outputRequiresInput = false)))
lazy val apbDebugNodeOpt = p(ExportDebug).apb.option(APBMasterNode(Seq(APBMasterPortParameters(Seq(APBMasterParameters("debugAPB"))))))
val debugTLDomainOpt = p(DebugModuleKey).map { _ =>
val domain = ClockSinkNode(Seq(ClockSinkParameters()))
domain := tlbus.fixedClockNode
domain
}
lazy val debugOpt = p(DebugModuleKey).map { params =>
val tlDM = LazyModule(new TLDebugModule(tlbus.beatBytes))
tlDM.node := tlbus.coupleTo("debug"){ TLFragmenter(tlbus.beatBytes, tlbus.blockBytes, nameSuffix = Some("Debug")) := _ }
tlDM.dmInner.dmInner.customNode := debugCustomXbarOpt.get.node
(apbDebugNodeOpt zip tlDM.apbNodeOpt) foreach { case (master, slave) =>
slave := master
}
tlDM.dmInner.dmInner.sb2tlOpt.foreach { sb2tl =>
locateTLBusWrapper(p(ExportDebug).masterWhere).coupleFrom("debug_sb") {
_ := TLWidthWidget(1) := sb2tl.node
}
}
tlDM
}
val debugNode = debugOpt.map(_.intnode)
val psd = InModuleBody {
val psd = IO(new PSDIO)
psd
}
val resetctrl = InModuleBody {
debugOpt.map { debug =>
debug.module.io.tl_reset := debugTLDomainOpt.get.in.head._1.reset
debug.module.io.tl_clock := debugTLDomainOpt.get.in.head._1.clock
val resetctrl = IO(new ResetCtrlIO(debug.dmOuter.dmOuter.intnode.edges.out.size))
debug.module.io.hartIsInReset := resetctrl.hartIsInReset
resetctrl.hartResetReq.foreach { rcio => debug.module.io.hartResetReq.foreach { rcdm => rcio := rcdm }}
resetctrl
}
}
// noPrefix is workaround https://github.com/freechipsproject/chisel3/issues/1603
val debug = InModuleBody { noPrefix(debugOpt.map { debugmod =>
val debug = IO(new DebugIO)
require(!(debug.clockeddmi.isDefined && debug.systemjtag.isDefined),
"You cannot have both DMI and JTAG interface in HasPeripheryDebug")
require(!(debug.clockeddmi.isDefined && debug.apb.isDefined),
"You cannot have both DMI and APB interface in HasPeripheryDebug")
require(!(debug.systemjtag.isDefined && debug.apb.isDefined),
"You cannot have both APB and JTAG interface in HasPeripheryDebug")
debug.clockeddmi.foreach { dbg => debugmod.module.io.dmi.get <> dbg }
(debug.apb
zip apbDebugNodeOpt
zip debugmod.module.io.apb_clock
zip debugmod.module.io.apb_reset).foreach {
case (((io, apb), c ), r) =>
apb.out(0)._1 <> io
c:= io.clock
r:= io.reset
}
debugmod.module.io.debug_reset := debug.reset
debugmod.module.io.debug_clock := debug.clock
debug.ndreset := debugmod.module.io.ctrl.ndreset
debug.dmactive := debugmod.module.io.ctrl.dmactive
debugmod.module.io.ctrl.dmactiveAck := debug.dmactiveAck
debug.extTrigger.foreach { x => debugmod.module.io.extTrigger.foreach {y => x <> y}}
// TODO in inheriting traits: Set this to something meaningful, e.g. "component is in reset or powered down"
debugmod.module.io.ctrl.debugUnavail.foreach { _ := false.B }
debug
})}
val dtm = InModuleBody { debug.flatMap(_.systemjtag.map(instantiateJtagDTM(_))) }
def instantiateJtagDTM(sj: SystemJTAGIO): DebugTransportModuleJTAG = {
val dtm = Module(new DebugTransportModuleJTAG(p(DebugModuleKey).get.nDMIAddrSize, p(JtagDTMKey)))
dtm.io.jtag <> sj.jtag
debug.map(_.disableDebug.foreach { x => dtm.io.jtag.TMS := sj.jtag.TMS | x }) // force TMS high when debug is disabled
dtm.io.jtag_clock := sj.jtag.TCK
dtm.io.jtag_reset := sj.reset
dtm.io.jtag_mfr_id := sj.mfr_id
dtm.io.jtag_part_number := sj.part_number
dtm.io.jtag_version := sj.version
dtm.rf_reset := sj.reset
debugOpt.map { outerdebug =>
outerdebug.module.io.dmi.get.dmi <> dtm.io.dmi
outerdebug.module.io.dmi.get.dmiClock := sj.jtag.TCK
outerdebug.module.io.dmi.get.dmiReset := sj.reset
}
dtm
}
}
/** BlackBox to export DMI interface */
class SimDTM(implicit p: Parameters) extends BlackBox with HasBlackBoxResource {
val io = IO(new Bundle {
val clk = Input(Clock())
val reset = Input(Bool())
val debug = new DMIIO
val exit = Output(UInt(32.W))
})
def connect(tbclk: Clock, tbreset: Bool, dutio: ClockedDMIIO, tbsuccess: Bool) = {
io.clk := tbclk
io.reset := tbreset
dutio.dmi <> io.debug
dutio.dmiClock := tbclk
dutio.dmiReset := tbreset
tbsuccess := io.exit === 1.U
assert(io.exit < 2.U, "*** FAILED *** (exit code = %d)\n", io.exit >> 1.U)
}
addResource("/vsrc/SimDTM.v")
addResource("/csrc/SimDTM.cc")
}
/** BlackBox to export JTAG interface */
class SimJTAG(tickDelay: Int = 50) extends BlackBox(Map("TICK_DELAY" -> IntParam(tickDelay)))
with HasBlackBoxResource {
val io = IO(new Bundle {
val clock = Input(Clock())
val reset = Input(Bool())
val jtag = new JTAGIO(hasTRSTn = true)
val enable = Input(Bool())
val init_done = Input(Bool())
val exit = Output(UInt(32.W))
})
def connect(dutio: JTAGIO, tbclock: Clock, tbreset: Bool, init_done: Bool, tbsuccess: Bool) = {
dutio.TCK := io.jtag.TCK
dutio.TMS := io.jtag.TMS
dutio.TDI := io.jtag.TDI
io.jtag.TDO := dutio.TDO
io.clock := tbclock
io.reset := tbreset
io.enable := PlusArg("jtag_rbb_enable", 0, "Enable SimJTAG for JTAG Connections. Simulation will pause until connection is made.")
io.init_done := init_done
// Success is determined by the gdbserver
// which is controlling this simulation.
tbsuccess := io.exit === 1.U
assert(io.exit < 2.U, "*** FAILED *** (exit code = %d)\n", io.exit >> 1.U)
}
addResource("/vsrc/SimJTAG.v")
addResource("/csrc/SimJTAG.cc")
addResource("/csrc/remote_bitbang.h")
addResource("/csrc/remote_bitbang.cc")
}
object Debug {
def connectDebug(
debugOpt: Option[DebugIO],
resetctrlOpt: Option[ResetCtrlIO],
psdio: PSDIO,
c: Clock,
r: Bool,
out: Bool,
tckHalfPeriod: Int = 2,
cmdDelay: Int = 2,
psd: PSDTestMode = 0.U.asTypeOf(new PSDTestMode()))
(implicit p: Parameters): Unit = {
connectDebugClockAndReset(debugOpt, c)
resetctrlOpt.map { rcio => rcio.hartIsInReset.map { _ := r }}
debugOpt.map { debug =>
debug.clockeddmi.foreach { d =>
val dtm = Module(new SimDTM).connect(c, r, d, out)
}
debug.systemjtag.foreach { sj =>
val jtag = Module(new SimJTAG(tickDelay=3)).connect(sj.jtag, c, r, ~r, out)
sj.reset := r.asAsyncReset
sj.mfr_id := p(JtagDTMKey).idcodeManufId.U(11.W)
sj.part_number := p(JtagDTMKey).idcodePartNum.U(16.W)
sj.version := p(JtagDTMKey).idcodeVersion.U(4.W)
}
debug.apb.foreach { apb =>
require(false, "No support for connectDebug for an APB debug connection.")
}
psdio.psd.foreach { _ <> psd }
debug.disableDebug.foreach { x => x := false.B }
}
}
def connectDebugClockAndReset(debugOpt: Option[DebugIO], c: Clock, sync: Boolean = true)(implicit p: Parameters): Unit = {
debugOpt.foreach { debug =>
val dmi_reset = debug.clockeddmi.map(_.dmiReset.asBool).getOrElse(false.B) |
debug.systemjtag.map(_.reset.asBool).getOrElse(false.B) |
debug.apb.map(_.reset.asBool).getOrElse(false.B)
connectDebugClockHelper(debug, dmi_reset, c, sync)
}
}
def connectDebugClockHelper(debug: DebugIO, dmi_reset: Reset, c: Clock, sync: Boolean = true)(implicit p: Parameters): Unit = {
val debug_reset = Wire(Bool())
withClockAndReset(c, dmi_reset) {
val debug_reset_syncd = if(sync) ~AsyncResetSynchronizerShiftReg(in=true.B, sync=3, name=Some("debug_reset_sync")) else dmi_reset
debug_reset := debug_reset_syncd
}
// Need to clock DM during debug_reset because of synchronous reset, so keep
// the clock alive for one cycle after debug_reset asserts to action this behavior.
// The unit should also be clocked when dmactive is high.
withClockAndReset(c, debug_reset.asAsyncReset) {
val dmactiveAck = if (sync) ResetSynchronizerShiftReg(in=debug.dmactive, sync=3, name=Some("dmactiveAck")) else debug.dmactive
val clock_en = RegNext(next=dmactiveAck, init=true.B)
val gated_clock =
if (!p(DebugModuleKey).get.clockGate) c
else ClockGate(c, clock_en, "debug_clock_gate")
debug.clock := gated_clock
debug.reset := (if (p(SubsystemResetSchemeKey)==ResetSynchronous) debug_reset else debug_reset.asAsyncReset)
debug.dmactiveAck := dmactiveAck
}
}
def tieoffDebug(debugOpt: Option[DebugIO], resetctrlOpt: Option[ResetCtrlIO] = None, psdio: Option[PSDIO] = None)(implicit p: Parameters): Bool = {
psdio.foreach(_.psd.foreach { _ <> 0.U.asTypeOf(new PSDTestMode()) } )
resetctrlOpt.map { rcio => rcio.hartIsInReset.map { _ := false.B }}
debugOpt.map { debug =>
debug.clock := true.B.asClock
debug.reset := (if (p(SubsystemResetSchemeKey)==ResetSynchronous) true.B else true.B.asAsyncReset)
debug.systemjtag.foreach { sj =>
sj.jtag.TCK := true.B.asClock
sj.jtag.TMS := true.B
sj.jtag.TDI := true.B
sj.jtag.TRSTn.foreach { r => r := true.B }
sj.reset := true.B.asAsyncReset
sj.mfr_id := 0.U
sj.part_number := 0.U
sj.version := 0.U
}
debug.clockeddmi.foreach { d =>
d.dmi.req.valid := false.B
d.dmi.req.bits.addr := 0.U
d.dmi.req.bits.data := 0.U
d.dmi.req.bits.op := 0.U
d.dmi.resp.ready := true.B
d.dmiClock := false.B.asClock
d.dmiReset := true.B.asAsyncReset
}
debug.apb.foreach { apb =>
apb.clock := false.B.asClock
apb.reset := true.B.asAsyncReset
apb.pready := false.B
apb.pslverr := false.B
apb.prdata := 0.U
apb.pduser := 0.U.asTypeOf(chiselTypeOf(apb.pduser))
apb.psel := false.B
apb.penable := false.B
}
debug.extTrigger.foreach { t =>
t.in.req := false.B
t.out.ack := t.out.req
}
debug.disableDebug.foreach { x => x := false.B }
debug.dmactiveAck := false.B
debug.ndreset
}.getOrElse(false.B)
}
}
File ResetCatchAndSync.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.{withClockAndReset, withReset}
/** Reset: asynchronous assert,
* synchronous de-assert
*
*/
class ResetCatchAndSync (sync: Int = 3) extends Module {
override def desiredName = s"ResetCatchAndSync_d${sync}"
val io = IO(new Bundle {
val sync_reset = Output(Bool())
val psd = Input(new PSDTestMode())
})
// Bypass both the resets to the flops themselves (to prevent DFT holes on
// those flops) and on the output of the synchronizer circuit (to control
// reset to any flops this circuit drives).
val post_psd_reset = Mux(io.psd.test_mode, io.psd.test_mode_reset, reset.asBool)
withReset(post_psd_reset) {
io.sync_reset := Mux(io.psd.test_mode, io.psd.test_mode_reset,
~AsyncResetSynchronizerShiftReg(true.B, sync))
}
}
object ResetCatchAndSync {
def apply(clk: Clock, rst: Bool, sync: Int = 3, name: Option[String] = None,
psd: Option[PSDTestMode] = None): Bool = {
withClockAndReset(clk, rst) {
val catcher = Module (new ResetCatchAndSync(sync))
if (name.isDefined) {catcher.suggestName(name.get)}
catcher.io.psd <> psd.getOrElse(WireDefault(0.U.asTypeOf(new PSDTestMode())))
catcher.io.sync_reset
}
}
def apply(clk: Clock, rst: Bool, sync: Int, name: String): Bool = apply(clk, rst, sync, Some(name))
def apply(clk: Clock, rst: Bool, name: String): Bool = apply(clk, rst, name = Some(name))
def apply(clk: Clock, rst: Bool, sync: Int, name: String, psd: PSDTestMode): Bool =
apply(clk, rst, sync, Some(name), Some(psd))
def apply(clk: Clock, rst: Bool, name: String, psd: PSDTestMode): Bool =
apply(clk, rst, name = Some(name), psd = Some(psd))
}
File ShiftReg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
// Similar to the Chisel ShiftRegister but allows the user to suggest a
// name to the registers that get instantiated, and
// to provide a reset value.
object ShiftRegInit {
def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T =
(0 until n).foldRight(in) {
case (i, next) => {
val r = RegNext(next, init)
name.foreach { na => r.suggestName(s"${na}_${i}") }
r
}
}
}
/** These wrap behavioral
* shift registers into specific modules to allow for
* backend flows to replace or constrain
* them properly when used for CDC synchronization,
* rather than buffering.
*
* The different types vary in their reset behavior:
* AsyncResetShiftReg -- Asynchronously reset register array
* A W(width) x D(depth) sized array is constructed from D instantiations of a
* W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg,
* but only used for timing applications
*/
abstract class AbstractPipelineReg(w: Int = 1) extends Module {
val io = IO(new Bundle {
val d = Input(UInt(w.W))
val q = Output(UInt(w.W))
}
)
}
object AbstractPipelineReg {
def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = {
val chain = Module(gen)
name.foreach{ chain.suggestName(_) }
chain.io.d := in.asUInt
chain.io.q.asTypeOf(in)
}
}
class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) {
require(depth > 0, "Depth must be greater than 0.")
override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}"
val chain = List.tabulate(depth) { i =>
Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}")
}
chain.last.io.d := io.d
chain.last.io.en := true.B
(chain.init zip chain.tail).foreach { case (sink, source) =>
sink.io.d := source.io.q
sink.io.en := true.B
}
io.q := chain.head.io.q
}
object AsyncResetShiftReg {
def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T =
AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name)
def apply [T <: Data](in: T, depth: Int, name: Option[String]): T =
apply(in, depth, 0, name)
def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T =
apply(in, depth, init.litValue.toInt, name)
def apply [T <: Data](in: T, depth: Int, init: T): T =
apply (in, depth, init.litValue.toInt, None)
}
File IOCell.scala:
// See LICENSE for license details
package chipyard.iocell
import chisel3._
import chisel3.util.{Cat, HasBlackBoxInline}
import chisel3.reflect.DataMirror
import chisel3.experimental.{Analog, BaseModule}
// The following four IO cell bundle types are bare-minimum functional connections
// for modeling 4 different IO cell scenarios. The intention is that the user
// would create wrapper modules that extend these interfaces with additional
// control signals. These are loosely similar to the sifive-blocks PinCtrl bundles
// (https://github.com/sifive/sifive-blocks/blob/master/src/main/scala/devices/pinctrl/PinCtrl.scala),
// but we want to avoid a dependency on an external libraries.
/** The base IO bundle for an analog signal (typically something with no digital buffers inside)
* pad: off-chip (external) connection
* core: internal connection
*/
class AnalogIOCellBundle extends Bundle {
val pad = Analog(1.W) // Pad/bump signal (off-chip)
val core = Analog(1.W) // core signal (on-chip)
}
/** The base IO bundle for a signal with runtime-controllable direction
* pad: off-chip (external) connection
* i: input to chip logic (output from IO cell)
* ie: enable signal for i
* o: output from chip logic (input to IO cell)
* oe: enable signal for o
*/
class DigitalGPIOCellBundle extends Bundle {
val pad = Analog(1.W)
val i = Output(Bool())
val ie = Input(Bool())
val o = Input(Bool())
val oe = Input(Bool())
}
/** The base IO bundle for a digital output signal
* pad: off-chip (external) connection
* o: output from chip logic (input to IO cell)
* oe: enable signal for o
*/
class DigitalOutIOCellBundle extends Bundle {
val pad = Output(Bool())
val o = Input(Bool())
val oe = Input(Bool())
}
/** The base IO bundle for a digital input signal
* pad: off-chip (external) connection
* i: input to chip logic (output from IO cell)
* ie: enable signal for i
*/
class DigitalInIOCellBundle extends Bundle {
val pad = Input(Bool())
val i = Output(Bool())
val ie = Input(Bool())
}
trait IOCell extends BaseModule {
var iocell_name: Option[String] = None
/** Set IOCell name
* @param s Proposed name for the IOCell
*
* @return An inherited IOCell with given the proposed name
*/
def suggestName(s: String): this.type = {
iocell_name = Some(s)
super.suggestName(s)
}
}
trait AnalogIOCell extends IOCell {
val io: AnalogIOCellBundle
}
trait DigitalGPIOCell extends IOCell {
val io: DigitalGPIOCellBundle
}
trait DigitalInIOCell extends IOCell {
val io: DigitalInIOCellBundle
}
trait DigitalOutIOCell extends IOCell {
val io: DigitalOutIOCellBundle
}
// The following Generic IO cell black boxes have verilog models that mimic a very simple
// implementation of an IO cell. For building a real chip, it is important to implement
// and use similar classes which wrap the foundry-specific IO cells.
abstract class GenericIOCell extends BlackBox with HasBlackBoxInline {
val impl: String
val moduleName = this.getClass.getSimpleName
setInline(s"$moduleName.v", impl);
}
class GenericAnalogIOCell extends GenericIOCell with AnalogIOCell {
val io = IO(new AnalogIOCellBundle)
lazy val impl = s"""
`timescale 1ns/1ps
module GenericAnalogIOCell(
inout pad,
inout core
);
assign core = 1'bz;
assign pad = core;
endmodule"""
}
class GenericDigitalGPIOCell extends GenericIOCell with DigitalGPIOCell {
val io = IO(new DigitalGPIOCellBundle)
lazy val impl = s"""
`timescale 1ns/1ps
module GenericDigitalGPIOCell(
inout pad,
output i,
input ie,
input o,
input oe
);
assign pad = oe ? o : 1'bz;
assign i = ie ? pad : 1'b0;
endmodule"""
}
class GenericDigitalInIOCell extends GenericIOCell with DigitalInIOCell {
val io = IO(new DigitalInIOCellBundle)
lazy val impl = s"""
`timescale 1ns/1ps
module GenericDigitalInIOCell(
input pad,
output i,
input ie
);
assign i = ie ? pad : 1'b0;
endmodule"""
}
class GenericDigitalOutIOCell extends GenericIOCell with DigitalOutIOCell {
val io = IO(new DigitalOutIOCellBundle)
lazy val impl = s"""
`timescale 1ns/1ps
module GenericDigitalOutIOCell(
output pad,
input o,
input oe
);
assign pad = oe ? o : 1'bz;
endmodule"""
}
trait IOCellTypeParams {
def analog(): AnalogIOCell
def gpio(): DigitalGPIOCell
def input(): DigitalInIOCell
def output(): DigitalOutIOCell
}
case class GenericIOCellParams() extends IOCellTypeParams {
def analog() = Module(new GenericAnalogIOCell)
def gpio() = Module(new GenericDigitalGPIOCell)
def input() = Module(new GenericDigitalInIOCell)
def output() = Module(new GenericDigitalOutIOCell)
}
object IOCell {
/** From within a RawModule or MultiIOModule context, generate new module IOs from a given
* signal and return the new IO and a Seq containing all generated IO cells.
* @param coreSignal The signal onto which to add IO cells
* @param name An optional name or name prefix to use for naming IO cells
* @param abstractResetAsAsync When set, will coerce abstract resets to
* AsyncReset, and otherwise to Bool (sync reset)
* @return A tuple of (the generated IO data node, a Seq of all generated IO cell instances)
*/
def generateIOFromSignal[T <: Data](
coreSignal: T,
name: String,
typeParams: IOCellTypeParams = GenericIOCellParams(),
abstractResetAsAsync: Boolean = false
): (T, Seq[IOCell]) = {
val padSignal = IO(DataMirror.internal.chiselTypeClone[T](coreSignal)).suggestName(name)
val resetFn = if (abstractResetAsAsync) toAsyncReset else toSyncReset
val iocells = IOCell.generateFromSignal(coreSignal, padSignal, Some(s"iocell_$name"), typeParams, resetFn)
(padSignal, iocells)
}
/** Connect two identical signals together by adding IO cells between them and return a Seq
* containing all generated IO cells.
* @param coreSignal The core-side (internal) signal onto which to connect/add IO cells
* @param padSignal The pad-side (external) signal onto which to connect IO cells
* @param name An optional name or name prefix to use for naming IO cells
* @return A Seq of all generated IO cell instances
*/
val toSyncReset: (Reset) => Bool = _.asBool
val toAsyncReset: (Reset) => AsyncReset = _.asAsyncReset
def generateFromSignal[T <: Data, R <: Reset](
coreSignal: T,
padSignal: T,
name: Option[String] = None,
typeParams: IOCellTypeParams = GenericIOCellParams(),
concretizeResetFn: (Reset) => R = toSyncReset
): Seq[IOCell] = {
def genCell[T <: Data](
castToBool: (T) => Bool,
castFromBool: (Bool) => T
)(coreSignal: T,
padSignal: T
): Seq[IOCell] = {
DataMirror.directionOf(coreSignal) match {
case ActualDirection.Input => {
val iocell = typeParams.input()
name.foreach(n => {
iocell.suggestName(n)
})
coreSignal := castFromBool(iocell.io.i)
iocell.io.ie := true.B
iocell.io.pad := castToBool(padSignal)
Seq(iocell)
}
case ActualDirection.Output => {
val iocell = typeParams.output()
name.foreach(n => {
iocell.suggestName(n)
})
iocell.io.o := castToBool(coreSignal)
iocell.io.oe := true.B
padSignal := castFromBool(iocell.io.pad)
Seq(iocell)
}
case _ => throw new Exception(s"Signal does not have a direction and cannot be matched to an IOCell")
}
}
def genCellForClock = genCell[Clock](_.asUInt.asBool, _.asClock) _
def genCellForAsyncReset = genCell[AsyncReset](_.asBool, _.asAsyncReset) _
def genCellForAbstractReset = genCell[Reset](_.asBool, concretizeResetFn) _
(coreSignal, padSignal) match {
case (coreSignal: Analog, padSignal: Analog) => {
if (coreSignal.getWidth == 0) {
Seq()
} else {
require(
coreSignal.getWidth == 1,
"Analogs wider than 1 bit are not supported because we can't bit-select Analogs (https://github.com/freechipsproject/chisel3/issues/536)"
)
val iocell = typeParams.analog()
name.foreach(n => iocell.suggestName(n))
iocell.io.core <> coreSignal
padSignal <> iocell.io.pad
Seq(iocell)
}
}
case (coreSignal: Clock, padSignal: Clock) => genCellForClock(coreSignal, padSignal)
case (coreSignal: AsyncReset, padSignal: AsyncReset) => genCellForAsyncReset(coreSignal, padSignal)
case (coreSignal: Bits, padSignal: Bits) => {
require(padSignal.getWidth == coreSignal.getWidth, "padSignal and coreSignal must be the same width")
if (padSignal.getWidth == 0) {
// This dummy assignment will prevent invalid firrtl from being emitted
DataMirror.directionOf(coreSignal) match {
case ActualDirection.Input => coreSignal := 0.U
case _ => {}
}
Seq()
} else {
DataMirror.directionOf(coreSignal) match {
case ActualDirection.Input => {
val iocells = padSignal.asBools.zipWithIndex.map { case (sig, i) =>
val iocell = typeParams.input()
// Note that we are relying on chisel deterministically naming this in the index order (which it does)
// This has the side-effect of naming index 0 with no _0 suffix, which is how chisel names other signals
// An alternative solution would be to suggestName(n + "_" + i)
name.foreach(n => {
iocell.suggestName(n)
})
iocell.io.pad := sig
iocell.io.ie := true.B
iocell
}
// Note that the reverse here is because Cat(Seq(a,b,c,d)) yields abcd, but a is index 0 of the Seq
coreSignal := Cat(iocells.map(_.io.i).reverse)
iocells
}
case ActualDirection.Output => {
val iocells = coreSignal.asBools.zipWithIndex.map { case (sig, i) =>
val iocell = typeParams.output()
// Note that we are relying on chisel deterministically naming this in the index order (which it does)
// This has the side-effect of naming index 0 with no _0 suffix, which is how chisel names other signals
// An alternative solution would be to suggestName(n + "_" + i)
name.foreach(n => {
iocell.suggestName(n)
})
iocell.io.o := sig
iocell.io.oe := true.B
iocell
}
// Note that the reverse here is because Cat(Seq(a,b,c,d)) yields abcd, but a is index 0 of the Seq
padSignal := Cat(iocells.map(_.io.pad).reverse)
iocells
}
case _ => throw new Exception("Bits signal does not have a direction and cannot be matched to IOCell(s)")
}
}
}
case (coreSignal: Reset, padSignal: Reset) => genCellForAbstractReset(coreSignal, padSignal)
case (coreSignal: Vec[_], padSignal: Vec[_]) => {
require(padSignal.size == coreSignal.size, "size of Vec for padSignal and coreSignal must be the same")
coreSignal.zip(padSignal).zipWithIndex.foldLeft(Seq.empty[IOCell]) { case (total, ((core, pad), i)) =>
val ios = IOCell.generateFromSignal(core, pad, name.map(_ + "_" + i), typeParams)
total ++ ios
}
}
case (coreSignal: Record, padSignal: Record) => {
coreSignal.elements.foldLeft(Seq.empty[IOCell]) { case (total, (eltName, core)) =>
val pad = padSignal.elements(eltName)
val ios = IOCell.generateFromSignal(core, pad, name.map(_ + "_" + eltName), typeParams)
total ++ ios
}
}
case _ => { throw new Exception("Oops, I don't know how to handle this signal.") }
}
}
}
File ChipTop.scala:
package chipyard
import chisel3._
import scala.collection.mutable.{ArrayBuffer}
import freechips.rocketchip.prci.{ClockGroupIdentityNode, ClockSinkParameters, ClockSinkNode, ClockGroup}
import org.chipsalliance.cde.config.{Parameters, Field}
import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp, LazyRawModuleImp, LazyModuleImpLike, BindingScope}
import freechips.rocketchip.util.{DontTouch}
import chipyard.iobinders._
import chipyard.iocell._
case object BuildSystem extends Field[Parameters => LazyModule]((p: Parameters) => new DigitalTop()(p))
/**
* The base class used for building chips. This constructor instantiates a module specified by the BuildSystem parameter,
* named "system", which is an instance of DigitalTop by default. The diplomatic clocks of System, as well as its implicit clock,
* is aggregated into the clockGroupNode. The parameterized functions controlled by ClockingSchemeKey and GlobalResetSchemeKey
* drive clock and reset generation
*/
class ChipTop(implicit p: Parameters) extends LazyModule with BindingScope
with HasIOBinders {
// The system module specified by BuildSystem
lazy val lazySystem = LazyModule(p(BuildSystem)(p)).suggestName("system")
// NOTE: Making this a LazyRawModule is moderately dangerous, as anonymous children
// of ChipTop (ex: ClockGroup) do not receive clock or reset.
// However. anonymous children of ChipTop should not need an implicit Clock or Reset
// anyways, they probably need to be explicitly clocked.
lazy val module: LazyModuleImpLike = new LazyRawModuleImp(this) with DontTouch { }
}
File ClockGate.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util.{HasBlackBoxResource, HasBlackBoxPath}
import org.chipsalliance.cde.config.{Field, Parameters}
import java.nio.file.{Files, Paths}
case object ClockGateImpl extends Field[() => ClockGate](() => new EICG_wrapper)
case object ClockGateModelFile extends Field[Option[String]](None)
abstract class ClockGate extends BlackBox
with HasBlackBoxResource with HasBlackBoxPath {
val io = IO(new Bundle{
val in = Input(Clock())
val test_en = Input(Bool())
val en = Input(Bool())
val out = Output(Clock())
})
def addVerilogResource(vsrc: String): Unit = {
if (Files.exists(Paths.get(vsrc)))
addPath(vsrc)
else
addResource(vsrc)
}
}
object ClockGate {
def apply[T <: ClockGate](
in: Clock,
en: Bool,
name: Option[String] = None)(implicit p: Parameters): Clock = {
val cg = Module(p(ClockGateImpl)())
name.foreach(cg.suggestName(_))
p(ClockGateModelFile).map(cg.addVerilogResource(_))
cg.io.in := in
cg.io.test_en := false.B
cg.io.en := en
cg.io.out
}
def apply[T <: ClockGate](
in: Clock,
en: Bool,
name: String)(implicit p: Parameters): Clock =
apply(in, en, Some(name))
}
// behavioral model of Integrated Clock Gating cell
class EICG_wrapper extends ClockGate
File IOBinders.scala:
package chipyard.iobinders
import chisel3._
import chisel3.reflect.DataMirror
import chisel3.experimental.Analog
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import org.chipsalliance.diplomacy.nodes._
import org.chipsalliance.diplomacy.aop._
import org.chipsalliance.diplomacy.lazymodule._
import org.chipsalliance.diplomacy.bundlebridge._
import freechips.rocketchip.diplomacy.{Resource, ResourceBinding, ResourceAddress, RegionType}
import freechips.rocketchip.devices.debug._
import freechips.rocketchip.jtag.{JTAGIO}
import freechips.rocketchip.subsystem._
import freechips.rocketchip.system.{SimAXIMem}
import freechips.rocketchip.amba.axi4.{AXI4Bundle, AXI4SlaveNode, AXI4MasterNode, AXI4EdgeParameters}
import freechips.rocketchip.util._
import freechips.rocketchip.prci._
import freechips.rocketchip.groundtest.{GroundTestSubsystemModuleImp, GroundTestSubsystem}
import freechips.rocketchip.tilelink.{TLBundle}
import sifive.blocks.devices.gpio._
import sifive.blocks.devices.uart._
import sifive.blocks.devices.spi._
import sifive.blocks.devices.i2c._
import tracegen.{TraceGenSystemModuleImp}
import chipyard.iocell._
import testchipip.serdes.{CanHavePeripheryTLSerial, SerialTLKey}
import testchipip.spi.{SPIChipIO}
import testchipip.boot.{CanHavePeripheryCustomBootPin}
import testchipip.soc.{CanHavePeripheryChipIdPin}
import testchipip.util.{ClockedIO}
import testchipip.iceblk.{CanHavePeripheryBlockDevice, BlockDeviceKey, BlockDeviceIO}
import testchipip.cosim.{CanHaveTraceIO, TraceOutputTop, SpikeCosimConfig}
import testchipip.tsi.{CanHavePeripheryUARTTSI, UARTTSIIO}
import icenet.{CanHavePeripheryIceNIC, SimNetwork, NicLoopback, NICKey, NICIOvonly}
import chipyard.{CanHaveMasterTLMemPort, ChipyardSystem, ChipyardSystemModule}
import chipyard.example.{CanHavePeripheryGCD}
import scala.reflect.{ClassTag}
object IOBinderTypes {
type IOBinderTuple = (Seq[Port[_]], Seq[IOCell])
type IOBinderFunction = (Boolean, => Any) => ModuleValue[IOBinderTuple]
}
import IOBinderTypes._
// System for instantiating binders based
// on the scala type of the Target (_not_ its IO). This avoids needing to
// duplicate harnesses (essentially test harnesses) for each target.
// IOBinders is map between string representations of traits to the desired
// IO connection behavior for tops matching that trait. We use strings to enable
// composition and overriding of IOBinders, much like how normal Keys in the config
// system are used/ At elaboration, the testharness traverses this set of functions,
// and functions which match the type of the DigitalTop are evaluated.
// You can add your own binder by adding a new (key, fn) pair, typically by using
// the OverrideIOBinder or ComposeIOBinder macros
case object IOBinders extends Field[Map[String, Seq[IOBinderFunction]]](
Map[String, Seq[IOBinderFunction]]().withDefaultValue(Nil)
)
abstract trait HasIOBinders extends HasChipyardPorts { this: LazyModule =>
val lazySystem: LazyModule
private val iobinders = p(IOBinders)
// Note: IOBinders cannot rely on the implicit clock/reset, as they may be called from the
// context of a LazyRawModuleImp
private val lzy = iobinders.map({ case (s,fns) => s -> fns.map(f => f(true, lazySystem)) })
private val imp = iobinders.map({ case (s,fns) => s -> fns.map(f => f(false, lazySystem.module)) })
private lazy val lzyFlattened: Map[String, IOBinderTuple] = lzy.map({
case (s,ms) => s -> (ms.map(_._1).flatten, ms.map(_._2).flatten)
})
private lazy val impFlattened: Map[String, IOBinderTuple] = imp.map({
case (s,ms) => s -> (ms.map(_._1).flatten, ms.map(_._2).flatten)
})
// A publicly accessible list of IO cells (useful for a floorplanning tool, for example)
val iocells = InModuleBody { (lzyFlattened.values ++ impFlattened.values).unzip._2.flatten.toBuffer }
// A mapping between stringified DigitalSystem traits and their corresponding ChipTop ports
val portMap = InModuleBody { iobinders.keys.map(k => k -> (lzyFlattened(k)._1 ++ impFlattened(k)._1)).toMap }
// A mapping between stringified DigitalSystem traits and their corresponding ChipTop iocells
val iocellMap = InModuleBody { iobinders.keys.map(k => k -> (lzyFlattened(k)._2 ++ impFlattened(k)._2)).toMap }
def ports = portMap.getWrappedValue.values.flatten.toSeq
InModuleBody {
println("IOCells generated by IOBinders:")
for ((k, v) <- iocellMap) {
if (!v.isEmpty) {
val cells = v.map(_.getClass.getSimpleName).groupBy(identity).mapValues(_.size)
println(s" IOBinder for $k generated:")
for ((t, c) <- cells) { println(s" $c X $t") }
}
}
println()
val totals = iocells.map(_.getClass.getSimpleName).groupBy(identity).mapValues(_.size)
println(s" Total generated ${iocells.size} IOCells:")
for ((t, c) <- totals) { println(s" $c X $t") }
}
}
// Note: The parameters instance is accessible only through LazyModule
// or LazyModuleImpLike. The self-type requirement in traits like
// CanHaveMasterAXI4MemPort is insufficient to make it accessible to the IOBinder
// As a result, IOBinders only work on Modules which inherit LazyModule or
// or LazyModuleImpLike
object GetSystemParameters {
def apply(s: Any): Parameters = {
s match {
case s: LazyModule => s.p
case s: LazyModuleImpLike => s.p
case _ => throw new Exception(s"Trying to get Parameters from a system that is not LazyModule or LazyModuleImpLike")
}
}
}
class IOBinder[T](composer: Seq[IOBinderFunction] => Seq[IOBinderFunction])(implicit tag: ClassTag[T]) extends Config((site, here, up) => {
case IOBinders => {
val upMap = up(IOBinders)
upMap + (tag.runtimeClass.toString -> composer(upMap(tag.runtimeClass.toString)))
}
})
class ConcreteIOBinder[T](composes: Boolean, fn: T => IOBinderTuple)(implicit tag: ClassTag[T]) extends IOBinder[T](
up => (if (composes) up else Nil) ++ Seq(((_, t) => { InModuleBody {
t match {
case system: T => fn(system)
case _ => (Nil, Nil)
}
}}): IOBinderFunction)
)
class LazyIOBinder[T](composes: Boolean, fn: T => ModuleValue[IOBinderTuple])(implicit tag: ClassTag[T]) extends IOBinder[T](
up => (if (composes) up else Nil) ++ Seq(((isLazy, t) => {
val empty = new ModuleValue[IOBinderTuple] {
def getWrappedValue: IOBinderTuple = (Nil, Nil)
}
if (isLazy) {
t match {
case system: T => fn(system)
case _ => empty
}
} else {
empty
}
}): IOBinderFunction)
)
// The "Override" binders override any previous IOBinders (lazy or concrete) defined on the same trait.
// The "Compose" binders do not override previously defined IOBinders on the same trait
// The default IOBinders evaluate only in the concrete "ModuleImp" phase of elaboration
// The "Lazy" IOBinders evaluate in the LazyModule phase, but can also generate hardware through InModuleBody
class OverrideIOBinder[T](fn: T => IOBinderTuple)(implicit tag: ClassTag[T]) extends ConcreteIOBinder[T](false, fn)
class ComposeIOBinder[T](fn: T => IOBinderTuple)(implicit tag: ClassTag[T]) extends ConcreteIOBinder[T](true, fn)
class OverrideLazyIOBinder[T](fn: T => ModuleValue[IOBinderTuple])(implicit tag: ClassTag[T]) extends LazyIOBinder[T](false, fn)
class ComposeLazyIOBinder[T](fn: T => ModuleValue[IOBinderTuple])(implicit tag: ClassTag[T]) extends LazyIOBinder[T](true, fn)
case object IOCellKey extends Field[IOCellTypeParams](GenericIOCellParams())
class WithGPIOCells extends OverrideIOBinder({
(system: HasPeripheryGPIO) => {
val (ports2d, cells2d) = system.gpio.zipWithIndex.map({ case (gpio, i) =>
gpio.pins.zipWithIndex.map({ case (pin, j) =>
val p = system.asInstanceOf[BaseSubsystem].p
val g = IO(Analog(1.W)).suggestName(s"gpio_${i}_${j}")
val iocell = p(IOCellKey).gpio().suggestName(s"iocell_gpio_${i}_${j}")
iocell.io.o := pin.o.oval
iocell.io.oe := pin.o.oe
iocell.io.ie := pin.o.ie
pin.i.ival := iocell.io.i
pin.i.po.foreach(_ := DontCare)
iocell.io.pad <> g
(GPIOPort(() => g, i, j), iocell)
}).unzip
}).unzip
(ports2d.flatten, cells2d.flatten)
}
})
class WithGPIOPunchthrough extends OverrideIOBinder({
(system: HasPeripheryGPIO) => {
val ports = system.gpio.zipWithIndex.map { case (gpio, i) =>
val io_gpio = IO(gpio.cloneType).suggestName(s"gpio_$i")
io_gpio <> gpio
GPIOPinsPort(() => io_gpio, i)
}
(ports, Nil)
}
})
class WithI2CPunchthrough extends OverrideIOBinder({
(system: HasPeripheryI2C) => {
val ports = system.i2c.zipWithIndex.map { case (i2c, i) =>
val io_i2c = IO(i2c.cloneType).suggestName(s"i2c_$i")
io_i2c <> i2c
I2CPort(() => i2c)
}
(ports, Nil)
}
})
// DOC include start: WithUARTIOCells
class WithUARTIOCells extends OverrideIOBinder({
(system: HasPeripheryUART) => {
val (ports: Seq[UARTPort], cells2d) = system.uart.zipWithIndex.map({ case (u, i) =>
val p = system.asInstanceOf[BaseSubsystem].p
val (port, ios) = IOCell.generateIOFromSignal(u, s"uart_${i}", p(IOCellKey), abstractResetAsAsync = true)
val where = PBUS // TODO fix
val bus = system.asInstanceOf[HasTileLinkLocations].locateTLBusWrapper(where)
val freqMHz = bus.dtsFrequency.get / 1000000
(UARTPort(() => port, i, freqMHz.toInt), ios)
}).unzip
(ports, cells2d.flatten)
}
})
// DOC include end: WithUARTIOCells
class WithSPIIOPunchthrough extends OverrideLazyIOBinder({
(system: HasPeripherySPI) => {
// attach resource to 1st SPI
if (system.tlSpiNodes.size > 0) ResourceBinding {
Resource(new MMCDevice(system.tlSpiNodes.head.device, 1), "reg").bind(ResourceAddress(0))
}
InModuleBody {
val spi = system.spi
val ports = spi.zipWithIndex.map({ case (s, i) =>
val io_spi = IO(s.cloneType).suggestName(s"spi_$i")
io_spi <> s
SPIPort(() => io_spi)
})
(ports, Nil)
}
}
})
class WithSPIFlashIOCells extends OverrideIOBinder({
(system: HasPeripherySPIFlash) => {
val (ports: Seq[SPIFlashPort], cells2d) = system.qspi.zipWithIndex.map({ case (s, i) =>
val p = system.asInstanceOf[BaseSubsystem].p
val name = s"spi_${i}"
val port = IO(new SPIChipIO(s.c.csWidth)).suggestName(name)
val iocellBase = s"iocell_${name}"
// SCK and CS are unidirectional outputs
val sckIOs = IOCell.generateFromSignal(s.sck, port.sck, Some(s"${iocellBase}_sck"), p(IOCellKey), IOCell.toAsyncReset)
val csIOs = IOCell.generateFromSignal(s.cs, port.cs, Some(s"${iocellBase}_cs"), p(IOCellKey), IOCell.toAsyncReset)
// DQ are bidirectional, so then need special treatment
val dqIOs = s.dq.zip(port.dq).zipWithIndex.map { case ((pin, ana), j) =>
val iocell = p(IOCellKey).gpio().suggestName(s"${iocellBase}_dq_${j}")
iocell.io.o := pin.o
iocell.io.oe := pin.oe
iocell.io.ie := true.B
pin.i := iocell.io.i
iocell.io.pad <> ana
iocell
}
(SPIFlashPort(() => port, p(PeripherySPIFlashKey)(i), i), dqIOs ++ csIOs ++ sckIOs)
}).unzip
(ports, cells2d.flatten)
}
})
class WithExtInterruptIOCells extends OverrideIOBinder({
(system: HasExtInterruptsModuleImp) => {
if (system.outer.nExtInterrupts > 0) {
val (port: UInt, cells) = IOCell.generateIOFromSignal(system.interrupts, "ext_interrupts", system.p(IOCellKey), abstractResetAsAsync = true)
(Seq(ExtIntPort(() => port)), cells)
} else {
system.interrupts := DontCare // why do I have to drive this 0-wide wire???
(Nil, Nil)
}
}
})
// Rocketchip's JTAGIO exposes the oe signal, which doesn't go off-chip
class JTAGChipIO extends Bundle {
val TCK = Input(Clock())
val TMS = Input(Bool())
val TDI = Input(Bool())
val TDO = Output(Bool())
}
// WARNING: Don't disable syncReset unless you are trying to
// get around bugs in RTL simulators
class WithDebugIOCells(syncReset: Boolean = true) extends OverrideLazyIOBinder({
(system: HasPeripheryDebug) => {
implicit val p = GetSystemParameters(system)
val tlbus = system.asInstanceOf[BaseSubsystem].locateTLBusWrapper(p(ExportDebug).slaveWhere)
val clockSinkNode = system.debugOpt.map(_ => ClockSinkNode(Seq(ClockSinkParameters())))
clockSinkNode.map(_ := tlbus.fixedClockNode)
def clockBundle = clockSinkNode.get.in.head._1
InModuleBody { system.asInstanceOf[BaseSubsystem] match { case system: HasPeripheryDebug => {
system.debug.map({ debug =>
// We never use the PSDIO, so tie it off on-chip
system.psd.psd.foreach { _ <> 0.U.asTypeOf(new PSDTestMode) }
system.resetctrl.map { rcio => rcio.hartIsInReset.map { _ := clockBundle.reset.asBool } }
system.debug.map { d =>
// Tie off extTrigger
d.extTrigger.foreach { t =>
t.in.req := false.B
t.out.ack := t.out.req
}
// Tie off disableDebug
d.disableDebug.foreach { d => d := false.B }
// Drive JTAG on-chip IOs
d.systemjtag.map { j =>
j.reset := (if (syncReset) ResetCatchAndSync(j.jtag.TCK, clockBundle.reset.asBool) else clockBundle.reset.asBool)
j.mfr_id := p(JtagDTMKey).idcodeManufId.U(11.W)
j.part_number := p(JtagDTMKey).idcodePartNum.U(16.W)
j.version := p(JtagDTMKey).idcodeVersion.U(4.W)
}
}
Debug.connectDebugClockAndReset(Some(debug), clockBundle.clock)
// Add IOCells for the DMI/JTAG/APB ports
val dmiTuple = debug.clockeddmi.map { d =>
val (port, cells) = IOCell.generateIOFromSignal(d, "dmi", p(IOCellKey), abstractResetAsAsync = true)
(DMIPort(() => port), cells)
}
val jtagTuple = debug.systemjtag.map { j =>
val jtag_wire = Wire(new JTAGChipIO)
j.jtag.TCK := jtag_wire.TCK
j.jtag.TMS := jtag_wire.TMS
j.jtag.TDI := jtag_wire.TDI
jtag_wire.TDO := j.jtag.TDO.data
val (port, cells) = IOCell.generateIOFromSignal(jtag_wire, "jtag", p(IOCellKey), abstractResetAsAsync = true)
(JTAGPort(() => port), cells)
}
require(!debug.apb.isDefined)
val allTuples = (dmiTuple ++ jtagTuple).toSeq
(allTuples.map(_._1).toSeq, allTuples.flatMap(_._2).toSeq)
}).getOrElse((Nil, Nil))
}}}
}
})
class WithSerialTLIOCells extends OverrideIOBinder({
(system: CanHavePeripheryTLSerial) => {
val (ports, cells) = system.serial_tls.zipWithIndex.map({ case (s, id) =>
val sys = system.asInstanceOf[BaseSubsystem]
val (port, cells) = IOCell.generateIOFromSignal(s.getWrappedValue, s"serial_tl_$id", sys.p(IOCellKey), abstractResetAsAsync = true)
(SerialTLPort(() => port, sys.p(SerialTLKey)(id), system.serdessers(id), id), cells)
}).unzip
(ports.toSeq, cells.flatten.toSeq)
}
})
class WithChipIdIOCells extends OverrideIOBinder({
(system: CanHavePeripheryChipIdPin) => system.chip_id_pin.map({ p =>
val sys = system.asInstanceOf[BaseSubsystem]
val (port, cells) = IOCell.generateIOFromSignal(p.getWrappedValue, s"chip_id", sys.p(IOCellKey), abstractResetAsAsync = true)
(Seq(ChipIdPort(() => port)), cells)
}).getOrElse(Nil, Nil)
})
class WithSerialTLPunchthrough extends OverrideIOBinder({
(system: CanHavePeripheryTLSerial) => {
val (ports, cells) = system.serial_tls.zipWithIndex.map({ case (s, id) =>
val sys = system.asInstanceOf[BaseSubsystem]
val port = IO(chiselTypeOf(s.getWrappedValue))
port <> s.getWrappedValue
(SerialTLPort(() => port, sys.p(SerialTLKey)(id), system.serdessers(id), id), Nil)
}).unzip
(ports.toSeq, cells.flatten.toSeq)
}
})
class WithAXI4MemPunchthrough extends OverrideLazyIOBinder({
(system: CanHaveMasterAXI4MemPort) => {
implicit val p: Parameters = GetSystemParameters(system)
val clockSinkNode = p(ExtMem).map(_ => ClockSinkNode(Seq(ClockSinkParameters())))
clockSinkNode.map(_ := system.asInstanceOf[HasTileLinkLocations].locateTLBusWrapper(MBUS).fixedClockNode)
def clockBundle = clockSinkNode.get.in.head._1
InModuleBody {
val ports: Seq[AXI4MemPort] = system.mem_axi4.zipWithIndex.map({ case (m, i) =>
val port = IO(new ClockedIO(DataMirror.internal.chiselTypeClone[AXI4Bundle](m))).suggestName(s"axi4_mem_${i}")
port.bits <> m
port.clock := clockBundle.clock
AXI4MemPort(() => port, p(ExtMem).get, system.memAXI4Node.edges.in(i), p(MemoryBusKey).dtsFrequency.get.toInt)
}).toSeq
(ports, Nil)
}
}
})
class WithAXI4MMIOPunchthrough extends OverrideLazyIOBinder({
(system: CanHaveMasterAXI4MMIOPort) => {
implicit val p: Parameters = GetSystemParameters(system)
val clockSinkNode = p(ExtBus).map(_ => ClockSinkNode(Seq(ClockSinkParameters())))
clockSinkNode.map(_ := system.asInstanceOf[HasTileLinkLocations].locateTLBusWrapper(SBUS).fixedClockNode)
def clockBundle = clockSinkNode.get.in.head._1
InModuleBody {
val ports: Seq[AXI4MMIOPort] = system.mmio_axi4.zipWithIndex.map({ case (m, i) =>
val port = IO(new ClockedIO(DataMirror.internal.chiselTypeClone[AXI4Bundle](m))).suggestName(s"axi4_mmio_${i}")
port.bits <> m
port.clock := clockBundle.clock
AXI4MMIOPort(() => port, p(ExtBus).get, system.mmioAXI4Node.edges.in(i))
}).toSeq
(ports, Nil)
}
}
})
class WithL2FBusAXI4Punchthrough extends OverrideLazyIOBinder({
(system: CanHaveSlaveAXI4Port) => {
implicit val p: Parameters = GetSystemParameters(system)
val clockSinkNode = p(ExtIn).map(_ => ClockSinkNode(Seq(ClockSinkParameters())))
val fbus = system.asInstanceOf[HasTileLinkLocations].locateTLBusWrapper(FBUS)
clockSinkNode.map(_ := fbus.fixedClockNode)
def clockBundle = clockSinkNode.get.in.head._1
InModuleBody {
val ports: Seq[AXI4InPort] = system.l2_frontend_bus_axi4.zipWithIndex.map({ case (m, i) =>
val port = IO(new ClockedIO(Flipped(DataMirror.internal.chiselTypeClone[AXI4Bundle](m)))).suggestName(s"axi4_fbus_${i}")
m <> port.bits
port.clock := clockBundle.clock
AXI4InPort(() => port, p(ExtIn).get)
}).toSeq
(ports, Nil)
}
}
})
class WithBlockDeviceIOPunchthrough extends OverrideIOBinder({
(system: CanHavePeripheryBlockDevice) => {
val ports: Seq[BlockDevicePort] = system.bdev.map({ bdev =>
val p = GetSystemParameters(system)
val bdParams = p(BlockDeviceKey).get
val port = IO(new ClockedIO(new BlockDeviceIO(bdParams))).suggestName("blockdev")
port <> bdev
BlockDevicePort(() => port, bdParams)
}).toSeq
(ports, Nil)
}
})
class WithNICIOPunchthrough extends OverrideIOBinder({
(system: CanHavePeripheryIceNIC) => {
val ports: Seq[NICPort] = system.icenicOpt.map({ n =>
val p = GetSystemParameters(system)
val port = IO(new ClockedIO(new NICIOvonly)).suggestName("nic")
port <> n
NICPort(() => port, p(NICKey).get)
}).toSeq
(ports, Nil)
}
})
class WithTraceGenSuccessPunchthrough extends OverrideIOBinder({
(system: TraceGenSystemModuleImp) => {
val success: Bool = IO(Output(Bool())).suggestName("success")
success := system.success
(Seq(SuccessPort(() => success)), Nil)
}
})
class WithTraceIOPunchthrough extends OverrideLazyIOBinder({
(system: CanHaveTraceIO) => InModuleBody {
val ports: Option[TracePort] = system.traceIO.map { t =>
val trace = IO(DataMirror.internal.chiselTypeClone[TraceOutputTop](t)).suggestName("trace")
trace <> t
val p = GetSystemParameters(system)
val chipyardSystem = system.asInstanceOf[ChipyardSystem]
val tiles = chipyardSystem.totalTiles.values
val viewpointBus = system.asInstanceOf[HasConfigurableTLNetworkTopology].viewpointBus
val mems = viewpointBus.unifyManagers.filter { m =>
val regionTypes = Seq(RegionType.CACHED, RegionType.TRACKED, RegionType.UNCACHED, RegionType.IDEMPOTENT)
val ignoreAddresses = Seq(
0x10000 // bootrom is handled specially
)
regionTypes.contains(m.regionType) && !ignoreAddresses.contains(m.address.map(_.base).min)
}.map { m =>
val base = m.address.map(_.base).min
val size = m.address.map(_.max).max - base + 1
(base, size)
}
val useSimDTM = p(ExportDebug).protocols.contains(DMI) // assume that exposing clockeddmi means we will connect SimDTM
val cfg = SpikeCosimConfig(
isa = tiles.headOption.map(_.isaDTS).getOrElse(""),
priv = tiles.headOption.map(t => if (t.usingUser) "MSU" else if (t.usingSupervisor) "MS" else "M").getOrElse(""),
maxpglevels = tiles.headOption.map(_.tileParams.core.pgLevels).getOrElse(0),
pmpregions = tiles.headOption.map(_.tileParams.core.nPMPs).getOrElse(0),
nharts = tiles.size,
bootrom = chipyardSystem.bootROM.map(_.module.contents.toArray.mkString(" ")).getOrElse(""),
has_dtm = useSimDTM,
mems = mems,
// Connect using the legacy API for firesim only
mem0_base = p(ExtMem).map(_.master.base).getOrElse(BigInt(0)),
mem0_size = p(ExtMem).map(_.master.size).getOrElse(BigInt(0)),
)
TracePort(() => trace, cfg)
}
(ports.toSeq, Nil)
}
})
class WithCustomBootPin extends OverrideIOBinder({
(system: CanHavePeripheryCustomBootPin) => system.custom_boot_pin.map({ p =>
val sys = system.asInstanceOf[BaseSubsystem]
val (port, cells) = IOCell.generateIOFromSignal(p.getWrappedValue, "custom_boot", sys.p(IOCellKey), abstractResetAsAsync = true)
(Seq(CustomBootPort(() => port)), cells)
}).getOrElse((Nil, Nil))
})
class WithUARTTSIPunchthrough extends OverrideIOBinder({
(system: CanHavePeripheryUARTTSI) => system.uart_tsi.map({ p =>
val sys = system.asInstanceOf[BaseSubsystem]
val uart_tsi = IO(new UARTTSIIO(p.uartParams))
uart_tsi <> p
(Seq(UARTTSIPort(() => uart_tsi)), Nil)
}).getOrElse((Nil, Nil))
})
class WithTLMemPunchthrough extends OverrideIOBinder({
(system: CanHaveMasterTLMemPort) => {
val io_tl_mem_pins_temp = IO(DataMirror.internal.chiselTypeClone[HeterogeneousBag[TLBundle]](system.mem_tl)).suggestName("tl_slave")
io_tl_mem_pins_temp <> system.mem_tl
(Seq(TLMemPort(() => io_tl_mem_pins_temp)), Nil)
}
})
class WithDontTouchPorts extends OverrideIOBinder({
(system: DontTouch) => system.dontTouchPorts(); (Nil, Nil)
})
class WithNMITiedOff extends ComposeIOBinder({
(system: HasHierarchicalElementsRootContextModuleImp) => {
system.nmi.foreach { nmi =>
nmi.rnmi := false.B
nmi.rnmi_interrupt_vector := 0.U
nmi.rnmi_exception_vector := 0.U
}
(Nil, Nil)
}
})
class WithGCDBusyPunchthrough extends OverrideIOBinder({
(system: CanHavePeripheryGCD) => system.gcd_busy.map { busy =>
val io_gcd_busy = IO(Output(Bool()))
io_gcd_busy := busy
(Seq(GCDBusyPort(() => io_gcd_busy)), Nil)
}.getOrElse((Nil, Nil))
})
File ClockBinders.scala:
package chipyard.clocking
import chisel3._
import chisel3.util._
import chipyard.iobinders._
import freechips.rocketchip.prci._
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.subsystem._
import freechips.rocketchip.tilelink._
import chipyard.iocell._
// This uses the FakePLL, which uses a ClockAtFreq Verilog blackbox to generate
// the requested clocks. This also adds TileLink ClockDivider and ClockSelector
// blocks, which allow memory-mapped control of clock division, and clock muxing
// between the FakePLL and the slow off-chip clock
// Note: This will not simulate properly with firesim
// Unsetting enable will prevent the divider/selector from actually modifying the clock,
// while preserving the address map. Unsetting enable should only be done for RTL
// simulators (Verilator) which do not model reset properly
class WithPLLSelectorDividerClockGenerator(enable: Boolean = true) extends OverrideLazyIOBinder({
(system: HasChipyardPRCI) => {
// Connect the implicit clock
implicit val p = GetSystemParameters(system)
val tlbus = system.asInstanceOf[BaseSubsystem].locateTLBusWrapper(system.prciParams.slaveWhere)
val baseAddress = system.prciParams.baseAddress
val clockDivider = system.prci_ctrl_domain { LazyModule(new TLClockDivider (baseAddress + 0x20000, tlbus.beatBytes, enable=enable)) }
val clockSelector = system.prci_ctrl_domain { LazyModule(new TLClockSelector(baseAddress + 0x30000, tlbus.beatBytes, enable=enable)) }
val pllCtrl = system.prci_ctrl_domain { LazyModule(new FakePLLCtrl (baseAddress + 0x40000, tlbus.beatBytes)) }
clockDivider.tlNode := system.prci_ctrl_domain { TLFragmenter(tlbus, Some("ClockDivider")) := system.prci_ctrl_bus.get }
clockSelector.tlNode := system.prci_ctrl_domain { TLFragmenter(tlbus, Some("ClockSelector")) := system.prci_ctrl_bus.get }
pllCtrl.tlNode := system.prci_ctrl_domain { TLFragmenter(tlbus, Some("PLLCtrl")) := system.prci_ctrl_bus.get }
system.chiptopClockGroupsNode := clockDivider.clockNode := clockSelector.clockNode
// Connect all other requested clocks
val slowClockSource = ClockSourceNode(Seq(ClockSourceParameters()))
val pllClockSource = ClockSourceNode(Seq(ClockSourceParameters()))
// The order of the connections to clockSelector.clockNode configures the inputs
// of the clockSelector's clockMux. Default to using the slowClockSource,
// software should enable the PLL, then switch to the pllClockSource
clockSelector.clockNode := slowClockSource
clockSelector.clockNode := pllClockSource
val pllCtrlSink = BundleBridgeSink[FakePLLCtrlBundle]()
pllCtrlSink := pllCtrl.ctrlNode
InModuleBody {
val clock_wire = Wire(Input(Clock()))
val reset_wire = Wire(Input(AsyncReset()))
val (clock_io, clockIOCell) = IOCell.generateIOFromSignal(clock_wire, "clock", p(IOCellKey))
val (reset_io, resetIOCell) = IOCell.generateIOFromSignal(reset_wire, "reset", p(IOCellKey))
slowClockSource.out.unzip._1.map { o =>
o.clock := clock_wire
o.reset := reset_wire
}
// For a real chip you should replace this ClockSourceAtFreqFromPlusArg
// with a blackbox of whatever PLL is being integrated
val fake_pll = Module(new ClockSourceAtFreqFromPlusArg("pll_freq_mhz"))
fake_pll.io.power := pllCtrlSink.in(0)._1.power
fake_pll.io.gate := pllCtrlSink.in(0)._1.gate
pllClockSource.out.unzip._1.map { o =>
o.clock := fake_pll.io.clk
o.reset := reset_wire
}
(Seq(ClockPort(() => clock_io, 100), ResetPort(() => reset_io)), clockIOCell ++ resetIOCell)
}
}
})
// This passes all clocks through to the TestHarness
class WithPassthroughClockGenerator extends OverrideLazyIOBinder({
(system: HasChipyardPRCI) => {
implicit val p = GetSystemParameters(system)
// This aggregate node should do nothing
val clockGroupAggNode = ClockGroupAggregateNode("fake")
val clockGroupsSourceNode = ClockGroupSourceNode(Seq(ClockGroupSourceParameters()))
system.chiptopClockGroupsNode := clockGroupAggNode := clockGroupsSourceNode
InModuleBody {
val reset_io = IO(Input(AsyncReset()))
require(clockGroupAggNode.out.size == 1)
val (bundle, edge) = clockGroupAggNode.out(0)
val clock_ios = (bundle.member.data zip edge.sink.members).map { case (b, m) =>
require(m.take.isDefined, s"""Clock ${m.name.get} has no requested frequency
|Clocks: ${edge.sink.members.map(_.name.get)}""".stripMargin)
val freq = m.take.get.freqMHz
val clock_io = IO(Input(Clock())).suggestName(s"clock_${m.name.get}")
b.clock := clock_io
b.reset := reset_io
ClockPort(() => clock_io, freq)
}.toSeq
((clock_ios :+ ResetPort(() => reset_io)), Nil)
}
}
})
// Broadcasts a single clock IO to all clock domains. Ignores all requested frequencies
class WithSingleClockBroadcastClockGenerator(freqMHz: Int = 100) extends OverrideLazyIOBinder({
(system: HasChipyardPRCI) => {
implicit val p = GetSystemParameters(system)
val clockGroupsAggregator = LazyModule(new ClockGroupAggregator("single_clock"))
val clockGroupsSourceNode = ClockGroupSourceNode(Seq(ClockGroupSourceParameters()))
system.chiptopClockGroupsNode :*= clockGroupsAggregator.node := clockGroupsSourceNode
InModuleBody {
val clock_wire = Wire(Input(Clock()))
val reset_wire = Wire(Input(AsyncReset()))
val (clock_io, clockIOCell) = IOCell.generateIOFromSignal(clock_wire, "clock", p(IOCellKey))
val (reset_io, resetIOCell) = IOCell.generateIOFromSignal(reset_wire, "reset", p(IOCellKey))
clockGroupsSourceNode.out.foreach { case (bundle, edge) =>
bundle.member.data.foreach { b =>
b.clock := clock_io
b.reset := reset_io
}
}
(Seq(ClockPort(() => clock_io, freqMHz), ResetPort(() => reset_io)), clockIOCell ++ resetIOCell)
}
}
})
class WithClockTapIOCells extends OverrideIOBinder({
(system: CanHaveClockTap) => {
system.clockTapIO.map { tap =>
val (clock_tap_io, clock_tap_cell) = IOCell.generateIOFromSignal(tap.getWrappedValue, "clock_tap")
(Seq(ClockTapPort(() => clock_tap_io)), clock_tap_cell)
}.getOrElse((Nil, Nil))
}
})
| module ChipTop( // @[ChipTop.scala:33:44]
output uart_0_txd, // @[IOCell.scala:196:23]
input uart_0_rxd, // @[IOCell.scala:196:23]
output axi4_mem_0_clock, // @[IOBinders.scala:397:22]
input axi4_mem_0_bits_aw_ready, // @[IOBinders.scala:397:22]
output axi4_mem_0_bits_aw_valid, // @[IOBinders.scala:397:22]
output [3:0] axi4_mem_0_bits_aw_bits_id, // @[IOBinders.scala:397:22]
output [31:0] axi4_mem_0_bits_aw_bits_addr, // @[IOBinders.scala:397:22]
output [7:0] axi4_mem_0_bits_aw_bits_len, // @[IOBinders.scala:397:22]
output [2:0] axi4_mem_0_bits_aw_bits_size, // @[IOBinders.scala:397:22]
output [1:0] axi4_mem_0_bits_aw_bits_burst, // @[IOBinders.scala:397:22]
output axi4_mem_0_bits_aw_bits_lock, // @[IOBinders.scala:397:22]
output [3:0] axi4_mem_0_bits_aw_bits_cache, // @[IOBinders.scala:397:22]
output [2:0] axi4_mem_0_bits_aw_bits_prot, // @[IOBinders.scala:397:22]
output [3:0] axi4_mem_0_bits_aw_bits_qos, // @[IOBinders.scala:397:22]
input axi4_mem_0_bits_w_ready, // @[IOBinders.scala:397:22]
output axi4_mem_0_bits_w_valid, // @[IOBinders.scala:397:22]
output [63:0] axi4_mem_0_bits_w_bits_data, // @[IOBinders.scala:397:22]
output [7:0] axi4_mem_0_bits_w_bits_strb, // @[IOBinders.scala:397:22]
output axi4_mem_0_bits_w_bits_last, // @[IOBinders.scala:397:22]
output axi4_mem_0_bits_b_ready, // @[IOBinders.scala:397:22]
input axi4_mem_0_bits_b_valid, // @[IOBinders.scala:397:22]
input [3:0] axi4_mem_0_bits_b_bits_id, // @[IOBinders.scala:397:22]
input [1:0] axi4_mem_0_bits_b_bits_resp, // @[IOBinders.scala:397:22]
input axi4_mem_0_bits_ar_ready, // @[IOBinders.scala:397:22]
output axi4_mem_0_bits_ar_valid, // @[IOBinders.scala:397:22]
output [3:0] axi4_mem_0_bits_ar_bits_id, // @[IOBinders.scala:397:22]
output [31:0] axi4_mem_0_bits_ar_bits_addr, // @[IOBinders.scala:397:22]
output [7:0] axi4_mem_0_bits_ar_bits_len, // @[IOBinders.scala:397:22]
output [2:0] axi4_mem_0_bits_ar_bits_size, // @[IOBinders.scala:397:22]
output [1:0] axi4_mem_0_bits_ar_bits_burst, // @[IOBinders.scala:397:22]
output axi4_mem_0_bits_ar_bits_lock, // @[IOBinders.scala:397:22]
output [3:0] axi4_mem_0_bits_ar_bits_cache, // @[IOBinders.scala:397:22]
output [2:0] axi4_mem_0_bits_ar_bits_prot, // @[IOBinders.scala:397:22]
output [3:0] axi4_mem_0_bits_ar_bits_qos, // @[IOBinders.scala:397:22]
output axi4_mem_0_bits_r_ready, // @[IOBinders.scala:397:22]
input axi4_mem_0_bits_r_valid, // @[IOBinders.scala:397:22]
input [3:0] axi4_mem_0_bits_r_bits_id, // @[IOBinders.scala:397:22]
input [63:0] axi4_mem_0_bits_r_bits_data, // @[IOBinders.scala:397:22]
input [1:0] axi4_mem_0_bits_r_bits_resp, // @[IOBinders.scala:397:22]
input axi4_mem_0_bits_r_bits_last, // @[IOBinders.scala:397:22]
input custom_boot, // @[IOCell.scala:196:23]
input jtag_TCK, // @[IOCell.scala:196:23]
input jtag_TMS, // @[IOCell.scala:196:23]
input jtag_TDI, // @[IOCell.scala:196:23]
output jtag_TDO, // @[IOCell.scala:196:23]
input reset_io, // @[ClockBinders.scala:87:24]
input clock_uncore, // @[ClockBinders.scala:95:26]
output clock_tap, // @[IOCell.scala:196:23]
output serial_tl_0_in_ready, // @[IOCell.scala:196:23]
input serial_tl_0_in_valid, // @[IOCell.scala:196:23]
input [31:0] serial_tl_0_in_bits_phit, // @[IOCell.scala:196:23]
input serial_tl_0_out_ready, // @[IOCell.scala:196:23]
output serial_tl_0_out_valid, // @[IOCell.scala:196:23]
output [31:0] serial_tl_0_out_bits_phit, // @[IOCell.scala:196:23]
input serial_tl_0_clock_in // @[IOCell.scala:196:23]
);
wire _iocell_serial_tl_0_in_valid_i; // @[IOCell.scala:176:23]
wire _iocell_serial_tl_0_in_bits_phit_31_i; // @[IOCell.scala:176:23]
wire _iocell_serial_tl_0_in_bits_phit_30_i; // @[IOCell.scala:176:23]
wire _iocell_serial_tl_0_in_bits_phit_29_i; // @[IOCell.scala:176:23]
wire _iocell_serial_tl_0_in_bits_phit_28_i; // @[IOCell.scala:176:23]
wire _iocell_serial_tl_0_in_bits_phit_27_i; // @[IOCell.scala:176:23]
wire _iocell_serial_tl_0_in_bits_phit_26_i; // @[IOCell.scala:176:23]
wire _iocell_serial_tl_0_in_bits_phit_25_i; // @[IOCell.scala:176:23]
wire _iocell_serial_tl_0_in_bits_phit_24_i; // @[IOCell.scala:176:23]
wire _iocell_serial_tl_0_in_bits_phit_23_i; // @[IOCell.scala:176:23]
wire _iocell_serial_tl_0_in_bits_phit_22_i; // @[IOCell.scala:176:23]
wire _iocell_serial_tl_0_in_bits_phit_21_i; // @[IOCell.scala:176:23]
wire _iocell_serial_tl_0_in_bits_phit_20_i; // @[IOCell.scala:176:23]
wire _iocell_serial_tl_0_in_bits_phit_19_i; // @[IOCell.scala:176:23]
wire _iocell_serial_tl_0_in_bits_phit_18_i; // @[IOCell.scala:176:23]
wire _iocell_serial_tl_0_in_bits_phit_17_i; // @[IOCell.scala:176:23]
wire _iocell_serial_tl_0_in_bits_phit_16_i; // @[IOCell.scala:176:23]
wire _iocell_serial_tl_0_in_bits_phit_15_i; // @[IOCell.scala:176:23]
wire _iocell_serial_tl_0_in_bits_phit_14_i; // @[IOCell.scala:176:23]
wire _iocell_serial_tl_0_in_bits_phit_13_i; // @[IOCell.scala:176:23]
wire _iocell_serial_tl_0_in_bits_phit_12_i; // @[IOCell.scala:176:23]
wire _iocell_serial_tl_0_in_bits_phit_11_i; // @[IOCell.scala:176:23]
wire _iocell_serial_tl_0_in_bits_phit_10_i; // @[IOCell.scala:176:23]
wire _iocell_serial_tl_0_in_bits_phit_9_i; // @[IOCell.scala:176:23]
wire _iocell_serial_tl_0_in_bits_phit_8_i; // @[IOCell.scala:176:23]
wire _iocell_serial_tl_0_in_bits_phit_7_i; // @[IOCell.scala:176:23]
wire _iocell_serial_tl_0_in_bits_phit_6_i; // @[IOCell.scala:176:23]
wire _iocell_serial_tl_0_in_bits_phit_5_i; // @[IOCell.scala:176:23]
wire _iocell_serial_tl_0_in_bits_phit_4_i; // @[IOCell.scala:176:23]
wire _iocell_serial_tl_0_in_bits_phit_3_i; // @[IOCell.scala:176:23]
wire _iocell_serial_tl_0_in_bits_phit_2_i; // @[IOCell.scala:176:23]
wire _iocell_serial_tl_0_in_bits_phit_1_i; // @[IOCell.scala:176:23]
wire _iocell_serial_tl_0_in_bits_phit_i; // @[IOCell.scala:176:23]
wire _iocell_serial_tl_0_out_ready_i; // @[IOCell.scala:176:23]
wire _iocell_serial_tl_0_out_bits_phit_31_pad; // @[IOCell.scala:177:24]
wire _iocell_serial_tl_0_out_bits_phit_30_pad; // @[IOCell.scala:177:24]
wire _iocell_serial_tl_0_out_bits_phit_29_pad; // @[IOCell.scala:177:24]
wire _iocell_serial_tl_0_out_bits_phit_28_pad; // @[IOCell.scala:177:24]
wire _iocell_serial_tl_0_out_bits_phit_27_pad; // @[IOCell.scala:177:24]
wire _iocell_serial_tl_0_out_bits_phit_26_pad; // @[IOCell.scala:177:24]
wire _iocell_serial_tl_0_out_bits_phit_25_pad; // @[IOCell.scala:177:24]
wire _iocell_serial_tl_0_out_bits_phit_24_pad; // @[IOCell.scala:177:24]
wire _iocell_serial_tl_0_out_bits_phit_23_pad; // @[IOCell.scala:177:24]
wire _iocell_serial_tl_0_out_bits_phit_22_pad; // @[IOCell.scala:177:24]
wire _iocell_serial_tl_0_out_bits_phit_21_pad; // @[IOCell.scala:177:24]
wire _iocell_serial_tl_0_out_bits_phit_20_pad; // @[IOCell.scala:177:24]
wire _iocell_serial_tl_0_out_bits_phit_19_pad; // @[IOCell.scala:177:24]
wire _iocell_serial_tl_0_out_bits_phit_18_pad; // @[IOCell.scala:177:24]
wire _iocell_serial_tl_0_out_bits_phit_17_pad; // @[IOCell.scala:177:24]
wire _iocell_serial_tl_0_out_bits_phit_16_pad; // @[IOCell.scala:177:24]
wire _iocell_serial_tl_0_out_bits_phit_15_pad; // @[IOCell.scala:177:24]
wire _iocell_serial_tl_0_out_bits_phit_14_pad; // @[IOCell.scala:177:24]
wire _iocell_serial_tl_0_out_bits_phit_13_pad; // @[IOCell.scala:177:24]
wire _iocell_serial_tl_0_out_bits_phit_12_pad; // @[IOCell.scala:177:24]
wire _iocell_serial_tl_0_out_bits_phit_11_pad; // @[IOCell.scala:177:24]
wire _iocell_serial_tl_0_out_bits_phit_10_pad; // @[IOCell.scala:177:24]
wire _iocell_serial_tl_0_out_bits_phit_9_pad; // @[IOCell.scala:177:24]
wire _iocell_serial_tl_0_out_bits_phit_8_pad; // @[IOCell.scala:177:24]
wire _iocell_serial_tl_0_out_bits_phit_7_pad; // @[IOCell.scala:177:24]
wire _iocell_serial_tl_0_out_bits_phit_6_pad; // @[IOCell.scala:177:24]
wire _iocell_serial_tl_0_out_bits_phit_5_pad; // @[IOCell.scala:177:24]
wire _iocell_serial_tl_0_out_bits_phit_4_pad; // @[IOCell.scala:177:24]
wire _iocell_serial_tl_0_out_bits_phit_3_pad; // @[IOCell.scala:177:24]
wire _iocell_serial_tl_0_out_bits_phit_2_pad; // @[IOCell.scala:177:24]
wire _iocell_serial_tl_0_out_bits_phit_1_pad; // @[IOCell.scala:177:24]
wire _iocell_serial_tl_0_out_bits_phit_pad; // @[IOCell.scala:177:24]
wire _iocell_serial_tl_0_clock_in_i; // @[IOCell.scala:176:23]
wire _iocell_jtag_TCK_i; // @[IOCell.scala:176:23]
wire _iocell_jtag_TMS_i; // @[IOCell.scala:176:23]
wire _iocell_jtag_TDI_i; // @[IOCell.scala:176:23]
wire _gated_clock_debug_clock_gate_out; // @[ClockGate.scala:36:20]
wire _dmactiveAck_dmactiveAck_io_q; // @[ShiftReg.scala:45:23]
wire _debug_reset_syncd_debug_reset_sync_io_q; // @[ShiftReg.scala:45:23]
wire _system_debug_systemjtag_reset_catcher_io_sync_reset; // @[ResetCatchAndSync.scala:39:28]
wire _iocell_custom_boot_i; // @[IOCell.scala:176:23]
wire _iocell_uart_0_rxd_i; // @[IOCell.scala:176:23]
wire _system_auto_cbus_fixedClockNode_anon_out_clock; // @[ChipTop.scala:27:35]
wire _system_auto_cbus_fixedClockNode_anon_out_reset; // @[ChipTop.scala:27:35]
wire _system_debug_systemjtag_jtag_TDO_data; // @[ChipTop.scala:27:35]
wire _system_debug_dmactive; // @[ChipTop.scala:27:35]
wire _system_serial_tl_0_in_ready; // @[ChipTop.scala:27:35]
wire _system_serial_tl_0_out_valid; // @[ChipTop.scala:27:35]
wire [31:0] _system_serial_tl_0_out_bits_phit; // @[ChipTop.scala:27:35]
wire _system_uart_0_txd; // @[ChipTop.scala:27:35]
wire _system_clock_tap; // @[ChipTop.scala:27:35]
wire debug_reset = ~_debug_reset_syncd_debug_reset_sync_io_q; // @[ShiftReg.scala:45:23]
reg clock_en; // @[Periphery.scala:298:29]
always @(posedge _system_auto_cbus_fixedClockNode_anon_out_clock or posedge debug_reset) begin // @[Periphery.scala:290:40]
if (debug_reset) // @[Periphery.scala:290:40]
clock_en <= 1'h1; // @[Periphery.scala:298:29]
else // @[ChipTop.scala:27:35]
clock_en <= _dmactiveAck_dmactiveAck_io_q; // @[ShiftReg.scala:45:23]
always @(posedge, posedge) |
Generate the Verilog code corresponding to the following Chisel files.
File ShiftReg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
// Similar to the Chisel ShiftRegister but allows the user to suggest a
// name to the registers that get instantiated, and
// to provide a reset value.
object ShiftRegInit {
def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T =
(0 until n).foldRight(in) {
case (i, next) => {
val r = RegNext(next, init)
name.foreach { na => r.suggestName(s"${na}_${i}") }
r
}
}
}
/** These wrap behavioral
* shift registers into specific modules to allow for
* backend flows to replace or constrain
* them properly when used for CDC synchronization,
* rather than buffering.
*
* The different types vary in their reset behavior:
* AsyncResetShiftReg -- Asynchronously reset register array
* A W(width) x D(depth) sized array is constructed from D instantiations of a
* W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg,
* but only used for timing applications
*/
abstract class AbstractPipelineReg(w: Int = 1) extends Module {
val io = IO(new Bundle {
val d = Input(UInt(w.W))
val q = Output(UInt(w.W))
}
)
}
object AbstractPipelineReg {
def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = {
val chain = Module(gen)
name.foreach{ chain.suggestName(_) }
chain.io.d := in.asUInt
chain.io.q.asTypeOf(in)
}
}
class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) {
require(depth > 0, "Depth must be greater than 0.")
override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}"
val chain = List.tabulate(depth) { i =>
Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}")
}
chain.last.io.d := io.d
chain.last.io.en := true.B
(chain.init zip chain.tail).foreach { case (sink, source) =>
sink.io.d := source.io.q
sink.io.en := true.B
}
io.q := chain.head.io.q
}
object AsyncResetShiftReg {
def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T =
AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name)
def apply [T <: Data](in: T, depth: Int, name: Option[String]): T =
apply(in, depth, 0, name)
def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T =
apply(in, depth, init.litValue.toInt, name)
def apply [T <: Data](in: T, depth: Int, init: T): T =
apply (in, depth, init.litValue.toInt, None)
}
File SynchronizerReg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util.{RegEnable, Cat}
/** These wrap behavioral
* shift and next registers into specific modules to allow for
* backend flows to replace or constrain
* them properly when used for CDC synchronization,
* rather than buffering.
*
*
* These are built up of *ResetSynchronizerPrimitiveShiftReg,
* intended to be replaced by the integrator's metastable flops chains or replaced
* at this level if they have a multi-bit wide synchronizer primitive.
* The different types vary in their reset behavior:
* NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin
* AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep
* 1-bit-wide shift registers.
* SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg
*
* [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference.
*
* ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross
* Clock Domains.
*/
object SynchronizerResetType extends Enumeration {
val NonSync, Inferred, Sync, Async = Value
}
// Note: this should not be used directly.
// Use the companion object to generate this with the correct reset type mixin.
private class SynchronizerPrimitiveShiftReg(
sync: Int,
init: Boolean,
resetType: SynchronizerResetType.Value)
extends AbstractPipelineReg(1) {
val initInt = if (init) 1 else 0
val initPostfix = resetType match {
case SynchronizerResetType.NonSync => ""
case _ => s"_i${initInt}"
}
override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}"
val chain = List.tabulate(sync) { i =>
val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B)
reg.suggestName(s"sync_$i")
}
chain.last := io.d.asBool
(chain.init zip chain.tail).foreach { case (sink, source) =>
sink := source
}
io.q := chain.head.asUInt
}
private object SynchronizerPrimitiveShiftReg {
def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = {
val gen: () => SynchronizerPrimitiveShiftReg = resetType match {
case SynchronizerResetType.NonSync =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType)
case SynchronizerResetType.Async =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset
case SynchronizerResetType.Sync =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset
case SynchronizerResetType.Inferred =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType)
}
AbstractPipelineReg(gen(), in)
}
}
// Note: This module may end up with a non-AsyncReset type reset.
// But the Primitives within will always have AsyncReset type.
class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int)
extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
withReset(reset.asAsyncReset){
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async)
}
}
io.q := Cat(output.reverse)
}
object AsyncResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
// Note: This module may end up with a non-Bool type reset.
// But the Primitives within will always have Bool reset type.
@deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2")
class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
withReset(reset.asBool){
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync)
}
}
io.q := Cat(output.reverse)
}
object SyncResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred)
}
io.q := Cat(output.reverse)
}
object ResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}"
val output = Seq.tabulate(w) { i =>
SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync)
}
io.q := Cat(output.reverse)
}
object SynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T =
if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, None)
def apply [T <: Data](in: T): T =
apply (in, 3, None)
}
class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module {
override def desiredName = s"ClockCrossingReg_w${w}"
val io = IO(new Bundle{
val d = Input(UInt(w.W))
val q = Output(UInt(w.W))
val en = Input(Bool())
})
val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en)
io.q := cdc_reg
}
object ClockCrossingReg {
def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = {
val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit))
name.foreach{ cdc_reg.suggestName(_) }
cdc_reg.io.d := in.asUInt
cdc_reg.io.en := en
cdc_reg.io.q.asTypeOf(in)
}
}
| module AsyncResetSynchronizerShiftReg_w1_d3_i0_45( // @[SynchronizerReg.scala:80:7]
input clock, // @[SynchronizerReg.scala:80:7]
input reset, // @[SynchronizerReg.scala:80:7]
output io_q // @[ShiftReg.scala:36:14]
);
wire _output_T = reset; // @[SynchronizerReg.scala:86:21]
wire io_d = 1'h1; // @[SynchronizerReg.scala:80:7, :87:41]
wire _output_T_1 = 1'h1; // @[SynchronizerReg.scala:80:7, :87:41]
wire output_0; // @[ShiftReg.scala:48:24]
wire io_q_0; // @[SynchronizerReg.scala:80:7]
assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7]
AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_53 output_chain ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (_output_T), // @[SynchronizerReg.scala:86:21]
.io_q (output_0)
); // @[ShiftReg.scala:45:23]
assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File LazyModuleImp.scala:
package org.chipsalliance.diplomacy.lazymodule
import chisel3.{withClockAndReset, Module, RawModule, Reset, _}
import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo}
import firrtl.passes.InlineAnnotation
import org.chipsalliance.cde.config.Parameters
import org.chipsalliance.diplomacy.nodes.Dangle
import scala.collection.immutable.SortedMap
/** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]].
*
* This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy.
*/
sealed trait LazyModuleImpLike extends RawModule {
/** [[LazyModule]] that contains this instance. */
val wrapper: LazyModule
/** IOs that will be automatically "punched" for this instance. */
val auto: AutoBundle
/** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */
protected[diplomacy] val dangles: Seq[Dangle]
// [[wrapper.module]] had better not be accessed while LazyModules are still being built!
require(
LazyModule.scope.isEmpty,
s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}"
)
/** Set module name. Defaults to the containing LazyModule's desiredName. */
override def desiredName: String = wrapper.desiredName
suggestName(wrapper.suggestedName)
/** [[Parameters]] for chisel [[Module]]s. */
implicit val p: Parameters = wrapper.p
/** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and
* submodules.
*/
protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = {
// 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]],
// 2. return [[Dangle]]s from each module.
val childDangles = wrapper.children.reverse.flatMap { c =>
implicit val sourceInfo: SourceInfo = c.info
c.cloneProto.map { cp =>
// If the child is a clone, then recursively set cloneProto of its children as well
def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = {
require(bases.size == clones.size)
(bases.zip(clones)).map { case (l, r) =>
require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}")
l.cloneProto = Some(r)
assignCloneProtos(l.children, r.children)
}
}
assignCloneProtos(c.children, cp.children)
// Clone the child module as a record, and get its [[AutoBundle]]
val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName)
val clonedAuto = clone("auto").asInstanceOf[AutoBundle]
// Get the empty [[Dangle]]'s of the cloned child
val rawDangles = c.cloneDangles()
require(rawDangles.size == clonedAuto.elements.size)
// Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s
val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) }
dangles
}.getOrElse {
// For non-clones, instantiate the child module
val mod = try {
Module(c.module)
} catch {
case e: ChiselException => {
println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}")
throw e
}
}
mod.dangles
}
}
// Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]].
// This will result in a sequence of [[Dangle]] from these [[BaseNode]]s.
val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate())
// Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]]
val allDangles = nodeDangles ++ childDangles
// Group [[allDangles]] by their [[source]].
val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*)
// For each [[source]] set of [[Dangle]]s of size 2, ensure that these
// can be connected as a source-sink pair (have opposite flipped value).
// Make the connection and mark them as [[done]].
val done = Set() ++ pairing.values.filter(_.size == 2).map {
case Seq(a, b) =>
require(a.flipped != b.flipped)
// @todo <> in chisel3 makes directionless connection.
if (a.flipped) {
a.data <> b.data
} else {
b.data <> a.data
}
a.source
case _ => None
}
// Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module.
val forward = allDangles.filter(d => !done(d.source))
// Generate [[AutoBundle]] IO from [[forward]].
val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*))
// Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]]
val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) =>
if (d.flipped) {
d.data <> io
} else {
io <> d.data
}
d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name)
}
// Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]].
wrapper.inModuleBody.reverse.foreach {
_()
}
if (wrapper.shouldBeInlined) {
chisel3.experimental.annotate(new ChiselAnnotation {
def toFirrtl = InlineAnnotation(toNamed)
})
}
// Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]].
(auto, dangles)
}
}
/** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike {
/** Instantiate hardware of this `Module`. */
val (auto, dangles) = instantiate()
}
/** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike {
// These wires are the default clock+reset for all LazyModule children.
// It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the
// [[LazyRawModuleImp]] children.
// Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly.
/** drive clock explicitly. */
val childClock: Clock = Wire(Clock())
/** drive reset explicitly. */
val childReset: Reset = Wire(Reset())
// the default is that these are disabled
childClock := false.B.asClock
childReset := chisel3.DontCare
def provideImplicitClockToLazyChildren: Boolean = false
val (auto, dangles) =
if (provideImplicitClockToLazyChildren) {
withClockAndReset(childClock, childReset) { instantiate() }
} else {
instantiate()
}
}
File MixedNode.scala:
package org.chipsalliance.diplomacy.nodes
import chisel3.{Data, DontCare, Wire}
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.{Field, Parameters}
import org.chipsalliance.diplomacy.ValName
import org.chipsalliance.diplomacy.sourceLine
/** One side metadata of a [[Dangle]].
*
* Describes one side of an edge going into or out of a [[BaseNode]].
*
* @param serial
* the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to.
* @param index
* the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to.
*/
case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] {
import scala.math.Ordered.orderingToOrdered
def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that))
}
/** [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]]
* connects.
*
* [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] ,
* [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]].
*
* @param source
* the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within
* that [[BaseNode]].
* @param sink
* sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that
* [[BaseNode]].
* @param flipped
* flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to
* `danglesIn`.
* @param dataOpt
* actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module
*/
case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) {
def data = dataOpt.get
}
/** [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often
* derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually
* implement the protocol.
*/
case class Edges[EI, EO](in: Seq[EI], out: Seq[EO])
/** A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. */
case object MonitorsEnabled extends Field[Boolean](true)
/** When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented.
*
* For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but
* [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink
* nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the
* [[LazyModule]].
*/
case object RenderFlipped extends Field[Boolean](false)
/** The sealed node class in the package, all node are derived from it.
*
* @param inner
* Sink interface implementation.
* @param outer
* Source interface implementation.
* @param valName
* val name of this node.
* @tparam DI
* Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters
* describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected
* [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port
* parameters.
* @tparam UI
* Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing
* the protocol parameters of a sink. For an [[InwardNode]], it is determined itself.
* @tparam EI
* Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers
* specified for a sink according to protocol.
* @tparam BI
* Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface.
* It should extends from [[chisel3.Data]], which represents the real hardware.
* @tparam DO
* Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters
* describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself.
* @tparam UO
* Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing
* the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]].
* Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters.
* @tparam EO
* Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers
* specified for a source according to protocol.
* @tparam BO
* Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source
* interface. It should extends from [[chisel3.Data]], which represents the real hardware.
*
* @note
* Call Graph of [[MixedNode]]
* - line `─`: source is process by a function and generate pass to others
* - Arrow `→`: target of arrow is generated by source
*
* {{{
* (from the other node)
* ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐
* ↓ │
* (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │
* [[InwardNode.accPI]] │ │ │
* │ │ (based on protocol) │
* │ │ [[MixedNode.inner.edgeI]] │
* │ │ ↓ │
* ↓ │ │ │
* (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │
* [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │
* │ │ ↑ │ │ │
* │ │ │ [[OutwardNode.doParams]] │ │
* │ │ │ (from the other node) │ │
* │ │ │ │ │ │
* │ │ │ │ │ │
* │ │ │ └────────┬──────────────┤ │
* │ │ │ │ │ │
* │ │ │ │ (based on protocol) │
* │ │ │ │ [[MixedNode.inner.edgeI]] │
* │ │ │ │ │ │
* │ │ (from the other node) │ ↓ │
* │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │
* │ ↑ ↑ │ │ ↓ │
* │ │ │ │ │ [[MixedNode.in]] │
* │ │ │ │ ↓ ↑ │
* │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │
* ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │
* │ │ │ [[MixedNode.bundleOut]]─┐ │ │
* │ │ │ ↑ ↓ │ │
* │ │ │ │ [[MixedNode.out]] │ │
* │ ↓ ↓ │ ↑ │ │
* │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │
* │ │ (from the other node) ↑ │ │
* │ │ │ │ │ │
* │ │ │ [[MixedNode.outer.edgeO]] │ │
* │ │ │ (based on protocol) │ │
* │ │ │ │ │ │
* │ │ │ ┌────────────────────────────────────────┤ │ │
* │ │ │ │ │ │ │
* │ │ │ │ │ │ │
* │ │ │ │ │ │ │
* (immobilize after elaboration)│ ↓ │ │ │ │
* [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │
* ↑ (inward port from [[OutwardNode]]) │ │ │ │
* │ ┌─────────────────────────────────────────┤ │ │ │
* │ │ │ │ │ │
* │ │ │ │ │ │
* [[OutwardNode.accPO]] │ ↓ │ │ │
* (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │
* │ ↑ │ │
* │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │
* └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘
* }}}
*/
abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data](
val inner: InwardNodeImp[DI, UI, EI, BI],
val outer: OutwardNodeImp[DO, UO, EO, BO]
)(
implicit valName: ValName)
extends BaseNode
with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO]
with InwardNode[DI, UI, BI]
with OutwardNode[DO, UO, BO] {
// Generate a [[NodeHandle]] with inward and outward node are both this node.
val inward = this
val outward = this
/** Debug info of nodes binding. */
def bindingInfo: String = s"""$iBindingInfo
|$oBindingInfo
|""".stripMargin
/** Debug info of ports connecting. */
def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}]
|${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}]
|""".stripMargin
/** Debug info of parameters propagations. */
def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}]
|${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}]
|${diParams.size} downstream inward parameters: [${diParams.mkString(",")}]
|${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}]
|""".stripMargin
/** For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and
* [[MixedNode.iPortMapping]].
*
* Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward
* stars and outward stars.
*
* This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type
* of node.
*
* @param iKnown
* Number of known-size ([[BIND_ONCE]]) input bindings.
* @param oKnown
* Number of known-size ([[BIND_ONCE]]) output bindings.
* @param iStar
* Number of unknown size ([[BIND_STAR]]) input bindings.
* @param oStar
* Number of unknown size ([[BIND_STAR]]) output bindings.
* @return
* A Tuple of the resolved number of input and output connections.
*/
protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int)
/** Function to generate downward-flowing outward params from the downward-flowing input params and the current output
* ports.
*
* @param n
* The size of the output sequence to generate.
* @param p
* Sequence of downward-flowing input parameters of this node.
* @return
* A `n`-sized sequence of downward-flowing output edge parameters.
*/
protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO]
/** Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]].
*
* @param n
* Size of the output sequence.
* @param p
* Upward-flowing output edge parameters.
* @return
* A n-sized sequence of upward-flowing input edge parameters.
*/
protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI]
/** @return
* The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with
* [[BIND_STAR]].
*/
protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR)
/** @return
* The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of
* output bindings bound with [[BIND_STAR]].
*/
protected[diplomacy] lazy val sourceCard: Int =
iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR)
/** @return list of nodes involved in flex bindings with this node. */
protected[diplomacy] lazy val flexes: Seq[BaseNode] =
oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2)
/** Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin
* greedily taking up the remaining connections.
*
* @return
* A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return
* value is not relevant.
*/
protected[diplomacy] lazy val flexOffset: Int = {
/** Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex
* operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a
* connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of
* each node in the current set and decide whether they should be added to the set or not.
*
* @return
* the mapping of [[BaseNode]] indexed by their serial numbers.
*/
def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = {
if (visited.contains(v.serial) || !v.flexibleArityDirection) {
visited
} else {
v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum))
}
}
/** Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node.
*
* @example
* {{{
* a :*=* b :*=* c
* d :*=* b
* e :*=* f
* }}}
*
* `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)`
*/
val flexSet = DFS(this, Map()).values
/** The total number of :*= operators where we're on the left. */
val allSink = flexSet.map(_.sinkCard).sum
/** The total number of :=* operators used when we're on the right. */
val allSource = flexSet.map(_.sourceCard).sum
require(
allSink == 0 || allSource == 0,
s"The nodes ${flexSet.map(_.name)} which are inter-connected by :*=* have ${allSink} :*= operators and ${allSource} :=* operators connected to them, making it impossible to determine cardinality inference direction."
)
allSink - allSource
}
/** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. */
protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = {
if (flexibleArityDirection) flexOffset
else if (n.flexibleArityDirection) n.flexOffset
else 0
}
/** For a node which is connected between two nodes, select the one that will influence the direction of the flex
* resolution.
*/
protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = {
val dir = edgeArityDirection(n)
if (dir < 0) l
else if (dir > 0) r
else 1
}
/** Ensure that the same node is not visited twice in resolving `:*=`, etc operators. */
private var starCycleGuard = false
/** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star"
* connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also
* need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct
* edge parameters and later build up correct bundle connections.
*
* [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding
* operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort
* (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N :*= foo` or `N :*=* foo :*=
* bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo :*=* N`
*/
protected[diplomacy] lazy val (
oPortMapping: Seq[(Int, Int)],
iPortMapping: Seq[(Int, Int)],
oStar: Int,
iStar: Int
) = {
try {
if (starCycleGuard) throw StarCycleException()
starCycleGuard = true
// For a given node N...
// Number of foo :=* N
// + Number of bar :=* foo :*=* N
val oStars = oBindings.count { case (_, n, b, _, _) =>
b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) < 0)
}
// Number of N :*= foo
// + Number of N :*=* foo :*= bar
val iStars = iBindings.count { case (_, n, b, _, _) =>
b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) > 0)
}
// 1 for foo := N
// + bar.iStar for bar :*= foo :*=* N
// + foo.iStar for foo :*= N
// + 0 for foo :=* N
val oKnown = oBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, 0, n.iStar)
case BIND_QUERY => n.iStar
case BIND_STAR => 0
}
}.sum
// 1 for N := foo
// + bar.oStar for N :*=* foo :=* bar
// + foo.oStar for N :=* foo
// + 0 for N :*= foo
val iKnown = iBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, n.oStar, 0)
case BIND_QUERY => n.oStar
case BIND_STAR => 0
}
}.sum
// Resolve star depends on the node subclass to implement the algorithm for this.
val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars)
// Cumulative list of resolved outward binding range starting points
val oSum = oBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar)
case BIND_QUERY => n.iStar
case BIND_STAR => oStar
}
}.scanLeft(0)(_ + _)
// Cumulative list of resolved inward binding range starting points
val iSum = iBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar)
case BIND_QUERY => n.oStar
case BIND_STAR => iStar
}
}.scanLeft(0)(_ + _)
// Create ranges for each binding based on the running sums and return
// those along with resolved values for the star operations.
(oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar)
} catch {
case c: StarCycleException => throw c.copy(loop = context +: c.loop)
}
}
/** Sequence of inward ports.
*
* This should be called after all star bindings are resolved.
*
* Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding.
* `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this
* connection was made in the source code.
*/
protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] =
oBindings.flatMap { case (i, n, _, p, s) =>
// for each binding operator in this node, look at what it connects to
val (start, end) = n.iPortMapping(i)
(start until end).map { j => (j, n, p, s) }
}
/** Sequence of outward ports.
*
* This should be called after all star bindings are resolved.
*
* `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of
* outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection
* was made in the source code.
*/
protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] =
iBindings.flatMap { case (i, n, _, p, s) =>
// query this port index range of this node in the other side of node.
val (start, end) = n.oPortMapping(i)
(start until end).map { j => (j, n, p, s) }
}
// Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree
// Thus, there must exist an Eulerian path and the below algorithms terminate
@scala.annotation.tailrec
private def oTrace(
tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)
): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match {
case (i, n, p, s) => n.iForward(i) match {
case None => (i, n, p, s)
case Some((j, m)) => oTrace((j, m, p, s))
}
}
@scala.annotation.tailrec
private def iTrace(
tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)
): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match {
case (i, n, p, s) => n.oForward(i) match {
case None => (i, n, p, s)
case Some((j, m)) => iTrace((j, m, p, s))
}
}
/** Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved.
*
* Each Port is a tuple of:
* - Numeric index of this binding in the [[InwardNode]] on the other end.
* - [[InwardNode]] on the other end of this binding.
* - A view of [[Parameters]] where the binding occurred.
* - [[SourceInfo]] for source-level error reporting.
*/
lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace)
/** Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved.
*
* Each Port is a tuple of:
* - numeric index of this binding in [[OutwardNode]] on the other end.
* - [[OutwardNode]] on the other end of this binding.
* - a view of [[Parameters]] where the binding occurred.
* - [[SourceInfo]] for source-level error reporting.
*/
lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace)
private var oParamsCycleGuard = false
protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) }
protected[diplomacy] lazy val doParams: Seq[DO] = {
try {
if (oParamsCycleGuard) throw DownwardCycleException()
oParamsCycleGuard = true
val o = mapParamsD(oPorts.size, diParams)
require(
o.size == oPorts.size,
s"""Diplomacy has detected a problem with your graph:
|At the following node, the number of outward ports should equal the number of produced outward parameters.
|$context
|$connectedPortsInfo
|Downstreamed inward parameters: [${diParams.mkString(",")}]
|Produced outward parameters: [${o.mkString(",")}]
|""".stripMargin
)
o.map(outer.mixO(_, this))
} catch {
case c: DownwardCycleException => throw c.copy(loop = context +: c.loop)
}
}
private var iParamsCycleGuard = false
protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) }
protected[diplomacy] lazy val uiParams: Seq[UI] = {
try {
if (iParamsCycleGuard) throw UpwardCycleException()
iParamsCycleGuard = true
val i = mapParamsU(iPorts.size, uoParams)
require(
i.size == iPorts.size,
s"""Diplomacy has detected a problem with your graph:
|At the following node, the number of inward ports should equal the number of produced inward parameters.
|$context
|$connectedPortsInfo
|Upstreamed outward parameters: [${uoParams.mkString(",")}]
|Produced inward parameters: [${i.mkString(",")}]
|""".stripMargin
)
i.map(inner.mixI(_, this))
} catch {
case c: UpwardCycleException => throw c.copy(loop = context +: c.loop)
}
}
/** Outward edge parameters. */
protected[diplomacy] lazy val edgesOut: Seq[EO] =
(oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) }
/** Inward edge parameters. */
protected[diplomacy] lazy val edgesIn: Seq[EI] =
(iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) }
/** A tuple of the input edge parameters and output edge parameters for the edges bound to this node.
*
* If you need to access to the edges of a foreign Node, use this method (in/out create bundles).
*/
lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut)
/** Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. */
protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e =>
val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out")
// TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue,
// In the future, we should add an option to decide whether allowing unconnected in the LazyModule
x := DontCare
x
}
/** Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. */
protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e =>
val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In")
// TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue,
// In the future, we should add an option to decide whether allowing unconnected in the LazyModule
x := DontCare
x
}
private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) =>
Dangle(
source = HalfEdge(serial, i),
sink = HalfEdge(n.serial, j),
flipped = false,
name = wirePrefix + "out",
dataOpt = None
)
}
private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) =>
Dangle(
source = HalfEdge(n.serial, j),
sink = HalfEdge(serial, i),
flipped = true,
name = wirePrefix + "in",
dataOpt = None
)
}
/** Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. */
protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) =>
d.copy(dataOpt = Some(bundleOut(i)))
}
/** Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. */
protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) =>
d.copy(dataOpt = Some(bundleIn(i)))
}
private[diplomacy] var instantiated = false
/** Gather Bundle and edge parameters of outward ports.
*
* Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within
* [[LazyModuleImp]] code or after its instantiation has completed.
*/
def out: Seq[(BO, EO)] = {
require(
instantiated,
s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun"
)
bundleOut.zip(edgesOut)
}
/** Gather Bundle and edge parameters of inward ports.
*
* Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within
* [[LazyModuleImp]] code or after its instantiation has completed.
*/
def in: Seq[(BI, EI)] = {
require(
instantiated,
s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun"
)
bundleIn.zip(edgesIn)
}
/** Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires,
* instantiate monitors on all input ports if appropriate, and return all the dangles of this node.
*/
protected[diplomacy] def instantiate(): Seq[Dangle] = {
instantiated = true
if (!circuitIdentity) {
(iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) }
}
danglesOut ++ danglesIn
}
protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn
/** Connects the outward part of a node with the inward part of this node. */
protected[diplomacy] def bind(
h: OutwardNode[DI, UI, BI],
binding: NodeBinding
)(
implicit p: Parameters,
sourceInfo: SourceInfo
): Unit = {
val x = this // x := y
val y = h
sourceLine(sourceInfo, " at ", "")
val i = x.iPushed
val o = y.oPushed
y.oPush(
i,
x,
binding match {
case BIND_ONCE => BIND_ONCE
case BIND_FLEX => BIND_FLEX
case BIND_STAR => BIND_QUERY
case BIND_QUERY => BIND_STAR
}
)
x.iPush(o, y, binding)
}
/* Metadata for printing the node graph. */
def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) =>
val re = inner.render(e)
(n, re.copy(flipped = re.flipped != p(RenderFlipped)))
}
/** Metadata for printing the node graph */
def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) }
}
File Xbar.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.interrupts
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy.lazymodule._
class IntXbar()(implicit p: Parameters) extends LazyModule
{
val intnode = new IntNexusNode(
sinkFn = { _ => IntSinkPortParameters(Seq(IntSinkParameters())) },
sourceFn = { seq =>
IntSourcePortParameters((seq zip seq.map(_.num).scanLeft(0)(_+_).init).map {
case (s, o) => s.sources.map(z => z.copy(range = z.range.offset(o)))
}.flatten)
})
{
override def circuitIdentity = outputs == 1 && inputs == 1
}
lazy val module = new Impl
class Impl extends LazyRawModuleImp(this) {
override def desiredName = s"IntXbar_i${intnode.in.size}_o${intnode.out.size}"
val cat = intnode.in.map { case (i, e) => i.take(e.source.num) }.flatten
intnode.out.foreach { case (o, _) => o := cat }
}
}
class IntSyncXbar()(implicit p: Parameters) extends LazyModule
{
val intnode = new IntSyncNexusNode(
sinkFn = { _ => IntSinkPortParameters(Seq(IntSinkParameters())) },
sourceFn = { seq =>
IntSourcePortParameters((seq zip seq.map(_.num).scanLeft(0)(_+_).init).map {
case (s, o) => s.sources.map(z => z.copy(range = z.range.offset(o)))
}.flatten)
})
{
override def circuitIdentity = outputs == 1 && inputs == 1
}
lazy val module = new Impl
class Impl extends LazyModuleImp(this) {
override def desiredName = s"IntSyncXbar_i${intnode.in.size}_o${intnode.out.size}"
val cat = intnode.in.map { case (i, e) => i.sync.take(e.source.num) }.flatten
intnode.out.foreach { case (o, _) => o.sync := cat }
}
}
object IntXbar {
def apply()(implicit p: Parameters): IntNode = {
val xbar = LazyModule(new IntXbar)
xbar.intnode
}
}
object IntSyncXbar {
def apply()(implicit p: Parameters): IntSyncNode = {
val xbar = LazyModule(new IntSyncXbar)
xbar.intnode
}
}
| module IntXbar_i4_o1( // @[Xbar.scala:22:9]
input auto_anon_in_3_0, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_2_0, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_1_0, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_1_1, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_0_0, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_0, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_1, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_2, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_3, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_4 // @[LazyModuleImp.scala:107:25]
);
wire auto_anon_in_3_0_0 = auto_anon_in_3_0; // @[Xbar.scala:22:9]
wire auto_anon_in_2_0_0 = auto_anon_in_2_0; // @[Xbar.scala:22:9]
wire auto_anon_in_1_0_0 = auto_anon_in_1_0; // @[Xbar.scala:22:9]
wire auto_anon_in_1_1_0 = auto_anon_in_1_1; // @[Xbar.scala:22:9]
wire auto_anon_in_0_0_0 = auto_anon_in_0_0; // @[Xbar.scala:22:9]
wire childClock = 1'h0; // @[LazyModuleImp.scala:155:31]
wire childReset = 1'h0; // @[LazyModuleImp.scala:158:31]
wire _childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25]
wire anonIn_3_0 = auto_anon_in_3_0_0; // @[Xbar.scala:22:9]
wire anonIn_2_0 = auto_anon_in_2_0_0; // @[Xbar.scala:22:9]
wire anonIn_1_0 = auto_anon_in_1_0_0; // @[Xbar.scala:22:9]
wire anonIn_1_1 = auto_anon_in_1_1_0; // @[Xbar.scala:22:9]
wire anonIn_0 = auto_anon_in_0_0_0; // @[Xbar.scala:22:9]
wire anonOut_0; // @[MixedNode.scala:542:17]
wire anonOut_1; // @[MixedNode.scala:542:17]
wire anonOut_2; // @[MixedNode.scala:542:17]
wire anonOut_3; // @[MixedNode.scala:542:17]
wire anonOut_4; // @[MixedNode.scala:542:17]
wire auto_anon_out_0_0; // @[Xbar.scala:22:9]
wire auto_anon_out_1_0; // @[Xbar.scala:22:9]
wire auto_anon_out_2_0; // @[Xbar.scala:22:9]
wire auto_anon_out_3_0; // @[Xbar.scala:22:9]
wire auto_anon_out_4_0; // @[Xbar.scala:22:9]
assign anonOut_0 = anonIn_0; // @[MixedNode.scala:542:17, :551:17]
assign anonOut_1 = anonIn_1_0; // @[MixedNode.scala:542:17, :551:17]
assign anonOut_2 = anonIn_1_1; // @[MixedNode.scala:542:17, :551:17]
assign anonOut_3 = anonIn_2_0; // @[MixedNode.scala:542:17, :551:17]
assign anonOut_4 = anonIn_3_0; // @[MixedNode.scala:542:17, :551:17]
assign auto_anon_out_0_0 = anonOut_0; // @[Xbar.scala:22:9]
assign auto_anon_out_1_0 = anonOut_1; // @[Xbar.scala:22:9]
assign auto_anon_out_2_0 = anonOut_2; // @[Xbar.scala:22:9]
assign auto_anon_out_3_0 = anonOut_3; // @[Xbar.scala:22:9]
assign auto_anon_out_4_0 = anonOut_4; // @[Xbar.scala:22:9]
assign auto_anon_out_0 = auto_anon_out_0_0; // @[Xbar.scala:22:9]
assign auto_anon_out_1 = auto_anon_out_1_0; // @[Xbar.scala:22:9]
assign auto_anon_out_2 = auto_anon_out_2_0; // @[Xbar.scala:22:9]
assign auto_anon_out_3 = auto_anon_out_3_0; // @[Xbar.scala:22:9]
assign auto_anon_out_4 = auto_anon_out_4_0; // @[Xbar.scala:22:9]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File Crossing.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.interrupts
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy.lazymodule._
import freechips.rocketchip.util.{SynchronizerShiftReg, AsyncResetReg}
@deprecated("IntXing does not ensure interrupt source is glitch free. Use IntSyncSource and IntSyncSink", "rocket-chip 1.2")
class IntXing(sync: Int = 3)(implicit p: Parameters) extends LazyModule
{
val intnode = IntAdapterNode()
lazy val module = new Impl
class Impl extends LazyModuleImp(this) {
(intnode.in zip intnode.out) foreach { case ((in, _), (out, _)) =>
out := SynchronizerShiftReg(in, sync)
}
}
}
object IntSyncCrossingSource
{
def apply(alreadyRegistered: Boolean = false)(implicit p: Parameters) =
{
val intsource = LazyModule(new IntSyncCrossingSource(alreadyRegistered))
intsource.node
}
}
class IntSyncCrossingSource(alreadyRegistered: Boolean = false)(implicit p: Parameters) extends LazyModule
{
val node = IntSyncSourceNode(alreadyRegistered)
lazy val module = if (alreadyRegistered) (new ImplRegistered) else (new Impl)
class Impl extends LazyModuleImp(this) {
def outSize = node.out.headOption.map(_._1.sync.size).getOrElse(0)
override def desiredName = s"IntSyncCrossingSource_n${node.out.size}x${outSize}"
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
out.sync := AsyncResetReg(Cat(in.reverse)).asBools
}
}
class ImplRegistered extends LazyRawModuleImp(this) {
def outSize = node.out.headOption.map(_._1.sync.size).getOrElse(0)
override def desiredName = s"IntSyncCrossingSource_n${node.out.size}x${outSize}_Registered"
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
out.sync := in
}
}
}
object IntSyncCrossingSink
{
@deprecated("IntSyncCrossingSink which used the `sync` parameter to determine crossing type is deprecated. Use IntSyncAsyncCrossingSink, IntSyncRationalCrossingSink, or IntSyncSyncCrossingSink instead for > 1, 1, and 0 sync values respectively", "rocket-chip 1.2")
def apply(sync: Int = 3)(implicit p: Parameters) =
{
val intsink = LazyModule(new IntSyncAsyncCrossingSink(sync))
intsink.node
}
}
class IntSyncAsyncCrossingSink(sync: Int = 3)(implicit p: Parameters) extends LazyModule
{
val node = IntSyncSinkNode(sync)
lazy val module = new Impl
class Impl extends LazyModuleImp(this) {
override def desiredName = s"IntSyncAsyncCrossingSink_n${node.out.size}x${node.out.head._1.size}"
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
out := SynchronizerShiftReg(in.sync, sync)
}
}
}
object IntSyncAsyncCrossingSink
{
def apply(sync: Int = 3)(implicit p: Parameters) =
{
val intsink = LazyModule(new IntSyncAsyncCrossingSink(sync))
intsink.node
}
}
class IntSyncSyncCrossingSink()(implicit p: Parameters) extends LazyModule
{
val node = IntSyncSinkNode(0)
lazy val module = new Impl
class Impl extends LazyRawModuleImp(this) {
def outSize = node.out.headOption.map(_._1.size).getOrElse(0)
override def desiredName = s"IntSyncSyncCrossingSink_n${node.out.size}x${outSize}"
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
out := in.sync
}
}
}
object IntSyncSyncCrossingSink
{
def apply()(implicit p: Parameters) =
{
val intsink = LazyModule(new IntSyncSyncCrossingSink())
intsink.node
}
}
class IntSyncRationalCrossingSink()(implicit p: Parameters) extends LazyModule
{
val node = IntSyncSinkNode(1)
lazy val module = new Impl
class Impl extends LazyModuleImp(this) {
def outSize = node.out.headOption.map(_._1.size).getOrElse(0)
override def desiredName = s"IntSyncRationalCrossingSink_n${node.out.size}x${outSize}"
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
out := RegNext(in.sync)
}
}
}
object IntSyncRationalCrossingSink
{
def apply()(implicit p: Parameters) =
{
val intsink = LazyModule(new IntSyncRationalCrossingSink())
intsink.node
}
}
File LazyModuleImp.scala:
package org.chipsalliance.diplomacy.lazymodule
import chisel3.{withClockAndReset, Module, RawModule, Reset, _}
import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo}
import firrtl.passes.InlineAnnotation
import org.chipsalliance.cde.config.Parameters
import org.chipsalliance.diplomacy.nodes.Dangle
import scala.collection.immutable.SortedMap
/** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]].
*
* This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy.
*/
sealed trait LazyModuleImpLike extends RawModule {
/** [[LazyModule]] that contains this instance. */
val wrapper: LazyModule
/** IOs that will be automatically "punched" for this instance. */
val auto: AutoBundle
/** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */
protected[diplomacy] val dangles: Seq[Dangle]
// [[wrapper.module]] had better not be accessed while LazyModules are still being built!
require(
LazyModule.scope.isEmpty,
s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}"
)
/** Set module name. Defaults to the containing LazyModule's desiredName. */
override def desiredName: String = wrapper.desiredName
suggestName(wrapper.suggestedName)
/** [[Parameters]] for chisel [[Module]]s. */
implicit val p: Parameters = wrapper.p
/** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and
* submodules.
*/
protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = {
// 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]],
// 2. return [[Dangle]]s from each module.
val childDangles = wrapper.children.reverse.flatMap { c =>
implicit val sourceInfo: SourceInfo = c.info
c.cloneProto.map { cp =>
// If the child is a clone, then recursively set cloneProto of its children as well
def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = {
require(bases.size == clones.size)
(bases.zip(clones)).map { case (l, r) =>
require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}")
l.cloneProto = Some(r)
assignCloneProtos(l.children, r.children)
}
}
assignCloneProtos(c.children, cp.children)
// Clone the child module as a record, and get its [[AutoBundle]]
val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName)
val clonedAuto = clone("auto").asInstanceOf[AutoBundle]
// Get the empty [[Dangle]]'s of the cloned child
val rawDangles = c.cloneDangles()
require(rawDangles.size == clonedAuto.elements.size)
// Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s
val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) }
dangles
}.getOrElse {
// For non-clones, instantiate the child module
val mod = try {
Module(c.module)
} catch {
case e: ChiselException => {
println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}")
throw e
}
}
mod.dangles
}
}
// Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]].
// This will result in a sequence of [[Dangle]] from these [[BaseNode]]s.
val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate())
// Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]]
val allDangles = nodeDangles ++ childDangles
// Group [[allDangles]] by their [[source]].
val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*)
// For each [[source]] set of [[Dangle]]s of size 2, ensure that these
// can be connected as a source-sink pair (have opposite flipped value).
// Make the connection and mark them as [[done]].
val done = Set() ++ pairing.values.filter(_.size == 2).map {
case Seq(a, b) =>
require(a.flipped != b.flipped)
// @todo <> in chisel3 makes directionless connection.
if (a.flipped) {
a.data <> b.data
} else {
b.data <> a.data
}
a.source
case _ => None
}
// Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module.
val forward = allDangles.filter(d => !done(d.source))
// Generate [[AutoBundle]] IO from [[forward]].
val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*))
// Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]]
val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) =>
if (d.flipped) {
d.data <> io
} else {
io <> d.data
}
d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name)
}
// Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]].
wrapper.inModuleBody.reverse.foreach {
_()
}
if (wrapper.shouldBeInlined) {
chisel3.experimental.annotate(new ChiselAnnotation {
def toFirrtl = InlineAnnotation(toNamed)
})
}
// Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]].
(auto, dangles)
}
}
/** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike {
/** Instantiate hardware of this `Module`. */
val (auto, dangles) = instantiate()
}
/** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike {
// These wires are the default clock+reset for all LazyModule children.
// It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the
// [[LazyRawModuleImp]] children.
// Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly.
/** drive clock explicitly. */
val childClock: Clock = Wire(Clock())
/** drive reset explicitly. */
val childReset: Reset = Wire(Reset())
// the default is that these are disabled
childClock := false.B.asClock
childReset := chisel3.DontCare
def provideImplicitClockToLazyChildren: Boolean = false
val (auto, dangles) =
if (provideImplicitClockToLazyChildren) {
withClockAndReset(childClock, childReset) { instantiate() }
} else {
instantiate()
}
}
File MixedNode.scala:
package org.chipsalliance.diplomacy.nodes
import chisel3.{Data, DontCare, Wire}
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.{Field, Parameters}
import org.chipsalliance.diplomacy.ValName
import org.chipsalliance.diplomacy.sourceLine
/** One side metadata of a [[Dangle]].
*
* Describes one side of an edge going into or out of a [[BaseNode]].
*
* @param serial
* the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to.
* @param index
* the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to.
*/
case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] {
import scala.math.Ordered.orderingToOrdered
def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that))
}
/** [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]]
* connects.
*
* [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] ,
* [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]].
*
* @param source
* the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within
* that [[BaseNode]].
* @param sink
* sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that
* [[BaseNode]].
* @param flipped
* flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to
* `danglesIn`.
* @param dataOpt
* actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module
*/
case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) {
def data = dataOpt.get
}
/** [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often
* derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually
* implement the protocol.
*/
case class Edges[EI, EO](in: Seq[EI], out: Seq[EO])
/** A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. */
case object MonitorsEnabled extends Field[Boolean](true)
/** When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented.
*
* For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but
* [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink
* nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the
* [[LazyModule]].
*/
case object RenderFlipped extends Field[Boolean](false)
/** The sealed node class in the package, all node are derived from it.
*
* @param inner
* Sink interface implementation.
* @param outer
* Source interface implementation.
* @param valName
* val name of this node.
* @tparam DI
* Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters
* describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected
* [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port
* parameters.
* @tparam UI
* Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing
* the protocol parameters of a sink. For an [[InwardNode]], it is determined itself.
* @tparam EI
* Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers
* specified for a sink according to protocol.
* @tparam BI
* Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface.
* It should extends from [[chisel3.Data]], which represents the real hardware.
* @tparam DO
* Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters
* describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself.
* @tparam UO
* Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing
* the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]].
* Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters.
* @tparam EO
* Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers
* specified for a source according to protocol.
* @tparam BO
* Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source
* interface. It should extends from [[chisel3.Data]], which represents the real hardware.
*
* @note
* Call Graph of [[MixedNode]]
* - line `─`: source is process by a function and generate pass to others
* - Arrow `→`: target of arrow is generated by source
*
* {{{
* (from the other node)
* ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐
* ↓ │
* (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │
* [[InwardNode.accPI]] │ │ │
* │ │ (based on protocol) │
* │ │ [[MixedNode.inner.edgeI]] │
* │ │ ↓ │
* ↓ │ │ │
* (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │
* [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │
* │ │ ↑ │ │ │
* │ │ │ [[OutwardNode.doParams]] │ │
* │ │ │ (from the other node) │ │
* │ │ │ │ │ │
* │ │ │ │ │ │
* │ │ │ └────────┬──────────────┤ │
* │ │ │ │ │ │
* │ │ │ │ (based on protocol) │
* │ │ │ │ [[MixedNode.inner.edgeI]] │
* │ │ │ │ │ │
* │ │ (from the other node) │ ↓ │
* │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │
* │ ↑ ↑ │ │ ↓ │
* │ │ │ │ │ [[MixedNode.in]] │
* │ │ │ │ ↓ ↑ │
* │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │
* ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │
* │ │ │ [[MixedNode.bundleOut]]─┐ │ │
* │ │ │ ↑ ↓ │ │
* │ │ │ │ [[MixedNode.out]] │ │
* │ ↓ ↓ │ ↑ │ │
* │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │
* │ │ (from the other node) ↑ │ │
* │ │ │ │ │ │
* │ │ │ [[MixedNode.outer.edgeO]] │ │
* │ │ │ (based on protocol) │ │
* │ │ │ │ │ │
* │ │ │ ┌────────────────────────────────────────┤ │ │
* │ │ │ │ │ │ │
* │ │ │ │ │ │ │
* │ │ │ │ │ │ │
* (immobilize after elaboration)│ ↓ │ │ │ │
* [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │
* ↑ (inward port from [[OutwardNode]]) │ │ │ │
* │ ┌─────────────────────────────────────────┤ │ │ │
* │ │ │ │ │ │
* │ │ │ │ │ │
* [[OutwardNode.accPO]] │ ↓ │ │ │
* (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │
* │ ↑ │ │
* │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │
* └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘
* }}}
*/
abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data](
val inner: InwardNodeImp[DI, UI, EI, BI],
val outer: OutwardNodeImp[DO, UO, EO, BO]
)(
implicit valName: ValName)
extends BaseNode
with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO]
with InwardNode[DI, UI, BI]
with OutwardNode[DO, UO, BO] {
// Generate a [[NodeHandle]] with inward and outward node are both this node.
val inward = this
val outward = this
/** Debug info of nodes binding. */
def bindingInfo: String = s"""$iBindingInfo
|$oBindingInfo
|""".stripMargin
/** Debug info of ports connecting. */
def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}]
|${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}]
|""".stripMargin
/** Debug info of parameters propagations. */
def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}]
|${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}]
|${diParams.size} downstream inward parameters: [${diParams.mkString(",")}]
|${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}]
|""".stripMargin
/** For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and
* [[MixedNode.iPortMapping]].
*
* Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward
* stars and outward stars.
*
* This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type
* of node.
*
* @param iKnown
* Number of known-size ([[BIND_ONCE]]) input bindings.
* @param oKnown
* Number of known-size ([[BIND_ONCE]]) output bindings.
* @param iStar
* Number of unknown size ([[BIND_STAR]]) input bindings.
* @param oStar
* Number of unknown size ([[BIND_STAR]]) output bindings.
* @return
* A Tuple of the resolved number of input and output connections.
*/
protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int)
/** Function to generate downward-flowing outward params from the downward-flowing input params and the current output
* ports.
*
* @param n
* The size of the output sequence to generate.
* @param p
* Sequence of downward-flowing input parameters of this node.
* @return
* A `n`-sized sequence of downward-flowing output edge parameters.
*/
protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO]
/** Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]].
*
* @param n
* Size of the output sequence.
* @param p
* Upward-flowing output edge parameters.
* @return
* A n-sized sequence of upward-flowing input edge parameters.
*/
protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI]
/** @return
* The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with
* [[BIND_STAR]].
*/
protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR)
/** @return
* The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of
* output bindings bound with [[BIND_STAR]].
*/
protected[diplomacy] lazy val sourceCard: Int =
iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR)
/** @return list of nodes involved in flex bindings with this node. */
protected[diplomacy] lazy val flexes: Seq[BaseNode] =
oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2)
/** Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin
* greedily taking up the remaining connections.
*
* @return
* A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return
* value is not relevant.
*/
protected[diplomacy] lazy val flexOffset: Int = {
/** Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex
* operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a
* connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of
* each node in the current set and decide whether they should be added to the set or not.
*
* @return
* the mapping of [[BaseNode]] indexed by their serial numbers.
*/
def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = {
if (visited.contains(v.serial) || !v.flexibleArityDirection) {
visited
} else {
v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum))
}
}
/** Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node.
*
* @example
* {{{
* a :*=* b :*=* c
* d :*=* b
* e :*=* f
* }}}
*
* `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)`
*/
val flexSet = DFS(this, Map()).values
/** The total number of :*= operators where we're on the left. */
val allSink = flexSet.map(_.sinkCard).sum
/** The total number of :=* operators used when we're on the right. */
val allSource = flexSet.map(_.sourceCard).sum
require(
allSink == 0 || allSource == 0,
s"The nodes ${flexSet.map(_.name)} which are inter-connected by :*=* have ${allSink} :*= operators and ${allSource} :=* operators connected to them, making it impossible to determine cardinality inference direction."
)
allSink - allSource
}
/** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. */
protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = {
if (flexibleArityDirection) flexOffset
else if (n.flexibleArityDirection) n.flexOffset
else 0
}
/** For a node which is connected between two nodes, select the one that will influence the direction of the flex
* resolution.
*/
protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = {
val dir = edgeArityDirection(n)
if (dir < 0) l
else if (dir > 0) r
else 1
}
/** Ensure that the same node is not visited twice in resolving `:*=`, etc operators. */
private var starCycleGuard = false
/** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star"
* connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also
* need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct
* edge parameters and later build up correct bundle connections.
*
* [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding
* operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort
* (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N :*= foo` or `N :*=* foo :*=
* bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo :*=* N`
*/
protected[diplomacy] lazy val (
oPortMapping: Seq[(Int, Int)],
iPortMapping: Seq[(Int, Int)],
oStar: Int,
iStar: Int
) = {
try {
if (starCycleGuard) throw StarCycleException()
starCycleGuard = true
// For a given node N...
// Number of foo :=* N
// + Number of bar :=* foo :*=* N
val oStars = oBindings.count { case (_, n, b, _, _) =>
b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) < 0)
}
// Number of N :*= foo
// + Number of N :*=* foo :*= bar
val iStars = iBindings.count { case (_, n, b, _, _) =>
b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) > 0)
}
// 1 for foo := N
// + bar.iStar for bar :*= foo :*=* N
// + foo.iStar for foo :*= N
// + 0 for foo :=* N
val oKnown = oBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, 0, n.iStar)
case BIND_QUERY => n.iStar
case BIND_STAR => 0
}
}.sum
// 1 for N := foo
// + bar.oStar for N :*=* foo :=* bar
// + foo.oStar for N :=* foo
// + 0 for N :*= foo
val iKnown = iBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, n.oStar, 0)
case BIND_QUERY => n.oStar
case BIND_STAR => 0
}
}.sum
// Resolve star depends on the node subclass to implement the algorithm for this.
val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars)
// Cumulative list of resolved outward binding range starting points
val oSum = oBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar)
case BIND_QUERY => n.iStar
case BIND_STAR => oStar
}
}.scanLeft(0)(_ + _)
// Cumulative list of resolved inward binding range starting points
val iSum = iBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar)
case BIND_QUERY => n.oStar
case BIND_STAR => iStar
}
}.scanLeft(0)(_ + _)
// Create ranges for each binding based on the running sums and return
// those along with resolved values for the star operations.
(oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar)
} catch {
case c: StarCycleException => throw c.copy(loop = context +: c.loop)
}
}
/** Sequence of inward ports.
*
* This should be called after all star bindings are resolved.
*
* Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding.
* `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this
* connection was made in the source code.
*/
protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] =
oBindings.flatMap { case (i, n, _, p, s) =>
// for each binding operator in this node, look at what it connects to
val (start, end) = n.iPortMapping(i)
(start until end).map { j => (j, n, p, s) }
}
/** Sequence of outward ports.
*
* This should be called after all star bindings are resolved.
*
* `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of
* outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection
* was made in the source code.
*/
protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] =
iBindings.flatMap { case (i, n, _, p, s) =>
// query this port index range of this node in the other side of node.
val (start, end) = n.oPortMapping(i)
(start until end).map { j => (j, n, p, s) }
}
// Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree
// Thus, there must exist an Eulerian path and the below algorithms terminate
@scala.annotation.tailrec
private def oTrace(
tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)
): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match {
case (i, n, p, s) => n.iForward(i) match {
case None => (i, n, p, s)
case Some((j, m)) => oTrace((j, m, p, s))
}
}
@scala.annotation.tailrec
private def iTrace(
tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)
): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match {
case (i, n, p, s) => n.oForward(i) match {
case None => (i, n, p, s)
case Some((j, m)) => iTrace((j, m, p, s))
}
}
/** Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved.
*
* Each Port is a tuple of:
* - Numeric index of this binding in the [[InwardNode]] on the other end.
* - [[InwardNode]] on the other end of this binding.
* - A view of [[Parameters]] where the binding occurred.
* - [[SourceInfo]] for source-level error reporting.
*/
lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace)
/** Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved.
*
* Each Port is a tuple of:
* - numeric index of this binding in [[OutwardNode]] on the other end.
* - [[OutwardNode]] on the other end of this binding.
* - a view of [[Parameters]] where the binding occurred.
* - [[SourceInfo]] for source-level error reporting.
*/
lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace)
private var oParamsCycleGuard = false
protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) }
protected[diplomacy] lazy val doParams: Seq[DO] = {
try {
if (oParamsCycleGuard) throw DownwardCycleException()
oParamsCycleGuard = true
val o = mapParamsD(oPorts.size, diParams)
require(
o.size == oPorts.size,
s"""Diplomacy has detected a problem with your graph:
|At the following node, the number of outward ports should equal the number of produced outward parameters.
|$context
|$connectedPortsInfo
|Downstreamed inward parameters: [${diParams.mkString(",")}]
|Produced outward parameters: [${o.mkString(",")}]
|""".stripMargin
)
o.map(outer.mixO(_, this))
} catch {
case c: DownwardCycleException => throw c.copy(loop = context +: c.loop)
}
}
private var iParamsCycleGuard = false
protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) }
protected[diplomacy] lazy val uiParams: Seq[UI] = {
try {
if (iParamsCycleGuard) throw UpwardCycleException()
iParamsCycleGuard = true
val i = mapParamsU(iPorts.size, uoParams)
require(
i.size == iPorts.size,
s"""Diplomacy has detected a problem with your graph:
|At the following node, the number of inward ports should equal the number of produced inward parameters.
|$context
|$connectedPortsInfo
|Upstreamed outward parameters: [${uoParams.mkString(",")}]
|Produced inward parameters: [${i.mkString(",")}]
|""".stripMargin
)
i.map(inner.mixI(_, this))
} catch {
case c: UpwardCycleException => throw c.copy(loop = context +: c.loop)
}
}
/** Outward edge parameters. */
protected[diplomacy] lazy val edgesOut: Seq[EO] =
(oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) }
/** Inward edge parameters. */
protected[diplomacy] lazy val edgesIn: Seq[EI] =
(iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) }
/** A tuple of the input edge parameters and output edge parameters for the edges bound to this node.
*
* If you need to access to the edges of a foreign Node, use this method (in/out create bundles).
*/
lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut)
/** Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. */
protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e =>
val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out")
// TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue,
// In the future, we should add an option to decide whether allowing unconnected in the LazyModule
x := DontCare
x
}
/** Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. */
protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e =>
val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In")
// TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue,
// In the future, we should add an option to decide whether allowing unconnected in the LazyModule
x := DontCare
x
}
private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) =>
Dangle(
source = HalfEdge(serial, i),
sink = HalfEdge(n.serial, j),
flipped = false,
name = wirePrefix + "out",
dataOpt = None
)
}
private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) =>
Dangle(
source = HalfEdge(n.serial, j),
sink = HalfEdge(serial, i),
flipped = true,
name = wirePrefix + "in",
dataOpt = None
)
}
/** Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. */
protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) =>
d.copy(dataOpt = Some(bundleOut(i)))
}
/** Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. */
protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) =>
d.copy(dataOpt = Some(bundleIn(i)))
}
private[diplomacy] var instantiated = false
/** Gather Bundle and edge parameters of outward ports.
*
* Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within
* [[LazyModuleImp]] code or after its instantiation has completed.
*/
def out: Seq[(BO, EO)] = {
require(
instantiated,
s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun"
)
bundleOut.zip(edgesOut)
}
/** Gather Bundle and edge parameters of inward ports.
*
* Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within
* [[LazyModuleImp]] code or after its instantiation has completed.
*/
def in: Seq[(BI, EI)] = {
require(
instantiated,
s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun"
)
bundleIn.zip(edgesIn)
}
/** Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires,
* instantiate monitors on all input ports if appropriate, and return all the dangles of this node.
*/
protected[diplomacy] def instantiate(): Seq[Dangle] = {
instantiated = true
if (!circuitIdentity) {
(iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) }
}
danglesOut ++ danglesIn
}
protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn
/** Connects the outward part of a node with the inward part of this node. */
protected[diplomacy] def bind(
h: OutwardNode[DI, UI, BI],
binding: NodeBinding
)(
implicit p: Parameters,
sourceInfo: SourceInfo
): Unit = {
val x = this // x := y
val y = h
sourceLine(sourceInfo, " at ", "")
val i = x.iPushed
val o = y.oPushed
y.oPush(
i,
x,
binding match {
case BIND_ONCE => BIND_ONCE
case BIND_FLEX => BIND_FLEX
case BIND_STAR => BIND_QUERY
case BIND_QUERY => BIND_STAR
}
)
x.iPush(o, y, binding)
}
/* Metadata for printing the node graph. */
def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) =>
val re = inner.render(e)
(n, re.copy(flipped = re.flipped != p(RenderFlipped)))
}
/** Metadata for printing the node graph */
def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) }
}
File AsyncResetReg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
/** This black-boxes an Async Reset
* (or Set)
* Register.
*
* Because Chisel doesn't support
* parameterized black boxes,
* we unfortunately have to
* instantiate a number of these.
*
* We also have to hard-code the set/
* reset behavior.
*
* Do not confuse an asynchronous
* reset signal with an asynchronously
* reset reg. You should still
* properly synchronize your reset
* deassertion.
*
* @param d Data input
* @param q Data Output
* @param clk Clock Input
* @param rst Reset Input
* @param en Write Enable Input
*
*/
class AsyncResetReg(resetValue: Int = 0) extends RawModule {
val io = IO(new Bundle {
val d = Input(Bool())
val q = Output(Bool())
val en = Input(Bool())
val clk = Input(Clock())
val rst = Input(Reset())
})
val reg = withClockAndReset(io.clk, io.rst.asAsyncReset)(RegInit(resetValue.U(1.W)))
when (io.en) {
reg := io.d
}
io.q := reg
}
class SimpleRegIO(val w: Int) extends Bundle{
val d = Input(UInt(w.W))
val q = Output(UInt(w.W))
val en = Input(Bool())
}
class AsyncResetRegVec(val w: Int, val init: BigInt) extends Module {
override def desiredName = s"AsyncResetRegVec_w${w}_i${init}"
val io = IO(new SimpleRegIO(w))
val reg = withReset(reset.asAsyncReset)(RegInit(init.U(w.W)))
when (io.en) {
reg := io.d
}
io.q := reg
}
object AsyncResetReg {
// Create Single Registers
def apply(d: Bool, clk: Clock, rst: Bool, init: Boolean, name: Option[String]): Bool = {
val reg = Module(new AsyncResetReg(if (init) 1 else 0))
reg.io.d := d
reg.io.clk := clk
reg.io.rst := rst
reg.io.en := true.B
name.foreach(reg.suggestName(_))
reg.io.q
}
def apply(d: Bool, clk: Clock, rst: Bool): Bool = apply(d, clk, rst, false, None)
def apply(d: Bool, clk: Clock, rst: Bool, name: String): Bool = apply(d, clk, rst, false, Some(name))
// Create Vectors of Registers
def apply(updateData: UInt, resetData: BigInt, enable: Bool, name: Option[String] = None): UInt = {
val w = updateData.getWidth max resetData.bitLength
val reg = Module(new AsyncResetRegVec(w, resetData))
name.foreach(reg.suggestName(_))
reg.io.d := updateData
reg.io.en := enable
reg.io.q
}
def apply(updateData: UInt, resetData: BigInt, enable: Bool, name: String): UInt = apply(updateData,
resetData, enable, Some(name))
def apply(updateData: UInt, resetData: BigInt): UInt = apply(updateData, resetData, enable = true.B)
def apply(updateData: UInt, resetData: BigInt, name: String): UInt = apply(updateData, resetData, enable = true.B, Some(name))
def apply(updateData: UInt, enable: Bool): UInt = apply(updateData, resetData=BigInt(0), enable)
def apply(updateData: UInt, enable: Bool, name: String): UInt = apply(updateData, resetData = BigInt(0), enable, Some(name))
def apply(updateData: UInt): UInt = apply(updateData, resetData = BigInt(0), enable = true.B)
def apply(updateData: UInt, name:String): UInt = apply(updateData, resetData = BigInt(0), enable = true.B, Some(name))
}
| module IntSyncCrossingSource_n1x1_21( // @[Crossing.scala:41:9]
input clock, // @[Crossing.scala:41:9]
input reset, // @[Crossing.scala:41:9]
input auto_in_0, // @[LazyModuleImp.scala:107:25]
output auto_out_sync_0 // @[LazyModuleImp.scala:107:25]
);
wire auto_in_0_0 = auto_in_0; // @[Crossing.scala:41:9]
wire nodeIn_0 = auto_in_0_0; // @[Crossing.scala:41:9]
wire nodeOut_sync_0; // @[MixedNode.scala:542:17]
wire auto_out_sync_0_0; // @[Crossing.scala:41:9]
assign auto_out_sync_0_0 = nodeOut_sync_0; // @[Crossing.scala:41:9]
AsyncResetRegVec_w1_i0_21 reg_0 ( // @[AsyncResetReg.scala:86:21]
.clock (clock),
.reset (reset),
.io_d (nodeIn_0), // @[MixedNode.scala:551:17]
.io_q (nodeOut_sync_0)
); // @[AsyncResetReg.scala:86:21]
assign auto_out_sync_0 = auto_out_sync_0_0; // @[Crossing.scala:41:9]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File PlusArg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.experimental._
import chisel3.util.HasBlackBoxResource
@deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05")
case class PlusArgInfo(default: BigInt, docstring: String)
/** Case class for PlusArg information
*
* @tparam A scala type of the PlusArg value
* @param default optional default value
* @param docstring text to include in the help
* @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT)
*/
private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String)
/** Typeclass for converting a type to a doctype string
* @tparam A some type
*/
trait Doctypeable[A] {
/** Return the doctype string for some option */
def toDoctype(a: Option[A]): String
}
/** Object containing implementations of the Doctypeable typeclass */
object Doctypes {
/** Converts an Int => "INT" */
implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" }
/** Converts a BigInt => "INT" */
implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" }
/** Converts a String => "STRING" */
implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" }
}
class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map(
"FORMAT" -> StringParam(format),
"DEFAULT" -> IntParam(default),
"WIDTH" -> IntParam(width)
)) with HasBlackBoxResource {
val io = IO(new Bundle {
val out = Output(UInt(width.W))
})
addResource("/vsrc/plusarg_reader.v")
}
/* This wrapper class has no outputs, making it clear it is a simulation-only construct */
class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module {
val io = IO(new Bundle {
val count = Input(UInt(width.W))
})
val max = Module(new plusarg_reader(format, default, docstring, width)).io.out
when (max > 0.U) {
assert (io.count < max, s"Timeout exceeded: $docstring")
}
}
import Doctypes._
object PlusArg
{
/** PlusArg("foo") will return 42.U if the simulation is run with +foo=42
* Do not use this as an initial register value. The value is set in an
* initial block and thus accessing it from another initial is racey.
* Add a docstring to document the arg, which can be dumped in an elaboration
* pass.
*/
def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = {
PlusArgArtefacts.append(name, Some(default), docstring)
Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out
}
/** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert
* to kill the simulation when count exceeds the specified integer argument.
* Default 0 will never assert.
*/
def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = {
PlusArgArtefacts.append(name, Some(default), docstring)
Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count
}
}
object PlusArgArtefacts {
private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty
/* Add a new PlusArg */
@deprecated(
"Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08",
"Rocket Chip 2020.05"
)
def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring)
/** Add a new PlusArg
*
* @tparam A scala type of the PlusArg value
* @param name name for the PlusArg
* @param default optional default value
* @param docstring text to include in the help
*/
def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit =
artefacts = artefacts ++
Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default)))
/* From plus args, generate help text */
private def serializeHelp_cHeader(tab: String = ""): String = artefacts
.map{ case(arg, info) =>
s"""|$tab+$arg=${info.doctype}\\n\\
|$tab${" "*20}${info.docstring}\\n\\
|""".stripMargin ++ info.default.map{ case default =>
s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("")
}.toSeq.mkString("\\n\\\n") ++ "\""
/* From plus args, generate a char array of their names */
private def serializeArray_cHeader(tab: String = ""): String = {
val prettyTab = tab + " " * 44 // Length of 'static const ...'
s"${tab}static const char * verilog_plusargs [] = {\\\n" ++
artefacts
.map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" }
.mkString("")++
s"${prettyTab}0};"
}
/* Generate C code to be included in emulator.cc that helps with
* argument parsing based on available Verilog PlusArgs */
def serialize_cHeader(): String =
s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\
|${serializeHelp_cHeader(" "*7)}
|${serializeArray_cHeader()}
|""".stripMargin
}
File Nodes.scala:
package constellation.channel
import chisel3._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.{Parameters, Field}
import freechips.rocketchip.diplomacy._
case class EmptyParams()
case class ChannelEdgeParams(cp: ChannelParams, p: Parameters)
object ChannelImp extends SimpleNodeImp[EmptyParams, ChannelParams, ChannelEdgeParams, Channel] {
def edge(pd: EmptyParams, pu: ChannelParams, p: Parameters, sourceInfo: SourceInfo) = {
ChannelEdgeParams(pu, p)
}
def bundle(e: ChannelEdgeParams) = new Channel(e.cp)(e.p)
def render(e: ChannelEdgeParams) = if (e.cp.possibleFlows.size == 0) {
RenderedEdge(colour = "ffffff", label = "X")
} else {
RenderedEdge(colour = "#0000ff", label = e.cp.payloadBits.toString)
}
override def monitor(bundle: Channel, edge: ChannelEdgeParams): Unit = {
val monitor = Module(new NoCMonitor(edge.cp)(edge.p))
monitor.io.in := bundle
}
// TODO: Add nodepath stuff? override def mixO, override def mixI
}
case class ChannelSourceNode(val destId: Int)(implicit valName: ValName) extends SourceNode(ChannelImp)(Seq(EmptyParams()))
case class ChannelDestNode(val destParams: ChannelParams)(implicit valName: ValName) extends SinkNode(ChannelImp)(Seq(destParams))
case class ChannelAdapterNode(
slaveFn: ChannelParams => ChannelParams = { d => d })(
implicit valName: ValName) extends AdapterNode(ChannelImp)((e: EmptyParams) => e, slaveFn)
case class ChannelIdentityNode()(implicit valName: ValName) extends IdentityNode(ChannelImp)()
case class ChannelEphemeralNode()(implicit valName: ValName) extends EphemeralNode(ChannelImp)()
case class IngressChannelEdgeParams(cp: IngressChannelParams, p: Parameters)
case class EgressChannelEdgeParams(cp: EgressChannelParams, p: Parameters)
object IngressChannelImp extends SimpleNodeImp[EmptyParams, IngressChannelParams, IngressChannelEdgeParams, IngressChannel] {
def edge(pd: EmptyParams, pu: IngressChannelParams, p: Parameters, sourceInfo: SourceInfo) = {
IngressChannelEdgeParams(pu, p)
}
def bundle(e: IngressChannelEdgeParams) = new IngressChannel(e.cp)(e.p)
def render(e: IngressChannelEdgeParams) = if (e.cp.possibleFlows.size == 0) {
RenderedEdge(colour = "ffffff", label = "X")
} else {
RenderedEdge(colour = "#00ff00", label = e.cp.payloadBits.toString)
}
}
object EgressChannelImp extends SimpleNodeImp[EmptyParams, EgressChannelParams, EgressChannelEdgeParams, EgressChannel] {
def edge(pd: EmptyParams, pu: EgressChannelParams, p: Parameters, sourceInfo: SourceInfo) = {
EgressChannelEdgeParams(pu, p)
}
def bundle(e: EgressChannelEdgeParams) = new EgressChannel(e.cp)(e.p)
def render(e: EgressChannelEdgeParams) = if (e.cp.possibleFlows.size == 0) {
RenderedEdge(colour = "ffffff", label = "X")
} else {
RenderedEdge(colour = "#ff0000", label = e.cp.payloadBits.toString)
}
}
case class IngressChannelSourceNode(val destId: Int)(implicit valName: ValName) extends SourceNode(IngressChannelImp)(Seq(EmptyParams()))
case class IngressChannelDestNode(val destParams: IngressChannelParams)(implicit valName: ValName) extends SinkNode(IngressChannelImp)(Seq(destParams))
case class EgressChannelSourceNode(val egressId: Int)(implicit valName: ValName) extends SourceNode(EgressChannelImp)(Seq(EmptyParams()))
case class EgressChannelDestNode(val destParams: EgressChannelParams)(implicit valName: ValName) extends SinkNode(EgressChannelImp)(Seq(destParams))
case class IngressChannelAdapterNode(
slaveFn: IngressChannelParams => IngressChannelParams = { d => d })(
implicit valName: ValName) extends AdapterNode(IngressChannelImp)(m => m, slaveFn)
case class EgressChannelAdapterNode(
slaveFn: EgressChannelParams => EgressChannelParams = { d => d })(
implicit valName: ValName) extends AdapterNode(EgressChannelImp)(m => m, slaveFn)
case class IngressChannelIdentityNode()(implicit valName: ValName) extends IdentityNode(IngressChannelImp)()
case class EgressChannelIdentityNode()(implicit valName: ValName) extends IdentityNode(EgressChannelImp)()
case class IngressChannelEphemeralNode()(implicit valName: ValName) extends EphemeralNode(IngressChannelImp)()
case class EgressChannelEphemeralNode()(implicit valName: ValName) extends EphemeralNode(EgressChannelImp)()
File Router.scala:
package constellation.router
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.{Field, Parameters}
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.util._
import constellation.channel._
import constellation.routing.{RoutingRelation}
import constellation.noc.{HasNoCParams}
case class UserRouterParams(
// Payload width. Must match payload width on all channels attached to this routing node
payloadBits: Int = 64,
// Combines SA and ST stages (removes pipeline register)
combineSAST: Boolean = false,
// Combines RC and VA stages (removes pipeline register)
combineRCVA: Boolean = false,
// Adds combinational path from SA to VA
coupleSAVA: Boolean = false,
vcAllocator: VCAllocatorParams => Parameters => VCAllocator = (vP) => (p) => new RotatingSingleVCAllocator(vP)(p)
)
case class RouterParams(
nodeId: Int,
nIngress: Int,
nEgress: Int,
user: UserRouterParams
)
trait HasRouterOutputParams {
def outParams: Seq[ChannelParams]
def egressParams: Seq[EgressChannelParams]
def allOutParams = outParams ++ egressParams
def nOutputs = outParams.size
def nEgress = egressParams.size
def nAllOutputs = allOutParams.size
}
trait HasRouterInputParams {
def inParams: Seq[ChannelParams]
def ingressParams: Seq[IngressChannelParams]
def allInParams = inParams ++ ingressParams
def nInputs = inParams.size
def nIngress = ingressParams.size
def nAllInputs = allInParams.size
}
trait HasRouterParams
{
def routerParams: RouterParams
def nodeId = routerParams.nodeId
def payloadBits = routerParams.user.payloadBits
}
class DebugBundle(val nIn: Int) extends Bundle {
val va_stall = Vec(nIn, UInt())
val sa_stall = Vec(nIn, UInt())
}
class Router(
val routerParams: RouterParams,
preDiplomaticInParams: Seq[ChannelParams],
preDiplomaticIngressParams: Seq[IngressChannelParams],
outDests: Seq[Int],
egressIds: Seq[Int]
)(implicit p: Parameters) extends LazyModule with HasNoCParams with HasRouterParams {
val allPreDiplomaticInParams = preDiplomaticInParams ++ preDiplomaticIngressParams
val destNodes = preDiplomaticInParams.map(u => ChannelDestNode(u))
val sourceNodes = outDests.map(u => ChannelSourceNode(u))
val ingressNodes = preDiplomaticIngressParams.map(u => IngressChannelDestNode(u))
val egressNodes = egressIds.map(u => EgressChannelSourceNode(u))
val debugNode = BundleBridgeSource(() => new DebugBundle(allPreDiplomaticInParams.size))
val ctrlNode = if (hasCtrl) Some(BundleBridgeSource(() => new RouterCtrlBundle)) else None
def inParams = module.inParams
def outParams = module.outParams
def ingressParams = module.ingressParams
def egressParams = module.egressParams
lazy val module = new LazyModuleImp(this) with HasRouterInputParams with HasRouterOutputParams {
val (io_in, edgesIn) = destNodes.map(_.in(0)).unzip
val (io_out, edgesOut) = sourceNodes.map(_.out(0)).unzip
val (io_ingress, edgesIngress) = ingressNodes.map(_.in(0)).unzip
val (io_egress, edgesEgress) = egressNodes.map(_.out(0)).unzip
val io_debug = debugNode.out(0)._1
val inParams = edgesIn.map(_.cp)
val outParams = edgesOut.map(_.cp)
val ingressParams = edgesIngress.map(_.cp)
val egressParams = edgesEgress.map(_.cp)
allOutParams.foreach(u => require(u.srcId == nodeId && u.payloadBits == routerParams.user.payloadBits))
allInParams.foreach(u => require(u.destId == nodeId && u.payloadBits == routerParams.user.payloadBits))
require(nIngress == routerParams.nIngress)
require(nEgress == routerParams.nEgress)
require(nAllInputs >= 1)
require(nAllOutputs >= 1)
require(nodeId < (1 << nodeIdBits))
val input_units = inParams.zipWithIndex.map { case (u,i) =>
Module(new InputUnit(u, outParams, egressParams,
routerParams.user.combineRCVA, routerParams.user.combineSAST))
.suggestName(s"input_unit_${i}_from_${u.srcId}") }
val ingress_units = ingressParams.zipWithIndex.map { case (u,i) =>
Module(new IngressUnit(i, u, outParams, egressParams,
routerParams.user.combineRCVA, routerParams.user.combineSAST))
.suggestName(s"ingress_unit_${i+nInputs}_from_${u.ingressId}") }
val all_input_units = input_units ++ ingress_units
val output_units = outParams.zipWithIndex.map { case (u,i) =>
Module(new OutputUnit(inParams, ingressParams, u))
.suggestName(s"output_unit_${i}_to_${u.destId}")}
val egress_units = egressParams.zipWithIndex.map { case (u,i) =>
Module(new EgressUnit(routerParams.user.coupleSAVA && all_input_units.size == 1,
routerParams.user.combineSAST,
inParams, ingressParams, u))
.suggestName(s"egress_unit_${i+nOutputs}_to_${u.egressId}")}
val all_output_units = output_units ++ egress_units
val switch = Module(new Switch(routerParams, inParams, outParams, ingressParams, egressParams))
val switch_allocator = Module(new SwitchAllocator(routerParams, inParams, outParams, ingressParams, egressParams))
val vc_allocator = Module(routerParams.user.vcAllocator(
VCAllocatorParams(routerParams, inParams, outParams, ingressParams, egressParams)
)(p))
val route_computer = Module(new RouteComputer(routerParams, inParams, outParams, ingressParams, egressParams))
val fires_count = WireInit(PopCount(vc_allocator.io.req.map(_.fire)))
dontTouch(fires_count)
(io_in zip input_units ).foreach { case (i,u) => u.io.in <> i }
(io_ingress zip ingress_units).foreach { case (i,u) => u.io.in <> i.flit }
(output_units zip io_out ).foreach { case (u,o) => o <> u.io.out }
(egress_units zip io_egress).foreach { case (u,o) => o.flit <> u.io.out }
(route_computer.io.req zip all_input_units).foreach {
case (i,u) => i <> u.io.router_req }
(all_input_units zip route_computer.io.resp).foreach {
case (u,o) => u.io.router_resp <> o }
(vc_allocator.io.req zip all_input_units).foreach {
case (i,u) => i <> u.io.vcalloc_req }
(all_input_units zip vc_allocator.io.resp).foreach {
case (u,o) => u.io.vcalloc_resp <> o }
(all_output_units zip vc_allocator.io.out_allocs).foreach {
case (u,a) => u.io.allocs <> a }
(vc_allocator.io.channel_status zip all_output_units).foreach {
case (a,u) => a := u.io.channel_status }
all_input_units.foreach(in => all_output_units.zipWithIndex.foreach { case (out,outIdx) =>
in.io.out_credit_available(outIdx) := out.io.credit_available
})
(all_input_units zip switch_allocator.io.req).foreach {
case (u,r) => r <> u.io.salloc_req }
(all_output_units zip switch_allocator.io.credit_alloc).foreach {
case (u,a) => u.io.credit_alloc := a }
(switch.io.in zip all_input_units).foreach {
case (i,u) => i <> u.io.out }
(all_output_units zip switch.io.out).foreach {
case (u,o) => u.io.in <> o }
switch.io.sel := (if (routerParams.user.combineSAST) {
switch_allocator.io.switch_sel
} else {
RegNext(switch_allocator.io.switch_sel)
})
if (hasCtrl) {
val io_ctrl = ctrlNode.get.out(0)._1
val ctrl = Module(new RouterControlUnit(routerParams, inParams, outParams, ingressParams, egressParams))
io_ctrl <> ctrl.io.ctrl
(all_input_units zip ctrl.io.in_block ).foreach { case (l,r) => l.io.block := r }
(all_input_units zip ctrl.io.in_fire ).foreach { case (l,r) => r := l.io.out.map(_.valid) }
} else {
input_units.foreach(_.io.block := false.B)
ingress_units.foreach(_.io.block := false.B)
}
(io_debug.va_stall zip all_input_units.map(_.io.debug.va_stall)).map { case (l,r) => l := r }
(io_debug.sa_stall zip all_input_units.map(_.io.debug.sa_stall)).map { case (l,r) => l := r }
val debug_tsc = RegInit(0.U(64.W))
debug_tsc := debug_tsc + 1.U
val debug_sample = RegInit(0.U(64.W))
debug_sample := debug_sample + 1.U
val sample_rate = PlusArg("noc_util_sample_rate", width=20)
when (debug_sample === sample_rate - 1.U) { debug_sample := 0.U }
def sample(fire: Bool, s: String) = {
val util_ctr = RegInit(0.U(64.W))
val fired = RegInit(false.B)
util_ctr := util_ctr + fire
fired := fired || fire
when (sample_rate =/= 0.U && debug_sample === sample_rate - 1.U && fired) {
val fmtStr = s"nocsample %d $s %d\n"
printf(fmtStr, debug_tsc, util_ctr);
fired := fire
}
}
destNodes.map(_.in(0)).foreach { case (in, edge) => in.flit.map { f =>
sample(f.fire, s"${edge.cp.srcId} $nodeId")
} }
ingressNodes.map(_.in(0)).foreach { case (in, edge) =>
sample(in.flit.fire, s"i${edge.cp.asInstanceOf[IngressChannelParams].ingressId} $nodeId")
}
egressNodes.map(_.out(0)).foreach { case (out, edge) =>
sample(out.flit.fire, s"$nodeId e${edge.cp.asInstanceOf[EgressChannelParams].egressId}")
}
}
}
File LazyModuleImp.scala:
package org.chipsalliance.diplomacy.lazymodule
import chisel3.{withClockAndReset, Module, RawModule, Reset, _}
import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo}
import firrtl.passes.InlineAnnotation
import org.chipsalliance.cde.config.Parameters
import org.chipsalliance.diplomacy.nodes.Dangle
import scala.collection.immutable.SortedMap
/** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]].
*
* This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy.
*/
sealed trait LazyModuleImpLike extends RawModule {
/** [[LazyModule]] that contains this instance. */
val wrapper: LazyModule
/** IOs that will be automatically "punched" for this instance. */
val auto: AutoBundle
/** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */
protected[diplomacy] val dangles: Seq[Dangle]
// [[wrapper.module]] had better not be accessed while LazyModules are still being built!
require(
LazyModule.scope.isEmpty,
s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}"
)
/** Set module name. Defaults to the containing LazyModule's desiredName. */
override def desiredName: String = wrapper.desiredName
suggestName(wrapper.suggestedName)
/** [[Parameters]] for chisel [[Module]]s. */
implicit val p: Parameters = wrapper.p
/** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and
* submodules.
*/
protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = {
// 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]],
// 2. return [[Dangle]]s from each module.
val childDangles = wrapper.children.reverse.flatMap { c =>
implicit val sourceInfo: SourceInfo = c.info
c.cloneProto.map { cp =>
// If the child is a clone, then recursively set cloneProto of its children as well
def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = {
require(bases.size == clones.size)
(bases.zip(clones)).map { case (l, r) =>
require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}")
l.cloneProto = Some(r)
assignCloneProtos(l.children, r.children)
}
}
assignCloneProtos(c.children, cp.children)
// Clone the child module as a record, and get its [[AutoBundle]]
val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName)
val clonedAuto = clone("auto").asInstanceOf[AutoBundle]
// Get the empty [[Dangle]]'s of the cloned child
val rawDangles = c.cloneDangles()
require(rawDangles.size == clonedAuto.elements.size)
// Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s
val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) }
dangles
}.getOrElse {
// For non-clones, instantiate the child module
val mod = try {
Module(c.module)
} catch {
case e: ChiselException => {
println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}")
throw e
}
}
mod.dangles
}
}
// Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]].
// This will result in a sequence of [[Dangle]] from these [[BaseNode]]s.
val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate())
// Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]]
val allDangles = nodeDangles ++ childDangles
// Group [[allDangles]] by their [[source]].
val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*)
// For each [[source]] set of [[Dangle]]s of size 2, ensure that these
// can be connected as a source-sink pair (have opposite flipped value).
// Make the connection and mark them as [[done]].
val done = Set() ++ pairing.values.filter(_.size == 2).map {
case Seq(a, b) =>
require(a.flipped != b.flipped)
// @todo <> in chisel3 makes directionless connection.
if (a.flipped) {
a.data <> b.data
} else {
b.data <> a.data
}
a.source
case _ => None
}
// Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module.
val forward = allDangles.filter(d => !done(d.source))
// Generate [[AutoBundle]] IO from [[forward]].
val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*))
// Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]]
val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) =>
if (d.flipped) {
d.data <> io
} else {
io <> d.data
}
d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name)
}
// Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]].
wrapper.inModuleBody.reverse.foreach {
_()
}
if (wrapper.shouldBeInlined) {
chisel3.experimental.annotate(new ChiselAnnotation {
def toFirrtl = InlineAnnotation(toNamed)
})
}
// Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]].
(auto, dangles)
}
}
/** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike {
/** Instantiate hardware of this `Module`. */
val (auto, dangles) = instantiate()
}
/** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike {
// These wires are the default clock+reset for all LazyModule children.
// It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the
// [[LazyRawModuleImp]] children.
// Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly.
/** drive clock explicitly. */
val childClock: Clock = Wire(Clock())
/** drive reset explicitly. */
val childReset: Reset = Wire(Reset())
// the default is that these are disabled
childClock := false.B.asClock
childReset := chisel3.DontCare
def provideImplicitClockToLazyChildren: Boolean = false
val (auto, dangles) =
if (provideImplicitClockToLazyChildren) {
withClockAndReset(childClock, childReset) { instantiate() }
} else {
instantiate()
}
}
| module Router_6( // @[Router.scala:89:25]
input clock, // @[Router.scala:89:25]
input reset, // @[Router.scala:89:25]
output [2:0] auto_debug_out_va_stall_0, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_debug_out_va_stall_1, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_debug_out_va_stall_2, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_debug_out_sa_stall_0, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_debug_out_sa_stall_1, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_debug_out_sa_stall_2, // @[LazyModuleImp.scala:107:25]
output auto_egress_nodes_out_2_flit_valid, // @[LazyModuleImp.scala:107:25]
output auto_egress_nodes_out_2_flit_bits_head, // @[LazyModuleImp.scala:107:25]
output auto_egress_nodes_out_2_flit_bits_tail, // @[LazyModuleImp.scala:107:25]
output [72:0] auto_egress_nodes_out_2_flit_bits_payload, // @[LazyModuleImp.scala:107:25]
input auto_egress_nodes_out_1_flit_ready, // @[LazyModuleImp.scala:107:25]
output auto_egress_nodes_out_1_flit_valid, // @[LazyModuleImp.scala:107:25]
output auto_egress_nodes_out_1_flit_bits_head, // @[LazyModuleImp.scala:107:25]
output auto_egress_nodes_out_1_flit_bits_tail, // @[LazyModuleImp.scala:107:25]
output [72:0] auto_egress_nodes_out_1_flit_bits_payload, // @[LazyModuleImp.scala:107:25]
input auto_egress_nodes_out_0_flit_ready, // @[LazyModuleImp.scala:107:25]
output auto_egress_nodes_out_0_flit_valid, // @[LazyModuleImp.scala:107:25]
output auto_egress_nodes_out_0_flit_bits_head, // @[LazyModuleImp.scala:107:25]
output auto_egress_nodes_out_0_flit_bits_tail, // @[LazyModuleImp.scala:107:25]
output [72:0] auto_egress_nodes_out_0_flit_bits_payload, // @[LazyModuleImp.scala:107:25]
output auto_ingress_nodes_in_1_flit_ready, // @[LazyModuleImp.scala:107:25]
input auto_ingress_nodes_in_1_flit_valid, // @[LazyModuleImp.scala:107:25]
input auto_ingress_nodes_in_1_flit_bits_head, // @[LazyModuleImp.scala:107:25]
input auto_ingress_nodes_in_1_flit_bits_tail, // @[LazyModuleImp.scala:107:25]
input [72:0] auto_ingress_nodes_in_1_flit_bits_payload, // @[LazyModuleImp.scala:107:25]
input [4:0] auto_ingress_nodes_in_1_flit_bits_egress_id, // @[LazyModuleImp.scala:107:25]
output auto_ingress_nodes_in_0_flit_ready, // @[LazyModuleImp.scala:107:25]
input auto_ingress_nodes_in_0_flit_valid, // @[LazyModuleImp.scala:107:25]
input auto_ingress_nodes_in_0_flit_bits_head, // @[LazyModuleImp.scala:107:25]
input auto_ingress_nodes_in_0_flit_bits_tail, // @[LazyModuleImp.scala:107:25]
input [72:0] auto_ingress_nodes_in_0_flit_bits_payload, // @[LazyModuleImp.scala:107:25]
input [4:0] auto_ingress_nodes_in_0_flit_bits_egress_id, // @[LazyModuleImp.scala:107:25]
output auto_source_nodes_out_flit_0_valid, // @[LazyModuleImp.scala:107:25]
output auto_source_nodes_out_flit_0_bits_head, // @[LazyModuleImp.scala:107:25]
output auto_source_nodes_out_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25]
output [72:0] auto_source_nodes_out_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_source_nodes_out_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25]
output [4:0] auto_source_nodes_out_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_source_nodes_out_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25]
output [4:0] auto_source_nodes_out_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_source_nodes_out_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_source_nodes_out_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_source_nodes_out_credit_return, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_source_nodes_out_vc_free, // @[LazyModuleImp.scala:107:25]
input auto_dest_nodes_in_flit_0_valid, // @[LazyModuleImp.scala:107:25]
input auto_dest_nodes_in_flit_0_bits_head, // @[LazyModuleImp.scala:107:25]
input auto_dest_nodes_in_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25]
input [72:0] auto_dest_nodes_in_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_dest_nodes_in_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25]
input [4:0] auto_dest_nodes_in_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_dest_nodes_in_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25]
input [4:0] auto_dest_nodes_in_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_dest_nodes_in_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_dest_nodes_in_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_dest_nodes_in_credit_return, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_dest_nodes_in_vc_free // @[LazyModuleImp.scala:107:25]
);
wire [19:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire _vc_allocator_io_req_2_ready; // @[Router.scala:133:30]
wire _vc_allocator_io_req_1_ready; // @[Router.scala:133:30]
wire _vc_allocator_io_req_0_ready; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_2_vc_sel_3_0; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_2_vc_sel_2_0; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_2_vc_sel_1_0; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_2_vc_sel_0_0; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_2_vc_sel_0_1; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_2_vc_sel_0_2; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_2_vc_sel_0_3; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_2_vc_sel_0_4; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_2_vc_sel_0_5; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_2_vc_sel_0_6; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_2_vc_sel_0_7; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_1_vc_sel_3_0; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_1_vc_sel_2_0; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_1_vc_sel_1_0; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_1_vc_sel_0_0; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_1_vc_sel_0_1; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_1_vc_sel_0_2; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_1_vc_sel_0_3; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_1_vc_sel_0_4; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_1_vc_sel_0_5; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_1_vc_sel_0_6; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_1_vc_sel_0_7; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_0_vc_sel_3_0; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_0_vc_sel_2_0; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_0_vc_sel_1_0; // @[Router.scala:133:30]
wire _vc_allocator_io_out_allocs_3_0_alloc; // @[Router.scala:133:30]
wire _vc_allocator_io_out_allocs_2_0_alloc; // @[Router.scala:133:30]
wire _vc_allocator_io_out_allocs_1_0_alloc; // @[Router.scala:133:30]
wire _vc_allocator_io_out_allocs_0_1_alloc; // @[Router.scala:133:30]
wire _vc_allocator_io_out_allocs_0_2_alloc; // @[Router.scala:133:30]
wire _vc_allocator_io_out_allocs_0_3_alloc; // @[Router.scala:133:30]
wire _vc_allocator_io_out_allocs_0_4_alloc; // @[Router.scala:133:30]
wire _vc_allocator_io_out_allocs_0_5_alloc; // @[Router.scala:133:30]
wire _vc_allocator_io_out_allocs_0_6_alloc; // @[Router.scala:133:30]
wire _vc_allocator_io_out_allocs_0_7_alloc; // @[Router.scala:133:30]
wire _switch_allocator_io_req_2_0_ready; // @[Router.scala:132:34]
wire _switch_allocator_io_req_1_0_ready; // @[Router.scala:132:34]
wire _switch_allocator_io_req_0_0_ready; // @[Router.scala:132:34]
wire _switch_allocator_io_credit_alloc_3_0_alloc; // @[Router.scala:132:34]
wire _switch_allocator_io_credit_alloc_3_0_tail; // @[Router.scala:132:34]
wire _switch_allocator_io_credit_alloc_2_0_alloc; // @[Router.scala:132:34]
wire _switch_allocator_io_credit_alloc_2_0_tail; // @[Router.scala:132:34]
wire _switch_allocator_io_credit_alloc_1_0_alloc; // @[Router.scala:132:34]
wire _switch_allocator_io_credit_alloc_1_0_tail; // @[Router.scala:132:34]
wire _switch_allocator_io_credit_alloc_0_1_alloc; // @[Router.scala:132:34]
wire _switch_allocator_io_credit_alloc_0_2_alloc; // @[Router.scala:132:34]
wire _switch_allocator_io_credit_alloc_0_3_alloc; // @[Router.scala:132:34]
wire _switch_allocator_io_credit_alloc_0_4_alloc; // @[Router.scala:132:34]
wire _switch_allocator_io_credit_alloc_0_5_alloc; // @[Router.scala:132:34]
wire _switch_allocator_io_credit_alloc_0_6_alloc; // @[Router.scala:132:34]
wire _switch_allocator_io_credit_alloc_0_7_alloc; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_3_0_2_0; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_3_0_1_0; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_3_0_0_0; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_2_0_2_0; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_2_0_1_0; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_2_0_0_0; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_1_0_2_0; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_1_0_1_0; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_1_0_0_0; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_0_0_2_0; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_0_0_1_0; // @[Router.scala:132:34]
wire _switch_io_out_3_0_valid; // @[Router.scala:131:24]
wire _switch_io_out_3_0_bits_head; // @[Router.scala:131:24]
wire _switch_io_out_3_0_bits_tail; // @[Router.scala:131:24]
wire [72:0] _switch_io_out_3_0_bits_payload; // @[Router.scala:131:24]
wire [4:0] _switch_io_out_3_0_bits_flow_ingress_node; // @[Router.scala:131:24]
wire [1:0] _switch_io_out_3_0_bits_flow_ingress_node_id; // @[Router.scala:131:24]
wire _switch_io_out_2_0_valid; // @[Router.scala:131:24]
wire _switch_io_out_2_0_bits_head; // @[Router.scala:131:24]
wire _switch_io_out_2_0_bits_tail; // @[Router.scala:131:24]
wire [72:0] _switch_io_out_2_0_bits_payload; // @[Router.scala:131:24]
wire [4:0] _switch_io_out_2_0_bits_flow_ingress_node; // @[Router.scala:131:24]
wire [1:0] _switch_io_out_2_0_bits_flow_ingress_node_id; // @[Router.scala:131:24]
wire _switch_io_out_1_0_valid; // @[Router.scala:131:24]
wire _switch_io_out_1_0_bits_head; // @[Router.scala:131:24]
wire _switch_io_out_1_0_bits_tail; // @[Router.scala:131:24]
wire [72:0] _switch_io_out_1_0_bits_payload; // @[Router.scala:131:24]
wire [4:0] _switch_io_out_1_0_bits_flow_ingress_node; // @[Router.scala:131:24]
wire [1:0] _switch_io_out_1_0_bits_flow_ingress_node_id; // @[Router.scala:131:24]
wire _switch_io_out_0_0_valid; // @[Router.scala:131:24]
wire _switch_io_out_0_0_bits_head; // @[Router.scala:131:24]
wire _switch_io_out_0_0_bits_tail; // @[Router.scala:131:24]
wire [72:0] _switch_io_out_0_0_bits_payload; // @[Router.scala:131:24]
wire [2:0] _switch_io_out_0_0_bits_flow_vnet_id; // @[Router.scala:131:24]
wire [4:0] _switch_io_out_0_0_bits_flow_ingress_node; // @[Router.scala:131:24]
wire [1:0] _switch_io_out_0_0_bits_flow_ingress_node_id; // @[Router.scala:131:24]
wire [4:0] _switch_io_out_0_0_bits_flow_egress_node; // @[Router.scala:131:24]
wire [1:0] _switch_io_out_0_0_bits_flow_egress_node_id; // @[Router.scala:131:24]
wire [2:0] _switch_io_out_0_0_bits_virt_channel_id; // @[Router.scala:131:24]
wire _egress_unit_3_to_26_io_credit_available_0; // @[Router.scala:125:13]
wire _egress_unit_3_to_26_io_channel_status_0_occupied; // @[Router.scala:125:13]
wire _egress_unit_3_to_26_io_out_valid; // @[Router.scala:125:13]
wire _egress_unit_2_to_25_io_credit_available_0; // @[Router.scala:125:13]
wire _egress_unit_2_to_25_io_channel_status_0_occupied; // @[Router.scala:125:13]
wire _egress_unit_2_to_25_io_out_valid; // @[Router.scala:125:13]
wire _egress_unit_1_to_24_io_credit_available_0; // @[Router.scala:125:13]
wire _egress_unit_1_to_24_io_channel_status_0_occupied; // @[Router.scala:125:13]
wire _egress_unit_1_to_24_io_out_valid; // @[Router.scala:125:13]
wire _output_unit_0_to_22_io_credit_available_1; // @[Router.scala:122:13]
wire _output_unit_0_to_22_io_credit_available_2; // @[Router.scala:122:13]
wire _output_unit_0_to_22_io_credit_available_3; // @[Router.scala:122:13]
wire _output_unit_0_to_22_io_credit_available_4; // @[Router.scala:122:13]
wire _output_unit_0_to_22_io_credit_available_5; // @[Router.scala:122:13]
wire _output_unit_0_to_22_io_credit_available_6; // @[Router.scala:122:13]
wire _output_unit_0_to_22_io_credit_available_7; // @[Router.scala:122:13]
wire _output_unit_0_to_22_io_channel_status_1_occupied; // @[Router.scala:122:13]
wire _output_unit_0_to_22_io_channel_status_2_occupied; // @[Router.scala:122:13]
wire _output_unit_0_to_22_io_channel_status_3_occupied; // @[Router.scala:122:13]
wire _output_unit_0_to_22_io_channel_status_4_occupied; // @[Router.scala:122:13]
wire _output_unit_0_to_22_io_channel_status_5_occupied; // @[Router.scala:122:13]
wire _output_unit_0_to_22_io_channel_status_6_occupied; // @[Router.scala:122:13]
wire _output_unit_0_to_22_io_channel_status_7_occupied; // @[Router.scala:122:13]
wire _ingress_unit_2_from_32_io_vcalloc_req_valid; // @[Router.scala:116:13]
wire _ingress_unit_2_from_32_io_vcalloc_req_bits_vc_sel_3_0; // @[Router.scala:116:13]
wire _ingress_unit_2_from_32_io_vcalloc_req_bits_vc_sel_2_0; // @[Router.scala:116:13]
wire _ingress_unit_2_from_32_io_vcalloc_req_bits_vc_sel_1_0; // @[Router.scala:116:13]
wire _ingress_unit_2_from_32_io_vcalloc_req_bits_vc_sel_0_0; // @[Router.scala:116:13]
wire _ingress_unit_2_from_32_io_vcalloc_req_bits_vc_sel_0_1; // @[Router.scala:116:13]
wire _ingress_unit_2_from_32_io_vcalloc_req_bits_vc_sel_0_2; // @[Router.scala:116:13]
wire _ingress_unit_2_from_32_io_vcalloc_req_bits_vc_sel_0_3; // @[Router.scala:116:13]
wire _ingress_unit_2_from_32_io_vcalloc_req_bits_vc_sel_0_4; // @[Router.scala:116:13]
wire _ingress_unit_2_from_32_io_vcalloc_req_bits_vc_sel_0_5; // @[Router.scala:116:13]
wire _ingress_unit_2_from_32_io_vcalloc_req_bits_vc_sel_0_6; // @[Router.scala:116:13]
wire _ingress_unit_2_from_32_io_vcalloc_req_bits_vc_sel_0_7; // @[Router.scala:116:13]
wire _ingress_unit_2_from_32_io_salloc_req_0_valid; // @[Router.scala:116:13]
wire _ingress_unit_2_from_32_io_salloc_req_0_bits_vc_sel_3_0; // @[Router.scala:116:13]
wire _ingress_unit_2_from_32_io_salloc_req_0_bits_vc_sel_2_0; // @[Router.scala:116:13]
wire _ingress_unit_2_from_32_io_salloc_req_0_bits_vc_sel_1_0; // @[Router.scala:116:13]
wire _ingress_unit_2_from_32_io_salloc_req_0_bits_vc_sel_0_0; // @[Router.scala:116:13]
wire _ingress_unit_2_from_32_io_salloc_req_0_bits_vc_sel_0_1; // @[Router.scala:116:13]
wire _ingress_unit_2_from_32_io_salloc_req_0_bits_vc_sel_0_2; // @[Router.scala:116:13]
wire _ingress_unit_2_from_32_io_salloc_req_0_bits_vc_sel_0_3; // @[Router.scala:116:13]
wire _ingress_unit_2_from_32_io_salloc_req_0_bits_vc_sel_0_4; // @[Router.scala:116:13]
wire _ingress_unit_2_from_32_io_salloc_req_0_bits_vc_sel_0_5; // @[Router.scala:116:13]
wire _ingress_unit_2_from_32_io_salloc_req_0_bits_vc_sel_0_6; // @[Router.scala:116:13]
wire _ingress_unit_2_from_32_io_salloc_req_0_bits_vc_sel_0_7; // @[Router.scala:116:13]
wire _ingress_unit_2_from_32_io_salloc_req_0_bits_tail; // @[Router.scala:116:13]
wire _ingress_unit_2_from_32_io_out_0_valid; // @[Router.scala:116:13]
wire _ingress_unit_2_from_32_io_out_0_bits_flit_head; // @[Router.scala:116:13]
wire _ingress_unit_2_from_32_io_out_0_bits_flit_tail; // @[Router.scala:116:13]
wire [72:0] _ingress_unit_2_from_32_io_out_0_bits_flit_payload; // @[Router.scala:116:13]
wire [2:0] _ingress_unit_2_from_32_io_out_0_bits_flit_flow_vnet_id; // @[Router.scala:116:13]
wire [4:0] _ingress_unit_2_from_32_io_out_0_bits_flit_flow_ingress_node; // @[Router.scala:116:13]
wire [1:0] _ingress_unit_2_from_32_io_out_0_bits_flit_flow_ingress_node_id; // @[Router.scala:116:13]
wire [4:0] _ingress_unit_2_from_32_io_out_0_bits_flit_flow_egress_node; // @[Router.scala:116:13]
wire [1:0] _ingress_unit_2_from_32_io_out_0_bits_flit_flow_egress_node_id; // @[Router.scala:116:13]
wire [2:0] _ingress_unit_2_from_32_io_out_0_bits_out_virt_channel; // @[Router.scala:116:13]
wire _ingress_unit_2_from_32_io_in_ready; // @[Router.scala:116:13]
wire _ingress_unit_1_from_31_io_vcalloc_req_valid; // @[Router.scala:116:13]
wire _ingress_unit_1_from_31_io_vcalloc_req_bits_vc_sel_3_0; // @[Router.scala:116:13]
wire _ingress_unit_1_from_31_io_vcalloc_req_bits_vc_sel_2_0; // @[Router.scala:116:13]
wire _ingress_unit_1_from_31_io_vcalloc_req_bits_vc_sel_1_0; // @[Router.scala:116:13]
wire _ingress_unit_1_from_31_io_vcalloc_req_bits_vc_sel_0_0; // @[Router.scala:116:13]
wire _ingress_unit_1_from_31_io_vcalloc_req_bits_vc_sel_0_1; // @[Router.scala:116:13]
wire _ingress_unit_1_from_31_io_vcalloc_req_bits_vc_sel_0_2; // @[Router.scala:116:13]
wire _ingress_unit_1_from_31_io_vcalloc_req_bits_vc_sel_0_3; // @[Router.scala:116:13]
wire _ingress_unit_1_from_31_io_vcalloc_req_bits_vc_sel_0_4; // @[Router.scala:116:13]
wire _ingress_unit_1_from_31_io_vcalloc_req_bits_vc_sel_0_5; // @[Router.scala:116:13]
wire _ingress_unit_1_from_31_io_vcalloc_req_bits_vc_sel_0_6; // @[Router.scala:116:13]
wire _ingress_unit_1_from_31_io_vcalloc_req_bits_vc_sel_0_7; // @[Router.scala:116:13]
wire _ingress_unit_1_from_31_io_salloc_req_0_valid; // @[Router.scala:116:13]
wire _ingress_unit_1_from_31_io_salloc_req_0_bits_vc_sel_3_0; // @[Router.scala:116:13]
wire _ingress_unit_1_from_31_io_salloc_req_0_bits_vc_sel_2_0; // @[Router.scala:116:13]
wire _ingress_unit_1_from_31_io_salloc_req_0_bits_vc_sel_1_0; // @[Router.scala:116:13]
wire _ingress_unit_1_from_31_io_salloc_req_0_bits_vc_sel_0_0; // @[Router.scala:116:13]
wire _ingress_unit_1_from_31_io_salloc_req_0_bits_vc_sel_0_1; // @[Router.scala:116:13]
wire _ingress_unit_1_from_31_io_salloc_req_0_bits_vc_sel_0_2; // @[Router.scala:116:13]
wire _ingress_unit_1_from_31_io_salloc_req_0_bits_vc_sel_0_3; // @[Router.scala:116:13]
wire _ingress_unit_1_from_31_io_salloc_req_0_bits_vc_sel_0_4; // @[Router.scala:116:13]
wire _ingress_unit_1_from_31_io_salloc_req_0_bits_vc_sel_0_5; // @[Router.scala:116:13]
wire _ingress_unit_1_from_31_io_salloc_req_0_bits_vc_sel_0_6; // @[Router.scala:116:13]
wire _ingress_unit_1_from_31_io_salloc_req_0_bits_vc_sel_0_7; // @[Router.scala:116:13]
wire _ingress_unit_1_from_31_io_salloc_req_0_bits_tail; // @[Router.scala:116:13]
wire _ingress_unit_1_from_31_io_out_0_valid; // @[Router.scala:116:13]
wire _ingress_unit_1_from_31_io_out_0_bits_flit_head; // @[Router.scala:116:13]
wire _ingress_unit_1_from_31_io_out_0_bits_flit_tail; // @[Router.scala:116:13]
wire [72:0] _ingress_unit_1_from_31_io_out_0_bits_flit_payload; // @[Router.scala:116:13]
wire [2:0] _ingress_unit_1_from_31_io_out_0_bits_flit_flow_vnet_id; // @[Router.scala:116:13]
wire [4:0] _ingress_unit_1_from_31_io_out_0_bits_flit_flow_ingress_node; // @[Router.scala:116:13]
wire [1:0] _ingress_unit_1_from_31_io_out_0_bits_flit_flow_ingress_node_id; // @[Router.scala:116:13]
wire [4:0] _ingress_unit_1_from_31_io_out_0_bits_flit_flow_egress_node; // @[Router.scala:116:13]
wire [1:0] _ingress_unit_1_from_31_io_out_0_bits_flit_flow_egress_node_id; // @[Router.scala:116:13]
wire [2:0] _ingress_unit_1_from_31_io_out_0_bits_out_virt_channel; // @[Router.scala:116:13]
wire _ingress_unit_1_from_31_io_in_ready; // @[Router.scala:116:13]
wire _input_unit_0_from_22_io_vcalloc_req_valid; // @[Router.scala:112:13]
wire _input_unit_0_from_22_io_vcalloc_req_bits_vc_sel_3_0; // @[Router.scala:112:13]
wire _input_unit_0_from_22_io_vcalloc_req_bits_vc_sel_2_0; // @[Router.scala:112:13]
wire _input_unit_0_from_22_io_vcalloc_req_bits_vc_sel_1_0; // @[Router.scala:112:13]
wire _input_unit_0_from_22_io_salloc_req_0_valid; // @[Router.scala:112:13]
wire _input_unit_0_from_22_io_salloc_req_0_bits_vc_sel_3_0; // @[Router.scala:112:13]
wire _input_unit_0_from_22_io_salloc_req_0_bits_vc_sel_2_0; // @[Router.scala:112:13]
wire _input_unit_0_from_22_io_salloc_req_0_bits_vc_sel_1_0; // @[Router.scala:112:13]
wire _input_unit_0_from_22_io_salloc_req_0_bits_tail; // @[Router.scala:112:13]
wire _input_unit_0_from_22_io_out_0_valid; // @[Router.scala:112:13]
wire _input_unit_0_from_22_io_out_0_bits_flit_head; // @[Router.scala:112:13]
wire _input_unit_0_from_22_io_out_0_bits_flit_tail; // @[Router.scala:112:13]
wire [72:0] _input_unit_0_from_22_io_out_0_bits_flit_payload; // @[Router.scala:112:13]
wire [2:0] _input_unit_0_from_22_io_out_0_bits_flit_flow_vnet_id; // @[Router.scala:112:13]
wire [4:0] _input_unit_0_from_22_io_out_0_bits_flit_flow_ingress_node; // @[Router.scala:112:13]
wire [1:0] _input_unit_0_from_22_io_out_0_bits_flit_flow_ingress_node_id; // @[Router.scala:112:13]
wire [4:0] _input_unit_0_from_22_io_out_0_bits_flit_flow_egress_node; // @[Router.scala:112:13]
wire [1:0] _input_unit_0_from_22_io_out_0_bits_flit_flow_egress_node_id; // @[Router.scala:112:13]
wire [1:0] fires_count = {1'h0, _vc_allocator_io_req_0_ready & _input_unit_0_from_22_io_vcalloc_req_valid} + {1'h0, _vc_allocator_io_req_1_ready & _ingress_unit_1_from_31_io_vcalloc_req_valid} + {1'h0, _vc_allocator_io_req_2_ready & _ingress_unit_2_from_32_io_vcalloc_req_valid}; // @[Decoupled.scala:51:35]
reg REG_3_0_2_0; // @[Router.scala:178:14]
reg REG_3_0_1_0; // @[Router.scala:178:14]
reg REG_3_0_0_0; // @[Router.scala:178:14]
reg REG_2_0_2_0; // @[Router.scala:178:14]
reg REG_2_0_1_0; // @[Router.scala:178:14]
reg REG_2_0_0_0; // @[Router.scala:178:14]
reg REG_1_0_2_0; // @[Router.scala:178:14]
reg REG_1_0_1_0; // @[Router.scala:178:14]
reg REG_1_0_0_0; // @[Router.scala:178:14]
reg REG_0_0_2_0; // @[Router.scala:178:14]
reg REG_0_0_1_0; // @[Router.scala:178:14]
reg [63:0] debug_tsc; // @[Router.scala:195:28]
reg [63:0] debug_sample; // @[Router.scala:197:31]
wire _GEN = debug_sample == {44'h0, _plusarg_reader_out - 20'h1}; // @[PlusArg.scala:80:11]
reg [63:0] util_ctr; // @[Router.scala:203:29]
reg fired; // @[Router.scala:204:26]
wire _GEN_0 = (|_plusarg_reader_out) & _GEN; // @[PlusArg.scala:80:11]
wire _GEN_1 = _GEN_0 & fired; // @[Router.scala:204:26, :207:{33,71}]
reg [63:0] util_ctr_1; // @[Router.scala:203:29]
reg fired_1; // @[Router.scala:204:26]
wire _GEN_2 = _GEN_0 & fired_1; // @[Router.scala:204:26, :207:{33,71}]
reg [63:0] util_ctr_2; // @[Router.scala:203:29]
reg fired_2; // @[Router.scala:204:26]
wire _GEN_3 = _GEN_0 & fired_2; // @[Router.scala:204:26, :207:{33,71}]
reg [63:0] util_ctr_3; // @[Router.scala:203:29]
reg fired_3; // @[Router.scala:204:26]
wire _GEN_4 = _GEN_0 & fired_3; // @[Router.scala:204:26, :207:{33,71}]
reg [63:0] util_ctr_4; // @[Router.scala:203:29]
reg fired_4; // @[Router.scala:204:26]
wire _GEN_5 = _GEN_0 & fired_4; // @[Router.scala:204:26, :207:{33,71}]
reg [63:0] util_ctr_5; // @[Router.scala:203:29]
reg fired_5; // @[Router.scala:204:26]
wire _GEN_6 = _GEN_0 & fired_5; // @[Router.scala:204:26, :207:{33,71}] |
Generate the Verilog code corresponding to the following Chisel files.
File Tilelink.scala:
package constellation.protocol
import chisel3._
import chisel3.util._
import constellation.channel._
import constellation.noc._
import constellation.soc.{CanAttachToGlobalNoC}
import org.chipsalliance.cde.config._
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.util._
import freechips.rocketchip.tilelink._
import scala.collection.immutable.{ListMap}
trait TLFieldHelper {
def getBodyFields(b: TLChannel): Seq[Data] = b match {
case b: TLBundleA => Seq(b.mask, b.data, b.corrupt)
case b: TLBundleB => Seq(b.mask, b.data, b.corrupt)
case b: TLBundleC => Seq( b.data, b.corrupt)
case b: TLBundleD => Seq( b.data, b.corrupt)
case b: TLBundleE => Seq()
}
def getConstFields(b: TLChannel): Seq[Data] = b match {
case b: TLBundleA => Seq(b.opcode, b.param, b.size, b.source, b.address, b.user, b.echo )
case b: TLBundleB => Seq(b.opcode, b.param, b.size, b.source, b.address )
case b: TLBundleC => Seq(b.opcode, b.param, b.size, b.source, b.address, b.user, b.echo )
case b: TLBundleD => Seq(b.opcode, b.param, b.size, b.source, b.user, b.echo, b.sink, b.denied)
case b: TLBundleE => Seq( b.sink )
}
def minTLPayloadWidth(b: TLChannel): Int = Seq(getBodyFields(b), getConstFields(b)).map(_.map(_.getWidth).sum).max
def minTLPayloadWidth(bs: Seq[TLChannel]): Int = bs.map(b => minTLPayloadWidth(b)).max
def minTLPayloadWidth(b: TLBundle): Int = minTLPayloadWidth(Seq(b.a, b.b, b.c, b.d, b.e).map(_.bits))
}
class TLMasterToNoC(
edgeIn: TLEdge, edgesOut: Seq[TLEdge],
sourceStart: Int, sourceSize: Int,
wideBundle: TLBundleParameters,
slaveToEgressOffset: Int => Int,
flitWidth: Int
)(implicit p: Parameters) extends Module {
val io = IO(new Bundle {
val tilelink = Flipped(new TLBundle(wideBundle))
val flits = new Bundle {
val a = Decoupled(new IngressFlit(flitWidth))
val b = Flipped(Decoupled(new EgressFlit(flitWidth)))
val c = Decoupled(new IngressFlit(flitWidth))
val d = Flipped(Decoupled(new EgressFlit(flitWidth)))
val e = Decoupled(new IngressFlit(flitWidth))
}
})
val a = Module(new TLAToNoC(edgeIn, edgesOut, wideBundle, (i) => slaveToEgressOffset(i) + 0, sourceStart))
val b = Module(new TLBFromNoC(edgeIn, wideBundle, sourceSize))
val c = Module(new TLCToNoC(edgeIn, edgesOut, wideBundle, (i) => slaveToEgressOffset(i) + 1, sourceStart))
val d = Module(new TLDFromNoC(edgeIn, wideBundle, sourceSize))
val e = Module(new TLEToNoC(edgeIn, edgesOut, wideBundle, (i) => slaveToEgressOffset(i) + 2))
a.io.protocol <> io.tilelink.a
io.tilelink.b <> b.io.protocol
c.io.protocol <> io.tilelink.c
io.tilelink.d <> d.io.protocol
e.io.protocol <> io.tilelink.e
io.flits.a <> a.io.flit
b.io.flit <> io.flits.b
io.flits.c <> c.io.flit
d.io.flit <> io.flits.d
io.flits.e <> e.io.flit
}
class TLMasterACDToNoC(
edgeIn: TLEdge, edgesOut: Seq[TLEdge],
sourceStart: Int, sourceSize: Int,
wideBundle: TLBundleParameters,
slaveToEgressOffset: Int => Int,
flitWidth: Int
)(implicit p: Parameters) extends Module {
val io = IO(new Bundle {
val tilelink = Flipped(new TLBundle(wideBundle))
val flits = new Bundle {
val a = Decoupled(new IngressFlit(flitWidth))
val c = Decoupled(new IngressFlit(flitWidth))
val d = Flipped(Decoupled(new EgressFlit(flitWidth)))
}
})
io.tilelink := DontCare
val a = Module(new TLAToNoC(edgeIn, edgesOut, wideBundle, (i) => slaveToEgressOffset(i) + 0, sourceStart))
val c = Module(new TLCToNoC(edgeIn, edgesOut, wideBundle, (i) => slaveToEgressOffset(i) + 1, sourceStart))
val d = Module(new TLDFromNoC(edgeIn, wideBundle, sourceSize))
a.io.protocol <> io.tilelink.a
c.io.protocol <> io.tilelink.c
io.tilelink.d <> d.io.protocol
io.flits.a <> a.io.flit
io.flits.c <> c.io.flit
d.io.flit <> io.flits.d
}
class TLMasterBEToNoC(
edgeIn: TLEdge, edgesOut: Seq[TLEdge],
sourceStart: Int, sourceSize: Int,
wideBundle: TLBundleParameters,
slaveToEgressOffset: Int => Int,
flitWidth: Int
)(implicit p: Parameters) extends Module {
val io = IO(new Bundle {
val tilelink = Flipped(new TLBundle(wideBundle))
val flits = new Bundle {
val b = Flipped(Decoupled(new EgressFlit(flitWidth)))
val e = Decoupled(new IngressFlit(flitWidth))
}
})
io.tilelink := DontCare
val b = Module(new TLBFromNoC(edgeIn, wideBundle, sourceSize))
val e = Module(new TLEToNoC(edgeIn, edgesOut, wideBundle, (i) => slaveToEgressOffset(i) + 0))
io.tilelink.b <> b.io.protocol
e.io.protocol <> io.tilelink.e
b.io.flit <> io.flits.b
io.flits.e <> e.io.flit
}
class TLSlaveToNoC(
edgeOut: TLEdge, edgesIn: Seq[TLEdge],
sourceStart: Int, sourceSize: Int,
wideBundle: TLBundleParameters,
masterToEgressOffset: Int => Int,
flitWidth: Int
)(implicit p: Parameters) extends Module {
val io = IO(new Bundle {
val tilelink = new TLBundle(wideBundle)
val flits = new Bundle {
val a = Flipped(Decoupled(new EgressFlit(flitWidth)))
val b = Decoupled(new IngressFlit(flitWidth))
val c = Flipped(Decoupled(new EgressFlit(flitWidth)))
val d = Decoupled(new IngressFlit(flitWidth))
val e = Flipped(Decoupled(new EgressFlit(flitWidth)))
}
})
val a = Module(new TLAFromNoC(edgeOut, wideBundle))
val b = Module(new TLBToNoC(edgeOut, edgesIn, wideBundle, (i) => masterToEgressOffset(i) + 0))
val c = Module(new TLCFromNoC(edgeOut, wideBundle))
val d = Module(new TLDToNoC(edgeOut, edgesIn, wideBundle, (i) => masterToEgressOffset(i) + 1, sourceStart))
val e = Module(new TLEFromNoC(edgeOut, wideBundle, sourceSize))
io.tilelink.a <> a.io.protocol
b.io.protocol <> io.tilelink.b
io.tilelink.c <> c.io.protocol
d.io.protocol <> io.tilelink.d
io.tilelink.e <> e.io.protocol
a.io.flit <> io.flits.a
io.flits.b <> b.io.flit
c.io.flit <> io.flits.c
io.flits.d <> d.io.flit
e.io.flit <> io.flits.e
}
class TLSlaveACDToNoC(
edgeOut: TLEdge, edgesIn: Seq[TLEdge],
sourceStart: Int, sourceSize: Int,
wideBundle: TLBundleParameters,
masterToEgressOffset: Int => Int,
flitWidth: Int
)(implicit p: Parameters) extends Module {
val io = IO(new Bundle {
val tilelink = new TLBundle(wideBundle)
val flits = new Bundle {
val a = Flipped(Decoupled(new EgressFlit(flitWidth)))
val c = Flipped(Decoupled(new EgressFlit(flitWidth)))
val d = Decoupled(new IngressFlit(flitWidth))
}
})
io.tilelink := DontCare
val a = Module(new TLAFromNoC(edgeOut, wideBundle))
val c = Module(new TLCFromNoC(edgeOut, wideBundle))
val d = Module(new TLDToNoC(edgeOut, edgesIn, wideBundle, (i) => masterToEgressOffset(i) + 0, sourceStart))
io.tilelink.a <> a.io.protocol
io.tilelink.c <> c.io.protocol
d.io.protocol <> io.tilelink.d
a.io.flit <> io.flits.a
c.io.flit <> io.flits.c
io.flits.d <> d.io.flit
}
class TLSlaveBEToNoC(
edgeOut: TLEdge, edgesIn: Seq[TLEdge],
sourceStart: Int, sourceSize: Int,
wideBundle: TLBundleParameters,
masterToEgressOffset: Int => Int,
flitWidth: Int
)(implicit p: Parameters) extends Module {
val io = IO(new Bundle {
val tilelink = new TLBundle(wideBundle)
val flits = new Bundle {
val b = Decoupled(new IngressFlit(flitWidth))
val e = Flipped(Decoupled(new EgressFlit(flitWidth)))
}
})
io.tilelink := DontCare
val b = Module(new TLBToNoC(edgeOut, edgesIn, wideBundle, (i) => masterToEgressOffset(i) + 0))
val e = Module(new TLEFromNoC(edgeOut, wideBundle, sourceSize))
b.io.protocol <> io.tilelink.b
io.tilelink.e <> e.io.protocol
io.flits.b <> b.io.flit
e.io.flit <> io.flits.e
}
class TileLinkInterconnectInterface(edgesIn: Seq[TLEdge], edgesOut: Seq[TLEdge])(implicit val p: Parameters) extends Bundle {
val in = MixedVec(edgesIn.map { e => Flipped(new TLBundle(e.bundle)) })
val out = MixedVec(edgesOut.map { e => new TLBundle(e.bundle) })
}
trait TileLinkProtocolParams extends ProtocolParams with TLFieldHelper {
def edgesIn: Seq[TLEdge]
def edgesOut: Seq[TLEdge]
def edgeInNodes: Seq[Int]
def edgeOutNodes: Seq[Int]
require(edgesIn.size == edgeInNodes.size && edgesOut.size == edgeOutNodes.size)
def wideBundle = TLBundleParameters.union(edgesIn.map(_.bundle) ++ edgesOut.map(_.bundle))
def genBundle = new TLBundle(wideBundle)
def inputIdRanges = TLXbar.mapInputIds(edgesIn.map(_.client))
def outputIdRanges = TLXbar.mapOutputIds(edgesOut.map(_.manager))
val vNetBlocking = (blocker: Int, blockee: Int) => blocker < blockee
def genIO()(implicit p: Parameters): Data = new TileLinkInterconnectInterface(edgesIn, edgesOut)
}
object TLConnect {
def apply[T <: TLBundleBase](l: DecoupledIO[T], r: DecoupledIO[T]) = {
l.valid := r.valid
r.ready := l.ready
l.bits.squeezeAll.waiveAll :<>= r.bits.squeezeAll.waiveAll
}
}
// BEGIN: TileLinkProtocolParams
case class TileLinkABCDEProtocolParams(
edgesIn: Seq[TLEdge],
edgesOut: Seq[TLEdge],
edgeInNodes: Seq[Int],
edgeOutNodes: Seq[Int]
) extends TileLinkProtocolParams {
// END: TileLinkProtocolParams
val minPayloadWidth = minTLPayloadWidth(new TLBundle(wideBundle))
val ingressNodes = (edgeInNodes.map(u => Seq.fill(3) (u)) ++ edgeOutNodes.map(u => Seq.fill (2) {u})).flatten
val egressNodes = (edgeInNodes.map(u => Seq.fill(2) (u)) ++ edgeOutNodes.map(u => Seq.fill (3) {u})).flatten
val nVirtualNetworks = 5
val flows = edgesIn.zipWithIndex.map { case (edgeIn, ii) => edgesOut.zipWithIndex.map { case (edgeOut, oi) =>
val reachable = edgeIn.client.clients.exists { c => edgeOut.manager.managers.exists { m =>
c.visibility.exists { ca => m.address.exists { ma =>
ca.overlaps(ma)
}}
}}
val probe = edgeIn.client.anySupportProbe && edgeOut.manager.managers.exists(_.regionType >= RegionType.TRACKED)
val release = edgeIn.client.anySupportProbe && edgeOut.manager.anySupportAcquireB
( (if (reachable) Some(FlowParams(ii * 3 + 0 , oi * 3 + 0 + edgesIn.size * 2, 4)) else None) ++ // A
(if (probe ) Some(FlowParams(oi * 2 + 0 + edgesIn.size * 3, ii * 2 + 0 , 3)) else None) ++ // B
(if (release ) Some(FlowParams(ii * 3 + 1 , oi * 3 + 1 + edgesIn.size * 2, 2)) else None) ++ // C
(if (reachable) Some(FlowParams(oi * 2 + 1 + edgesIn.size * 3, ii * 2 + 1 , 1)) else None) ++ // D
(if (release ) Some(FlowParams(ii * 3 + 2 , oi * 3 + 2 + edgesIn.size * 2, 0)) else None)) // E
}}.flatten.flatten
def interface(terminals: NoCTerminalIO,
ingressOffset: Int, egressOffset: Int, protocol: Data)(implicit p: Parameters) = {
val ingresses = terminals.ingress
val egresses = terminals.egress
protocol match { case protocol: TileLinkInterconnectInterface => {
edgesIn.zipWithIndex.map { case (e,i) =>
val nif_master = Module(new TLMasterToNoC(
e, edgesOut, inputIdRanges(i).start, inputIdRanges(i).size,
wideBundle,
(s) => s * 3 + edgesIn.size * 2 + egressOffset,
minPayloadWidth
))
nif_master.io.tilelink := DontCare
nif_master.io.tilelink.a.valid := false.B
nif_master.io.tilelink.c.valid := false.B
nif_master.io.tilelink.e.valid := false.B
TLConnect(nif_master.io.tilelink.a, protocol.in(i).a)
TLConnect(protocol.in(i).d, nif_master.io.tilelink.d)
if (protocol.in(i).params.hasBCE) {
TLConnect(protocol.in(i).b, nif_master.io.tilelink.b)
TLConnect(nif_master.io.tilelink.c, protocol.in(i).c)
TLConnect(nif_master.io.tilelink.e, protocol.in(i).e)
}
ingresses(i * 3 + 0).flit <> nif_master.io.flits.a
ingresses(i * 3 + 1).flit <> nif_master.io.flits.c
ingresses(i * 3 + 2).flit <> nif_master.io.flits.e
nif_master.io.flits.b <> egresses(i * 2 + 0).flit
nif_master.io.flits.d <> egresses(i * 2 + 1).flit
}
edgesOut.zipWithIndex.map { case (e,i) =>
val nif_slave = Module(new TLSlaveToNoC(
e, edgesIn, outputIdRanges(i).start, outputIdRanges(i).size,
wideBundle,
(s) => s * 2 + egressOffset,
minPayloadWidth
))
nif_slave.io.tilelink := DontCare
nif_slave.io.tilelink.b.valid := false.B
nif_slave.io.tilelink.d.valid := false.B
TLConnect(protocol.out(i).a, nif_slave.io.tilelink.a)
TLConnect(nif_slave.io.tilelink.d, protocol.out(i).d)
if (protocol.out(i).params.hasBCE) {
TLConnect(nif_slave.io.tilelink.b, protocol.out(i).b)
TLConnect(protocol.out(i).c, nif_slave.io.tilelink.c)
TLConnect(protocol.out(i).e, nif_slave.io.tilelink.e)
}
ingresses(i * 2 + 0 + edgesIn.size * 3).flit <> nif_slave.io.flits.b
ingresses(i * 2 + 1 + edgesIn.size * 3).flit <> nif_slave.io.flits.d
nif_slave.io.flits.a <> egresses(i * 3 + 0 + edgesIn.size * 2).flit
nif_slave.io.flits.c <> egresses(i * 3 + 1 + edgesIn.size * 2).flit
nif_slave.io.flits.e <> egresses(i * 3 + 2 + edgesIn.size * 2).flit
}
} }
}
}
case class TileLinkACDProtocolParams(
edgesIn: Seq[TLEdge],
edgesOut: Seq[TLEdge],
edgeInNodes: Seq[Int],
edgeOutNodes: Seq[Int]) extends TileLinkProtocolParams {
val minPayloadWidth = minTLPayloadWidth(Seq(genBundle.a, genBundle.c, genBundle.d).map(_.bits))
val ingressNodes = (edgeInNodes.map(u => Seq.fill(2) (u)) ++ edgeOutNodes.map(u => Seq.fill (1) {u})).flatten
val egressNodes = (edgeInNodes.map(u => Seq.fill(1) (u)) ++ edgeOutNodes.map(u => Seq.fill (2) {u})).flatten
val nVirtualNetworks = 3
val flows = edgesIn.zipWithIndex.map { case (edgeIn, ii) => edgesOut.zipWithIndex.map { case (edgeOut, oi) =>
val reachable = edgeIn.client.clients.exists { c => edgeOut.manager.managers.exists { m =>
c.visibility.exists { ca => m.address.exists { ma =>
ca.overlaps(ma)
}}
}}
val release = edgeIn.client.anySupportProbe && edgeOut.manager.anySupportAcquireB
( (if (reachable) Some(FlowParams(ii * 2 + 0 , oi * 2 + 0 + edgesIn.size * 1, 2)) else None) ++ // A
(if (release ) Some(FlowParams(ii * 2 + 1 , oi * 2 + 1 + edgesIn.size * 1, 1)) else None) ++ // C
(if (reachable) Some(FlowParams(oi * 1 + 0 + edgesIn.size * 2, ii * 1 + 0 , 0)) else None)) // D
}}.flatten.flatten
def interface(terminals: NoCTerminalIO,
ingressOffset: Int, egressOffset: Int, protocol: Data)(implicit p: Parameters) = {
val ingresses = terminals.ingress
val egresses = terminals.egress
protocol match { case protocol: TileLinkInterconnectInterface => {
protocol := DontCare
edgesIn.zipWithIndex.map { case (e,i) =>
val nif_master_acd = Module(new TLMasterACDToNoC(
e, edgesOut, inputIdRanges(i).start, inputIdRanges(i).size,
wideBundle,
(s) => s * 2 + edgesIn.size * 1 + egressOffset,
minPayloadWidth
))
nif_master_acd.io.tilelink := DontCare
nif_master_acd.io.tilelink.a.valid := false.B
nif_master_acd.io.tilelink.c.valid := false.B
nif_master_acd.io.tilelink.e.valid := false.B
TLConnect(nif_master_acd.io.tilelink.a, protocol.in(i).a)
TLConnect(protocol.in(i).d, nif_master_acd.io.tilelink.d)
if (protocol.in(i).params.hasBCE) {
TLConnect(nif_master_acd.io.tilelink.c, protocol.in(i).c)
}
ingresses(i * 2 + 0).flit <> nif_master_acd.io.flits.a
ingresses(i * 2 + 1).flit <> nif_master_acd.io.flits.c
nif_master_acd.io.flits.d <> egresses(i * 1 + 0).flit
}
edgesOut.zipWithIndex.map { case (e,i) =>
val nif_slave_acd = Module(new TLSlaveACDToNoC(
e, edgesIn, outputIdRanges(i).start, outputIdRanges(i).size,
wideBundle,
(s) => s * 1 + egressOffset,
minPayloadWidth
))
nif_slave_acd.io.tilelink := DontCare
nif_slave_acd.io.tilelink.b.valid := false.B
nif_slave_acd.io.tilelink.d.valid := false.B
TLConnect(protocol.out(i).a, nif_slave_acd.io.tilelink.a)
TLConnect(nif_slave_acd.io.tilelink.d, protocol.out(i).d)
if (protocol.out(i).params.hasBCE) {
TLConnect(protocol.out(i).c, nif_slave_acd.io.tilelink.c)
}
ingresses(i * 1 + 0 + edgesIn.size * 2).flit <> nif_slave_acd.io.flits.d
nif_slave_acd.io.flits.a <> egresses(i * 2 + 0 + edgesIn.size * 1).flit
nif_slave_acd.io.flits.c <> egresses(i * 2 + 1 + edgesIn.size * 1).flit
}
}}
}
}
case class TileLinkBEProtocolParams(
edgesIn: Seq[TLEdge],
edgesOut: Seq[TLEdge],
edgeInNodes: Seq[Int],
edgeOutNodes: Seq[Int]) extends TileLinkProtocolParams {
val minPayloadWidth = minTLPayloadWidth(Seq(genBundle.b, genBundle.e).map(_.bits))
val ingressNodes = (edgeInNodes.map(u => Seq.fill(1) (u)) ++ edgeOutNodes.map(u => Seq.fill (1) {u})).flatten
val egressNodes = (edgeInNodes.map(u => Seq.fill(1) (u)) ++ edgeOutNodes.map(u => Seq.fill (1) {u})).flatten
val nVirtualNetworks = 2
val flows = edgesIn.zipWithIndex.map { case (edgeIn, ii) => edgesOut.zipWithIndex.map { case (edgeOut, oi) =>
val probe = edgeIn.client.anySupportProbe && edgeOut.manager.managers.exists(_.regionType >= RegionType.TRACKED)
val release = edgeIn.client.anySupportProbe && edgeOut.manager.anySupportAcquireB
( (if (probe ) Some(FlowParams(oi * 1 + 0 + edgesIn.size * 1, ii * 1 + 0 , 1)) else None) ++ // B
(if (release ) Some(FlowParams(ii * 1 + 0 , oi * 1 + 0 + edgesIn.size * 1, 0)) else None)) // E
}}.flatten.flatten
def interface(terminals: NoCTerminalIO,
ingressOffset: Int, egressOffset: Int, protocol: Data)(implicit p: Parameters) = {
val ingresses = terminals.ingress
val egresses = terminals.egress
protocol match { case protocol: TileLinkInterconnectInterface => {
protocol := DontCare
edgesIn.zipWithIndex.map { case (e,i) =>
val nif_master_be = Module(new TLMasterBEToNoC(
e, edgesOut, inputIdRanges(i).start, inputIdRanges(i).size,
wideBundle,
(s) => s * 1 + edgesIn.size * 1 + egressOffset,
minPayloadWidth
))
nif_master_be.io.tilelink := DontCare
nif_master_be.io.tilelink.a.valid := false.B
nif_master_be.io.tilelink.c.valid := false.B
nif_master_be.io.tilelink.e.valid := false.B
if (protocol.in(i).params.hasBCE) {
TLConnect(protocol.in(i).b, nif_master_be.io.tilelink.b)
TLConnect(nif_master_be.io.tilelink.e, protocol.in(i).e)
}
ingresses(i * 1 + 0).flit <> nif_master_be.io.flits.e
nif_master_be.io.flits.b <> egresses(i * 1 + 0).flit
}
edgesOut.zipWithIndex.map { case (e,i) =>
val nif_slave_be = Module(new TLSlaveBEToNoC(
e, edgesIn, outputIdRanges(i).start, outputIdRanges(i).size,
wideBundle,
(s) => s * 1 + egressOffset,
minPayloadWidth
))
nif_slave_be.io.tilelink := DontCare
nif_slave_be.io.tilelink.b.valid := false.B
nif_slave_be.io.tilelink.d.valid := false.B
if (protocol.out(i).params.hasBCE) {
TLConnect(protocol.out(i).e, nif_slave_be.io.tilelink.e)
TLConnect(nif_slave_be.io.tilelink.b, protocol.out(i).b)
}
ingresses(i * 1 + 0 + edgesIn.size * 1).flit <> nif_slave_be.io.flits.b
nif_slave_be.io.flits.e <> egresses(i * 1 + 0 + edgesIn.size * 1).flit
}
}}
}
}
abstract class TLNoCLike(implicit p: Parameters) extends LazyModule {
val node = new TLNexusNode(
clientFn = { seq =>
seq(0).v1copy(
echoFields = BundleField.union(seq.flatMap(_.echoFields)),
requestFields = BundleField.union(seq.flatMap(_.requestFields)),
responseKeys = seq.flatMap(_.responseKeys).distinct,
minLatency = seq.map(_.minLatency).min,
clients = (TLXbar.mapInputIds(seq) zip seq) flatMap { case (range, port) =>
port.clients map { client => client.v1copy(
sourceId = client.sourceId.shift(range.start)
)}
}
)
},
managerFn = { seq =>
val fifoIdFactory = TLXbar.relabeler()
seq(0).v1copy(
responseFields = BundleField.union(seq.flatMap(_.responseFields)),
requestKeys = seq.flatMap(_.requestKeys).distinct,
minLatency = seq.map(_.minLatency).min,
endSinkId = TLXbar.mapOutputIds(seq).map(_.end).max,
managers = seq.flatMap { port =>
require (port.beatBytes == seq(0).beatBytes,
s"TLNoC (data widths don't match: ${port.managers.map(_.name)} has ${port.beatBytes}B vs ${seq(0).managers.map(_.name)} has ${seq(0).beatBytes}B")
// TileLink NoC does not preserve FIFO-ness, masters to this NoC should instantiate FIFOFixers
port.managers map { manager => manager.v1copy(fifoId = None) }
}
)
}
)
}
abstract class TLNoCModuleImp(outer: LazyModule) extends LazyModuleImp(outer) {
val edgesIn: Seq[TLEdge]
val edgesOut: Seq[TLEdge]
val nodeMapping: DiplomaticNetworkNodeMapping
val nocName: String
lazy val inNames = nodeMapping.genUniqueName(edgesIn.map(_.master.masters.map(_.name)))
lazy val outNames = nodeMapping.genUniqueName(edgesOut.map(_.slave.slaves.map(_.name)))
lazy val edgeInNodes = nodeMapping.getNodesIn(inNames)
lazy val edgeOutNodes = nodeMapping.getNodesOut(outNames)
def printNodeMappings() {
println(s"Constellation: TLNoC $nocName inwards mapping:")
for ((n, i) <- inNames zip edgeInNodes) {
val node = i.map(_.toString).getOrElse("X")
println(s" $node <- $n")
}
println(s"Constellation: TLNoC $nocName outwards mapping:")
for ((n, i) <- outNames zip edgeOutNodes) {
val node = i.map(_.toString).getOrElse("X")
println(s" $node <- $n")
}
}
}
trait TLNoCParams
// Instantiates a private TLNoC. Replaces the TLXbar
// BEGIN: TLNoCParams
case class SimpleTLNoCParams(
nodeMappings: DiplomaticNetworkNodeMapping,
nocParams: NoCParams = NoCParams(),
) extends TLNoCParams
class TLNoC(params: SimpleTLNoCParams, name: String = "test", inlineNoC: Boolean = false)(implicit p: Parameters) extends TLNoCLike {
// END: TLNoCParams
override def shouldBeInlined = inlineNoC
lazy val module = new TLNoCModuleImp(this) {
val (io_in, edgesIn) = node.in.unzip
val (io_out, edgesOut) = node.out.unzip
val nodeMapping = params.nodeMappings
val nocName = name
printNodeMappings()
val protocolParams = TileLinkABCDEProtocolParams(
edgesIn = edgesIn,
edgesOut = edgesOut,
edgeInNodes = edgeInNodes.flatten,
edgeOutNodes = edgeOutNodes.flatten
)
val noc = Module(new ProtocolNoC(ProtocolNoCParams(
params.nocParams.copy(hasCtrl = false, nocName=name, inlineNoC = inlineNoC),
Seq(protocolParams),
inlineNoC = inlineNoC
)))
noc.io.protocol(0) match {
case protocol: TileLinkInterconnectInterface => {
(protocol.in zip io_in).foreach { case (l,r) => l <> r }
(io_out zip protocol.out).foreach { case (l,r) => l <> r }
}
}
}
}
case class SplitACDxBETLNoCParams(
nodeMappings: DiplomaticNetworkNodeMapping,
acdNoCParams: NoCParams = NoCParams(),
beNoCParams: NoCParams = NoCParams(),
beDivision: Int = 2
) extends TLNoCParams
class TLSplitACDxBENoC(params: SplitACDxBETLNoCParams, name: String = "test", inlineNoC: Boolean = false)(implicit p: Parameters) extends TLNoCLike {
override def shouldBeInlined = inlineNoC
lazy val module = new TLNoCModuleImp(this) {
val (io_in, edgesIn) = node.in.unzip
val (io_out, edgesOut) = node.out.unzip
val nodeMapping = params.nodeMappings
val nocName = name
printNodeMappings()
val acdProtocolParams = TileLinkACDProtocolParams(
edgesIn = edgesIn,
edgesOut = edgesOut,
edgeInNodes = edgeInNodes.flatten,
edgeOutNodes = edgeOutNodes.flatten
)
val beProtocolParams = TileLinkBEProtocolParams(
edgesIn = edgesIn,
edgesOut = edgesOut,
edgeInNodes = edgeInNodes.flatten,
edgeOutNodes = edgeOutNodes.flatten
)
val acd_noc = Module(new ProtocolNoC(ProtocolNoCParams(
params.acdNoCParams.copy(hasCtrl = false, nocName=s"${name}_acd", inlineNoC = inlineNoC),
Seq(acdProtocolParams),
inlineNoC = inlineNoC
)))
val be_noc = Module(new ProtocolNoC(ProtocolNoCParams(
params.beNoCParams.copy(hasCtrl = false, nocName=s"${name}_be", inlineNoC = inlineNoC),
Seq(beProtocolParams),
widthDivision = params.beDivision,
inlineNoC = inlineNoC
)))
acd_noc.io.protocol(0) match { case protocol: TileLinkInterconnectInterface => {
(protocol.in zip io_in).foreach { case (l,r) =>
l := DontCare
l.a <> r.a
l.c <> r.c
l.d <> r.d
}
(io_out zip protocol.out).foreach { case (l,r) =>
r := DontCare
l.a <> r.a
l.c <> r.c
l.d <> r.d
}
}}
be_noc.io.protocol(0) match { case protocol: TileLinkInterconnectInterface => {
(protocol.in zip io_in).foreach { case (l,r) =>
l := DontCare
l.b <> r.b
l.e <> r.e
}
(io_out zip protocol.out).foreach { case (l,r) =>
r := DontCare
l.b <> r.b
l.e <> r.e
}
}}
}
}
case class GlobalTLNoCParams(
nodeMappings: DiplomaticNetworkNodeMapping
) extends TLNoCParams
// Maps this interconnect onto a global NoC
class TLGlobalNoC(params: GlobalTLNoCParams, name: String = "test")(implicit p: Parameters) extends TLNoCLike {
lazy val module = new TLNoCModuleImp(this) with CanAttachToGlobalNoC {
val (io_in, edgesIn) = node.in.unzip
val (io_out, edgesOut) = node.out.unzip
val nodeMapping = params.nodeMappings
val nocName = name
val protocolParams = TileLinkABCDEProtocolParams(
edgesIn = edgesIn,
edgesOut = edgesOut,
edgeInNodes = edgeInNodes.flatten,
edgeOutNodes = edgeOutNodes.flatten
)
printNodeMappings()
val io_global = IO(Flipped(protocolParams.genIO()))
io_global match {
case protocol: TileLinkInterconnectInterface => {
(protocol.in zip io_in).foreach { case (l,r) => l <> r }
(io_out zip protocol.out).foreach { case (l,r) => l <> r }
}
}
}
}
| module TLSlaveToNoC_5( // @[Tilelink.scala:125:7]
input clock, // @[Tilelink.scala:125:7]
input reset, // @[Tilelink.scala:125:7]
input io_tilelink_a_ready, // @[Tilelink.scala:132:14]
output io_tilelink_a_valid, // @[Tilelink.scala:132:14]
output [2:0] io_tilelink_a_bits_opcode, // @[Tilelink.scala:132:14]
output [2:0] io_tilelink_a_bits_param, // @[Tilelink.scala:132:14]
output [3:0] io_tilelink_a_bits_size, // @[Tilelink.scala:132:14]
output [6:0] io_tilelink_a_bits_source, // @[Tilelink.scala:132:14]
output [28:0] io_tilelink_a_bits_address, // @[Tilelink.scala:132:14]
output [7:0] io_tilelink_a_bits_mask, // @[Tilelink.scala:132:14]
output [63:0] io_tilelink_a_bits_data, // @[Tilelink.scala:132:14]
output io_tilelink_a_bits_corrupt, // @[Tilelink.scala:132:14]
output io_tilelink_d_ready, // @[Tilelink.scala:132:14]
input io_tilelink_d_valid, // @[Tilelink.scala:132:14]
input [2:0] io_tilelink_d_bits_opcode, // @[Tilelink.scala:132:14]
input [1:0] io_tilelink_d_bits_param, // @[Tilelink.scala:132:14]
input [3:0] io_tilelink_d_bits_size, // @[Tilelink.scala:132:14]
input [6:0] io_tilelink_d_bits_source, // @[Tilelink.scala:132:14]
input io_tilelink_d_bits_sink, // @[Tilelink.scala:132:14]
input io_tilelink_d_bits_denied, // @[Tilelink.scala:132:14]
input [63:0] io_tilelink_d_bits_data, // @[Tilelink.scala:132:14]
input io_tilelink_d_bits_corrupt, // @[Tilelink.scala:132:14]
output io_flits_a_ready, // @[Tilelink.scala:132:14]
input io_flits_a_valid, // @[Tilelink.scala:132:14]
input io_flits_a_bits_head, // @[Tilelink.scala:132:14]
input io_flits_a_bits_tail, // @[Tilelink.scala:132:14]
input [72:0] io_flits_a_bits_payload, // @[Tilelink.scala:132:14]
output io_flits_c_ready, // @[Tilelink.scala:132:14]
input io_flits_c_valid, // @[Tilelink.scala:132:14]
input io_flits_c_bits_head, // @[Tilelink.scala:132:14]
input io_flits_c_bits_tail, // @[Tilelink.scala:132:14]
input io_flits_d_ready, // @[Tilelink.scala:132:14]
output io_flits_d_valid, // @[Tilelink.scala:132:14]
output io_flits_d_bits_head, // @[Tilelink.scala:132:14]
output io_flits_d_bits_tail, // @[Tilelink.scala:132:14]
output [72:0] io_flits_d_bits_payload, // @[Tilelink.scala:132:14]
output io_flits_e_ready, // @[Tilelink.scala:132:14]
input io_flits_e_valid, // @[Tilelink.scala:132:14]
input io_flits_e_bits_head, // @[Tilelink.scala:132:14]
input io_flits_e_bits_tail // @[Tilelink.scala:132:14]
);
wire [64:0] _d_io_flit_bits_payload; // @[Tilelink.scala:146:17]
TLAFromNoC_5 a ( // @[Tilelink.scala:143:17]
.clock (clock),
.reset (reset),
.io_protocol_ready (io_tilelink_a_ready),
.io_protocol_valid (io_tilelink_a_valid),
.io_protocol_bits_opcode (io_tilelink_a_bits_opcode),
.io_protocol_bits_param (io_tilelink_a_bits_param),
.io_protocol_bits_size (io_tilelink_a_bits_size),
.io_protocol_bits_source (io_tilelink_a_bits_source),
.io_protocol_bits_address (io_tilelink_a_bits_address),
.io_protocol_bits_mask (io_tilelink_a_bits_mask),
.io_protocol_bits_data (io_tilelink_a_bits_data),
.io_protocol_bits_corrupt (io_tilelink_a_bits_corrupt),
.io_flit_ready (io_flits_a_ready),
.io_flit_valid (io_flits_a_valid),
.io_flit_bits_head (io_flits_a_bits_head),
.io_flit_bits_tail (io_flits_a_bits_tail),
.io_flit_bits_payload (io_flits_a_bits_payload)
); // @[Tilelink.scala:143:17]
TLCFromNoC_5 c ( // @[Tilelink.scala:145:17]
.clock (clock),
.reset (reset),
.io_flit_ready (io_flits_c_ready),
.io_flit_valid (io_flits_c_valid),
.io_flit_bits_head (io_flits_c_bits_head),
.io_flit_bits_tail (io_flits_c_bits_tail)
); // @[Tilelink.scala:145:17]
TLDToNoC_5 d ( // @[Tilelink.scala:146:17]
.clock (clock),
.reset (reset),
.io_protocol_ready (io_tilelink_d_ready),
.io_protocol_valid (io_tilelink_d_valid),
.io_protocol_bits_opcode (io_tilelink_d_bits_opcode),
.io_protocol_bits_param (io_tilelink_d_bits_param),
.io_protocol_bits_size (io_tilelink_d_bits_size),
.io_protocol_bits_source (io_tilelink_d_bits_source),
.io_protocol_bits_sink (io_tilelink_d_bits_sink),
.io_protocol_bits_denied (io_tilelink_d_bits_denied),
.io_protocol_bits_data (io_tilelink_d_bits_data),
.io_protocol_bits_corrupt (io_tilelink_d_bits_corrupt),
.io_flit_ready (io_flits_d_ready),
.io_flit_valid (io_flits_d_valid),
.io_flit_bits_head (io_flits_d_bits_head),
.io_flit_bits_tail (io_flits_d_bits_tail),
.io_flit_bits_payload (_d_io_flit_bits_payload)
); // @[Tilelink.scala:146:17]
TLEFromNoC_5 e ( // @[Tilelink.scala:147:17]
.clock (clock),
.reset (reset),
.io_flit_ready (io_flits_e_ready),
.io_flit_valid (io_flits_e_valid),
.io_flit_bits_head (io_flits_e_bits_head),
.io_flit_bits_tail (io_flits_e_bits_tail)
); // @[Tilelink.scala:147:17]
assign io_flits_d_bits_payload = {8'h0, _d_io_flit_bits_payload}; // @[Tilelink.scala:125:7, :146:17, :157:14]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File primitives.scala:
/*============================================================================
This Chisel source file is part of a pre-release version of the HardFloat IEEE
Floating-Point Arithmetic Package, by John R. Hauser (with some contributions
from Yunsup Lee and Andrew Waterman, mainly concerning testing).
Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
University of California. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
package hardfloat
import chisel3._
import chisel3.util._
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
object lowMask
{
def apply(in: UInt, topBound: BigInt, bottomBound: BigInt): UInt =
{
require(topBound != bottomBound)
val numInVals = BigInt(1)<<in.getWidth
if (topBound < bottomBound) {
lowMask(~in, numInVals - 1 - topBound, numInVals - 1 - bottomBound)
} else if (numInVals > 64 /* Empirical */) {
// For simulation performance, we should avoid generating
// exteremely wide shifters, so we divide and conquer.
// Empirically, this does not impact synthesis QoR.
val mid = numInVals / 2
val msb = in(in.getWidth - 1)
val lsbs = in(in.getWidth - 2, 0)
if (mid < topBound) {
if (mid <= bottomBound) {
Mux(msb,
lowMask(lsbs, topBound - mid, bottomBound - mid),
0.U
)
} else {
Mux(msb,
lowMask(lsbs, topBound - mid, 0) ## ((BigInt(1)<<(mid - bottomBound).toInt) - 1).U,
lowMask(lsbs, mid, bottomBound)
)
}
} else {
~Mux(msb, 0.U, ~lowMask(lsbs, topBound, bottomBound))
}
} else {
val shift = (BigInt(-1)<<numInVals.toInt).S>>in
Reverse(
shift(
(numInVals - 1 - bottomBound).toInt,
(numInVals - topBound).toInt
)
)
}
}
}
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
object countLeadingZeros
{
def apply(in: UInt): UInt = PriorityEncoder(in.asBools.reverse)
}
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
object orReduceBy2
{
def apply(in: UInt): UInt =
{
val reducedWidth = (in.getWidth + 1)>>1
val reducedVec = Wire(Vec(reducedWidth, Bool()))
for (ix <- 0 until reducedWidth - 1) {
reducedVec(ix) := in(ix * 2 + 1, ix * 2).orR
}
reducedVec(reducedWidth - 1) :=
in(in.getWidth - 1, (reducedWidth - 1) * 2).orR
reducedVec.asUInt
}
}
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
object orReduceBy4
{
def apply(in: UInt): UInt =
{
val reducedWidth = (in.getWidth + 3)>>2
val reducedVec = Wire(Vec(reducedWidth, Bool()))
for (ix <- 0 until reducedWidth - 1) {
reducedVec(ix) := in(ix * 4 + 3, ix * 4).orR
}
reducedVec(reducedWidth - 1) :=
in(in.getWidth - 1, (reducedWidth - 1) * 4).orR
reducedVec.asUInt
}
}
File RoundAnyRawFNToRecFN.scala:
/*============================================================================
This Chisel source file is part of a pre-release version of the HardFloat IEEE
Floating-Point Arithmetic Package, by John R. Hauser (with some contributions
from Yunsup Lee and Andrew Waterman, mainly concerning testing).
Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
University of California. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
package hardfloat
import chisel3._
import chisel3.util.Fill
import consts._
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
class
RoundAnyRawFNToRecFN(
inExpWidth: Int,
inSigWidth: Int,
outExpWidth: Int,
outSigWidth: Int,
options: Int
)
extends RawModule
{
override def desiredName = s"RoundAnyRawFNToRecFN_ie${inExpWidth}_is${inSigWidth}_oe${outExpWidth}_os${outSigWidth}"
val io = IO(new Bundle {
val invalidExc = Input(Bool()) // overrides 'infiniteExc' and 'in'
val infiniteExc = Input(Bool()) // overrides 'in' except for 'in.sign'
val in = Input(new RawFloat(inExpWidth, inSigWidth))
// (allowed exponent range has limits)
val roundingMode = Input(UInt(3.W))
val detectTininess = Input(UInt(1.W))
val out = Output(Bits((outExpWidth + outSigWidth + 1).W))
val exceptionFlags = Output(Bits(5.W))
})
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val sigMSBitAlwaysZero = ((options & flRoundOpt_sigMSBitAlwaysZero) != 0)
val effectiveInSigWidth =
if (sigMSBitAlwaysZero) inSigWidth else inSigWidth + 1
val neverUnderflows =
((options &
(flRoundOpt_neverUnderflows | flRoundOpt_subnormsAlwaysExact)
) != 0) ||
(inExpWidth < outExpWidth)
val neverOverflows =
((options & flRoundOpt_neverOverflows) != 0) ||
(inExpWidth < outExpWidth)
val outNaNExp = BigInt(7)<<(outExpWidth - 2)
val outInfExp = BigInt(6)<<(outExpWidth - 2)
val outMaxFiniteExp = outInfExp - 1
val outMinNormExp = (BigInt(1)<<(outExpWidth - 1)) + 2
val outMinNonzeroExp = outMinNormExp - outSigWidth + 1
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val roundingMode_near_even = (io.roundingMode === round_near_even)
val roundingMode_minMag = (io.roundingMode === round_minMag)
val roundingMode_min = (io.roundingMode === round_min)
val roundingMode_max = (io.roundingMode === round_max)
val roundingMode_near_maxMag = (io.roundingMode === round_near_maxMag)
val roundingMode_odd = (io.roundingMode === round_odd)
val roundMagUp =
(roundingMode_min && io.in.sign) || (roundingMode_max && ! io.in.sign)
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val sAdjustedExp =
if (inExpWidth < outExpWidth)
(io.in.sExp +&
((BigInt(1)<<outExpWidth) - (BigInt(1)<<inExpWidth)).S
)(outExpWidth, 0).zext
else if (inExpWidth == outExpWidth)
io.in.sExp
else
io.in.sExp +&
((BigInt(1)<<outExpWidth) - (BigInt(1)<<inExpWidth)).S
val adjustedSig =
if (inSigWidth <= outSigWidth + 2)
io.in.sig<<(outSigWidth - inSigWidth + 2)
else
(io.in.sig(inSigWidth, inSigWidth - outSigWidth - 1) ##
io.in.sig(inSigWidth - outSigWidth - 2, 0).orR
)
val doShiftSigDown1 =
if (sigMSBitAlwaysZero) false.B else adjustedSig(outSigWidth + 2)
val common_expOut = Wire(UInt((outExpWidth + 1).W))
val common_fractOut = Wire(UInt((outSigWidth - 1).W))
val common_overflow = Wire(Bool())
val common_totalUnderflow = Wire(Bool())
val common_underflow = Wire(Bool())
val common_inexact = Wire(Bool())
if (
neverOverflows && neverUnderflows
&& (effectiveInSigWidth <= outSigWidth)
) {
//--------------------------------------------------------------------
//--------------------------------------------------------------------
common_expOut := sAdjustedExp(outExpWidth, 0) + doShiftSigDown1
common_fractOut :=
Mux(doShiftSigDown1,
adjustedSig(outSigWidth + 1, 3),
adjustedSig(outSigWidth, 2)
)
common_overflow := false.B
common_totalUnderflow := false.B
common_underflow := false.B
common_inexact := false.B
} else {
//--------------------------------------------------------------------
//--------------------------------------------------------------------
val roundMask =
if (neverUnderflows)
0.U(outSigWidth.W) ## doShiftSigDown1 ## 3.U(2.W)
else
(lowMask(
sAdjustedExp(outExpWidth, 0),
outMinNormExp - outSigWidth - 1,
outMinNormExp
) | doShiftSigDown1) ##
3.U(2.W)
val shiftedRoundMask = 0.U(1.W) ## roundMask>>1
val roundPosMask = ~shiftedRoundMask & roundMask
val roundPosBit = (adjustedSig & roundPosMask).orR
val anyRoundExtra = (adjustedSig & shiftedRoundMask).orR
val anyRound = roundPosBit || anyRoundExtra
val roundIncr =
((roundingMode_near_even || roundingMode_near_maxMag) &&
roundPosBit) ||
(roundMagUp && anyRound)
val roundedSig: Bits =
Mux(roundIncr,
(((adjustedSig | roundMask)>>2) +& 1.U) &
~Mux(roundingMode_near_even && roundPosBit &&
! anyRoundExtra,
roundMask>>1,
0.U((outSigWidth + 2).W)
),
(adjustedSig & ~roundMask)>>2 |
Mux(roundingMode_odd && anyRound, roundPosMask>>1, 0.U)
)
//*** IF SIG WIDTH IS VERY NARROW, NEED TO ACCOUNT FOR ROUND-EVEN ZEROING
//*** M.S. BIT OF SUBNORMAL SIG?
val sRoundedExp = sAdjustedExp +& (roundedSig>>outSigWidth).asUInt.zext
common_expOut := sRoundedExp(outExpWidth, 0)
common_fractOut :=
Mux(doShiftSigDown1,
roundedSig(outSigWidth - 1, 1),
roundedSig(outSigWidth - 2, 0)
)
common_overflow :=
(if (neverOverflows) false.B else
//*** REWRITE BASED ON BEFORE-ROUNDING EXPONENT?:
(sRoundedExp>>(outExpWidth - 1) >= 3.S))
common_totalUnderflow :=
(if (neverUnderflows) false.B else
//*** WOULD BE GOOD ENOUGH TO USE EXPONENT BEFORE ROUNDING?:
(sRoundedExp < outMinNonzeroExp.S))
val unboundedRange_roundPosBit =
Mux(doShiftSigDown1, adjustedSig(2), adjustedSig(1))
val unboundedRange_anyRound =
(doShiftSigDown1 && adjustedSig(2)) || adjustedSig(1, 0).orR
val unboundedRange_roundIncr =
((roundingMode_near_even || roundingMode_near_maxMag) &&
unboundedRange_roundPosBit) ||
(roundMagUp && unboundedRange_anyRound)
val roundCarry =
Mux(doShiftSigDown1,
roundedSig(outSigWidth + 1),
roundedSig(outSigWidth)
)
common_underflow :=
(if (neverUnderflows) false.B else
common_totalUnderflow ||
//*** IF SIG WIDTH IS VERY NARROW, NEED TO ACCOUNT FOR ROUND-EVEN ZEROING
//*** M.S. BIT OF SUBNORMAL SIG?
(anyRound && ((sAdjustedExp>>outExpWidth) <= 0.S) &&
Mux(doShiftSigDown1, roundMask(3), roundMask(2)) &&
! ((io.detectTininess === tininess_afterRounding) &&
! Mux(doShiftSigDown1,
roundMask(4),
roundMask(3)
) &&
roundCarry && roundPosBit &&
unboundedRange_roundIncr)))
common_inexact := common_totalUnderflow || anyRound
}
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val isNaNOut = io.invalidExc || io.in.isNaN
val notNaN_isSpecialInfOut = io.infiniteExc || io.in.isInf
val commonCase = ! isNaNOut && ! notNaN_isSpecialInfOut && ! io.in.isZero
val overflow = commonCase && common_overflow
val underflow = commonCase && common_underflow
val inexact = overflow || (commonCase && common_inexact)
val overflow_roundMagUp =
roundingMode_near_even || roundingMode_near_maxMag || roundMagUp
val pegMinNonzeroMagOut =
commonCase && common_totalUnderflow && (roundMagUp || roundingMode_odd)
val pegMaxFiniteMagOut = overflow && ! overflow_roundMagUp
val notNaN_isInfOut =
notNaN_isSpecialInfOut || (overflow && overflow_roundMagUp)
val signOut = Mux(isNaNOut, false.B, io.in.sign)
val expOut =
(common_expOut &
~Mux(io.in.isZero || common_totalUnderflow,
(BigInt(7)<<(outExpWidth - 2)).U((outExpWidth + 1).W),
0.U
) &
~Mux(pegMinNonzeroMagOut,
~outMinNonzeroExp.U((outExpWidth + 1).W),
0.U
) &
~Mux(pegMaxFiniteMagOut,
(BigInt(1)<<(outExpWidth - 1)).U((outExpWidth + 1).W),
0.U
) &
~Mux(notNaN_isInfOut,
(BigInt(1)<<(outExpWidth - 2)).U((outExpWidth + 1).W),
0.U
)) |
Mux(pegMinNonzeroMagOut,
outMinNonzeroExp.U((outExpWidth + 1).W),
0.U
) |
Mux(pegMaxFiniteMagOut,
outMaxFiniteExp.U((outExpWidth + 1).W),
0.U
) |
Mux(notNaN_isInfOut, outInfExp.U((outExpWidth + 1).W), 0.U) |
Mux(isNaNOut, outNaNExp.U((outExpWidth + 1).W), 0.U)
val fractOut =
Mux(isNaNOut || io.in.isZero || common_totalUnderflow,
Mux(isNaNOut, (BigInt(1)<<(outSigWidth - 2)).U, 0.U),
common_fractOut
) |
Fill(outSigWidth - 1, pegMaxFiniteMagOut)
io.out := signOut ## expOut ## fractOut
io.exceptionFlags :=
io.invalidExc ## io.infiniteExc ## overflow ## underflow ## inexact
}
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
class
RoundRawFNToRecFN(expWidth: Int, sigWidth: Int, options: Int)
extends RawModule
{
override def desiredName = s"RoundRawFNToRecFN_e${expWidth}_s${sigWidth}"
val io = IO(new Bundle {
val invalidExc = Input(Bool()) // overrides 'infiniteExc' and 'in'
val infiniteExc = Input(Bool()) // overrides 'in' except for 'in.sign'
val in = Input(new RawFloat(expWidth, sigWidth + 2))
val roundingMode = Input(UInt(3.W))
val detectTininess = Input(UInt(1.W))
val out = Output(Bits((expWidth + sigWidth + 1).W))
val exceptionFlags = Output(Bits(5.W))
})
val roundAnyRawFNToRecFN =
Module(
new RoundAnyRawFNToRecFN(
expWidth, sigWidth + 2, expWidth, sigWidth, options))
roundAnyRawFNToRecFN.io.invalidExc := io.invalidExc
roundAnyRawFNToRecFN.io.infiniteExc := io.infiniteExc
roundAnyRawFNToRecFN.io.in := io.in
roundAnyRawFNToRecFN.io.roundingMode := io.roundingMode
roundAnyRawFNToRecFN.io.detectTininess := io.detectTininess
io.out := roundAnyRawFNToRecFN.io.out
io.exceptionFlags := roundAnyRawFNToRecFN.io.exceptionFlags
}
| module RoundAnyRawFNToRecFN_ie11_is55_oe11_os53_13( // @[RoundAnyRawFNToRecFN.scala:48:5]
input io_invalidExc, // @[RoundAnyRawFNToRecFN.scala:58:16]
input io_infiniteExc, // @[RoundAnyRawFNToRecFN.scala:58:16]
input io_in_isNaN, // @[RoundAnyRawFNToRecFN.scala:58:16]
input io_in_isInf, // @[RoundAnyRawFNToRecFN.scala:58:16]
input io_in_isZero, // @[RoundAnyRawFNToRecFN.scala:58:16]
input io_in_sign, // @[RoundAnyRawFNToRecFN.scala:58:16]
input [12:0] io_in_sExp, // @[RoundAnyRawFNToRecFN.scala:58:16]
input [55:0] io_in_sig, // @[RoundAnyRawFNToRecFN.scala:58:16]
input [2:0] io_roundingMode, // @[RoundAnyRawFNToRecFN.scala:58:16]
output [64:0] io_out, // @[RoundAnyRawFNToRecFN.scala:58:16]
output [4:0] io_exceptionFlags // @[RoundAnyRawFNToRecFN.scala:58:16]
);
wire io_invalidExc_0 = io_invalidExc; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire io_infiniteExc_0 = io_infiniteExc; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire io_in_isNaN_0 = io_in_isNaN; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire io_in_isInf_0 = io_in_isInf; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire io_in_isZero_0 = io_in_isZero; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire io_in_sign_0 = io_in_sign; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire [12:0] io_in_sExp_0 = io_in_sExp; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire [55:0] io_in_sig_0 = io_in_sig; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire [2:0] io_roundingMode_0 = io_roundingMode; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire [31:0] _roundMask_T_5 = 32'hFFFF; // @[primitives.scala:77:20]
wire [31:0] _roundMask_T_4 = 32'hFFFF0000; // @[primitives.scala:77:20]
wire [31:0] _roundMask_T_10 = 32'hFFFF0000; // @[primitives.scala:77:20]
wire [23:0] _roundMask_T_13 = 24'hFFFF; // @[primitives.scala:77:20]
wire [31:0] _roundMask_T_14 = 32'hFFFF00; // @[primitives.scala:77:20]
wire [31:0] _roundMask_T_15 = 32'hFF00FF; // @[primitives.scala:77:20]
wire [31:0] _roundMask_T_20 = 32'hFF00FF00; // @[primitives.scala:77:20]
wire [27:0] _roundMask_T_23 = 28'hFF00FF; // @[primitives.scala:77:20]
wire [31:0] _roundMask_T_24 = 32'hFF00FF0; // @[primitives.scala:77:20]
wire [31:0] _roundMask_T_25 = 32'hF0F0F0F; // @[primitives.scala:77:20]
wire [31:0] _roundMask_T_30 = 32'hF0F0F0F0; // @[primitives.scala:77:20]
wire [29:0] _roundMask_T_33 = 30'hF0F0F0F; // @[primitives.scala:77:20]
wire [31:0] _roundMask_T_34 = 32'h3C3C3C3C; // @[primitives.scala:77:20]
wire [31:0] _roundMask_T_35 = 32'h33333333; // @[primitives.scala:77:20]
wire [31:0] _roundMask_T_40 = 32'hCCCCCCCC; // @[primitives.scala:77:20]
wire [30:0] _roundMask_T_43 = 31'h33333333; // @[primitives.scala:77:20]
wire [31:0] _roundMask_T_44 = 32'h66666666; // @[primitives.scala:77:20]
wire [31:0] _roundMask_T_45 = 32'h55555555; // @[primitives.scala:77:20]
wire [31:0] _roundMask_T_50 = 32'hAAAAAAAA; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_56 = 16'hFF; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_55 = 16'hFF00; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_61 = 16'hFF00; // @[primitives.scala:77:20]
wire [11:0] _roundMask_T_64 = 12'hFF; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_65 = 16'hFF0; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_66 = 16'hF0F; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_71 = 16'hF0F0; // @[primitives.scala:77:20]
wire [13:0] _roundMask_T_74 = 14'hF0F; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_75 = 16'h3C3C; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_76 = 16'h3333; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_81 = 16'hCCCC; // @[primitives.scala:77:20]
wire [14:0] _roundMask_T_84 = 15'h3333; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_85 = 16'h6666; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_86 = 16'h5555; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_91 = 16'hAAAA; // @[primitives.scala:77:20]
wire [11:0] _expOut_T_4 = 12'hC31; // @[RoundAnyRawFNToRecFN.scala:258:19]
wire io_detectTininess = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire _common_underflow_T_7 = 1'h1; // @[RoundAnyRawFNToRecFN.scala:222:49]
wire [55:0] adjustedSig = io_in_sig_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :114:22]
wire [64:0] _io_out_T_1; // @[RoundAnyRawFNToRecFN.scala:286:33]
wire [4:0] _io_exceptionFlags_T_3; // @[RoundAnyRawFNToRecFN.scala:288:66]
wire [64:0] io_out_0; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire [4:0] io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire roundingMode_near_even = io_roundingMode_0 == 3'h0; // @[RoundAnyRawFNToRecFN.scala:48:5, :90:53]
wire roundingMode_minMag = io_roundingMode_0 == 3'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :91:53]
wire roundingMode_min = io_roundingMode_0 == 3'h2; // @[RoundAnyRawFNToRecFN.scala:48:5, :92:53]
wire roundingMode_max = io_roundingMode_0 == 3'h3; // @[RoundAnyRawFNToRecFN.scala:48:5, :93:53]
wire roundingMode_near_maxMag = io_roundingMode_0 == 3'h4; // @[RoundAnyRawFNToRecFN.scala:48:5, :94:53]
wire roundingMode_odd = io_roundingMode_0 == 3'h6; // @[RoundAnyRawFNToRecFN.scala:48:5, :95:53]
wire _roundMagUp_T = roundingMode_min & io_in_sign_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :92:53, :98:27]
wire _roundMagUp_T_1 = ~io_in_sign_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :98:66]
wire _roundMagUp_T_2 = roundingMode_max & _roundMagUp_T_1; // @[RoundAnyRawFNToRecFN.scala:93:53, :98:{63,66}]
wire roundMagUp = _roundMagUp_T | _roundMagUp_T_2; // @[RoundAnyRawFNToRecFN.scala:98:{27,42,63}]
wire doShiftSigDown1 = adjustedSig[55]; // @[RoundAnyRawFNToRecFN.scala:114:22, :120:57]
wire [11:0] _common_expOut_T; // @[RoundAnyRawFNToRecFN.scala:187:37]
wire [11:0] common_expOut; // @[RoundAnyRawFNToRecFN.scala:122:31]
wire [51:0] _common_fractOut_T_2; // @[RoundAnyRawFNToRecFN.scala:189:16]
wire [51:0] common_fractOut; // @[RoundAnyRawFNToRecFN.scala:123:31]
wire _common_overflow_T_1; // @[RoundAnyRawFNToRecFN.scala:196:50]
wire common_overflow; // @[RoundAnyRawFNToRecFN.scala:124:37]
wire _common_totalUnderflow_T; // @[RoundAnyRawFNToRecFN.scala:200:31]
wire common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:125:37]
wire _common_underflow_T_18; // @[RoundAnyRawFNToRecFN.scala:217:40]
wire common_underflow; // @[RoundAnyRawFNToRecFN.scala:126:37]
wire _common_inexact_T; // @[RoundAnyRawFNToRecFN.scala:230:49]
wire common_inexact; // @[RoundAnyRawFNToRecFN.scala:127:37]
wire [11:0] _roundMask_T = io_in_sExp_0[11:0]; // @[RoundAnyRawFNToRecFN.scala:48:5, :156:37]
wire [11:0] _roundMask_T_1 = ~_roundMask_T; // @[primitives.scala:52:21]
wire roundMask_msb = _roundMask_T_1[11]; // @[primitives.scala:52:21, :58:25]
wire [10:0] roundMask_lsbs = _roundMask_T_1[10:0]; // @[primitives.scala:52:21, :59:26]
wire roundMask_msb_1 = roundMask_lsbs[10]; // @[primitives.scala:58:25, :59:26]
wire [9:0] roundMask_lsbs_1 = roundMask_lsbs[9:0]; // @[primitives.scala:59:26]
wire roundMask_msb_2 = roundMask_lsbs_1[9]; // @[primitives.scala:58:25, :59:26]
wire roundMask_msb_6 = roundMask_lsbs_1[9]; // @[primitives.scala:58:25, :59:26]
wire [8:0] roundMask_lsbs_2 = roundMask_lsbs_1[8:0]; // @[primitives.scala:59:26]
wire [8:0] roundMask_lsbs_6 = roundMask_lsbs_1[8:0]; // @[primitives.scala:59:26]
wire roundMask_msb_3 = roundMask_lsbs_2[8]; // @[primitives.scala:58:25, :59:26]
wire [7:0] roundMask_lsbs_3 = roundMask_lsbs_2[7:0]; // @[primitives.scala:59:26]
wire roundMask_msb_4 = roundMask_lsbs_3[7]; // @[primitives.scala:58:25, :59:26]
wire [6:0] roundMask_lsbs_4 = roundMask_lsbs_3[6:0]; // @[primitives.scala:59:26]
wire roundMask_msb_5 = roundMask_lsbs_4[6]; // @[primitives.scala:58:25, :59:26]
wire [5:0] roundMask_lsbs_5 = roundMask_lsbs_4[5:0]; // @[primitives.scala:59:26]
wire [64:0] roundMask_shift = $signed(65'sh10000000000000000 >>> roundMask_lsbs_5); // @[primitives.scala:59:26, :76:56]
wire [50:0] _roundMask_T_2 = roundMask_shift[63:13]; // @[primitives.scala:76:56, :78:22]
wire [31:0] _roundMask_T_3 = _roundMask_T_2[31:0]; // @[primitives.scala:77:20, :78:22]
wire [15:0] _roundMask_T_6 = _roundMask_T_3[31:16]; // @[primitives.scala:77:20]
wire [31:0] _roundMask_T_7 = {16'h0, _roundMask_T_6}; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_8 = _roundMask_T_3[15:0]; // @[primitives.scala:77:20]
wire [31:0] _roundMask_T_9 = {_roundMask_T_8, 16'h0}; // @[primitives.scala:77:20]
wire [31:0] _roundMask_T_11 = _roundMask_T_9 & 32'hFFFF0000; // @[primitives.scala:77:20]
wire [31:0] _roundMask_T_12 = _roundMask_T_7 | _roundMask_T_11; // @[primitives.scala:77:20]
wire [23:0] _roundMask_T_16 = _roundMask_T_12[31:8]; // @[primitives.scala:77:20]
wire [31:0] _roundMask_T_17 = {8'h0, _roundMask_T_16 & 24'hFF00FF}; // @[primitives.scala:77:20]
wire [23:0] _roundMask_T_18 = _roundMask_T_12[23:0]; // @[primitives.scala:77:20]
wire [31:0] _roundMask_T_19 = {_roundMask_T_18, 8'h0}; // @[primitives.scala:77:20]
wire [31:0] _roundMask_T_21 = _roundMask_T_19 & 32'hFF00FF00; // @[primitives.scala:77:20]
wire [31:0] _roundMask_T_22 = _roundMask_T_17 | _roundMask_T_21; // @[primitives.scala:77:20]
wire [27:0] _roundMask_T_26 = _roundMask_T_22[31:4]; // @[primitives.scala:77:20]
wire [31:0] _roundMask_T_27 = {4'h0, _roundMask_T_26 & 28'hF0F0F0F}; // @[primitives.scala:77:20]
wire [27:0] _roundMask_T_28 = _roundMask_T_22[27:0]; // @[primitives.scala:77:20]
wire [31:0] _roundMask_T_29 = {_roundMask_T_28, 4'h0}; // @[primitives.scala:77:20]
wire [31:0] _roundMask_T_31 = _roundMask_T_29 & 32'hF0F0F0F0; // @[primitives.scala:77:20]
wire [31:0] _roundMask_T_32 = _roundMask_T_27 | _roundMask_T_31; // @[primitives.scala:77:20]
wire [29:0] _roundMask_T_36 = _roundMask_T_32[31:2]; // @[primitives.scala:77:20]
wire [31:0] _roundMask_T_37 = {2'h0, _roundMask_T_36 & 30'h33333333}; // @[primitives.scala:77:20]
wire [29:0] _roundMask_T_38 = _roundMask_T_32[29:0]; // @[primitives.scala:77:20]
wire [31:0] _roundMask_T_39 = {_roundMask_T_38, 2'h0}; // @[primitives.scala:77:20]
wire [31:0] _roundMask_T_41 = _roundMask_T_39 & 32'hCCCCCCCC; // @[primitives.scala:77:20]
wire [31:0] _roundMask_T_42 = _roundMask_T_37 | _roundMask_T_41; // @[primitives.scala:77:20]
wire [30:0] _roundMask_T_46 = _roundMask_T_42[31:1]; // @[primitives.scala:77:20]
wire [31:0] _roundMask_T_47 = {1'h0, _roundMask_T_46 & 31'h55555555}; // @[primitives.scala:77:20]
wire [30:0] _roundMask_T_48 = _roundMask_T_42[30:0]; // @[primitives.scala:77:20]
wire [31:0] _roundMask_T_49 = {_roundMask_T_48, 1'h0}; // @[primitives.scala:77:20]
wire [31:0] _roundMask_T_51 = _roundMask_T_49 & 32'hAAAAAAAA; // @[primitives.scala:77:20]
wire [31:0] _roundMask_T_52 = _roundMask_T_47 | _roundMask_T_51; // @[primitives.scala:77:20]
wire [18:0] _roundMask_T_53 = _roundMask_T_2[50:32]; // @[primitives.scala:77:20, :78:22]
wire [15:0] _roundMask_T_54 = _roundMask_T_53[15:0]; // @[primitives.scala:77:20]
wire [7:0] _roundMask_T_57 = _roundMask_T_54[15:8]; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_58 = {8'h0, _roundMask_T_57}; // @[primitives.scala:77:20]
wire [7:0] _roundMask_T_59 = _roundMask_T_54[7:0]; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_60 = {_roundMask_T_59, 8'h0}; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_62 = _roundMask_T_60 & 16'hFF00; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_63 = _roundMask_T_58 | _roundMask_T_62; // @[primitives.scala:77:20]
wire [11:0] _roundMask_T_67 = _roundMask_T_63[15:4]; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_68 = {4'h0, _roundMask_T_67 & 12'hF0F}; // @[primitives.scala:77:20]
wire [11:0] _roundMask_T_69 = _roundMask_T_63[11:0]; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_70 = {_roundMask_T_69, 4'h0}; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_72 = _roundMask_T_70 & 16'hF0F0; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_73 = _roundMask_T_68 | _roundMask_T_72; // @[primitives.scala:77:20]
wire [13:0] _roundMask_T_77 = _roundMask_T_73[15:2]; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_78 = {2'h0, _roundMask_T_77 & 14'h3333}; // @[primitives.scala:77:20]
wire [13:0] _roundMask_T_79 = _roundMask_T_73[13:0]; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_80 = {_roundMask_T_79, 2'h0}; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_82 = _roundMask_T_80 & 16'hCCCC; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_83 = _roundMask_T_78 | _roundMask_T_82; // @[primitives.scala:77:20]
wire [14:0] _roundMask_T_87 = _roundMask_T_83[15:1]; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_88 = {1'h0, _roundMask_T_87 & 15'h5555}; // @[primitives.scala:77:20]
wire [14:0] _roundMask_T_89 = _roundMask_T_83[14:0]; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_90 = {_roundMask_T_89, 1'h0}; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_92 = _roundMask_T_90 & 16'hAAAA; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_93 = _roundMask_T_88 | _roundMask_T_92; // @[primitives.scala:77:20]
wire [2:0] _roundMask_T_94 = _roundMask_T_53[18:16]; // @[primitives.scala:77:20]
wire [1:0] _roundMask_T_95 = _roundMask_T_94[1:0]; // @[primitives.scala:77:20]
wire _roundMask_T_96 = _roundMask_T_95[0]; // @[primitives.scala:77:20]
wire _roundMask_T_97 = _roundMask_T_95[1]; // @[primitives.scala:77:20]
wire [1:0] _roundMask_T_98 = {_roundMask_T_96, _roundMask_T_97}; // @[primitives.scala:77:20]
wire _roundMask_T_99 = _roundMask_T_94[2]; // @[primitives.scala:77:20]
wire [2:0] _roundMask_T_100 = {_roundMask_T_98, _roundMask_T_99}; // @[primitives.scala:77:20]
wire [18:0] _roundMask_T_101 = {_roundMask_T_93, _roundMask_T_100}; // @[primitives.scala:77:20]
wire [50:0] _roundMask_T_102 = {_roundMask_T_52, _roundMask_T_101}; // @[primitives.scala:77:20]
wire [50:0] _roundMask_T_103 = ~_roundMask_T_102; // @[primitives.scala:73:32, :77:20]
wire [50:0] _roundMask_T_104 = roundMask_msb_5 ? 51'h0 : _roundMask_T_103; // @[primitives.scala:58:25, :73:{21,32}]
wire [50:0] _roundMask_T_105 = ~_roundMask_T_104; // @[primitives.scala:73:{17,21}]
wire [50:0] _roundMask_T_106 = ~_roundMask_T_105; // @[primitives.scala:73:{17,32}]
wire [50:0] _roundMask_T_107 = roundMask_msb_4 ? 51'h0 : _roundMask_T_106; // @[primitives.scala:58:25, :73:{21,32}]
wire [50:0] _roundMask_T_108 = ~_roundMask_T_107; // @[primitives.scala:73:{17,21}]
wire [50:0] _roundMask_T_109 = ~_roundMask_T_108; // @[primitives.scala:73:{17,32}]
wire [50:0] _roundMask_T_110 = roundMask_msb_3 ? 51'h0 : _roundMask_T_109; // @[primitives.scala:58:25, :73:{21,32}]
wire [50:0] _roundMask_T_111 = ~_roundMask_T_110; // @[primitives.scala:73:{17,21}]
wire [50:0] _roundMask_T_112 = ~_roundMask_T_111; // @[primitives.scala:73:{17,32}]
wire [50:0] _roundMask_T_113 = roundMask_msb_2 ? 51'h0 : _roundMask_T_112; // @[primitives.scala:58:25, :73:{21,32}]
wire [50:0] _roundMask_T_114 = ~_roundMask_T_113; // @[primitives.scala:73:{17,21}]
wire [53:0] _roundMask_T_115 = {_roundMask_T_114, 3'h7}; // @[primitives.scala:68:58, :73:17]
wire roundMask_msb_7 = roundMask_lsbs_6[8]; // @[primitives.scala:58:25, :59:26]
wire [7:0] roundMask_lsbs_7 = roundMask_lsbs_6[7:0]; // @[primitives.scala:59:26]
wire roundMask_msb_8 = roundMask_lsbs_7[7]; // @[primitives.scala:58:25, :59:26]
wire [6:0] roundMask_lsbs_8 = roundMask_lsbs_7[6:0]; // @[primitives.scala:59:26]
wire roundMask_msb_9 = roundMask_lsbs_8[6]; // @[primitives.scala:58:25, :59:26]
wire [5:0] roundMask_lsbs_9 = roundMask_lsbs_8[5:0]; // @[primitives.scala:59:26]
wire [64:0] roundMask_shift_1 = $signed(65'sh10000000000000000 >>> roundMask_lsbs_9); // @[primitives.scala:59:26, :76:56]
wire [2:0] _roundMask_T_116 = roundMask_shift_1[2:0]; // @[primitives.scala:76:56, :78:22]
wire [1:0] _roundMask_T_117 = _roundMask_T_116[1:0]; // @[primitives.scala:77:20, :78:22]
wire _roundMask_T_118 = _roundMask_T_117[0]; // @[primitives.scala:77:20]
wire _roundMask_T_119 = _roundMask_T_117[1]; // @[primitives.scala:77:20]
wire [1:0] _roundMask_T_120 = {_roundMask_T_118, _roundMask_T_119}; // @[primitives.scala:77:20]
wire _roundMask_T_121 = _roundMask_T_116[2]; // @[primitives.scala:77:20, :78:22]
wire [2:0] _roundMask_T_122 = {_roundMask_T_120, _roundMask_T_121}; // @[primitives.scala:77:20]
wire [2:0] _roundMask_T_123 = roundMask_msb_9 ? _roundMask_T_122 : 3'h0; // @[primitives.scala:58:25, :62:24, :77:20]
wire [2:0] _roundMask_T_124 = roundMask_msb_8 ? _roundMask_T_123 : 3'h0; // @[primitives.scala:58:25, :62:24]
wire [2:0] _roundMask_T_125 = roundMask_msb_7 ? _roundMask_T_124 : 3'h0; // @[primitives.scala:58:25, :62:24]
wire [2:0] _roundMask_T_126 = roundMask_msb_6 ? _roundMask_T_125 : 3'h0; // @[primitives.scala:58:25, :62:24]
wire [53:0] _roundMask_T_127 = roundMask_msb_1 ? _roundMask_T_115 : {51'h0, _roundMask_T_126}; // @[primitives.scala:58:25, :62:24, :67:24, :68:58]
wire [53:0] _roundMask_T_128 = roundMask_msb ? _roundMask_T_127 : 54'h0; // @[primitives.scala:58:25, :62:24, :67:24]
wire [53:0] _roundMask_T_129 = {_roundMask_T_128[53:1], _roundMask_T_128[0] | doShiftSigDown1}; // @[primitives.scala:62:24]
wire [55:0] roundMask = {_roundMask_T_129, 2'h3}; // @[RoundAnyRawFNToRecFN.scala:159:{23,42}]
wire [56:0] _shiftedRoundMask_T = {1'h0, roundMask}; // @[RoundAnyRawFNToRecFN.scala:159:42, :162:41]
wire [55:0] shiftedRoundMask = _shiftedRoundMask_T[56:1]; // @[RoundAnyRawFNToRecFN.scala:162:{41,53}]
wire [55:0] _roundPosMask_T = ~shiftedRoundMask; // @[RoundAnyRawFNToRecFN.scala:162:53, :163:28]
wire [55:0] roundPosMask = _roundPosMask_T & roundMask; // @[RoundAnyRawFNToRecFN.scala:159:42, :163:{28,46}]
wire [55:0] _roundPosBit_T = adjustedSig & roundPosMask; // @[RoundAnyRawFNToRecFN.scala:114:22, :163:46, :164:40]
wire roundPosBit = |_roundPosBit_T; // @[RoundAnyRawFNToRecFN.scala:164:{40,56}]
wire [55:0] _anyRoundExtra_T = adjustedSig & shiftedRoundMask; // @[RoundAnyRawFNToRecFN.scala:114:22, :162:53, :165:42]
wire anyRoundExtra = |_anyRoundExtra_T; // @[RoundAnyRawFNToRecFN.scala:165:{42,62}]
wire anyRound = roundPosBit | anyRoundExtra; // @[RoundAnyRawFNToRecFN.scala:164:56, :165:62, :166:36]
wire _GEN = roundingMode_near_even | roundingMode_near_maxMag; // @[RoundAnyRawFNToRecFN.scala:90:53, :94:53, :169:38]
wire _roundIncr_T; // @[RoundAnyRawFNToRecFN.scala:169:38]
assign _roundIncr_T = _GEN; // @[RoundAnyRawFNToRecFN.scala:169:38]
wire _unboundedRange_roundIncr_T; // @[RoundAnyRawFNToRecFN.scala:207:38]
assign _unboundedRange_roundIncr_T = _GEN; // @[RoundAnyRawFNToRecFN.scala:169:38, :207:38]
wire _overflow_roundMagUp_T; // @[RoundAnyRawFNToRecFN.scala:243:32]
assign _overflow_roundMagUp_T = _GEN; // @[RoundAnyRawFNToRecFN.scala:169:38, :243:32]
wire _roundIncr_T_1 = _roundIncr_T & roundPosBit; // @[RoundAnyRawFNToRecFN.scala:164:56, :169:{38,67}]
wire _roundIncr_T_2 = roundMagUp & anyRound; // @[RoundAnyRawFNToRecFN.scala:98:42, :166:36, :171:29]
wire roundIncr = _roundIncr_T_1 | _roundIncr_T_2; // @[RoundAnyRawFNToRecFN.scala:169:67, :170:31, :171:29]
wire [55:0] _roundedSig_T = adjustedSig | roundMask; // @[RoundAnyRawFNToRecFN.scala:114:22, :159:42, :174:32]
wire [53:0] _roundedSig_T_1 = _roundedSig_T[55:2]; // @[RoundAnyRawFNToRecFN.scala:174:{32,44}]
wire [54:0] _roundedSig_T_2 = {1'h0, _roundedSig_T_1} + 55'h1; // @[RoundAnyRawFNToRecFN.scala:174:{44,49}]
wire _roundedSig_T_3 = roundingMode_near_even & roundPosBit; // @[RoundAnyRawFNToRecFN.scala:90:53, :164:56, :175:49]
wire _roundedSig_T_4 = ~anyRoundExtra; // @[RoundAnyRawFNToRecFN.scala:165:62, :176:30]
wire _roundedSig_T_5 = _roundedSig_T_3 & _roundedSig_T_4; // @[RoundAnyRawFNToRecFN.scala:175:{49,64}, :176:30]
wire [54:0] _roundedSig_T_6 = roundMask[55:1]; // @[RoundAnyRawFNToRecFN.scala:159:42, :177:35]
wire [54:0] _roundedSig_T_7 = _roundedSig_T_5 ? _roundedSig_T_6 : 55'h0; // @[RoundAnyRawFNToRecFN.scala:175:{25,64}, :177:35]
wire [54:0] _roundedSig_T_8 = ~_roundedSig_T_7; // @[RoundAnyRawFNToRecFN.scala:175:{21,25}]
wire [54:0] _roundedSig_T_9 = _roundedSig_T_2 & _roundedSig_T_8; // @[RoundAnyRawFNToRecFN.scala:174:{49,57}, :175:21]
wire [55:0] _roundedSig_T_10 = ~roundMask; // @[RoundAnyRawFNToRecFN.scala:159:42, :180:32]
wire [55:0] _roundedSig_T_11 = adjustedSig & _roundedSig_T_10; // @[RoundAnyRawFNToRecFN.scala:114:22, :180:{30,32}]
wire [53:0] _roundedSig_T_12 = _roundedSig_T_11[55:2]; // @[RoundAnyRawFNToRecFN.scala:180:{30,43}]
wire _roundedSig_T_13 = roundingMode_odd & anyRound; // @[RoundAnyRawFNToRecFN.scala:95:53, :166:36, :181:42]
wire [54:0] _roundedSig_T_14 = roundPosMask[55:1]; // @[RoundAnyRawFNToRecFN.scala:163:46, :181:67]
wire [54:0] _roundedSig_T_15 = _roundedSig_T_13 ? _roundedSig_T_14 : 55'h0; // @[RoundAnyRawFNToRecFN.scala:181:{24,42,67}]
wire [54:0] _roundedSig_T_16 = {1'h0, _roundedSig_T_12} | _roundedSig_T_15; // @[RoundAnyRawFNToRecFN.scala:180:{43,47}, :181:24]
wire [54:0] roundedSig = roundIncr ? _roundedSig_T_9 : _roundedSig_T_16; // @[RoundAnyRawFNToRecFN.scala:170:31, :173:16, :174:57, :180:47]
wire [1:0] _sRoundedExp_T = roundedSig[54:53]; // @[RoundAnyRawFNToRecFN.scala:173:16, :185:54]
wire [2:0] _sRoundedExp_T_1 = {1'h0, _sRoundedExp_T}; // @[RoundAnyRawFNToRecFN.scala:185:{54,76}]
wire [13:0] sRoundedExp = {io_in_sExp_0[12], io_in_sExp_0} + {{11{_sRoundedExp_T_1[2]}}, _sRoundedExp_T_1}; // @[RoundAnyRawFNToRecFN.scala:48:5, :185:{40,76}]
assign _common_expOut_T = sRoundedExp[11:0]; // @[RoundAnyRawFNToRecFN.scala:185:40, :187:37]
assign common_expOut = _common_expOut_T; // @[RoundAnyRawFNToRecFN.scala:122:31, :187:37]
wire [51:0] _common_fractOut_T = roundedSig[52:1]; // @[RoundAnyRawFNToRecFN.scala:173:16, :190:27]
wire [51:0] _common_fractOut_T_1 = roundedSig[51:0]; // @[RoundAnyRawFNToRecFN.scala:173:16, :191:27]
assign _common_fractOut_T_2 = doShiftSigDown1 ? _common_fractOut_T : _common_fractOut_T_1; // @[RoundAnyRawFNToRecFN.scala:120:57, :189:16, :190:27, :191:27]
assign common_fractOut = _common_fractOut_T_2; // @[RoundAnyRawFNToRecFN.scala:123:31, :189:16]
wire [3:0] _common_overflow_T = sRoundedExp[13:10]; // @[RoundAnyRawFNToRecFN.scala:185:40, :196:30]
assign _common_overflow_T_1 = $signed(_common_overflow_T) > 4'sh2; // @[RoundAnyRawFNToRecFN.scala:196:{30,50}]
assign common_overflow = _common_overflow_T_1; // @[RoundAnyRawFNToRecFN.scala:124:37, :196:50]
assign _common_totalUnderflow_T = $signed(sRoundedExp) < 14'sh3CE; // @[RoundAnyRawFNToRecFN.scala:185:40, :200:31]
assign common_totalUnderflow = _common_totalUnderflow_T; // @[RoundAnyRawFNToRecFN.scala:125:37, :200:31]
wire _unboundedRange_roundPosBit_T = adjustedSig[2]; // @[RoundAnyRawFNToRecFN.scala:114:22, :203:45]
wire _unboundedRange_anyRound_T = adjustedSig[2]; // @[RoundAnyRawFNToRecFN.scala:114:22, :203:45, :205:44]
wire _unboundedRange_roundPosBit_T_1 = adjustedSig[1]; // @[RoundAnyRawFNToRecFN.scala:114:22, :203:61]
wire unboundedRange_roundPosBit = doShiftSigDown1 ? _unboundedRange_roundPosBit_T : _unboundedRange_roundPosBit_T_1; // @[RoundAnyRawFNToRecFN.scala:120:57, :203:{16,45,61}]
wire _unboundedRange_anyRound_T_1 = doShiftSigDown1 & _unboundedRange_anyRound_T; // @[RoundAnyRawFNToRecFN.scala:120:57, :205:{30,44}]
wire [1:0] _unboundedRange_anyRound_T_2 = adjustedSig[1:0]; // @[RoundAnyRawFNToRecFN.scala:114:22, :205:63]
wire _unboundedRange_anyRound_T_3 = |_unboundedRange_anyRound_T_2; // @[RoundAnyRawFNToRecFN.scala:205:{63,70}]
wire unboundedRange_anyRound = _unboundedRange_anyRound_T_1 | _unboundedRange_anyRound_T_3; // @[RoundAnyRawFNToRecFN.scala:205:{30,49,70}]
wire _unboundedRange_roundIncr_T_1 = _unboundedRange_roundIncr_T & unboundedRange_roundPosBit; // @[RoundAnyRawFNToRecFN.scala:203:16, :207:{38,67}]
wire _unboundedRange_roundIncr_T_2 = roundMagUp & unboundedRange_anyRound; // @[RoundAnyRawFNToRecFN.scala:98:42, :205:49, :209:29]
wire unboundedRange_roundIncr = _unboundedRange_roundIncr_T_1 | _unboundedRange_roundIncr_T_2; // @[RoundAnyRawFNToRecFN.scala:207:67, :208:46, :209:29]
wire _roundCarry_T = roundedSig[54]; // @[RoundAnyRawFNToRecFN.scala:173:16, :212:27]
wire _roundCarry_T_1 = roundedSig[53]; // @[RoundAnyRawFNToRecFN.scala:173:16, :213:27]
wire roundCarry = doShiftSigDown1 ? _roundCarry_T : _roundCarry_T_1; // @[RoundAnyRawFNToRecFN.scala:120:57, :211:16, :212:27, :213:27]
wire [1:0] _common_underflow_T = io_in_sExp_0[12:11]; // @[RoundAnyRawFNToRecFN.scala:48:5, :220:49]
wire _common_underflow_T_1 = _common_underflow_T != 2'h1; // @[RoundAnyRawFNToRecFN.scala:220:{49,64}]
wire _common_underflow_T_2 = anyRound & _common_underflow_T_1; // @[RoundAnyRawFNToRecFN.scala:166:36, :220:{32,64}]
wire _common_underflow_T_3 = roundMask[3]; // @[RoundAnyRawFNToRecFN.scala:159:42, :221:57]
wire _common_underflow_T_9 = roundMask[3]; // @[RoundAnyRawFNToRecFN.scala:159:42, :221:57, :225:49]
wire _common_underflow_T_4 = roundMask[2]; // @[RoundAnyRawFNToRecFN.scala:159:42, :221:71]
wire _common_underflow_T_5 = doShiftSigDown1 ? _common_underflow_T_3 : _common_underflow_T_4; // @[RoundAnyRawFNToRecFN.scala:120:57, :221:{30,57,71}]
wire _common_underflow_T_6 = _common_underflow_T_2 & _common_underflow_T_5; // @[RoundAnyRawFNToRecFN.scala:220:{32,72}, :221:30]
wire _common_underflow_T_8 = roundMask[4]; // @[RoundAnyRawFNToRecFN.scala:159:42, :224:49]
wire _common_underflow_T_10 = doShiftSigDown1 ? _common_underflow_T_8 : _common_underflow_T_9; // @[RoundAnyRawFNToRecFN.scala:120:57, :223:39, :224:49, :225:49]
wire _common_underflow_T_11 = ~_common_underflow_T_10; // @[RoundAnyRawFNToRecFN.scala:223:{34,39}]
wire _common_underflow_T_12 = _common_underflow_T_11; // @[RoundAnyRawFNToRecFN.scala:222:77, :223:34]
wire _common_underflow_T_13 = _common_underflow_T_12 & roundCarry; // @[RoundAnyRawFNToRecFN.scala:211:16, :222:77, :226:38]
wire _common_underflow_T_14 = _common_underflow_T_13 & roundPosBit; // @[RoundAnyRawFNToRecFN.scala:164:56, :226:38, :227:45]
wire _common_underflow_T_15 = _common_underflow_T_14 & unboundedRange_roundIncr; // @[RoundAnyRawFNToRecFN.scala:208:46, :227:{45,60}]
wire _common_underflow_T_16 = ~_common_underflow_T_15; // @[RoundAnyRawFNToRecFN.scala:222:27, :227:60]
wire _common_underflow_T_17 = _common_underflow_T_6 & _common_underflow_T_16; // @[RoundAnyRawFNToRecFN.scala:220:72, :221:76, :222:27]
assign _common_underflow_T_18 = common_totalUnderflow | _common_underflow_T_17; // @[RoundAnyRawFNToRecFN.scala:125:37, :217:40, :221:76]
assign common_underflow = _common_underflow_T_18; // @[RoundAnyRawFNToRecFN.scala:126:37, :217:40]
assign _common_inexact_T = common_totalUnderflow | anyRound; // @[RoundAnyRawFNToRecFN.scala:125:37, :166:36, :230:49]
assign common_inexact = _common_inexact_T; // @[RoundAnyRawFNToRecFN.scala:127:37, :230:49]
wire isNaNOut = io_invalidExc_0 | io_in_isNaN_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :235:34]
wire notNaN_isSpecialInfOut = io_infiniteExc_0 | io_in_isInf_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :236:49]
wire _commonCase_T = ~isNaNOut; // @[RoundAnyRawFNToRecFN.scala:235:34, :237:22]
wire _commonCase_T_1 = ~notNaN_isSpecialInfOut; // @[RoundAnyRawFNToRecFN.scala:236:49, :237:36]
wire _commonCase_T_2 = _commonCase_T & _commonCase_T_1; // @[RoundAnyRawFNToRecFN.scala:237:{22,33,36}]
wire _commonCase_T_3 = ~io_in_isZero_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :237:64]
wire commonCase = _commonCase_T_2 & _commonCase_T_3; // @[RoundAnyRawFNToRecFN.scala:237:{33,61,64}]
wire overflow = commonCase & common_overflow; // @[RoundAnyRawFNToRecFN.scala:124:37, :237:61, :238:32]
wire underflow = commonCase & common_underflow; // @[RoundAnyRawFNToRecFN.scala:126:37, :237:61, :239:32]
wire _inexact_T = commonCase & common_inexact; // @[RoundAnyRawFNToRecFN.scala:127:37, :237:61, :240:43]
wire inexact = overflow | _inexact_T; // @[RoundAnyRawFNToRecFN.scala:238:32, :240:{28,43}]
wire overflow_roundMagUp = _overflow_roundMagUp_T | roundMagUp; // @[RoundAnyRawFNToRecFN.scala:98:42, :243:{32,60}]
wire _pegMinNonzeroMagOut_T = commonCase & common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:125:37, :237:61, :245:20]
wire _pegMinNonzeroMagOut_T_1 = roundMagUp | roundingMode_odd; // @[RoundAnyRawFNToRecFN.scala:95:53, :98:42, :245:60]
wire pegMinNonzeroMagOut = _pegMinNonzeroMagOut_T & _pegMinNonzeroMagOut_T_1; // @[RoundAnyRawFNToRecFN.scala:245:{20,45,60}]
wire _pegMaxFiniteMagOut_T = ~overflow_roundMagUp; // @[RoundAnyRawFNToRecFN.scala:243:60, :246:42]
wire pegMaxFiniteMagOut = overflow & _pegMaxFiniteMagOut_T; // @[RoundAnyRawFNToRecFN.scala:238:32, :246:{39,42}]
wire _notNaN_isInfOut_T = overflow & overflow_roundMagUp; // @[RoundAnyRawFNToRecFN.scala:238:32, :243:60, :248:45]
wire notNaN_isInfOut = notNaN_isSpecialInfOut | _notNaN_isInfOut_T; // @[RoundAnyRawFNToRecFN.scala:236:49, :248:{32,45}]
wire signOut = ~isNaNOut & io_in_sign_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :235:34, :250:22]
wire _expOut_T = io_in_isZero_0 | common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:48:5, :125:37, :253:32]
wire [11:0] _expOut_T_1 = _expOut_T ? 12'hE00 : 12'h0; // @[RoundAnyRawFNToRecFN.scala:253:{18,32}]
wire [11:0] _expOut_T_2 = ~_expOut_T_1; // @[RoundAnyRawFNToRecFN.scala:253:{14,18}]
wire [11:0] _expOut_T_3 = common_expOut & _expOut_T_2; // @[RoundAnyRawFNToRecFN.scala:122:31, :252:24, :253:14]
wire [11:0] _expOut_T_5 = pegMinNonzeroMagOut ? 12'hC31 : 12'h0; // @[RoundAnyRawFNToRecFN.scala:245:45, :257:18]
wire [11:0] _expOut_T_6 = ~_expOut_T_5; // @[RoundAnyRawFNToRecFN.scala:257:{14,18}]
wire [11:0] _expOut_T_7 = _expOut_T_3 & _expOut_T_6; // @[RoundAnyRawFNToRecFN.scala:252:24, :256:17, :257:14]
wire [11:0] _expOut_T_8 = {1'h0, pegMaxFiniteMagOut, 10'h0}; // @[RoundAnyRawFNToRecFN.scala:246:39, :261:18]
wire [11:0] _expOut_T_9 = ~_expOut_T_8; // @[RoundAnyRawFNToRecFN.scala:261:{14,18}]
wire [11:0] _expOut_T_10 = _expOut_T_7 & _expOut_T_9; // @[RoundAnyRawFNToRecFN.scala:256:17, :260:17, :261:14]
wire [11:0] _expOut_T_11 = {2'h0, notNaN_isInfOut, 9'h0}; // @[RoundAnyRawFNToRecFN.scala:248:32, :265:18]
wire [11:0] _expOut_T_12 = ~_expOut_T_11; // @[RoundAnyRawFNToRecFN.scala:265:{14,18}]
wire [11:0] _expOut_T_13 = _expOut_T_10 & _expOut_T_12; // @[RoundAnyRawFNToRecFN.scala:260:17, :264:17, :265:14]
wire [11:0] _expOut_T_14 = pegMinNonzeroMagOut ? 12'h3CE : 12'h0; // @[RoundAnyRawFNToRecFN.scala:245:45, :269:16]
wire [11:0] _expOut_T_15 = _expOut_T_13 | _expOut_T_14; // @[RoundAnyRawFNToRecFN.scala:264:17, :268:18, :269:16]
wire [11:0] _expOut_T_16 = pegMaxFiniteMagOut ? 12'hBFF : 12'h0; // @[RoundAnyRawFNToRecFN.scala:246:39, :273:16]
wire [11:0] _expOut_T_17 = _expOut_T_15 | _expOut_T_16; // @[RoundAnyRawFNToRecFN.scala:268:18, :272:15, :273:16]
wire [11:0] _expOut_T_18 = notNaN_isInfOut ? 12'hC00 : 12'h0; // @[RoundAnyRawFNToRecFN.scala:248:32, :277:16]
wire [11:0] _expOut_T_19 = _expOut_T_17 | _expOut_T_18; // @[RoundAnyRawFNToRecFN.scala:272:15, :276:15, :277:16]
wire [11:0] _expOut_T_20 = isNaNOut ? 12'hE00 : 12'h0; // @[RoundAnyRawFNToRecFN.scala:235:34, :278:16]
wire [11:0] expOut = _expOut_T_19 | _expOut_T_20; // @[RoundAnyRawFNToRecFN.scala:276:15, :277:73, :278:16]
wire _fractOut_T = isNaNOut | io_in_isZero_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :235:34, :280:22]
wire _fractOut_T_1 = _fractOut_T | common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:125:37, :280:{22,38}]
wire [51:0] _fractOut_T_2 = {isNaNOut, 51'h0}; // @[RoundAnyRawFNToRecFN.scala:235:34, :281:16]
wire [51:0] _fractOut_T_3 = _fractOut_T_1 ? _fractOut_T_2 : common_fractOut; // @[RoundAnyRawFNToRecFN.scala:123:31, :280:{12,38}, :281:16]
wire [51:0] _fractOut_T_4 = {52{pegMaxFiniteMagOut}}; // @[RoundAnyRawFNToRecFN.scala:246:39, :284:13]
wire [51:0] fractOut = _fractOut_T_3 | _fractOut_T_4; // @[RoundAnyRawFNToRecFN.scala:280:12, :283:11, :284:13]
wire [12:0] _io_out_T = {signOut, expOut}; // @[RoundAnyRawFNToRecFN.scala:250:22, :277:73, :286:23]
assign _io_out_T_1 = {_io_out_T, fractOut}; // @[RoundAnyRawFNToRecFN.scala:283:11, :286:{23,33}]
assign io_out_0 = _io_out_T_1; // @[RoundAnyRawFNToRecFN.scala:48:5, :286:33]
wire [1:0] _io_exceptionFlags_T = {io_invalidExc_0, io_infiniteExc_0}; // @[RoundAnyRawFNToRecFN.scala:48:5, :288:23]
wire [2:0] _io_exceptionFlags_T_1 = {_io_exceptionFlags_T, overflow}; // @[RoundAnyRawFNToRecFN.scala:238:32, :288:{23,41}]
wire [3:0] _io_exceptionFlags_T_2 = {_io_exceptionFlags_T_1, underflow}; // @[RoundAnyRawFNToRecFN.scala:239:32, :288:{41,53}]
assign _io_exceptionFlags_T_3 = {_io_exceptionFlags_T_2, inexact}; // @[RoundAnyRawFNToRecFN.scala:240:28, :288:{53,66}]
assign io_exceptionFlags_0 = _io_exceptionFlags_T_3; // @[RoundAnyRawFNToRecFN.scala:48:5, :288:66]
assign io_out = io_out_0; // @[RoundAnyRawFNToRecFN.scala:48:5]
assign io_exceptionFlags = io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:48:5]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File package.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip
import chisel3._
import chisel3.util._
import scala.math.min
import scala.collection.{immutable, mutable}
package object util {
implicit class UnzippableOption[S, T](val x: Option[(S, T)]) {
def unzip = (x.map(_._1), x.map(_._2))
}
implicit class UIntIsOneOf(private val x: UInt) extends AnyVal {
def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR
def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq)
}
implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal {
/** Like Vec.apply(idx), but tolerates indices of mismatched width */
def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0))
}
implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal {
def apply(idx: UInt): T = {
if (x.size <= 1) {
x.head
} else if (!isPow2(x.size)) {
// For non-power-of-2 seqs, reflect elements to simplify decoder
(x ++ x.takeRight(x.size & -x.size)).toSeq(idx)
} else {
// Ignore MSBs of idx
val truncIdx =
if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx
else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0)
x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) }
}
}
def extract(idx: UInt): T = VecInit(x).extract(idx)
def asUInt: UInt = Cat(x.map(_.asUInt).reverse)
def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n)
def rotate(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n)
def rotateRight(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
}
// allow bitwise ops on Seq[Bool] just like UInt
implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal {
def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b }
def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b }
def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b }
def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x
def >> (n: Int): Seq[Bool] = x drop n
def unary_~ : Seq[Bool] = x.map(!_)
def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_)
def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_)
def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_)
private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B)
}
implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal {
def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable))
def getElements: Seq[Element] = x match {
case e: Element => Seq(e)
case a: Aggregate => a.getElements.flatMap(_.getElements)
}
}
/** Any Data subtype that has a Bool member named valid. */
type DataCanBeValid = Data { val valid: Bool }
implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal {
def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable)
}
implicit class StringToAugmentedString(private val x: String) extends AnyVal {
/** converts from camel case to to underscores, also removing all spaces */
def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") {
case (acc, c) if c.isUpper => acc + "_" + c.toLower
case (acc, c) if c == ' ' => acc
case (acc, c) => acc + c
}
/** converts spaces or underscores to hyphens, also lowering case */
def kebab: String = x.toLowerCase map {
case ' ' => '-'
case '_' => '-'
case c => c
}
def named(name: Option[String]): String = {
x + name.map("_named_" + _ ).getOrElse("_with_no_name")
}
def named(name: String): String = named(Some(name))
}
implicit def uintToBitPat(x: UInt): BitPat = BitPat(x)
implicit def wcToUInt(c: WideCounter): UInt = c.value
implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal {
def sextTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x)
}
def padTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(0.U((n - x.getWidth).W), x)
}
// shifts left by n if n >= 0, or right by -n if n < 0
def << (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << n(w-1, 0)
Mux(n(w), shifted >> (1 << w), shifted)
}
// shifts right by n if n >= 0, or left by -n if n < 0
def >> (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << (1 << w) >> n(w-1, 0)
Mux(n(w), shifted, shifted >> (1 << w))
}
// Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts
def extract(hi: Int, lo: Int): UInt = {
require(hi >= lo-1)
if (hi == lo-1) 0.U
else x(hi, lo)
}
// Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts
def extractOption(hi: Int, lo: Int): Option[UInt] = {
require(hi >= lo-1)
if (hi == lo-1) None
else Some(x(hi, lo))
}
// like x & ~y, but first truncate or zero-extend y to x's width
def andNot(y: UInt): UInt = x & ~(y | (x & 0.U))
def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n)
def rotateRight(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r))
}
}
def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n))
def rotateLeft(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r))
}
}
// compute (this + y) % n, given (this < n) and (y < n)
def addWrap(y: UInt, n: Int): UInt = {
val z = x +& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0)
}
// compute (this - y) % n, given (this < n) and (y < n)
def subWrap(y: UInt, n: Int): UInt = {
val z = x -& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0)
}
def grouped(width: Int): Seq[UInt] =
(0 until x.getWidth by width).map(base => x(base + width - 1, base))
def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds
def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x)
// Like >=, but prevents x-prop for ('x >= 0)
def >== (y: UInt): Bool = x >= y || y === 0.U
}
implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal {
def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y)
def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y)
}
implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal {
def toInt: Int = if (x) 1 else 0
// this one's snagged from scalaz
def option[T](z: => T): Option[T] = if (x) Some(z) else None
}
implicit class IntToAugmentedInt(private val x: Int) extends AnyVal {
// exact log2
def log2: Int = {
require(isPow2(x))
log2Ceil(x)
}
}
def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x)
def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x))
def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0)
def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1)
def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None
// Fill 1s from low bits to high bits
def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth)
def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0))
helper(1, x)(width-1, 0)
}
// Fill 1s form high bits to low bits
def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth)
def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x >> s))
helper(1, x)(width-1, 0)
}
def OptimizationBarrier[T <: Data](in: T): T = {
val barrier = Module(new Module {
val io = IO(new Bundle {
val x = Input(chiselTypeOf(in))
val y = Output(chiselTypeOf(in))
})
io.y := io.x
override def desiredName = s"OptimizationBarrier_${in.typeName}"
})
barrier.io.x := in
barrier.io.y
}
/** Similar to Seq.groupBy except this returns a Seq instead of a Map
* Useful for deterministic code generation
*/
def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = {
val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]]
for (x <- xs) {
val key = f(x)
val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A])
l += x
}
map.view.map({ case (k, vs) => k -> vs.toList }).toList
}
def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match {
case 1 => List.fill(n)(in.head)
case x if x == n => in
case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in")
}
// HeterogeneousBag moved to standalond diplomacy
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts)
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag
}
| module OptimizationBarrier_TLBEntryData_93( // @[package.scala:267:30]
input clock, // @[package.scala:267:30]
input reset, // @[package.scala:267:30]
input [19:0] io_x_ppn, // @[package.scala:268:18]
input io_x_u, // @[package.scala:268:18]
input io_x_g, // @[package.scala:268:18]
input io_x_ae_ptw, // @[package.scala:268:18]
input io_x_ae_final, // @[package.scala:268:18]
input io_x_ae_stage2, // @[package.scala:268:18]
input io_x_pf, // @[package.scala:268:18]
input io_x_gf, // @[package.scala:268:18]
input io_x_sw, // @[package.scala:268:18]
input io_x_sx, // @[package.scala:268:18]
input io_x_sr, // @[package.scala:268:18]
input io_x_hw, // @[package.scala:268:18]
input io_x_hx, // @[package.scala:268:18]
input io_x_hr, // @[package.scala:268:18]
input io_x_pw, // @[package.scala:268:18]
input io_x_px, // @[package.scala:268:18]
input io_x_pr, // @[package.scala:268:18]
input io_x_ppp, // @[package.scala:268:18]
input io_x_pal, // @[package.scala:268:18]
input io_x_paa, // @[package.scala:268:18]
input io_x_eff, // @[package.scala:268:18]
input io_x_c, // @[package.scala:268:18]
input io_x_fragmented_superpage, // @[package.scala:268:18]
output [19:0] io_y_ppn, // @[package.scala:268:18]
output io_y_u, // @[package.scala:268:18]
output io_y_ae_ptw, // @[package.scala:268:18]
output io_y_ae_final, // @[package.scala:268:18]
output io_y_ae_stage2, // @[package.scala:268:18]
output io_y_pf, // @[package.scala:268:18]
output io_y_gf, // @[package.scala:268:18]
output io_y_sw, // @[package.scala:268:18]
output io_y_sx, // @[package.scala:268:18]
output io_y_sr, // @[package.scala:268:18]
output io_y_hw, // @[package.scala:268:18]
output io_y_hx, // @[package.scala:268:18]
output io_y_hr, // @[package.scala:268:18]
output io_y_pw, // @[package.scala:268:18]
output io_y_px, // @[package.scala:268:18]
output io_y_pr, // @[package.scala:268:18]
output io_y_ppp, // @[package.scala:268:18]
output io_y_pal, // @[package.scala:268:18]
output io_y_paa, // @[package.scala:268:18]
output io_y_eff, // @[package.scala:268:18]
output io_y_c // @[package.scala:268:18]
);
wire [19:0] io_x_ppn_0 = io_x_ppn; // @[package.scala:267:30]
wire io_x_u_0 = io_x_u; // @[package.scala:267:30]
wire io_x_g_0 = io_x_g; // @[package.scala:267:30]
wire io_x_ae_ptw_0 = io_x_ae_ptw; // @[package.scala:267:30]
wire io_x_ae_final_0 = io_x_ae_final; // @[package.scala:267:30]
wire io_x_ae_stage2_0 = io_x_ae_stage2; // @[package.scala:267:30]
wire io_x_pf_0 = io_x_pf; // @[package.scala:267:30]
wire io_x_gf_0 = io_x_gf; // @[package.scala:267:30]
wire io_x_sw_0 = io_x_sw; // @[package.scala:267:30]
wire io_x_sx_0 = io_x_sx; // @[package.scala:267:30]
wire io_x_sr_0 = io_x_sr; // @[package.scala:267:30]
wire io_x_hw_0 = io_x_hw; // @[package.scala:267:30]
wire io_x_hx_0 = io_x_hx; // @[package.scala:267:30]
wire io_x_hr_0 = io_x_hr; // @[package.scala:267:30]
wire io_x_pw_0 = io_x_pw; // @[package.scala:267:30]
wire io_x_px_0 = io_x_px; // @[package.scala:267:30]
wire io_x_pr_0 = io_x_pr; // @[package.scala:267:30]
wire io_x_ppp_0 = io_x_ppp; // @[package.scala:267:30]
wire io_x_pal_0 = io_x_pal; // @[package.scala:267:30]
wire io_x_paa_0 = io_x_paa; // @[package.scala:267:30]
wire io_x_eff_0 = io_x_eff; // @[package.scala:267:30]
wire io_x_c_0 = io_x_c; // @[package.scala:267:30]
wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage; // @[package.scala:267:30]
wire [19:0] io_y_ppn_0 = io_x_ppn_0; // @[package.scala:267:30]
wire io_y_u_0 = io_x_u_0; // @[package.scala:267:30]
wire io_y_g = io_x_g_0; // @[package.scala:267:30]
wire io_y_ae_ptw_0 = io_x_ae_ptw_0; // @[package.scala:267:30]
wire io_y_ae_final_0 = io_x_ae_final_0; // @[package.scala:267:30]
wire io_y_ae_stage2_0 = io_x_ae_stage2_0; // @[package.scala:267:30]
wire io_y_pf_0 = io_x_pf_0; // @[package.scala:267:30]
wire io_y_gf_0 = io_x_gf_0; // @[package.scala:267:30]
wire io_y_sw_0 = io_x_sw_0; // @[package.scala:267:30]
wire io_y_sx_0 = io_x_sx_0; // @[package.scala:267:30]
wire io_y_sr_0 = io_x_sr_0; // @[package.scala:267:30]
wire io_y_hw_0 = io_x_hw_0; // @[package.scala:267:30]
wire io_y_hx_0 = io_x_hx_0; // @[package.scala:267:30]
wire io_y_hr_0 = io_x_hr_0; // @[package.scala:267:30]
wire io_y_pw_0 = io_x_pw_0; // @[package.scala:267:30]
wire io_y_px_0 = io_x_px_0; // @[package.scala:267:30]
wire io_y_pr_0 = io_x_pr_0; // @[package.scala:267:30]
wire io_y_ppp_0 = io_x_ppp_0; // @[package.scala:267:30]
wire io_y_pal_0 = io_x_pal_0; // @[package.scala:267:30]
wire io_y_paa_0 = io_x_paa_0; // @[package.scala:267:30]
wire io_y_eff_0 = io_x_eff_0; // @[package.scala:267:30]
wire io_y_c_0 = io_x_c_0; // @[package.scala:267:30]
wire io_y_fragmented_superpage = io_x_fragmented_superpage_0; // @[package.scala:267:30]
assign io_y_ppn = io_y_ppn_0; // @[package.scala:267:30]
assign io_y_u = io_y_u_0; // @[package.scala:267:30]
assign io_y_ae_ptw = io_y_ae_ptw_0; // @[package.scala:267:30]
assign io_y_ae_final = io_y_ae_final_0; // @[package.scala:267:30]
assign io_y_ae_stage2 = io_y_ae_stage2_0; // @[package.scala:267:30]
assign io_y_pf = io_y_pf_0; // @[package.scala:267:30]
assign io_y_gf = io_y_gf_0; // @[package.scala:267:30]
assign io_y_sw = io_y_sw_0; // @[package.scala:267:30]
assign io_y_sx = io_y_sx_0; // @[package.scala:267:30]
assign io_y_sr = io_y_sr_0; // @[package.scala:267:30]
assign io_y_hw = io_y_hw_0; // @[package.scala:267:30]
assign io_y_hx = io_y_hx_0; // @[package.scala:267:30]
assign io_y_hr = io_y_hr_0; // @[package.scala:267:30]
assign io_y_pw = io_y_pw_0; // @[package.scala:267:30]
assign io_y_px = io_y_px_0; // @[package.scala:267:30]
assign io_y_pr = io_y_pr_0; // @[package.scala:267:30]
assign io_y_ppp = io_y_ppp_0; // @[package.scala:267:30]
assign io_y_pal = io_y_pal_0; // @[package.scala:267:30]
assign io_y_paa = io_y_paa_0; // @[package.scala:267:30]
assign io_y_eff = io_y_eff_0; // @[package.scala:267:30]
assign io_y_c = io_y_c_0; // @[package.scala:267:30]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File PE.scala:
// See README.md for license details.
package gemmini
import chisel3._
import chisel3.util._
class PEControl[T <: Data : Arithmetic](accType: T) extends Bundle {
val dataflow = UInt(1.W) // TODO make this an Enum
val propagate = UInt(1.W) // Which register should be propagated (and which should be accumulated)?
val shift = UInt(log2Up(accType.getWidth).W) // TODO this isn't correct for Floats
}
class MacUnit[T <: Data](inputType: T, cType: T, dType: T) (implicit ev: Arithmetic[T]) extends Module {
import ev._
val io = IO(new Bundle {
val in_a = Input(inputType)
val in_b = Input(inputType)
val in_c = Input(cType)
val out_d = Output(dType)
})
io.out_d := io.in_c.mac(io.in_a, io.in_b)
}
// TODO update documentation
/**
* A PE implementing a MAC operation. Configured as fully combinational when integrated into a Mesh.
* @param width Data width of operands
*/
class PE[T <: Data](inputType: T, outputType: T, accType: T, df: Dataflow.Value, max_simultaneous_matmuls: Int)
(implicit ev: Arithmetic[T]) extends Module { // Debugging variables
import ev._
val io = IO(new Bundle {
val in_a = Input(inputType)
val in_b = Input(outputType)
val in_d = Input(outputType)
val out_a = Output(inputType)
val out_b = Output(outputType)
val out_c = Output(outputType)
val in_control = Input(new PEControl(accType))
val out_control = Output(new PEControl(accType))
val in_id = Input(UInt(log2Up(max_simultaneous_matmuls).W))
val out_id = Output(UInt(log2Up(max_simultaneous_matmuls).W))
val in_last = Input(Bool())
val out_last = Output(Bool())
val in_valid = Input(Bool())
val out_valid = Output(Bool())
val bad_dataflow = Output(Bool())
})
val cType = if (df == Dataflow.WS) inputType else accType
// When creating PEs that support multiple dataflows, the
// elaboration/synthesis tools often fail to consolidate and de-duplicate
// MAC units. To force mac circuitry to be re-used, we create a "mac_unit"
// module here which just performs a single MAC operation
val mac_unit = Module(new MacUnit(inputType,
if (df == Dataflow.WS) outputType else accType, outputType))
val a = io.in_a
val b = io.in_b
val d = io.in_d
val c1 = Reg(cType)
val c2 = Reg(cType)
val dataflow = io.in_control.dataflow
val prop = io.in_control.propagate
val shift = io.in_control.shift
val id = io.in_id
val last = io.in_last
val valid = io.in_valid
io.out_a := a
io.out_control.dataflow := dataflow
io.out_control.propagate := prop
io.out_control.shift := shift
io.out_id := id
io.out_last := last
io.out_valid := valid
mac_unit.io.in_a := a
val last_s = RegEnable(prop, valid)
val flip = last_s =/= prop
val shift_offset = Mux(flip, shift, 0.U)
// Which dataflow are we using?
val OUTPUT_STATIONARY = Dataflow.OS.id.U(1.W)
val WEIGHT_STATIONARY = Dataflow.WS.id.U(1.W)
// Is c1 being computed on, or propagated forward (in the output-stationary dataflow)?
val COMPUTE = 0.U(1.W)
val PROPAGATE = 1.U(1.W)
io.bad_dataflow := false.B
when ((df == Dataflow.OS).B || ((df == Dataflow.BOTH).B && dataflow === OUTPUT_STATIONARY)) {
when(prop === PROPAGATE) {
io.out_c := (c1 >> shift_offset).clippedToWidthOf(outputType)
io.out_b := b
mac_unit.io.in_b := b.asTypeOf(inputType)
mac_unit.io.in_c := c2
c2 := mac_unit.io.out_d
c1 := d.withWidthOf(cType)
}.otherwise {
io.out_c := (c2 >> shift_offset).clippedToWidthOf(outputType)
io.out_b := b
mac_unit.io.in_b := b.asTypeOf(inputType)
mac_unit.io.in_c := c1
c1 := mac_unit.io.out_d
c2 := d.withWidthOf(cType)
}
}.elsewhen ((df == Dataflow.WS).B || ((df == Dataflow.BOTH).B && dataflow === WEIGHT_STATIONARY)) {
when(prop === PROPAGATE) {
io.out_c := c1
mac_unit.io.in_b := c2.asTypeOf(inputType)
mac_unit.io.in_c := b
io.out_b := mac_unit.io.out_d
c1 := d
}.otherwise {
io.out_c := c2
mac_unit.io.in_b := c1.asTypeOf(inputType)
mac_unit.io.in_c := b
io.out_b := mac_unit.io.out_d
c2 := d
}
}.otherwise {
io.bad_dataflow := true.B
//assert(false.B, "unknown dataflow")
io.out_c := DontCare
io.out_b := DontCare
mac_unit.io.in_b := b.asTypeOf(inputType)
mac_unit.io.in_c := c2
}
when (!valid) {
c1 := c1
c2 := c2
mac_unit.io.in_b := DontCare
mac_unit.io.in_c := DontCare
}
}
File Arithmetic.scala:
// A simple type class for Chisel datatypes that can add and multiply. To add your own type, simply create your own:
// implicit MyTypeArithmetic extends Arithmetic[MyType] { ... }
package gemmini
import chisel3._
import chisel3.util._
import hardfloat._
// Bundles that represent the raw bits of custom datatypes
case class Float(expWidth: Int, sigWidth: Int) extends Bundle {
val bits = UInt((expWidth + sigWidth).W)
val bias: Int = (1 << (expWidth-1)) - 1
}
case class DummySInt(w: Int) extends Bundle {
val bits = UInt(w.W)
def dontCare: DummySInt = {
val o = Wire(new DummySInt(w))
o.bits := 0.U
o
}
}
// The Arithmetic typeclass which implements various arithmetic operations on custom datatypes
abstract class Arithmetic[T <: Data] {
implicit def cast(t: T): ArithmeticOps[T]
}
abstract class ArithmeticOps[T <: Data](self: T) {
def *(t: T): T
def mac(m1: T, m2: T): T // Returns (m1 * m2 + self)
def +(t: T): T
def -(t: T): T
def >>(u: UInt): T // This is a rounding shift! Rounds away from 0
def >(t: T): Bool
def identity: T
def withWidthOf(t: T): T
def clippedToWidthOf(t: T): T // Like "withWidthOf", except that it saturates
def relu: T
def zero: T
def minimum: T
// Optional parameters, which only need to be defined if you want to enable various optimizations for transformers
def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[T])] = None
def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[T])] = None
def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = None
def mult_with_reciprocal[U <: Data](reciprocal: U) = self
}
object Arithmetic {
implicit object UIntArithmetic extends Arithmetic[UInt] {
override implicit def cast(self: UInt) = new ArithmeticOps(self) {
override def *(t: UInt) = self * t
override def mac(m1: UInt, m2: UInt) = m1 * m2 + self
override def +(t: UInt) = self + t
override def -(t: UInt) = self - t
override def >>(u: UInt) = {
// The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm
// TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here?
val point_five = Mux(u === 0.U, 0.U, self(u - 1.U))
val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U
val ones_digit = self(u)
val r = point_five & (zeros | ones_digit)
(self >> u).asUInt + r
}
override def >(t: UInt): Bool = self > t
override def withWidthOf(t: UInt) = self.asTypeOf(t)
override def clippedToWidthOf(t: UInt) = {
val sat = ((1 << (t.getWidth-1))-1).U
Mux(self > sat, sat, self)(t.getWidth-1, 0)
}
override def relu: UInt = self
override def zero: UInt = 0.U
override def identity: UInt = 1.U
override def minimum: UInt = 0.U
}
}
implicit object SIntArithmetic extends Arithmetic[SInt] {
override implicit def cast(self: SInt) = new ArithmeticOps(self) {
override def *(t: SInt) = self * t
override def mac(m1: SInt, m2: SInt) = m1 * m2 + self
override def +(t: SInt) = self + t
override def -(t: SInt) = self - t
override def >>(u: UInt) = {
// The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm
// TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here?
val point_five = Mux(u === 0.U, 0.U, self(u - 1.U))
val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U
val ones_digit = self(u)
val r = (point_five & (zeros | ones_digit)).asBool
(self >> u).asSInt + Mux(r, 1.S, 0.S)
}
override def >(t: SInt): Bool = self > t
override def withWidthOf(t: SInt) = {
if (self.getWidth >= t.getWidth)
self(t.getWidth-1, 0).asSInt
else {
val sign_bits = t.getWidth - self.getWidth
val sign = self(self.getWidth-1)
Cat(Cat(Seq.fill(sign_bits)(sign)), self).asTypeOf(t)
}
}
override def clippedToWidthOf(t: SInt): SInt = {
val maxsat = ((1 << (t.getWidth-1))-1).S
val minsat = (-(1 << (t.getWidth-1))).S
MuxCase(self, Seq((self > maxsat) -> maxsat, (self < minsat) -> minsat))(t.getWidth-1, 0).asSInt
}
override def relu: SInt = Mux(self >= 0.S, self, 0.S)
override def zero: SInt = 0.S
override def identity: SInt = 1.S
override def minimum: SInt = (-(1 << (self.getWidth-1))).S
override def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = {
// TODO this uses a floating point divider, but we should use an integer divider instead
val input = Wire(Decoupled(denom_t.cloneType))
val output = Wire(Decoupled(self.cloneType))
// We translate our integer to floating-point form so that we can use the hardfloat divider
val expWidth = log2Up(self.getWidth) + 1
val sigWidth = self.getWidth
def sin_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def uin_to_float(x: UInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := false.B
in_to_rec_fn.io.in := x
in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def float_to_in(x: UInt) = {
val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth))
rec_fn_to_in.io.signedOut := true.B
rec_fn_to_in.io.in := x
rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
rec_fn_to_in.io.out.asSInt
}
val self_rec = sin_to_float(self)
val denom_rec = uin_to_float(input.bits)
// Instantiate the hardloat divider
val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options))
input.ready := divider.io.inReady
divider.io.inValid := input.valid
divider.io.sqrtOp := false.B
divider.io.a := self_rec
divider.io.b := denom_rec
divider.io.roundingMode := consts.round_minMag
divider.io.detectTininess := consts.tininess_afterRounding
output.valid := divider.io.outValid_div
output.bits := float_to_in(divider.io.out)
assert(!output.valid || output.ready)
Some((input, output))
}
override def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = {
// TODO this uses a floating point divider, but we should use an integer divider instead
val input = Wire(Decoupled(UInt(0.W)))
val output = Wire(Decoupled(self.cloneType))
input.bits := DontCare
// We translate our integer to floating-point form so that we can use the hardfloat divider
val expWidth = log2Up(self.getWidth) + 1
val sigWidth = self.getWidth
def in_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def float_to_in(x: UInt) = {
val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth))
rec_fn_to_in.io.signedOut := true.B
rec_fn_to_in.io.in := x
rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
rec_fn_to_in.io.out.asSInt
}
val self_rec = in_to_float(self)
// Instantiate the hardloat sqrt
val sqrter = Module(new DivSqrtRecFN_small(expWidth, sigWidth, 0))
input.ready := sqrter.io.inReady
sqrter.io.inValid := input.valid
sqrter.io.sqrtOp := true.B
sqrter.io.a := self_rec
sqrter.io.b := DontCare
sqrter.io.roundingMode := consts.round_minMag
sqrter.io.detectTininess := consts.tininess_afterRounding
output.valid := sqrter.io.outValid_sqrt
output.bits := float_to_in(sqrter.io.out)
assert(!output.valid || output.ready)
Some((input, output))
}
override def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = u match {
case Float(expWidth, sigWidth) =>
val input = Wire(Decoupled(UInt(0.W)))
val output = Wire(Decoupled(u.cloneType))
input.bits := DontCare
// We translate our integer to floating-point form so that we can use the hardfloat divider
def in_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
val self_rec = in_to_float(self)
val one_rec = in_to_float(1.S)
// Instantiate the hardloat divider
val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options))
input.ready := divider.io.inReady
divider.io.inValid := input.valid
divider.io.sqrtOp := false.B
divider.io.a := one_rec
divider.io.b := self_rec
divider.io.roundingMode := consts.round_near_even
divider.io.detectTininess := consts.tininess_afterRounding
output.valid := divider.io.outValid_div
output.bits := fNFromRecFN(expWidth, sigWidth, divider.io.out).asTypeOf(u)
assert(!output.valid || output.ready)
Some((input, output))
case _ => None
}
override def mult_with_reciprocal[U <: Data](reciprocal: U): SInt = reciprocal match {
case recip @ Float(expWidth, sigWidth) =>
def in_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def float_to_in(x: UInt) = {
val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth))
rec_fn_to_in.io.signedOut := true.B
rec_fn_to_in.io.in := x
rec_fn_to_in.io.roundingMode := consts.round_minMag
rec_fn_to_in.io.out.asSInt
}
val self_rec = in_to_float(self)
val reciprocal_rec = recFNFromFN(expWidth, sigWidth, recip.bits)
// Instantiate the hardloat divider
val muladder = Module(new MulRecFN(expWidth, sigWidth))
muladder.io.roundingMode := consts.round_near_even
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := self_rec
muladder.io.b := reciprocal_rec
float_to_in(muladder.io.out)
case _ => self
}
}
}
implicit object FloatArithmetic extends Arithmetic[Float] {
// TODO Floating point arithmetic currently switches between recoded and standard formats for every operation. However, it should stay in the recoded format as it travels through the systolic array
override implicit def cast(self: Float): ArithmeticOps[Float] = new ArithmeticOps(self) {
override def *(t: Float): Float = {
val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth))
t_resizer.io.in := t_rec
t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
t_resizer.io.detectTininess := consts.tininess_afterRounding
val t_rec_resized = t_resizer.io.out
val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth))
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := self_rec
muladder.io.b := t_rec_resized
val out = Wire(Float(self.expWidth, self.sigWidth))
out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
out
}
override def mac(m1: Float, m2: Float): Float = {
// Recode all operands
val m1_rec = recFNFromFN(m1.expWidth, m1.sigWidth, m1.bits)
val m2_rec = recFNFromFN(m2.expWidth, m2.sigWidth, m2.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Resize m1 to self's width
val m1_resizer = Module(new RecFNToRecFN(m1.expWidth, m1.sigWidth, self.expWidth, self.sigWidth))
m1_resizer.io.in := m1_rec
m1_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
m1_resizer.io.detectTininess := consts.tininess_afterRounding
val m1_rec_resized = m1_resizer.io.out
// Resize m2 to self's width
val m2_resizer = Module(new RecFNToRecFN(m2.expWidth, m2.sigWidth, self.expWidth, self.sigWidth))
m2_resizer.io.in := m2_rec
m2_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
m2_resizer.io.detectTininess := consts.tininess_afterRounding
val m2_rec_resized = m2_resizer.io.out
// Perform multiply-add
val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth))
muladder.io.op := 0.U
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := m1_rec_resized
muladder.io.b := m2_rec_resized
muladder.io.c := self_rec
// Convert result to standard format // TODO remove these intermediate recodings
val out = Wire(Float(self.expWidth, self.sigWidth))
out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
out
}
override def +(t: Float): Float = {
require(self.getWidth >= t.getWidth) // This just makes it easier to write the resizing code
// Recode all operands
val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Generate 1 as a float
val in_to_rec_fn = Module(new INToRecFN(1, self.expWidth, self.sigWidth))
in_to_rec_fn.io.signedIn := false.B
in_to_rec_fn.io.in := 1.U
in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
val one_rec = in_to_rec_fn.io.out
// Resize t
val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth))
t_resizer.io.in := t_rec
t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
t_resizer.io.detectTininess := consts.tininess_afterRounding
val t_rec_resized = t_resizer.io.out
// Perform addition
val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth))
muladder.io.op := 0.U
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := t_rec_resized
muladder.io.b := one_rec
muladder.io.c := self_rec
val result = Wire(Float(self.expWidth, self.sigWidth))
result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
result
}
override def -(t: Float): Float = {
val t_sgn = t.bits(t.getWidth-1)
val neg_t = Cat(~t_sgn, t.bits(t.getWidth-2,0)).asTypeOf(t)
self + neg_t
}
override def >>(u: UInt): Float = {
// Recode self
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Get 2^(-u) as a recoded float
val shift_exp = Wire(UInt(self.expWidth.W))
shift_exp := self.bias.U - u
val shift_fn = Cat(0.U(1.W), shift_exp, 0.U((self.sigWidth-1).W))
val shift_rec = recFNFromFN(self.expWidth, self.sigWidth, shift_fn)
assert(shift_exp =/= 0.U, "scaling by denormalized numbers is not currently supported")
// Multiply self and 2^(-u)
val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth))
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := self_rec
muladder.io.b := shift_rec
val result = Wire(Float(self.expWidth, self.sigWidth))
result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
result
}
override def >(t: Float): Bool = {
// Recode all operands
val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Resize t to self's width
val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth))
t_resizer.io.in := t_rec
t_resizer.io.roundingMode := consts.round_near_even
t_resizer.io.detectTininess := consts.tininess_afterRounding
val t_rec_resized = t_resizer.io.out
val comparator = Module(new CompareRecFN(self.expWidth, self.sigWidth))
comparator.io.a := self_rec
comparator.io.b := t_rec_resized
comparator.io.signaling := false.B
comparator.io.gt
}
override def withWidthOf(t: Float): Float = {
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth))
resizer.io.in := self_rec
resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
resizer.io.detectTininess := consts.tininess_afterRounding
val result = Wire(Float(t.expWidth, t.sigWidth))
result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out)
result
}
override def clippedToWidthOf(t: Float): Float = {
// TODO check for overflow. Right now, we just assume that overflow doesn't happen
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth))
resizer.io.in := self_rec
resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
resizer.io.detectTininess := consts.tininess_afterRounding
val result = Wire(Float(t.expWidth, t.sigWidth))
result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out)
result
}
override def relu: Float = {
val raw = rawFloatFromFN(self.expWidth, self.sigWidth, self.bits)
val result = Wire(Float(self.expWidth, self.sigWidth))
result.bits := Mux(!raw.isZero && raw.sign, 0.U, self.bits)
result
}
override def zero: Float = 0.U.asTypeOf(self)
override def identity: Float = Cat(0.U(2.W), ~(0.U((self.expWidth-1).W)), 0.U((self.sigWidth-1).W)).asTypeOf(self)
override def minimum: Float = Cat(1.U, ~(0.U(self.expWidth.W)), 0.U((self.sigWidth-1).W)).asTypeOf(self)
}
}
implicit object DummySIntArithmetic extends Arithmetic[DummySInt] {
override implicit def cast(self: DummySInt) = new ArithmeticOps(self) {
override def *(t: DummySInt) = self.dontCare
override def mac(m1: DummySInt, m2: DummySInt) = self.dontCare
override def +(t: DummySInt) = self.dontCare
override def -(t: DummySInt) = self.dontCare
override def >>(t: UInt) = self.dontCare
override def >(t: DummySInt): Bool = false.B
override def identity = self.dontCare
override def withWidthOf(t: DummySInt) = self.dontCare
override def clippedToWidthOf(t: DummySInt) = self.dontCare
override def relu = self.dontCare
override def zero = self.dontCare
override def minimum: DummySInt = self.dontCare
}
}
}
| module PE_452( // @[PE.scala:31:7]
input clock, // @[PE.scala:31:7]
input reset, // @[PE.scala:31:7]
input [7:0] io_in_a, // @[PE.scala:35:14]
input [19:0] io_in_b, // @[PE.scala:35:14]
input [19:0] io_in_d, // @[PE.scala:35:14]
output [7:0] io_out_a, // @[PE.scala:35:14]
output [19:0] io_out_b, // @[PE.scala:35:14]
output [19:0] io_out_c, // @[PE.scala:35:14]
input io_in_control_dataflow, // @[PE.scala:35:14]
input io_in_control_propagate, // @[PE.scala:35:14]
input [4:0] io_in_control_shift, // @[PE.scala:35:14]
output io_out_control_dataflow, // @[PE.scala:35:14]
output io_out_control_propagate, // @[PE.scala:35:14]
output [4:0] io_out_control_shift, // @[PE.scala:35:14]
input [2:0] io_in_id, // @[PE.scala:35:14]
output [2:0] io_out_id, // @[PE.scala:35:14]
input io_in_last, // @[PE.scala:35:14]
output io_out_last, // @[PE.scala:35:14]
input io_in_valid, // @[PE.scala:35:14]
output io_out_valid // @[PE.scala:35:14]
);
wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:31:7]
wire [19:0] io_in_b_0 = io_in_b; // @[PE.scala:31:7]
wire [19:0] io_in_d_0 = io_in_d; // @[PE.scala:31:7]
wire io_in_control_dataflow_0 = io_in_control_dataflow; // @[PE.scala:31:7]
wire io_in_control_propagate_0 = io_in_control_propagate; // @[PE.scala:31:7]
wire [4:0] io_in_control_shift_0 = io_in_control_shift; // @[PE.scala:31:7]
wire [2:0] io_in_id_0 = io_in_id; // @[PE.scala:31:7]
wire io_in_last_0 = io_in_last; // @[PE.scala:31:7]
wire io_in_valid_0 = io_in_valid; // @[PE.scala:31:7]
wire io_bad_dataflow = 1'h0; // @[PE.scala:31:7]
wire _io_out_c_T_5 = 1'h0; // @[Arithmetic.scala:125:33]
wire _io_out_c_T_6 = 1'h0; // @[Arithmetic.scala:125:60]
wire _io_out_c_T_16 = 1'h0; // @[Arithmetic.scala:125:33]
wire _io_out_c_T_17 = 1'h0; // @[Arithmetic.scala:125:60]
wire [7:0] io_out_a_0 = io_in_a_0; // @[PE.scala:31:7]
wire [19:0] _mac_unit_io_in_b_T = io_in_b_0; // @[PE.scala:31:7, :106:37]
wire [19:0] _mac_unit_io_in_b_T_2 = io_in_b_0; // @[PE.scala:31:7, :113:37]
wire [19:0] _mac_unit_io_in_b_T_8 = io_in_b_0; // @[PE.scala:31:7, :137:35]
wire io_out_control_dataflow_0 = io_in_control_dataflow_0; // @[PE.scala:31:7]
wire io_out_control_propagate_0 = io_in_control_propagate_0; // @[PE.scala:31:7]
wire [4:0] io_out_control_shift_0 = io_in_control_shift_0; // @[PE.scala:31:7]
wire [2:0] io_out_id_0 = io_in_id_0; // @[PE.scala:31:7]
wire io_out_last_0 = io_in_last_0; // @[PE.scala:31:7]
wire io_out_valid_0 = io_in_valid_0; // @[PE.scala:31:7]
wire [19:0] io_out_b_0; // @[PE.scala:31:7]
wire [19:0] io_out_c_0; // @[PE.scala:31:7]
reg [7:0] c1; // @[PE.scala:70:15]
wire [7:0] _io_out_c_zeros_T_1 = c1; // @[PE.scala:70:15]
wire [7:0] _mac_unit_io_in_b_T_6 = c1; // @[PE.scala:70:15, :127:38]
reg [7:0] c2; // @[PE.scala:71:15]
wire [7:0] _io_out_c_zeros_T_10 = c2; // @[PE.scala:71:15]
wire [7:0] _mac_unit_io_in_b_T_4 = c2; // @[PE.scala:71:15, :121:38]
reg last_s; // @[PE.scala:89:25]
wire flip = last_s != io_in_control_propagate_0; // @[PE.scala:31:7, :89:25, :90:21]
wire [4:0] shift_offset = flip ? io_in_control_shift_0 : 5'h0; // @[PE.scala:31:7, :90:21, :91:25]
wire _GEN = shift_offset == 5'h0; // @[PE.scala:91:25]
wire _io_out_c_point_five_T; // @[Arithmetic.scala:101:32]
assign _io_out_c_point_five_T = _GEN; // @[Arithmetic.scala:101:32]
wire _io_out_c_point_five_T_5; // @[Arithmetic.scala:101:32]
assign _io_out_c_point_five_T_5 = _GEN; // @[Arithmetic.scala:101:32]
wire [5:0] _GEN_0 = {1'h0, shift_offset} - 6'h1; // @[PE.scala:91:25]
wire [5:0] _io_out_c_point_five_T_1; // @[Arithmetic.scala:101:53]
assign _io_out_c_point_five_T_1 = _GEN_0; // @[Arithmetic.scala:101:53]
wire [5:0] _io_out_c_zeros_T_2; // @[Arithmetic.scala:102:66]
assign _io_out_c_zeros_T_2 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66]
wire [5:0] _io_out_c_point_five_T_6; // @[Arithmetic.scala:101:53]
assign _io_out_c_point_five_T_6 = _GEN_0; // @[Arithmetic.scala:101:53]
wire [5:0] _io_out_c_zeros_T_11; // @[Arithmetic.scala:102:66]
assign _io_out_c_zeros_T_11 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66]
wire [4:0] _io_out_c_point_five_T_2 = _io_out_c_point_five_T_1[4:0]; // @[Arithmetic.scala:101:53]
wire [7:0] _io_out_c_point_five_T_3 = $signed($signed(c1) >>> _io_out_c_point_five_T_2); // @[PE.scala:70:15]
wire _io_out_c_point_five_T_4 = _io_out_c_point_five_T_3[0]; // @[Arithmetic.scala:101:50]
wire io_out_c_point_five = ~_io_out_c_point_five_T & _io_out_c_point_five_T_4; // @[Arithmetic.scala:101:{29,32,50}]
wire _GEN_1 = shift_offset < 5'h2; // @[PE.scala:91:25]
wire _io_out_c_zeros_T; // @[Arithmetic.scala:102:27]
assign _io_out_c_zeros_T = _GEN_1; // @[Arithmetic.scala:102:27]
wire _io_out_c_zeros_T_9; // @[Arithmetic.scala:102:27]
assign _io_out_c_zeros_T_9 = _GEN_1; // @[Arithmetic.scala:102:27]
wire [4:0] _io_out_c_zeros_T_3 = _io_out_c_zeros_T_2[4:0]; // @[Arithmetic.scala:102:66]
wire [31:0] _io_out_c_zeros_T_4 = 32'h1 << _io_out_c_zeros_T_3; // @[Arithmetic.scala:102:{60,66}]
wire [32:0] _io_out_c_zeros_T_5 = {1'h0, _io_out_c_zeros_T_4} - 33'h1; // @[Arithmetic.scala:102:{60,81}]
wire [31:0] _io_out_c_zeros_T_6 = _io_out_c_zeros_T_5[31:0]; // @[Arithmetic.scala:102:81]
wire [31:0] _io_out_c_zeros_T_7 = {24'h0, _io_out_c_zeros_T_6[7:0] & _io_out_c_zeros_T_1}; // @[Arithmetic.scala:102:{45,52,81}]
wire [31:0] _io_out_c_zeros_T_8 = _io_out_c_zeros_T ? 32'h0 : _io_out_c_zeros_T_7; // @[Arithmetic.scala:102:{24,27,52}]
wire io_out_c_zeros = |_io_out_c_zeros_T_8; // @[Arithmetic.scala:102:{24,89}]
wire [7:0] _GEN_2 = {3'h0, shift_offset}; // @[PE.scala:91:25]
wire [7:0] _GEN_3 = $signed($signed(c1) >>> _GEN_2); // @[PE.scala:70:15]
wire [7:0] _io_out_c_ones_digit_T; // @[Arithmetic.scala:103:30]
assign _io_out_c_ones_digit_T = _GEN_3; // @[Arithmetic.scala:103:30]
wire [7:0] _io_out_c_T; // @[Arithmetic.scala:107:15]
assign _io_out_c_T = _GEN_3; // @[Arithmetic.scala:103:30, :107:15]
wire io_out_c_ones_digit = _io_out_c_ones_digit_T[0]; // @[Arithmetic.scala:103:30]
wire _io_out_c_r_T = io_out_c_zeros | io_out_c_ones_digit; // @[Arithmetic.scala:102:89, :103:30, :105:38]
wire _io_out_c_r_T_1 = io_out_c_point_five & _io_out_c_r_T; // @[Arithmetic.scala:101:29, :105:{29,38}]
wire io_out_c_r = _io_out_c_r_T_1; // @[Arithmetic.scala:105:{29,53}]
wire [1:0] _io_out_c_T_1 = {1'h0, io_out_c_r}; // @[Arithmetic.scala:105:53, :107:33]
wire [8:0] _io_out_c_T_2 = {_io_out_c_T[7], _io_out_c_T} + {{7{_io_out_c_T_1[1]}}, _io_out_c_T_1}; // @[Arithmetic.scala:107:{15,28,33}]
wire [7:0] _io_out_c_T_3 = _io_out_c_T_2[7:0]; // @[Arithmetic.scala:107:28]
wire [7:0] _io_out_c_T_4 = _io_out_c_T_3; // @[Arithmetic.scala:107:28]
wire [19:0] _io_out_c_T_7 = {{12{_io_out_c_T_4[7]}}, _io_out_c_T_4}; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_8 = _io_out_c_T_7; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_9 = _io_out_c_T_8; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_10 = _io_out_c_T_9; // @[Arithmetic.scala:125:{81,99}]
wire [19:0] _mac_unit_io_in_b_T_1 = _mac_unit_io_in_b_T; // @[PE.scala:106:37]
wire [7:0] _mac_unit_io_in_b_WIRE = _mac_unit_io_in_b_T_1[7:0]; // @[PE.scala:106:37]
wire [7:0] _c1_T = io_in_d_0[7:0]; // @[PE.scala:31:7]
wire [7:0] _c2_T = io_in_d_0[7:0]; // @[PE.scala:31:7]
wire [7:0] _c1_T_1 = _c1_T; // @[Arithmetic.scala:114:{15,33}]
wire [4:0] _io_out_c_point_five_T_7 = _io_out_c_point_five_T_6[4:0]; // @[Arithmetic.scala:101:53]
wire [7:0] _io_out_c_point_five_T_8 = $signed($signed(c2) >>> _io_out_c_point_five_T_7); // @[PE.scala:71:15]
wire _io_out_c_point_five_T_9 = _io_out_c_point_five_T_8[0]; // @[Arithmetic.scala:101:50]
wire io_out_c_point_five_1 = ~_io_out_c_point_five_T_5 & _io_out_c_point_five_T_9; // @[Arithmetic.scala:101:{29,32,50}]
wire [4:0] _io_out_c_zeros_T_12 = _io_out_c_zeros_T_11[4:0]; // @[Arithmetic.scala:102:66]
wire [31:0] _io_out_c_zeros_T_13 = 32'h1 << _io_out_c_zeros_T_12; // @[Arithmetic.scala:102:{60,66}]
wire [32:0] _io_out_c_zeros_T_14 = {1'h0, _io_out_c_zeros_T_13} - 33'h1; // @[Arithmetic.scala:102:{60,81}]
wire [31:0] _io_out_c_zeros_T_15 = _io_out_c_zeros_T_14[31:0]; // @[Arithmetic.scala:102:81]
wire [31:0] _io_out_c_zeros_T_16 = {24'h0, _io_out_c_zeros_T_15[7:0] & _io_out_c_zeros_T_10}; // @[Arithmetic.scala:102:{45,52,81}]
wire [31:0] _io_out_c_zeros_T_17 = _io_out_c_zeros_T_9 ? 32'h0 : _io_out_c_zeros_T_16; // @[Arithmetic.scala:102:{24,27,52}]
wire io_out_c_zeros_1 = |_io_out_c_zeros_T_17; // @[Arithmetic.scala:102:{24,89}]
wire [7:0] _GEN_4 = $signed($signed(c2) >>> _GEN_2); // @[PE.scala:71:15]
wire [7:0] _io_out_c_ones_digit_T_1; // @[Arithmetic.scala:103:30]
assign _io_out_c_ones_digit_T_1 = _GEN_4; // @[Arithmetic.scala:103:30]
wire [7:0] _io_out_c_T_11; // @[Arithmetic.scala:107:15]
assign _io_out_c_T_11 = _GEN_4; // @[Arithmetic.scala:103:30, :107:15]
wire io_out_c_ones_digit_1 = _io_out_c_ones_digit_T_1[0]; // @[Arithmetic.scala:103:30]
wire _io_out_c_r_T_2 = io_out_c_zeros_1 | io_out_c_ones_digit_1; // @[Arithmetic.scala:102:89, :103:30, :105:38]
wire _io_out_c_r_T_3 = io_out_c_point_five_1 & _io_out_c_r_T_2; // @[Arithmetic.scala:101:29, :105:{29,38}]
wire io_out_c_r_1 = _io_out_c_r_T_3; // @[Arithmetic.scala:105:{29,53}]
wire [1:0] _io_out_c_T_12 = {1'h0, io_out_c_r_1}; // @[Arithmetic.scala:105:53, :107:33]
wire [8:0] _io_out_c_T_13 = {_io_out_c_T_11[7], _io_out_c_T_11} + {{7{_io_out_c_T_12[1]}}, _io_out_c_T_12}; // @[Arithmetic.scala:107:{15,28,33}]
wire [7:0] _io_out_c_T_14 = _io_out_c_T_13[7:0]; // @[Arithmetic.scala:107:28]
wire [7:0] _io_out_c_T_15 = _io_out_c_T_14; // @[Arithmetic.scala:107:28]
wire [19:0] _io_out_c_T_18 = {{12{_io_out_c_T_15[7]}}, _io_out_c_T_15}; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_19 = _io_out_c_T_18; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_20 = _io_out_c_T_19; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_21 = _io_out_c_T_20; // @[Arithmetic.scala:125:{81,99}]
wire [19:0] _mac_unit_io_in_b_T_3 = _mac_unit_io_in_b_T_2; // @[PE.scala:113:37]
wire [7:0] _mac_unit_io_in_b_WIRE_1 = _mac_unit_io_in_b_T_3[7:0]; // @[PE.scala:113:37]
wire [7:0] _c2_T_1 = _c2_T; // @[Arithmetic.scala:114:{15,33}]
wire [7:0] _mac_unit_io_in_b_T_5; // @[PE.scala:121:38]
assign _mac_unit_io_in_b_T_5 = _mac_unit_io_in_b_T_4; // @[PE.scala:121:38]
wire [7:0] _mac_unit_io_in_b_WIRE_2 = _mac_unit_io_in_b_T_5; // @[PE.scala:121:38]
assign io_out_c_0 = io_in_control_propagate_0 ? {{12{c1[7]}}, c1} : {{12{c2[7]}}, c2}; // @[PE.scala:31:7, :70:15, :71:15, :119:30, :120:16, :126:16]
wire [7:0] _mac_unit_io_in_b_T_7; // @[PE.scala:127:38]
assign _mac_unit_io_in_b_T_7 = _mac_unit_io_in_b_T_6; // @[PE.scala:127:38]
wire [7:0] _mac_unit_io_in_b_WIRE_3 = _mac_unit_io_in_b_T_7; // @[PE.scala:127:38]
wire [19:0] _mac_unit_io_in_b_T_9 = _mac_unit_io_in_b_T_8; // @[PE.scala:137:35]
wire [7:0] _mac_unit_io_in_b_WIRE_4 = _mac_unit_io_in_b_T_9[7:0]; // @[PE.scala:137:35]
always @(posedge clock) begin // @[PE.scala:31:7]
if (io_in_valid_0 & io_in_control_propagate_0) // @[PE.scala:31:7, :102:95, :141:17, :142:8]
c1 <= io_in_d_0[7:0]; // @[PE.scala:31:7, :70:15]
if (~(~io_in_valid_0 | io_in_control_propagate_0)) // @[PE.scala:31:7, :71:15, :102:95, :119:30, :130:10, :141:{9,17}, :143:8]
c2 <= io_in_d_0[7:0]; // @[PE.scala:31:7, :71:15]
if (io_in_valid_0) // @[PE.scala:31:7]
last_s <= io_in_control_propagate_0; // @[PE.scala:31:7, :89:25]
always @(posedge)
MacUnit_196 mac_unit ( // @[PE.scala:64:24]
.clock (clock),
.reset (reset),
.io_in_a (io_in_a_0), // @[PE.scala:31:7]
.io_in_b (io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE_2 : _mac_unit_io_in_b_WIRE_3), // @[PE.scala:31:7, :119:30, :121:{24,38}, :127:{24,38}]
.io_in_c (io_in_b_0), // @[PE.scala:31:7]
.io_out_d (io_out_b_0)
); // @[PE.scala:64:24]
assign io_out_a = io_out_a_0; // @[PE.scala:31:7]
assign io_out_b = io_out_b_0; // @[PE.scala:31:7]
assign io_out_c = io_out_c_0; // @[PE.scala:31:7]
assign io_out_control_dataflow = io_out_control_dataflow_0; // @[PE.scala:31:7]
assign io_out_control_propagate = io_out_control_propagate_0; // @[PE.scala:31:7]
assign io_out_control_shift = io_out_control_shift_0; // @[PE.scala:31:7]
assign io_out_id = io_out_id_0; // @[PE.scala:31:7]
assign io_out_last = io_out_last_0; // @[PE.scala:31:7]
assign io_out_valid = io_out_valid_0; // @[PE.scala:31:7]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File ClockDomain.scala:
package freechips.rocketchip.prci
import chisel3._
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy.lazymodule._
abstract class Domain(implicit p: Parameters) extends LazyModule with HasDomainCrossing
{
def clockBundle: ClockBundle
lazy val module = new Impl
class Impl extends LazyRawModuleImp(this) {
childClock := clockBundle.clock
childReset := clockBundle.reset
override def provideImplicitClockToLazyChildren = true
// these are just for backwards compatibility with external devices
// that were manually wiring themselves to the domain's clock/reset input:
val clock = IO(Output(chiselTypeOf(clockBundle.clock)))
val reset = IO(Output(chiselTypeOf(clockBundle.reset)))
clock := clockBundle.clock
reset := clockBundle.reset
}
}
abstract class ClockDomain(implicit p: Parameters) extends Domain with HasClockDomainCrossing
class ClockSinkDomain(val clockSinkParams: ClockSinkParameters)(implicit p: Parameters) extends ClockDomain
{
def this(take: Option[ClockParameters] = None, name: Option[String] = None)(implicit p: Parameters) = this(ClockSinkParameters(take = take, name = name))
val clockNode = ClockSinkNode(Seq(clockSinkParams))
def clockBundle = clockNode.in.head._1
override lazy val desiredName = (clockSinkParams.name.toSeq :+ "ClockSinkDomain").mkString
}
class ClockSourceDomain(val clockSourceParams: ClockSourceParameters)(implicit p: Parameters) extends ClockDomain
{
def this(give: Option[ClockParameters] = None, name: Option[String] = None)(implicit p: Parameters) = this(ClockSourceParameters(give = give, name = name))
val clockNode = ClockSourceNode(Seq(clockSourceParams))
def clockBundle = clockNode.out.head._1
override lazy val desiredName = (clockSourceParams.name.toSeq :+ "ClockSourceDomain").mkString
}
abstract class ResetDomain(implicit p: Parameters) extends Domain with HasResetDomainCrossing
File LazyModuleImp.scala:
package org.chipsalliance.diplomacy.lazymodule
import chisel3.{withClockAndReset, Module, RawModule, Reset, _}
import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo}
import firrtl.passes.InlineAnnotation
import org.chipsalliance.cde.config.Parameters
import org.chipsalliance.diplomacy.nodes.Dangle
import scala.collection.immutable.SortedMap
/** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]].
*
* This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy.
*/
sealed trait LazyModuleImpLike extends RawModule {
/** [[LazyModule]] that contains this instance. */
val wrapper: LazyModule
/** IOs that will be automatically "punched" for this instance. */
val auto: AutoBundle
/** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */
protected[diplomacy] val dangles: Seq[Dangle]
// [[wrapper.module]] had better not be accessed while LazyModules are still being built!
require(
LazyModule.scope.isEmpty,
s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}"
)
/** Set module name. Defaults to the containing LazyModule's desiredName. */
override def desiredName: String = wrapper.desiredName
suggestName(wrapper.suggestedName)
/** [[Parameters]] for chisel [[Module]]s. */
implicit val p: Parameters = wrapper.p
/** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and
* submodules.
*/
protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = {
// 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]],
// 2. return [[Dangle]]s from each module.
val childDangles = wrapper.children.reverse.flatMap { c =>
implicit val sourceInfo: SourceInfo = c.info
c.cloneProto.map { cp =>
// If the child is a clone, then recursively set cloneProto of its children as well
def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = {
require(bases.size == clones.size)
(bases.zip(clones)).map { case (l, r) =>
require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}")
l.cloneProto = Some(r)
assignCloneProtos(l.children, r.children)
}
}
assignCloneProtos(c.children, cp.children)
// Clone the child module as a record, and get its [[AutoBundle]]
val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName)
val clonedAuto = clone("auto").asInstanceOf[AutoBundle]
// Get the empty [[Dangle]]'s of the cloned child
val rawDangles = c.cloneDangles()
require(rawDangles.size == clonedAuto.elements.size)
// Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s
val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) }
dangles
}.getOrElse {
// For non-clones, instantiate the child module
val mod = try {
Module(c.module)
} catch {
case e: ChiselException => {
println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}")
throw e
}
}
mod.dangles
}
}
// Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]].
// This will result in a sequence of [[Dangle]] from these [[BaseNode]]s.
val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate())
// Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]]
val allDangles = nodeDangles ++ childDangles
// Group [[allDangles]] by their [[source]].
val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*)
// For each [[source]] set of [[Dangle]]s of size 2, ensure that these
// can be connected as a source-sink pair (have opposite flipped value).
// Make the connection and mark them as [[done]].
val done = Set() ++ pairing.values.filter(_.size == 2).map {
case Seq(a, b) =>
require(a.flipped != b.flipped)
// @todo <> in chisel3 makes directionless connection.
if (a.flipped) {
a.data <> b.data
} else {
b.data <> a.data
}
a.source
case _ => None
}
// Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module.
val forward = allDangles.filter(d => !done(d.source))
// Generate [[AutoBundle]] IO from [[forward]].
val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*))
// Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]]
val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) =>
if (d.flipped) {
d.data <> io
} else {
io <> d.data
}
d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name)
}
// Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]].
wrapper.inModuleBody.reverse.foreach {
_()
}
if (wrapper.shouldBeInlined) {
chisel3.experimental.annotate(new ChiselAnnotation {
def toFirrtl = InlineAnnotation(toNamed)
})
}
// Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]].
(auto, dangles)
}
}
/** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike {
/** Instantiate hardware of this `Module`. */
val (auto, dangles) = instantiate()
}
/** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike {
// These wires are the default clock+reset for all LazyModule children.
// It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the
// [[LazyRawModuleImp]] children.
// Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly.
/** drive clock explicitly. */
val childClock: Clock = Wire(Clock())
/** drive reset explicitly. */
val childReset: Reset = Wire(Reset())
// the default is that these are disabled
childClock := false.B.asClock
childReset := chisel3.DontCare
def provideImplicitClockToLazyChildren: Boolean = false
val (auto, dangles) =
if (provideImplicitClockToLazyChildren) {
withClockAndReset(childClock, childReset) { instantiate() }
} else {
instantiate()
}
}
File NoC.scala:
package constellation.noc
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.{Field, Parameters}
import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp, BundleBridgeSink, InModuleBody}
import freechips.rocketchip.util.ElaborationArtefacts
import freechips.rocketchip.prci._
import constellation.router._
import constellation.channel._
import constellation.routing.{RoutingRelation, ChannelRoutingInfo}
import constellation.topology.{PhysicalTopology, UnidirectionalLine}
class NoCTerminalIO(
val ingressParams: Seq[IngressChannelParams],
val egressParams: Seq[EgressChannelParams])(implicit val p: Parameters) extends Bundle {
val ingress = MixedVec(ingressParams.map { u => Flipped(new IngressChannel(u)) })
val egress = MixedVec(egressParams.map { u => new EgressChannel(u) })
}
class NoC(nocParams: NoCParams)(implicit p: Parameters) extends LazyModule {
override def shouldBeInlined = nocParams.inlineNoC
val internalParams = InternalNoCParams(nocParams)
val allChannelParams = internalParams.channelParams
val allIngressParams = internalParams.ingressParams
val allEgressParams = internalParams.egressParams
val allRouterParams = internalParams.routerParams
val iP = p.alterPartial({ case InternalNoCKey => internalParams })
val nNodes = nocParams.topology.nNodes
val nocName = nocParams.nocName
val skipValidationChecks = nocParams.skipValidationChecks
val clockSourceNodes = Seq.tabulate(nNodes) { i => ClockSourceNode(Seq(ClockSourceParameters())) }
val router_sink_domains = Seq.tabulate(nNodes) { i =>
val router_sink_domain = LazyModule(new ClockSinkDomain(ClockSinkParameters(
name = Some(s"${nocName}_router_$i")
)))
router_sink_domain.clockNode := clockSourceNodes(i)
router_sink_domain
}
val routers = Seq.tabulate(nNodes) { i => router_sink_domains(i) {
val inParams = allChannelParams.filter(_.destId == i).map(
_.copy(payloadBits=allRouterParams(i).user.payloadBits)
)
val outParams = allChannelParams.filter(_.srcId == i).map(
_.copy(payloadBits=allRouterParams(i).user.payloadBits)
)
val ingressParams = allIngressParams.filter(_.destId == i).map(
_.copy(payloadBits=allRouterParams(i).user.payloadBits)
)
val egressParams = allEgressParams.filter(_.srcId == i).map(
_.copy(payloadBits=allRouterParams(i).user.payloadBits)
)
val noIn = inParams.size + ingressParams.size == 0
val noOut = outParams.size + egressParams.size == 0
if (noIn || noOut) {
println(s"Constellation WARNING: $nocName router $i seems to be unused, it will not be generated")
None
} else {
Some(LazyModule(new Router(
routerParams = allRouterParams(i),
preDiplomaticInParams = inParams,
preDiplomaticIngressParams = ingressParams,
outDests = outParams.map(_.destId),
egressIds = egressParams.map(_.egressId)
)(iP)))
}
}}.flatten
val ingressNodes = allIngressParams.map { u => IngressChannelSourceNode(u.destId) }
val egressNodes = allEgressParams.map { u => EgressChannelDestNode(u) }
// Generate channels between routers diplomatically
Seq.tabulate(nNodes, nNodes) { case (i, j) => if (i != j) {
val routerI = routers.find(_.nodeId == i)
val routerJ = routers.find(_.nodeId == j)
if (routerI.isDefined && routerJ.isDefined) {
val sourceNodes: Seq[ChannelSourceNode] = routerI.get.sourceNodes.filter(_.destId == j)
val destNodes: Seq[ChannelDestNode] = routerJ.get.destNodes.filter(_.destParams.srcId == i)
require (sourceNodes.size == destNodes.size)
(sourceNodes zip destNodes).foreach { case (src, dst) =>
val channelParam = allChannelParams.find(c => c.srcId == i && c.destId == j).get
router_sink_domains(j) {
implicit val p: Parameters = iP
(dst
:= ChannelWidthWidget(routerJ.get.payloadBits, routerI.get.payloadBits)
:= channelParam.channelGen(p)(src)
)
}
}
}
}}
// Generate terminal channels diplomatically
routers.foreach { dst => router_sink_domains(dst.nodeId) {
implicit val p: Parameters = iP
dst.ingressNodes.foreach(n => {
val ingressId = n.destParams.ingressId
require(dst.payloadBits <= allIngressParams(ingressId).payloadBits)
(n
:= IngressWidthWidget(dst.payloadBits, allIngressParams(ingressId).payloadBits)
:= ingressNodes(ingressId)
)
})
dst.egressNodes.foreach(n => {
val egressId = n.egressId
require(dst.payloadBits <= allEgressParams(egressId).payloadBits)
(egressNodes(egressId)
:= EgressWidthWidget(allEgressParams(egressId).payloadBits, dst.payloadBits)
:= n
)
})
}}
val debugNodes = routers.map { r =>
val sink = BundleBridgeSink[DebugBundle]()
sink := r.debugNode
sink
}
val ctrlNodes = if (nocParams.hasCtrl) {
(0 until nNodes).map { i =>
routers.find(_.nodeId == i).map { r =>
val sink = BundleBridgeSink[RouterCtrlBundle]()
sink := r.ctrlNode.get
sink
}
}
} else {
Nil
}
println(s"Constellation: $nocName Finished parameter validation")
lazy val module = new Impl
class Impl extends LazyModuleImp(this) {
println(s"Constellation: $nocName Starting NoC RTL generation")
val io = IO(new NoCTerminalIO(allIngressParams, allEgressParams)(iP) {
val router_clocks = Vec(nNodes, Input(new ClockBundle(ClockBundleParameters())))
val router_ctrl = if (nocParams.hasCtrl) Vec(nNodes, new RouterCtrlBundle) else Nil
})
(io.ingress zip ingressNodes.map(_.out(0)._1)).foreach { case (l,r) => r <> l }
(io.egress zip egressNodes .map(_.in (0)._1)).foreach { case (l,r) => l <> r }
(io.router_clocks zip clockSourceNodes.map(_.out(0)._1)).foreach { case (l,r) => l <> r }
if (nocParams.hasCtrl) {
ctrlNodes.zipWithIndex.map { case (c,i) =>
if (c.isDefined) {
io.router_ctrl(i) <> c.get.in(0)._1
} else {
io.router_ctrl(i) <> DontCare
}
}
}
// TODO: These assume a single clock-domain across the entire noc
val debug_va_stall_ctr = RegInit(0.U(64.W))
val debug_sa_stall_ctr = RegInit(0.U(64.W))
val debug_any_stall_ctr = debug_va_stall_ctr + debug_sa_stall_ctr
debug_va_stall_ctr := debug_va_stall_ctr + debugNodes.map(_.in(0)._1.va_stall.reduce(_+_)).reduce(_+_)
debug_sa_stall_ctr := debug_sa_stall_ctr + debugNodes.map(_.in(0)._1.sa_stall.reduce(_+_)).reduce(_+_)
dontTouch(debug_va_stall_ctr)
dontTouch(debug_sa_stall_ctr)
dontTouch(debug_any_stall_ctr)
def prepend(s: String) = Seq(nocName, s).mkString(".")
ElaborationArtefacts.add(prepend("noc.graphml"), graphML)
val adjList = routers.map { r =>
val outs = r.outParams.map(o => s"${o.destId}").mkString(" ")
val egresses = r.egressParams.map(e => s"e${e.egressId}").mkString(" ")
val ingresses = r.ingressParams.map(i => s"i${i.ingressId} ${r.nodeId}")
(Seq(s"${r.nodeId} $outs $egresses") ++ ingresses).mkString("\n")
}.mkString("\n")
ElaborationArtefacts.add(prepend("noc.adjlist"), adjList)
val xys = routers.map(r => {
val n = r.nodeId
val ids = (Seq(r.nodeId.toString)
++ r.egressParams.map(e => s"e${e.egressId}")
++ r.ingressParams.map(i => s"i${i.ingressId}")
)
val plotter = nocParams.topology.plotter
val coords = (Seq(plotter.node(r.nodeId))
++ Seq.tabulate(r.egressParams.size ) { i => plotter. egress(i, r. egressParams.size, r.nodeId) }
++ Seq.tabulate(r.ingressParams.size) { i => plotter.ingress(i, r.ingressParams.size, r.nodeId) }
)
(ids zip coords).map { case (i, (x, y)) => s"$i $x $y" }.mkString("\n")
}).mkString("\n")
ElaborationArtefacts.add(prepend("noc.xy"), xys)
val edgeProps = routers.map { r =>
val outs = r.outParams.map { o =>
(Seq(s"${r.nodeId} ${o.destId}") ++ (if (o.possibleFlows.size == 0) Some("unused") else None))
.mkString(" ")
}
val egresses = r.egressParams.map { e =>
(Seq(s"${r.nodeId} e${e.egressId}") ++ (if (e.possibleFlows.size == 0) Some("unused") else None))
.mkString(" ")
}
val ingresses = r.ingressParams.map { i =>
(Seq(s"i${i.ingressId} ${r.nodeId}") ++ (if (i.possibleFlows.size == 0) Some("unused") else None))
.mkString(" ")
}
(outs ++ egresses ++ ingresses).mkString("\n")
}.mkString("\n")
ElaborationArtefacts.add(prepend("noc.edgeprops"), edgeProps)
println(s"Constellation: $nocName Finished NoC RTL generation")
}
}
| module test_router_15ClockSinkDomain( // @[ClockDomain.scala:14:9]
output [4:0] auto_routers_debug_out_va_stall_0, // @[LazyModuleImp.scala:107:25]
output [4:0] auto_routers_debug_out_va_stall_1, // @[LazyModuleImp.scala:107:25]
output [4:0] auto_routers_debug_out_va_stall_2, // @[LazyModuleImp.scala:107:25]
output [4:0] auto_routers_debug_out_va_stall_3, // @[LazyModuleImp.scala:107:25]
output [4:0] auto_routers_debug_out_sa_stall_0, // @[LazyModuleImp.scala:107:25]
output [4:0] auto_routers_debug_out_sa_stall_1, // @[LazyModuleImp.scala:107:25]
output [4:0] auto_routers_debug_out_sa_stall_2, // @[LazyModuleImp.scala:107:25]
output [4:0] auto_routers_debug_out_sa_stall_3, // @[LazyModuleImp.scala:107:25]
input auto_routers_egress_nodes_out_1_flit_ready, // @[LazyModuleImp.scala:107:25]
output auto_routers_egress_nodes_out_1_flit_valid, // @[LazyModuleImp.scala:107:25]
output auto_routers_egress_nodes_out_1_flit_bits_head, // @[LazyModuleImp.scala:107:25]
output auto_routers_egress_nodes_out_1_flit_bits_tail, // @[LazyModuleImp.scala:107:25]
output [72:0] auto_routers_egress_nodes_out_1_flit_bits_payload, // @[LazyModuleImp.scala:107:25]
input auto_routers_egress_nodes_out_0_flit_ready, // @[LazyModuleImp.scala:107:25]
output auto_routers_egress_nodes_out_0_flit_valid, // @[LazyModuleImp.scala:107:25]
output auto_routers_egress_nodes_out_0_flit_bits_head, // @[LazyModuleImp.scala:107:25]
output auto_routers_egress_nodes_out_0_flit_bits_tail, // @[LazyModuleImp.scala:107:25]
output [72:0] auto_routers_egress_nodes_out_0_flit_bits_payload, // @[LazyModuleImp.scala:107:25]
output auto_routers_ingress_nodes_in_2_flit_ready, // @[LazyModuleImp.scala:107:25]
input auto_routers_ingress_nodes_in_2_flit_valid, // @[LazyModuleImp.scala:107:25]
input auto_routers_ingress_nodes_in_2_flit_bits_head, // @[LazyModuleImp.scala:107:25]
input [72:0] auto_routers_ingress_nodes_in_2_flit_bits_payload, // @[LazyModuleImp.scala:107:25]
input [5:0] auto_routers_ingress_nodes_in_2_flit_bits_egress_id, // @[LazyModuleImp.scala:107:25]
output auto_routers_ingress_nodes_in_1_flit_ready, // @[LazyModuleImp.scala:107:25]
input auto_routers_ingress_nodes_in_1_flit_valid, // @[LazyModuleImp.scala:107:25]
input auto_routers_ingress_nodes_in_1_flit_bits_head, // @[LazyModuleImp.scala:107:25]
input auto_routers_ingress_nodes_in_1_flit_bits_tail, // @[LazyModuleImp.scala:107:25]
input [72:0] auto_routers_ingress_nodes_in_1_flit_bits_payload, // @[LazyModuleImp.scala:107:25]
input [5:0] auto_routers_ingress_nodes_in_1_flit_bits_egress_id, // @[LazyModuleImp.scala:107:25]
output auto_routers_ingress_nodes_in_0_flit_ready, // @[LazyModuleImp.scala:107:25]
input auto_routers_ingress_nodes_in_0_flit_valid, // @[LazyModuleImp.scala:107:25]
input auto_routers_ingress_nodes_in_0_flit_bits_head, // @[LazyModuleImp.scala:107:25]
input auto_routers_ingress_nodes_in_0_flit_bits_tail, // @[LazyModuleImp.scala:107:25]
input [72:0] auto_routers_ingress_nodes_in_0_flit_bits_payload, // @[LazyModuleImp.scala:107:25]
input [5:0] auto_routers_ingress_nodes_in_0_flit_bits_egress_id, // @[LazyModuleImp.scala:107:25]
output auto_routers_source_nodes_out_flit_0_valid, // @[LazyModuleImp.scala:107:25]
output auto_routers_source_nodes_out_flit_0_bits_head, // @[LazyModuleImp.scala:107:25]
output auto_routers_source_nodes_out_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25]
output [72:0] auto_routers_source_nodes_out_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_routers_source_nodes_out_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25]
output [5:0] auto_routers_source_nodes_out_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_routers_source_nodes_out_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25]
output [5:0] auto_routers_source_nodes_out_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_routers_source_nodes_out_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25]
output [4:0] auto_routers_source_nodes_out_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25]
input [21:0] auto_routers_source_nodes_out_credit_return, // @[LazyModuleImp.scala:107:25]
input [21:0] auto_routers_source_nodes_out_vc_free, // @[LazyModuleImp.scala:107:25]
input auto_routers_dest_nodes_in_flit_0_valid, // @[LazyModuleImp.scala:107:25]
input auto_routers_dest_nodes_in_flit_0_bits_head, // @[LazyModuleImp.scala:107:25]
input auto_routers_dest_nodes_in_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25]
input [72:0] auto_routers_dest_nodes_in_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_routers_dest_nodes_in_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25]
input [5:0] auto_routers_dest_nodes_in_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_routers_dest_nodes_in_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25]
input [5:0] auto_routers_dest_nodes_in_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_routers_dest_nodes_in_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25]
input [4:0] auto_routers_dest_nodes_in_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25]
output [21:0] auto_routers_dest_nodes_in_credit_return, // @[LazyModuleImp.scala:107:25]
output [21:0] auto_routers_dest_nodes_in_vc_free, // @[LazyModuleImp.scala:107:25]
input auto_clock_in_clock, // @[LazyModuleImp.scala:107:25]
input auto_clock_in_reset // @[LazyModuleImp.scala:107:25]
);
Router_12 routers ( // @[NoC.scala:67:22]
.clock (auto_clock_in_clock),
.reset (auto_clock_in_reset),
.auto_debug_out_va_stall_0 (auto_routers_debug_out_va_stall_0),
.auto_debug_out_va_stall_1 (auto_routers_debug_out_va_stall_1),
.auto_debug_out_va_stall_2 (auto_routers_debug_out_va_stall_2),
.auto_debug_out_va_stall_3 (auto_routers_debug_out_va_stall_3),
.auto_debug_out_sa_stall_0 (auto_routers_debug_out_sa_stall_0),
.auto_debug_out_sa_stall_1 (auto_routers_debug_out_sa_stall_1),
.auto_debug_out_sa_stall_2 (auto_routers_debug_out_sa_stall_2),
.auto_debug_out_sa_stall_3 (auto_routers_debug_out_sa_stall_3),
.auto_egress_nodes_out_1_flit_ready (auto_routers_egress_nodes_out_1_flit_ready),
.auto_egress_nodes_out_1_flit_valid (auto_routers_egress_nodes_out_1_flit_valid),
.auto_egress_nodes_out_1_flit_bits_head (auto_routers_egress_nodes_out_1_flit_bits_head),
.auto_egress_nodes_out_1_flit_bits_tail (auto_routers_egress_nodes_out_1_flit_bits_tail),
.auto_egress_nodes_out_1_flit_bits_payload (auto_routers_egress_nodes_out_1_flit_bits_payload),
.auto_egress_nodes_out_0_flit_ready (auto_routers_egress_nodes_out_0_flit_ready),
.auto_egress_nodes_out_0_flit_valid (auto_routers_egress_nodes_out_0_flit_valid),
.auto_egress_nodes_out_0_flit_bits_head (auto_routers_egress_nodes_out_0_flit_bits_head),
.auto_egress_nodes_out_0_flit_bits_tail (auto_routers_egress_nodes_out_0_flit_bits_tail),
.auto_egress_nodes_out_0_flit_bits_payload (auto_routers_egress_nodes_out_0_flit_bits_payload),
.auto_ingress_nodes_in_2_flit_ready (auto_routers_ingress_nodes_in_2_flit_ready),
.auto_ingress_nodes_in_2_flit_valid (auto_routers_ingress_nodes_in_2_flit_valid),
.auto_ingress_nodes_in_2_flit_bits_head (auto_routers_ingress_nodes_in_2_flit_bits_head),
.auto_ingress_nodes_in_2_flit_bits_payload (auto_routers_ingress_nodes_in_2_flit_bits_payload),
.auto_ingress_nodes_in_2_flit_bits_egress_id (auto_routers_ingress_nodes_in_2_flit_bits_egress_id),
.auto_ingress_nodes_in_1_flit_ready (auto_routers_ingress_nodes_in_1_flit_ready),
.auto_ingress_nodes_in_1_flit_valid (auto_routers_ingress_nodes_in_1_flit_valid),
.auto_ingress_nodes_in_1_flit_bits_head (auto_routers_ingress_nodes_in_1_flit_bits_head),
.auto_ingress_nodes_in_1_flit_bits_tail (auto_routers_ingress_nodes_in_1_flit_bits_tail),
.auto_ingress_nodes_in_1_flit_bits_payload (auto_routers_ingress_nodes_in_1_flit_bits_payload),
.auto_ingress_nodes_in_1_flit_bits_egress_id (auto_routers_ingress_nodes_in_1_flit_bits_egress_id),
.auto_ingress_nodes_in_0_flit_ready (auto_routers_ingress_nodes_in_0_flit_ready),
.auto_ingress_nodes_in_0_flit_valid (auto_routers_ingress_nodes_in_0_flit_valid),
.auto_ingress_nodes_in_0_flit_bits_head (auto_routers_ingress_nodes_in_0_flit_bits_head),
.auto_ingress_nodes_in_0_flit_bits_tail (auto_routers_ingress_nodes_in_0_flit_bits_tail),
.auto_ingress_nodes_in_0_flit_bits_payload (auto_routers_ingress_nodes_in_0_flit_bits_payload),
.auto_ingress_nodes_in_0_flit_bits_egress_id (auto_routers_ingress_nodes_in_0_flit_bits_egress_id),
.auto_source_nodes_out_flit_0_valid (auto_routers_source_nodes_out_flit_0_valid),
.auto_source_nodes_out_flit_0_bits_head (auto_routers_source_nodes_out_flit_0_bits_head),
.auto_source_nodes_out_flit_0_bits_tail (auto_routers_source_nodes_out_flit_0_bits_tail),
.auto_source_nodes_out_flit_0_bits_payload (auto_routers_source_nodes_out_flit_0_bits_payload),
.auto_source_nodes_out_flit_0_bits_flow_vnet_id (auto_routers_source_nodes_out_flit_0_bits_flow_vnet_id),
.auto_source_nodes_out_flit_0_bits_flow_ingress_node (auto_routers_source_nodes_out_flit_0_bits_flow_ingress_node),
.auto_source_nodes_out_flit_0_bits_flow_ingress_node_id (auto_routers_source_nodes_out_flit_0_bits_flow_ingress_node_id),
.auto_source_nodes_out_flit_0_bits_flow_egress_node (auto_routers_source_nodes_out_flit_0_bits_flow_egress_node),
.auto_source_nodes_out_flit_0_bits_flow_egress_node_id (auto_routers_source_nodes_out_flit_0_bits_flow_egress_node_id),
.auto_source_nodes_out_flit_0_bits_virt_channel_id (auto_routers_source_nodes_out_flit_0_bits_virt_channel_id),
.auto_source_nodes_out_credit_return (auto_routers_source_nodes_out_credit_return),
.auto_source_nodes_out_vc_free (auto_routers_source_nodes_out_vc_free),
.auto_dest_nodes_in_flit_0_valid (auto_routers_dest_nodes_in_flit_0_valid),
.auto_dest_nodes_in_flit_0_bits_head (auto_routers_dest_nodes_in_flit_0_bits_head),
.auto_dest_nodes_in_flit_0_bits_tail (auto_routers_dest_nodes_in_flit_0_bits_tail),
.auto_dest_nodes_in_flit_0_bits_payload (auto_routers_dest_nodes_in_flit_0_bits_payload),
.auto_dest_nodes_in_flit_0_bits_flow_vnet_id (auto_routers_dest_nodes_in_flit_0_bits_flow_vnet_id),
.auto_dest_nodes_in_flit_0_bits_flow_ingress_node (auto_routers_dest_nodes_in_flit_0_bits_flow_ingress_node),
.auto_dest_nodes_in_flit_0_bits_flow_ingress_node_id (auto_routers_dest_nodes_in_flit_0_bits_flow_ingress_node_id),
.auto_dest_nodes_in_flit_0_bits_flow_egress_node (auto_routers_dest_nodes_in_flit_0_bits_flow_egress_node),
.auto_dest_nodes_in_flit_0_bits_flow_egress_node_id (auto_routers_dest_nodes_in_flit_0_bits_flow_egress_node_id),
.auto_dest_nodes_in_flit_0_bits_virt_channel_id (auto_routers_dest_nodes_in_flit_0_bits_virt_channel_id),
.auto_dest_nodes_in_credit_return (auto_routers_dest_nodes_in_credit_return),
.auto_dest_nodes_in_vc_free (auto_routers_dest_nodes_in_vc_free)
); // @[NoC.scala:67:22]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File PE.scala:
// See README.md for license details.
package gemmini
import chisel3._
import chisel3.util._
class PEControl[T <: Data : Arithmetic](accType: T) extends Bundle {
val dataflow = UInt(1.W) // TODO make this an Enum
val propagate = UInt(1.W) // Which register should be propagated (and which should be accumulated)?
val shift = UInt(log2Up(accType.getWidth).W) // TODO this isn't correct for Floats
}
class MacUnit[T <: Data](inputType: T, cType: T, dType: T) (implicit ev: Arithmetic[T]) extends Module {
import ev._
val io = IO(new Bundle {
val in_a = Input(inputType)
val in_b = Input(inputType)
val in_c = Input(cType)
val out_d = Output(dType)
})
io.out_d := io.in_c.mac(io.in_a, io.in_b)
}
// TODO update documentation
/**
* A PE implementing a MAC operation. Configured as fully combinational when integrated into a Mesh.
* @param width Data width of operands
*/
class PE[T <: Data](inputType: T, outputType: T, accType: T, df: Dataflow.Value, max_simultaneous_matmuls: Int)
(implicit ev: Arithmetic[T]) extends Module { // Debugging variables
import ev._
val io = IO(new Bundle {
val in_a = Input(inputType)
val in_b = Input(outputType)
val in_d = Input(outputType)
val out_a = Output(inputType)
val out_b = Output(outputType)
val out_c = Output(outputType)
val in_control = Input(new PEControl(accType))
val out_control = Output(new PEControl(accType))
val in_id = Input(UInt(log2Up(max_simultaneous_matmuls).W))
val out_id = Output(UInt(log2Up(max_simultaneous_matmuls).W))
val in_last = Input(Bool())
val out_last = Output(Bool())
val in_valid = Input(Bool())
val out_valid = Output(Bool())
val bad_dataflow = Output(Bool())
})
val cType = if (df == Dataflow.WS) inputType else accType
// When creating PEs that support multiple dataflows, the
// elaboration/synthesis tools often fail to consolidate and de-duplicate
// MAC units. To force mac circuitry to be re-used, we create a "mac_unit"
// module here which just performs a single MAC operation
val mac_unit = Module(new MacUnit(inputType,
if (df == Dataflow.WS) outputType else accType, outputType))
val a = io.in_a
val b = io.in_b
val d = io.in_d
val c1 = Reg(cType)
val c2 = Reg(cType)
val dataflow = io.in_control.dataflow
val prop = io.in_control.propagate
val shift = io.in_control.shift
val id = io.in_id
val last = io.in_last
val valid = io.in_valid
io.out_a := a
io.out_control.dataflow := dataflow
io.out_control.propagate := prop
io.out_control.shift := shift
io.out_id := id
io.out_last := last
io.out_valid := valid
mac_unit.io.in_a := a
val last_s = RegEnable(prop, valid)
val flip = last_s =/= prop
val shift_offset = Mux(flip, shift, 0.U)
// Which dataflow are we using?
val OUTPUT_STATIONARY = Dataflow.OS.id.U(1.W)
val WEIGHT_STATIONARY = Dataflow.WS.id.U(1.W)
// Is c1 being computed on, or propagated forward (in the output-stationary dataflow)?
val COMPUTE = 0.U(1.W)
val PROPAGATE = 1.U(1.W)
io.bad_dataflow := false.B
when ((df == Dataflow.OS).B || ((df == Dataflow.BOTH).B && dataflow === OUTPUT_STATIONARY)) {
when(prop === PROPAGATE) {
io.out_c := (c1 >> shift_offset).clippedToWidthOf(outputType)
io.out_b := b
mac_unit.io.in_b := b.asTypeOf(inputType)
mac_unit.io.in_c := c2
c2 := mac_unit.io.out_d
c1 := d.withWidthOf(cType)
}.otherwise {
io.out_c := (c2 >> shift_offset).clippedToWidthOf(outputType)
io.out_b := b
mac_unit.io.in_b := b.asTypeOf(inputType)
mac_unit.io.in_c := c1
c1 := mac_unit.io.out_d
c2 := d.withWidthOf(cType)
}
}.elsewhen ((df == Dataflow.WS).B || ((df == Dataflow.BOTH).B && dataflow === WEIGHT_STATIONARY)) {
when(prop === PROPAGATE) {
io.out_c := c1
mac_unit.io.in_b := c2.asTypeOf(inputType)
mac_unit.io.in_c := b
io.out_b := mac_unit.io.out_d
c1 := d
}.otherwise {
io.out_c := c2
mac_unit.io.in_b := c1.asTypeOf(inputType)
mac_unit.io.in_c := b
io.out_b := mac_unit.io.out_d
c2 := d
}
}.otherwise {
io.bad_dataflow := true.B
//assert(false.B, "unknown dataflow")
io.out_c := DontCare
io.out_b := DontCare
mac_unit.io.in_b := b.asTypeOf(inputType)
mac_unit.io.in_c := c2
}
when (!valid) {
c1 := c1
c2 := c2
mac_unit.io.in_b := DontCare
mac_unit.io.in_c := DontCare
}
}
File Arithmetic.scala:
// A simple type class for Chisel datatypes that can add and multiply. To add your own type, simply create your own:
// implicit MyTypeArithmetic extends Arithmetic[MyType] { ... }
package gemmini
import chisel3._
import chisel3.util._
import hardfloat._
// Bundles that represent the raw bits of custom datatypes
case class Float(expWidth: Int, sigWidth: Int) extends Bundle {
val bits = UInt((expWidth + sigWidth).W)
val bias: Int = (1 << (expWidth-1)) - 1
}
case class DummySInt(w: Int) extends Bundle {
val bits = UInt(w.W)
def dontCare: DummySInt = {
val o = Wire(new DummySInt(w))
o.bits := 0.U
o
}
}
// The Arithmetic typeclass which implements various arithmetic operations on custom datatypes
abstract class Arithmetic[T <: Data] {
implicit def cast(t: T): ArithmeticOps[T]
}
abstract class ArithmeticOps[T <: Data](self: T) {
def *(t: T): T
def mac(m1: T, m2: T): T // Returns (m1 * m2 + self)
def +(t: T): T
def -(t: T): T
def >>(u: UInt): T // This is a rounding shift! Rounds away from 0
def >(t: T): Bool
def identity: T
def withWidthOf(t: T): T
def clippedToWidthOf(t: T): T // Like "withWidthOf", except that it saturates
def relu: T
def zero: T
def minimum: T
// Optional parameters, which only need to be defined if you want to enable various optimizations for transformers
def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[T])] = None
def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[T])] = None
def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = None
def mult_with_reciprocal[U <: Data](reciprocal: U) = self
}
object Arithmetic {
implicit object UIntArithmetic extends Arithmetic[UInt] {
override implicit def cast(self: UInt) = new ArithmeticOps(self) {
override def *(t: UInt) = self * t
override def mac(m1: UInt, m2: UInt) = m1 * m2 + self
override def +(t: UInt) = self + t
override def -(t: UInt) = self - t
override def >>(u: UInt) = {
// The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm
// TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here?
val point_five = Mux(u === 0.U, 0.U, self(u - 1.U))
val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U
val ones_digit = self(u)
val r = point_five & (zeros | ones_digit)
(self >> u).asUInt + r
}
override def >(t: UInt): Bool = self > t
override def withWidthOf(t: UInt) = self.asTypeOf(t)
override def clippedToWidthOf(t: UInt) = {
val sat = ((1 << (t.getWidth-1))-1).U
Mux(self > sat, sat, self)(t.getWidth-1, 0)
}
override def relu: UInt = self
override def zero: UInt = 0.U
override def identity: UInt = 1.U
override def minimum: UInt = 0.U
}
}
implicit object SIntArithmetic extends Arithmetic[SInt] {
override implicit def cast(self: SInt) = new ArithmeticOps(self) {
override def *(t: SInt) = self * t
override def mac(m1: SInt, m2: SInt) = m1 * m2 + self
override def +(t: SInt) = self + t
override def -(t: SInt) = self - t
override def >>(u: UInt) = {
// The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm
// TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here?
val point_five = Mux(u === 0.U, 0.U, self(u - 1.U))
val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U
val ones_digit = self(u)
val r = (point_five & (zeros | ones_digit)).asBool
(self >> u).asSInt + Mux(r, 1.S, 0.S)
}
override def >(t: SInt): Bool = self > t
override def withWidthOf(t: SInt) = {
if (self.getWidth >= t.getWidth)
self(t.getWidth-1, 0).asSInt
else {
val sign_bits = t.getWidth - self.getWidth
val sign = self(self.getWidth-1)
Cat(Cat(Seq.fill(sign_bits)(sign)), self).asTypeOf(t)
}
}
override def clippedToWidthOf(t: SInt): SInt = {
val maxsat = ((1 << (t.getWidth-1))-1).S
val minsat = (-(1 << (t.getWidth-1))).S
MuxCase(self, Seq((self > maxsat) -> maxsat, (self < minsat) -> minsat))(t.getWidth-1, 0).asSInt
}
override def relu: SInt = Mux(self >= 0.S, self, 0.S)
override def zero: SInt = 0.S
override def identity: SInt = 1.S
override def minimum: SInt = (-(1 << (self.getWidth-1))).S
override def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = {
// TODO this uses a floating point divider, but we should use an integer divider instead
val input = Wire(Decoupled(denom_t.cloneType))
val output = Wire(Decoupled(self.cloneType))
// We translate our integer to floating-point form so that we can use the hardfloat divider
val expWidth = log2Up(self.getWidth) + 1
val sigWidth = self.getWidth
def sin_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def uin_to_float(x: UInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := false.B
in_to_rec_fn.io.in := x
in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def float_to_in(x: UInt) = {
val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth))
rec_fn_to_in.io.signedOut := true.B
rec_fn_to_in.io.in := x
rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
rec_fn_to_in.io.out.asSInt
}
val self_rec = sin_to_float(self)
val denom_rec = uin_to_float(input.bits)
// Instantiate the hardloat divider
val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options))
input.ready := divider.io.inReady
divider.io.inValid := input.valid
divider.io.sqrtOp := false.B
divider.io.a := self_rec
divider.io.b := denom_rec
divider.io.roundingMode := consts.round_minMag
divider.io.detectTininess := consts.tininess_afterRounding
output.valid := divider.io.outValid_div
output.bits := float_to_in(divider.io.out)
assert(!output.valid || output.ready)
Some((input, output))
}
override def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = {
// TODO this uses a floating point divider, but we should use an integer divider instead
val input = Wire(Decoupled(UInt(0.W)))
val output = Wire(Decoupled(self.cloneType))
input.bits := DontCare
// We translate our integer to floating-point form so that we can use the hardfloat divider
val expWidth = log2Up(self.getWidth) + 1
val sigWidth = self.getWidth
def in_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def float_to_in(x: UInt) = {
val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth))
rec_fn_to_in.io.signedOut := true.B
rec_fn_to_in.io.in := x
rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
rec_fn_to_in.io.out.asSInt
}
val self_rec = in_to_float(self)
// Instantiate the hardloat sqrt
val sqrter = Module(new DivSqrtRecFN_small(expWidth, sigWidth, 0))
input.ready := sqrter.io.inReady
sqrter.io.inValid := input.valid
sqrter.io.sqrtOp := true.B
sqrter.io.a := self_rec
sqrter.io.b := DontCare
sqrter.io.roundingMode := consts.round_minMag
sqrter.io.detectTininess := consts.tininess_afterRounding
output.valid := sqrter.io.outValid_sqrt
output.bits := float_to_in(sqrter.io.out)
assert(!output.valid || output.ready)
Some((input, output))
}
override def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = u match {
case Float(expWidth, sigWidth) =>
val input = Wire(Decoupled(UInt(0.W)))
val output = Wire(Decoupled(u.cloneType))
input.bits := DontCare
// We translate our integer to floating-point form so that we can use the hardfloat divider
def in_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
val self_rec = in_to_float(self)
val one_rec = in_to_float(1.S)
// Instantiate the hardloat divider
val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options))
input.ready := divider.io.inReady
divider.io.inValid := input.valid
divider.io.sqrtOp := false.B
divider.io.a := one_rec
divider.io.b := self_rec
divider.io.roundingMode := consts.round_near_even
divider.io.detectTininess := consts.tininess_afterRounding
output.valid := divider.io.outValid_div
output.bits := fNFromRecFN(expWidth, sigWidth, divider.io.out).asTypeOf(u)
assert(!output.valid || output.ready)
Some((input, output))
case _ => None
}
override def mult_with_reciprocal[U <: Data](reciprocal: U): SInt = reciprocal match {
case recip @ Float(expWidth, sigWidth) =>
def in_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def float_to_in(x: UInt) = {
val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth))
rec_fn_to_in.io.signedOut := true.B
rec_fn_to_in.io.in := x
rec_fn_to_in.io.roundingMode := consts.round_minMag
rec_fn_to_in.io.out.asSInt
}
val self_rec = in_to_float(self)
val reciprocal_rec = recFNFromFN(expWidth, sigWidth, recip.bits)
// Instantiate the hardloat divider
val muladder = Module(new MulRecFN(expWidth, sigWidth))
muladder.io.roundingMode := consts.round_near_even
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := self_rec
muladder.io.b := reciprocal_rec
float_to_in(muladder.io.out)
case _ => self
}
}
}
implicit object FloatArithmetic extends Arithmetic[Float] {
// TODO Floating point arithmetic currently switches between recoded and standard formats for every operation. However, it should stay in the recoded format as it travels through the systolic array
override implicit def cast(self: Float): ArithmeticOps[Float] = new ArithmeticOps(self) {
override def *(t: Float): Float = {
val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth))
t_resizer.io.in := t_rec
t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
t_resizer.io.detectTininess := consts.tininess_afterRounding
val t_rec_resized = t_resizer.io.out
val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth))
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := self_rec
muladder.io.b := t_rec_resized
val out = Wire(Float(self.expWidth, self.sigWidth))
out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
out
}
override def mac(m1: Float, m2: Float): Float = {
// Recode all operands
val m1_rec = recFNFromFN(m1.expWidth, m1.sigWidth, m1.bits)
val m2_rec = recFNFromFN(m2.expWidth, m2.sigWidth, m2.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Resize m1 to self's width
val m1_resizer = Module(new RecFNToRecFN(m1.expWidth, m1.sigWidth, self.expWidth, self.sigWidth))
m1_resizer.io.in := m1_rec
m1_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
m1_resizer.io.detectTininess := consts.tininess_afterRounding
val m1_rec_resized = m1_resizer.io.out
// Resize m2 to self's width
val m2_resizer = Module(new RecFNToRecFN(m2.expWidth, m2.sigWidth, self.expWidth, self.sigWidth))
m2_resizer.io.in := m2_rec
m2_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
m2_resizer.io.detectTininess := consts.tininess_afterRounding
val m2_rec_resized = m2_resizer.io.out
// Perform multiply-add
val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth))
muladder.io.op := 0.U
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := m1_rec_resized
muladder.io.b := m2_rec_resized
muladder.io.c := self_rec
// Convert result to standard format // TODO remove these intermediate recodings
val out = Wire(Float(self.expWidth, self.sigWidth))
out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
out
}
override def +(t: Float): Float = {
require(self.getWidth >= t.getWidth) // This just makes it easier to write the resizing code
// Recode all operands
val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Generate 1 as a float
val in_to_rec_fn = Module(new INToRecFN(1, self.expWidth, self.sigWidth))
in_to_rec_fn.io.signedIn := false.B
in_to_rec_fn.io.in := 1.U
in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
val one_rec = in_to_rec_fn.io.out
// Resize t
val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth))
t_resizer.io.in := t_rec
t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
t_resizer.io.detectTininess := consts.tininess_afterRounding
val t_rec_resized = t_resizer.io.out
// Perform addition
val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth))
muladder.io.op := 0.U
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := t_rec_resized
muladder.io.b := one_rec
muladder.io.c := self_rec
val result = Wire(Float(self.expWidth, self.sigWidth))
result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
result
}
override def -(t: Float): Float = {
val t_sgn = t.bits(t.getWidth-1)
val neg_t = Cat(~t_sgn, t.bits(t.getWidth-2,0)).asTypeOf(t)
self + neg_t
}
override def >>(u: UInt): Float = {
// Recode self
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Get 2^(-u) as a recoded float
val shift_exp = Wire(UInt(self.expWidth.W))
shift_exp := self.bias.U - u
val shift_fn = Cat(0.U(1.W), shift_exp, 0.U((self.sigWidth-1).W))
val shift_rec = recFNFromFN(self.expWidth, self.sigWidth, shift_fn)
assert(shift_exp =/= 0.U, "scaling by denormalized numbers is not currently supported")
// Multiply self and 2^(-u)
val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth))
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := self_rec
muladder.io.b := shift_rec
val result = Wire(Float(self.expWidth, self.sigWidth))
result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
result
}
override def >(t: Float): Bool = {
// Recode all operands
val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Resize t to self's width
val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth))
t_resizer.io.in := t_rec
t_resizer.io.roundingMode := consts.round_near_even
t_resizer.io.detectTininess := consts.tininess_afterRounding
val t_rec_resized = t_resizer.io.out
val comparator = Module(new CompareRecFN(self.expWidth, self.sigWidth))
comparator.io.a := self_rec
comparator.io.b := t_rec_resized
comparator.io.signaling := false.B
comparator.io.gt
}
override def withWidthOf(t: Float): Float = {
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth))
resizer.io.in := self_rec
resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
resizer.io.detectTininess := consts.tininess_afterRounding
val result = Wire(Float(t.expWidth, t.sigWidth))
result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out)
result
}
override def clippedToWidthOf(t: Float): Float = {
// TODO check for overflow. Right now, we just assume that overflow doesn't happen
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth))
resizer.io.in := self_rec
resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
resizer.io.detectTininess := consts.tininess_afterRounding
val result = Wire(Float(t.expWidth, t.sigWidth))
result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out)
result
}
override def relu: Float = {
val raw = rawFloatFromFN(self.expWidth, self.sigWidth, self.bits)
val result = Wire(Float(self.expWidth, self.sigWidth))
result.bits := Mux(!raw.isZero && raw.sign, 0.U, self.bits)
result
}
override def zero: Float = 0.U.asTypeOf(self)
override def identity: Float = Cat(0.U(2.W), ~(0.U((self.expWidth-1).W)), 0.U((self.sigWidth-1).W)).asTypeOf(self)
override def minimum: Float = Cat(1.U, ~(0.U(self.expWidth.W)), 0.U((self.sigWidth-1).W)).asTypeOf(self)
}
}
implicit object DummySIntArithmetic extends Arithmetic[DummySInt] {
override implicit def cast(self: DummySInt) = new ArithmeticOps(self) {
override def *(t: DummySInt) = self.dontCare
override def mac(m1: DummySInt, m2: DummySInt) = self.dontCare
override def +(t: DummySInt) = self.dontCare
override def -(t: DummySInt) = self.dontCare
override def >>(t: UInt) = self.dontCare
override def >(t: DummySInt): Bool = false.B
override def identity = self.dontCare
override def withWidthOf(t: DummySInt) = self.dontCare
override def clippedToWidthOf(t: DummySInt) = self.dontCare
override def relu = self.dontCare
override def zero = self.dontCare
override def minimum: DummySInt = self.dontCare
}
}
}
| module PE_292( // @[PE.scala:31:7]
input clock, // @[PE.scala:31:7]
input reset, // @[PE.scala:31:7]
input [7:0] io_in_a, // @[PE.scala:35:14]
input [19:0] io_in_b, // @[PE.scala:35:14]
input [19:0] io_in_d, // @[PE.scala:35:14]
output [7:0] io_out_a, // @[PE.scala:35:14]
output [19:0] io_out_b, // @[PE.scala:35:14]
output [19:0] io_out_c, // @[PE.scala:35:14]
input io_in_control_dataflow, // @[PE.scala:35:14]
input io_in_control_propagate, // @[PE.scala:35:14]
input [4:0] io_in_control_shift, // @[PE.scala:35:14]
output io_out_control_dataflow, // @[PE.scala:35:14]
output io_out_control_propagate, // @[PE.scala:35:14]
output [4:0] io_out_control_shift, // @[PE.scala:35:14]
input [2:0] io_in_id, // @[PE.scala:35:14]
output [2:0] io_out_id, // @[PE.scala:35:14]
input io_in_last, // @[PE.scala:35:14]
output io_out_last, // @[PE.scala:35:14]
input io_in_valid, // @[PE.scala:35:14]
output io_out_valid, // @[PE.scala:35:14]
output io_bad_dataflow // @[PE.scala:35:14]
);
wire [19:0] _mac_unit_io_out_d; // @[PE.scala:64:24]
wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:31:7]
wire [19:0] io_in_b_0 = io_in_b; // @[PE.scala:31:7]
wire [19:0] io_in_d_0 = io_in_d; // @[PE.scala:31:7]
wire io_in_control_dataflow_0 = io_in_control_dataflow; // @[PE.scala:31:7]
wire io_in_control_propagate_0 = io_in_control_propagate; // @[PE.scala:31:7]
wire [4:0] io_in_control_shift_0 = io_in_control_shift; // @[PE.scala:31:7]
wire [2:0] io_in_id_0 = io_in_id; // @[PE.scala:31:7]
wire io_in_last_0 = io_in_last; // @[PE.scala:31:7]
wire io_in_valid_0 = io_in_valid; // @[PE.scala:31:7]
wire io_bad_dataflow_0 = 1'h0; // @[PE.scala:31:7]
wire [7:0] io_out_a_0 = io_in_a_0; // @[PE.scala:31:7]
wire [19:0] _mac_unit_io_in_b_T = io_in_b_0; // @[PE.scala:31:7, :106:37]
wire [19:0] _mac_unit_io_in_b_T_2 = io_in_b_0; // @[PE.scala:31:7, :113:37]
wire [19:0] _mac_unit_io_in_b_T_8 = io_in_b_0; // @[PE.scala:31:7, :137:35]
wire [19:0] c1_lo_1 = io_in_d_0; // @[PE.scala:31:7]
wire [19:0] c2_lo_1 = io_in_d_0; // @[PE.scala:31:7]
wire io_out_control_dataflow_0 = io_in_control_dataflow_0; // @[PE.scala:31:7]
wire io_out_control_propagate_0 = io_in_control_propagate_0; // @[PE.scala:31:7]
wire [4:0] io_out_control_shift_0 = io_in_control_shift_0; // @[PE.scala:31:7]
wire [2:0] io_out_id_0 = io_in_id_0; // @[PE.scala:31:7]
wire io_out_last_0 = io_in_last_0; // @[PE.scala:31:7]
wire io_out_valid_0 = io_in_valid_0; // @[PE.scala:31:7]
wire [19:0] io_out_b_0; // @[PE.scala:31:7]
wire [19:0] io_out_c_0; // @[PE.scala:31:7]
reg [31:0] c1; // @[PE.scala:70:15]
wire [31:0] _io_out_c_zeros_T_1 = c1; // @[PE.scala:70:15]
wire [31:0] _mac_unit_io_in_b_T_6 = c1; // @[PE.scala:70:15, :127:38]
reg [31:0] c2; // @[PE.scala:71:15]
wire [31:0] _io_out_c_zeros_T_10 = c2; // @[PE.scala:71:15]
wire [31:0] _mac_unit_io_in_b_T_4 = c2; // @[PE.scala:71:15, :121:38]
reg last_s; // @[PE.scala:89:25]
wire flip = last_s != io_in_control_propagate_0; // @[PE.scala:31:7, :89:25, :90:21]
wire [4:0] shift_offset = flip ? io_in_control_shift_0 : 5'h0; // @[PE.scala:31:7, :90:21, :91:25]
wire _GEN = shift_offset == 5'h0; // @[PE.scala:91:25]
wire _io_out_c_point_five_T; // @[Arithmetic.scala:101:32]
assign _io_out_c_point_five_T = _GEN; // @[Arithmetic.scala:101:32]
wire _io_out_c_point_five_T_5; // @[Arithmetic.scala:101:32]
assign _io_out_c_point_five_T_5 = _GEN; // @[Arithmetic.scala:101:32]
wire [5:0] _GEN_0 = {1'h0, shift_offset} - 6'h1; // @[PE.scala:91:25]
wire [5:0] _io_out_c_point_five_T_1; // @[Arithmetic.scala:101:53]
assign _io_out_c_point_five_T_1 = _GEN_0; // @[Arithmetic.scala:101:53]
wire [5:0] _io_out_c_zeros_T_2; // @[Arithmetic.scala:102:66]
assign _io_out_c_zeros_T_2 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66]
wire [5:0] _io_out_c_point_five_T_6; // @[Arithmetic.scala:101:53]
assign _io_out_c_point_five_T_6 = _GEN_0; // @[Arithmetic.scala:101:53]
wire [5:0] _io_out_c_zeros_T_11; // @[Arithmetic.scala:102:66]
assign _io_out_c_zeros_T_11 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66]
wire [4:0] _io_out_c_point_five_T_2 = _io_out_c_point_five_T_1[4:0]; // @[Arithmetic.scala:101:53]
wire [31:0] _io_out_c_point_five_T_3 = $signed($signed(c1) >>> _io_out_c_point_five_T_2); // @[PE.scala:70:15]
wire _io_out_c_point_five_T_4 = _io_out_c_point_five_T_3[0]; // @[Arithmetic.scala:101:50]
wire io_out_c_point_five = ~_io_out_c_point_five_T & _io_out_c_point_five_T_4; // @[Arithmetic.scala:101:{29,32,50}]
wire _GEN_1 = shift_offset < 5'h2; // @[PE.scala:91:25]
wire _io_out_c_zeros_T; // @[Arithmetic.scala:102:27]
assign _io_out_c_zeros_T = _GEN_1; // @[Arithmetic.scala:102:27]
wire _io_out_c_zeros_T_9; // @[Arithmetic.scala:102:27]
assign _io_out_c_zeros_T_9 = _GEN_1; // @[Arithmetic.scala:102:27]
wire [4:0] _io_out_c_zeros_T_3 = _io_out_c_zeros_T_2[4:0]; // @[Arithmetic.scala:102:66]
wire [31:0] _io_out_c_zeros_T_4 = 32'h1 << _io_out_c_zeros_T_3; // @[Arithmetic.scala:102:{60,66}]
wire [32:0] _io_out_c_zeros_T_5 = {1'h0, _io_out_c_zeros_T_4} - 33'h1; // @[Arithmetic.scala:102:{60,81}]
wire [31:0] _io_out_c_zeros_T_6 = _io_out_c_zeros_T_5[31:0]; // @[Arithmetic.scala:102:81]
wire [31:0] _io_out_c_zeros_T_7 = _io_out_c_zeros_T_1 & _io_out_c_zeros_T_6; // @[Arithmetic.scala:102:{45,52,81}]
wire [31:0] _io_out_c_zeros_T_8 = _io_out_c_zeros_T ? 32'h0 : _io_out_c_zeros_T_7; // @[Arithmetic.scala:102:{24,27,52}]
wire io_out_c_zeros = |_io_out_c_zeros_T_8; // @[Arithmetic.scala:102:{24,89}]
wire [31:0] _GEN_2 = {27'h0, shift_offset}; // @[PE.scala:91:25]
wire [31:0] _GEN_3 = $signed($signed(c1) >>> _GEN_2); // @[PE.scala:70:15]
wire [31:0] _io_out_c_ones_digit_T; // @[Arithmetic.scala:103:30]
assign _io_out_c_ones_digit_T = _GEN_3; // @[Arithmetic.scala:103:30]
wire [31:0] _io_out_c_T; // @[Arithmetic.scala:107:15]
assign _io_out_c_T = _GEN_3; // @[Arithmetic.scala:103:30, :107:15]
wire io_out_c_ones_digit = _io_out_c_ones_digit_T[0]; // @[Arithmetic.scala:103:30]
wire _io_out_c_r_T = io_out_c_zeros | io_out_c_ones_digit; // @[Arithmetic.scala:102:89, :103:30, :105:38]
wire _io_out_c_r_T_1 = io_out_c_point_five & _io_out_c_r_T; // @[Arithmetic.scala:101:29, :105:{29,38}]
wire io_out_c_r = _io_out_c_r_T_1; // @[Arithmetic.scala:105:{29,53}]
wire [1:0] _io_out_c_T_1 = {1'h0, io_out_c_r}; // @[Arithmetic.scala:105:53, :107:33]
wire [32:0] _io_out_c_T_2 = {_io_out_c_T[31], _io_out_c_T} + {{31{_io_out_c_T_1[1]}}, _io_out_c_T_1}; // @[Arithmetic.scala:107:{15,28,33}]
wire [31:0] _io_out_c_T_3 = _io_out_c_T_2[31:0]; // @[Arithmetic.scala:107:28]
wire [31:0] _io_out_c_T_4 = _io_out_c_T_3; // @[Arithmetic.scala:107:28]
wire _io_out_c_T_5 = $signed(_io_out_c_T_4) > 32'sh7FFFF; // @[Arithmetic.scala:107:28, :125:33]
wire _io_out_c_T_6 = $signed(_io_out_c_T_4) < -32'sh80000; // @[Arithmetic.scala:107:28, :125:60]
wire [31:0] _io_out_c_T_7 = _io_out_c_T_6 ? 32'hFFF80000 : _io_out_c_T_4; // @[Mux.scala:126:16]
wire [31:0] _io_out_c_T_8 = _io_out_c_T_5 ? 32'h7FFFF : _io_out_c_T_7; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_9 = _io_out_c_T_8[19:0]; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_10 = _io_out_c_T_9; // @[Arithmetic.scala:125:{81,99}]
wire [19:0] _mac_unit_io_in_b_T_1 = _mac_unit_io_in_b_T; // @[PE.scala:106:37]
wire [7:0] _mac_unit_io_in_b_WIRE = _mac_unit_io_in_b_T_1[7:0]; // @[PE.scala:106:37]
wire c1_sign = io_in_d_0[19]; // @[PE.scala:31:7]
wire c2_sign = io_in_d_0[19]; // @[PE.scala:31:7]
wire [1:0] _GEN_4 = {2{c1_sign}}; // @[Arithmetic.scala:117:26, :118:18]
wire [1:0] c1_lo_lo_hi; // @[Arithmetic.scala:118:18]
assign c1_lo_lo_hi = _GEN_4; // @[Arithmetic.scala:118:18]
wire [1:0] c1_lo_hi_hi; // @[Arithmetic.scala:118:18]
assign c1_lo_hi_hi = _GEN_4; // @[Arithmetic.scala:118:18]
wire [1:0] c1_hi_lo_hi; // @[Arithmetic.scala:118:18]
assign c1_hi_lo_hi = _GEN_4; // @[Arithmetic.scala:118:18]
wire [1:0] c1_hi_hi_hi; // @[Arithmetic.scala:118:18]
assign c1_hi_hi_hi = _GEN_4; // @[Arithmetic.scala:118:18]
wire [2:0] c1_lo_lo = {c1_lo_lo_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [2:0] c1_lo_hi = {c1_lo_hi_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [5:0] c1_lo = {c1_lo_hi, c1_lo_lo}; // @[Arithmetic.scala:118:18]
wire [2:0] c1_hi_lo = {c1_hi_lo_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [2:0] c1_hi_hi = {c1_hi_hi_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [5:0] c1_hi = {c1_hi_hi, c1_hi_lo}; // @[Arithmetic.scala:118:18]
wire [11:0] _c1_T = {c1_hi, c1_lo}; // @[Arithmetic.scala:118:18]
wire [31:0] _c1_T_1 = {_c1_T, c1_lo_1}; // @[Arithmetic.scala:118:{14,18}]
wire [31:0] _c1_T_2 = _c1_T_1; // @[Arithmetic.scala:118:{14,61}]
wire [31:0] _c1_WIRE = _c1_T_2; // @[Arithmetic.scala:118:61]
wire [4:0] _io_out_c_point_five_T_7 = _io_out_c_point_five_T_6[4:0]; // @[Arithmetic.scala:101:53]
wire [31:0] _io_out_c_point_five_T_8 = $signed($signed(c2) >>> _io_out_c_point_five_T_7); // @[PE.scala:71:15]
wire _io_out_c_point_five_T_9 = _io_out_c_point_five_T_8[0]; // @[Arithmetic.scala:101:50]
wire io_out_c_point_five_1 = ~_io_out_c_point_five_T_5 & _io_out_c_point_five_T_9; // @[Arithmetic.scala:101:{29,32,50}]
wire [4:0] _io_out_c_zeros_T_12 = _io_out_c_zeros_T_11[4:0]; // @[Arithmetic.scala:102:66]
wire [31:0] _io_out_c_zeros_T_13 = 32'h1 << _io_out_c_zeros_T_12; // @[Arithmetic.scala:102:{60,66}]
wire [32:0] _io_out_c_zeros_T_14 = {1'h0, _io_out_c_zeros_T_13} - 33'h1; // @[Arithmetic.scala:102:{60,81}]
wire [31:0] _io_out_c_zeros_T_15 = _io_out_c_zeros_T_14[31:0]; // @[Arithmetic.scala:102:81]
wire [31:0] _io_out_c_zeros_T_16 = _io_out_c_zeros_T_10 & _io_out_c_zeros_T_15; // @[Arithmetic.scala:102:{45,52,81}]
wire [31:0] _io_out_c_zeros_T_17 = _io_out_c_zeros_T_9 ? 32'h0 : _io_out_c_zeros_T_16; // @[Arithmetic.scala:102:{24,27,52}]
wire io_out_c_zeros_1 = |_io_out_c_zeros_T_17; // @[Arithmetic.scala:102:{24,89}]
wire [31:0] _GEN_5 = $signed($signed(c2) >>> _GEN_2); // @[PE.scala:71:15]
wire [31:0] _io_out_c_ones_digit_T_1; // @[Arithmetic.scala:103:30]
assign _io_out_c_ones_digit_T_1 = _GEN_5; // @[Arithmetic.scala:103:30]
wire [31:0] _io_out_c_T_11; // @[Arithmetic.scala:107:15]
assign _io_out_c_T_11 = _GEN_5; // @[Arithmetic.scala:103:30, :107:15]
wire io_out_c_ones_digit_1 = _io_out_c_ones_digit_T_1[0]; // @[Arithmetic.scala:103:30]
wire _io_out_c_r_T_2 = io_out_c_zeros_1 | io_out_c_ones_digit_1; // @[Arithmetic.scala:102:89, :103:30, :105:38]
wire _io_out_c_r_T_3 = io_out_c_point_five_1 & _io_out_c_r_T_2; // @[Arithmetic.scala:101:29, :105:{29,38}]
wire io_out_c_r_1 = _io_out_c_r_T_3; // @[Arithmetic.scala:105:{29,53}]
wire [1:0] _io_out_c_T_12 = {1'h0, io_out_c_r_1}; // @[Arithmetic.scala:105:53, :107:33]
wire [32:0] _io_out_c_T_13 = {_io_out_c_T_11[31], _io_out_c_T_11} + {{31{_io_out_c_T_12[1]}}, _io_out_c_T_12}; // @[Arithmetic.scala:107:{15,28,33}]
wire [31:0] _io_out_c_T_14 = _io_out_c_T_13[31:0]; // @[Arithmetic.scala:107:28]
wire [31:0] _io_out_c_T_15 = _io_out_c_T_14; // @[Arithmetic.scala:107:28]
wire _io_out_c_T_16 = $signed(_io_out_c_T_15) > 32'sh7FFFF; // @[Arithmetic.scala:107:28, :125:33]
wire _io_out_c_T_17 = $signed(_io_out_c_T_15) < -32'sh80000; // @[Arithmetic.scala:107:28, :125:60]
wire [31:0] _io_out_c_T_18 = _io_out_c_T_17 ? 32'hFFF80000 : _io_out_c_T_15; // @[Mux.scala:126:16]
wire [31:0] _io_out_c_T_19 = _io_out_c_T_16 ? 32'h7FFFF : _io_out_c_T_18; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_20 = _io_out_c_T_19[19:0]; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_21 = _io_out_c_T_20; // @[Arithmetic.scala:125:{81,99}]
wire [19:0] _mac_unit_io_in_b_T_3 = _mac_unit_io_in_b_T_2; // @[PE.scala:113:37]
wire [7:0] _mac_unit_io_in_b_WIRE_1 = _mac_unit_io_in_b_T_3[7:0]; // @[PE.scala:113:37]
wire [1:0] _GEN_6 = {2{c2_sign}}; // @[Arithmetic.scala:117:26, :118:18]
wire [1:0] c2_lo_lo_hi; // @[Arithmetic.scala:118:18]
assign c2_lo_lo_hi = _GEN_6; // @[Arithmetic.scala:118:18]
wire [1:0] c2_lo_hi_hi; // @[Arithmetic.scala:118:18]
assign c2_lo_hi_hi = _GEN_6; // @[Arithmetic.scala:118:18]
wire [1:0] c2_hi_lo_hi; // @[Arithmetic.scala:118:18]
assign c2_hi_lo_hi = _GEN_6; // @[Arithmetic.scala:118:18]
wire [1:0] c2_hi_hi_hi; // @[Arithmetic.scala:118:18]
assign c2_hi_hi_hi = _GEN_6; // @[Arithmetic.scala:118:18]
wire [2:0] c2_lo_lo = {c2_lo_lo_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [2:0] c2_lo_hi = {c2_lo_hi_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [5:0] c2_lo = {c2_lo_hi, c2_lo_lo}; // @[Arithmetic.scala:118:18]
wire [2:0] c2_hi_lo = {c2_hi_lo_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [2:0] c2_hi_hi = {c2_hi_hi_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [5:0] c2_hi = {c2_hi_hi, c2_hi_lo}; // @[Arithmetic.scala:118:18]
wire [11:0] _c2_T = {c2_hi, c2_lo}; // @[Arithmetic.scala:118:18]
wire [31:0] _c2_T_1 = {_c2_T, c2_lo_1}; // @[Arithmetic.scala:118:{14,18}]
wire [31:0] _c2_T_2 = _c2_T_1; // @[Arithmetic.scala:118:{14,61}]
wire [31:0] _c2_WIRE = _c2_T_2; // @[Arithmetic.scala:118:61]
wire [31:0] _mac_unit_io_in_b_T_5 = _mac_unit_io_in_b_T_4; // @[PE.scala:121:38]
wire [7:0] _mac_unit_io_in_b_WIRE_2 = _mac_unit_io_in_b_T_5[7:0]; // @[PE.scala:121:38]
wire [31:0] _mac_unit_io_in_b_T_7 = _mac_unit_io_in_b_T_6; // @[PE.scala:127:38]
wire [7:0] _mac_unit_io_in_b_WIRE_3 = _mac_unit_io_in_b_T_7[7:0]; // @[PE.scala:127:38]
assign io_out_c_0 = io_in_control_dataflow_0 ? (io_in_control_propagate_0 ? c1[19:0] : c2[19:0]) : io_in_control_propagate_0 ? _io_out_c_T_10 : _io_out_c_T_21; // @[PE.scala:31:7, :70:15, :71:15, :102:95, :103:30, :104:16, :111:16, :118:101, :119:30, :120:16, :126:16]
assign io_out_b_0 = io_in_control_dataflow_0 ? _mac_unit_io_out_d : io_in_b_0; // @[PE.scala:31:7, :64:24, :102:95, :103:30, :118:101]
wire [19:0] _mac_unit_io_in_b_T_9 = _mac_unit_io_in_b_T_8; // @[PE.scala:137:35]
wire [7:0] _mac_unit_io_in_b_WIRE_4 = _mac_unit_io_in_b_T_9[7:0]; // @[PE.scala:137:35]
wire [31:0] _GEN_7 = {{12{io_in_d_0[19]}}, io_in_d_0}; // @[PE.scala:31:7, :124:10]
wire [31:0] _GEN_8 = {{12{_mac_unit_io_out_d[19]}}, _mac_unit_io_out_d}; // @[PE.scala:64:24, :108:10]
always @(posedge clock) begin // @[PE.scala:31:7]
if (io_in_valid_0) begin // @[PE.scala:31:7]
if (io_in_control_dataflow_0) begin // @[PE.scala:31:7]
if (io_in_control_dataflow_0 & io_in_control_propagate_0) // @[PE.scala:31:7, :70:15, :118:101, :119:30, :124:10]
c1 <= _GEN_7; // @[PE.scala:70:15, :124:10]
if (~io_in_control_dataflow_0 | io_in_control_propagate_0) begin // @[PE.scala:31:7, :71:15, :118:101, :119:30]
end
else // @[PE.scala:71:15, :118:101, :119:30]
c2 <= _GEN_7; // @[PE.scala:71:15, :124:10]
end
else begin // @[PE.scala:31:7]
c1 <= io_in_control_propagate_0 ? _c1_WIRE : _GEN_8; // @[PE.scala:31:7, :70:15, :103:30, :108:10, :109:10, :115:10]
c2 <= io_in_control_propagate_0 ? _GEN_8 : _c2_WIRE; // @[PE.scala:31:7, :71:15, :103:30, :108:10, :116:10]
end
last_s <= io_in_control_propagate_0; // @[PE.scala:31:7, :89:25]
end
always @(posedge)
MacUnit_36 mac_unit ( // @[PE.scala:64:24]
.clock (clock),
.reset (reset),
.io_in_a (io_in_a_0), // @[PE.scala:31:7]
.io_in_b (io_in_control_dataflow_0 ? (io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE_2 : _mac_unit_io_in_b_WIRE_3) : io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE : _mac_unit_io_in_b_WIRE_1), // @[PE.scala:31:7, :102:95, :103:30, :106:{24,37}, :113:{24,37}, :118:101, :119:30, :121:{24,38}, :127:{24,38}]
.io_in_c (io_in_control_dataflow_0 ? {{12{io_in_b_0[19]}}, io_in_b_0} : io_in_control_propagate_0 ? c2 : c1), // @[PE.scala:31:7, :70:15, :71:15, :102:95, :103:30, :107:24, :114:24, :118:101, :122:24]
.io_out_d (_mac_unit_io_out_d)
); // @[PE.scala:64:24]
assign io_out_a = io_out_a_0; // @[PE.scala:31:7]
assign io_out_b = io_out_b_0; // @[PE.scala:31:7]
assign io_out_c = io_out_c_0; // @[PE.scala:31:7]
assign io_out_control_dataflow = io_out_control_dataflow_0; // @[PE.scala:31:7]
assign io_out_control_propagate = io_out_control_propagate_0; // @[PE.scala:31:7]
assign io_out_control_shift = io_out_control_shift_0; // @[PE.scala:31:7]
assign io_out_id = io_out_id_0; // @[PE.scala:31:7]
assign io_out_last = io_out_last_0; // @[PE.scala:31:7]
assign io_out_valid = io_out_valid_0; // @[PE.scala:31:7]
assign io_bad_dataflow = io_bad_dataflow_0; // @[PE.scala:31:7]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File PE.scala:
// See README.md for license details.
package gemmini
import chisel3._
import chisel3.util._
class PEControl[T <: Data : Arithmetic](accType: T) extends Bundle {
val dataflow = UInt(1.W) // TODO make this an Enum
val propagate = UInt(1.W) // Which register should be propagated (and which should be accumulated)?
val shift = UInt(log2Up(accType.getWidth).W) // TODO this isn't correct for Floats
}
class MacUnit[T <: Data](inputType: T, cType: T, dType: T) (implicit ev: Arithmetic[T]) extends Module {
import ev._
val io = IO(new Bundle {
val in_a = Input(inputType)
val in_b = Input(inputType)
val in_c = Input(cType)
val out_d = Output(dType)
})
io.out_d := io.in_c.mac(io.in_a, io.in_b)
}
// TODO update documentation
/**
* A PE implementing a MAC operation. Configured as fully combinational when integrated into a Mesh.
* @param width Data width of operands
*/
class PE[T <: Data](inputType: T, outputType: T, accType: T, df: Dataflow.Value, max_simultaneous_matmuls: Int)
(implicit ev: Arithmetic[T]) extends Module { // Debugging variables
import ev._
val io = IO(new Bundle {
val in_a = Input(inputType)
val in_b = Input(outputType)
val in_d = Input(outputType)
val out_a = Output(inputType)
val out_b = Output(outputType)
val out_c = Output(outputType)
val in_control = Input(new PEControl(accType))
val out_control = Output(new PEControl(accType))
val in_id = Input(UInt(log2Up(max_simultaneous_matmuls).W))
val out_id = Output(UInt(log2Up(max_simultaneous_matmuls).W))
val in_last = Input(Bool())
val out_last = Output(Bool())
val in_valid = Input(Bool())
val out_valid = Output(Bool())
val bad_dataflow = Output(Bool())
})
val cType = if (df == Dataflow.WS) inputType else accType
// When creating PEs that support multiple dataflows, the
// elaboration/synthesis tools often fail to consolidate and de-duplicate
// MAC units. To force mac circuitry to be re-used, we create a "mac_unit"
// module here which just performs a single MAC operation
val mac_unit = Module(new MacUnit(inputType,
if (df == Dataflow.WS) outputType else accType, outputType))
val a = io.in_a
val b = io.in_b
val d = io.in_d
val c1 = Reg(cType)
val c2 = Reg(cType)
val dataflow = io.in_control.dataflow
val prop = io.in_control.propagate
val shift = io.in_control.shift
val id = io.in_id
val last = io.in_last
val valid = io.in_valid
io.out_a := a
io.out_control.dataflow := dataflow
io.out_control.propagate := prop
io.out_control.shift := shift
io.out_id := id
io.out_last := last
io.out_valid := valid
mac_unit.io.in_a := a
val last_s = RegEnable(prop, valid)
val flip = last_s =/= prop
val shift_offset = Mux(flip, shift, 0.U)
// Which dataflow are we using?
val OUTPUT_STATIONARY = Dataflow.OS.id.U(1.W)
val WEIGHT_STATIONARY = Dataflow.WS.id.U(1.W)
// Is c1 being computed on, or propagated forward (in the output-stationary dataflow)?
val COMPUTE = 0.U(1.W)
val PROPAGATE = 1.U(1.W)
io.bad_dataflow := false.B
when ((df == Dataflow.OS).B || ((df == Dataflow.BOTH).B && dataflow === OUTPUT_STATIONARY)) {
when(prop === PROPAGATE) {
io.out_c := (c1 >> shift_offset).clippedToWidthOf(outputType)
io.out_b := b
mac_unit.io.in_b := b.asTypeOf(inputType)
mac_unit.io.in_c := c2
c2 := mac_unit.io.out_d
c1 := d.withWidthOf(cType)
}.otherwise {
io.out_c := (c2 >> shift_offset).clippedToWidthOf(outputType)
io.out_b := b
mac_unit.io.in_b := b.asTypeOf(inputType)
mac_unit.io.in_c := c1
c1 := mac_unit.io.out_d
c2 := d.withWidthOf(cType)
}
}.elsewhen ((df == Dataflow.WS).B || ((df == Dataflow.BOTH).B && dataflow === WEIGHT_STATIONARY)) {
when(prop === PROPAGATE) {
io.out_c := c1
mac_unit.io.in_b := c2.asTypeOf(inputType)
mac_unit.io.in_c := b
io.out_b := mac_unit.io.out_d
c1 := d
}.otherwise {
io.out_c := c2
mac_unit.io.in_b := c1.asTypeOf(inputType)
mac_unit.io.in_c := b
io.out_b := mac_unit.io.out_d
c2 := d
}
}.otherwise {
io.bad_dataflow := true.B
//assert(false.B, "unknown dataflow")
io.out_c := DontCare
io.out_b := DontCare
mac_unit.io.in_b := b.asTypeOf(inputType)
mac_unit.io.in_c := c2
}
when (!valid) {
c1 := c1
c2 := c2
mac_unit.io.in_b := DontCare
mac_unit.io.in_c := DontCare
}
}
File Arithmetic.scala:
// A simple type class for Chisel datatypes that can add and multiply. To add your own type, simply create your own:
// implicit MyTypeArithmetic extends Arithmetic[MyType] { ... }
package gemmini
import chisel3._
import chisel3.util._
import hardfloat._
// Bundles that represent the raw bits of custom datatypes
case class Float(expWidth: Int, sigWidth: Int) extends Bundle {
val bits = UInt((expWidth + sigWidth).W)
val bias: Int = (1 << (expWidth-1)) - 1
}
case class DummySInt(w: Int) extends Bundle {
val bits = UInt(w.W)
def dontCare: DummySInt = {
val o = Wire(new DummySInt(w))
o.bits := 0.U
o
}
}
// The Arithmetic typeclass which implements various arithmetic operations on custom datatypes
abstract class Arithmetic[T <: Data] {
implicit def cast(t: T): ArithmeticOps[T]
}
abstract class ArithmeticOps[T <: Data](self: T) {
def *(t: T): T
def mac(m1: T, m2: T): T // Returns (m1 * m2 + self)
def +(t: T): T
def -(t: T): T
def >>(u: UInt): T // This is a rounding shift! Rounds away from 0
def >(t: T): Bool
def identity: T
def withWidthOf(t: T): T
def clippedToWidthOf(t: T): T // Like "withWidthOf", except that it saturates
def relu: T
def zero: T
def minimum: T
// Optional parameters, which only need to be defined if you want to enable various optimizations for transformers
def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[T])] = None
def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[T])] = None
def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = None
def mult_with_reciprocal[U <: Data](reciprocal: U) = self
}
object Arithmetic {
implicit object UIntArithmetic extends Arithmetic[UInt] {
override implicit def cast(self: UInt) = new ArithmeticOps(self) {
override def *(t: UInt) = self * t
override def mac(m1: UInt, m2: UInt) = m1 * m2 + self
override def +(t: UInt) = self + t
override def -(t: UInt) = self - t
override def >>(u: UInt) = {
// The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm
// TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here?
val point_five = Mux(u === 0.U, 0.U, self(u - 1.U))
val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U
val ones_digit = self(u)
val r = point_five & (zeros | ones_digit)
(self >> u).asUInt + r
}
override def >(t: UInt): Bool = self > t
override def withWidthOf(t: UInt) = self.asTypeOf(t)
override def clippedToWidthOf(t: UInt) = {
val sat = ((1 << (t.getWidth-1))-1).U
Mux(self > sat, sat, self)(t.getWidth-1, 0)
}
override def relu: UInt = self
override def zero: UInt = 0.U
override def identity: UInt = 1.U
override def minimum: UInt = 0.U
}
}
implicit object SIntArithmetic extends Arithmetic[SInt] {
override implicit def cast(self: SInt) = new ArithmeticOps(self) {
override def *(t: SInt) = self * t
override def mac(m1: SInt, m2: SInt) = m1 * m2 + self
override def +(t: SInt) = self + t
override def -(t: SInt) = self - t
override def >>(u: UInt) = {
// The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm
// TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here?
val point_five = Mux(u === 0.U, 0.U, self(u - 1.U))
val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U
val ones_digit = self(u)
val r = (point_five & (zeros | ones_digit)).asBool
(self >> u).asSInt + Mux(r, 1.S, 0.S)
}
override def >(t: SInt): Bool = self > t
override def withWidthOf(t: SInt) = {
if (self.getWidth >= t.getWidth)
self(t.getWidth-1, 0).asSInt
else {
val sign_bits = t.getWidth - self.getWidth
val sign = self(self.getWidth-1)
Cat(Cat(Seq.fill(sign_bits)(sign)), self).asTypeOf(t)
}
}
override def clippedToWidthOf(t: SInt): SInt = {
val maxsat = ((1 << (t.getWidth-1))-1).S
val minsat = (-(1 << (t.getWidth-1))).S
MuxCase(self, Seq((self > maxsat) -> maxsat, (self < minsat) -> minsat))(t.getWidth-1, 0).asSInt
}
override def relu: SInt = Mux(self >= 0.S, self, 0.S)
override def zero: SInt = 0.S
override def identity: SInt = 1.S
override def minimum: SInt = (-(1 << (self.getWidth-1))).S
override def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = {
// TODO this uses a floating point divider, but we should use an integer divider instead
val input = Wire(Decoupled(denom_t.cloneType))
val output = Wire(Decoupled(self.cloneType))
// We translate our integer to floating-point form so that we can use the hardfloat divider
val expWidth = log2Up(self.getWidth) + 1
val sigWidth = self.getWidth
def sin_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def uin_to_float(x: UInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := false.B
in_to_rec_fn.io.in := x
in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def float_to_in(x: UInt) = {
val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth))
rec_fn_to_in.io.signedOut := true.B
rec_fn_to_in.io.in := x
rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
rec_fn_to_in.io.out.asSInt
}
val self_rec = sin_to_float(self)
val denom_rec = uin_to_float(input.bits)
// Instantiate the hardloat divider
val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options))
input.ready := divider.io.inReady
divider.io.inValid := input.valid
divider.io.sqrtOp := false.B
divider.io.a := self_rec
divider.io.b := denom_rec
divider.io.roundingMode := consts.round_minMag
divider.io.detectTininess := consts.tininess_afterRounding
output.valid := divider.io.outValid_div
output.bits := float_to_in(divider.io.out)
assert(!output.valid || output.ready)
Some((input, output))
}
override def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = {
// TODO this uses a floating point divider, but we should use an integer divider instead
val input = Wire(Decoupled(UInt(0.W)))
val output = Wire(Decoupled(self.cloneType))
input.bits := DontCare
// We translate our integer to floating-point form so that we can use the hardfloat divider
val expWidth = log2Up(self.getWidth) + 1
val sigWidth = self.getWidth
def in_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def float_to_in(x: UInt) = {
val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth))
rec_fn_to_in.io.signedOut := true.B
rec_fn_to_in.io.in := x
rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
rec_fn_to_in.io.out.asSInt
}
val self_rec = in_to_float(self)
// Instantiate the hardloat sqrt
val sqrter = Module(new DivSqrtRecFN_small(expWidth, sigWidth, 0))
input.ready := sqrter.io.inReady
sqrter.io.inValid := input.valid
sqrter.io.sqrtOp := true.B
sqrter.io.a := self_rec
sqrter.io.b := DontCare
sqrter.io.roundingMode := consts.round_minMag
sqrter.io.detectTininess := consts.tininess_afterRounding
output.valid := sqrter.io.outValid_sqrt
output.bits := float_to_in(sqrter.io.out)
assert(!output.valid || output.ready)
Some((input, output))
}
override def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = u match {
case Float(expWidth, sigWidth) =>
val input = Wire(Decoupled(UInt(0.W)))
val output = Wire(Decoupled(u.cloneType))
input.bits := DontCare
// We translate our integer to floating-point form so that we can use the hardfloat divider
def in_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
val self_rec = in_to_float(self)
val one_rec = in_to_float(1.S)
// Instantiate the hardloat divider
val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options))
input.ready := divider.io.inReady
divider.io.inValid := input.valid
divider.io.sqrtOp := false.B
divider.io.a := one_rec
divider.io.b := self_rec
divider.io.roundingMode := consts.round_near_even
divider.io.detectTininess := consts.tininess_afterRounding
output.valid := divider.io.outValid_div
output.bits := fNFromRecFN(expWidth, sigWidth, divider.io.out).asTypeOf(u)
assert(!output.valid || output.ready)
Some((input, output))
case _ => None
}
override def mult_with_reciprocal[U <: Data](reciprocal: U): SInt = reciprocal match {
case recip @ Float(expWidth, sigWidth) =>
def in_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def float_to_in(x: UInt) = {
val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth))
rec_fn_to_in.io.signedOut := true.B
rec_fn_to_in.io.in := x
rec_fn_to_in.io.roundingMode := consts.round_minMag
rec_fn_to_in.io.out.asSInt
}
val self_rec = in_to_float(self)
val reciprocal_rec = recFNFromFN(expWidth, sigWidth, recip.bits)
// Instantiate the hardloat divider
val muladder = Module(new MulRecFN(expWidth, sigWidth))
muladder.io.roundingMode := consts.round_near_even
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := self_rec
muladder.io.b := reciprocal_rec
float_to_in(muladder.io.out)
case _ => self
}
}
}
implicit object FloatArithmetic extends Arithmetic[Float] {
// TODO Floating point arithmetic currently switches between recoded and standard formats for every operation. However, it should stay in the recoded format as it travels through the systolic array
override implicit def cast(self: Float): ArithmeticOps[Float] = new ArithmeticOps(self) {
override def *(t: Float): Float = {
val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth))
t_resizer.io.in := t_rec
t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
t_resizer.io.detectTininess := consts.tininess_afterRounding
val t_rec_resized = t_resizer.io.out
val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth))
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := self_rec
muladder.io.b := t_rec_resized
val out = Wire(Float(self.expWidth, self.sigWidth))
out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
out
}
override def mac(m1: Float, m2: Float): Float = {
// Recode all operands
val m1_rec = recFNFromFN(m1.expWidth, m1.sigWidth, m1.bits)
val m2_rec = recFNFromFN(m2.expWidth, m2.sigWidth, m2.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Resize m1 to self's width
val m1_resizer = Module(new RecFNToRecFN(m1.expWidth, m1.sigWidth, self.expWidth, self.sigWidth))
m1_resizer.io.in := m1_rec
m1_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
m1_resizer.io.detectTininess := consts.tininess_afterRounding
val m1_rec_resized = m1_resizer.io.out
// Resize m2 to self's width
val m2_resizer = Module(new RecFNToRecFN(m2.expWidth, m2.sigWidth, self.expWidth, self.sigWidth))
m2_resizer.io.in := m2_rec
m2_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
m2_resizer.io.detectTininess := consts.tininess_afterRounding
val m2_rec_resized = m2_resizer.io.out
// Perform multiply-add
val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth))
muladder.io.op := 0.U
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := m1_rec_resized
muladder.io.b := m2_rec_resized
muladder.io.c := self_rec
// Convert result to standard format // TODO remove these intermediate recodings
val out = Wire(Float(self.expWidth, self.sigWidth))
out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
out
}
override def +(t: Float): Float = {
require(self.getWidth >= t.getWidth) // This just makes it easier to write the resizing code
// Recode all operands
val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Generate 1 as a float
val in_to_rec_fn = Module(new INToRecFN(1, self.expWidth, self.sigWidth))
in_to_rec_fn.io.signedIn := false.B
in_to_rec_fn.io.in := 1.U
in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
val one_rec = in_to_rec_fn.io.out
// Resize t
val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth))
t_resizer.io.in := t_rec
t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
t_resizer.io.detectTininess := consts.tininess_afterRounding
val t_rec_resized = t_resizer.io.out
// Perform addition
val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth))
muladder.io.op := 0.U
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := t_rec_resized
muladder.io.b := one_rec
muladder.io.c := self_rec
val result = Wire(Float(self.expWidth, self.sigWidth))
result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
result
}
override def -(t: Float): Float = {
val t_sgn = t.bits(t.getWidth-1)
val neg_t = Cat(~t_sgn, t.bits(t.getWidth-2,0)).asTypeOf(t)
self + neg_t
}
override def >>(u: UInt): Float = {
// Recode self
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Get 2^(-u) as a recoded float
val shift_exp = Wire(UInt(self.expWidth.W))
shift_exp := self.bias.U - u
val shift_fn = Cat(0.U(1.W), shift_exp, 0.U((self.sigWidth-1).W))
val shift_rec = recFNFromFN(self.expWidth, self.sigWidth, shift_fn)
assert(shift_exp =/= 0.U, "scaling by denormalized numbers is not currently supported")
// Multiply self and 2^(-u)
val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth))
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := self_rec
muladder.io.b := shift_rec
val result = Wire(Float(self.expWidth, self.sigWidth))
result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
result
}
override def >(t: Float): Bool = {
// Recode all operands
val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Resize t to self's width
val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth))
t_resizer.io.in := t_rec
t_resizer.io.roundingMode := consts.round_near_even
t_resizer.io.detectTininess := consts.tininess_afterRounding
val t_rec_resized = t_resizer.io.out
val comparator = Module(new CompareRecFN(self.expWidth, self.sigWidth))
comparator.io.a := self_rec
comparator.io.b := t_rec_resized
comparator.io.signaling := false.B
comparator.io.gt
}
override def withWidthOf(t: Float): Float = {
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth))
resizer.io.in := self_rec
resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
resizer.io.detectTininess := consts.tininess_afterRounding
val result = Wire(Float(t.expWidth, t.sigWidth))
result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out)
result
}
override def clippedToWidthOf(t: Float): Float = {
// TODO check for overflow. Right now, we just assume that overflow doesn't happen
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth))
resizer.io.in := self_rec
resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
resizer.io.detectTininess := consts.tininess_afterRounding
val result = Wire(Float(t.expWidth, t.sigWidth))
result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out)
result
}
override def relu: Float = {
val raw = rawFloatFromFN(self.expWidth, self.sigWidth, self.bits)
val result = Wire(Float(self.expWidth, self.sigWidth))
result.bits := Mux(!raw.isZero && raw.sign, 0.U, self.bits)
result
}
override def zero: Float = 0.U.asTypeOf(self)
override def identity: Float = Cat(0.U(2.W), ~(0.U((self.expWidth-1).W)), 0.U((self.sigWidth-1).W)).asTypeOf(self)
override def minimum: Float = Cat(1.U, ~(0.U(self.expWidth.W)), 0.U((self.sigWidth-1).W)).asTypeOf(self)
}
}
implicit object DummySIntArithmetic extends Arithmetic[DummySInt] {
override implicit def cast(self: DummySInt) = new ArithmeticOps(self) {
override def *(t: DummySInt) = self.dontCare
override def mac(m1: DummySInt, m2: DummySInt) = self.dontCare
override def +(t: DummySInt) = self.dontCare
override def -(t: DummySInt) = self.dontCare
override def >>(t: UInt) = self.dontCare
override def >(t: DummySInt): Bool = false.B
override def identity = self.dontCare
override def withWidthOf(t: DummySInt) = self.dontCare
override def clippedToWidthOf(t: DummySInt) = self.dontCare
override def relu = self.dontCare
override def zero = self.dontCare
override def minimum: DummySInt = self.dontCare
}
}
}
| module PE_423( // @[PE.scala:31:7]
input clock, // @[PE.scala:31:7]
input reset, // @[PE.scala:31:7]
input [7:0] io_in_a, // @[PE.scala:35:14]
input [19:0] io_in_b, // @[PE.scala:35:14]
input [19:0] io_in_d, // @[PE.scala:35:14]
output [7:0] io_out_a, // @[PE.scala:35:14]
output [19:0] io_out_b, // @[PE.scala:35:14]
output [19:0] io_out_c, // @[PE.scala:35:14]
input io_in_control_dataflow, // @[PE.scala:35:14]
input io_in_control_propagate, // @[PE.scala:35:14]
input [4:0] io_in_control_shift, // @[PE.scala:35:14]
output io_out_control_dataflow, // @[PE.scala:35:14]
output io_out_control_propagate, // @[PE.scala:35:14]
output [4:0] io_out_control_shift, // @[PE.scala:35:14]
input [2:0] io_in_id, // @[PE.scala:35:14]
output [2:0] io_out_id, // @[PE.scala:35:14]
input io_in_last, // @[PE.scala:35:14]
output io_out_last, // @[PE.scala:35:14]
input io_in_valid, // @[PE.scala:35:14]
output io_out_valid // @[PE.scala:35:14]
);
wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:31:7]
wire [19:0] io_in_b_0 = io_in_b; // @[PE.scala:31:7]
wire [19:0] io_in_d_0 = io_in_d; // @[PE.scala:31:7]
wire io_in_control_dataflow_0 = io_in_control_dataflow; // @[PE.scala:31:7]
wire io_in_control_propagate_0 = io_in_control_propagate; // @[PE.scala:31:7]
wire [4:0] io_in_control_shift_0 = io_in_control_shift; // @[PE.scala:31:7]
wire [2:0] io_in_id_0 = io_in_id; // @[PE.scala:31:7]
wire io_in_last_0 = io_in_last; // @[PE.scala:31:7]
wire io_in_valid_0 = io_in_valid; // @[PE.scala:31:7]
wire io_bad_dataflow = 1'h0; // @[PE.scala:31:7]
wire _io_out_c_T_5 = 1'h0; // @[Arithmetic.scala:125:33]
wire _io_out_c_T_6 = 1'h0; // @[Arithmetic.scala:125:60]
wire _io_out_c_T_16 = 1'h0; // @[Arithmetic.scala:125:33]
wire _io_out_c_T_17 = 1'h0; // @[Arithmetic.scala:125:60]
wire [7:0] io_out_a_0 = io_in_a_0; // @[PE.scala:31:7]
wire [19:0] _mac_unit_io_in_b_T = io_in_b_0; // @[PE.scala:31:7, :106:37]
wire [19:0] _mac_unit_io_in_b_T_2 = io_in_b_0; // @[PE.scala:31:7, :113:37]
wire [19:0] _mac_unit_io_in_b_T_8 = io_in_b_0; // @[PE.scala:31:7, :137:35]
wire io_out_control_dataflow_0 = io_in_control_dataflow_0; // @[PE.scala:31:7]
wire io_out_control_propagate_0 = io_in_control_propagate_0; // @[PE.scala:31:7]
wire [4:0] io_out_control_shift_0 = io_in_control_shift_0; // @[PE.scala:31:7]
wire [2:0] io_out_id_0 = io_in_id_0; // @[PE.scala:31:7]
wire io_out_last_0 = io_in_last_0; // @[PE.scala:31:7]
wire io_out_valid_0 = io_in_valid_0; // @[PE.scala:31:7]
wire [19:0] io_out_b_0; // @[PE.scala:31:7]
wire [19:0] io_out_c_0; // @[PE.scala:31:7]
reg [7:0] c1; // @[PE.scala:70:15]
wire [7:0] _io_out_c_zeros_T_1 = c1; // @[PE.scala:70:15]
wire [7:0] _mac_unit_io_in_b_T_6 = c1; // @[PE.scala:70:15, :127:38]
reg [7:0] c2; // @[PE.scala:71:15]
wire [7:0] _io_out_c_zeros_T_10 = c2; // @[PE.scala:71:15]
wire [7:0] _mac_unit_io_in_b_T_4 = c2; // @[PE.scala:71:15, :121:38]
reg last_s; // @[PE.scala:89:25]
wire flip = last_s != io_in_control_propagate_0; // @[PE.scala:31:7, :89:25, :90:21]
wire [4:0] shift_offset = flip ? io_in_control_shift_0 : 5'h0; // @[PE.scala:31:7, :90:21, :91:25]
wire _GEN = shift_offset == 5'h0; // @[PE.scala:91:25]
wire _io_out_c_point_five_T; // @[Arithmetic.scala:101:32]
assign _io_out_c_point_five_T = _GEN; // @[Arithmetic.scala:101:32]
wire _io_out_c_point_five_T_5; // @[Arithmetic.scala:101:32]
assign _io_out_c_point_five_T_5 = _GEN; // @[Arithmetic.scala:101:32]
wire [5:0] _GEN_0 = {1'h0, shift_offset} - 6'h1; // @[PE.scala:91:25]
wire [5:0] _io_out_c_point_five_T_1; // @[Arithmetic.scala:101:53]
assign _io_out_c_point_five_T_1 = _GEN_0; // @[Arithmetic.scala:101:53]
wire [5:0] _io_out_c_zeros_T_2; // @[Arithmetic.scala:102:66]
assign _io_out_c_zeros_T_2 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66]
wire [5:0] _io_out_c_point_five_T_6; // @[Arithmetic.scala:101:53]
assign _io_out_c_point_five_T_6 = _GEN_0; // @[Arithmetic.scala:101:53]
wire [5:0] _io_out_c_zeros_T_11; // @[Arithmetic.scala:102:66]
assign _io_out_c_zeros_T_11 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66]
wire [4:0] _io_out_c_point_five_T_2 = _io_out_c_point_five_T_1[4:0]; // @[Arithmetic.scala:101:53]
wire [7:0] _io_out_c_point_five_T_3 = $signed($signed(c1) >>> _io_out_c_point_five_T_2); // @[PE.scala:70:15]
wire _io_out_c_point_five_T_4 = _io_out_c_point_five_T_3[0]; // @[Arithmetic.scala:101:50]
wire io_out_c_point_five = ~_io_out_c_point_five_T & _io_out_c_point_five_T_4; // @[Arithmetic.scala:101:{29,32,50}]
wire _GEN_1 = shift_offset < 5'h2; // @[PE.scala:91:25]
wire _io_out_c_zeros_T; // @[Arithmetic.scala:102:27]
assign _io_out_c_zeros_T = _GEN_1; // @[Arithmetic.scala:102:27]
wire _io_out_c_zeros_T_9; // @[Arithmetic.scala:102:27]
assign _io_out_c_zeros_T_9 = _GEN_1; // @[Arithmetic.scala:102:27]
wire [4:0] _io_out_c_zeros_T_3 = _io_out_c_zeros_T_2[4:0]; // @[Arithmetic.scala:102:66]
wire [31:0] _io_out_c_zeros_T_4 = 32'h1 << _io_out_c_zeros_T_3; // @[Arithmetic.scala:102:{60,66}]
wire [32:0] _io_out_c_zeros_T_5 = {1'h0, _io_out_c_zeros_T_4} - 33'h1; // @[Arithmetic.scala:102:{60,81}]
wire [31:0] _io_out_c_zeros_T_6 = _io_out_c_zeros_T_5[31:0]; // @[Arithmetic.scala:102:81]
wire [31:0] _io_out_c_zeros_T_7 = {24'h0, _io_out_c_zeros_T_6[7:0] & _io_out_c_zeros_T_1}; // @[Arithmetic.scala:102:{45,52,81}]
wire [31:0] _io_out_c_zeros_T_8 = _io_out_c_zeros_T ? 32'h0 : _io_out_c_zeros_T_7; // @[Arithmetic.scala:102:{24,27,52}]
wire io_out_c_zeros = |_io_out_c_zeros_T_8; // @[Arithmetic.scala:102:{24,89}]
wire [7:0] _GEN_2 = {3'h0, shift_offset}; // @[PE.scala:91:25]
wire [7:0] _GEN_3 = $signed($signed(c1) >>> _GEN_2); // @[PE.scala:70:15]
wire [7:0] _io_out_c_ones_digit_T; // @[Arithmetic.scala:103:30]
assign _io_out_c_ones_digit_T = _GEN_3; // @[Arithmetic.scala:103:30]
wire [7:0] _io_out_c_T; // @[Arithmetic.scala:107:15]
assign _io_out_c_T = _GEN_3; // @[Arithmetic.scala:103:30, :107:15]
wire io_out_c_ones_digit = _io_out_c_ones_digit_T[0]; // @[Arithmetic.scala:103:30]
wire _io_out_c_r_T = io_out_c_zeros | io_out_c_ones_digit; // @[Arithmetic.scala:102:89, :103:30, :105:38]
wire _io_out_c_r_T_1 = io_out_c_point_five & _io_out_c_r_T; // @[Arithmetic.scala:101:29, :105:{29,38}]
wire io_out_c_r = _io_out_c_r_T_1; // @[Arithmetic.scala:105:{29,53}]
wire [1:0] _io_out_c_T_1 = {1'h0, io_out_c_r}; // @[Arithmetic.scala:105:53, :107:33]
wire [8:0] _io_out_c_T_2 = {_io_out_c_T[7], _io_out_c_T} + {{7{_io_out_c_T_1[1]}}, _io_out_c_T_1}; // @[Arithmetic.scala:107:{15,28,33}]
wire [7:0] _io_out_c_T_3 = _io_out_c_T_2[7:0]; // @[Arithmetic.scala:107:28]
wire [7:0] _io_out_c_T_4 = _io_out_c_T_3; // @[Arithmetic.scala:107:28]
wire [19:0] _io_out_c_T_7 = {{12{_io_out_c_T_4[7]}}, _io_out_c_T_4}; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_8 = _io_out_c_T_7; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_9 = _io_out_c_T_8; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_10 = _io_out_c_T_9; // @[Arithmetic.scala:125:{81,99}]
wire [19:0] _mac_unit_io_in_b_T_1 = _mac_unit_io_in_b_T; // @[PE.scala:106:37]
wire [7:0] _mac_unit_io_in_b_WIRE = _mac_unit_io_in_b_T_1[7:0]; // @[PE.scala:106:37]
wire [7:0] _c1_T = io_in_d_0[7:0]; // @[PE.scala:31:7]
wire [7:0] _c2_T = io_in_d_0[7:0]; // @[PE.scala:31:7]
wire [7:0] _c1_T_1 = _c1_T; // @[Arithmetic.scala:114:{15,33}]
wire [4:0] _io_out_c_point_five_T_7 = _io_out_c_point_five_T_6[4:0]; // @[Arithmetic.scala:101:53]
wire [7:0] _io_out_c_point_five_T_8 = $signed($signed(c2) >>> _io_out_c_point_five_T_7); // @[PE.scala:71:15]
wire _io_out_c_point_five_T_9 = _io_out_c_point_five_T_8[0]; // @[Arithmetic.scala:101:50]
wire io_out_c_point_five_1 = ~_io_out_c_point_five_T_5 & _io_out_c_point_five_T_9; // @[Arithmetic.scala:101:{29,32,50}]
wire [4:0] _io_out_c_zeros_T_12 = _io_out_c_zeros_T_11[4:0]; // @[Arithmetic.scala:102:66]
wire [31:0] _io_out_c_zeros_T_13 = 32'h1 << _io_out_c_zeros_T_12; // @[Arithmetic.scala:102:{60,66}]
wire [32:0] _io_out_c_zeros_T_14 = {1'h0, _io_out_c_zeros_T_13} - 33'h1; // @[Arithmetic.scala:102:{60,81}]
wire [31:0] _io_out_c_zeros_T_15 = _io_out_c_zeros_T_14[31:0]; // @[Arithmetic.scala:102:81]
wire [31:0] _io_out_c_zeros_T_16 = {24'h0, _io_out_c_zeros_T_15[7:0] & _io_out_c_zeros_T_10}; // @[Arithmetic.scala:102:{45,52,81}]
wire [31:0] _io_out_c_zeros_T_17 = _io_out_c_zeros_T_9 ? 32'h0 : _io_out_c_zeros_T_16; // @[Arithmetic.scala:102:{24,27,52}]
wire io_out_c_zeros_1 = |_io_out_c_zeros_T_17; // @[Arithmetic.scala:102:{24,89}]
wire [7:0] _GEN_4 = $signed($signed(c2) >>> _GEN_2); // @[PE.scala:71:15]
wire [7:0] _io_out_c_ones_digit_T_1; // @[Arithmetic.scala:103:30]
assign _io_out_c_ones_digit_T_1 = _GEN_4; // @[Arithmetic.scala:103:30]
wire [7:0] _io_out_c_T_11; // @[Arithmetic.scala:107:15]
assign _io_out_c_T_11 = _GEN_4; // @[Arithmetic.scala:103:30, :107:15]
wire io_out_c_ones_digit_1 = _io_out_c_ones_digit_T_1[0]; // @[Arithmetic.scala:103:30]
wire _io_out_c_r_T_2 = io_out_c_zeros_1 | io_out_c_ones_digit_1; // @[Arithmetic.scala:102:89, :103:30, :105:38]
wire _io_out_c_r_T_3 = io_out_c_point_five_1 & _io_out_c_r_T_2; // @[Arithmetic.scala:101:29, :105:{29,38}]
wire io_out_c_r_1 = _io_out_c_r_T_3; // @[Arithmetic.scala:105:{29,53}]
wire [1:0] _io_out_c_T_12 = {1'h0, io_out_c_r_1}; // @[Arithmetic.scala:105:53, :107:33]
wire [8:0] _io_out_c_T_13 = {_io_out_c_T_11[7], _io_out_c_T_11} + {{7{_io_out_c_T_12[1]}}, _io_out_c_T_12}; // @[Arithmetic.scala:107:{15,28,33}]
wire [7:0] _io_out_c_T_14 = _io_out_c_T_13[7:0]; // @[Arithmetic.scala:107:28]
wire [7:0] _io_out_c_T_15 = _io_out_c_T_14; // @[Arithmetic.scala:107:28]
wire [19:0] _io_out_c_T_18 = {{12{_io_out_c_T_15[7]}}, _io_out_c_T_15}; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_19 = _io_out_c_T_18; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_20 = _io_out_c_T_19; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_21 = _io_out_c_T_20; // @[Arithmetic.scala:125:{81,99}]
wire [19:0] _mac_unit_io_in_b_T_3 = _mac_unit_io_in_b_T_2; // @[PE.scala:113:37]
wire [7:0] _mac_unit_io_in_b_WIRE_1 = _mac_unit_io_in_b_T_3[7:0]; // @[PE.scala:113:37]
wire [7:0] _c2_T_1 = _c2_T; // @[Arithmetic.scala:114:{15,33}]
wire [7:0] _mac_unit_io_in_b_T_5; // @[PE.scala:121:38]
assign _mac_unit_io_in_b_T_5 = _mac_unit_io_in_b_T_4; // @[PE.scala:121:38]
wire [7:0] _mac_unit_io_in_b_WIRE_2 = _mac_unit_io_in_b_T_5; // @[PE.scala:121:38]
assign io_out_c_0 = io_in_control_propagate_0 ? {{12{c1[7]}}, c1} : {{12{c2[7]}}, c2}; // @[PE.scala:31:7, :70:15, :71:15, :119:30, :120:16, :126:16]
wire [7:0] _mac_unit_io_in_b_T_7; // @[PE.scala:127:38]
assign _mac_unit_io_in_b_T_7 = _mac_unit_io_in_b_T_6; // @[PE.scala:127:38]
wire [7:0] _mac_unit_io_in_b_WIRE_3 = _mac_unit_io_in_b_T_7; // @[PE.scala:127:38]
wire [19:0] _mac_unit_io_in_b_T_9 = _mac_unit_io_in_b_T_8; // @[PE.scala:137:35]
wire [7:0] _mac_unit_io_in_b_WIRE_4 = _mac_unit_io_in_b_T_9[7:0]; // @[PE.scala:137:35]
always @(posedge clock) begin // @[PE.scala:31:7]
if (io_in_valid_0 & io_in_control_propagate_0) // @[PE.scala:31:7, :102:95, :141:17, :142:8]
c1 <= io_in_d_0[7:0]; // @[PE.scala:31:7, :70:15]
if (~(~io_in_valid_0 | io_in_control_propagate_0)) // @[PE.scala:31:7, :71:15, :102:95, :119:30, :130:10, :141:{9,17}, :143:8]
c2 <= io_in_d_0[7:0]; // @[PE.scala:31:7, :71:15]
if (io_in_valid_0) // @[PE.scala:31:7]
last_s <= io_in_control_propagate_0; // @[PE.scala:31:7, :89:25]
always @(posedge)
MacUnit_167 mac_unit ( // @[PE.scala:64:24]
.clock (clock),
.reset (reset),
.io_in_a (io_in_a_0), // @[PE.scala:31:7]
.io_in_b (io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE_2 : _mac_unit_io_in_b_WIRE_3), // @[PE.scala:31:7, :119:30, :121:{24,38}, :127:{24,38}]
.io_in_c (io_in_b_0), // @[PE.scala:31:7]
.io_out_d (io_out_b_0)
); // @[PE.scala:64:24]
assign io_out_a = io_out_a_0; // @[PE.scala:31:7]
assign io_out_b = io_out_b_0; // @[PE.scala:31:7]
assign io_out_c = io_out_c_0; // @[PE.scala:31:7]
assign io_out_control_dataflow = io_out_control_dataflow_0; // @[PE.scala:31:7]
assign io_out_control_propagate = io_out_control_propagate_0; // @[PE.scala:31:7]
assign io_out_control_shift = io_out_control_shift_0; // @[PE.scala:31:7]
assign io_out_id = io_out_id_0; // @[PE.scala:31:7]
assign io_out_last = io_out_last_0; // @[PE.scala:31:7]
assign io_out_valid = io_out_valid_0; // @[PE.scala:31:7]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File Monitor.scala:
package constellation.channel
import chisel3._
import chisel3.util._
import freechips.rocketchip.diplomacy._
import org.chipsalliance.cde.config.{Parameters}
import freechips.rocketchip.util._
import constellation.noc.{HasNoCParams}
class NoCMonitor(val cParam: ChannelParams)(implicit val p: Parameters) extends Module with HasNoCParams {
val io = IO(new Bundle {
val in = Input(new Channel(cParam))
})
val in_flight = RegInit(VecInit(Seq.fill(cParam.nVirtualChannels) { false.B }))
for (i <- 0 until cParam.srcSpeedup) {
val flit = io.in.flit(i)
when (flit.valid) {
when (flit.bits.head) {
in_flight(flit.bits.virt_channel_id) := true.B
assert (!in_flight(flit.bits.virt_channel_id), "Flit head/tail sequencing is broken")
}
when (flit.bits.tail) {
in_flight(flit.bits.virt_channel_id) := false.B
}
}
val possibleFlows = cParam.possibleFlows
when (flit.valid && flit.bits.head) {
cParam match {
case n: ChannelParams => n.virtualChannelParams.zipWithIndex.foreach { case (v,i) =>
assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)
}
case _ => assert(cParam.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)
}
}
}
}
File Types.scala:
package constellation.routing
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.{Parameters}
import constellation.noc.{HasNoCParams}
import constellation.channel.{Flit}
/** A representation for 1 specific virtual channel in wormhole routing
*
* @param src the source node
* @param vc ID for the virtual channel
* @param dst the destination node
* @param n_vc the number of virtual channels
*/
// BEGIN: ChannelRoutingInfo
case class ChannelRoutingInfo(
src: Int,
dst: Int,
vc: Int,
n_vc: Int
) {
// END: ChannelRoutingInfo
require (src >= -1 && dst >= -1 && vc >= 0, s"Illegal $this")
require (!(src == -1 && dst == -1), s"Illegal $this")
require (vc < n_vc, s"Illegal $this")
val isIngress = src == -1
val isEgress = dst == -1
}
/** Represents the properties of a packet that are relevant for routing
* ingressId and egressId uniquely identify a flow, but vnet and dst are used here
* to simplify the implementation of routingrelations
*
* @param ingressId packet's source ingress point
* @param egressId packet's destination egress point
* @param vNet virtual subnetwork identifier
* @param dst packet's destination node ID
*/
// BEGIN: FlowRoutingInfo
case class FlowRoutingInfo(
ingressId: Int,
egressId: Int,
vNetId: Int,
ingressNode: Int,
ingressNodeId: Int,
egressNode: Int,
egressNodeId: Int,
fifo: Boolean
) {
// END: FlowRoutingInfo
def isFlow(f: FlowRoutingBundle): Bool = {
(f.ingress_node === ingressNode.U &&
f.egress_node === egressNode.U &&
f.ingress_node_id === ingressNodeId.U &&
f.egress_node_id === egressNodeId.U)
}
def asLiteral(b: FlowRoutingBundle): BigInt = {
Seq(
(vNetId , b.vnet_id),
(ingressNode , b.ingress_node),
(ingressNodeId , b.ingress_node_id),
(egressNode , b.egress_node),
(egressNodeId , b.egress_node_id)
).foldLeft(0)((l, t) => {
(l << t._2.getWidth) | t._1
})
}
}
class FlowRoutingBundle(implicit val p: Parameters) extends Bundle with HasNoCParams {
// Instead of tracking ingress/egress ID, track the physical destination id and the offset at the destination
// This simplifies the routing tables
val vnet_id = UInt(log2Ceil(nVirtualNetworks).W)
val ingress_node = UInt(log2Ceil(nNodes).W)
val ingress_node_id = UInt(log2Ceil(maxIngressesAtNode).W)
val egress_node = UInt(log2Ceil(nNodes).W)
val egress_node_id = UInt(log2Ceil(maxEgressesAtNode).W)
}
| module NoCMonitor_4( // @[Monitor.scala:11:7]
input clock, // @[Monitor.scala:11:7]
input reset, // @[Monitor.scala:11:7]
input io_in_flit_0_valid, // @[Monitor.scala:12:14]
input io_in_flit_0_bits_head, // @[Monitor.scala:12:14]
input io_in_flit_0_bits_tail, // @[Monitor.scala:12:14]
input [3:0] io_in_flit_0_bits_flow_ingress_node, // @[Monitor.scala:12:14]
input [2:0] io_in_flit_0_bits_flow_ingress_node_id, // @[Monitor.scala:12:14]
input [3:0] io_in_flit_0_bits_flow_egress_node, // @[Monitor.scala:12:14]
input [2:0] io_in_flit_0_bits_flow_egress_node_id, // @[Monitor.scala:12:14]
input [3:0] io_in_flit_0_bits_virt_channel_id // @[Monitor.scala:12:14]
);
reg in_flight_0; // @[Monitor.scala:16:26]
reg in_flight_1; // @[Monitor.scala:16:26]
reg in_flight_2; // @[Monitor.scala:16:26]
reg in_flight_3; // @[Monitor.scala:16:26]
reg in_flight_4; // @[Monitor.scala:16:26]
reg in_flight_5; // @[Monitor.scala:16:26]
reg in_flight_6; // @[Monitor.scala:16:26]
reg in_flight_7; // @[Monitor.scala:16:26]
reg in_flight_8; // @[Monitor.scala:16:26]
reg in_flight_9; // @[Monitor.scala:16:26]
wire _GEN = io_in_flit_0_bits_virt_channel_id == 4'h6; // @[Monitor.scala:21:46]
wire _GEN_0 = io_in_flit_0_bits_virt_channel_id == 4'h7; // @[Monitor.scala:21:46] |
Generate the Verilog code corresponding to the following Chisel files.
File ShiftReg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
// Similar to the Chisel ShiftRegister but allows the user to suggest a
// name to the registers that get instantiated, and
// to provide a reset value.
object ShiftRegInit {
def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T =
(0 until n).foldRight(in) {
case (i, next) => {
val r = RegNext(next, init)
name.foreach { na => r.suggestName(s"${na}_${i}") }
r
}
}
}
/** These wrap behavioral
* shift registers into specific modules to allow for
* backend flows to replace or constrain
* them properly when used for CDC synchronization,
* rather than buffering.
*
* The different types vary in their reset behavior:
* AsyncResetShiftReg -- Asynchronously reset register array
* A W(width) x D(depth) sized array is constructed from D instantiations of a
* W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg,
* but only used for timing applications
*/
abstract class AbstractPipelineReg(w: Int = 1) extends Module {
val io = IO(new Bundle {
val d = Input(UInt(w.W))
val q = Output(UInt(w.W))
}
)
}
object AbstractPipelineReg {
def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = {
val chain = Module(gen)
name.foreach{ chain.suggestName(_) }
chain.io.d := in.asUInt
chain.io.q.asTypeOf(in)
}
}
class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) {
require(depth > 0, "Depth must be greater than 0.")
override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}"
val chain = List.tabulate(depth) { i =>
Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}")
}
chain.last.io.d := io.d
chain.last.io.en := true.B
(chain.init zip chain.tail).foreach { case (sink, source) =>
sink.io.d := source.io.q
sink.io.en := true.B
}
io.q := chain.head.io.q
}
object AsyncResetShiftReg {
def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T =
AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name)
def apply [T <: Data](in: T, depth: Int, name: Option[String]): T =
apply(in, depth, 0, name)
def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T =
apply(in, depth, init.litValue.toInt, name)
def apply [T <: Data](in: T, depth: Int, init: T): T =
apply (in, depth, init.litValue.toInt, None)
}
File SynchronizerReg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util.{RegEnable, Cat}
/** These wrap behavioral
* shift and next registers into specific modules to allow for
* backend flows to replace or constrain
* them properly when used for CDC synchronization,
* rather than buffering.
*
*
* These are built up of *ResetSynchronizerPrimitiveShiftReg,
* intended to be replaced by the integrator's metastable flops chains or replaced
* at this level if they have a multi-bit wide synchronizer primitive.
* The different types vary in their reset behavior:
* NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin
* AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep
* 1-bit-wide shift registers.
* SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg
*
* [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference.
*
* ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross
* Clock Domains.
*/
object SynchronizerResetType extends Enumeration {
val NonSync, Inferred, Sync, Async = Value
}
// Note: this should not be used directly.
// Use the companion object to generate this with the correct reset type mixin.
private class SynchronizerPrimitiveShiftReg(
sync: Int,
init: Boolean,
resetType: SynchronizerResetType.Value)
extends AbstractPipelineReg(1) {
val initInt = if (init) 1 else 0
val initPostfix = resetType match {
case SynchronizerResetType.NonSync => ""
case _ => s"_i${initInt}"
}
override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}"
val chain = List.tabulate(sync) { i =>
val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B)
reg.suggestName(s"sync_$i")
}
chain.last := io.d.asBool
(chain.init zip chain.tail).foreach { case (sink, source) =>
sink := source
}
io.q := chain.head.asUInt
}
private object SynchronizerPrimitiveShiftReg {
def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = {
val gen: () => SynchronizerPrimitiveShiftReg = resetType match {
case SynchronizerResetType.NonSync =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType)
case SynchronizerResetType.Async =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset
case SynchronizerResetType.Sync =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset
case SynchronizerResetType.Inferred =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType)
}
AbstractPipelineReg(gen(), in)
}
}
// Note: This module may end up with a non-AsyncReset type reset.
// But the Primitives within will always have AsyncReset type.
class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int)
extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
withReset(reset.asAsyncReset){
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async)
}
}
io.q := Cat(output.reverse)
}
object AsyncResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
// Note: This module may end up with a non-Bool type reset.
// But the Primitives within will always have Bool reset type.
@deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2")
class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
withReset(reset.asBool){
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync)
}
}
io.q := Cat(output.reverse)
}
object SyncResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred)
}
io.q := Cat(output.reverse)
}
object ResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}"
val output = Seq.tabulate(w) { i =>
SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync)
}
io.q := Cat(output.reverse)
}
object SynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T =
if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, None)
def apply [T <: Data](in: T): T =
apply (in, 3, None)
}
class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module {
override def desiredName = s"ClockCrossingReg_w${w}"
val io = IO(new Bundle{
val d = Input(UInt(w.W))
val q = Output(UInt(w.W))
val en = Input(Bool())
})
val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en)
io.q := cdc_reg
}
object ClockCrossingReg {
def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = {
val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit))
name.foreach{ cdc_reg.suggestName(_) }
cdc_reg.io.d := in.asUInt
cdc_reg.io.en := en
cdc_reg.io.q.asTypeOf(in)
}
}
| module AsyncResetSynchronizerShiftReg_w4_d3_i0_35( // @[SynchronizerReg.scala:80:7]
input clock, // @[SynchronizerReg.scala:80:7]
input reset, // @[SynchronizerReg.scala:80:7]
input [3:0] io_d, // @[ShiftReg.scala:36:14]
output [3:0] io_q // @[ShiftReg.scala:36:14]
);
wire [3:0] io_d_0 = io_d; // @[SynchronizerReg.scala:80:7]
wire _output_T = reset; // @[SynchronizerReg.scala:86:21]
wire _output_T_2 = reset; // @[SynchronizerReg.scala:86:21]
wire _output_T_4 = reset; // @[SynchronizerReg.scala:86:21]
wire _output_T_6 = reset; // @[SynchronizerReg.scala:86:21]
wire [3:0] _io_q_T; // @[SynchronizerReg.scala:90:14]
wire [3:0] io_q_0; // @[SynchronizerReg.scala:80:7]
wire _output_T_1 = io_d_0[0]; // @[SynchronizerReg.scala:80:7, :87:41]
wire output_0; // @[ShiftReg.scala:48:24]
wire _output_T_3 = io_d_0[1]; // @[SynchronizerReg.scala:80:7, :87:41]
wire output_1; // @[ShiftReg.scala:48:24]
wire _output_T_5 = io_d_0[2]; // @[SynchronizerReg.scala:80:7, :87:41]
wire output_2; // @[ShiftReg.scala:48:24]
wire _output_T_7 = io_d_0[3]; // @[SynchronizerReg.scala:80:7, :87:41]
wire output_3; // @[ShiftReg.scala:48:24]
wire [1:0] io_q_lo = {output_1, output_0}; // @[SynchronizerReg.scala:90:14]
wire [1:0] io_q_hi = {output_3, output_2}; // @[SynchronizerReg.scala:90:14]
assign _io_q_T = {io_q_hi, io_q_lo}; // @[SynchronizerReg.scala:90:14]
assign io_q_0 = _io_q_T; // @[SynchronizerReg.scala:80:7, :90:14]
AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_325 output_chain ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (_output_T), // @[SynchronizerReg.scala:86:21]
.io_d (_output_T_1), // @[SynchronizerReg.scala:87:41]
.io_q (output_0)
); // @[ShiftReg.scala:45:23]
AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_326 output_chain_1 ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (_output_T_2), // @[SynchronizerReg.scala:86:21]
.io_d (_output_T_3), // @[SynchronizerReg.scala:87:41]
.io_q (output_1)
); // @[ShiftReg.scala:45:23]
AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_327 output_chain_2 ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (_output_T_4), // @[SynchronizerReg.scala:86:21]
.io_d (_output_T_5), // @[SynchronizerReg.scala:87:41]
.io_q (output_2)
); // @[ShiftReg.scala:45:23]
AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_328 output_chain_3 ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (_output_T_6), // @[SynchronizerReg.scala:86:21]
.io_d (_output_T_7), // @[SynchronizerReg.scala:87:41]
.io_q (output_3)
); // @[ShiftReg.scala:45:23]
assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File Crossing.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.interrupts
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy.lazymodule._
import freechips.rocketchip.util.{SynchronizerShiftReg, AsyncResetReg}
@deprecated("IntXing does not ensure interrupt source is glitch free. Use IntSyncSource and IntSyncSink", "rocket-chip 1.2")
class IntXing(sync: Int = 3)(implicit p: Parameters) extends LazyModule
{
val intnode = IntAdapterNode()
lazy val module = new Impl
class Impl extends LazyModuleImp(this) {
(intnode.in zip intnode.out) foreach { case ((in, _), (out, _)) =>
out := SynchronizerShiftReg(in, sync)
}
}
}
object IntSyncCrossingSource
{
def apply(alreadyRegistered: Boolean = false)(implicit p: Parameters) =
{
val intsource = LazyModule(new IntSyncCrossingSource(alreadyRegistered))
intsource.node
}
}
class IntSyncCrossingSource(alreadyRegistered: Boolean = false)(implicit p: Parameters) extends LazyModule
{
val node = IntSyncSourceNode(alreadyRegistered)
lazy val module = if (alreadyRegistered) (new ImplRegistered) else (new Impl)
class Impl extends LazyModuleImp(this) {
def outSize = node.out.headOption.map(_._1.sync.size).getOrElse(0)
override def desiredName = s"IntSyncCrossingSource_n${node.out.size}x${outSize}"
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
out.sync := AsyncResetReg(Cat(in.reverse)).asBools
}
}
class ImplRegistered extends LazyRawModuleImp(this) {
def outSize = node.out.headOption.map(_._1.sync.size).getOrElse(0)
override def desiredName = s"IntSyncCrossingSource_n${node.out.size}x${outSize}_Registered"
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
out.sync := in
}
}
}
object IntSyncCrossingSink
{
@deprecated("IntSyncCrossingSink which used the `sync` parameter to determine crossing type is deprecated. Use IntSyncAsyncCrossingSink, IntSyncRationalCrossingSink, or IntSyncSyncCrossingSink instead for > 1, 1, and 0 sync values respectively", "rocket-chip 1.2")
def apply(sync: Int = 3)(implicit p: Parameters) =
{
val intsink = LazyModule(new IntSyncAsyncCrossingSink(sync))
intsink.node
}
}
class IntSyncAsyncCrossingSink(sync: Int = 3)(implicit p: Parameters) extends LazyModule
{
val node = IntSyncSinkNode(sync)
lazy val module = new Impl
class Impl extends LazyModuleImp(this) {
override def desiredName = s"IntSyncAsyncCrossingSink_n${node.out.size}x${node.out.head._1.size}"
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
out := SynchronizerShiftReg(in.sync, sync)
}
}
}
object IntSyncAsyncCrossingSink
{
def apply(sync: Int = 3)(implicit p: Parameters) =
{
val intsink = LazyModule(new IntSyncAsyncCrossingSink(sync))
intsink.node
}
}
class IntSyncSyncCrossingSink()(implicit p: Parameters) extends LazyModule
{
val node = IntSyncSinkNode(0)
lazy val module = new Impl
class Impl extends LazyRawModuleImp(this) {
def outSize = node.out.headOption.map(_._1.size).getOrElse(0)
override def desiredName = s"IntSyncSyncCrossingSink_n${node.out.size}x${outSize}"
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
out := in.sync
}
}
}
object IntSyncSyncCrossingSink
{
def apply()(implicit p: Parameters) =
{
val intsink = LazyModule(new IntSyncSyncCrossingSink())
intsink.node
}
}
class IntSyncRationalCrossingSink()(implicit p: Parameters) extends LazyModule
{
val node = IntSyncSinkNode(1)
lazy val module = new Impl
class Impl extends LazyModuleImp(this) {
def outSize = node.out.headOption.map(_._1.size).getOrElse(0)
override def desiredName = s"IntSyncRationalCrossingSink_n${node.out.size}x${outSize}"
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
out := RegNext(in.sync)
}
}
}
object IntSyncRationalCrossingSink
{
def apply()(implicit p: Parameters) =
{
val intsink = LazyModule(new IntSyncRationalCrossingSink())
intsink.node
}
}
File LazyModuleImp.scala:
package org.chipsalliance.diplomacy.lazymodule
import chisel3.{withClockAndReset, Module, RawModule, Reset, _}
import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo}
import firrtl.passes.InlineAnnotation
import org.chipsalliance.cde.config.Parameters
import org.chipsalliance.diplomacy.nodes.Dangle
import scala.collection.immutable.SortedMap
/** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]].
*
* This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy.
*/
sealed trait LazyModuleImpLike extends RawModule {
/** [[LazyModule]] that contains this instance. */
val wrapper: LazyModule
/** IOs that will be automatically "punched" for this instance. */
val auto: AutoBundle
/** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */
protected[diplomacy] val dangles: Seq[Dangle]
// [[wrapper.module]] had better not be accessed while LazyModules are still being built!
require(
LazyModule.scope.isEmpty,
s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}"
)
/** Set module name. Defaults to the containing LazyModule's desiredName. */
override def desiredName: String = wrapper.desiredName
suggestName(wrapper.suggestedName)
/** [[Parameters]] for chisel [[Module]]s. */
implicit val p: Parameters = wrapper.p
/** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and
* submodules.
*/
protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = {
// 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]],
// 2. return [[Dangle]]s from each module.
val childDangles = wrapper.children.reverse.flatMap { c =>
implicit val sourceInfo: SourceInfo = c.info
c.cloneProto.map { cp =>
// If the child is a clone, then recursively set cloneProto of its children as well
def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = {
require(bases.size == clones.size)
(bases.zip(clones)).map { case (l, r) =>
require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}")
l.cloneProto = Some(r)
assignCloneProtos(l.children, r.children)
}
}
assignCloneProtos(c.children, cp.children)
// Clone the child module as a record, and get its [[AutoBundle]]
val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName)
val clonedAuto = clone("auto").asInstanceOf[AutoBundle]
// Get the empty [[Dangle]]'s of the cloned child
val rawDangles = c.cloneDangles()
require(rawDangles.size == clonedAuto.elements.size)
// Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s
val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) }
dangles
}.getOrElse {
// For non-clones, instantiate the child module
val mod = try {
Module(c.module)
} catch {
case e: ChiselException => {
println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}")
throw e
}
}
mod.dangles
}
}
// Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]].
// This will result in a sequence of [[Dangle]] from these [[BaseNode]]s.
val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate())
// Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]]
val allDangles = nodeDangles ++ childDangles
// Group [[allDangles]] by their [[source]].
val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*)
// For each [[source]] set of [[Dangle]]s of size 2, ensure that these
// can be connected as a source-sink pair (have opposite flipped value).
// Make the connection and mark them as [[done]].
val done = Set() ++ pairing.values.filter(_.size == 2).map {
case Seq(a, b) =>
require(a.flipped != b.flipped)
// @todo <> in chisel3 makes directionless connection.
if (a.flipped) {
a.data <> b.data
} else {
b.data <> a.data
}
a.source
case _ => None
}
// Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module.
val forward = allDangles.filter(d => !done(d.source))
// Generate [[AutoBundle]] IO from [[forward]].
val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*))
// Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]]
val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) =>
if (d.flipped) {
d.data <> io
} else {
io <> d.data
}
d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name)
}
// Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]].
wrapper.inModuleBody.reverse.foreach {
_()
}
if (wrapper.shouldBeInlined) {
chisel3.experimental.annotate(new ChiselAnnotation {
def toFirrtl = InlineAnnotation(toNamed)
})
}
// Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]].
(auto, dangles)
}
}
/** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike {
/** Instantiate hardware of this `Module`. */
val (auto, dangles) = instantiate()
}
/** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike {
// These wires are the default clock+reset for all LazyModule children.
// It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the
// [[LazyRawModuleImp]] children.
// Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly.
/** drive clock explicitly. */
val childClock: Clock = Wire(Clock())
/** drive reset explicitly. */
val childReset: Reset = Wire(Reset())
// the default is that these are disabled
childClock := false.B.asClock
childReset := chisel3.DontCare
def provideImplicitClockToLazyChildren: Boolean = false
val (auto, dangles) =
if (provideImplicitClockToLazyChildren) {
withClockAndReset(childClock, childReset) { instantiate() }
} else {
instantiate()
}
}
File MixedNode.scala:
package org.chipsalliance.diplomacy.nodes
import chisel3.{Data, DontCare, Wire}
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.{Field, Parameters}
import org.chipsalliance.diplomacy.ValName
import org.chipsalliance.diplomacy.sourceLine
/** One side metadata of a [[Dangle]].
*
* Describes one side of an edge going into or out of a [[BaseNode]].
*
* @param serial
* the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to.
* @param index
* the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to.
*/
case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] {
import scala.math.Ordered.orderingToOrdered
def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that))
}
/** [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]]
* connects.
*
* [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] ,
* [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]].
*
* @param source
* the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within
* that [[BaseNode]].
* @param sink
* sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that
* [[BaseNode]].
* @param flipped
* flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to
* `danglesIn`.
* @param dataOpt
* actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module
*/
case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) {
def data = dataOpt.get
}
/** [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often
* derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually
* implement the protocol.
*/
case class Edges[EI, EO](in: Seq[EI], out: Seq[EO])
/** A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. */
case object MonitorsEnabled extends Field[Boolean](true)
/** When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented.
*
* For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but
* [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink
* nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the
* [[LazyModule]].
*/
case object RenderFlipped extends Field[Boolean](false)
/** The sealed node class in the package, all node are derived from it.
*
* @param inner
* Sink interface implementation.
* @param outer
* Source interface implementation.
* @param valName
* val name of this node.
* @tparam DI
* Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters
* describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected
* [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port
* parameters.
* @tparam UI
* Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing
* the protocol parameters of a sink. For an [[InwardNode]], it is determined itself.
* @tparam EI
* Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers
* specified for a sink according to protocol.
* @tparam BI
* Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface.
* It should extends from [[chisel3.Data]], which represents the real hardware.
* @tparam DO
* Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters
* describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself.
* @tparam UO
* Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing
* the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]].
* Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters.
* @tparam EO
* Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers
* specified for a source according to protocol.
* @tparam BO
* Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source
* interface. It should extends from [[chisel3.Data]], which represents the real hardware.
*
* @note
* Call Graph of [[MixedNode]]
* - line `─`: source is process by a function and generate pass to others
* - Arrow `→`: target of arrow is generated by source
*
* {{{
* (from the other node)
* ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐
* ↓ │
* (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │
* [[InwardNode.accPI]] │ │ │
* │ │ (based on protocol) │
* │ │ [[MixedNode.inner.edgeI]] │
* │ │ ↓ │
* ↓ │ │ │
* (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │
* [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │
* │ │ ↑ │ │ │
* │ │ │ [[OutwardNode.doParams]] │ │
* │ │ │ (from the other node) │ │
* │ │ │ │ │ │
* │ │ │ │ │ │
* │ │ │ └────────┬──────────────┤ │
* │ │ │ │ │ │
* │ │ │ │ (based on protocol) │
* │ │ │ │ [[MixedNode.inner.edgeI]] │
* │ │ │ │ │ │
* │ │ (from the other node) │ ↓ │
* │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │
* │ ↑ ↑ │ │ ↓ │
* │ │ │ │ │ [[MixedNode.in]] │
* │ │ │ │ ↓ ↑ │
* │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │
* ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │
* │ │ │ [[MixedNode.bundleOut]]─┐ │ │
* │ │ │ ↑ ↓ │ │
* │ │ │ │ [[MixedNode.out]] │ │
* │ ↓ ↓ │ ↑ │ │
* │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │
* │ │ (from the other node) ↑ │ │
* │ │ │ │ │ │
* │ │ │ [[MixedNode.outer.edgeO]] │ │
* │ │ │ (based on protocol) │ │
* │ │ │ │ │ │
* │ │ │ ┌────────────────────────────────────────┤ │ │
* │ │ │ │ │ │ │
* │ │ │ │ │ │ │
* │ │ │ │ │ │ │
* (immobilize after elaboration)│ ↓ │ │ │ │
* [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │
* ↑ (inward port from [[OutwardNode]]) │ │ │ │
* │ ┌─────────────────────────────────────────┤ │ │ │
* │ │ │ │ │ │
* │ │ │ │ │ │
* [[OutwardNode.accPO]] │ ↓ │ │ │
* (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │
* │ ↑ │ │
* │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │
* └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘
* }}}
*/
abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data](
val inner: InwardNodeImp[DI, UI, EI, BI],
val outer: OutwardNodeImp[DO, UO, EO, BO]
)(
implicit valName: ValName)
extends BaseNode
with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO]
with InwardNode[DI, UI, BI]
with OutwardNode[DO, UO, BO] {
// Generate a [[NodeHandle]] with inward and outward node are both this node.
val inward = this
val outward = this
/** Debug info of nodes binding. */
def bindingInfo: String = s"""$iBindingInfo
|$oBindingInfo
|""".stripMargin
/** Debug info of ports connecting. */
def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}]
|${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}]
|""".stripMargin
/** Debug info of parameters propagations. */
def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}]
|${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}]
|${diParams.size} downstream inward parameters: [${diParams.mkString(",")}]
|${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}]
|""".stripMargin
/** For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and
* [[MixedNode.iPortMapping]].
*
* Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward
* stars and outward stars.
*
* This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type
* of node.
*
* @param iKnown
* Number of known-size ([[BIND_ONCE]]) input bindings.
* @param oKnown
* Number of known-size ([[BIND_ONCE]]) output bindings.
* @param iStar
* Number of unknown size ([[BIND_STAR]]) input bindings.
* @param oStar
* Number of unknown size ([[BIND_STAR]]) output bindings.
* @return
* A Tuple of the resolved number of input and output connections.
*/
protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int)
/** Function to generate downward-flowing outward params from the downward-flowing input params and the current output
* ports.
*
* @param n
* The size of the output sequence to generate.
* @param p
* Sequence of downward-flowing input parameters of this node.
* @return
* A `n`-sized sequence of downward-flowing output edge parameters.
*/
protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO]
/** Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]].
*
* @param n
* Size of the output sequence.
* @param p
* Upward-flowing output edge parameters.
* @return
* A n-sized sequence of upward-flowing input edge parameters.
*/
protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI]
/** @return
* The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with
* [[BIND_STAR]].
*/
protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR)
/** @return
* The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of
* output bindings bound with [[BIND_STAR]].
*/
protected[diplomacy] lazy val sourceCard: Int =
iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR)
/** @return list of nodes involved in flex bindings with this node. */
protected[diplomacy] lazy val flexes: Seq[BaseNode] =
oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2)
/** Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin
* greedily taking up the remaining connections.
*
* @return
* A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return
* value is not relevant.
*/
protected[diplomacy] lazy val flexOffset: Int = {
/** Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex
* operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a
* connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of
* each node in the current set and decide whether they should be added to the set or not.
*
* @return
* the mapping of [[BaseNode]] indexed by their serial numbers.
*/
def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = {
if (visited.contains(v.serial) || !v.flexibleArityDirection) {
visited
} else {
v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum))
}
}
/** Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node.
*
* @example
* {{{
* a :*=* b :*=* c
* d :*=* b
* e :*=* f
* }}}
*
* `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)`
*/
val flexSet = DFS(this, Map()).values
/** The total number of :*= operators where we're on the left. */
val allSink = flexSet.map(_.sinkCard).sum
/** The total number of :=* operators used when we're on the right. */
val allSource = flexSet.map(_.sourceCard).sum
require(
allSink == 0 || allSource == 0,
s"The nodes ${flexSet.map(_.name)} which are inter-connected by :*=* have ${allSink} :*= operators and ${allSource} :=* operators connected to them, making it impossible to determine cardinality inference direction."
)
allSink - allSource
}
/** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. */
protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = {
if (flexibleArityDirection) flexOffset
else if (n.flexibleArityDirection) n.flexOffset
else 0
}
/** For a node which is connected between two nodes, select the one that will influence the direction of the flex
* resolution.
*/
protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = {
val dir = edgeArityDirection(n)
if (dir < 0) l
else if (dir > 0) r
else 1
}
/** Ensure that the same node is not visited twice in resolving `:*=`, etc operators. */
private var starCycleGuard = false
/** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star"
* connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also
* need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct
* edge parameters and later build up correct bundle connections.
*
* [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding
* operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort
* (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N :*= foo` or `N :*=* foo :*=
* bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo :*=* N`
*/
protected[diplomacy] lazy val (
oPortMapping: Seq[(Int, Int)],
iPortMapping: Seq[(Int, Int)],
oStar: Int,
iStar: Int
) = {
try {
if (starCycleGuard) throw StarCycleException()
starCycleGuard = true
// For a given node N...
// Number of foo :=* N
// + Number of bar :=* foo :*=* N
val oStars = oBindings.count { case (_, n, b, _, _) =>
b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) < 0)
}
// Number of N :*= foo
// + Number of N :*=* foo :*= bar
val iStars = iBindings.count { case (_, n, b, _, _) =>
b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) > 0)
}
// 1 for foo := N
// + bar.iStar for bar :*= foo :*=* N
// + foo.iStar for foo :*= N
// + 0 for foo :=* N
val oKnown = oBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, 0, n.iStar)
case BIND_QUERY => n.iStar
case BIND_STAR => 0
}
}.sum
// 1 for N := foo
// + bar.oStar for N :*=* foo :=* bar
// + foo.oStar for N :=* foo
// + 0 for N :*= foo
val iKnown = iBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, n.oStar, 0)
case BIND_QUERY => n.oStar
case BIND_STAR => 0
}
}.sum
// Resolve star depends on the node subclass to implement the algorithm for this.
val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars)
// Cumulative list of resolved outward binding range starting points
val oSum = oBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar)
case BIND_QUERY => n.iStar
case BIND_STAR => oStar
}
}.scanLeft(0)(_ + _)
// Cumulative list of resolved inward binding range starting points
val iSum = iBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar)
case BIND_QUERY => n.oStar
case BIND_STAR => iStar
}
}.scanLeft(0)(_ + _)
// Create ranges for each binding based on the running sums and return
// those along with resolved values for the star operations.
(oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar)
} catch {
case c: StarCycleException => throw c.copy(loop = context +: c.loop)
}
}
/** Sequence of inward ports.
*
* This should be called after all star bindings are resolved.
*
* Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding.
* `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this
* connection was made in the source code.
*/
protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] =
oBindings.flatMap { case (i, n, _, p, s) =>
// for each binding operator in this node, look at what it connects to
val (start, end) = n.iPortMapping(i)
(start until end).map { j => (j, n, p, s) }
}
/** Sequence of outward ports.
*
* This should be called after all star bindings are resolved.
*
* `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of
* outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection
* was made in the source code.
*/
protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] =
iBindings.flatMap { case (i, n, _, p, s) =>
// query this port index range of this node in the other side of node.
val (start, end) = n.oPortMapping(i)
(start until end).map { j => (j, n, p, s) }
}
// Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree
// Thus, there must exist an Eulerian path and the below algorithms terminate
@scala.annotation.tailrec
private def oTrace(
tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)
): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match {
case (i, n, p, s) => n.iForward(i) match {
case None => (i, n, p, s)
case Some((j, m)) => oTrace((j, m, p, s))
}
}
@scala.annotation.tailrec
private def iTrace(
tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)
): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match {
case (i, n, p, s) => n.oForward(i) match {
case None => (i, n, p, s)
case Some((j, m)) => iTrace((j, m, p, s))
}
}
/** Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved.
*
* Each Port is a tuple of:
* - Numeric index of this binding in the [[InwardNode]] on the other end.
* - [[InwardNode]] on the other end of this binding.
* - A view of [[Parameters]] where the binding occurred.
* - [[SourceInfo]] for source-level error reporting.
*/
lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace)
/** Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved.
*
* Each Port is a tuple of:
* - numeric index of this binding in [[OutwardNode]] on the other end.
* - [[OutwardNode]] on the other end of this binding.
* - a view of [[Parameters]] where the binding occurred.
* - [[SourceInfo]] for source-level error reporting.
*/
lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace)
private var oParamsCycleGuard = false
protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) }
protected[diplomacy] lazy val doParams: Seq[DO] = {
try {
if (oParamsCycleGuard) throw DownwardCycleException()
oParamsCycleGuard = true
val o = mapParamsD(oPorts.size, diParams)
require(
o.size == oPorts.size,
s"""Diplomacy has detected a problem with your graph:
|At the following node, the number of outward ports should equal the number of produced outward parameters.
|$context
|$connectedPortsInfo
|Downstreamed inward parameters: [${diParams.mkString(",")}]
|Produced outward parameters: [${o.mkString(",")}]
|""".stripMargin
)
o.map(outer.mixO(_, this))
} catch {
case c: DownwardCycleException => throw c.copy(loop = context +: c.loop)
}
}
private var iParamsCycleGuard = false
protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) }
protected[diplomacy] lazy val uiParams: Seq[UI] = {
try {
if (iParamsCycleGuard) throw UpwardCycleException()
iParamsCycleGuard = true
val i = mapParamsU(iPorts.size, uoParams)
require(
i.size == iPorts.size,
s"""Diplomacy has detected a problem with your graph:
|At the following node, the number of inward ports should equal the number of produced inward parameters.
|$context
|$connectedPortsInfo
|Upstreamed outward parameters: [${uoParams.mkString(",")}]
|Produced inward parameters: [${i.mkString(",")}]
|""".stripMargin
)
i.map(inner.mixI(_, this))
} catch {
case c: UpwardCycleException => throw c.copy(loop = context +: c.loop)
}
}
/** Outward edge parameters. */
protected[diplomacy] lazy val edgesOut: Seq[EO] =
(oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) }
/** Inward edge parameters. */
protected[diplomacy] lazy val edgesIn: Seq[EI] =
(iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) }
/** A tuple of the input edge parameters and output edge parameters for the edges bound to this node.
*
* If you need to access to the edges of a foreign Node, use this method (in/out create bundles).
*/
lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut)
/** Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. */
protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e =>
val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out")
// TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue,
// In the future, we should add an option to decide whether allowing unconnected in the LazyModule
x := DontCare
x
}
/** Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. */
protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e =>
val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In")
// TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue,
// In the future, we should add an option to decide whether allowing unconnected in the LazyModule
x := DontCare
x
}
private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) =>
Dangle(
source = HalfEdge(serial, i),
sink = HalfEdge(n.serial, j),
flipped = false,
name = wirePrefix + "out",
dataOpt = None
)
}
private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) =>
Dangle(
source = HalfEdge(n.serial, j),
sink = HalfEdge(serial, i),
flipped = true,
name = wirePrefix + "in",
dataOpt = None
)
}
/** Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. */
protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) =>
d.copy(dataOpt = Some(bundleOut(i)))
}
/** Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. */
protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) =>
d.copy(dataOpt = Some(bundleIn(i)))
}
private[diplomacy] var instantiated = false
/** Gather Bundle and edge parameters of outward ports.
*
* Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within
* [[LazyModuleImp]] code or after its instantiation has completed.
*/
def out: Seq[(BO, EO)] = {
require(
instantiated,
s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun"
)
bundleOut.zip(edgesOut)
}
/** Gather Bundle and edge parameters of inward ports.
*
* Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within
* [[LazyModuleImp]] code or after its instantiation has completed.
*/
def in: Seq[(BI, EI)] = {
require(
instantiated,
s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun"
)
bundleIn.zip(edgesIn)
}
/** Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires,
* instantiate monitors on all input ports if appropriate, and return all the dangles of this node.
*/
protected[diplomacy] def instantiate(): Seq[Dangle] = {
instantiated = true
if (!circuitIdentity) {
(iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) }
}
danglesOut ++ danglesIn
}
protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn
/** Connects the outward part of a node with the inward part of this node. */
protected[diplomacy] def bind(
h: OutwardNode[DI, UI, BI],
binding: NodeBinding
)(
implicit p: Parameters,
sourceInfo: SourceInfo
): Unit = {
val x = this // x := y
val y = h
sourceLine(sourceInfo, " at ", "")
val i = x.iPushed
val o = y.oPushed
y.oPush(
i,
x,
binding match {
case BIND_ONCE => BIND_ONCE
case BIND_FLEX => BIND_FLEX
case BIND_STAR => BIND_QUERY
case BIND_QUERY => BIND_STAR
}
)
x.iPush(o, y, binding)
}
/* Metadata for printing the node graph. */
def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) =>
val re = inner.render(e)
(n, re.copy(flipped = re.flipped != p(RenderFlipped)))
}
/** Metadata for printing the node graph */
def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) }
}
| module IntSyncSyncCrossingSink_n1x1_15( // @[Crossing.scala:96:9]
input auto_in_sync_0, // @[LazyModuleImp.scala:107:25]
output auto_out_0 // @[LazyModuleImp.scala:107:25]
);
wire auto_in_sync_0_0 = auto_in_sync_0; // @[Crossing.scala:96:9]
wire childClock = 1'h0; // @[LazyModuleImp.scala:155:31]
wire childReset = 1'h0; // @[LazyModuleImp.scala:158:31]
wire _childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25]
wire nodeIn_sync_0 = auto_in_sync_0_0; // @[Crossing.scala:96:9]
wire nodeOut_0; // @[MixedNode.scala:542:17]
wire auto_out_0_0; // @[Crossing.scala:96:9]
assign nodeOut_0 = nodeIn_sync_0; // @[MixedNode.scala:542:17, :551:17]
assign auto_out_0_0 = nodeOut_0; // @[Crossing.scala:96:9]
assign auto_out_0 = auto_out_0_0; // @[Crossing.scala:96:9]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File PE.scala:
// See README.md for license details.
package gemmini
import chisel3._
import chisel3.util._
class PEControl[T <: Data : Arithmetic](accType: T) extends Bundle {
val dataflow = UInt(1.W) // TODO make this an Enum
val propagate = UInt(1.W) // Which register should be propagated (and which should be accumulated)?
val shift = UInt(log2Up(accType.getWidth).W) // TODO this isn't correct for Floats
}
class MacUnit[T <: Data](inputType: T, cType: T, dType: T) (implicit ev: Arithmetic[T]) extends Module {
import ev._
val io = IO(new Bundle {
val in_a = Input(inputType)
val in_b = Input(inputType)
val in_c = Input(cType)
val out_d = Output(dType)
})
io.out_d := io.in_c.mac(io.in_a, io.in_b)
}
// TODO update documentation
/**
* A PE implementing a MAC operation. Configured as fully combinational when integrated into a Mesh.
* @param width Data width of operands
*/
class PE[T <: Data](inputType: T, outputType: T, accType: T, df: Dataflow.Value, max_simultaneous_matmuls: Int)
(implicit ev: Arithmetic[T]) extends Module { // Debugging variables
import ev._
val io = IO(new Bundle {
val in_a = Input(inputType)
val in_b = Input(outputType)
val in_d = Input(outputType)
val out_a = Output(inputType)
val out_b = Output(outputType)
val out_c = Output(outputType)
val in_control = Input(new PEControl(accType))
val out_control = Output(new PEControl(accType))
val in_id = Input(UInt(log2Up(max_simultaneous_matmuls).W))
val out_id = Output(UInt(log2Up(max_simultaneous_matmuls).W))
val in_last = Input(Bool())
val out_last = Output(Bool())
val in_valid = Input(Bool())
val out_valid = Output(Bool())
val bad_dataflow = Output(Bool())
})
val cType = if (df == Dataflow.WS) inputType else accType
// When creating PEs that support multiple dataflows, the
// elaboration/synthesis tools often fail to consolidate and de-duplicate
// MAC units. To force mac circuitry to be re-used, we create a "mac_unit"
// module here which just performs a single MAC operation
val mac_unit = Module(new MacUnit(inputType,
if (df == Dataflow.WS) outputType else accType, outputType))
val a = io.in_a
val b = io.in_b
val d = io.in_d
val c1 = Reg(cType)
val c2 = Reg(cType)
val dataflow = io.in_control.dataflow
val prop = io.in_control.propagate
val shift = io.in_control.shift
val id = io.in_id
val last = io.in_last
val valid = io.in_valid
io.out_a := a
io.out_control.dataflow := dataflow
io.out_control.propagate := prop
io.out_control.shift := shift
io.out_id := id
io.out_last := last
io.out_valid := valid
mac_unit.io.in_a := a
val last_s = RegEnable(prop, valid)
val flip = last_s =/= prop
val shift_offset = Mux(flip, shift, 0.U)
// Which dataflow are we using?
val OUTPUT_STATIONARY = Dataflow.OS.id.U(1.W)
val WEIGHT_STATIONARY = Dataflow.WS.id.U(1.W)
// Is c1 being computed on, or propagated forward (in the output-stationary dataflow)?
val COMPUTE = 0.U(1.W)
val PROPAGATE = 1.U(1.W)
io.bad_dataflow := false.B
when ((df == Dataflow.OS).B || ((df == Dataflow.BOTH).B && dataflow === OUTPUT_STATIONARY)) {
when(prop === PROPAGATE) {
io.out_c := (c1 >> shift_offset).clippedToWidthOf(outputType)
io.out_b := b
mac_unit.io.in_b := b.asTypeOf(inputType)
mac_unit.io.in_c := c2
c2 := mac_unit.io.out_d
c1 := d.withWidthOf(cType)
}.otherwise {
io.out_c := (c2 >> shift_offset).clippedToWidthOf(outputType)
io.out_b := b
mac_unit.io.in_b := b.asTypeOf(inputType)
mac_unit.io.in_c := c1
c1 := mac_unit.io.out_d
c2 := d.withWidthOf(cType)
}
}.elsewhen ((df == Dataflow.WS).B || ((df == Dataflow.BOTH).B && dataflow === WEIGHT_STATIONARY)) {
when(prop === PROPAGATE) {
io.out_c := c1
mac_unit.io.in_b := c2.asTypeOf(inputType)
mac_unit.io.in_c := b
io.out_b := mac_unit.io.out_d
c1 := d
}.otherwise {
io.out_c := c2
mac_unit.io.in_b := c1.asTypeOf(inputType)
mac_unit.io.in_c := b
io.out_b := mac_unit.io.out_d
c2 := d
}
}.otherwise {
io.bad_dataflow := true.B
//assert(false.B, "unknown dataflow")
io.out_c := DontCare
io.out_b := DontCare
mac_unit.io.in_b := b.asTypeOf(inputType)
mac_unit.io.in_c := c2
}
when (!valid) {
c1 := c1
c2 := c2
mac_unit.io.in_b := DontCare
mac_unit.io.in_c := DontCare
}
}
File recFNFromFN.scala:
/*============================================================================
This Chisel source file is part of a pre-release version of the HardFloat IEEE
Floating-Point Arithmetic Package, by John R. Hauser (with some contributions
from Yunsup Lee and Andrew Waterman, mainly concerning testing).
Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the
University of California. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
package hardfloat
import chisel3._
object recFNFromFN
{
def apply(expWidth: Int, sigWidth: Int, in: Bits) =
{
val rawIn = rawFloatFromFN(expWidth, sigWidth, in)
rawIn.sign ##
(Mux(rawIn.isZero, 0.U(3.W), rawIn.sExp(expWidth, expWidth - 2)) |
Mux(rawIn.isNaN, 1.U, 0.U)) ##
rawIn.sExp(expWidth - 3, 0) ##
rawIn.sig(sigWidth - 2, 0)
}
}
File Arithmetic.scala:
// A simple type class for Chisel datatypes that can add and multiply. To add your own type, simply create your own:
// implicit MyTypeArithmetic extends Arithmetic[MyType] { ... }
package gemmini
import chisel3._
import chisel3.util._
import hardfloat._
// Bundles that represent the raw bits of custom datatypes
case class Float(expWidth: Int, sigWidth: Int) extends Bundle {
val bits = UInt((expWidth + sigWidth).W)
val bias: Int = (1 << (expWidth-1)) - 1
}
case class DummySInt(w: Int) extends Bundle {
val bits = UInt(w.W)
def dontCare: DummySInt = {
val o = Wire(new DummySInt(w))
o.bits := 0.U
o
}
}
// The Arithmetic typeclass which implements various arithmetic operations on custom datatypes
abstract class Arithmetic[T <: Data] {
implicit def cast(t: T): ArithmeticOps[T]
}
abstract class ArithmeticOps[T <: Data](self: T) {
def *(t: T): T
def mac(m1: T, m2: T): T // Returns (m1 * m2 + self)
def +(t: T): T
def -(t: T): T
def >>(u: UInt): T // This is a rounding shift! Rounds away from 0
def >(t: T): Bool
def identity: T
def withWidthOf(t: T): T
def clippedToWidthOf(t: T): T // Like "withWidthOf", except that it saturates
def relu: T
def zero: T
def minimum: T
// Optional parameters, which only need to be defined if you want to enable various optimizations for transformers
def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[T])] = None
def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[T])] = None
def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = None
def mult_with_reciprocal[U <: Data](reciprocal: U) = self
}
object Arithmetic {
implicit object UIntArithmetic extends Arithmetic[UInt] {
override implicit def cast(self: UInt) = new ArithmeticOps(self) {
override def *(t: UInt) = self * t
override def mac(m1: UInt, m2: UInt) = m1 * m2 + self
override def +(t: UInt) = self + t
override def -(t: UInt) = self - t
override def >>(u: UInt) = {
// The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm
// TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here?
val point_five = Mux(u === 0.U, 0.U, self(u - 1.U))
val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U
val ones_digit = self(u)
val r = point_five & (zeros | ones_digit)
(self >> u).asUInt + r
}
override def >(t: UInt): Bool = self > t
override def withWidthOf(t: UInt) = self.asTypeOf(t)
override def clippedToWidthOf(t: UInt) = {
val sat = ((1 << (t.getWidth-1))-1).U
Mux(self > sat, sat, self)(t.getWidth-1, 0)
}
override def relu: UInt = self
override def zero: UInt = 0.U
override def identity: UInt = 1.U
override def minimum: UInt = 0.U
}
}
implicit object SIntArithmetic extends Arithmetic[SInt] {
override implicit def cast(self: SInt) = new ArithmeticOps(self) {
override def *(t: SInt) = self * t
override def mac(m1: SInt, m2: SInt) = m1 * m2 + self
override def +(t: SInt) = self + t
override def -(t: SInt) = self - t
override def >>(u: UInt) = {
// The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm
// TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here?
val point_five = Mux(u === 0.U, 0.U, self(u - 1.U))
val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U
val ones_digit = self(u)
val r = (point_five & (zeros | ones_digit)).asBool
(self >> u).asSInt + Mux(r, 1.S, 0.S)
}
override def >(t: SInt): Bool = self > t
override def withWidthOf(t: SInt) = {
if (self.getWidth >= t.getWidth)
self(t.getWidth-1, 0).asSInt
else {
val sign_bits = t.getWidth - self.getWidth
val sign = self(self.getWidth-1)
Cat(Cat(Seq.fill(sign_bits)(sign)), self).asTypeOf(t)
}
}
override def clippedToWidthOf(t: SInt): SInt = {
val maxsat = ((1 << (t.getWidth-1))-1).S
val minsat = (-(1 << (t.getWidth-1))).S
MuxCase(self, Seq((self > maxsat) -> maxsat, (self < minsat) -> minsat))(t.getWidth-1, 0).asSInt
}
override def relu: SInt = Mux(self >= 0.S, self, 0.S)
override def zero: SInt = 0.S
override def identity: SInt = 1.S
override def minimum: SInt = (-(1 << (self.getWidth-1))).S
override def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = {
// TODO this uses a floating point divider, but we should use an integer divider instead
val input = Wire(Decoupled(denom_t.cloneType))
val output = Wire(Decoupled(self.cloneType))
// We translate our integer to floating-point form so that we can use the hardfloat divider
val expWidth = log2Up(self.getWidth) + 1
val sigWidth = self.getWidth
def sin_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def uin_to_float(x: UInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := false.B
in_to_rec_fn.io.in := x
in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def float_to_in(x: UInt) = {
val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth))
rec_fn_to_in.io.signedOut := true.B
rec_fn_to_in.io.in := x
rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
rec_fn_to_in.io.out.asSInt
}
val self_rec = sin_to_float(self)
val denom_rec = uin_to_float(input.bits)
// Instantiate the hardloat divider
val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options))
input.ready := divider.io.inReady
divider.io.inValid := input.valid
divider.io.sqrtOp := false.B
divider.io.a := self_rec
divider.io.b := denom_rec
divider.io.roundingMode := consts.round_minMag
divider.io.detectTininess := consts.tininess_afterRounding
output.valid := divider.io.outValid_div
output.bits := float_to_in(divider.io.out)
assert(!output.valid || output.ready)
Some((input, output))
}
override def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = {
// TODO this uses a floating point divider, but we should use an integer divider instead
val input = Wire(Decoupled(UInt(0.W)))
val output = Wire(Decoupled(self.cloneType))
input.bits := DontCare
// We translate our integer to floating-point form so that we can use the hardfloat divider
val expWidth = log2Up(self.getWidth) + 1
val sigWidth = self.getWidth
def in_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def float_to_in(x: UInt) = {
val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth))
rec_fn_to_in.io.signedOut := true.B
rec_fn_to_in.io.in := x
rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
rec_fn_to_in.io.out.asSInt
}
val self_rec = in_to_float(self)
// Instantiate the hardloat sqrt
val sqrter = Module(new DivSqrtRecFN_small(expWidth, sigWidth, 0))
input.ready := sqrter.io.inReady
sqrter.io.inValid := input.valid
sqrter.io.sqrtOp := true.B
sqrter.io.a := self_rec
sqrter.io.b := DontCare
sqrter.io.roundingMode := consts.round_minMag
sqrter.io.detectTininess := consts.tininess_afterRounding
output.valid := sqrter.io.outValid_sqrt
output.bits := float_to_in(sqrter.io.out)
assert(!output.valid || output.ready)
Some((input, output))
}
override def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = u match {
case Float(expWidth, sigWidth) =>
val input = Wire(Decoupled(UInt(0.W)))
val output = Wire(Decoupled(u.cloneType))
input.bits := DontCare
// We translate our integer to floating-point form so that we can use the hardfloat divider
def in_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
val self_rec = in_to_float(self)
val one_rec = in_to_float(1.S)
// Instantiate the hardloat divider
val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options))
input.ready := divider.io.inReady
divider.io.inValid := input.valid
divider.io.sqrtOp := false.B
divider.io.a := one_rec
divider.io.b := self_rec
divider.io.roundingMode := consts.round_near_even
divider.io.detectTininess := consts.tininess_afterRounding
output.valid := divider.io.outValid_div
output.bits := fNFromRecFN(expWidth, sigWidth, divider.io.out).asTypeOf(u)
assert(!output.valid || output.ready)
Some((input, output))
case _ => None
}
override def mult_with_reciprocal[U <: Data](reciprocal: U): SInt = reciprocal match {
case recip @ Float(expWidth, sigWidth) =>
def in_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def float_to_in(x: UInt) = {
val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth))
rec_fn_to_in.io.signedOut := true.B
rec_fn_to_in.io.in := x
rec_fn_to_in.io.roundingMode := consts.round_minMag
rec_fn_to_in.io.out.asSInt
}
val self_rec = in_to_float(self)
val reciprocal_rec = recFNFromFN(expWidth, sigWidth, recip.bits)
// Instantiate the hardloat divider
val muladder = Module(new MulRecFN(expWidth, sigWidth))
muladder.io.roundingMode := consts.round_near_even
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := self_rec
muladder.io.b := reciprocal_rec
float_to_in(muladder.io.out)
case _ => self
}
}
}
implicit object FloatArithmetic extends Arithmetic[Float] {
// TODO Floating point arithmetic currently switches between recoded and standard formats for every operation. However, it should stay in the recoded format as it travels through the systolic array
override implicit def cast(self: Float): ArithmeticOps[Float] = new ArithmeticOps(self) {
override def *(t: Float): Float = {
val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth))
t_resizer.io.in := t_rec
t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
t_resizer.io.detectTininess := consts.tininess_afterRounding
val t_rec_resized = t_resizer.io.out
val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth))
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := self_rec
muladder.io.b := t_rec_resized
val out = Wire(Float(self.expWidth, self.sigWidth))
out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
out
}
override def mac(m1: Float, m2: Float): Float = {
// Recode all operands
val m1_rec = recFNFromFN(m1.expWidth, m1.sigWidth, m1.bits)
val m2_rec = recFNFromFN(m2.expWidth, m2.sigWidth, m2.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Resize m1 to self's width
val m1_resizer = Module(new RecFNToRecFN(m1.expWidth, m1.sigWidth, self.expWidth, self.sigWidth))
m1_resizer.io.in := m1_rec
m1_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
m1_resizer.io.detectTininess := consts.tininess_afterRounding
val m1_rec_resized = m1_resizer.io.out
// Resize m2 to self's width
val m2_resizer = Module(new RecFNToRecFN(m2.expWidth, m2.sigWidth, self.expWidth, self.sigWidth))
m2_resizer.io.in := m2_rec
m2_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
m2_resizer.io.detectTininess := consts.tininess_afterRounding
val m2_rec_resized = m2_resizer.io.out
// Perform multiply-add
val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth))
muladder.io.op := 0.U
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := m1_rec_resized
muladder.io.b := m2_rec_resized
muladder.io.c := self_rec
// Convert result to standard format // TODO remove these intermediate recodings
val out = Wire(Float(self.expWidth, self.sigWidth))
out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
out
}
override def +(t: Float): Float = {
require(self.getWidth >= t.getWidth) // This just makes it easier to write the resizing code
// Recode all operands
val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Generate 1 as a float
val in_to_rec_fn = Module(new INToRecFN(1, self.expWidth, self.sigWidth))
in_to_rec_fn.io.signedIn := false.B
in_to_rec_fn.io.in := 1.U
in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
val one_rec = in_to_rec_fn.io.out
// Resize t
val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth))
t_resizer.io.in := t_rec
t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
t_resizer.io.detectTininess := consts.tininess_afterRounding
val t_rec_resized = t_resizer.io.out
// Perform addition
val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth))
muladder.io.op := 0.U
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := t_rec_resized
muladder.io.b := one_rec
muladder.io.c := self_rec
val result = Wire(Float(self.expWidth, self.sigWidth))
result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
result
}
override def -(t: Float): Float = {
val t_sgn = t.bits(t.getWidth-1)
val neg_t = Cat(~t_sgn, t.bits(t.getWidth-2,0)).asTypeOf(t)
self + neg_t
}
override def >>(u: UInt): Float = {
// Recode self
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Get 2^(-u) as a recoded float
val shift_exp = Wire(UInt(self.expWidth.W))
shift_exp := self.bias.U - u
val shift_fn = Cat(0.U(1.W), shift_exp, 0.U((self.sigWidth-1).W))
val shift_rec = recFNFromFN(self.expWidth, self.sigWidth, shift_fn)
assert(shift_exp =/= 0.U, "scaling by denormalized numbers is not currently supported")
// Multiply self and 2^(-u)
val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth))
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := self_rec
muladder.io.b := shift_rec
val result = Wire(Float(self.expWidth, self.sigWidth))
result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
result
}
override def >(t: Float): Bool = {
// Recode all operands
val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Resize t to self's width
val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth))
t_resizer.io.in := t_rec
t_resizer.io.roundingMode := consts.round_near_even
t_resizer.io.detectTininess := consts.tininess_afterRounding
val t_rec_resized = t_resizer.io.out
val comparator = Module(new CompareRecFN(self.expWidth, self.sigWidth))
comparator.io.a := self_rec
comparator.io.b := t_rec_resized
comparator.io.signaling := false.B
comparator.io.gt
}
override def withWidthOf(t: Float): Float = {
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth))
resizer.io.in := self_rec
resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
resizer.io.detectTininess := consts.tininess_afterRounding
val result = Wire(Float(t.expWidth, t.sigWidth))
result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out)
result
}
override def clippedToWidthOf(t: Float): Float = {
// TODO check for overflow. Right now, we just assume that overflow doesn't happen
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth))
resizer.io.in := self_rec
resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
resizer.io.detectTininess := consts.tininess_afterRounding
val result = Wire(Float(t.expWidth, t.sigWidth))
result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out)
result
}
override def relu: Float = {
val raw = rawFloatFromFN(self.expWidth, self.sigWidth, self.bits)
val result = Wire(Float(self.expWidth, self.sigWidth))
result.bits := Mux(!raw.isZero && raw.sign, 0.U, self.bits)
result
}
override def zero: Float = 0.U.asTypeOf(self)
override def identity: Float = Cat(0.U(2.W), ~(0.U((self.expWidth-1).W)), 0.U((self.sigWidth-1).W)).asTypeOf(self)
override def minimum: Float = Cat(1.U, ~(0.U(self.expWidth.W)), 0.U((self.sigWidth-1).W)).asTypeOf(self)
}
}
implicit object DummySIntArithmetic extends Arithmetic[DummySInt] {
override implicit def cast(self: DummySInt) = new ArithmeticOps(self) {
override def *(t: DummySInt) = self.dontCare
override def mac(m1: DummySInt, m2: DummySInt) = self.dontCare
override def +(t: DummySInt) = self.dontCare
override def -(t: DummySInt) = self.dontCare
override def >>(t: UInt) = self.dontCare
override def >(t: DummySInt): Bool = false.B
override def identity = self.dontCare
override def withWidthOf(t: DummySInt) = self.dontCare
override def clippedToWidthOf(t: DummySInt) = self.dontCare
override def relu = self.dontCare
override def zero = self.dontCare
override def minimum: DummySInt = self.dontCare
}
}
}
File fNFromRecFN.scala:
/*============================================================================
This Chisel source file is part of a pre-release version of the HardFloat IEEE
Floating-Point Arithmetic Package, by John R. Hauser (with some contributions
from Yunsup Lee and Andrew Waterman, mainly concerning testing).
Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
University of California. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
package hardfloat
import chisel3._
import chisel3.util._
object fNFromRecFN
{
def apply(expWidth: Int, sigWidth: Int, in: Bits) =
{
val minNormExp = (BigInt(1)<<(expWidth - 1)) + 2
val rawIn = rawFloatFromRecFN(expWidth, sigWidth, in)
val isSubnormal = rawIn.sExp < minNormExp.S
val denormShiftDist = 1.U - rawIn.sExp(log2Up(sigWidth - 1) - 1, 0)
val denormFract = ((rawIn.sig>>1)>>denormShiftDist)(sigWidth - 2, 0)
val expOut =
Mux(isSubnormal,
0.U,
rawIn.sExp(expWidth - 1, 0) -
((BigInt(1)<<(expWidth - 1)) + 1).U
) | Fill(expWidth, rawIn.isNaN || rawIn.isInf)
val fractOut =
Mux(isSubnormal,
denormFract,
Mux(rawIn.isInf, 0.U, rawIn.sig(sigWidth - 2, 0))
)
Cat(rawIn.sign, expOut, fractOut)
}
}
File rawFloatFromFN.scala:
/*============================================================================
This Chisel source file is part of a pre-release version of the HardFloat IEEE
Floating-Point Arithmetic Package, by John R. Hauser (with some contributions
from Yunsup Lee and Andrew Waterman, mainly concerning testing).
Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
University of California. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
package hardfloat
import chisel3._
object rawFloatFromFN {
def apply(expWidth: Int, sigWidth: Int, in: Bits) = {
val sign = in(expWidth + sigWidth - 1)
val expIn = in(expWidth + sigWidth - 2, sigWidth - 1)
val fractIn = in(sigWidth - 2, 0)
val isZeroExpIn = (expIn === 0.U)
val isZeroFractIn = (fractIn === 0.U)
val normDist = countLeadingZeros(fractIn)
val subnormFract = (fractIn << normDist) (sigWidth - 3, 0) << 1
val adjustedExp =
Mux(isZeroExpIn,
normDist ^ ((BigInt(1) << (expWidth + 1)) - 1).U,
expIn
) + ((BigInt(1) << (expWidth - 1)).U
| Mux(isZeroExpIn, 2.U, 1.U))
val isZero = isZeroExpIn && isZeroFractIn
val isSpecial = adjustedExp(expWidth, expWidth - 1) === 3.U
val out = Wire(new RawFloat(expWidth, sigWidth))
out.isNaN := isSpecial && !isZeroFractIn
out.isInf := isSpecial && isZeroFractIn
out.isZero := isZero
out.sign := sign
out.sExp := adjustedExp(expWidth, 0).zext
out.sig :=
0.U(1.W) ## !isZero ## Mux(isZeroExpIn, subnormFract, fractIn)
out
}
}
File rawFloatFromRecFN.scala:
/*============================================================================
This Chisel source file is part of a pre-release version of the HardFloat IEEE
Floating-Point Arithmetic Package, by John R. Hauser (with some contributions
from Yunsup Lee and Andrew Waterman, mainly concerning testing).
Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the
University of California. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
package hardfloat
import chisel3._
import chisel3.util._
/*----------------------------------------------------------------------------
| In the result, no more than one of 'isNaN', 'isInf', and 'isZero' will be
| set.
*----------------------------------------------------------------------------*/
object rawFloatFromRecFN
{
def apply(expWidth: Int, sigWidth: Int, in: Bits): RawFloat =
{
val exp = in(expWidth + sigWidth - 1, sigWidth - 1)
val isZero = exp(expWidth, expWidth - 2) === 0.U
val isSpecial = exp(expWidth, expWidth - 1) === 3.U
val out = Wire(new RawFloat(expWidth, sigWidth))
out.isNaN := isSpecial && exp(expWidth - 2)
out.isInf := isSpecial && ! exp(expWidth - 2)
out.isZero := isZero
out.sign := in(expWidth + sigWidth)
out.sExp := exp.zext
out.sig := 0.U(1.W) ## ! isZero ## in(sigWidth - 2, 0)
out
}
}
| module PE_17( // @[PE.scala:31:7]
input clock, // @[PE.scala:31:7]
input reset, // @[PE.scala:31:7]
input [31:0] io_in_a_bits, // @[PE.scala:35:14]
input [31:0] io_in_b_bits, // @[PE.scala:35:14]
input [31:0] io_in_d_bits, // @[PE.scala:35:14]
output [31:0] io_out_a_bits, // @[PE.scala:35:14]
output [31:0] io_out_b_bits, // @[PE.scala:35:14]
output [31:0] io_out_c_bits, // @[PE.scala:35:14]
input io_in_control_dataflow, // @[PE.scala:35:14]
input io_in_control_propagate, // @[PE.scala:35:14]
input [4:0] io_in_control_shift, // @[PE.scala:35:14]
output io_out_control_dataflow, // @[PE.scala:35:14]
output io_out_control_propagate, // @[PE.scala:35:14]
output [4:0] io_out_control_shift, // @[PE.scala:35:14]
input [3:0] io_in_id, // @[PE.scala:35:14]
output [3:0] io_out_id, // @[PE.scala:35:14]
input io_in_last, // @[PE.scala:35:14]
output io_out_last, // @[PE.scala:35:14]
input io_in_valid, // @[PE.scala:35:14]
output io_out_valid, // @[PE.scala:35:14]
output io_bad_dataflow // @[PE.scala:35:14]
);
wire c2_self_rec_rawIn_isNaN; // @[rawFloatFromFN.scala:63:19]
wire io_out_c_self_rec_rawIn_3_isNaN; // @[rawFloatFromFN.scala:63:19]
wire io_out_c_shift_rec_rawIn_1_isNaN; // @[rawFloatFromFN.scala:63:19]
wire io_out_c_self_rec_rawIn_2_isNaN; // @[rawFloatFromFN.scala:63:19]
wire c1_self_rec_rawIn_isNaN; // @[rawFloatFromFN.scala:63:19]
wire io_out_c_self_rec_rawIn_1_isNaN; // @[rawFloatFromFN.scala:63:19]
wire io_out_c_shift_rec_rawIn_isNaN; // @[rawFloatFromFN.scala:63:19]
wire io_out_c_self_rec_rawIn_isNaN; // @[rawFloatFromFN.scala:63:19]
wire [32:0] _c2_resizer_io_out; // @[Arithmetic.scala:486:29]
wire [32:0] _io_out_c_resizer_1_io_out; // @[Arithmetic.scala:500:29]
wire [32:0] _io_out_c_muladder_1_io_out; // @[Arithmetic.scala:450:30]
wire [32:0] _c1_resizer_io_out; // @[Arithmetic.scala:486:29]
wire [32:0] _io_out_c_resizer_io_out; // @[Arithmetic.scala:500:29]
wire [32:0] _io_out_c_muladder_io_out; // @[Arithmetic.scala:450:30]
wire [31:0] _mac_unit_io_out_d_bits; // @[PE.scala:64:24]
wire [31:0] io_in_a_bits_0 = io_in_a_bits; // @[PE.scala:31:7]
wire [31:0] io_in_b_bits_0 = io_in_b_bits; // @[PE.scala:31:7]
wire [31:0] io_in_d_bits_0 = io_in_d_bits; // @[PE.scala:31:7]
wire io_in_control_dataflow_0 = io_in_control_dataflow; // @[PE.scala:31:7]
wire io_in_control_propagate_0 = io_in_control_propagate; // @[PE.scala:31:7]
wire [4:0] io_in_control_shift_0 = io_in_control_shift; // @[PE.scala:31:7]
wire [3:0] io_in_id_0 = io_in_id; // @[PE.scala:31:7]
wire io_in_last_0 = io_in_last; // @[PE.scala:31:7]
wire io_in_valid_0 = io_in_valid; // @[PE.scala:31:7]
wire _io_out_c_T_1 = reset; // @[Arithmetic.scala:447:15]
wire _io_out_c_T_5 = reset; // @[Arithmetic.scala:447:15]
wire io_bad_dataflow_0 = 1'h0; // @[PE.scala:31:7]
wire [31:0] io_out_a_bits_0 = io_in_a_bits_0; // @[PE.scala:31:7]
wire [31:0] _mac_unit_io_in_b_WIRE_1 = io_in_b_bits_0; // @[PE.scala:31:7, :106:37]
wire [31:0] _mac_unit_io_in_b_WIRE_3 = io_in_b_bits_0; // @[PE.scala:31:7, :113:37]
wire [31:0] _mac_unit_io_in_b_WIRE_9 = io_in_b_bits_0; // @[PE.scala:31:7, :137:35]
wire io_out_control_dataflow_0 = io_in_control_dataflow_0; // @[PE.scala:31:7]
wire io_out_control_propagate_0 = io_in_control_propagate_0; // @[PE.scala:31:7]
wire [4:0] io_out_control_shift_0 = io_in_control_shift_0; // @[PE.scala:31:7]
wire [3:0] io_out_id_0 = io_in_id_0; // @[PE.scala:31:7]
wire io_out_last_0 = io_in_last_0; // @[PE.scala:31:7]
wire io_out_valid_0 = io_in_valid_0; // @[PE.scala:31:7]
wire [31:0] io_out_b_bits_0; // @[PE.scala:31:7]
wire [31:0] io_out_c_bits_0; // @[PE.scala:31:7]
reg [31:0] c1_bits; // @[PE.scala:70:15]
wire [31:0] _mac_unit_io_in_b_WIRE_7 = c1_bits; // @[PE.scala:70:15, :127:38]
reg [31:0] c2_bits; // @[PE.scala:71:15]
wire [31:0] _mac_unit_io_in_b_WIRE_5 = c2_bits; // @[PE.scala:71:15, :121:38]
reg last_s; // @[PE.scala:89:25]
wire flip = last_s != io_in_control_propagate_0; // @[PE.scala:31:7, :89:25, :90:21]
wire [4:0] shift_offset = flip ? io_in_control_shift_0 : 5'h0; // @[PE.scala:31:7, :90:21, :91:25]
wire io_out_c_self_rec_rawIn_sign = c1_bits[31]; // @[rawFloatFromFN.scala:44:18]
wire io_out_c_self_rec_rawIn_sign_0 = io_out_c_self_rec_rawIn_sign; // @[rawFloatFromFN.scala:44:18, :63:19]
wire [7:0] io_out_c_self_rec_rawIn_expIn = c1_bits[30:23]; // @[rawFloatFromFN.scala:45:19]
wire [22:0] io_out_c_self_rec_rawIn_fractIn = c1_bits[22:0]; // @[rawFloatFromFN.scala:46:21]
wire io_out_c_self_rec_rawIn_isZeroExpIn = io_out_c_self_rec_rawIn_expIn == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30]
wire io_out_c_self_rec_rawIn_isZeroFractIn = io_out_c_self_rec_rawIn_fractIn == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34]
wire _io_out_c_self_rec_rawIn_normDist_T = io_out_c_self_rec_rawIn_fractIn[0]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_c_self_rec_rawIn_normDist_T_1 = io_out_c_self_rec_rawIn_fractIn[1]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_c_self_rec_rawIn_normDist_T_2 = io_out_c_self_rec_rawIn_fractIn[2]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_c_self_rec_rawIn_normDist_T_3 = io_out_c_self_rec_rawIn_fractIn[3]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_c_self_rec_rawIn_normDist_T_4 = io_out_c_self_rec_rawIn_fractIn[4]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_c_self_rec_rawIn_normDist_T_5 = io_out_c_self_rec_rawIn_fractIn[5]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_c_self_rec_rawIn_normDist_T_6 = io_out_c_self_rec_rawIn_fractIn[6]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_c_self_rec_rawIn_normDist_T_7 = io_out_c_self_rec_rawIn_fractIn[7]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_c_self_rec_rawIn_normDist_T_8 = io_out_c_self_rec_rawIn_fractIn[8]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_c_self_rec_rawIn_normDist_T_9 = io_out_c_self_rec_rawIn_fractIn[9]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_c_self_rec_rawIn_normDist_T_10 = io_out_c_self_rec_rawIn_fractIn[10]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_c_self_rec_rawIn_normDist_T_11 = io_out_c_self_rec_rawIn_fractIn[11]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_c_self_rec_rawIn_normDist_T_12 = io_out_c_self_rec_rawIn_fractIn[12]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_c_self_rec_rawIn_normDist_T_13 = io_out_c_self_rec_rawIn_fractIn[13]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_c_self_rec_rawIn_normDist_T_14 = io_out_c_self_rec_rawIn_fractIn[14]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_c_self_rec_rawIn_normDist_T_15 = io_out_c_self_rec_rawIn_fractIn[15]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_c_self_rec_rawIn_normDist_T_16 = io_out_c_self_rec_rawIn_fractIn[16]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_c_self_rec_rawIn_normDist_T_17 = io_out_c_self_rec_rawIn_fractIn[17]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_c_self_rec_rawIn_normDist_T_18 = io_out_c_self_rec_rawIn_fractIn[18]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_c_self_rec_rawIn_normDist_T_19 = io_out_c_self_rec_rawIn_fractIn[19]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_c_self_rec_rawIn_normDist_T_20 = io_out_c_self_rec_rawIn_fractIn[20]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_c_self_rec_rawIn_normDist_T_21 = io_out_c_self_rec_rawIn_fractIn[21]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_c_self_rec_rawIn_normDist_T_22 = io_out_c_self_rec_rawIn_fractIn[22]; // @[rawFloatFromFN.scala:46:21]
wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_23 = _io_out_c_self_rec_rawIn_normDist_T_1 ? 5'h15 : 5'h16; // @[Mux.scala:50:70]
wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_24 = _io_out_c_self_rec_rawIn_normDist_T_2 ? 5'h14 : _io_out_c_self_rec_rawIn_normDist_T_23; // @[Mux.scala:50:70]
wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_25 = _io_out_c_self_rec_rawIn_normDist_T_3 ? 5'h13 : _io_out_c_self_rec_rawIn_normDist_T_24; // @[Mux.scala:50:70]
wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_26 = _io_out_c_self_rec_rawIn_normDist_T_4 ? 5'h12 : _io_out_c_self_rec_rawIn_normDist_T_25; // @[Mux.scala:50:70]
wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_27 = _io_out_c_self_rec_rawIn_normDist_T_5 ? 5'h11 : _io_out_c_self_rec_rawIn_normDist_T_26; // @[Mux.scala:50:70]
wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_28 = _io_out_c_self_rec_rawIn_normDist_T_6 ? 5'h10 : _io_out_c_self_rec_rawIn_normDist_T_27; // @[Mux.scala:50:70]
wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_29 = _io_out_c_self_rec_rawIn_normDist_T_7 ? 5'hF : _io_out_c_self_rec_rawIn_normDist_T_28; // @[Mux.scala:50:70]
wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_30 = _io_out_c_self_rec_rawIn_normDist_T_8 ? 5'hE : _io_out_c_self_rec_rawIn_normDist_T_29; // @[Mux.scala:50:70]
wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_31 = _io_out_c_self_rec_rawIn_normDist_T_9 ? 5'hD : _io_out_c_self_rec_rawIn_normDist_T_30; // @[Mux.scala:50:70]
wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_32 = _io_out_c_self_rec_rawIn_normDist_T_10 ? 5'hC : _io_out_c_self_rec_rawIn_normDist_T_31; // @[Mux.scala:50:70]
wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_33 = _io_out_c_self_rec_rawIn_normDist_T_11 ? 5'hB : _io_out_c_self_rec_rawIn_normDist_T_32; // @[Mux.scala:50:70]
wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_34 = _io_out_c_self_rec_rawIn_normDist_T_12 ? 5'hA : _io_out_c_self_rec_rawIn_normDist_T_33; // @[Mux.scala:50:70]
wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_35 = _io_out_c_self_rec_rawIn_normDist_T_13 ? 5'h9 : _io_out_c_self_rec_rawIn_normDist_T_34; // @[Mux.scala:50:70]
wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_36 = _io_out_c_self_rec_rawIn_normDist_T_14 ? 5'h8 : _io_out_c_self_rec_rawIn_normDist_T_35; // @[Mux.scala:50:70]
wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_37 = _io_out_c_self_rec_rawIn_normDist_T_15 ? 5'h7 : _io_out_c_self_rec_rawIn_normDist_T_36; // @[Mux.scala:50:70]
wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_38 = _io_out_c_self_rec_rawIn_normDist_T_16 ? 5'h6 : _io_out_c_self_rec_rawIn_normDist_T_37; // @[Mux.scala:50:70]
wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_39 = _io_out_c_self_rec_rawIn_normDist_T_17 ? 5'h5 : _io_out_c_self_rec_rawIn_normDist_T_38; // @[Mux.scala:50:70]
wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_40 = _io_out_c_self_rec_rawIn_normDist_T_18 ? 5'h4 : _io_out_c_self_rec_rawIn_normDist_T_39; // @[Mux.scala:50:70]
wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_41 = _io_out_c_self_rec_rawIn_normDist_T_19 ? 5'h3 : _io_out_c_self_rec_rawIn_normDist_T_40; // @[Mux.scala:50:70]
wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_42 = _io_out_c_self_rec_rawIn_normDist_T_20 ? 5'h2 : _io_out_c_self_rec_rawIn_normDist_T_41; // @[Mux.scala:50:70]
wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_43 = _io_out_c_self_rec_rawIn_normDist_T_21 ? 5'h1 : _io_out_c_self_rec_rawIn_normDist_T_42; // @[Mux.scala:50:70]
wire [4:0] io_out_c_self_rec_rawIn_normDist = _io_out_c_self_rec_rawIn_normDist_T_22 ? 5'h0 : _io_out_c_self_rec_rawIn_normDist_T_43; // @[Mux.scala:50:70]
wire [53:0] _io_out_c_self_rec_rawIn_subnormFract_T = {31'h0, io_out_c_self_rec_rawIn_fractIn} << io_out_c_self_rec_rawIn_normDist; // @[Mux.scala:50:70]
wire [21:0] _io_out_c_self_rec_rawIn_subnormFract_T_1 = _io_out_c_self_rec_rawIn_subnormFract_T[21:0]; // @[rawFloatFromFN.scala:52:{33,46}]
wire [22:0] io_out_c_self_rec_rawIn_subnormFract = {_io_out_c_self_rec_rawIn_subnormFract_T_1, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}]
wire [8:0] _io_out_c_self_rec_rawIn_adjustedExp_T = {4'hF, ~io_out_c_self_rec_rawIn_normDist}; // @[Mux.scala:50:70]
wire [8:0] _io_out_c_self_rec_rawIn_adjustedExp_T_1 = io_out_c_self_rec_rawIn_isZeroExpIn ? _io_out_c_self_rec_rawIn_adjustedExp_T : {1'h0, io_out_c_self_rec_rawIn_expIn}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18]
wire [1:0] _io_out_c_self_rec_rawIn_adjustedExp_T_2 = io_out_c_self_rec_rawIn_isZeroExpIn ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14]
wire [7:0] _io_out_c_self_rec_rawIn_adjustedExp_T_3 = {6'h20, _io_out_c_self_rec_rawIn_adjustedExp_T_2}; // @[rawFloatFromFN.scala:58:{9,14}]
wire [9:0] _io_out_c_self_rec_rawIn_adjustedExp_T_4 = {1'h0, _io_out_c_self_rec_rawIn_adjustedExp_T_1} + {2'h0, _io_out_c_self_rec_rawIn_adjustedExp_T_3}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9]
wire [8:0] io_out_c_self_rec_rawIn_adjustedExp = _io_out_c_self_rec_rawIn_adjustedExp_T_4[8:0]; // @[rawFloatFromFN.scala:57:9]
wire [8:0] _io_out_c_self_rec_rawIn_out_sExp_T = io_out_c_self_rec_rawIn_adjustedExp; // @[rawFloatFromFN.scala:57:9, :68:28]
wire io_out_c_self_rec_rawIn_isZero = io_out_c_self_rec_rawIn_isZeroExpIn & io_out_c_self_rec_rawIn_isZeroFractIn; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30]
wire io_out_c_self_rec_rawIn_isZero_0 = io_out_c_self_rec_rawIn_isZero; // @[rawFloatFromFN.scala:60:30, :63:19]
wire [1:0] _io_out_c_self_rec_rawIn_isSpecial_T = io_out_c_self_rec_rawIn_adjustedExp[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32]
wire io_out_c_self_rec_rawIn_isSpecial = &_io_out_c_self_rec_rawIn_isSpecial_T; // @[rawFloatFromFN.scala:61:{32,57}]
wire _io_out_c_self_rec_rawIn_out_isNaN_T_1; // @[rawFloatFromFN.scala:64:28]
wire _io_out_c_self_rec_rawIn_out_isInf_T; // @[rawFloatFromFN.scala:65:28]
wire _io_out_c_self_rec_T_2 = io_out_c_self_rec_rawIn_isNaN; // @[recFNFromFN.scala:49:20]
wire [9:0] _io_out_c_self_rec_rawIn_out_sExp_T_1; // @[rawFloatFromFN.scala:68:42]
wire [24:0] _io_out_c_self_rec_rawIn_out_sig_T_3; // @[rawFloatFromFN.scala:70:27]
wire io_out_c_self_rec_rawIn_isInf; // @[rawFloatFromFN.scala:63:19]
wire [9:0] io_out_c_self_rec_rawIn_sExp; // @[rawFloatFromFN.scala:63:19]
wire [24:0] io_out_c_self_rec_rawIn_sig; // @[rawFloatFromFN.scala:63:19]
wire _io_out_c_self_rec_rawIn_out_isNaN_T = ~io_out_c_self_rec_rawIn_isZeroFractIn; // @[rawFloatFromFN.scala:49:34, :64:31]
assign _io_out_c_self_rec_rawIn_out_isNaN_T_1 = io_out_c_self_rec_rawIn_isSpecial & _io_out_c_self_rec_rawIn_out_isNaN_T; // @[rawFloatFromFN.scala:61:57, :64:{28,31}]
assign io_out_c_self_rec_rawIn_isNaN = _io_out_c_self_rec_rawIn_out_isNaN_T_1; // @[rawFloatFromFN.scala:63:19, :64:28]
assign _io_out_c_self_rec_rawIn_out_isInf_T = io_out_c_self_rec_rawIn_isSpecial & io_out_c_self_rec_rawIn_isZeroFractIn; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28]
assign io_out_c_self_rec_rawIn_isInf = _io_out_c_self_rec_rawIn_out_isInf_T; // @[rawFloatFromFN.scala:63:19, :65:28]
assign _io_out_c_self_rec_rawIn_out_sExp_T_1 = {1'h0, _io_out_c_self_rec_rawIn_out_sExp_T}; // @[rawFloatFromFN.scala:68:{28,42}]
assign io_out_c_self_rec_rawIn_sExp = _io_out_c_self_rec_rawIn_out_sExp_T_1; // @[rawFloatFromFN.scala:63:19, :68:42]
wire _io_out_c_self_rec_rawIn_out_sig_T = ~io_out_c_self_rec_rawIn_isZero; // @[rawFloatFromFN.scala:60:30, :70:19]
wire [1:0] _io_out_c_self_rec_rawIn_out_sig_T_1 = {1'h0, _io_out_c_self_rec_rawIn_out_sig_T}; // @[rawFloatFromFN.scala:70:{16,19}]
wire [22:0] _io_out_c_self_rec_rawIn_out_sig_T_2 = io_out_c_self_rec_rawIn_isZeroExpIn ? io_out_c_self_rec_rawIn_subnormFract : io_out_c_self_rec_rawIn_fractIn; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33]
assign _io_out_c_self_rec_rawIn_out_sig_T_3 = {_io_out_c_self_rec_rawIn_out_sig_T_1, _io_out_c_self_rec_rawIn_out_sig_T_2}; // @[rawFloatFromFN.scala:70:{16,27,33}]
assign io_out_c_self_rec_rawIn_sig = _io_out_c_self_rec_rawIn_out_sig_T_3; // @[rawFloatFromFN.scala:63:19, :70:27]
wire [2:0] _io_out_c_self_rec_T = io_out_c_self_rec_rawIn_sExp[8:6]; // @[recFNFromFN.scala:48:50]
wire [2:0] _io_out_c_self_rec_T_1 = io_out_c_self_rec_rawIn_isZero_0 ? 3'h0 : _io_out_c_self_rec_T; // @[recFNFromFN.scala:48:{15,50}]
wire [2:0] _io_out_c_self_rec_T_3 = {_io_out_c_self_rec_T_1[2:1], _io_out_c_self_rec_T_1[0] | _io_out_c_self_rec_T_2}; // @[recFNFromFN.scala:48:{15,76}, :49:20]
wire [3:0] _io_out_c_self_rec_T_4 = {io_out_c_self_rec_rawIn_sign_0, _io_out_c_self_rec_T_3}; // @[recFNFromFN.scala:47:20, :48:76]
wire [5:0] _io_out_c_self_rec_T_5 = io_out_c_self_rec_rawIn_sExp[5:0]; // @[recFNFromFN.scala:50:23]
wire [9:0] _io_out_c_self_rec_T_6 = {_io_out_c_self_rec_T_4, _io_out_c_self_rec_T_5}; // @[recFNFromFN.scala:47:20, :49:45, :50:23]
wire [22:0] _io_out_c_self_rec_T_7 = io_out_c_self_rec_rawIn_sig[22:0]; // @[recFNFromFN.scala:51:22]
wire [32:0] io_out_c_self_rec = {_io_out_c_self_rec_T_6, _io_out_c_self_rec_T_7}; // @[recFNFromFN.scala:49:45, :50:41, :51:22]
wire [7:0] io_out_c_shift_exp; // @[Arithmetic.scala:442:29]
wire [7:0] _GEN = 8'h7F - {3'h0, shift_offset}; // @[PE.scala:91:25]
wire [7:0] _io_out_c_shift_exp_T; // @[Arithmetic.scala:443:34]
assign _io_out_c_shift_exp_T = _GEN; // @[Arithmetic.scala:443:34]
wire [7:0] _io_out_c_shift_exp_T_2; // @[Arithmetic.scala:443:34]
assign _io_out_c_shift_exp_T_2 = _GEN; // @[Arithmetic.scala:443:34]
wire [6:0] _io_out_c_shift_exp_T_1 = _io_out_c_shift_exp_T[6:0]; // @[Arithmetic.scala:443:34]
assign io_out_c_shift_exp = {1'h0, _io_out_c_shift_exp_T_1}; // @[Arithmetic.scala:442:29, :443:{19,34}]
wire [8:0] io_out_c_shift_fn_hi = {1'h0, io_out_c_shift_exp}; // @[Arithmetic.scala:442:29, :444:27]
wire [31:0] io_out_c_shift_fn = {io_out_c_shift_fn_hi, 23'h0}; // @[Arithmetic.scala:444:27]
wire io_out_c_shift_rec_rawIn_sign = io_out_c_shift_fn[31]; // @[rawFloatFromFN.scala:44:18]
wire io_out_c_shift_rec_rawIn_sign_0 = io_out_c_shift_rec_rawIn_sign; // @[rawFloatFromFN.scala:44:18, :63:19]
wire [7:0] io_out_c_shift_rec_rawIn_expIn = io_out_c_shift_fn[30:23]; // @[rawFloatFromFN.scala:45:19]
wire [22:0] io_out_c_shift_rec_rawIn_fractIn = io_out_c_shift_fn[22:0]; // @[rawFloatFromFN.scala:46:21]
wire io_out_c_shift_rec_rawIn_isZeroExpIn = io_out_c_shift_rec_rawIn_expIn == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30]
wire io_out_c_shift_rec_rawIn_isZeroFractIn = io_out_c_shift_rec_rawIn_fractIn == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34]
wire _io_out_c_shift_rec_rawIn_normDist_T = io_out_c_shift_rec_rawIn_fractIn[0]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_c_shift_rec_rawIn_normDist_T_1 = io_out_c_shift_rec_rawIn_fractIn[1]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_c_shift_rec_rawIn_normDist_T_2 = io_out_c_shift_rec_rawIn_fractIn[2]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_c_shift_rec_rawIn_normDist_T_3 = io_out_c_shift_rec_rawIn_fractIn[3]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_c_shift_rec_rawIn_normDist_T_4 = io_out_c_shift_rec_rawIn_fractIn[4]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_c_shift_rec_rawIn_normDist_T_5 = io_out_c_shift_rec_rawIn_fractIn[5]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_c_shift_rec_rawIn_normDist_T_6 = io_out_c_shift_rec_rawIn_fractIn[6]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_c_shift_rec_rawIn_normDist_T_7 = io_out_c_shift_rec_rawIn_fractIn[7]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_c_shift_rec_rawIn_normDist_T_8 = io_out_c_shift_rec_rawIn_fractIn[8]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_c_shift_rec_rawIn_normDist_T_9 = io_out_c_shift_rec_rawIn_fractIn[9]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_c_shift_rec_rawIn_normDist_T_10 = io_out_c_shift_rec_rawIn_fractIn[10]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_c_shift_rec_rawIn_normDist_T_11 = io_out_c_shift_rec_rawIn_fractIn[11]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_c_shift_rec_rawIn_normDist_T_12 = io_out_c_shift_rec_rawIn_fractIn[12]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_c_shift_rec_rawIn_normDist_T_13 = io_out_c_shift_rec_rawIn_fractIn[13]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_c_shift_rec_rawIn_normDist_T_14 = io_out_c_shift_rec_rawIn_fractIn[14]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_c_shift_rec_rawIn_normDist_T_15 = io_out_c_shift_rec_rawIn_fractIn[15]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_c_shift_rec_rawIn_normDist_T_16 = io_out_c_shift_rec_rawIn_fractIn[16]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_c_shift_rec_rawIn_normDist_T_17 = io_out_c_shift_rec_rawIn_fractIn[17]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_c_shift_rec_rawIn_normDist_T_18 = io_out_c_shift_rec_rawIn_fractIn[18]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_c_shift_rec_rawIn_normDist_T_19 = io_out_c_shift_rec_rawIn_fractIn[19]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_c_shift_rec_rawIn_normDist_T_20 = io_out_c_shift_rec_rawIn_fractIn[20]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_c_shift_rec_rawIn_normDist_T_21 = io_out_c_shift_rec_rawIn_fractIn[21]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_c_shift_rec_rawIn_normDist_T_22 = io_out_c_shift_rec_rawIn_fractIn[22]; // @[rawFloatFromFN.scala:46:21]
wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_23 = _io_out_c_shift_rec_rawIn_normDist_T_1 ? 5'h15 : 5'h16; // @[Mux.scala:50:70]
wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_24 = _io_out_c_shift_rec_rawIn_normDist_T_2 ? 5'h14 : _io_out_c_shift_rec_rawIn_normDist_T_23; // @[Mux.scala:50:70]
wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_25 = _io_out_c_shift_rec_rawIn_normDist_T_3 ? 5'h13 : _io_out_c_shift_rec_rawIn_normDist_T_24; // @[Mux.scala:50:70]
wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_26 = _io_out_c_shift_rec_rawIn_normDist_T_4 ? 5'h12 : _io_out_c_shift_rec_rawIn_normDist_T_25; // @[Mux.scala:50:70]
wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_27 = _io_out_c_shift_rec_rawIn_normDist_T_5 ? 5'h11 : _io_out_c_shift_rec_rawIn_normDist_T_26; // @[Mux.scala:50:70]
wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_28 = _io_out_c_shift_rec_rawIn_normDist_T_6 ? 5'h10 : _io_out_c_shift_rec_rawIn_normDist_T_27; // @[Mux.scala:50:70]
wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_29 = _io_out_c_shift_rec_rawIn_normDist_T_7 ? 5'hF : _io_out_c_shift_rec_rawIn_normDist_T_28; // @[Mux.scala:50:70]
wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_30 = _io_out_c_shift_rec_rawIn_normDist_T_8 ? 5'hE : _io_out_c_shift_rec_rawIn_normDist_T_29; // @[Mux.scala:50:70]
wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_31 = _io_out_c_shift_rec_rawIn_normDist_T_9 ? 5'hD : _io_out_c_shift_rec_rawIn_normDist_T_30; // @[Mux.scala:50:70]
wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_32 = _io_out_c_shift_rec_rawIn_normDist_T_10 ? 5'hC : _io_out_c_shift_rec_rawIn_normDist_T_31; // @[Mux.scala:50:70]
wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_33 = _io_out_c_shift_rec_rawIn_normDist_T_11 ? 5'hB : _io_out_c_shift_rec_rawIn_normDist_T_32; // @[Mux.scala:50:70]
wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_34 = _io_out_c_shift_rec_rawIn_normDist_T_12 ? 5'hA : _io_out_c_shift_rec_rawIn_normDist_T_33; // @[Mux.scala:50:70]
wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_35 = _io_out_c_shift_rec_rawIn_normDist_T_13 ? 5'h9 : _io_out_c_shift_rec_rawIn_normDist_T_34; // @[Mux.scala:50:70]
wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_36 = _io_out_c_shift_rec_rawIn_normDist_T_14 ? 5'h8 : _io_out_c_shift_rec_rawIn_normDist_T_35; // @[Mux.scala:50:70]
wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_37 = _io_out_c_shift_rec_rawIn_normDist_T_15 ? 5'h7 : _io_out_c_shift_rec_rawIn_normDist_T_36; // @[Mux.scala:50:70]
wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_38 = _io_out_c_shift_rec_rawIn_normDist_T_16 ? 5'h6 : _io_out_c_shift_rec_rawIn_normDist_T_37; // @[Mux.scala:50:70]
wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_39 = _io_out_c_shift_rec_rawIn_normDist_T_17 ? 5'h5 : _io_out_c_shift_rec_rawIn_normDist_T_38; // @[Mux.scala:50:70]
wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_40 = _io_out_c_shift_rec_rawIn_normDist_T_18 ? 5'h4 : _io_out_c_shift_rec_rawIn_normDist_T_39; // @[Mux.scala:50:70]
wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_41 = _io_out_c_shift_rec_rawIn_normDist_T_19 ? 5'h3 : _io_out_c_shift_rec_rawIn_normDist_T_40; // @[Mux.scala:50:70]
wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_42 = _io_out_c_shift_rec_rawIn_normDist_T_20 ? 5'h2 : _io_out_c_shift_rec_rawIn_normDist_T_41; // @[Mux.scala:50:70]
wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_43 = _io_out_c_shift_rec_rawIn_normDist_T_21 ? 5'h1 : _io_out_c_shift_rec_rawIn_normDist_T_42; // @[Mux.scala:50:70]
wire [4:0] io_out_c_shift_rec_rawIn_normDist = _io_out_c_shift_rec_rawIn_normDist_T_22 ? 5'h0 : _io_out_c_shift_rec_rawIn_normDist_T_43; // @[Mux.scala:50:70]
wire [53:0] _io_out_c_shift_rec_rawIn_subnormFract_T = {31'h0, io_out_c_shift_rec_rawIn_fractIn} << io_out_c_shift_rec_rawIn_normDist; // @[Mux.scala:50:70]
wire [21:0] _io_out_c_shift_rec_rawIn_subnormFract_T_1 = _io_out_c_shift_rec_rawIn_subnormFract_T[21:0]; // @[rawFloatFromFN.scala:52:{33,46}]
wire [22:0] io_out_c_shift_rec_rawIn_subnormFract = {_io_out_c_shift_rec_rawIn_subnormFract_T_1, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}]
wire [8:0] _io_out_c_shift_rec_rawIn_adjustedExp_T = {4'hF, ~io_out_c_shift_rec_rawIn_normDist}; // @[Mux.scala:50:70]
wire [8:0] _io_out_c_shift_rec_rawIn_adjustedExp_T_1 = io_out_c_shift_rec_rawIn_isZeroExpIn ? _io_out_c_shift_rec_rawIn_adjustedExp_T : {1'h0, io_out_c_shift_rec_rawIn_expIn}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18]
wire [1:0] _io_out_c_shift_rec_rawIn_adjustedExp_T_2 = io_out_c_shift_rec_rawIn_isZeroExpIn ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14]
wire [7:0] _io_out_c_shift_rec_rawIn_adjustedExp_T_3 = {6'h20, _io_out_c_shift_rec_rawIn_adjustedExp_T_2}; // @[rawFloatFromFN.scala:58:{9,14}]
wire [9:0] _io_out_c_shift_rec_rawIn_adjustedExp_T_4 = {1'h0, _io_out_c_shift_rec_rawIn_adjustedExp_T_1} + {2'h0, _io_out_c_shift_rec_rawIn_adjustedExp_T_3}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9]
wire [8:0] io_out_c_shift_rec_rawIn_adjustedExp = _io_out_c_shift_rec_rawIn_adjustedExp_T_4[8:0]; // @[rawFloatFromFN.scala:57:9]
wire [8:0] _io_out_c_shift_rec_rawIn_out_sExp_T = io_out_c_shift_rec_rawIn_adjustedExp; // @[rawFloatFromFN.scala:57:9, :68:28]
wire io_out_c_shift_rec_rawIn_isZero = io_out_c_shift_rec_rawIn_isZeroExpIn & io_out_c_shift_rec_rawIn_isZeroFractIn; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30]
wire io_out_c_shift_rec_rawIn_isZero_0 = io_out_c_shift_rec_rawIn_isZero; // @[rawFloatFromFN.scala:60:30, :63:19]
wire [1:0] _io_out_c_shift_rec_rawIn_isSpecial_T = io_out_c_shift_rec_rawIn_adjustedExp[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32]
wire io_out_c_shift_rec_rawIn_isSpecial = &_io_out_c_shift_rec_rawIn_isSpecial_T; // @[rawFloatFromFN.scala:61:{32,57}]
wire _io_out_c_shift_rec_rawIn_out_isNaN_T_1; // @[rawFloatFromFN.scala:64:28]
wire _io_out_c_shift_rec_rawIn_out_isInf_T; // @[rawFloatFromFN.scala:65:28]
wire _io_out_c_shift_rec_T_2 = io_out_c_shift_rec_rawIn_isNaN; // @[recFNFromFN.scala:49:20]
wire [9:0] _io_out_c_shift_rec_rawIn_out_sExp_T_1; // @[rawFloatFromFN.scala:68:42]
wire [24:0] _io_out_c_shift_rec_rawIn_out_sig_T_3; // @[rawFloatFromFN.scala:70:27]
wire io_out_c_shift_rec_rawIn_isInf; // @[rawFloatFromFN.scala:63:19]
wire [9:0] io_out_c_shift_rec_rawIn_sExp; // @[rawFloatFromFN.scala:63:19]
wire [24:0] io_out_c_shift_rec_rawIn_sig; // @[rawFloatFromFN.scala:63:19]
wire _io_out_c_shift_rec_rawIn_out_isNaN_T = ~io_out_c_shift_rec_rawIn_isZeroFractIn; // @[rawFloatFromFN.scala:49:34, :64:31]
assign _io_out_c_shift_rec_rawIn_out_isNaN_T_1 = io_out_c_shift_rec_rawIn_isSpecial & _io_out_c_shift_rec_rawIn_out_isNaN_T; // @[rawFloatFromFN.scala:61:57, :64:{28,31}]
assign io_out_c_shift_rec_rawIn_isNaN = _io_out_c_shift_rec_rawIn_out_isNaN_T_1; // @[rawFloatFromFN.scala:63:19, :64:28]
assign _io_out_c_shift_rec_rawIn_out_isInf_T = io_out_c_shift_rec_rawIn_isSpecial & io_out_c_shift_rec_rawIn_isZeroFractIn; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28]
assign io_out_c_shift_rec_rawIn_isInf = _io_out_c_shift_rec_rawIn_out_isInf_T; // @[rawFloatFromFN.scala:63:19, :65:28]
assign _io_out_c_shift_rec_rawIn_out_sExp_T_1 = {1'h0, _io_out_c_shift_rec_rawIn_out_sExp_T}; // @[rawFloatFromFN.scala:68:{28,42}]
assign io_out_c_shift_rec_rawIn_sExp = _io_out_c_shift_rec_rawIn_out_sExp_T_1; // @[rawFloatFromFN.scala:63:19, :68:42]
wire _io_out_c_shift_rec_rawIn_out_sig_T = ~io_out_c_shift_rec_rawIn_isZero; // @[rawFloatFromFN.scala:60:30, :70:19]
wire [1:0] _io_out_c_shift_rec_rawIn_out_sig_T_1 = {1'h0, _io_out_c_shift_rec_rawIn_out_sig_T}; // @[rawFloatFromFN.scala:70:{16,19}]
wire [22:0] _io_out_c_shift_rec_rawIn_out_sig_T_2 = io_out_c_shift_rec_rawIn_isZeroExpIn ? io_out_c_shift_rec_rawIn_subnormFract : io_out_c_shift_rec_rawIn_fractIn; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33]
assign _io_out_c_shift_rec_rawIn_out_sig_T_3 = {_io_out_c_shift_rec_rawIn_out_sig_T_1, _io_out_c_shift_rec_rawIn_out_sig_T_2}; // @[rawFloatFromFN.scala:70:{16,27,33}]
assign io_out_c_shift_rec_rawIn_sig = _io_out_c_shift_rec_rawIn_out_sig_T_3; // @[rawFloatFromFN.scala:63:19, :70:27]
wire [2:0] _io_out_c_shift_rec_T = io_out_c_shift_rec_rawIn_sExp[8:6]; // @[recFNFromFN.scala:48:50]
wire [2:0] _io_out_c_shift_rec_T_1 = io_out_c_shift_rec_rawIn_isZero_0 ? 3'h0 : _io_out_c_shift_rec_T; // @[recFNFromFN.scala:48:{15,50}]
wire [2:0] _io_out_c_shift_rec_T_3 = {_io_out_c_shift_rec_T_1[2:1], _io_out_c_shift_rec_T_1[0] | _io_out_c_shift_rec_T_2}; // @[recFNFromFN.scala:48:{15,76}, :49:20]
wire [3:0] _io_out_c_shift_rec_T_4 = {io_out_c_shift_rec_rawIn_sign_0, _io_out_c_shift_rec_T_3}; // @[recFNFromFN.scala:47:20, :48:76]
wire [5:0] _io_out_c_shift_rec_T_5 = io_out_c_shift_rec_rawIn_sExp[5:0]; // @[recFNFromFN.scala:50:23]
wire [9:0] _io_out_c_shift_rec_T_6 = {_io_out_c_shift_rec_T_4, _io_out_c_shift_rec_T_5}; // @[recFNFromFN.scala:47:20, :49:45, :50:23]
wire [22:0] _io_out_c_shift_rec_T_7 = io_out_c_shift_rec_rawIn_sig[22:0]; // @[recFNFromFN.scala:51:22]
wire [32:0] io_out_c_shift_rec = {_io_out_c_shift_rec_T_6, _io_out_c_shift_rec_T_7}; // @[recFNFromFN.scala:49:45, :50:41, :51:22]
wire _io_out_c_T = |io_out_c_shift_exp; // @[Arithmetic.scala:442:29, :447:26]
wire _io_out_c_T_2 = ~_io_out_c_T_1; // @[Arithmetic.scala:447:15]
wire _io_out_c_T_3 = ~_io_out_c_T; // @[Arithmetic.scala:447:{15,26}]
wire [31:0] _io_out_c_result_bits_T; // @[fNFromRecFN.scala:66:12]
wire [31:0] io_out_c_result_bits; // @[Arithmetic.scala:458:26]
wire [8:0] io_out_c_result_bits_rawIn_exp = _io_out_c_muladder_io_out[31:23]; // @[rawFloatFromRecFN.scala:51:21]
wire [2:0] _io_out_c_result_bits_rawIn_isZero_T = io_out_c_result_bits_rawIn_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28]
wire io_out_c_result_bits_rawIn_isZero = _io_out_c_result_bits_rawIn_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}]
wire io_out_c_result_bits_rawIn_isZero_0 = io_out_c_result_bits_rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23]
wire [1:0] _io_out_c_result_bits_rawIn_isSpecial_T = io_out_c_result_bits_rawIn_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28]
wire io_out_c_result_bits_rawIn_isSpecial = &_io_out_c_result_bits_rawIn_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}]
wire _io_out_c_result_bits_rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33]
wire _io_out_c_result_bits_rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33]
wire _io_out_c_result_bits_rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:59:25]
wire [9:0] _io_out_c_result_bits_rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27]
wire [24:0] _io_out_c_result_bits_rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44]
wire io_out_c_result_bits_rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23]
wire io_out_c_result_bits_rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire io_out_c_result_bits_rawIn_sign; // @[rawFloatFromRecFN.scala:55:23]
wire [9:0] io_out_c_result_bits_rawIn_sExp; // @[rawFloatFromRecFN.scala:55:23]
wire [24:0] io_out_c_result_bits_rawIn_sig; // @[rawFloatFromRecFN.scala:55:23]
wire _io_out_c_result_bits_rawIn_out_isNaN_T = io_out_c_result_bits_rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41]
wire _io_out_c_result_bits_rawIn_out_isInf_T = io_out_c_result_bits_rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41]
assign _io_out_c_result_bits_rawIn_out_isNaN_T_1 = io_out_c_result_bits_rawIn_isSpecial & _io_out_c_result_bits_rawIn_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}]
assign io_out_c_result_bits_rawIn_isNaN = _io_out_c_result_bits_rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33]
wire _io_out_c_result_bits_rawIn_out_isInf_T_1 = ~_io_out_c_result_bits_rawIn_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}]
assign _io_out_c_result_bits_rawIn_out_isInf_T_2 = io_out_c_result_bits_rawIn_isSpecial & _io_out_c_result_bits_rawIn_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}]
assign io_out_c_result_bits_rawIn_isInf = _io_out_c_result_bits_rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33]
assign _io_out_c_result_bits_rawIn_out_sign_T = _io_out_c_muladder_io_out[32]; // @[rawFloatFromRecFN.scala:59:25]
assign io_out_c_result_bits_rawIn_sign = _io_out_c_result_bits_rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25]
assign _io_out_c_result_bits_rawIn_out_sExp_T = {1'h0, io_out_c_result_bits_rawIn_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27]
assign io_out_c_result_bits_rawIn_sExp = _io_out_c_result_bits_rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire _io_out_c_result_bits_rawIn_out_sig_T = ~io_out_c_result_bits_rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35]
wire [1:0] _io_out_c_result_bits_rawIn_out_sig_T_1 = {1'h0, _io_out_c_result_bits_rawIn_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}]
wire [22:0] _io_out_c_result_bits_rawIn_out_sig_T_2 = _io_out_c_muladder_io_out[22:0]; // @[rawFloatFromRecFN.scala:61:49]
assign _io_out_c_result_bits_rawIn_out_sig_T_3 = {_io_out_c_result_bits_rawIn_out_sig_T_1, _io_out_c_result_bits_rawIn_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}]
assign io_out_c_result_bits_rawIn_sig = _io_out_c_result_bits_rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44]
wire io_out_c_result_bits_isSubnormal = $signed(io_out_c_result_bits_rawIn_sExp) < 10'sh82; // @[rawFloatFromRecFN.scala:55:23]
wire [4:0] _io_out_c_result_bits_denormShiftDist_T = io_out_c_result_bits_rawIn_sExp[4:0]; // @[rawFloatFromRecFN.scala:55:23]
wire [5:0] _io_out_c_result_bits_denormShiftDist_T_1 = 6'h1 - {1'h0, _io_out_c_result_bits_denormShiftDist_T}; // @[fNFromRecFN.scala:52:{35,47}]
wire [4:0] io_out_c_result_bits_denormShiftDist = _io_out_c_result_bits_denormShiftDist_T_1[4:0]; // @[fNFromRecFN.scala:52:35]
wire [23:0] _io_out_c_result_bits_denormFract_T = io_out_c_result_bits_rawIn_sig[24:1]; // @[rawFloatFromRecFN.scala:55:23]
wire [23:0] _io_out_c_result_bits_denormFract_T_1 = _io_out_c_result_bits_denormFract_T >> io_out_c_result_bits_denormShiftDist; // @[fNFromRecFN.scala:52:35, :53:{38,42}]
wire [22:0] io_out_c_result_bits_denormFract = _io_out_c_result_bits_denormFract_T_1[22:0]; // @[fNFromRecFN.scala:53:{42,60}]
wire [7:0] _io_out_c_result_bits_expOut_T = io_out_c_result_bits_rawIn_sExp[7:0]; // @[rawFloatFromRecFN.scala:55:23]
wire [8:0] _io_out_c_result_bits_expOut_T_1 = {1'h0, _io_out_c_result_bits_expOut_T} - 9'h81; // @[fNFromRecFN.scala:58:{27,45}]
wire [7:0] _io_out_c_result_bits_expOut_T_2 = _io_out_c_result_bits_expOut_T_1[7:0]; // @[fNFromRecFN.scala:58:45]
wire [7:0] _io_out_c_result_bits_expOut_T_3 = io_out_c_result_bits_isSubnormal ? 8'h0 : _io_out_c_result_bits_expOut_T_2; // @[fNFromRecFN.scala:51:38, :56:16, :58:45]
wire _io_out_c_result_bits_expOut_T_4 = io_out_c_result_bits_rawIn_isNaN | io_out_c_result_bits_rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire [7:0] _io_out_c_result_bits_expOut_T_5 = {8{_io_out_c_result_bits_expOut_T_4}}; // @[fNFromRecFN.scala:60:{21,44}]
wire [7:0] io_out_c_result_bits_expOut = _io_out_c_result_bits_expOut_T_3 | _io_out_c_result_bits_expOut_T_5; // @[fNFromRecFN.scala:56:16, :60:{15,21}]
wire [22:0] _io_out_c_result_bits_fractOut_T = io_out_c_result_bits_rawIn_sig[22:0]; // @[rawFloatFromRecFN.scala:55:23]
wire [22:0] _io_out_c_result_bits_fractOut_T_1 = io_out_c_result_bits_rawIn_isInf ? 23'h0 : _io_out_c_result_bits_fractOut_T; // @[rawFloatFromRecFN.scala:55:23]
wire [22:0] io_out_c_result_bits_fractOut = io_out_c_result_bits_isSubnormal ? io_out_c_result_bits_denormFract : _io_out_c_result_bits_fractOut_T_1; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20]
wire [8:0] io_out_c_result_bits_hi = {io_out_c_result_bits_rawIn_sign, io_out_c_result_bits_expOut}; // @[rawFloatFromRecFN.scala:55:23]
assign _io_out_c_result_bits_T = {io_out_c_result_bits_hi, io_out_c_result_bits_fractOut}; // @[fNFromRecFN.scala:62:16, :66:12]
assign io_out_c_result_bits = _io_out_c_result_bits_T; // @[fNFromRecFN.scala:66:12]
wire io_out_c_self_rec_rawIn_sign_1 = io_out_c_result_bits[31]; // @[rawFloatFromFN.scala:44:18]
wire io_out_c_self_rec_rawIn_1_sign = io_out_c_self_rec_rawIn_sign_1; // @[rawFloatFromFN.scala:44:18, :63:19]
wire [7:0] io_out_c_self_rec_rawIn_expIn_1 = io_out_c_result_bits[30:23]; // @[rawFloatFromFN.scala:45:19]
wire [22:0] io_out_c_self_rec_rawIn_fractIn_1 = io_out_c_result_bits[22:0]; // @[rawFloatFromFN.scala:46:21]
wire io_out_c_self_rec_rawIn_isZeroExpIn_1 = io_out_c_self_rec_rawIn_expIn_1 == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30]
wire io_out_c_self_rec_rawIn_isZeroFractIn_1 = io_out_c_self_rec_rawIn_fractIn_1 == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34]
wire _io_out_c_self_rec_rawIn_normDist_T_44 = io_out_c_self_rec_rawIn_fractIn_1[0]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_c_self_rec_rawIn_normDist_T_45 = io_out_c_self_rec_rawIn_fractIn_1[1]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_c_self_rec_rawIn_normDist_T_46 = io_out_c_self_rec_rawIn_fractIn_1[2]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_c_self_rec_rawIn_normDist_T_47 = io_out_c_self_rec_rawIn_fractIn_1[3]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_c_self_rec_rawIn_normDist_T_48 = io_out_c_self_rec_rawIn_fractIn_1[4]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_c_self_rec_rawIn_normDist_T_49 = io_out_c_self_rec_rawIn_fractIn_1[5]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_c_self_rec_rawIn_normDist_T_50 = io_out_c_self_rec_rawIn_fractIn_1[6]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_c_self_rec_rawIn_normDist_T_51 = io_out_c_self_rec_rawIn_fractIn_1[7]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_c_self_rec_rawIn_normDist_T_52 = io_out_c_self_rec_rawIn_fractIn_1[8]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_c_self_rec_rawIn_normDist_T_53 = io_out_c_self_rec_rawIn_fractIn_1[9]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_c_self_rec_rawIn_normDist_T_54 = io_out_c_self_rec_rawIn_fractIn_1[10]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_c_self_rec_rawIn_normDist_T_55 = io_out_c_self_rec_rawIn_fractIn_1[11]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_c_self_rec_rawIn_normDist_T_56 = io_out_c_self_rec_rawIn_fractIn_1[12]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_c_self_rec_rawIn_normDist_T_57 = io_out_c_self_rec_rawIn_fractIn_1[13]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_c_self_rec_rawIn_normDist_T_58 = io_out_c_self_rec_rawIn_fractIn_1[14]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_c_self_rec_rawIn_normDist_T_59 = io_out_c_self_rec_rawIn_fractIn_1[15]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_c_self_rec_rawIn_normDist_T_60 = io_out_c_self_rec_rawIn_fractIn_1[16]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_c_self_rec_rawIn_normDist_T_61 = io_out_c_self_rec_rawIn_fractIn_1[17]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_c_self_rec_rawIn_normDist_T_62 = io_out_c_self_rec_rawIn_fractIn_1[18]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_c_self_rec_rawIn_normDist_T_63 = io_out_c_self_rec_rawIn_fractIn_1[19]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_c_self_rec_rawIn_normDist_T_64 = io_out_c_self_rec_rawIn_fractIn_1[20]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_c_self_rec_rawIn_normDist_T_65 = io_out_c_self_rec_rawIn_fractIn_1[21]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_c_self_rec_rawIn_normDist_T_66 = io_out_c_self_rec_rawIn_fractIn_1[22]; // @[rawFloatFromFN.scala:46:21]
wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_67 = _io_out_c_self_rec_rawIn_normDist_T_45 ? 5'h15 : 5'h16; // @[Mux.scala:50:70]
wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_68 = _io_out_c_self_rec_rawIn_normDist_T_46 ? 5'h14 : _io_out_c_self_rec_rawIn_normDist_T_67; // @[Mux.scala:50:70]
wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_69 = _io_out_c_self_rec_rawIn_normDist_T_47 ? 5'h13 : _io_out_c_self_rec_rawIn_normDist_T_68; // @[Mux.scala:50:70]
wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_70 = _io_out_c_self_rec_rawIn_normDist_T_48 ? 5'h12 : _io_out_c_self_rec_rawIn_normDist_T_69; // @[Mux.scala:50:70]
wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_71 = _io_out_c_self_rec_rawIn_normDist_T_49 ? 5'h11 : _io_out_c_self_rec_rawIn_normDist_T_70; // @[Mux.scala:50:70]
wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_72 = _io_out_c_self_rec_rawIn_normDist_T_50 ? 5'h10 : _io_out_c_self_rec_rawIn_normDist_T_71; // @[Mux.scala:50:70]
wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_73 = _io_out_c_self_rec_rawIn_normDist_T_51 ? 5'hF : _io_out_c_self_rec_rawIn_normDist_T_72; // @[Mux.scala:50:70]
wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_74 = _io_out_c_self_rec_rawIn_normDist_T_52 ? 5'hE : _io_out_c_self_rec_rawIn_normDist_T_73; // @[Mux.scala:50:70]
wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_75 = _io_out_c_self_rec_rawIn_normDist_T_53 ? 5'hD : _io_out_c_self_rec_rawIn_normDist_T_74; // @[Mux.scala:50:70]
wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_76 = _io_out_c_self_rec_rawIn_normDist_T_54 ? 5'hC : _io_out_c_self_rec_rawIn_normDist_T_75; // @[Mux.scala:50:70]
wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_77 = _io_out_c_self_rec_rawIn_normDist_T_55 ? 5'hB : _io_out_c_self_rec_rawIn_normDist_T_76; // @[Mux.scala:50:70]
wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_78 = _io_out_c_self_rec_rawIn_normDist_T_56 ? 5'hA : _io_out_c_self_rec_rawIn_normDist_T_77; // @[Mux.scala:50:70]
wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_79 = _io_out_c_self_rec_rawIn_normDist_T_57 ? 5'h9 : _io_out_c_self_rec_rawIn_normDist_T_78; // @[Mux.scala:50:70]
wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_80 = _io_out_c_self_rec_rawIn_normDist_T_58 ? 5'h8 : _io_out_c_self_rec_rawIn_normDist_T_79; // @[Mux.scala:50:70]
wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_81 = _io_out_c_self_rec_rawIn_normDist_T_59 ? 5'h7 : _io_out_c_self_rec_rawIn_normDist_T_80; // @[Mux.scala:50:70]
wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_82 = _io_out_c_self_rec_rawIn_normDist_T_60 ? 5'h6 : _io_out_c_self_rec_rawIn_normDist_T_81; // @[Mux.scala:50:70]
wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_83 = _io_out_c_self_rec_rawIn_normDist_T_61 ? 5'h5 : _io_out_c_self_rec_rawIn_normDist_T_82; // @[Mux.scala:50:70]
wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_84 = _io_out_c_self_rec_rawIn_normDist_T_62 ? 5'h4 : _io_out_c_self_rec_rawIn_normDist_T_83; // @[Mux.scala:50:70]
wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_85 = _io_out_c_self_rec_rawIn_normDist_T_63 ? 5'h3 : _io_out_c_self_rec_rawIn_normDist_T_84; // @[Mux.scala:50:70]
wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_86 = _io_out_c_self_rec_rawIn_normDist_T_64 ? 5'h2 : _io_out_c_self_rec_rawIn_normDist_T_85; // @[Mux.scala:50:70]
wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_87 = _io_out_c_self_rec_rawIn_normDist_T_65 ? 5'h1 : _io_out_c_self_rec_rawIn_normDist_T_86; // @[Mux.scala:50:70]
wire [4:0] io_out_c_self_rec_rawIn_normDist_1 = _io_out_c_self_rec_rawIn_normDist_T_66 ? 5'h0 : _io_out_c_self_rec_rawIn_normDist_T_87; // @[Mux.scala:50:70]
wire [53:0] _io_out_c_self_rec_rawIn_subnormFract_T_2 = {31'h0, io_out_c_self_rec_rawIn_fractIn_1} << io_out_c_self_rec_rawIn_normDist_1; // @[Mux.scala:50:70]
wire [21:0] _io_out_c_self_rec_rawIn_subnormFract_T_3 = _io_out_c_self_rec_rawIn_subnormFract_T_2[21:0]; // @[rawFloatFromFN.scala:52:{33,46}]
wire [22:0] io_out_c_self_rec_rawIn_subnormFract_1 = {_io_out_c_self_rec_rawIn_subnormFract_T_3, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}]
wire [8:0] _io_out_c_self_rec_rawIn_adjustedExp_T_5 = {4'hF, ~io_out_c_self_rec_rawIn_normDist_1}; // @[Mux.scala:50:70]
wire [8:0] _io_out_c_self_rec_rawIn_adjustedExp_T_6 = io_out_c_self_rec_rawIn_isZeroExpIn_1 ? _io_out_c_self_rec_rawIn_adjustedExp_T_5 : {1'h0, io_out_c_self_rec_rawIn_expIn_1}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18]
wire [1:0] _io_out_c_self_rec_rawIn_adjustedExp_T_7 = io_out_c_self_rec_rawIn_isZeroExpIn_1 ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14]
wire [7:0] _io_out_c_self_rec_rawIn_adjustedExp_T_8 = {6'h20, _io_out_c_self_rec_rawIn_adjustedExp_T_7}; // @[rawFloatFromFN.scala:58:{9,14}]
wire [9:0] _io_out_c_self_rec_rawIn_adjustedExp_T_9 = {1'h0, _io_out_c_self_rec_rawIn_adjustedExp_T_6} + {2'h0, _io_out_c_self_rec_rawIn_adjustedExp_T_8}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9]
wire [8:0] io_out_c_self_rec_rawIn_adjustedExp_1 = _io_out_c_self_rec_rawIn_adjustedExp_T_9[8:0]; // @[rawFloatFromFN.scala:57:9]
wire [8:0] _io_out_c_self_rec_rawIn_out_sExp_T_2 = io_out_c_self_rec_rawIn_adjustedExp_1; // @[rawFloatFromFN.scala:57:9, :68:28]
wire io_out_c_self_rec_rawIn_isZero_1 = io_out_c_self_rec_rawIn_isZeroExpIn_1 & io_out_c_self_rec_rawIn_isZeroFractIn_1; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30]
wire io_out_c_self_rec_rawIn_1_isZero = io_out_c_self_rec_rawIn_isZero_1; // @[rawFloatFromFN.scala:60:30, :63:19]
wire [1:0] _io_out_c_self_rec_rawIn_isSpecial_T_1 = io_out_c_self_rec_rawIn_adjustedExp_1[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32]
wire io_out_c_self_rec_rawIn_isSpecial_1 = &_io_out_c_self_rec_rawIn_isSpecial_T_1; // @[rawFloatFromFN.scala:61:{32,57}]
wire _io_out_c_self_rec_rawIn_out_isNaN_T_3; // @[rawFloatFromFN.scala:64:28]
wire _io_out_c_self_rec_rawIn_out_isInf_T_1; // @[rawFloatFromFN.scala:65:28]
wire _io_out_c_self_rec_T_10 = io_out_c_self_rec_rawIn_1_isNaN; // @[recFNFromFN.scala:49:20]
wire [9:0] _io_out_c_self_rec_rawIn_out_sExp_T_3; // @[rawFloatFromFN.scala:68:42]
wire [24:0] _io_out_c_self_rec_rawIn_out_sig_T_7; // @[rawFloatFromFN.scala:70:27]
wire io_out_c_self_rec_rawIn_1_isInf; // @[rawFloatFromFN.scala:63:19]
wire [9:0] io_out_c_self_rec_rawIn_1_sExp; // @[rawFloatFromFN.scala:63:19]
wire [24:0] io_out_c_self_rec_rawIn_1_sig; // @[rawFloatFromFN.scala:63:19]
wire _io_out_c_self_rec_rawIn_out_isNaN_T_2 = ~io_out_c_self_rec_rawIn_isZeroFractIn_1; // @[rawFloatFromFN.scala:49:34, :64:31]
assign _io_out_c_self_rec_rawIn_out_isNaN_T_3 = io_out_c_self_rec_rawIn_isSpecial_1 & _io_out_c_self_rec_rawIn_out_isNaN_T_2; // @[rawFloatFromFN.scala:61:57, :64:{28,31}]
assign io_out_c_self_rec_rawIn_1_isNaN = _io_out_c_self_rec_rawIn_out_isNaN_T_3; // @[rawFloatFromFN.scala:63:19, :64:28]
assign _io_out_c_self_rec_rawIn_out_isInf_T_1 = io_out_c_self_rec_rawIn_isSpecial_1 & io_out_c_self_rec_rawIn_isZeroFractIn_1; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28]
assign io_out_c_self_rec_rawIn_1_isInf = _io_out_c_self_rec_rawIn_out_isInf_T_1; // @[rawFloatFromFN.scala:63:19, :65:28]
assign _io_out_c_self_rec_rawIn_out_sExp_T_3 = {1'h0, _io_out_c_self_rec_rawIn_out_sExp_T_2}; // @[rawFloatFromFN.scala:68:{28,42}]
assign io_out_c_self_rec_rawIn_1_sExp = _io_out_c_self_rec_rawIn_out_sExp_T_3; // @[rawFloatFromFN.scala:63:19, :68:42]
wire _io_out_c_self_rec_rawIn_out_sig_T_4 = ~io_out_c_self_rec_rawIn_isZero_1; // @[rawFloatFromFN.scala:60:30, :70:19]
wire [1:0] _io_out_c_self_rec_rawIn_out_sig_T_5 = {1'h0, _io_out_c_self_rec_rawIn_out_sig_T_4}; // @[rawFloatFromFN.scala:70:{16,19}]
wire [22:0] _io_out_c_self_rec_rawIn_out_sig_T_6 = io_out_c_self_rec_rawIn_isZeroExpIn_1 ? io_out_c_self_rec_rawIn_subnormFract_1 : io_out_c_self_rec_rawIn_fractIn_1; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33]
assign _io_out_c_self_rec_rawIn_out_sig_T_7 = {_io_out_c_self_rec_rawIn_out_sig_T_5, _io_out_c_self_rec_rawIn_out_sig_T_6}; // @[rawFloatFromFN.scala:70:{16,27,33}]
assign io_out_c_self_rec_rawIn_1_sig = _io_out_c_self_rec_rawIn_out_sig_T_7; // @[rawFloatFromFN.scala:63:19, :70:27]
wire [2:0] _io_out_c_self_rec_T_8 = io_out_c_self_rec_rawIn_1_sExp[8:6]; // @[recFNFromFN.scala:48:50]
wire [2:0] _io_out_c_self_rec_T_9 = io_out_c_self_rec_rawIn_1_isZero ? 3'h0 : _io_out_c_self_rec_T_8; // @[recFNFromFN.scala:48:{15,50}]
wire [2:0] _io_out_c_self_rec_T_11 = {_io_out_c_self_rec_T_9[2:1], _io_out_c_self_rec_T_9[0] | _io_out_c_self_rec_T_10}; // @[recFNFromFN.scala:48:{15,76}, :49:20]
wire [3:0] _io_out_c_self_rec_T_12 = {io_out_c_self_rec_rawIn_1_sign, _io_out_c_self_rec_T_11}; // @[recFNFromFN.scala:47:20, :48:76]
wire [5:0] _io_out_c_self_rec_T_13 = io_out_c_self_rec_rawIn_1_sExp[5:0]; // @[recFNFromFN.scala:50:23]
wire [9:0] _io_out_c_self_rec_T_14 = {_io_out_c_self_rec_T_12, _io_out_c_self_rec_T_13}; // @[recFNFromFN.scala:47:20, :49:45, :50:23]
wire [22:0] _io_out_c_self_rec_T_15 = io_out_c_self_rec_rawIn_1_sig[22:0]; // @[recFNFromFN.scala:51:22]
wire [32:0] io_out_c_self_rec_1 = {_io_out_c_self_rec_T_14, _io_out_c_self_rec_T_15}; // @[recFNFromFN.scala:49:45, :50:41, :51:22]
wire [31:0] _io_out_c_result_bits_T_1; // @[fNFromRecFN.scala:66:12]
wire [31:0] io_out_c_result_1_bits; // @[Arithmetic.scala:505:26]
wire [8:0] io_out_c_result_bits_rawIn_exp_1 = _io_out_c_resizer_io_out[31:23]; // @[rawFloatFromRecFN.scala:51:21]
wire [2:0] _io_out_c_result_bits_rawIn_isZero_T_1 = io_out_c_result_bits_rawIn_exp_1[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28]
wire io_out_c_result_bits_rawIn_isZero_1 = _io_out_c_result_bits_rawIn_isZero_T_1 == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}]
wire io_out_c_result_bits_rawIn_1_isZero = io_out_c_result_bits_rawIn_isZero_1; // @[rawFloatFromRecFN.scala:52:53, :55:23]
wire [1:0] _io_out_c_result_bits_rawIn_isSpecial_T_1 = io_out_c_result_bits_rawIn_exp_1[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28]
wire io_out_c_result_bits_rawIn_isSpecial_1 = &_io_out_c_result_bits_rawIn_isSpecial_T_1; // @[rawFloatFromRecFN.scala:53:{28,53}]
wire _io_out_c_result_bits_rawIn_out_isNaN_T_3; // @[rawFloatFromRecFN.scala:56:33]
wire _io_out_c_result_bits_rawIn_out_isInf_T_5; // @[rawFloatFromRecFN.scala:57:33]
wire _io_out_c_result_bits_rawIn_out_sign_T_1; // @[rawFloatFromRecFN.scala:59:25]
wire [9:0] _io_out_c_result_bits_rawIn_out_sExp_T_1; // @[rawFloatFromRecFN.scala:60:27]
wire [24:0] _io_out_c_result_bits_rawIn_out_sig_T_7; // @[rawFloatFromRecFN.scala:61:44]
wire io_out_c_result_bits_rawIn_1_isNaN; // @[rawFloatFromRecFN.scala:55:23]
wire io_out_c_result_bits_rawIn_1_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire io_out_c_result_bits_rawIn_1_sign; // @[rawFloatFromRecFN.scala:55:23]
wire [9:0] io_out_c_result_bits_rawIn_1_sExp; // @[rawFloatFromRecFN.scala:55:23]
wire [24:0] io_out_c_result_bits_rawIn_1_sig; // @[rawFloatFromRecFN.scala:55:23]
wire _io_out_c_result_bits_rawIn_out_isNaN_T_2 = io_out_c_result_bits_rawIn_exp_1[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41]
wire _io_out_c_result_bits_rawIn_out_isInf_T_3 = io_out_c_result_bits_rawIn_exp_1[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41]
assign _io_out_c_result_bits_rawIn_out_isNaN_T_3 = io_out_c_result_bits_rawIn_isSpecial_1 & _io_out_c_result_bits_rawIn_out_isNaN_T_2; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}]
assign io_out_c_result_bits_rawIn_1_isNaN = _io_out_c_result_bits_rawIn_out_isNaN_T_3; // @[rawFloatFromRecFN.scala:55:23, :56:33]
wire _io_out_c_result_bits_rawIn_out_isInf_T_4 = ~_io_out_c_result_bits_rawIn_out_isInf_T_3; // @[rawFloatFromRecFN.scala:57:{36,41}]
assign _io_out_c_result_bits_rawIn_out_isInf_T_5 = io_out_c_result_bits_rawIn_isSpecial_1 & _io_out_c_result_bits_rawIn_out_isInf_T_4; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}]
assign io_out_c_result_bits_rawIn_1_isInf = _io_out_c_result_bits_rawIn_out_isInf_T_5; // @[rawFloatFromRecFN.scala:55:23, :57:33]
assign _io_out_c_result_bits_rawIn_out_sign_T_1 = _io_out_c_resizer_io_out[32]; // @[rawFloatFromRecFN.scala:59:25]
assign io_out_c_result_bits_rawIn_1_sign = _io_out_c_result_bits_rawIn_out_sign_T_1; // @[rawFloatFromRecFN.scala:55:23, :59:25]
assign _io_out_c_result_bits_rawIn_out_sExp_T_1 = {1'h0, io_out_c_result_bits_rawIn_exp_1}; // @[rawFloatFromRecFN.scala:51:21, :60:27]
assign io_out_c_result_bits_rawIn_1_sExp = _io_out_c_result_bits_rawIn_out_sExp_T_1; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire _io_out_c_result_bits_rawIn_out_sig_T_4 = ~io_out_c_result_bits_rawIn_isZero_1; // @[rawFloatFromRecFN.scala:52:53, :61:35]
wire [1:0] _io_out_c_result_bits_rawIn_out_sig_T_5 = {1'h0, _io_out_c_result_bits_rawIn_out_sig_T_4}; // @[rawFloatFromRecFN.scala:61:{32,35}]
wire [22:0] _io_out_c_result_bits_rawIn_out_sig_T_6 = _io_out_c_resizer_io_out[22:0]; // @[rawFloatFromRecFN.scala:61:49]
assign _io_out_c_result_bits_rawIn_out_sig_T_7 = {_io_out_c_result_bits_rawIn_out_sig_T_5, _io_out_c_result_bits_rawIn_out_sig_T_6}; // @[rawFloatFromRecFN.scala:61:{32,44,49}]
assign io_out_c_result_bits_rawIn_1_sig = _io_out_c_result_bits_rawIn_out_sig_T_7; // @[rawFloatFromRecFN.scala:55:23, :61:44]
wire io_out_c_result_bits_isSubnormal_1 = $signed(io_out_c_result_bits_rawIn_1_sExp) < 10'sh82; // @[rawFloatFromRecFN.scala:55:23]
wire [4:0] _io_out_c_result_bits_denormShiftDist_T_2 = io_out_c_result_bits_rawIn_1_sExp[4:0]; // @[rawFloatFromRecFN.scala:55:23]
wire [5:0] _io_out_c_result_bits_denormShiftDist_T_3 = 6'h1 - {1'h0, _io_out_c_result_bits_denormShiftDist_T_2}; // @[fNFromRecFN.scala:52:{35,47}]
wire [4:0] io_out_c_result_bits_denormShiftDist_1 = _io_out_c_result_bits_denormShiftDist_T_3[4:0]; // @[fNFromRecFN.scala:52:35]
wire [23:0] _io_out_c_result_bits_denormFract_T_2 = io_out_c_result_bits_rawIn_1_sig[24:1]; // @[rawFloatFromRecFN.scala:55:23]
wire [23:0] _io_out_c_result_bits_denormFract_T_3 = _io_out_c_result_bits_denormFract_T_2 >> io_out_c_result_bits_denormShiftDist_1; // @[fNFromRecFN.scala:52:35, :53:{38,42}]
wire [22:0] io_out_c_result_bits_denormFract_1 = _io_out_c_result_bits_denormFract_T_3[22:0]; // @[fNFromRecFN.scala:53:{42,60}]
wire [7:0] _io_out_c_result_bits_expOut_T_6 = io_out_c_result_bits_rawIn_1_sExp[7:0]; // @[rawFloatFromRecFN.scala:55:23]
wire [8:0] _io_out_c_result_bits_expOut_T_7 = {1'h0, _io_out_c_result_bits_expOut_T_6} - 9'h81; // @[fNFromRecFN.scala:58:{27,45}]
wire [7:0] _io_out_c_result_bits_expOut_T_8 = _io_out_c_result_bits_expOut_T_7[7:0]; // @[fNFromRecFN.scala:58:45]
wire [7:0] _io_out_c_result_bits_expOut_T_9 = io_out_c_result_bits_isSubnormal_1 ? 8'h0 : _io_out_c_result_bits_expOut_T_8; // @[fNFromRecFN.scala:51:38, :56:16, :58:45]
wire _io_out_c_result_bits_expOut_T_10 = io_out_c_result_bits_rawIn_1_isNaN | io_out_c_result_bits_rawIn_1_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire [7:0] _io_out_c_result_bits_expOut_T_11 = {8{_io_out_c_result_bits_expOut_T_10}}; // @[fNFromRecFN.scala:60:{21,44}]
wire [7:0] io_out_c_result_bits_expOut_1 = _io_out_c_result_bits_expOut_T_9 | _io_out_c_result_bits_expOut_T_11; // @[fNFromRecFN.scala:56:16, :60:{15,21}]
wire [22:0] _io_out_c_result_bits_fractOut_T_2 = io_out_c_result_bits_rawIn_1_sig[22:0]; // @[rawFloatFromRecFN.scala:55:23]
wire [22:0] _io_out_c_result_bits_fractOut_T_3 = io_out_c_result_bits_rawIn_1_isInf ? 23'h0 : _io_out_c_result_bits_fractOut_T_2; // @[rawFloatFromRecFN.scala:55:23]
wire [22:0] io_out_c_result_bits_fractOut_1 = io_out_c_result_bits_isSubnormal_1 ? io_out_c_result_bits_denormFract_1 : _io_out_c_result_bits_fractOut_T_3; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20]
wire [8:0] io_out_c_result_bits_hi_1 = {io_out_c_result_bits_rawIn_1_sign, io_out_c_result_bits_expOut_1}; // @[rawFloatFromRecFN.scala:55:23]
assign _io_out_c_result_bits_T_1 = {io_out_c_result_bits_hi_1, io_out_c_result_bits_fractOut_1}; // @[fNFromRecFN.scala:62:16, :66:12]
assign io_out_c_result_1_bits = _io_out_c_result_bits_T_1; // @[fNFromRecFN.scala:66:12]
wire [31:0] _mac_unit_io_in_b_T; // @[PE.scala:106:37]
assign _mac_unit_io_in_b_T = _mac_unit_io_in_b_WIRE_1; // @[PE.scala:106:37]
wire [31:0] _mac_unit_io_in_b_WIRE_bits = _mac_unit_io_in_b_T; // @[PE.scala:106:37]
wire c1_self_rec_rawIn_sign = io_in_d_bits_0[31]; // @[rawFloatFromFN.scala:44:18]
wire c2_self_rec_rawIn_sign = io_in_d_bits_0[31]; // @[rawFloatFromFN.scala:44:18]
wire c1_self_rec_rawIn_sign_0 = c1_self_rec_rawIn_sign; // @[rawFloatFromFN.scala:44:18, :63:19]
wire [7:0] c1_self_rec_rawIn_expIn = io_in_d_bits_0[30:23]; // @[rawFloatFromFN.scala:45:19]
wire [7:0] c2_self_rec_rawIn_expIn = io_in_d_bits_0[30:23]; // @[rawFloatFromFN.scala:45:19]
wire [22:0] c1_self_rec_rawIn_fractIn = io_in_d_bits_0[22:0]; // @[rawFloatFromFN.scala:46:21]
wire [22:0] c2_self_rec_rawIn_fractIn = io_in_d_bits_0[22:0]; // @[rawFloatFromFN.scala:46:21]
wire c1_self_rec_rawIn_isZeroExpIn = c1_self_rec_rawIn_expIn == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30]
wire c1_self_rec_rawIn_isZeroFractIn = c1_self_rec_rawIn_fractIn == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34]
wire _c1_self_rec_rawIn_normDist_T = c1_self_rec_rawIn_fractIn[0]; // @[rawFloatFromFN.scala:46:21]
wire _c1_self_rec_rawIn_normDist_T_1 = c1_self_rec_rawIn_fractIn[1]; // @[rawFloatFromFN.scala:46:21]
wire _c1_self_rec_rawIn_normDist_T_2 = c1_self_rec_rawIn_fractIn[2]; // @[rawFloatFromFN.scala:46:21]
wire _c1_self_rec_rawIn_normDist_T_3 = c1_self_rec_rawIn_fractIn[3]; // @[rawFloatFromFN.scala:46:21]
wire _c1_self_rec_rawIn_normDist_T_4 = c1_self_rec_rawIn_fractIn[4]; // @[rawFloatFromFN.scala:46:21]
wire _c1_self_rec_rawIn_normDist_T_5 = c1_self_rec_rawIn_fractIn[5]; // @[rawFloatFromFN.scala:46:21]
wire _c1_self_rec_rawIn_normDist_T_6 = c1_self_rec_rawIn_fractIn[6]; // @[rawFloatFromFN.scala:46:21]
wire _c1_self_rec_rawIn_normDist_T_7 = c1_self_rec_rawIn_fractIn[7]; // @[rawFloatFromFN.scala:46:21]
wire _c1_self_rec_rawIn_normDist_T_8 = c1_self_rec_rawIn_fractIn[8]; // @[rawFloatFromFN.scala:46:21]
wire _c1_self_rec_rawIn_normDist_T_9 = c1_self_rec_rawIn_fractIn[9]; // @[rawFloatFromFN.scala:46:21]
wire _c1_self_rec_rawIn_normDist_T_10 = c1_self_rec_rawIn_fractIn[10]; // @[rawFloatFromFN.scala:46:21]
wire _c1_self_rec_rawIn_normDist_T_11 = c1_self_rec_rawIn_fractIn[11]; // @[rawFloatFromFN.scala:46:21]
wire _c1_self_rec_rawIn_normDist_T_12 = c1_self_rec_rawIn_fractIn[12]; // @[rawFloatFromFN.scala:46:21]
wire _c1_self_rec_rawIn_normDist_T_13 = c1_self_rec_rawIn_fractIn[13]; // @[rawFloatFromFN.scala:46:21]
wire _c1_self_rec_rawIn_normDist_T_14 = c1_self_rec_rawIn_fractIn[14]; // @[rawFloatFromFN.scala:46:21]
wire _c1_self_rec_rawIn_normDist_T_15 = c1_self_rec_rawIn_fractIn[15]; // @[rawFloatFromFN.scala:46:21]
wire _c1_self_rec_rawIn_normDist_T_16 = c1_self_rec_rawIn_fractIn[16]; // @[rawFloatFromFN.scala:46:21]
wire _c1_self_rec_rawIn_normDist_T_17 = c1_self_rec_rawIn_fractIn[17]; // @[rawFloatFromFN.scala:46:21]
wire _c1_self_rec_rawIn_normDist_T_18 = c1_self_rec_rawIn_fractIn[18]; // @[rawFloatFromFN.scala:46:21]
wire _c1_self_rec_rawIn_normDist_T_19 = c1_self_rec_rawIn_fractIn[19]; // @[rawFloatFromFN.scala:46:21]
wire _c1_self_rec_rawIn_normDist_T_20 = c1_self_rec_rawIn_fractIn[20]; // @[rawFloatFromFN.scala:46:21]
wire _c1_self_rec_rawIn_normDist_T_21 = c1_self_rec_rawIn_fractIn[21]; // @[rawFloatFromFN.scala:46:21]
wire _c1_self_rec_rawIn_normDist_T_22 = c1_self_rec_rawIn_fractIn[22]; // @[rawFloatFromFN.scala:46:21]
wire [4:0] _c1_self_rec_rawIn_normDist_T_23 = _c1_self_rec_rawIn_normDist_T_1 ? 5'h15 : 5'h16; // @[Mux.scala:50:70]
wire [4:0] _c1_self_rec_rawIn_normDist_T_24 = _c1_self_rec_rawIn_normDist_T_2 ? 5'h14 : _c1_self_rec_rawIn_normDist_T_23; // @[Mux.scala:50:70]
wire [4:0] _c1_self_rec_rawIn_normDist_T_25 = _c1_self_rec_rawIn_normDist_T_3 ? 5'h13 : _c1_self_rec_rawIn_normDist_T_24; // @[Mux.scala:50:70]
wire [4:0] _c1_self_rec_rawIn_normDist_T_26 = _c1_self_rec_rawIn_normDist_T_4 ? 5'h12 : _c1_self_rec_rawIn_normDist_T_25; // @[Mux.scala:50:70]
wire [4:0] _c1_self_rec_rawIn_normDist_T_27 = _c1_self_rec_rawIn_normDist_T_5 ? 5'h11 : _c1_self_rec_rawIn_normDist_T_26; // @[Mux.scala:50:70]
wire [4:0] _c1_self_rec_rawIn_normDist_T_28 = _c1_self_rec_rawIn_normDist_T_6 ? 5'h10 : _c1_self_rec_rawIn_normDist_T_27; // @[Mux.scala:50:70]
wire [4:0] _c1_self_rec_rawIn_normDist_T_29 = _c1_self_rec_rawIn_normDist_T_7 ? 5'hF : _c1_self_rec_rawIn_normDist_T_28; // @[Mux.scala:50:70]
wire [4:0] _c1_self_rec_rawIn_normDist_T_30 = _c1_self_rec_rawIn_normDist_T_8 ? 5'hE : _c1_self_rec_rawIn_normDist_T_29; // @[Mux.scala:50:70]
wire [4:0] _c1_self_rec_rawIn_normDist_T_31 = _c1_self_rec_rawIn_normDist_T_9 ? 5'hD : _c1_self_rec_rawIn_normDist_T_30; // @[Mux.scala:50:70]
wire [4:0] _c1_self_rec_rawIn_normDist_T_32 = _c1_self_rec_rawIn_normDist_T_10 ? 5'hC : _c1_self_rec_rawIn_normDist_T_31; // @[Mux.scala:50:70]
wire [4:0] _c1_self_rec_rawIn_normDist_T_33 = _c1_self_rec_rawIn_normDist_T_11 ? 5'hB : _c1_self_rec_rawIn_normDist_T_32; // @[Mux.scala:50:70]
wire [4:0] _c1_self_rec_rawIn_normDist_T_34 = _c1_self_rec_rawIn_normDist_T_12 ? 5'hA : _c1_self_rec_rawIn_normDist_T_33; // @[Mux.scala:50:70]
wire [4:0] _c1_self_rec_rawIn_normDist_T_35 = _c1_self_rec_rawIn_normDist_T_13 ? 5'h9 : _c1_self_rec_rawIn_normDist_T_34; // @[Mux.scala:50:70]
wire [4:0] _c1_self_rec_rawIn_normDist_T_36 = _c1_self_rec_rawIn_normDist_T_14 ? 5'h8 : _c1_self_rec_rawIn_normDist_T_35; // @[Mux.scala:50:70]
wire [4:0] _c1_self_rec_rawIn_normDist_T_37 = _c1_self_rec_rawIn_normDist_T_15 ? 5'h7 : _c1_self_rec_rawIn_normDist_T_36; // @[Mux.scala:50:70]
wire [4:0] _c1_self_rec_rawIn_normDist_T_38 = _c1_self_rec_rawIn_normDist_T_16 ? 5'h6 : _c1_self_rec_rawIn_normDist_T_37; // @[Mux.scala:50:70]
wire [4:0] _c1_self_rec_rawIn_normDist_T_39 = _c1_self_rec_rawIn_normDist_T_17 ? 5'h5 : _c1_self_rec_rawIn_normDist_T_38; // @[Mux.scala:50:70]
wire [4:0] _c1_self_rec_rawIn_normDist_T_40 = _c1_self_rec_rawIn_normDist_T_18 ? 5'h4 : _c1_self_rec_rawIn_normDist_T_39; // @[Mux.scala:50:70]
wire [4:0] _c1_self_rec_rawIn_normDist_T_41 = _c1_self_rec_rawIn_normDist_T_19 ? 5'h3 : _c1_self_rec_rawIn_normDist_T_40; // @[Mux.scala:50:70]
wire [4:0] _c1_self_rec_rawIn_normDist_T_42 = _c1_self_rec_rawIn_normDist_T_20 ? 5'h2 : _c1_self_rec_rawIn_normDist_T_41; // @[Mux.scala:50:70]
wire [4:0] _c1_self_rec_rawIn_normDist_T_43 = _c1_self_rec_rawIn_normDist_T_21 ? 5'h1 : _c1_self_rec_rawIn_normDist_T_42; // @[Mux.scala:50:70]
wire [4:0] c1_self_rec_rawIn_normDist = _c1_self_rec_rawIn_normDist_T_22 ? 5'h0 : _c1_self_rec_rawIn_normDist_T_43; // @[Mux.scala:50:70]
wire [53:0] _c1_self_rec_rawIn_subnormFract_T = {31'h0, c1_self_rec_rawIn_fractIn} << c1_self_rec_rawIn_normDist; // @[Mux.scala:50:70]
wire [21:0] _c1_self_rec_rawIn_subnormFract_T_1 = _c1_self_rec_rawIn_subnormFract_T[21:0]; // @[rawFloatFromFN.scala:52:{33,46}]
wire [22:0] c1_self_rec_rawIn_subnormFract = {_c1_self_rec_rawIn_subnormFract_T_1, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}]
wire [8:0] _c1_self_rec_rawIn_adjustedExp_T = {4'hF, ~c1_self_rec_rawIn_normDist}; // @[Mux.scala:50:70]
wire [8:0] _c1_self_rec_rawIn_adjustedExp_T_1 = c1_self_rec_rawIn_isZeroExpIn ? _c1_self_rec_rawIn_adjustedExp_T : {1'h0, c1_self_rec_rawIn_expIn}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18]
wire [1:0] _c1_self_rec_rawIn_adjustedExp_T_2 = c1_self_rec_rawIn_isZeroExpIn ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14]
wire [7:0] _c1_self_rec_rawIn_adjustedExp_T_3 = {6'h20, _c1_self_rec_rawIn_adjustedExp_T_2}; // @[rawFloatFromFN.scala:58:{9,14}]
wire [9:0] _c1_self_rec_rawIn_adjustedExp_T_4 = {1'h0, _c1_self_rec_rawIn_adjustedExp_T_1} + {2'h0, _c1_self_rec_rawIn_adjustedExp_T_3}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9]
wire [8:0] c1_self_rec_rawIn_adjustedExp = _c1_self_rec_rawIn_adjustedExp_T_4[8:0]; // @[rawFloatFromFN.scala:57:9]
wire [8:0] _c1_self_rec_rawIn_out_sExp_T = c1_self_rec_rawIn_adjustedExp; // @[rawFloatFromFN.scala:57:9, :68:28]
wire c1_self_rec_rawIn_isZero = c1_self_rec_rawIn_isZeroExpIn & c1_self_rec_rawIn_isZeroFractIn; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30]
wire c1_self_rec_rawIn_isZero_0 = c1_self_rec_rawIn_isZero; // @[rawFloatFromFN.scala:60:30, :63:19]
wire [1:0] _c1_self_rec_rawIn_isSpecial_T = c1_self_rec_rawIn_adjustedExp[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32]
wire c1_self_rec_rawIn_isSpecial = &_c1_self_rec_rawIn_isSpecial_T; // @[rawFloatFromFN.scala:61:{32,57}]
wire _c1_self_rec_rawIn_out_isNaN_T_1; // @[rawFloatFromFN.scala:64:28]
wire _c1_self_rec_rawIn_out_isInf_T; // @[rawFloatFromFN.scala:65:28]
wire _c1_self_rec_T_2 = c1_self_rec_rawIn_isNaN; // @[recFNFromFN.scala:49:20]
wire [9:0] _c1_self_rec_rawIn_out_sExp_T_1; // @[rawFloatFromFN.scala:68:42]
wire [24:0] _c1_self_rec_rawIn_out_sig_T_3; // @[rawFloatFromFN.scala:70:27]
wire c1_self_rec_rawIn_isInf; // @[rawFloatFromFN.scala:63:19]
wire [9:0] c1_self_rec_rawIn_sExp; // @[rawFloatFromFN.scala:63:19]
wire [24:0] c1_self_rec_rawIn_sig; // @[rawFloatFromFN.scala:63:19]
wire _c1_self_rec_rawIn_out_isNaN_T = ~c1_self_rec_rawIn_isZeroFractIn; // @[rawFloatFromFN.scala:49:34, :64:31]
assign _c1_self_rec_rawIn_out_isNaN_T_1 = c1_self_rec_rawIn_isSpecial & _c1_self_rec_rawIn_out_isNaN_T; // @[rawFloatFromFN.scala:61:57, :64:{28,31}]
assign c1_self_rec_rawIn_isNaN = _c1_self_rec_rawIn_out_isNaN_T_1; // @[rawFloatFromFN.scala:63:19, :64:28]
assign _c1_self_rec_rawIn_out_isInf_T = c1_self_rec_rawIn_isSpecial & c1_self_rec_rawIn_isZeroFractIn; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28]
assign c1_self_rec_rawIn_isInf = _c1_self_rec_rawIn_out_isInf_T; // @[rawFloatFromFN.scala:63:19, :65:28]
assign _c1_self_rec_rawIn_out_sExp_T_1 = {1'h0, _c1_self_rec_rawIn_out_sExp_T}; // @[rawFloatFromFN.scala:68:{28,42}]
assign c1_self_rec_rawIn_sExp = _c1_self_rec_rawIn_out_sExp_T_1; // @[rawFloatFromFN.scala:63:19, :68:42]
wire _c1_self_rec_rawIn_out_sig_T = ~c1_self_rec_rawIn_isZero; // @[rawFloatFromFN.scala:60:30, :70:19]
wire [1:0] _c1_self_rec_rawIn_out_sig_T_1 = {1'h0, _c1_self_rec_rawIn_out_sig_T}; // @[rawFloatFromFN.scala:70:{16,19}]
wire [22:0] _c1_self_rec_rawIn_out_sig_T_2 = c1_self_rec_rawIn_isZeroExpIn ? c1_self_rec_rawIn_subnormFract : c1_self_rec_rawIn_fractIn; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33]
assign _c1_self_rec_rawIn_out_sig_T_3 = {_c1_self_rec_rawIn_out_sig_T_1, _c1_self_rec_rawIn_out_sig_T_2}; // @[rawFloatFromFN.scala:70:{16,27,33}]
assign c1_self_rec_rawIn_sig = _c1_self_rec_rawIn_out_sig_T_3; // @[rawFloatFromFN.scala:63:19, :70:27]
wire [2:0] _c1_self_rec_T = c1_self_rec_rawIn_sExp[8:6]; // @[recFNFromFN.scala:48:50]
wire [2:0] _c1_self_rec_T_1 = c1_self_rec_rawIn_isZero_0 ? 3'h0 : _c1_self_rec_T; // @[recFNFromFN.scala:48:{15,50}]
wire [2:0] _c1_self_rec_T_3 = {_c1_self_rec_T_1[2:1], _c1_self_rec_T_1[0] | _c1_self_rec_T_2}; // @[recFNFromFN.scala:48:{15,76}, :49:20]
wire [3:0] _c1_self_rec_T_4 = {c1_self_rec_rawIn_sign_0, _c1_self_rec_T_3}; // @[recFNFromFN.scala:47:20, :48:76]
wire [5:0] _c1_self_rec_T_5 = c1_self_rec_rawIn_sExp[5:0]; // @[recFNFromFN.scala:50:23]
wire [9:0] _c1_self_rec_T_6 = {_c1_self_rec_T_4, _c1_self_rec_T_5}; // @[recFNFromFN.scala:47:20, :49:45, :50:23]
wire [22:0] _c1_self_rec_T_7 = c1_self_rec_rawIn_sig[22:0]; // @[recFNFromFN.scala:51:22]
wire [32:0] c1_self_rec = {_c1_self_rec_T_6, _c1_self_rec_T_7}; // @[recFNFromFN.scala:49:45, :50:41, :51:22]
wire [31:0] _c1_result_bits_T; // @[fNFromRecFN.scala:66:12]
wire [31:0] c1_result_bits; // @[Arithmetic.scala:491:26]
wire [8:0] c1_result_bits_rawIn_exp = _c1_resizer_io_out[31:23]; // @[rawFloatFromRecFN.scala:51:21]
wire [2:0] _c1_result_bits_rawIn_isZero_T = c1_result_bits_rawIn_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28]
wire c1_result_bits_rawIn_isZero = _c1_result_bits_rawIn_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}]
wire c1_result_bits_rawIn_isZero_0 = c1_result_bits_rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23]
wire [1:0] _c1_result_bits_rawIn_isSpecial_T = c1_result_bits_rawIn_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28]
wire c1_result_bits_rawIn_isSpecial = &_c1_result_bits_rawIn_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}]
wire _c1_result_bits_rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33]
wire _c1_result_bits_rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33]
wire _c1_result_bits_rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:59:25]
wire [9:0] _c1_result_bits_rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27]
wire [24:0] _c1_result_bits_rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44]
wire c1_result_bits_rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23]
wire c1_result_bits_rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire c1_result_bits_rawIn_sign; // @[rawFloatFromRecFN.scala:55:23]
wire [9:0] c1_result_bits_rawIn_sExp; // @[rawFloatFromRecFN.scala:55:23]
wire [24:0] c1_result_bits_rawIn_sig; // @[rawFloatFromRecFN.scala:55:23]
wire _c1_result_bits_rawIn_out_isNaN_T = c1_result_bits_rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41]
wire _c1_result_bits_rawIn_out_isInf_T = c1_result_bits_rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41]
assign _c1_result_bits_rawIn_out_isNaN_T_1 = c1_result_bits_rawIn_isSpecial & _c1_result_bits_rawIn_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}]
assign c1_result_bits_rawIn_isNaN = _c1_result_bits_rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33]
wire _c1_result_bits_rawIn_out_isInf_T_1 = ~_c1_result_bits_rawIn_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}]
assign _c1_result_bits_rawIn_out_isInf_T_2 = c1_result_bits_rawIn_isSpecial & _c1_result_bits_rawIn_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}]
assign c1_result_bits_rawIn_isInf = _c1_result_bits_rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33]
assign _c1_result_bits_rawIn_out_sign_T = _c1_resizer_io_out[32]; // @[rawFloatFromRecFN.scala:59:25]
assign c1_result_bits_rawIn_sign = _c1_result_bits_rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25]
assign _c1_result_bits_rawIn_out_sExp_T = {1'h0, c1_result_bits_rawIn_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27]
assign c1_result_bits_rawIn_sExp = _c1_result_bits_rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire _c1_result_bits_rawIn_out_sig_T = ~c1_result_bits_rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35]
wire [1:0] _c1_result_bits_rawIn_out_sig_T_1 = {1'h0, _c1_result_bits_rawIn_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}]
wire [22:0] _c1_result_bits_rawIn_out_sig_T_2 = _c1_resizer_io_out[22:0]; // @[rawFloatFromRecFN.scala:61:49]
assign _c1_result_bits_rawIn_out_sig_T_3 = {_c1_result_bits_rawIn_out_sig_T_1, _c1_result_bits_rawIn_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}]
assign c1_result_bits_rawIn_sig = _c1_result_bits_rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44]
wire c1_result_bits_isSubnormal = $signed(c1_result_bits_rawIn_sExp) < 10'sh82; // @[rawFloatFromRecFN.scala:55:23]
wire [4:0] _c1_result_bits_denormShiftDist_T = c1_result_bits_rawIn_sExp[4:0]; // @[rawFloatFromRecFN.scala:55:23]
wire [5:0] _c1_result_bits_denormShiftDist_T_1 = 6'h1 - {1'h0, _c1_result_bits_denormShiftDist_T}; // @[fNFromRecFN.scala:52:{35,47}]
wire [4:0] c1_result_bits_denormShiftDist = _c1_result_bits_denormShiftDist_T_1[4:0]; // @[fNFromRecFN.scala:52:35]
wire [23:0] _c1_result_bits_denormFract_T = c1_result_bits_rawIn_sig[24:1]; // @[rawFloatFromRecFN.scala:55:23]
wire [23:0] _c1_result_bits_denormFract_T_1 = _c1_result_bits_denormFract_T >> c1_result_bits_denormShiftDist; // @[fNFromRecFN.scala:52:35, :53:{38,42}]
wire [22:0] c1_result_bits_denormFract = _c1_result_bits_denormFract_T_1[22:0]; // @[fNFromRecFN.scala:53:{42,60}]
wire [7:0] _c1_result_bits_expOut_T = c1_result_bits_rawIn_sExp[7:0]; // @[rawFloatFromRecFN.scala:55:23]
wire [8:0] _c1_result_bits_expOut_T_1 = {1'h0, _c1_result_bits_expOut_T} - 9'h81; // @[fNFromRecFN.scala:58:{27,45}]
wire [7:0] _c1_result_bits_expOut_T_2 = _c1_result_bits_expOut_T_1[7:0]; // @[fNFromRecFN.scala:58:45]
wire [7:0] _c1_result_bits_expOut_T_3 = c1_result_bits_isSubnormal ? 8'h0 : _c1_result_bits_expOut_T_2; // @[fNFromRecFN.scala:51:38, :56:16, :58:45]
wire _c1_result_bits_expOut_T_4 = c1_result_bits_rawIn_isNaN | c1_result_bits_rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire [7:0] _c1_result_bits_expOut_T_5 = {8{_c1_result_bits_expOut_T_4}}; // @[fNFromRecFN.scala:60:{21,44}]
wire [7:0] c1_result_bits_expOut = _c1_result_bits_expOut_T_3 | _c1_result_bits_expOut_T_5; // @[fNFromRecFN.scala:56:16, :60:{15,21}]
wire [22:0] _c1_result_bits_fractOut_T = c1_result_bits_rawIn_sig[22:0]; // @[rawFloatFromRecFN.scala:55:23]
wire [22:0] _c1_result_bits_fractOut_T_1 = c1_result_bits_rawIn_isInf ? 23'h0 : _c1_result_bits_fractOut_T; // @[rawFloatFromRecFN.scala:55:23]
wire [22:0] c1_result_bits_fractOut = c1_result_bits_isSubnormal ? c1_result_bits_denormFract : _c1_result_bits_fractOut_T_1; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20]
wire [8:0] c1_result_bits_hi = {c1_result_bits_rawIn_sign, c1_result_bits_expOut}; // @[rawFloatFromRecFN.scala:55:23]
assign _c1_result_bits_T = {c1_result_bits_hi, c1_result_bits_fractOut}; // @[fNFromRecFN.scala:62:16, :66:12]
assign c1_result_bits = _c1_result_bits_T; // @[fNFromRecFN.scala:66:12]
wire io_out_c_self_rec_rawIn_sign_2 = c2_bits[31]; // @[rawFloatFromFN.scala:44:18]
wire io_out_c_self_rec_rawIn_2_sign = io_out_c_self_rec_rawIn_sign_2; // @[rawFloatFromFN.scala:44:18, :63:19]
wire [7:0] io_out_c_self_rec_rawIn_expIn_2 = c2_bits[30:23]; // @[rawFloatFromFN.scala:45:19]
wire [22:0] io_out_c_self_rec_rawIn_fractIn_2 = c2_bits[22:0]; // @[rawFloatFromFN.scala:46:21]
wire io_out_c_self_rec_rawIn_isZeroExpIn_2 = io_out_c_self_rec_rawIn_expIn_2 == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30]
wire io_out_c_self_rec_rawIn_isZeroFractIn_2 = io_out_c_self_rec_rawIn_fractIn_2 == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34]
wire _io_out_c_self_rec_rawIn_normDist_T_88 = io_out_c_self_rec_rawIn_fractIn_2[0]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_c_self_rec_rawIn_normDist_T_89 = io_out_c_self_rec_rawIn_fractIn_2[1]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_c_self_rec_rawIn_normDist_T_90 = io_out_c_self_rec_rawIn_fractIn_2[2]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_c_self_rec_rawIn_normDist_T_91 = io_out_c_self_rec_rawIn_fractIn_2[3]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_c_self_rec_rawIn_normDist_T_92 = io_out_c_self_rec_rawIn_fractIn_2[4]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_c_self_rec_rawIn_normDist_T_93 = io_out_c_self_rec_rawIn_fractIn_2[5]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_c_self_rec_rawIn_normDist_T_94 = io_out_c_self_rec_rawIn_fractIn_2[6]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_c_self_rec_rawIn_normDist_T_95 = io_out_c_self_rec_rawIn_fractIn_2[7]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_c_self_rec_rawIn_normDist_T_96 = io_out_c_self_rec_rawIn_fractIn_2[8]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_c_self_rec_rawIn_normDist_T_97 = io_out_c_self_rec_rawIn_fractIn_2[9]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_c_self_rec_rawIn_normDist_T_98 = io_out_c_self_rec_rawIn_fractIn_2[10]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_c_self_rec_rawIn_normDist_T_99 = io_out_c_self_rec_rawIn_fractIn_2[11]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_c_self_rec_rawIn_normDist_T_100 = io_out_c_self_rec_rawIn_fractIn_2[12]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_c_self_rec_rawIn_normDist_T_101 = io_out_c_self_rec_rawIn_fractIn_2[13]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_c_self_rec_rawIn_normDist_T_102 = io_out_c_self_rec_rawIn_fractIn_2[14]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_c_self_rec_rawIn_normDist_T_103 = io_out_c_self_rec_rawIn_fractIn_2[15]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_c_self_rec_rawIn_normDist_T_104 = io_out_c_self_rec_rawIn_fractIn_2[16]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_c_self_rec_rawIn_normDist_T_105 = io_out_c_self_rec_rawIn_fractIn_2[17]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_c_self_rec_rawIn_normDist_T_106 = io_out_c_self_rec_rawIn_fractIn_2[18]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_c_self_rec_rawIn_normDist_T_107 = io_out_c_self_rec_rawIn_fractIn_2[19]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_c_self_rec_rawIn_normDist_T_108 = io_out_c_self_rec_rawIn_fractIn_2[20]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_c_self_rec_rawIn_normDist_T_109 = io_out_c_self_rec_rawIn_fractIn_2[21]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_c_self_rec_rawIn_normDist_T_110 = io_out_c_self_rec_rawIn_fractIn_2[22]; // @[rawFloatFromFN.scala:46:21]
wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_111 = _io_out_c_self_rec_rawIn_normDist_T_89 ? 5'h15 : 5'h16; // @[Mux.scala:50:70]
wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_112 = _io_out_c_self_rec_rawIn_normDist_T_90 ? 5'h14 : _io_out_c_self_rec_rawIn_normDist_T_111; // @[Mux.scala:50:70]
wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_113 = _io_out_c_self_rec_rawIn_normDist_T_91 ? 5'h13 : _io_out_c_self_rec_rawIn_normDist_T_112; // @[Mux.scala:50:70]
wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_114 = _io_out_c_self_rec_rawIn_normDist_T_92 ? 5'h12 : _io_out_c_self_rec_rawIn_normDist_T_113; // @[Mux.scala:50:70]
wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_115 = _io_out_c_self_rec_rawIn_normDist_T_93 ? 5'h11 : _io_out_c_self_rec_rawIn_normDist_T_114; // @[Mux.scala:50:70]
wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_116 = _io_out_c_self_rec_rawIn_normDist_T_94 ? 5'h10 : _io_out_c_self_rec_rawIn_normDist_T_115; // @[Mux.scala:50:70]
wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_117 = _io_out_c_self_rec_rawIn_normDist_T_95 ? 5'hF : _io_out_c_self_rec_rawIn_normDist_T_116; // @[Mux.scala:50:70]
wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_118 = _io_out_c_self_rec_rawIn_normDist_T_96 ? 5'hE : _io_out_c_self_rec_rawIn_normDist_T_117; // @[Mux.scala:50:70]
wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_119 = _io_out_c_self_rec_rawIn_normDist_T_97 ? 5'hD : _io_out_c_self_rec_rawIn_normDist_T_118; // @[Mux.scala:50:70]
wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_120 = _io_out_c_self_rec_rawIn_normDist_T_98 ? 5'hC : _io_out_c_self_rec_rawIn_normDist_T_119; // @[Mux.scala:50:70]
wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_121 = _io_out_c_self_rec_rawIn_normDist_T_99 ? 5'hB : _io_out_c_self_rec_rawIn_normDist_T_120; // @[Mux.scala:50:70]
wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_122 = _io_out_c_self_rec_rawIn_normDist_T_100 ? 5'hA : _io_out_c_self_rec_rawIn_normDist_T_121; // @[Mux.scala:50:70]
wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_123 = _io_out_c_self_rec_rawIn_normDist_T_101 ? 5'h9 : _io_out_c_self_rec_rawIn_normDist_T_122; // @[Mux.scala:50:70]
wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_124 = _io_out_c_self_rec_rawIn_normDist_T_102 ? 5'h8 : _io_out_c_self_rec_rawIn_normDist_T_123; // @[Mux.scala:50:70]
wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_125 = _io_out_c_self_rec_rawIn_normDist_T_103 ? 5'h7 : _io_out_c_self_rec_rawIn_normDist_T_124; // @[Mux.scala:50:70]
wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_126 = _io_out_c_self_rec_rawIn_normDist_T_104 ? 5'h6 : _io_out_c_self_rec_rawIn_normDist_T_125; // @[Mux.scala:50:70]
wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_127 = _io_out_c_self_rec_rawIn_normDist_T_105 ? 5'h5 : _io_out_c_self_rec_rawIn_normDist_T_126; // @[Mux.scala:50:70]
wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_128 = _io_out_c_self_rec_rawIn_normDist_T_106 ? 5'h4 : _io_out_c_self_rec_rawIn_normDist_T_127; // @[Mux.scala:50:70]
wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_129 = _io_out_c_self_rec_rawIn_normDist_T_107 ? 5'h3 : _io_out_c_self_rec_rawIn_normDist_T_128; // @[Mux.scala:50:70]
wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_130 = _io_out_c_self_rec_rawIn_normDist_T_108 ? 5'h2 : _io_out_c_self_rec_rawIn_normDist_T_129; // @[Mux.scala:50:70]
wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_131 = _io_out_c_self_rec_rawIn_normDist_T_109 ? 5'h1 : _io_out_c_self_rec_rawIn_normDist_T_130; // @[Mux.scala:50:70]
wire [4:0] io_out_c_self_rec_rawIn_normDist_2 = _io_out_c_self_rec_rawIn_normDist_T_110 ? 5'h0 : _io_out_c_self_rec_rawIn_normDist_T_131; // @[Mux.scala:50:70]
wire [53:0] _io_out_c_self_rec_rawIn_subnormFract_T_4 = {31'h0, io_out_c_self_rec_rawIn_fractIn_2} << io_out_c_self_rec_rawIn_normDist_2; // @[Mux.scala:50:70]
wire [21:0] _io_out_c_self_rec_rawIn_subnormFract_T_5 = _io_out_c_self_rec_rawIn_subnormFract_T_4[21:0]; // @[rawFloatFromFN.scala:52:{33,46}]
wire [22:0] io_out_c_self_rec_rawIn_subnormFract_2 = {_io_out_c_self_rec_rawIn_subnormFract_T_5, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}]
wire [8:0] _io_out_c_self_rec_rawIn_adjustedExp_T_10 = {4'hF, ~io_out_c_self_rec_rawIn_normDist_2}; // @[Mux.scala:50:70]
wire [8:0] _io_out_c_self_rec_rawIn_adjustedExp_T_11 = io_out_c_self_rec_rawIn_isZeroExpIn_2 ? _io_out_c_self_rec_rawIn_adjustedExp_T_10 : {1'h0, io_out_c_self_rec_rawIn_expIn_2}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18]
wire [1:0] _io_out_c_self_rec_rawIn_adjustedExp_T_12 = io_out_c_self_rec_rawIn_isZeroExpIn_2 ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14]
wire [7:0] _io_out_c_self_rec_rawIn_adjustedExp_T_13 = {6'h20, _io_out_c_self_rec_rawIn_adjustedExp_T_12}; // @[rawFloatFromFN.scala:58:{9,14}]
wire [9:0] _io_out_c_self_rec_rawIn_adjustedExp_T_14 = {1'h0, _io_out_c_self_rec_rawIn_adjustedExp_T_11} + {2'h0, _io_out_c_self_rec_rawIn_adjustedExp_T_13}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9]
wire [8:0] io_out_c_self_rec_rawIn_adjustedExp_2 = _io_out_c_self_rec_rawIn_adjustedExp_T_14[8:0]; // @[rawFloatFromFN.scala:57:9]
wire [8:0] _io_out_c_self_rec_rawIn_out_sExp_T_4 = io_out_c_self_rec_rawIn_adjustedExp_2; // @[rawFloatFromFN.scala:57:9, :68:28]
wire io_out_c_self_rec_rawIn_isZero_2 = io_out_c_self_rec_rawIn_isZeroExpIn_2 & io_out_c_self_rec_rawIn_isZeroFractIn_2; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30]
wire io_out_c_self_rec_rawIn_2_isZero = io_out_c_self_rec_rawIn_isZero_2; // @[rawFloatFromFN.scala:60:30, :63:19]
wire [1:0] _io_out_c_self_rec_rawIn_isSpecial_T_2 = io_out_c_self_rec_rawIn_adjustedExp_2[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32]
wire io_out_c_self_rec_rawIn_isSpecial_2 = &_io_out_c_self_rec_rawIn_isSpecial_T_2; // @[rawFloatFromFN.scala:61:{32,57}]
wire _io_out_c_self_rec_rawIn_out_isNaN_T_5; // @[rawFloatFromFN.scala:64:28]
wire _io_out_c_self_rec_rawIn_out_isInf_T_2; // @[rawFloatFromFN.scala:65:28]
wire _io_out_c_self_rec_T_18 = io_out_c_self_rec_rawIn_2_isNaN; // @[recFNFromFN.scala:49:20]
wire [9:0] _io_out_c_self_rec_rawIn_out_sExp_T_5; // @[rawFloatFromFN.scala:68:42]
wire [24:0] _io_out_c_self_rec_rawIn_out_sig_T_11; // @[rawFloatFromFN.scala:70:27]
wire io_out_c_self_rec_rawIn_2_isInf; // @[rawFloatFromFN.scala:63:19]
wire [9:0] io_out_c_self_rec_rawIn_2_sExp; // @[rawFloatFromFN.scala:63:19]
wire [24:0] io_out_c_self_rec_rawIn_2_sig; // @[rawFloatFromFN.scala:63:19]
wire _io_out_c_self_rec_rawIn_out_isNaN_T_4 = ~io_out_c_self_rec_rawIn_isZeroFractIn_2; // @[rawFloatFromFN.scala:49:34, :64:31]
assign _io_out_c_self_rec_rawIn_out_isNaN_T_5 = io_out_c_self_rec_rawIn_isSpecial_2 & _io_out_c_self_rec_rawIn_out_isNaN_T_4; // @[rawFloatFromFN.scala:61:57, :64:{28,31}]
assign io_out_c_self_rec_rawIn_2_isNaN = _io_out_c_self_rec_rawIn_out_isNaN_T_5; // @[rawFloatFromFN.scala:63:19, :64:28]
assign _io_out_c_self_rec_rawIn_out_isInf_T_2 = io_out_c_self_rec_rawIn_isSpecial_2 & io_out_c_self_rec_rawIn_isZeroFractIn_2; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28]
assign io_out_c_self_rec_rawIn_2_isInf = _io_out_c_self_rec_rawIn_out_isInf_T_2; // @[rawFloatFromFN.scala:63:19, :65:28]
assign _io_out_c_self_rec_rawIn_out_sExp_T_5 = {1'h0, _io_out_c_self_rec_rawIn_out_sExp_T_4}; // @[rawFloatFromFN.scala:68:{28,42}]
assign io_out_c_self_rec_rawIn_2_sExp = _io_out_c_self_rec_rawIn_out_sExp_T_5; // @[rawFloatFromFN.scala:63:19, :68:42]
wire _io_out_c_self_rec_rawIn_out_sig_T_8 = ~io_out_c_self_rec_rawIn_isZero_2; // @[rawFloatFromFN.scala:60:30, :70:19]
wire [1:0] _io_out_c_self_rec_rawIn_out_sig_T_9 = {1'h0, _io_out_c_self_rec_rawIn_out_sig_T_8}; // @[rawFloatFromFN.scala:70:{16,19}]
wire [22:0] _io_out_c_self_rec_rawIn_out_sig_T_10 = io_out_c_self_rec_rawIn_isZeroExpIn_2 ? io_out_c_self_rec_rawIn_subnormFract_2 : io_out_c_self_rec_rawIn_fractIn_2; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33]
assign _io_out_c_self_rec_rawIn_out_sig_T_11 = {_io_out_c_self_rec_rawIn_out_sig_T_9, _io_out_c_self_rec_rawIn_out_sig_T_10}; // @[rawFloatFromFN.scala:70:{16,27,33}]
assign io_out_c_self_rec_rawIn_2_sig = _io_out_c_self_rec_rawIn_out_sig_T_11; // @[rawFloatFromFN.scala:63:19, :70:27]
wire [2:0] _io_out_c_self_rec_T_16 = io_out_c_self_rec_rawIn_2_sExp[8:6]; // @[recFNFromFN.scala:48:50]
wire [2:0] _io_out_c_self_rec_T_17 = io_out_c_self_rec_rawIn_2_isZero ? 3'h0 : _io_out_c_self_rec_T_16; // @[recFNFromFN.scala:48:{15,50}]
wire [2:0] _io_out_c_self_rec_T_19 = {_io_out_c_self_rec_T_17[2:1], _io_out_c_self_rec_T_17[0] | _io_out_c_self_rec_T_18}; // @[recFNFromFN.scala:48:{15,76}, :49:20]
wire [3:0] _io_out_c_self_rec_T_20 = {io_out_c_self_rec_rawIn_2_sign, _io_out_c_self_rec_T_19}; // @[recFNFromFN.scala:47:20, :48:76]
wire [5:0] _io_out_c_self_rec_T_21 = io_out_c_self_rec_rawIn_2_sExp[5:0]; // @[recFNFromFN.scala:50:23]
wire [9:0] _io_out_c_self_rec_T_22 = {_io_out_c_self_rec_T_20, _io_out_c_self_rec_T_21}; // @[recFNFromFN.scala:47:20, :49:45, :50:23]
wire [22:0] _io_out_c_self_rec_T_23 = io_out_c_self_rec_rawIn_2_sig[22:0]; // @[recFNFromFN.scala:51:22]
wire [32:0] io_out_c_self_rec_2 = {_io_out_c_self_rec_T_22, _io_out_c_self_rec_T_23}; // @[recFNFromFN.scala:49:45, :50:41, :51:22]
wire [7:0] io_out_c_shift_exp_1; // @[Arithmetic.scala:442:29]
wire [6:0] _io_out_c_shift_exp_T_3 = _io_out_c_shift_exp_T_2[6:0]; // @[Arithmetic.scala:443:34]
assign io_out_c_shift_exp_1 = {1'h0, _io_out_c_shift_exp_T_3}; // @[Arithmetic.scala:442:29, :443:{19,34}]
wire [8:0] io_out_c_shift_fn_hi_1 = {1'h0, io_out_c_shift_exp_1}; // @[Arithmetic.scala:442:29, :444:27]
wire [31:0] io_out_c_shift_fn_1 = {io_out_c_shift_fn_hi_1, 23'h0}; // @[Arithmetic.scala:444:27]
wire io_out_c_shift_rec_rawIn_sign_1 = io_out_c_shift_fn_1[31]; // @[rawFloatFromFN.scala:44:18]
wire io_out_c_shift_rec_rawIn_1_sign = io_out_c_shift_rec_rawIn_sign_1; // @[rawFloatFromFN.scala:44:18, :63:19]
wire [7:0] io_out_c_shift_rec_rawIn_expIn_1 = io_out_c_shift_fn_1[30:23]; // @[rawFloatFromFN.scala:45:19]
wire [22:0] io_out_c_shift_rec_rawIn_fractIn_1 = io_out_c_shift_fn_1[22:0]; // @[rawFloatFromFN.scala:46:21]
wire io_out_c_shift_rec_rawIn_isZeroExpIn_1 = io_out_c_shift_rec_rawIn_expIn_1 == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30]
wire io_out_c_shift_rec_rawIn_isZeroFractIn_1 = io_out_c_shift_rec_rawIn_fractIn_1 == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34]
wire _io_out_c_shift_rec_rawIn_normDist_T_44 = io_out_c_shift_rec_rawIn_fractIn_1[0]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_c_shift_rec_rawIn_normDist_T_45 = io_out_c_shift_rec_rawIn_fractIn_1[1]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_c_shift_rec_rawIn_normDist_T_46 = io_out_c_shift_rec_rawIn_fractIn_1[2]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_c_shift_rec_rawIn_normDist_T_47 = io_out_c_shift_rec_rawIn_fractIn_1[3]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_c_shift_rec_rawIn_normDist_T_48 = io_out_c_shift_rec_rawIn_fractIn_1[4]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_c_shift_rec_rawIn_normDist_T_49 = io_out_c_shift_rec_rawIn_fractIn_1[5]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_c_shift_rec_rawIn_normDist_T_50 = io_out_c_shift_rec_rawIn_fractIn_1[6]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_c_shift_rec_rawIn_normDist_T_51 = io_out_c_shift_rec_rawIn_fractIn_1[7]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_c_shift_rec_rawIn_normDist_T_52 = io_out_c_shift_rec_rawIn_fractIn_1[8]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_c_shift_rec_rawIn_normDist_T_53 = io_out_c_shift_rec_rawIn_fractIn_1[9]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_c_shift_rec_rawIn_normDist_T_54 = io_out_c_shift_rec_rawIn_fractIn_1[10]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_c_shift_rec_rawIn_normDist_T_55 = io_out_c_shift_rec_rawIn_fractIn_1[11]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_c_shift_rec_rawIn_normDist_T_56 = io_out_c_shift_rec_rawIn_fractIn_1[12]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_c_shift_rec_rawIn_normDist_T_57 = io_out_c_shift_rec_rawIn_fractIn_1[13]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_c_shift_rec_rawIn_normDist_T_58 = io_out_c_shift_rec_rawIn_fractIn_1[14]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_c_shift_rec_rawIn_normDist_T_59 = io_out_c_shift_rec_rawIn_fractIn_1[15]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_c_shift_rec_rawIn_normDist_T_60 = io_out_c_shift_rec_rawIn_fractIn_1[16]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_c_shift_rec_rawIn_normDist_T_61 = io_out_c_shift_rec_rawIn_fractIn_1[17]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_c_shift_rec_rawIn_normDist_T_62 = io_out_c_shift_rec_rawIn_fractIn_1[18]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_c_shift_rec_rawIn_normDist_T_63 = io_out_c_shift_rec_rawIn_fractIn_1[19]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_c_shift_rec_rawIn_normDist_T_64 = io_out_c_shift_rec_rawIn_fractIn_1[20]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_c_shift_rec_rawIn_normDist_T_65 = io_out_c_shift_rec_rawIn_fractIn_1[21]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_c_shift_rec_rawIn_normDist_T_66 = io_out_c_shift_rec_rawIn_fractIn_1[22]; // @[rawFloatFromFN.scala:46:21]
wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_67 = _io_out_c_shift_rec_rawIn_normDist_T_45 ? 5'h15 : 5'h16; // @[Mux.scala:50:70]
wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_68 = _io_out_c_shift_rec_rawIn_normDist_T_46 ? 5'h14 : _io_out_c_shift_rec_rawIn_normDist_T_67; // @[Mux.scala:50:70]
wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_69 = _io_out_c_shift_rec_rawIn_normDist_T_47 ? 5'h13 : _io_out_c_shift_rec_rawIn_normDist_T_68; // @[Mux.scala:50:70]
wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_70 = _io_out_c_shift_rec_rawIn_normDist_T_48 ? 5'h12 : _io_out_c_shift_rec_rawIn_normDist_T_69; // @[Mux.scala:50:70]
wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_71 = _io_out_c_shift_rec_rawIn_normDist_T_49 ? 5'h11 : _io_out_c_shift_rec_rawIn_normDist_T_70; // @[Mux.scala:50:70]
wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_72 = _io_out_c_shift_rec_rawIn_normDist_T_50 ? 5'h10 : _io_out_c_shift_rec_rawIn_normDist_T_71; // @[Mux.scala:50:70]
wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_73 = _io_out_c_shift_rec_rawIn_normDist_T_51 ? 5'hF : _io_out_c_shift_rec_rawIn_normDist_T_72; // @[Mux.scala:50:70]
wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_74 = _io_out_c_shift_rec_rawIn_normDist_T_52 ? 5'hE : _io_out_c_shift_rec_rawIn_normDist_T_73; // @[Mux.scala:50:70]
wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_75 = _io_out_c_shift_rec_rawIn_normDist_T_53 ? 5'hD : _io_out_c_shift_rec_rawIn_normDist_T_74; // @[Mux.scala:50:70]
wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_76 = _io_out_c_shift_rec_rawIn_normDist_T_54 ? 5'hC : _io_out_c_shift_rec_rawIn_normDist_T_75; // @[Mux.scala:50:70]
wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_77 = _io_out_c_shift_rec_rawIn_normDist_T_55 ? 5'hB : _io_out_c_shift_rec_rawIn_normDist_T_76; // @[Mux.scala:50:70]
wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_78 = _io_out_c_shift_rec_rawIn_normDist_T_56 ? 5'hA : _io_out_c_shift_rec_rawIn_normDist_T_77; // @[Mux.scala:50:70]
wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_79 = _io_out_c_shift_rec_rawIn_normDist_T_57 ? 5'h9 : _io_out_c_shift_rec_rawIn_normDist_T_78; // @[Mux.scala:50:70]
wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_80 = _io_out_c_shift_rec_rawIn_normDist_T_58 ? 5'h8 : _io_out_c_shift_rec_rawIn_normDist_T_79; // @[Mux.scala:50:70]
wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_81 = _io_out_c_shift_rec_rawIn_normDist_T_59 ? 5'h7 : _io_out_c_shift_rec_rawIn_normDist_T_80; // @[Mux.scala:50:70]
wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_82 = _io_out_c_shift_rec_rawIn_normDist_T_60 ? 5'h6 : _io_out_c_shift_rec_rawIn_normDist_T_81; // @[Mux.scala:50:70]
wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_83 = _io_out_c_shift_rec_rawIn_normDist_T_61 ? 5'h5 : _io_out_c_shift_rec_rawIn_normDist_T_82; // @[Mux.scala:50:70]
wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_84 = _io_out_c_shift_rec_rawIn_normDist_T_62 ? 5'h4 : _io_out_c_shift_rec_rawIn_normDist_T_83; // @[Mux.scala:50:70]
wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_85 = _io_out_c_shift_rec_rawIn_normDist_T_63 ? 5'h3 : _io_out_c_shift_rec_rawIn_normDist_T_84; // @[Mux.scala:50:70]
wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_86 = _io_out_c_shift_rec_rawIn_normDist_T_64 ? 5'h2 : _io_out_c_shift_rec_rawIn_normDist_T_85; // @[Mux.scala:50:70]
wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_87 = _io_out_c_shift_rec_rawIn_normDist_T_65 ? 5'h1 : _io_out_c_shift_rec_rawIn_normDist_T_86; // @[Mux.scala:50:70]
wire [4:0] io_out_c_shift_rec_rawIn_normDist_1 = _io_out_c_shift_rec_rawIn_normDist_T_66 ? 5'h0 : _io_out_c_shift_rec_rawIn_normDist_T_87; // @[Mux.scala:50:70]
wire [53:0] _io_out_c_shift_rec_rawIn_subnormFract_T_2 = {31'h0, io_out_c_shift_rec_rawIn_fractIn_1} << io_out_c_shift_rec_rawIn_normDist_1; // @[Mux.scala:50:70]
wire [21:0] _io_out_c_shift_rec_rawIn_subnormFract_T_3 = _io_out_c_shift_rec_rawIn_subnormFract_T_2[21:0]; // @[rawFloatFromFN.scala:52:{33,46}]
wire [22:0] io_out_c_shift_rec_rawIn_subnormFract_1 = {_io_out_c_shift_rec_rawIn_subnormFract_T_3, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}]
wire [8:0] _io_out_c_shift_rec_rawIn_adjustedExp_T_5 = {4'hF, ~io_out_c_shift_rec_rawIn_normDist_1}; // @[Mux.scala:50:70]
wire [8:0] _io_out_c_shift_rec_rawIn_adjustedExp_T_6 = io_out_c_shift_rec_rawIn_isZeroExpIn_1 ? _io_out_c_shift_rec_rawIn_adjustedExp_T_5 : {1'h0, io_out_c_shift_rec_rawIn_expIn_1}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18]
wire [1:0] _io_out_c_shift_rec_rawIn_adjustedExp_T_7 = io_out_c_shift_rec_rawIn_isZeroExpIn_1 ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14]
wire [7:0] _io_out_c_shift_rec_rawIn_adjustedExp_T_8 = {6'h20, _io_out_c_shift_rec_rawIn_adjustedExp_T_7}; // @[rawFloatFromFN.scala:58:{9,14}]
wire [9:0] _io_out_c_shift_rec_rawIn_adjustedExp_T_9 = {1'h0, _io_out_c_shift_rec_rawIn_adjustedExp_T_6} + {2'h0, _io_out_c_shift_rec_rawIn_adjustedExp_T_8}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9]
wire [8:0] io_out_c_shift_rec_rawIn_adjustedExp_1 = _io_out_c_shift_rec_rawIn_adjustedExp_T_9[8:0]; // @[rawFloatFromFN.scala:57:9]
wire [8:0] _io_out_c_shift_rec_rawIn_out_sExp_T_2 = io_out_c_shift_rec_rawIn_adjustedExp_1; // @[rawFloatFromFN.scala:57:9, :68:28]
wire io_out_c_shift_rec_rawIn_isZero_1 = io_out_c_shift_rec_rawIn_isZeroExpIn_1 & io_out_c_shift_rec_rawIn_isZeroFractIn_1; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30]
wire io_out_c_shift_rec_rawIn_1_isZero = io_out_c_shift_rec_rawIn_isZero_1; // @[rawFloatFromFN.scala:60:30, :63:19]
wire [1:0] _io_out_c_shift_rec_rawIn_isSpecial_T_1 = io_out_c_shift_rec_rawIn_adjustedExp_1[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32]
wire io_out_c_shift_rec_rawIn_isSpecial_1 = &_io_out_c_shift_rec_rawIn_isSpecial_T_1; // @[rawFloatFromFN.scala:61:{32,57}]
wire _io_out_c_shift_rec_rawIn_out_isNaN_T_3; // @[rawFloatFromFN.scala:64:28]
wire _io_out_c_shift_rec_rawIn_out_isInf_T_1; // @[rawFloatFromFN.scala:65:28]
wire _io_out_c_shift_rec_T_10 = io_out_c_shift_rec_rawIn_1_isNaN; // @[recFNFromFN.scala:49:20]
wire [9:0] _io_out_c_shift_rec_rawIn_out_sExp_T_3; // @[rawFloatFromFN.scala:68:42]
wire [24:0] _io_out_c_shift_rec_rawIn_out_sig_T_7; // @[rawFloatFromFN.scala:70:27]
wire io_out_c_shift_rec_rawIn_1_isInf; // @[rawFloatFromFN.scala:63:19]
wire [9:0] io_out_c_shift_rec_rawIn_1_sExp; // @[rawFloatFromFN.scala:63:19]
wire [24:0] io_out_c_shift_rec_rawIn_1_sig; // @[rawFloatFromFN.scala:63:19]
wire _io_out_c_shift_rec_rawIn_out_isNaN_T_2 = ~io_out_c_shift_rec_rawIn_isZeroFractIn_1; // @[rawFloatFromFN.scala:49:34, :64:31]
assign _io_out_c_shift_rec_rawIn_out_isNaN_T_3 = io_out_c_shift_rec_rawIn_isSpecial_1 & _io_out_c_shift_rec_rawIn_out_isNaN_T_2; // @[rawFloatFromFN.scala:61:57, :64:{28,31}]
assign io_out_c_shift_rec_rawIn_1_isNaN = _io_out_c_shift_rec_rawIn_out_isNaN_T_3; // @[rawFloatFromFN.scala:63:19, :64:28]
assign _io_out_c_shift_rec_rawIn_out_isInf_T_1 = io_out_c_shift_rec_rawIn_isSpecial_1 & io_out_c_shift_rec_rawIn_isZeroFractIn_1; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28]
assign io_out_c_shift_rec_rawIn_1_isInf = _io_out_c_shift_rec_rawIn_out_isInf_T_1; // @[rawFloatFromFN.scala:63:19, :65:28]
assign _io_out_c_shift_rec_rawIn_out_sExp_T_3 = {1'h0, _io_out_c_shift_rec_rawIn_out_sExp_T_2}; // @[rawFloatFromFN.scala:68:{28,42}]
assign io_out_c_shift_rec_rawIn_1_sExp = _io_out_c_shift_rec_rawIn_out_sExp_T_3; // @[rawFloatFromFN.scala:63:19, :68:42]
wire _io_out_c_shift_rec_rawIn_out_sig_T_4 = ~io_out_c_shift_rec_rawIn_isZero_1; // @[rawFloatFromFN.scala:60:30, :70:19]
wire [1:0] _io_out_c_shift_rec_rawIn_out_sig_T_5 = {1'h0, _io_out_c_shift_rec_rawIn_out_sig_T_4}; // @[rawFloatFromFN.scala:70:{16,19}]
wire [22:0] _io_out_c_shift_rec_rawIn_out_sig_T_6 = io_out_c_shift_rec_rawIn_isZeroExpIn_1 ? io_out_c_shift_rec_rawIn_subnormFract_1 : io_out_c_shift_rec_rawIn_fractIn_1; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33]
assign _io_out_c_shift_rec_rawIn_out_sig_T_7 = {_io_out_c_shift_rec_rawIn_out_sig_T_5, _io_out_c_shift_rec_rawIn_out_sig_T_6}; // @[rawFloatFromFN.scala:70:{16,27,33}]
assign io_out_c_shift_rec_rawIn_1_sig = _io_out_c_shift_rec_rawIn_out_sig_T_7; // @[rawFloatFromFN.scala:63:19, :70:27]
wire [2:0] _io_out_c_shift_rec_T_8 = io_out_c_shift_rec_rawIn_1_sExp[8:6]; // @[recFNFromFN.scala:48:50]
wire [2:0] _io_out_c_shift_rec_T_9 = io_out_c_shift_rec_rawIn_1_isZero ? 3'h0 : _io_out_c_shift_rec_T_8; // @[recFNFromFN.scala:48:{15,50}]
wire [2:0] _io_out_c_shift_rec_T_11 = {_io_out_c_shift_rec_T_9[2:1], _io_out_c_shift_rec_T_9[0] | _io_out_c_shift_rec_T_10}; // @[recFNFromFN.scala:48:{15,76}, :49:20]
wire [3:0] _io_out_c_shift_rec_T_12 = {io_out_c_shift_rec_rawIn_1_sign, _io_out_c_shift_rec_T_11}; // @[recFNFromFN.scala:47:20, :48:76]
wire [5:0] _io_out_c_shift_rec_T_13 = io_out_c_shift_rec_rawIn_1_sExp[5:0]; // @[recFNFromFN.scala:50:23]
wire [9:0] _io_out_c_shift_rec_T_14 = {_io_out_c_shift_rec_T_12, _io_out_c_shift_rec_T_13}; // @[recFNFromFN.scala:47:20, :49:45, :50:23]
wire [22:0] _io_out_c_shift_rec_T_15 = io_out_c_shift_rec_rawIn_1_sig[22:0]; // @[recFNFromFN.scala:51:22]
wire [32:0] io_out_c_shift_rec_1 = {_io_out_c_shift_rec_T_14, _io_out_c_shift_rec_T_15}; // @[recFNFromFN.scala:49:45, :50:41, :51:22]
wire _io_out_c_T_4 = |io_out_c_shift_exp_1; // @[Arithmetic.scala:442:29, :447:26]
wire _io_out_c_T_6 = ~_io_out_c_T_5; // @[Arithmetic.scala:447:15]
wire _io_out_c_T_7 = ~_io_out_c_T_4; // @[Arithmetic.scala:447:{15,26}] |
Generate the Verilog code corresponding to the following Chisel files.
File primitives.scala:
/*============================================================================
This Chisel source file is part of a pre-release version of the HardFloat IEEE
Floating-Point Arithmetic Package, by John R. Hauser (with some contributions
from Yunsup Lee and Andrew Waterman, mainly concerning testing).
Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
University of California. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
package hardfloat
import chisel3._
import chisel3.util._
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
object lowMask
{
def apply(in: UInt, topBound: BigInt, bottomBound: BigInt): UInt =
{
require(topBound != bottomBound)
val numInVals = BigInt(1)<<in.getWidth
if (topBound < bottomBound) {
lowMask(~in, numInVals - 1 - topBound, numInVals - 1 - bottomBound)
} else if (numInVals > 64 /* Empirical */) {
// For simulation performance, we should avoid generating
// exteremely wide shifters, so we divide and conquer.
// Empirically, this does not impact synthesis QoR.
val mid = numInVals / 2
val msb = in(in.getWidth - 1)
val lsbs = in(in.getWidth - 2, 0)
if (mid < topBound) {
if (mid <= bottomBound) {
Mux(msb,
lowMask(lsbs, topBound - mid, bottomBound - mid),
0.U
)
} else {
Mux(msb,
lowMask(lsbs, topBound - mid, 0) ## ((BigInt(1)<<(mid - bottomBound).toInt) - 1).U,
lowMask(lsbs, mid, bottomBound)
)
}
} else {
~Mux(msb, 0.U, ~lowMask(lsbs, topBound, bottomBound))
}
} else {
val shift = (BigInt(-1)<<numInVals.toInt).S>>in
Reverse(
shift(
(numInVals - 1 - bottomBound).toInt,
(numInVals - topBound).toInt
)
)
}
}
}
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
object countLeadingZeros
{
def apply(in: UInt): UInt = PriorityEncoder(in.asBools.reverse)
}
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
object orReduceBy2
{
def apply(in: UInt): UInt =
{
val reducedWidth = (in.getWidth + 1)>>1
val reducedVec = Wire(Vec(reducedWidth, Bool()))
for (ix <- 0 until reducedWidth - 1) {
reducedVec(ix) := in(ix * 2 + 1, ix * 2).orR
}
reducedVec(reducedWidth - 1) :=
in(in.getWidth - 1, (reducedWidth - 1) * 2).orR
reducedVec.asUInt
}
}
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
object orReduceBy4
{
def apply(in: UInt): UInt =
{
val reducedWidth = (in.getWidth + 3)>>2
val reducedVec = Wire(Vec(reducedWidth, Bool()))
for (ix <- 0 until reducedWidth - 1) {
reducedVec(ix) := in(ix * 4 + 3, ix * 4).orR
}
reducedVec(reducedWidth - 1) :=
in(in.getWidth - 1, (reducedWidth - 1) * 4).orR
reducedVec.asUInt
}
}
File MulAddRecFN.scala:
/*============================================================================
This Chisel source file is part of a pre-release version of the HardFloat IEEE
Floating-Point Arithmetic Package, by John R. Hauser (with some contributions
from Yunsup Lee and Andrew Waterman, mainly concerning testing).
Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
University of California. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
package hardfloat
import chisel3._
import chisel3.util._
import consts._
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
class MulAddRecFN_interIo(expWidth: Int, sigWidth: Int) extends Bundle
{
//*** ENCODE SOME OF THESE CASES IN FEWER BITS?:
val isSigNaNAny = Bool()
val isNaNAOrB = Bool()
val isInfA = Bool()
val isZeroA = Bool()
val isInfB = Bool()
val isZeroB = Bool()
val signProd = Bool()
val isNaNC = Bool()
val isInfC = Bool()
val isZeroC = Bool()
val sExpSum = SInt((expWidth + 2).W)
val doSubMags = Bool()
val CIsDominant = Bool()
val CDom_CAlignDist = UInt(log2Ceil(sigWidth + 1).W)
val highAlignedSigC = UInt((sigWidth + 2).W)
val bit0AlignedSigC = UInt(1.W)
}
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
class MulAddRecFNToRaw_preMul(expWidth: Int, sigWidth: Int) extends RawModule
{
override def desiredName = s"MulAddRecFNToRaw_preMul_e${expWidth}_s${sigWidth}"
val io = IO(new Bundle {
val op = Input(Bits(2.W))
val a = Input(Bits((expWidth + sigWidth + 1).W))
val b = Input(Bits((expWidth + sigWidth + 1).W))
val c = Input(Bits((expWidth + sigWidth + 1).W))
val mulAddA = Output(UInt(sigWidth.W))
val mulAddB = Output(UInt(sigWidth.W))
val mulAddC = Output(UInt((sigWidth * 2).W))
val toPostMul = Output(new MulAddRecFN_interIo(expWidth, sigWidth))
})
//------------------------------------------------------------------------
//------------------------------------------------------------------------
//*** POSSIBLE TO REDUCE THIS BY 1 OR 2 BITS? (CURRENTLY 2 BITS BETWEEN
//*** UNSHIFTED C AND PRODUCT):
val sigSumWidth = sigWidth * 3 + 3
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val rawA = rawFloatFromRecFN(expWidth, sigWidth, io.a)
val rawB = rawFloatFromRecFN(expWidth, sigWidth, io.b)
val rawC = rawFloatFromRecFN(expWidth, sigWidth, io.c)
val signProd = rawA.sign ^ rawB.sign ^ io.op(1)
//*** REVIEW THE BIAS FOR 'sExpAlignedProd':
val sExpAlignedProd =
rawA.sExp +& rawB.sExp + (-(BigInt(1)<<expWidth) + sigWidth + 3).S
val doSubMags = signProd ^ rawC.sign ^ io.op(0)
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val sNatCAlignDist = sExpAlignedProd - rawC.sExp
val posNatCAlignDist = sNatCAlignDist(expWidth + 1, 0)
val isMinCAlign = rawA.isZero || rawB.isZero || (sNatCAlignDist < 0.S)
val CIsDominant =
! rawC.isZero && (isMinCAlign || (posNatCAlignDist <= sigWidth.U))
val CAlignDist =
Mux(isMinCAlign,
0.U,
Mux(posNatCAlignDist < (sigSumWidth - 1).U,
posNatCAlignDist(log2Ceil(sigSumWidth) - 1, 0),
(sigSumWidth - 1).U
)
)
val mainAlignedSigC =
(Mux(doSubMags, ~rawC.sig, rawC.sig) ## Fill(sigSumWidth - sigWidth + 2, doSubMags)).asSInt>>CAlignDist
val reduced4CExtra =
(orReduceBy4(rawC.sig<<((sigSumWidth - sigWidth - 1) & 3)) &
lowMask(
CAlignDist>>2,
//*** NOT NEEDED?:
// (sigSumWidth + 2)>>2,
(sigSumWidth - 1)>>2,
(sigSumWidth - sigWidth - 1)>>2
)
).orR
val alignedSigC =
Cat(mainAlignedSigC>>3,
Mux(doSubMags,
mainAlignedSigC(2, 0).andR && ! reduced4CExtra,
mainAlignedSigC(2, 0).orR || reduced4CExtra
)
)
//------------------------------------------------------------------------
//------------------------------------------------------------------------
io.mulAddA := rawA.sig
io.mulAddB := rawB.sig
io.mulAddC := alignedSigC(sigWidth * 2, 1)
io.toPostMul.isSigNaNAny :=
isSigNaNRawFloat(rawA) || isSigNaNRawFloat(rawB) ||
isSigNaNRawFloat(rawC)
io.toPostMul.isNaNAOrB := rawA.isNaN || rawB.isNaN
io.toPostMul.isInfA := rawA.isInf
io.toPostMul.isZeroA := rawA.isZero
io.toPostMul.isInfB := rawB.isInf
io.toPostMul.isZeroB := rawB.isZero
io.toPostMul.signProd := signProd
io.toPostMul.isNaNC := rawC.isNaN
io.toPostMul.isInfC := rawC.isInf
io.toPostMul.isZeroC := rawC.isZero
io.toPostMul.sExpSum :=
Mux(CIsDominant, rawC.sExp, sExpAlignedProd - sigWidth.S)
io.toPostMul.doSubMags := doSubMags
io.toPostMul.CIsDominant := CIsDominant
io.toPostMul.CDom_CAlignDist := CAlignDist(log2Ceil(sigWidth + 1) - 1, 0)
io.toPostMul.highAlignedSigC :=
alignedSigC(sigSumWidth - 1, sigWidth * 2 + 1)
io.toPostMul.bit0AlignedSigC := alignedSigC(0)
}
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
class MulAddRecFNToRaw_postMul(expWidth: Int, sigWidth: Int) extends RawModule
{
override def desiredName = s"MulAddRecFNToRaw_postMul_e${expWidth}_s${sigWidth}"
val io = IO(new Bundle {
val fromPreMul = Input(new MulAddRecFN_interIo(expWidth, sigWidth))
val mulAddResult = Input(UInt((sigWidth * 2 + 1).W))
val roundingMode = Input(UInt(3.W))
val invalidExc = Output(Bool())
val rawOut = Output(new RawFloat(expWidth, sigWidth + 2))
})
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val sigSumWidth = sigWidth * 3 + 3
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val roundingMode_min = (io.roundingMode === round_min)
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val opSignC = io.fromPreMul.signProd ^ io.fromPreMul.doSubMags
val sigSum =
Cat(Mux(io.mulAddResult(sigWidth * 2),
io.fromPreMul.highAlignedSigC + 1.U,
io.fromPreMul.highAlignedSigC
),
io.mulAddResult(sigWidth * 2 - 1, 0),
io.fromPreMul.bit0AlignedSigC
)
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val CDom_sign = opSignC
val CDom_sExp = io.fromPreMul.sExpSum - io.fromPreMul.doSubMags.zext
val CDom_absSigSum =
Mux(io.fromPreMul.doSubMags,
~sigSum(sigSumWidth - 1, sigWidth + 1),
0.U(1.W) ##
//*** IF GAP IS REDUCED TO 1 BIT, MUST REDUCE THIS COMPONENT TO 1 BIT TOO:
io.fromPreMul.highAlignedSigC(sigWidth + 1, sigWidth) ##
sigSum(sigSumWidth - 3, sigWidth + 2)
)
val CDom_absSigSumExtra =
Mux(io.fromPreMul.doSubMags,
(~sigSum(sigWidth, 1)).orR,
sigSum(sigWidth + 1, 1).orR
)
val CDom_mainSig =
(CDom_absSigSum<<io.fromPreMul.CDom_CAlignDist)(
sigWidth * 2 + 1, sigWidth - 3)
val CDom_reduced4SigExtra =
(orReduceBy4(CDom_absSigSum(sigWidth - 1, 0)<<(~sigWidth & 3)) &
lowMask(io.fromPreMul.CDom_CAlignDist>>2, 0, sigWidth>>2)).orR
val CDom_sig =
Cat(CDom_mainSig>>3,
CDom_mainSig(2, 0).orR || CDom_reduced4SigExtra ||
CDom_absSigSumExtra
)
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val notCDom_signSigSum = sigSum(sigWidth * 2 + 3)
val notCDom_absSigSum =
Mux(notCDom_signSigSum,
~sigSum(sigWidth * 2 + 2, 0),
sigSum(sigWidth * 2 + 2, 0) + io.fromPreMul.doSubMags
)
val notCDom_reduced2AbsSigSum = orReduceBy2(notCDom_absSigSum)
val notCDom_normDistReduced2 = countLeadingZeros(notCDom_reduced2AbsSigSum)
val notCDom_nearNormDist = notCDom_normDistReduced2<<1
val notCDom_sExp = io.fromPreMul.sExpSum - notCDom_nearNormDist.asUInt.zext
val notCDom_mainSig =
(notCDom_absSigSum<<notCDom_nearNormDist)(
sigWidth * 2 + 3, sigWidth - 1)
val notCDom_reduced4SigExtra =
(orReduceBy2(
notCDom_reduced2AbsSigSum(sigWidth>>1, 0)<<((sigWidth>>1) & 1)) &
lowMask(notCDom_normDistReduced2>>1, 0, (sigWidth + 2)>>2)
).orR
val notCDom_sig =
Cat(notCDom_mainSig>>3,
notCDom_mainSig(2, 0).orR || notCDom_reduced4SigExtra
)
val notCDom_completeCancellation =
(notCDom_sig(sigWidth + 2, sigWidth + 1) === 0.U)
val notCDom_sign =
Mux(notCDom_completeCancellation,
roundingMode_min,
io.fromPreMul.signProd ^ notCDom_signSigSum
)
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val notNaN_isInfProd = io.fromPreMul.isInfA || io.fromPreMul.isInfB
val notNaN_isInfOut = notNaN_isInfProd || io.fromPreMul.isInfC
val notNaN_addZeros =
(io.fromPreMul.isZeroA || io.fromPreMul.isZeroB) &&
io.fromPreMul.isZeroC
io.invalidExc :=
io.fromPreMul.isSigNaNAny ||
(io.fromPreMul.isInfA && io.fromPreMul.isZeroB) ||
(io.fromPreMul.isZeroA && io.fromPreMul.isInfB) ||
(! io.fromPreMul.isNaNAOrB &&
(io.fromPreMul.isInfA || io.fromPreMul.isInfB) &&
io.fromPreMul.isInfC &&
io.fromPreMul.doSubMags)
io.rawOut.isNaN := io.fromPreMul.isNaNAOrB || io.fromPreMul.isNaNC
io.rawOut.isInf := notNaN_isInfOut
//*** IMPROVE?:
io.rawOut.isZero :=
notNaN_addZeros ||
(! io.fromPreMul.CIsDominant && notCDom_completeCancellation)
io.rawOut.sign :=
(notNaN_isInfProd && io.fromPreMul.signProd) ||
(io.fromPreMul.isInfC && opSignC) ||
(notNaN_addZeros && ! roundingMode_min &&
io.fromPreMul.signProd && opSignC) ||
(notNaN_addZeros && roundingMode_min &&
(io.fromPreMul.signProd || opSignC)) ||
(! notNaN_isInfOut && ! notNaN_addZeros &&
Mux(io.fromPreMul.CIsDominant, CDom_sign, notCDom_sign))
io.rawOut.sExp := Mux(io.fromPreMul.CIsDominant, CDom_sExp, notCDom_sExp)
io.rawOut.sig := Mux(io.fromPreMul.CIsDominant, CDom_sig, notCDom_sig)
}
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
class MulAddRecFN(expWidth: Int, sigWidth: Int) extends RawModule
{
override def desiredName = s"MulAddRecFN_e${expWidth}_s${sigWidth}"
val io = IO(new Bundle {
val op = Input(Bits(2.W))
val a = Input(Bits((expWidth + sigWidth + 1).W))
val b = Input(Bits((expWidth + sigWidth + 1).W))
val c = Input(Bits((expWidth + sigWidth + 1).W))
val roundingMode = Input(UInt(3.W))
val detectTininess = Input(UInt(1.W))
val out = Output(Bits((expWidth + sigWidth + 1).W))
val exceptionFlags = Output(Bits(5.W))
})
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val mulAddRecFNToRaw_preMul =
Module(new MulAddRecFNToRaw_preMul(expWidth, sigWidth))
val mulAddRecFNToRaw_postMul =
Module(new MulAddRecFNToRaw_postMul(expWidth, sigWidth))
mulAddRecFNToRaw_preMul.io.op := io.op
mulAddRecFNToRaw_preMul.io.a := io.a
mulAddRecFNToRaw_preMul.io.b := io.b
mulAddRecFNToRaw_preMul.io.c := io.c
val mulAddResult =
(mulAddRecFNToRaw_preMul.io.mulAddA *
mulAddRecFNToRaw_preMul.io.mulAddB) +&
mulAddRecFNToRaw_preMul.io.mulAddC
mulAddRecFNToRaw_postMul.io.fromPreMul :=
mulAddRecFNToRaw_preMul.io.toPostMul
mulAddRecFNToRaw_postMul.io.mulAddResult := mulAddResult
mulAddRecFNToRaw_postMul.io.roundingMode := io.roundingMode
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val roundRawFNToRecFN =
Module(new RoundRawFNToRecFN(expWidth, sigWidth, 0))
roundRawFNToRecFN.io.invalidExc := mulAddRecFNToRaw_postMul.io.invalidExc
roundRawFNToRecFN.io.infiniteExc := false.B
roundRawFNToRecFN.io.in := mulAddRecFNToRaw_postMul.io.rawOut
roundRawFNToRecFN.io.roundingMode := io.roundingMode
roundRawFNToRecFN.io.detectTininess := io.detectTininess
io.out := roundRawFNToRecFN.io.out
io.exceptionFlags := roundRawFNToRecFN.io.exceptionFlags
}
| module MulAddRecFNToRaw_postMul_e11_s53_6( // @[MulAddRecFN.scala:169:7]
input io_fromPreMul_isSigNaNAny, // @[MulAddRecFN.scala:172:16]
input io_fromPreMul_isNaNAOrB, // @[MulAddRecFN.scala:172:16]
input io_fromPreMul_isInfA, // @[MulAddRecFN.scala:172:16]
input io_fromPreMul_isZeroA, // @[MulAddRecFN.scala:172:16]
input io_fromPreMul_isInfB, // @[MulAddRecFN.scala:172:16]
input io_fromPreMul_isZeroB, // @[MulAddRecFN.scala:172:16]
input io_fromPreMul_signProd, // @[MulAddRecFN.scala:172:16]
input io_fromPreMul_isNaNC, // @[MulAddRecFN.scala:172:16]
input io_fromPreMul_isInfC, // @[MulAddRecFN.scala:172:16]
input io_fromPreMul_isZeroC, // @[MulAddRecFN.scala:172:16]
input [12:0] io_fromPreMul_sExpSum, // @[MulAddRecFN.scala:172:16]
input io_fromPreMul_doSubMags, // @[MulAddRecFN.scala:172:16]
input io_fromPreMul_CIsDominant, // @[MulAddRecFN.scala:172:16]
input [5:0] io_fromPreMul_CDom_CAlignDist, // @[MulAddRecFN.scala:172:16]
input [54:0] io_fromPreMul_highAlignedSigC, // @[MulAddRecFN.scala:172:16]
input io_fromPreMul_bit0AlignedSigC, // @[MulAddRecFN.scala:172:16]
input [106:0] io_mulAddResult, // @[MulAddRecFN.scala:172:16]
input [2:0] io_roundingMode, // @[MulAddRecFN.scala:172:16]
output io_invalidExc, // @[MulAddRecFN.scala:172:16]
output io_rawOut_isNaN, // @[MulAddRecFN.scala:172:16]
output io_rawOut_isInf, // @[MulAddRecFN.scala:172:16]
output io_rawOut_isZero, // @[MulAddRecFN.scala:172:16]
output io_rawOut_sign, // @[MulAddRecFN.scala:172:16]
output [12:0] io_rawOut_sExp, // @[MulAddRecFN.scala:172:16]
output [55:0] io_rawOut_sig // @[MulAddRecFN.scala:172:16]
);
wire io_fromPreMul_isSigNaNAny_0 = io_fromPreMul_isSigNaNAny; // @[MulAddRecFN.scala:169:7]
wire io_fromPreMul_isNaNAOrB_0 = io_fromPreMul_isNaNAOrB; // @[MulAddRecFN.scala:169:7]
wire io_fromPreMul_isInfA_0 = io_fromPreMul_isInfA; // @[MulAddRecFN.scala:169:7]
wire io_fromPreMul_isZeroA_0 = io_fromPreMul_isZeroA; // @[MulAddRecFN.scala:169:7]
wire io_fromPreMul_isInfB_0 = io_fromPreMul_isInfB; // @[MulAddRecFN.scala:169:7]
wire io_fromPreMul_isZeroB_0 = io_fromPreMul_isZeroB; // @[MulAddRecFN.scala:169:7]
wire io_fromPreMul_signProd_0 = io_fromPreMul_signProd; // @[MulAddRecFN.scala:169:7]
wire io_fromPreMul_isNaNC_0 = io_fromPreMul_isNaNC; // @[MulAddRecFN.scala:169:7]
wire io_fromPreMul_isInfC_0 = io_fromPreMul_isInfC; // @[MulAddRecFN.scala:169:7]
wire io_fromPreMul_isZeroC_0 = io_fromPreMul_isZeroC; // @[MulAddRecFN.scala:169:7]
wire [12:0] io_fromPreMul_sExpSum_0 = io_fromPreMul_sExpSum; // @[MulAddRecFN.scala:169:7]
wire io_fromPreMul_doSubMags_0 = io_fromPreMul_doSubMags; // @[MulAddRecFN.scala:169:7]
wire io_fromPreMul_CIsDominant_0 = io_fromPreMul_CIsDominant; // @[MulAddRecFN.scala:169:7]
wire [5:0] io_fromPreMul_CDom_CAlignDist_0 = io_fromPreMul_CDom_CAlignDist; // @[MulAddRecFN.scala:169:7]
wire [54:0] io_fromPreMul_highAlignedSigC_0 = io_fromPreMul_highAlignedSigC; // @[MulAddRecFN.scala:169:7]
wire io_fromPreMul_bit0AlignedSigC_0 = io_fromPreMul_bit0AlignedSigC; // @[MulAddRecFN.scala:169:7]
wire [106:0] io_mulAddResult_0 = io_mulAddResult; // @[MulAddRecFN.scala:169:7]
wire [2:0] io_roundingMode_0 = io_roundingMode; // @[MulAddRecFN.scala:169:7]
wire [7:0] _CDom_reduced4SigExtra_T_8 = 8'hF; // @[primitives.scala:77:20]
wire [7:0] _notCDom_reduced4SigExtra_T_8 = 8'hF; // @[primitives.scala:77:20]
wire [7:0] _CDom_reduced4SigExtra_T_7 = 8'hF0; // @[primitives.scala:77:20]
wire [7:0] _CDom_reduced4SigExtra_T_13 = 8'hF0; // @[primitives.scala:77:20]
wire [7:0] _notCDom_reduced4SigExtra_T_7 = 8'hF0; // @[primitives.scala:77:20]
wire [7:0] _notCDom_reduced4SigExtra_T_13 = 8'hF0; // @[primitives.scala:77:20]
wire [5:0] _CDom_reduced4SigExtra_T_16 = 6'hF; // @[primitives.scala:77:20]
wire [5:0] _notCDom_reduced4SigExtra_T_16 = 6'hF; // @[primitives.scala:77:20]
wire [7:0] _CDom_reduced4SigExtra_T_17 = 8'h3C; // @[primitives.scala:77:20]
wire [7:0] _notCDom_reduced4SigExtra_T_17 = 8'h3C; // @[primitives.scala:77:20]
wire [7:0] _CDom_reduced4SigExtra_T_18 = 8'h33; // @[primitives.scala:77:20]
wire [7:0] _notCDom_reduced4SigExtra_T_18 = 8'h33; // @[primitives.scala:77:20]
wire [7:0] _CDom_reduced4SigExtra_T_23 = 8'hCC; // @[primitives.scala:77:20]
wire [7:0] _notCDom_reduced4SigExtra_T_23 = 8'hCC; // @[primitives.scala:77:20]
wire [6:0] _CDom_reduced4SigExtra_T_26 = 7'h33; // @[primitives.scala:77:20]
wire [6:0] _notCDom_reduced4SigExtra_T_26 = 7'h33; // @[primitives.scala:77:20]
wire [7:0] _CDom_reduced4SigExtra_T_27 = 8'h66; // @[primitives.scala:77:20]
wire [7:0] _notCDom_reduced4SigExtra_T_27 = 8'h66; // @[primitives.scala:77:20]
wire [7:0] _CDom_reduced4SigExtra_T_28 = 8'h55; // @[primitives.scala:77:20]
wire [7:0] _notCDom_reduced4SigExtra_T_28 = 8'h55; // @[primitives.scala:77:20]
wire [7:0] _CDom_reduced4SigExtra_T_33 = 8'hAA; // @[primitives.scala:77:20]
wire [7:0] _notCDom_reduced4SigExtra_T_33 = 8'hAA; // @[primitives.scala:77:20]
wire _io_invalidExc_T_9; // @[MulAddRecFN.scala:273:57]
wire _io_rawOut_isNaN_T; // @[MulAddRecFN.scala:278:48]
wire notNaN_isInfOut; // @[MulAddRecFN.scala:265:44]
wire _io_rawOut_isZero_T_2; // @[MulAddRecFN.scala:282:25]
wire _io_rawOut_sign_T_17; // @[MulAddRecFN.scala:290:50]
wire [12:0] _io_rawOut_sExp_T; // @[MulAddRecFN.scala:293:26]
wire [55:0] _io_rawOut_sig_T; // @[MulAddRecFN.scala:294:25]
wire io_rawOut_isNaN_0; // @[MulAddRecFN.scala:169:7]
wire io_rawOut_isInf_0; // @[MulAddRecFN.scala:169:7]
wire io_rawOut_isZero_0; // @[MulAddRecFN.scala:169:7]
wire io_rawOut_sign_0; // @[MulAddRecFN.scala:169:7]
wire [12:0] io_rawOut_sExp_0; // @[MulAddRecFN.scala:169:7]
wire [55:0] io_rawOut_sig_0; // @[MulAddRecFN.scala:169:7]
wire io_invalidExc_0; // @[MulAddRecFN.scala:169:7]
wire roundingMode_min = io_roundingMode_0 == 3'h2; // @[MulAddRecFN.scala:169:7, :186:45]
wire opSignC = io_fromPreMul_signProd_0 ^ io_fromPreMul_doSubMags_0; // @[MulAddRecFN.scala:169:7, :190:42]
wire _sigSum_T = io_mulAddResult_0[106]; // @[MulAddRecFN.scala:169:7, :192:32]
wire [55:0] _sigSum_T_1 = {1'h0, io_fromPreMul_highAlignedSigC_0} + 56'h1; // @[MulAddRecFN.scala:169:7, :193:47]
wire [54:0] _sigSum_T_2 = _sigSum_T_1[54:0]; // @[MulAddRecFN.scala:193:47]
wire [54:0] _sigSum_T_3 = _sigSum_T ? _sigSum_T_2 : io_fromPreMul_highAlignedSigC_0; // @[MulAddRecFN.scala:169:7, :192:{16,32}, :193:47]
wire [105:0] _sigSum_T_4 = io_mulAddResult_0[105:0]; // @[MulAddRecFN.scala:169:7, :196:28]
wire [160:0] sigSum_hi = {_sigSum_T_3, _sigSum_T_4}; // @[MulAddRecFN.scala:192:{12,16}, :196:28]
wire [161:0] sigSum = {sigSum_hi, io_fromPreMul_bit0AlignedSigC_0}; // @[MulAddRecFN.scala:169:7, :192:12]
wire [1:0] _CDom_sExp_T = {1'h0, io_fromPreMul_doSubMags_0}; // @[MulAddRecFN.scala:169:7, :203:69]
wire [13:0] _GEN = {io_fromPreMul_sExpSum_0[12], io_fromPreMul_sExpSum_0}; // @[MulAddRecFN.scala:169:7, :203:43]
wire [13:0] _CDom_sExp_T_1 = _GEN - {{12{_CDom_sExp_T[1]}}, _CDom_sExp_T}; // @[MulAddRecFN.scala:203:{43,69}]
wire [12:0] _CDom_sExp_T_2 = _CDom_sExp_T_1[12:0]; // @[MulAddRecFN.scala:203:43]
wire [12:0] CDom_sExp = _CDom_sExp_T_2; // @[MulAddRecFN.scala:203:43]
wire [107:0] _CDom_absSigSum_T = sigSum[161:54]; // @[MulAddRecFN.scala:192:12, :206:20]
wire [107:0] _CDom_absSigSum_T_1 = ~_CDom_absSigSum_T; // @[MulAddRecFN.scala:206:{13,20}]
wire [1:0] _CDom_absSigSum_T_2 = io_fromPreMul_highAlignedSigC_0[54:53]; // @[MulAddRecFN.scala:169:7, :209:46]
wire [2:0] _CDom_absSigSum_T_3 = {1'h0, _CDom_absSigSum_T_2}; // @[MulAddRecFN.scala:207:22, :209:46]
wire [104:0] _CDom_absSigSum_T_4 = sigSum[159:55]; // @[MulAddRecFN.scala:192:12, :210:23]
wire [107:0] _CDom_absSigSum_T_5 = {_CDom_absSigSum_T_3, _CDom_absSigSum_T_4}; // @[MulAddRecFN.scala:207:22, :209:71, :210:23]
wire [107:0] CDom_absSigSum = io_fromPreMul_doSubMags_0 ? _CDom_absSigSum_T_1 : _CDom_absSigSum_T_5; // @[MulAddRecFN.scala:169:7, :205:12, :206:13, :209:71]
wire [52:0] _CDom_absSigSumExtra_T = sigSum[53:1]; // @[MulAddRecFN.scala:192:12, :215:21]
wire [52:0] _CDom_absSigSumExtra_T_1 = ~_CDom_absSigSumExtra_T; // @[MulAddRecFN.scala:215:{14,21}]
wire _CDom_absSigSumExtra_T_2 = |_CDom_absSigSumExtra_T_1; // @[MulAddRecFN.scala:215:{14,36}]
wire [53:0] _CDom_absSigSumExtra_T_3 = sigSum[54:1]; // @[MulAddRecFN.scala:192:12, :216:19]
wire _CDom_absSigSumExtra_T_4 = |_CDom_absSigSumExtra_T_3; // @[MulAddRecFN.scala:216:{19,37}]
wire CDom_absSigSumExtra = io_fromPreMul_doSubMags_0 ? _CDom_absSigSumExtra_T_2 : _CDom_absSigSumExtra_T_4; // @[MulAddRecFN.scala:169:7, :214:12, :215:36, :216:37]
wire [170:0] _CDom_mainSig_T = {63'h0, CDom_absSigSum} << io_fromPreMul_CDom_CAlignDist_0; // @[MulAddRecFN.scala:169:7, :205:12, :219:24]
wire [57:0] CDom_mainSig = _CDom_mainSig_T[107:50]; // @[MulAddRecFN.scala:219:{24,56}]
wire [52:0] _CDom_reduced4SigExtra_T = CDom_absSigSum[52:0]; // @[MulAddRecFN.scala:205:12, :222:36]
wire [54:0] _CDom_reduced4SigExtra_T_1 = {_CDom_reduced4SigExtra_T, 2'h0}; // @[MulAddRecFN.scala:222:{36,53}]
wire _CDom_reduced4SigExtra_reducedVec_0_T_1; // @[primitives.scala:120:54]
wire _CDom_reduced4SigExtra_reducedVec_1_T_1; // @[primitives.scala:120:54]
wire _CDom_reduced4SigExtra_reducedVec_2_T_1; // @[primitives.scala:120:54]
wire _CDom_reduced4SigExtra_reducedVec_3_T_1; // @[primitives.scala:120:54]
wire _CDom_reduced4SigExtra_reducedVec_4_T_1; // @[primitives.scala:120:54]
wire _CDom_reduced4SigExtra_reducedVec_5_T_1; // @[primitives.scala:120:54]
wire _CDom_reduced4SigExtra_reducedVec_6_T_1; // @[primitives.scala:120:54]
wire _CDom_reduced4SigExtra_reducedVec_7_T_1; // @[primitives.scala:120:54]
wire _CDom_reduced4SigExtra_reducedVec_8_T_1; // @[primitives.scala:120:54]
wire _CDom_reduced4SigExtra_reducedVec_9_T_1; // @[primitives.scala:120:54]
wire _CDom_reduced4SigExtra_reducedVec_10_T_1; // @[primitives.scala:120:54]
wire _CDom_reduced4SigExtra_reducedVec_11_T_1; // @[primitives.scala:120:54]
wire _CDom_reduced4SigExtra_reducedVec_12_T_1; // @[primitives.scala:120:54]
wire _CDom_reduced4SigExtra_reducedVec_13_T_1; // @[primitives.scala:123:57]
wire CDom_reduced4SigExtra_reducedVec_0; // @[primitives.scala:118:30]
wire CDom_reduced4SigExtra_reducedVec_1; // @[primitives.scala:118:30]
wire CDom_reduced4SigExtra_reducedVec_2; // @[primitives.scala:118:30]
wire CDom_reduced4SigExtra_reducedVec_3; // @[primitives.scala:118:30]
wire CDom_reduced4SigExtra_reducedVec_4; // @[primitives.scala:118:30]
wire CDom_reduced4SigExtra_reducedVec_5; // @[primitives.scala:118:30]
wire CDom_reduced4SigExtra_reducedVec_6; // @[primitives.scala:118:30]
wire CDom_reduced4SigExtra_reducedVec_7; // @[primitives.scala:118:30]
wire CDom_reduced4SigExtra_reducedVec_8; // @[primitives.scala:118:30]
wire CDom_reduced4SigExtra_reducedVec_9; // @[primitives.scala:118:30]
wire CDom_reduced4SigExtra_reducedVec_10; // @[primitives.scala:118:30]
wire CDom_reduced4SigExtra_reducedVec_11; // @[primitives.scala:118:30]
wire CDom_reduced4SigExtra_reducedVec_12; // @[primitives.scala:118:30]
wire CDom_reduced4SigExtra_reducedVec_13; // @[primitives.scala:118:30]
wire [3:0] _CDom_reduced4SigExtra_reducedVec_0_T = _CDom_reduced4SigExtra_T_1[3:0]; // @[primitives.scala:120:33]
assign _CDom_reduced4SigExtra_reducedVec_0_T_1 = |_CDom_reduced4SigExtra_reducedVec_0_T; // @[primitives.scala:120:{33,54}]
assign CDom_reduced4SigExtra_reducedVec_0 = _CDom_reduced4SigExtra_reducedVec_0_T_1; // @[primitives.scala:118:30, :120:54]
wire [3:0] _CDom_reduced4SigExtra_reducedVec_1_T = _CDom_reduced4SigExtra_T_1[7:4]; // @[primitives.scala:120:33]
assign _CDom_reduced4SigExtra_reducedVec_1_T_1 = |_CDom_reduced4SigExtra_reducedVec_1_T; // @[primitives.scala:120:{33,54}]
assign CDom_reduced4SigExtra_reducedVec_1 = _CDom_reduced4SigExtra_reducedVec_1_T_1; // @[primitives.scala:118:30, :120:54]
wire [3:0] _CDom_reduced4SigExtra_reducedVec_2_T = _CDom_reduced4SigExtra_T_1[11:8]; // @[primitives.scala:120:33]
assign _CDom_reduced4SigExtra_reducedVec_2_T_1 = |_CDom_reduced4SigExtra_reducedVec_2_T; // @[primitives.scala:120:{33,54}]
assign CDom_reduced4SigExtra_reducedVec_2 = _CDom_reduced4SigExtra_reducedVec_2_T_1; // @[primitives.scala:118:30, :120:54]
wire [3:0] _CDom_reduced4SigExtra_reducedVec_3_T = _CDom_reduced4SigExtra_T_1[15:12]; // @[primitives.scala:120:33]
assign _CDom_reduced4SigExtra_reducedVec_3_T_1 = |_CDom_reduced4SigExtra_reducedVec_3_T; // @[primitives.scala:120:{33,54}]
assign CDom_reduced4SigExtra_reducedVec_3 = _CDom_reduced4SigExtra_reducedVec_3_T_1; // @[primitives.scala:118:30, :120:54]
wire [3:0] _CDom_reduced4SigExtra_reducedVec_4_T = _CDom_reduced4SigExtra_T_1[19:16]; // @[primitives.scala:120:33]
assign _CDom_reduced4SigExtra_reducedVec_4_T_1 = |_CDom_reduced4SigExtra_reducedVec_4_T; // @[primitives.scala:120:{33,54}]
assign CDom_reduced4SigExtra_reducedVec_4 = _CDom_reduced4SigExtra_reducedVec_4_T_1; // @[primitives.scala:118:30, :120:54]
wire [3:0] _CDom_reduced4SigExtra_reducedVec_5_T = _CDom_reduced4SigExtra_T_1[23:20]; // @[primitives.scala:120:33]
assign _CDom_reduced4SigExtra_reducedVec_5_T_1 = |_CDom_reduced4SigExtra_reducedVec_5_T; // @[primitives.scala:120:{33,54}]
assign CDom_reduced4SigExtra_reducedVec_5 = _CDom_reduced4SigExtra_reducedVec_5_T_1; // @[primitives.scala:118:30, :120:54]
wire [3:0] _CDom_reduced4SigExtra_reducedVec_6_T = _CDom_reduced4SigExtra_T_1[27:24]; // @[primitives.scala:120:33]
assign _CDom_reduced4SigExtra_reducedVec_6_T_1 = |_CDom_reduced4SigExtra_reducedVec_6_T; // @[primitives.scala:120:{33,54}]
assign CDom_reduced4SigExtra_reducedVec_6 = _CDom_reduced4SigExtra_reducedVec_6_T_1; // @[primitives.scala:118:30, :120:54]
wire [3:0] _CDom_reduced4SigExtra_reducedVec_7_T = _CDom_reduced4SigExtra_T_1[31:28]; // @[primitives.scala:120:33]
assign _CDom_reduced4SigExtra_reducedVec_7_T_1 = |_CDom_reduced4SigExtra_reducedVec_7_T; // @[primitives.scala:120:{33,54}]
assign CDom_reduced4SigExtra_reducedVec_7 = _CDom_reduced4SigExtra_reducedVec_7_T_1; // @[primitives.scala:118:30, :120:54]
wire [3:0] _CDom_reduced4SigExtra_reducedVec_8_T = _CDom_reduced4SigExtra_T_1[35:32]; // @[primitives.scala:120:33]
assign _CDom_reduced4SigExtra_reducedVec_8_T_1 = |_CDom_reduced4SigExtra_reducedVec_8_T; // @[primitives.scala:120:{33,54}]
assign CDom_reduced4SigExtra_reducedVec_8 = _CDom_reduced4SigExtra_reducedVec_8_T_1; // @[primitives.scala:118:30, :120:54]
wire [3:0] _CDom_reduced4SigExtra_reducedVec_9_T = _CDom_reduced4SigExtra_T_1[39:36]; // @[primitives.scala:120:33]
assign _CDom_reduced4SigExtra_reducedVec_9_T_1 = |_CDom_reduced4SigExtra_reducedVec_9_T; // @[primitives.scala:120:{33,54}]
assign CDom_reduced4SigExtra_reducedVec_9 = _CDom_reduced4SigExtra_reducedVec_9_T_1; // @[primitives.scala:118:30, :120:54]
wire [3:0] _CDom_reduced4SigExtra_reducedVec_10_T = _CDom_reduced4SigExtra_T_1[43:40]; // @[primitives.scala:120:33]
assign _CDom_reduced4SigExtra_reducedVec_10_T_1 = |_CDom_reduced4SigExtra_reducedVec_10_T; // @[primitives.scala:120:{33,54}]
assign CDom_reduced4SigExtra_reducedVec_10 = _CDom_reduced4SigExtra_reducedVec_10_T_1; // @[primitives.scala:118:30, :120:54]
wire [3:0] _CDom_reduced4SigExtra_reducedVec_11_T = _CDom_reduced4SigExtra_T_1[47:44]; // @[primitives.scala:120:33]
assign _CDom_reduced4SigExtra_reducedVec_11_T_1 = |_CDom_reduced4SigExtra_reducedVec_11_T; // @[primitives.scala:120:{33,54}]
assign CDom_reduced4SigExtra_reducedVec_11 = _CDom_reduced4SigExtra_reducedVec_11_T_1; // @[primitives.scala:118:30, :120:54]
wire [3:0] _CDom_reduced4SigExtra_reducedVec_12_T = _CDom_reduced4SigExtra_T_1[51:48]; // @[primitives.scala:120:33]
assign _CDom_reduced4SigExtra_reducedVec_12_T_1 = |_CDom_reduced4SigExtra_reducedVec_12_T; // @[primitives.scala:120:{33,54}]
assign CDom_reduced4SigExtra_reducedVec_12 = _CDom_reduced4SigExtra_reducedVec_12_T_1; // @[primitives.scala:118:30, :120:54]
wire [2:0] _CDom_reduced4SigExtra_reducedVec_13_T = _CDom_reduced4SigExtra_T_1[54:52]; // @[primitives.scala:123:15]
assign _CDom_reduced4SigExtra_reducedVec_13_T_1 = |_CDom_reduced4SigExtra_reducedVec_13_T; // @[primitives.scala:123:{15,57}]
assign CDom_reduced4SigExtra_reducedVec_13 = _CDom_reduced4SigExtra_reducedVec_13_T_1; // @[primitives.scala:118:30, :123:57]
wire [1:0] CDom_reduced4SigExtra_lo_lo_hi = {CDom_reduced4SigExtra_reducedVec_2, CDom_reduced4SigExtra_reducedVec_1}; // @[primitives.scala:118:30, :124:20]
wire [2:0] CDom_reduced4SigExtra_lo_lo = {CDom_reduced4SigExtra_lo_lo_hi, CDom_reduced4SigExtra_reducedVec_0}; // @[primitives.scala:118:30, :124:20]
wire [1:0] CDom_reduced4SigExtra_lo_hi_lo = {CDom_reduced4SigExtra_reducedVec_4, CDom_reduced4SigExtra_reducedVec_3}; // @[primitives.scala:118:30, :124:20]
wire [1:0] CDom_reduced4SigExtra_lo_hi_hi = {CDom_reduced4SigExtra_reducedVec_6, CDom_reduced4SigExtra_reducedVec_5}; // @[primitives.scala:118:30, :124:20]
wire [3:0] CDom_reduced4SigExtra_lo_hi = {CDom_reduced4SigExtra_lo_hi_hi, CDom_reduced4SigExtra_lo_hi_lo}; // @[primitives.scala:124:20]
wire [6:0] CDom_reduced4SigExtra_lo = {CDom_reduced4SigExtra_lo_hi, CDom_reduced4SigExtra_lo_lo}; // @[primitives.scala:124:20]
wire [1:0] CDom_reduced4SigExtra_hi_lo_hi = {CDom_reduced4SigExtra_reducedVec_9, CDom_reduced4SigExtra_reducedVec_8}; // @[primitives.scala:118:30, :124:20]
wire [2:0] CDom_reduced4SigExtra_hi_lo = {CDom_reduced4SigExtra_hi_lo_hi, CDom_reduced4SigExtra_reducedVec_7}; // @[primitives.scala:118:30, :124:20]
wire [1:0] CDom_reduced4SigExtra_hi_hi_lo = {CDom_reduced4SigExtra_reducedVec_11, CDom_reduced4SigExtra_reducedVec_10}; // @[primitives.scala:118:30, :124:20]
wire [1:0] CDom_reduced4SigExtra_hi_hi_hi = {CDom_reduced4SigExtra_reducedVec_13, CDom_reduced4SigExtra_reducedVec_12}; // @[primitives.scala:118:30, :124:20]
wire [3:0] CDom_reduced4SigExtra_hi_hi = {CDom_reduced4SigExtra_hi_hi_hi, CDom_reduced4SigExtra_hi_hi_lo}; // @[primitives.scala:124:20]
wire [6:0] CDom_reduced4SigExtra_hi = {CDom_reduced4SigExtra_hi_hi, CDom_reduced4SigExtra_hi_lo}; // @[primitives.scala:124:20]
wire [13:0] _CDom_reduced4SigExtra_T_2 = {CDom_reduced4SigExtra_hi, CDom_reduced4SigExtra_lo}; // @[primitives.scala:124:20]
wire [3:0] _CDom_reduced4SigExtra_T_3 = io_fromPreMul_CDom_CAlignDist_0[5:2]; // @[MulAddRecFN.scala:169:7, :223:51]
wire [3:0] _CDom_reduced4SigExtra_T_4 = ~_CDom_reduced4SigExtra_T_3; // @[primitives.scala:52:21]
wire [16:0] CDom_reduced4SigExtra_shift = $signed(17'sh10000 >>> _CDom_reduced4SigExtra_T_4); // @[primitives.scala:52:21, :76:56]
wire [12:0] _CDom_reduced4SigExtra_T_5 = CDom_reduced4SigExtra_shift[13:1]; // @[primitives.scala:76:56, :78:22]
wire [7:0] _CDom_reduced4SigExtra_T_6 = _CDom_reduced4SigExtra_T_5[7:0]; // @[primitives.scala:77:20, :78:22]
wire [3:0] _CDom_reduced4SigExtra_T_9 = _CDom_reduced4SigExtra_T_6[7:4]; // @[primitives.scala:77:20]
wire [7:0] _CDom_reduced4SigExtra_T_10 = {4'h0, _CDom_reduced4SigExtra_T_9}; // @[primitives.scala:77:20, :120:54]
wire [3:0] _CDom_reduced4SigExtra_T_11 = _CDom_reduced4SigExtra_T_6[3:0]; // @[primitives.scala:77:20]
wire [7:0] _CDom_reduced4SigExtra_T_12 = {_CDom_reduced4SigExtra_T_11, 4'h0}; // @[primitives.scala:77:20, :120:54]
wire [7:0] _CDom_reduced4SigExtra_T_14 = _CDom_reduced4SigExtra_T_12 & 8'hF0; // @[primitives.scala:77:20]
wire [7:0] _CDom_reduced4SigExtra_T_15 = _CDom_reduced4SigExtra_T_10 | _CDom_reduced4SigExtra_T_14; // @[primitives.scala:77:20]
wire [5:0] _CDom_reduced4SigExtra_T_19 = _CDom_reduced4SigExtra_T_15[7:2]; // @[primitives.scala:77:20]
wire [7:0] _CDom_reduced4SigExtra_T_20 = {2'h0, _CDom_reduced4SigExtra_T_19 & 6'h33}; // @[primitives.scala:77:20]
wire [5:0] _CDom_reduced4SigExtra_T_21 = _CDom_reduced4SigExtra_T_15[5:0]; // @[primitives.scala:77:20]
wire [7:0] _CDom_reduced4SigExtra_T_22 = {_CDom_reduced4SigExtra_T_21, 2'h0}; // @[primitives.scala:77:20]
wire [7:0] _CDom_reduced4SigExtra_T_24 = _CDom_reduced4SigExtra_T_22 & 8'hCC; // @[primitives.scala:77:20]
wire [7:0] _CDom_reduced4SigExtra_T_25 = _CDom_reduced4SigExtra_T_20 | _CDom_reduced4SigExtra_T_24; // @[primitives.scala:77:20]
wire [6:0] _CDom_reduced4SigExtra_T_29 = _CDom_reduced4SigExtra_T_25[7:1]; // @[primitives.scala:77:20]
wire [7:0] _CDom_reduced4SigExtra_T_30 = {1'h0, _CDom_reduced4SigExtra_T_29 & 7'h55}; // @[primitives.scala:77:20]
wire [6:0] _CDom_reduced4SigExtra_T_31 = _CDom_reduced4SigExtra_T_25[6:0]; // @[primitives.scala:77:20]
wire [7:0] _CDom_reduced4SigExtra_T_32 = {_CDom_reduced4SigExtra_T_31, 1'h0}; // @[primitives.scala:77:20]
wire [7:0] _CDom_reduced4SigExtra_T_34 = _CDom_reduced4SigExtra_T_32 & 8'hAA; // @[primitives.scala:77:20]
wire [7:0] _CDom_reduced4SigExtra_T_35 = _CDom_reduced4SigExtra_T_30 | _CDom_reduced4SigExtra_T_34; // @[primitives.scala:77:20]
wire [4:0] _CDom_reduced4SigExtra_T_36 = _CDom_reduced4SigExtra_T_5[12:8]; // @[primitives.scala:77:20, :78:22]
wire [3:0] _CDom_reduced4SigExtra_T_37 = _CDom_reduced4SigExtra_T_36[3:0]; // @[primitives.scala:77:20]
wire [1:0] _CDom_reduced4SigExtra_T_38 = _CDom_reduced4SigExtra_T_37[1:0]; // @[primitives.scala:77:20]
wire _CDom_reduced4SigExtra_T_39 = _CDom_reduced4SigExtra_T_38[0]; // @[primitives.scala:77:20]
wire _CDom_reduced4SigExtra_T_40 = _CDom_reduced4SigExtra_T_38[1]; // @[primitives.scala:77:20]
wire [1:0] _CDom_reduced4SigExtra_T_41 = {_CDom_reduced4SigExtra_T_39, _CDom_reduced4SigExtra_T_40}; // @[primitives.scala:77:20]
wire [1:0] _CDom_reduced4SigExtra_T_42 = _CDom_reduced4SigExtra_T_37[3:2]; // @[primitives.scala:77:20]
wire _CDom_reduced4SigExtra_T_43 = _CDom_reduced4SigExtra_T_42[0]; // @[primitives.scala:77:20]
wire _CDom_reduced4SigExtra_T_44 = _CDom_reduced4SigExtra_T_42[1]; // @[primitives.scala:77:20]
wire [1:0] _CDom_reduced4SigExtra_T_45 = {_CDom_reduced4SigExtra_T_43, _CDom_reduced4SigExtra_T_44}; // @[primitives.scala:77:20]
wire [3:0] _CDom_reduced4SigExtra_T_46 = {_CDom_reduced4SigExtra_T_41, _CDom_reduced4SigExtra_T_45}; // @[primitives.scala:77:20]
wire _CDom_reduced4SigExtra_T_47 = _CDom_reduced4SigExtra_T_36[4]; // @[primitives.scala:77:20]
wire [4:0] _CDom_reduced4SigExtra_T_48 = {_CDom_reduced4SigExtra_T_46, _CDom_reduced4SigExtra_T_47}; // @[primitives.scala:77:20]
wire [12:0] _CDom_reduced4SigExtra_T_49 = {_CDom_reduced4SigExtra_T_35, _CDom_reduced4SigExtra_T_48}; // @[primitives.scala:77:20]
wire [13:0] _CDom_reduced4SigExtra_T_50 = {1'h0, _CDom_reduced4SigExtra_T_2[12:0] & _CDom_reduced4SigExtra_T_49}; // @[primitives.scala:77:20, :124:20]
wire CDom_reduced4SigExtra = |_CDom_reduced4SigExtra_T_50; // @[MulAddRecFN.scala:222:72, :223:73]
wire [54:0] _CDom_sig_T = CDom_mainSig[57:3]; // @[MulAddRecFN.scala:219:56, :225:25]
wire [2:0] _CDom_sig_T_1 = CDom_mainSig[2:0]; // @[MulAddRecFN.scala:219:56, :226:25]
wire _CDom_sig_T_2 = |_CDom_sig_T_1; // @[MulAddRecFN.scala:226:{25,32}]
wire _CDom_sig_T_3 = _CDom_sig_T_2 | CDom_reduced4SigExtra; // @[MulAddRecFN.scala:223:73, :226:{32,36}]
wire _CDom_sig_T_4 = _CDom_sig_T_3 | CDom_absSigSumExtra; // @[MulAddRecFN.scala:214:12, :226:{36,61}]
wire [55:0] CDom_sig = {_CDom_sig_T, _CDom_sig_T_4}; // @[MulAddRecFN.scala:225:{12,25}, :226:61]
wire notCDom_signSigSum = sigSum[109]; // @[MulAddRecFN.scala:192:12, :232:36]
wire [108:0] _notCDom_absSigSum_T = sigSum[108:0]; // @[MulAddRecFN.scala:192:12, :235:20]
wire [108:0] _notCDom_absSigSum_T_2 = sigSum[108:0]; // @[MulAddRecFN.scala:192:12, :235:20, :236:19]
wire [108:0] _notCDom_absSigSum_T_1 = ~_notCDom_absSigSum_T; // @[MulAddRecFN.scala:235:{13,20}]
wire [109:0] _notCDom_absSigSum_T_3 = {1'h0, _notCDom_absSigSum_T_2} + {109'h0, io_fromPreMul_doSubMags_0}; // @[MulAddRecFN.scala:169:7, :236:{19,41}]
wire [108:0] _notCDom_absSigSum_T_4 = _notCDom_absSigSum_T_3[108:0]; // @[MulAddRecFN.scala:236:41]
wire [108:0] notCDom_absSigSum = notCDom_signSigSum ? _notCDom_absSigSum_T_1 : _notCDom_absSigSum_T_4; // @[MulAddRecFN.scala:232:36, :234:12, :235:13, :236:41]
wire _notCDom_reduced2AbsSigSum_reducedVec_0_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_1_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_2_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_3_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_4_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_5_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_6_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_7_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_8_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_9_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_10_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_11_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_12_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_13_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_14_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_15_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_16_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_17_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_18_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_19_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_20_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_21_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_22_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_23_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_24_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_25_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_26_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_27_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_28_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_29_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_30_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_31_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_32_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_33_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_34_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_35_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_36_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_37_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_38_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_39_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_40_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_41_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_42_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_43_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_44_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_45_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_46_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_47_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_48_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_49_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_50_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_51_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_52_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_53_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_54_T_1; // @[primitives.scala:106:57]
wire notCDom_reduced2AbsSigSum_reducedVec_0; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_1; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_2; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_3; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_4; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_5; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_6; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_7; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_8; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_9; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_10; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_11; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_12; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_13; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_14; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_15; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_16; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_17; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_18; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_19; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_20; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_21; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_22; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_23; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_24; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_25; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_26; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_27; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_28; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_29; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_30; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_31; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_32; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_33; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_34; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_35; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_36; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_37; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_38; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_39; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_40; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_41; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_42; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_43; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_44; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_45; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_46; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_47; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_48; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_49; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_50; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_51; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_52; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_53; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_54; // @[primitives.scala:101:30]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_0_T = notCDom_absSigSum[1:0]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_0_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_0_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_0 = _notCDom_reduced2AbsSigSum_reducedVec_0_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_1_T = notCDom_absSigSum[3:2]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_1_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_1_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_1 = _notCDom_reduced2AbsSigSum_reducedVec_1_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_2_T = notCDom_absSigSum[5:4]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_2_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_2_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_2 = _notCDom_reduced2AbsSigSum_reducedVec_2_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_3_T = notCDom_absSigSum[7:6]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_3_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_3_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_3 = _notCDom_reduced2AbsSigSum_reducedVec_3_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_4_T = notCDom_absSigSum[9:8]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_4_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_4_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_4 = _notCDom_reduced2AbsSigSum_reducedVec_4_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_5_T = notCDom_absSigSum[11:10]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_5_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_5_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_5 = _notCDom_reduced2AbsSigSum_reducedVec_5_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_6_T = notCDom_absSigSum[13:12]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_6_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_6_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_6 = _notCDom_reduced2AbsSigSum_reducedVec_6_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_7_T = notCDom_absSigSum[15:14]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_7_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_7_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_7 = _notCDom_reduced2AbsSigSum_reducedVec_7_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_8_T = notCDom_absSigSum[17:16]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_8_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_8_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_8 = _notCDom_reduced2AbsSigSum_reducedVec_8_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_9_T = notCDom_absSigSum[19:18]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_9_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_9_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_9 = _notCDom_reduced2AbsSigSum_reducedVec_9_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_10_T = notCDom_absSigSum[21:20]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_10_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_10_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_10 = _notCDom_reduced2AbsSigSum_reducedVec_10_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_11_T = notCDom_absSigSum[23:22]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_11_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_11_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_11 = _notCDom_reduced2AbsSigSum_reducedVec_11_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_12_T = notCDom_absSigSum[25:24]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_12_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_12_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_12 = _notCDom_reduced2AbsSigSum_reducedVec_12_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_13_T = notCDom_absSigSum[27:26]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_13_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_13_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_13 = _notCDom_reduced2AbsSigSum_reducedVec_13_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_14_T = notCDom_absSigSum[29:28]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_14_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_14_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_14 = _notCDom_reduced2AbsSigSum_reducedVec_14_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_15_T = notCDom_absSigSum[31:30]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_15_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_15_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_15 = _notCDom_reduced2AbsSigSum_reducedVec_15_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_16_T = notCDom_absSigSum[33:32]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_16_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_16_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_16 = _notCDom_reduced2AbsSigSum_reducedVec_16_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_17_T = notCDom_absSigSum[35:34]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_17_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_17_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_17 = _notCDom_reduced2AbsSigSum_reducedVec_17_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_18_T = notCDom_absSigSum[37:36]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_18_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_18_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_18 = _notCDom_reduced2AbsSigSum_reducedVec_18_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_19_T = notCDom_absSigSum[39:38]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_19_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_19_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_19 = _notCDom_reduced2AbsSigSum_reducedVec_19_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_20_T = notCDom_absSigSum[41:40]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_20_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_20_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_20 = _notCDom_reduced2AbsSigSum_reducedVec_20_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_21_T = notCDom_absSigSum[43:42]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_21_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_21_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_21 = _notCDom_reduced2AbsSigSum_reducedVec_21_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_22_T = notCDom_absSigSum[45:44]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_22_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_22_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_22 = _notCDom_reduced2AbsSigSum_reducedVec_22_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_23_T = notCDom_absSigSum[47:46]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_23_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_23_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_23 = _notCDom_reduced2AbsSigSum_reducedVec_23_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_24_T = notCDom_absSigSum[49:48]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_24_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_24_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_24 = _notCDom_reduced2AbsSigSum_reducedVec_24_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_25_T = notCDom_absSigSum[51:50]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_25_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_25_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_25 = _notCDom_reduced2AbsSigSum_reducedVec_25_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_26_T = notCDom_absSigSum[53:52]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_26_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_26_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_26 = _notCDom_reduced2AbsSigSum_reducedVec_26_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_27_T = notCDom_absSigSum[55:54]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_27_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_27_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_27 = _notCDom_reduced2AbsSigSum_reducedVec_27_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_28_T = notCDom_absSigSum[57:56]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_28_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_28_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_28 = _notCDom_reduced2AbsSigSum_reducedVec_28_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_29_T = notCDom_absSigSum[59:58]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_29_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_29_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_29 = _notCDom_reduced2AbsSigSum_reducedVec_29_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_30_T = notCDom_absSigSum[61:60]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_30_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_30_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_30 = _notCDom_reduced2AbsSigSum_reducedVec_30_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_31_T = notCDom_absSigSum[63:62]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_31_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_31_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_31 = _notCDom_reduced2AbsSigSum_reducedVec_31_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_32_T = notCDom_absSigSum[65:64]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_32_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_32_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_32 = _notCDom_reduced2AbsSigSum_reducedVec_32_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_33_T = notCDom_absSigSum[67:66]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_33_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_33_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_33 = _notCDom_reduced2AbsSigSum_reducedVec_33_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_34_T = notCDom_absSigSum[69:68]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_34_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_34_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_34 = _notCDom_reduced2AbsSigSum_reducedVec_34_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_35_T = notCDom_absSigSum[71:70]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_35_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_35_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_35 = _notCDom_reduced2AbsSigSum_reducedVec_35_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_36_T = notCDom_absSigSum[73:72]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_36_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_36_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_36 = _notCDom_reduced2AbsSigSum_reducedVec_36_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_37_T = notCDom_absSigSum[75:74]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_37_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_37_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_37 = _notCDom_reduced2AbsSigSum_reducedVec_37_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_38_T = notCDom_absSigSum[77:76]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_38_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_38_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_38 = _notCDom_reduced2AbsSigSum_reducedVec_38_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_39_T = notCDom_absSigSum[79:78]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_39_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_39_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_39 = _notCDom_reduced2AbsSigSum_reducedVec_39_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_40_T = notCDom_absSigSum[81:80]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_40_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_40_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_40 = _notCDom_reduced2AbsSigSum_reducedVec_40_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_41_T = notCDom_absSigSum[83:82]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_41_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_41_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_41 = _notCDom_reduced2AbsSigSum_reducedVec_41_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_42_T = notCDom_absSigSum[85:84]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_42_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_42_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_42 = _notCDom_reduced2AbsSigSum_reducedVec_42_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_43_T = notCDom_absSigSum[87:86]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_43_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_43_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_43 = _notCDom_reduced2AbsSigSum_reducedVec_43_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_44_T = notCDom_absSigSum[89:88]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_44_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_44_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_44 = _notCDom_reduced2AbsSigSum_reducedVec_44_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_45_T = notCDom_absSigSum[91:90]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_45_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_45_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_45 = _notCDom_reduced2AbsSigSum_reducedVec_45_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_46_T = notCDom_absSigSum[93:92]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_46_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_46_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_46 = _notCDom_reduced2AbsSigSum_reducedVec_46_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_47_T = notCDom_absSigSum[95:94]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_47_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_47_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_47 = _notCDom_reduced2AbsSigSum_reducedVec_47_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_48_T = notCDom_absSigSum[97:96]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_48_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_48_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_48 = _notCDom_reduced2AbsSigSum_reducedVec_48_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_49_T = notCDom_absSigSum[99:98]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_49_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_49_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_49 = _notCDom_reduced2AbsSigSum_reducedVec_49_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_50_T = notCDom_absSigSum[101:100]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_50_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_50_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_50 = _notCDom_reduced2AbsSigSum_reducedVec_50_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_51_T = notCDom_absSigSum[103:102]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_51_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_51_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_51 = _notCDom_reduced2AbsSigSum_reducedVec_51_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_52_T = notCDom_absSigSum[105:104]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_52_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_52_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_52 = _notCDom_reduced2AbsSigSum_reducedVec_52_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_53_T = notCDom_absSigSum[107:106]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_53_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_53_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_53 = _notCDom_reduced2AbsSigSum_reducedVec_53_T_1; // @[primitives.scala:101:30, :103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_54_T = notCDom_absSigSum[108]; // @[primitives.scala:106:15]
assign _notCDom_reduced2AbsSigSum_reducedVec_54_T_1 = _notCDom_reduced2AbsSigSum_reducedVec_54_T; // @[primitives.scala:106:{15,57}]
assign notCDom_reduced2AbsSigSum_reducedVec_54 = _notCDom_reduced2AbsSigSum_reducedVec_54_T_1; // @[primitives.scala:101:30, :106:57]
wire [1:0] notCDom_reduced2AbsSigSum_lo_lo_lo_lo_hi = {notCDom_reduced2AbsSigSum_reducedVec_2, notCDom_reduced2AbsSigSum_reducedVec_1}; // @[primitives.scala:101:30, :107:20]
wire [2:0] notCDom_reduced2AbsSigSum_lo_lo_lo_lo = {notCDom_reduced2AbsSigSum_lo_lo_lo_lo_hi, notCDom_reduced2AbsSigSum_reducedVec_0}; // @[primitives.scala:101:30, :107:20]
wire [1:0] notCDom_reduced2AbsSigSum_lo_lo_lo_hi_hi = {notCDom_reduced2AbsSigSum_reducedVec_5, notCDom_reduced2AbsSigSum_reducedVec_4}; // @[primitives.scala:101:30, :107:20]
wire [2:0] notCDom_reduced2AbsSigSum_lo_lo_lo_hi = {notCDom_reduced2AbsSigSum_lo_lo_lo_hi_hi, notCDom_reduced2AbsSigSum_reducedVec_3}; // @[primitives.scala:101:30, :107:20]
wire [5:0] notCDom_reduced2AbsSigSum_lo_lo_lo = {notCDom_reduced2AbsSigSum_lo_lo_lo_hi, notCDom_reduced2AbsSigSum_lo_lo_lo_lo}; // @[primitives.scala:107:20]
wire [1:0] notCDom_reduced2AbsSigSum_lo_lo_hi_lo_hi = {notCDom_reduced2AbsSigSum_reducedVec_8, notCDom_reduced2AbsSigSum_reducedVec_7}; // @[primitives.scala:101:30, :107:20]
wire [2:0] notCDom_reduced2AbsSigSum_lo_lo_hi_lo = {notCDom_reduced2AbsSigSum_lo_lo_hi_lo_hi, notCDom_reduced2AbsSigSum_reducedVec_6}; // @[primitives.scala:101:30, :107:20]
wire [1:0] notCDom_reduced2AbsSigSum_lo_lo_hi_hi_lo = {notCDom_reduced2AbsSigSum_reducedVec_10, notCDom_reduced2AbsSigSum_reducedVec_9}; // @[primitives.scala:101:30, :107:20]
wire [1:0] notCDom_reduced2AbsSigSum_lo_lo_hi_hi_hi = {notCDom_reduced2AbsSigSum_reducedVec_12, notCDom_reduced2AbsSigSum_reducedVec_11}; // @[primitives.scala:101:30, :107:20]
wire [3:0] notCDom_reduced2AbsSigSum_lo_lo_hi_hi = {notCDom_reduced2AbsSigSum_lo_lo_hi_hi_hi, notCDom_reduced2AbsSigSum_lo_lo_hi_hi_lo}; // @[primitives.scala:107:20]
wire [6:0] notCDom_reduced2AbsSigSum_lo_lo_hi = {notCDom_reduced2AbsSigSum_lo_lo_hi_hi, notCDom_reduced2AbsSigSum_lo_lo_hi_lo}; // @[primitives.scala:107:20]
wire [12:0] notCDom_reduced2AbsSigSum_lo_lo = {notCDom_reduced2AbsSigSum_lo_lo_hi, notCDom_reduced2AbsSigSum_lo_lo_lo}; // @[primitives.scala:107:20]
wire [1:0] notCDom_reduced2AbsSigSum_lo_hi_lo_lo_hi = {notCDom_reduced2AbsSigSum_reducedVec_15, notCDom_reduced2AbsSigSum_reducedVec_14}; // @[primitives.scala:101:30, :107:20]
wire [2:0] notCDom_reduced2AbsSigSum_lo_hi_lo_lo = {notCDom_reduced2AbsSigSum_lo_hi_lo_lo_hi, notCDom_reduced2AbsSigSum_reducedVec_13}; // @[primitives.scala:101:30, :107:20]
wire [1:0] notCDom_reduced2AbsSigSum_lo_hi_lo_hi_lo = {notCDom_reduced2AbsSigSum_reducedVec_17, notCDom_reduced2AbsSigSum_reducedVec_16}; // @[primitives.scala:101:30, :107:20]
wire [1:0] notCDom_reduced2AbsSigSum_lo_hi_lo_hi_hi = {notCDom_reduced2AbsSigSum_reducedVec_19, notCDom_reduced2AbsSigSum_reducedVec_18}; // @[primitives.scala:101:30, :107:20]
wire [3:0] notCDom_reduced2AbsSigSum_lo_hi_lo_hi = {notCDom_reduced2AbsSigSum_lo_hi_lo_hi_hi, notCDom_reduced2AbsSigSum_lo_hi_lo_hi_lo}; // @[primitives.scala:107:20]
wire [6:0] notCDom_reduced2AbsSigSum_lo_hi_lo = {notCDom_reduced2AbsSigSum_lo_hi_lo_hi, notCDom_reduced2AbsSigSum_lo_hi_lo_lo}; // @[primitives.scala:107:20]
wire [1:0] notCDom_reduced2AbsSigSum_lo_hi_hi_lo_hi = {notCDom_reduced2AbsSigSum_reducedVec_22, notCDom_reduced2AbsSigSum_reducedVec_21}; // @[primitives.scala:101:30, :107:20]
wire [2:0] notCDom_reduced2AbsSigSum_lo_hi_hi_lo = {notCDom_reduced2AbsSigSum_lo_hi_hi_lo_hi, notCDom_reduced2AbsSigSum_reducedVec_20}; // @[primitives.scala:101:30, :107:20]
wire [1:0] notCDom_reduced2AbsSigSum_lo_hi_hi_hi_lo = {notCDom_reduced2AbsSigSum_reducedVec_24, notCDom_reduced2AbsSigSum_reducedVec_23}; // @[primitives.scala:101:30, :107:20]
wire [1:0] notCDom_reduced2AbsSigSum_lo_hi_hi_hi_hi = {notCDom_reduced2AbsSigSum_reducedVec_26, notCDom_reduced2AbsSigSum_reducedVec_25}; // @[primitives.scala:101:30, :107:20]
wire [3:0] notCDom_reduced2AbsSigSum_lo_hi_hi_hi = {notCDom_reduced2AbsSigSum_lo_hi_hi_hi_hi, notCDom_reduced2AbsSigSum_lo_hi_hi_hi_lo}; // @[primitives.scala:107:20]
wire [6:0] notCDom_reduced2AbsSigSum_lo_hi_hi = {notCDom_reduced2AbsSigSum_lo_hi_hi_hi, notCDom_reduced2AbsSigSum_lo_hi_hi_lo}; // @[primitives.scala:107:20]
wire [13:0] notCDom_reduced2AbsSigSum_lo_hi = {notCDom_reduced2AbsSigSum_lo_hi_hi, notCDom_reduced2AbsSigSum_lo_hi_lo}; // @[primitives.scala:107:20]
wire [26:0] notCDom_reduced2AbsSigSum_lo = {notCDom_reduced2AbsSigSum_lo_hi, notCDom_reduced2AbsSigSum_lo_lo}; // @[primitives.scala:107:20]
wire [1:0] notCDom_reduced2AbsSigSum_hi_lo_lo_lo_hi = {notCDom_reduced2AbsSigSum_reducedVec_29, notCDom_reduced2AbsSigSum_reducedVec_28}; // @[primitives.scala:101:30, :107:20]
wire [2:0] notCDom_reduced2AbsSigSum_hi_lo_lo_lo = {notCDom_reduced2AbsSigSum_hi_lo_lo_lo_hi, notCDom_reduced2AbsSigSum_reducedVec_27}; // @[primitives.scala:101:30, :107:20]
wire [1:0] notCDom_reduced2AbsSigSum_hi_lo_lo_hi_lo = {notCDom_reduced2AbsSigSum_reducedVec_31, notCDom_reduced2AbsSigSum_reducedVec_30}; // @[primitives.scala:101:30, :107:20]
wire [1:0] notCDom_reduced2AbsSigSum_hi_lo_lo_hi_hi = {notCDom_reduced2AbsSigSum_reducedVec_33, notCDom_reduced2AbsSigSum_reducedVec_32}; // @[primitives.scala:101:30, :107:20]
wire [3:0] notCDom_reduced2AbsSigSum_hi_lo_lo_hi = {notCDom_reduced2AbsSigSum_hi_lo_lo_hi_hi, notCDom_reduced2AbsSigSum_hi_lo_lo_hi_lo}; // @[primitives.scala:107:20]
wire [6:0] notCDom_reduced2AbsSigSum_hi_lo_lo = {notCDom_reduced2AbsSigSum_hi_lo_lo_hi, notCDom_reduced2AbsSigSum_hi_lo_lo_lo}; // @[primitives.scala:107:20]
wire [1:0] notCDom_reduced2AbsSigSum_hi_lo_hi_lo_hi = {notCDom_reduced2AbsSigSum_reducedVec_36, notCDom_reduced2AbsSigSum_reducedVec_35}; // @[primitives.scala:101:30, :107:20]
wire [2:0] notCDom_reduced2AbsSigSum_hi_lo_hi_lo = {notCDom_reduced2AbsSigSum_hi_lo_hi_lo_hi, notCDom_reduced2AbsSigSum_reducedVec_34}; // @[primitives.scala:101:30, :107:20]
wire [1:0] notCDom_reduced2AbsSigSum_hi_lo_hi_hi_lo = {notCDom_reduced2AbsSigSum_reducedVec_38, notCDom_reduced2AbsSigSum_reducedVec_37}; // @[primitives.scala:101:30, :107:20]
wire [1:0] notCDom_reduced2AbsSigSum_hi_lo_hi_hi_hi = {notCDom_reduced2AbsSigSum_reducedVec_40, notCDom_reduced2AbsSigSum_reducedVec_39}; // @[primitives.scala:101:30, :107:20]
wire [3:0] notCDom_reduced2AbsSigSum_hi_lo_hi_hi = {notCDom_reduced2AbsSigSum_hi_lo_hi_hi_hi, notCDom_reduced2AbsSigSum_hi_lo_hi_hi_lo}; // @[primitives.scala:107:20]
wire [6:0] notCDom_reduced2AbsSigSum_hi_lo_hi = {notCDom_reduced2AbsSigSum_hi_lo_hi_hi, notCDom_reduced2AbsSigSum_hi_lo_hi_lo}; // @[primitives.scala:107:20]
wire [13:0] notCDom_reduced2AbsSigSum_hi_lo = {notCDom_reduced2AbsSigSum_hi_lo_hi, notCDom_reduced2AbsSigSum_hi_lo_lo}; // @[primitives.scala:107:20]
wire [1:0] notCDom_reduced2AbsSigSum_hi_hi_lo_lo_hi = {notCDom_reduced2AbsSigSum_reducedVec_43, notCDom_reduced2AbsSigSum_reducedVec_42}; // @[primitives.scala:101:30, :107:20]
wire [2:0] notCDom_reduced2AbsSigSum_hi_hi_lo_lo = {notCDom_reduced2AbsSigSum_hi_hi_lo_lo_hi, notCDom_reduced2AbsSigSum_reducedVec_41}; // @[primitives.scala:101:30, :107:20]
wire [1:0] notCDom_reduced2AbsSigSum_hi_hi_lo_hi_lo = {notCDom_reduced2AbsSigSum_reducedVec_45, notCDom_reduced2AbsSigSum_reducedVec_44}; // @[primitives.scala:101:30, :107:20]
wire [1:0] notCDom_reduced2AbsSigSum_hi_hi_lo_hi_hi = {notCDom_reduced2AbsSigSum_reducedVec_47, notCDom_reduced2AbsSigSum_reducedVec_46}; // @[primitives.scala:101:30, :107:20]
wire [3:0] notCDom_reduced2AbsSigSum_hi_hi_lo_hi = {notCDom_reduced2AbsSigSum_hi_hi_lo_hi_hi, notCDom_reduced2AbsSigSum_hi_hi_lo_hi_lo}; // @[primitives.scala:107:20]
wire [6:0] notCDom_reduced2AbsSigSum_hi_hi_lo = {notCDom_reduced2AbsSigSum_hi_hi_lo_hi, notCDom_reduced2AbsSigSum_hi_hi_lo_lo}; // @[primitives.scala:107:20]
wire [1:0] notCDom_reduced2AbsSigSum_hi_hi_hi_lo_hi = {notCDom_reduced2AbsSigSum_reducedVec_50, notCDom_reduced2AbsSigSum_reducedVec_49}; // @[primitives.scala:101:30, :107:20]
wire [2:0] notCDom_reduced2AbsSigSum_hi_hi_hi_lo = {notCDom_reduced2AbsSigSum_hi_hi_hi_lo_hi, notCDom_reduced2AbsSigSum_reducedVec_48}; // @[primitives.scala:101:30, :107:20]
wire [1:0] notCDom_reduced2AbsSigSum_hi_hi_hi_hi_lo = {notCDom_reduced2AbsSigSum_reducedVec_52, notCDom_reduced2AbsSigSum_reducedVec_51}; // @[primitives.scala:101:30, :107:20]
wire [1:0] notCDom_reduced2AbsSigSum_hi_hi_hi_hi_hi = {notCDom_reduced2AbsSigSum_reducedVec_54, notCDom_reduced2AbsSigSum_reducedVec_53}; // @[primitives.scala:101:30, :107:20]
wire [3:0] notCDom_reduced2AbsSigSum_hi_hi_hi_hi = {notCDom_reduced2AbsSigSum_hi_hi_hi_hi_hi, notCDom_reduced2AbsSigSum_hi_hi_hi_hi_lo}; // @[primitives.scala:107:20]
wire [6:0] notCDom_reduced2AbsSigSum_hi_hi_hi = {notCDom_reduced2AbsSigSum_hi_hi_hi_hi, notCDom_reduced2AbsSigSum_hi_hi_hi_lo}; // @[primitives.scala:107:20]
wire [13:0] notCDom_reduced2AbsSigSum_hi_hi = {notCDom_reduced2AbsSigSum_hi_hi_hi, notCDom_reduced2AbsSigSum_hi_hi_lo}; // @[primitives.scala:107:20]
wire [27:0] notCDom_reduced2AbsSigSum_hi = {notCDom_reduced2AbsSigSum_hi_hi, notCDom_reduced2AbsSigSum_hi_lo}; // @[primitives.scala:107:20]
wire [54:0] notCDom_reduced2AbsSigSum = {notCDom_reduced2AbsSigSum_hi, notCDom_reduced2AbsSigSum_lo}; // @[primitives.scala:107:20]
wire _notCDom_normDistReduced2_T = notCDom_reduced2AbsSigSum[0]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_1 = notCDom_reduced2AbsSigSum[1]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_2 = notCDom_reduced2AbsSigSum[2]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_3 = notCDom_reduced2AbsSigSum[3]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_4 = notCDom_reduced2AbsSigSum[4]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_5 = notCDom_reduced2AbsSigSum[5]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_6 = notCDom_reduced2AbsSigSum[6]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_7 = notCDom_reduced2AbsSigSum[7]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_8 = notCDom_reduced2AbsSigSum[8]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_9 = notCDom_reduced2AbsSigSum[9]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_10 = notCDom_reduced2AbsSigSum[10]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_11 = notCDom_reduced2AbsSigSum[11]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_12 = notCDom_reduced2AbsSigSum[12]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_13 = notCDom_reduced2AbsSigSum[13]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_14 = notCDom_reduced2AbsSigSum[14]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_15 = notCDom_reduced2AbsSigSum[15]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_16 = notCDom_reduced2AbsSigSum[16]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_17 = notCDom_reduced2AbsSigSum[17]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_18 = notCDom_reduced2AbsSigSum[18]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_19 = notCDom_reduced2AbsSigSum[19]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_20 = notCDom_reduced2AbsSigSum[20]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_21 = notCDom_reduced2AbsSigSum[21]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_22 = notCDom_reduced2AbsSigSum[22]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_23 = notCDom_reduced2AbsSigSum[23]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_24 = notCDom_reduced2AbsSigSum[24]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_25 = notCDom_reduced2AbsSigSum[25]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_26 = notCDom_reduced2AbsSigSum[26]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_27 = notCDom_reduced2AbsSigSum[27]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_28 = notCDom_reduced2AbsSigSum[28]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_29 = notCDom_reduced2AbsSigSum[29]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_30 = notCDom_reduced2AbsSigSum[30]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_31 = notCDom_reduced2AbsSigSum[31]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_32 = notCDom_reduced2AbsSigSum[32]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_33 = notCDom_reduced2AbsSigSum[33]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_34 = notCDom_reduced2AbsSigSum[34]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_35 = notCDom_reduced2AbsSigSum[35]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_36 = notCDom_reduced2AbsSigSum[36]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_37 = notCDom_reduced2AbsSigSum[37]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_38 = notCDom_reduced2AbsSigSum[38]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_39 = notCDom_reduced2AbsSigSum[39]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_40 = notCDom_reduced2AbsSigSum[40]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_41 = notCDom_reduced2AbsSigSum[41]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_42 = notCDom_reduced2AbsSigSum[42]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_43 = notCDom_reduced2AbsSigSum[43]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_44 = notCDom_reduced2AbsSigSum[44]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_45 = notCDom_reduced2AbsSigSum[45]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_46 = notCDom_reduced2AbsSigSum[46]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_47 = notCDom_reduced2AbsSigSum[47]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_48 = notCDom_reduced2AbsSigSum[48]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_49 = notCDom_reduced2AbsSigSum[49]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_50 = notCDom_reduced2AbsSigSum[50]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_51 = notCDom_reduced2AbsSigSum[51]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_52 = notCDom_reduced2AbsSigSum[52]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_53 = notCDom_reduced2AbsSigSum[53]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_54 = notCDom_reduced2AbsSigSum[54]; // @[primitives.scala:91:52, :107:20]
wire [5:0] _notCDom_normDistReduced2_T_55 = _notCDom_normDistReduced2_T_1 ? 6'h35 : 6'h36; // @[Mux.scala:50:70]
wire [5:0] _notCDom_normDistReduced2_T_56 = _notCDom_normDistReduced2_T_2 ? 6'h34 : _notCDom_normDistReduced2_T_55; // @[Mux.scala:50:70]
wire [5:0] _notCDom_normDistReduced2_T_57 = _notCDom_normDistReduced2_T_3 ? 6'h33 : _notCDom_normDistReduced2_T_56; // @[Mux.scala:50:70]
wire [5:0] _notCDom_normDistReduced2_T_58 = _notCDom_normDistReduced2_T_4 ? 6'h32 : _notCDom_normDistReduced2_T_57; // @[Mux.scala:50:70]
wire [5:0] _notCDom_normDistReduced2_T_59 = _notCDom_normDistReduced2_T_5 ? 6'h31 : _notCDom_normDistReduced2_T_58; // @[Mux.scala:50:70]
wire [5:0] _notCDom_normDistReduced2_T_60 = _notCDom_normDistReduced2_T_6 ? 6'h30 : _notCDom_normDistReduced2_T_59; // @[Mux.scala:50:70]
wire [5:0] _notCDom_normDistReduced2_T_61 = _notCDom_normDistReduced2_T_7 ? 6'h2F : _notCDom_normDistReduced2_T_60; // @[Mux.scala:50:70]
wire [5:0] _notCDom_normDistReduced2_T_62 = _notCDom_normDistReduced2_T_8 ? 6'h2E : _notCDom_normDistReduced2_T_61; // @[Mux.scala:50:70]
wire [5:0] _notCDom_normDistReduced2_T_63 = _notCDom_normDistReduced2_T_9 ? 6'h2D : _notCDom_normDistReduced2_T_62; // @[Mux.scala:50:70]
wire [5:0] _notCDom_normDistReduced2_T_64 = _notCDom_normDistReduced2_T_10 ? 6'h2C : _notCDom_normDistReduced2_T_63; // @[Mux.scala:50:70]
wire [5:0] _notCDom_normDistReduced2_T_65 = _notCDom_normDistReduced2_T_11 ? 6'h2B : _notCDom_normDistReduced2_T_64; // @[Mux.scala:50:70]
wire [5:0] _notCDom_normDistReduced2_T_66 = _notCDom_normDistReduced2_T_12 ? 6'h2A : _notCDom_normDistReduced2_T_65; // @[Mux.scala:50:70]
wire [5:0] _notCDom_normDistReduced2_T_67 = _notCDom_normDistReduced2_T_13 ? 6'h29 : _notCDom_normDistReduced2_T_66; // @[Mux.scala:50:70]
wire [5:0] _notCDom_normDistReduced2_T_68 = _notCDom_normDistReduced2_T_14 ? 6'h28 : _notCDom_normDistReduced2_T_67; // @[Mux.scala:50:70]
wire [5:0] _notCDom_normDistReduced2_T_69 = _notCDom_normDistReduced2_T_15 ? 6'h27 : _notCDom_normDistReduced2_T_68; // @[Mux.scala:50:70]
wire [5:0] _notCDom_normDistReduced2_T_70 = _notCDom_normDistReduced2_T_16 ? 6'h26 : _notCDom_normDistReduced2_T_69; // @[Mux.scala:50:70]
wire [5:0] _notCDom_normDistReduced2_T_71 = _notCDom_normDistReduced2_T_17 ? 6'h25 : _notCDom_normDistReduced2_T_70; // @[Mux.scala:50:70]
wire [5:0] _notCDom_normDistReduced2_T_72 = _notCDom_normDistReduced2_T_18 ? 6'h24 : _notCDom_normDistReduced2_T_71; // @[Mux.scala:50:70]
wire [5:0] _notCDom_normDistReduced2_T_73 = _notCDom_normDistReduced2_T_19 ? 6'h23 : _notCDom_normDistReduced2_T_72; // @[Mux.scala:50:70]
wire [5:0] _notCDom_normDistReduced2_T_74 = _notCDom_normDistReduced2_T_20 ? 6'h22 : _notCDom_normDistReduced2_T_73; // @[Mux.scala:50:70]
wire [5:0] _notCDom_normDistReduced2_T_75 = _notCDom_normDistReduced2_T_21 ? 6'h21 : _notCDom_normDistReduced2_T_74; // @[Mux.scala:50:70]
wire [5:0] _notCDom_normDistReduced2_T_76 = _notCDom_normDistReduced2_T_22 ? 6'h20 : _notCDom_normDistReduced2_T_75; // @[Mux.scala:50:70]
wire [5:0] _notCDom_normDistReduced2_T_77 = _notCDom_normDistReduced2_T_23 ? 6'h1F : _notCDom_normDistReduced2_T_76; // @[Mux.scala:50:70]
wire [5:0] _notCDom_normDistReduced2_T_78 = _notCDom_normDistReduced2_T_24 ? 6'h1E : _notCDom_normDistReduced2_T_77; // @[Mux.scala:50:70]
wire [5:0] _notCDom_normDistReduced2_T_79 = _notCDom_normDistReduced2_T_25 ? 6'h1D : _notCDom_normDistReduced2_T_78; // @[Mux.scala:50:70]
wire [5:0] _notCDom_normDistReduced2_T_80 = _notCDom_normDistReduced2_T_26 ? 6'h1C : _notCDom_normDistReduced2_T_79; // @[Mux.scala:50:70]
wire [5:0] _notCDom_normDistReduced2_T_81 = _notCDom_normDistReduced2_T_27 ? 6'h1B : _notCDom_normDistReduced2_T_80; // @[Mux.scala:50:70]
wire [5:0] _notCDom_normDistReduced2_T_82 = _notCDom_normDistReduced2_T_28 ? 6'h1A : _notCDom_normDistReduced2_T_81; // @[Mux.scala:50:70]
wire [5:0] _notCDom_normDistReduced2_T_83 = _notCDom_normDistReduced2_T_29 ? 6'h19 : _notCDom_normDistReduced2_T_82; // @[Mux.scala:50:70]
wire [5:0] _notCDom_normDistReduced2_T_84 = _notCDom_normDistReduced2_T_30 ? 6'h18 : _notCDom_normDistReduced2_T_83; // @[Mux.scala:50:70]
wire [5:0] _notCDom_normDistReduced2_T_85 = _notCDom_normDistReduced2_T_31 ? 6'h17 : _notCDom_normDistReduced2_T_84; // @[Mux.scala:50:70]
wire [5:0] _notCDom_normDistReduced2_T_86 = _notCDom_normDistReduced2_T_32 ? 6'h16 : _notCDom_normDistReduced2_T_85; // @[Mux.scala:50:70]
wire [5:0] _notCDom_normDistReduced2_T_87 = _notCDom_normDistReduced2_T_33 ? 6'h15 : _notCDom_normDistReduced2_T_86; // @[Mux.scala:50:70]
wire [5:0] _notCDom_normDistReduced2_T_88 = _notCDom_normDistReduced2_T_34 ? 6'h14 : _notCDom_normDistReduced2_T_87; // @[Mux.scala:50:70]
wire [5:0] _notCDom_normDistReduced2_T_89 = _notCDom_normDistReduced2_T_35 ? 6'h13 : _notCDom_normDistReduced2_T_88; // @[Mux.scala:50:70]
wire [5:0] _notCDom_normDistReduced2_T_90 = _notCDom_normDistReduced2_T_36 ? 6'h12 : _notCDom_normDistReduced2_T_89; // @[Mux.scala:50:70]
wire [5:0] _notCDom_normDistReduced2_T_91 = _notCDom_normDistReduced2_T_37 ? 6'h11 : _notCDom_normDistReduced2_T_90; // @[Mux.scala:50:70]
wire [5:0] _notCDom_normDistReduced2_T_92 = _notCDom_normDistReduced2_T_38 ? 6'h10 : _notCDom_normDistReduced2_T_91; // @[Mux.scala:50:70]
wire [5:0] _notCDom_normDistReduced2_T_93 = _notCDom_normDistReduced2_T_39 ? 6'hF : _notCDom_normDistReduced2_T_92; // @[Mux.scala:50:70]
wire [5:0] _notCDom_normDistReduced2_T_94 = _notCDom_normDistReduced2_T_40 ? 6'hE : _notCDom_normDistReduced2_T_93; // @[Mux.scala:50:70]
wire [5:0] _notCDom_normDistReduced2_T_95 = _notCDom_normDistReduced2_T_41 ? 6'hD : _notCDom_normDistReduced2_T_94; // @[Mux.scala:50:70]
wire [5:0] _notCDom_normDistReduced2_T_96 = _notCDom_normDistReduced2_T_42 ? 6'hC : _notCDom_normDistReduced2_T_95; // @[Mux.scala:50:70]
wire [5:0] _notCDom_normDistReduced2_T_97 = _notCDom_normDistReduced2_T_43 ? 6'hB : _notCDom_normDistReduced2_T_96; // @[Mux.scala:50:70]
wire [5:0] _notCDom_normDistReduced2_T_98 = _notCDom_normDistReduced2_T_44 ? 6'hA : _notCDom_normDistReduced2_T_97; // @[Mux.scala:50:70]
wire [5:0] _notCDom_normDistReduced2_T_99 = _notCDom_normDistReduced2_T_45 ? 6'h9 : _notCDom_normDistReduced2_T_98; // @[Mux.scala:50:70]
wire [5:0] _notCDom_normDistReduced2_T_100 = _notCDom_normDistReduced2_T_46 ? 6'h8 : _notCDom_normDistReduced2_T_99; // @[Mux.scala:50:70]
wire [5:0] _notCDom_normDistReduced2_T_101 = _notCDom_normDistReduced2_T_47 ? 6'h7 : _notCDom_normDistReduced2_T_100; // @[Mux.scala:50:70]
wire [5:0] _notCDom_normDistReduced2_T_102 = _notCDom_normDistReduced2_T_48 ? 6'h6 : _notCDom_normDistReduced2_T_101; // @[Mux.scala:50:70]
wire [5:0] _notCDom_normDistReduced2_T_103 = _notCDom_normDistReduced2_T_49 ? 6'h5 : _notCDom_normDistReduced2_T_102; // @[Mux.scala:50:70]
wire [5:0] _notCDom_normDistReduced2_T_104 = _notCDom_normDistReduced2_T_50 ? 6'h4 : _notCDom_normDistReduced2_T_103; // @[Mux.scala:50:70]
wire [5:0] _notCDom_normDistReduced2_T_105 = _notCDom_normDistReduced2_T_51 ? 6'h3 : _notCDom_normDistReduced2_T_104; // @[Mux.scala:50:70]
wire [5:0] _notCDom_normDistReduced2_T_106 = _notCDom_normDistReduced2_T_52 ? 6'h2 : _notCDom_normDistReduced2_T_105; // @[Mux.scala:50:70]
wire [5:0] _notCDom_normDistReduced2_T_107 = _notCDom_normDistReduced2_T_53 ? 6'h1 : _notCDom_normDistReduced2_T_106; // @[Mux.scala:50:70]
wire [5:0] notCDom_normDistReduced2 = _notCDom_normDistReduced2_T_54 ? 6'h0 : _notCDom_normDistReduced2_T_107; // @[Mux.scala:50:70]
wire [6:0] notCDom_nearNormDist = {notCDom_normDistReduced2, 1'h0}; // @[Mux.scala:50:70]
wire [7:0] _notCDom_sExp_T = {1'h0, notCDom_nearNormDist}; // @[MulAddRecFN.scala:240:56, :241:76]
wire [13:0] _notCDom_sExp_T_1 = _GEN - {{6{_notCDom_sExp_T[7]}}, _notCDom_sExp_T}; // @[MulAddRecFN.scala:203:43, :241:{46,76}]
wire [12:0] _notCDom_sExp_T_2 = _notCDom_sExp_T_1[12:0]; // @[MulAddRecFN.scala:241:46]
wire [12:0] notCDom_sExp = _notCDom_sExp_T_2; // @[MulAddRecFN.scala:241:46]
wire [235:0] _notCDom_mainSig_T = {127'h0, notCDom_absSigSum} << notCDom_nearNormDist; // @[MulAddRecFN.scala:234:12, :240:56, :243:27]
wire [57:0] notCDom_mainSig = _notCDom_mainSig_T[109:52]; // @[MulAddRecFN.scala:243:{27,50}]
wire [26:0] _notCDom_reduced4SigExtra_T = notCDom_reduced2AbsSigSum[26:0]; // @[primitives.scala:107:20]
wire [26:0] _notCDom_reduced4SigExtra_T_1 = _notCDom_reduced4SigExtra_T; // @[MulAddRecFN.scala:247:{39,55}]
wire _notCDom_reduced4SigExtra_reducedVec_0_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced4SigExtra_reducedVec_1_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced4SigExtra_reducedVec_2_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced4SigExtra_reducedVec_3_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced4SigExtra_reducedVec_4_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced4SigExtra_reducedVec_5_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced4SigExtra_reducedVec_6_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced4SigExtra_reducedVec_7_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced4SigExtra_reducedVec_8_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced4SigExtra_reducedVec_9_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced4SigExtra_reducedVec_10_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced4SigExtra_reducedVec_11_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced4SigExtra_reducedVec_12_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced4SigExtra_reducedVec_13_T_1; // @[primitives.scala:106:57]
wire notCDom_reduced4SigExtra_reducedVec_0; // @[primitives.scala:101:30]
wire notCDom_reduced4SigExtra_reducedVec_1; // @[primitives.scala:101:30]
wire notCDom_reduced4SigExtra_reducedVec_2; // @[primitives.scala:101:30]
wire notCDom_reduced4SigExtra_reducedVec_3; // @[primitives.scala:101:30]
wire notCDom_reduced4SigExtra_reducedVec_4; // @[primitives.scala:101:30]
wire notCDom_reduced4SigExtra_reducedVec_5; // @[primitives.scala:101:30]
wire notCDom_reduced4SigExtra_reducedVec_6; // @[primitives.scala:101:30]
wire notCDom_reduced4SigExtra_reducedVec_7; // @[primitives.scala:101:30]
wire notCDom_reduced4SigExtra_reducedVec_8; // @[primitives.scala:101:30]
wire notCDom_reduced4SigExtra_reducedVec_9; // @[primitives.scala:101:30]
wire notCDom_reduced4SigExtra_reducedVec_10; // @[primitives.scala:101:30]
wire notCDom_reduced4SigExtra_reducedVec_11; // @[primitives.scala:101:30]
wire notCDom_reduced4SigExtra_reducedVec_12; // @[primitives.scala:101:30]
wire notCDom_reduced4SigExtra_reducedVec_13; // @[primitives.scala:101:30]
wire [1:0] _notCDom_reduced4SigExtra_reducedVec_0_T = _notCDom_reduced4SigExtra_T_1[1:0]; // @[primitives.scala:103:33]
assign _notCDom_reduced4SigExtra_reducedVec_0_T_1 = |_notCDom_reduced4SigExtra_reducedVec_0_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced4SigExtra_reducedVec_0 = _notCDom_reduced4SigExtra_reducedVec_0_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced4SigExtra_reducedVec_1_T = _notCDom_reduced4SigExtra_T_1[3:2]; // @[primitives.scala:103:33]
assign _notCDom_reduced4SigExtra_reducedVec_1_T_1 = |_notCDom_reduced4SigExtra_reducedVec_1_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced4SigExtra_reducedVec_1 = _notCDom_reduced4SigExtra_reducedVec_1_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced4SigExtra_reducedVec_2_T = _notCDom_reduced4SigExtra_T_1[5:4]; // @[primitives.scala:103:33]
assign _notCDom_reduced4SigExtra_reducedVec_2_T_1 = |_notCDom_reduced4SigExtra_reducedVec_2_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced4SigExtra_reducedVec_2 = _notCDom_reduced4SigExtra_reducedVec_2_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced4SigExtra_reducedVec_3_T = _notCDom_reduced4SigExtra_T_1[7:6]; // @[primitives.scala:103:33]
assign _notCDom_reduced4SigExtra_reducedVec_3_T_1 = |_notCDom_reduced4SigExtra_reducedVec_3_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced4SigExtra_reducedVec_3 = _notCDom_reduced4SigExtra_reducedVec_3_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced4SigExtra_reducedVec_4_T = _notCDom_reduced4SigExtra_T_1[9:8]; // @[primitives.scala:103:33]
assign _notCDom_reduced4SigExtra_reducedVec_4_T_1 = |_notCDom_reduced4SigExtra_reducedVec_4_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced4SigExtra_reducedVec_4 = _notCDom_reduced4SigExtra_reducedVec_4_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced4SigExtra_reducedVec_5_T = _notCDom_reduced4SigExtra_T_1[11:10]; // @[primitives.scala:103:33]
assign _notCDom_reduced4SigExtra_reducedVec_5_T_1 = |_notCDom_reduced4SigExtra_reducedVec_5_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced4SigExtra_reducedVec_5 = _notCDom_reduced4SigExtra_reducedVec_5_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced4SigExtra_reducedVec_6_T = _notCDom_reduced4SigExtra_T_1[13:12]; // @[primitives.scala:103:33]
assign _notCDom_reduced4SigExtra_reducedVec_6_T_1 = |_notCDom_reduced4SigExtra_reducedVec_6_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced4SigExtra_reducedVec_6 = _notCDom_reduced4SigExtra_reducedVec_6_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced4SigExtra_reducedVec_7_T = _notCDom_reduced4SigExtra_T_1[15:14]; // @[primitives.scala:103:33]
assign _notCDom_reduced4SigExtra_reducedVec_7_T_1 = |_notCDom_reduced4SigExtra_reducedVec_7_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced4SigExtra_reducedVec_7 = _notCDom_reduced4SigExtra_reducedVec_7_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced4SigExtra_reducedVec_8_T = _notCDom_reduced4SigExtra_T_1[17:16]; // @[primitives.scala:103:33]
assign _notCDom_reduced4SigExtra_reducedVec_8_T_1 = |_notCDom_reduced4SigExtra_reducedVec_8_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced4SigExtra_reducedVec_8 = _notCDom_reduced4SigExtra_reducedVec_8_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced4SigExtra_reducedVec_9_T = _notCDom_reduced4SigExtra_T_1[19:18]; // @[primitives.scala:103:33]
assign _notCDom_reduced4SigExtra_reducedVec_9_T_1 = |_notCDom_reduced4SigExtra_reducedVec_9_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced4SigExtra_reducedVec_9 = _notCDom_reduced4SigExtra_reducedVec_9_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced4SigExtra_reducedVec_10_T = _notCDom_reduced4SigExtra_T_1[21:20]; // @[primitives.scala:103:33]
assign _notCDom_reduced4SigExtra_reducedVec_10_T_1 = |_notCDom_reduced4SigExtra_reducedVec_10_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced4SigExtra_reducedVec_10 = _notCDom_reduced4SigExtra_reducedVec_10_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced4SigExtra_reducedVec_11_T = _notCDom_reduced4SigExtra_T_1[23:22]; // @[primitives.scala:103:33]
assign _notCDom_reduced4SigExtra_reducedVec_11_T_1 = |_notCDom_reduced4SigExtra_reducedVec_11_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced4SigExtra_reducedVec_11 = _notCDom_reduced4SigExtra_reducedVec_11_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced4SigExtra_reducedVec_12_T = _notCDom_reduced4SigExtra_T_1[25:24]; // @[primitives.scala:103:33]
assign _notCDom_reduced4SigExtra_reducedVec_12_T_1 = |_notCDom_reduced4SigExtra_reducedVec_12_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced4SigExtra_reducedVec_12 = _notCDom_reduced4SigExtra_reducedVec_12_T_1; // @[primitives.scala:101:30, :103:54]
wire _notCDom_reduced4SigExtra_reducedVec_13_T = _notCDom_reduced4SigExtra_T_1[26]; // @[primitives.scala:106:15]
assign _notCDom_reduced4SigExtra_reducedVec_13_T_1 = _notCDom_reduced4SigExtra_reducedVec_13_T; // @[primitives.scala:106:{15,57}]
assign notCDom_reduced4SigExtra_reducedVec_13 = _notCDom_reduced4SigExtra_reducedVec_13_T_1; // @[primitives.scala:101:30, :106:57]
wire [1:0] notCDom_reduced4SigExtra_lo_lo_hi = {notCDom_reduced4SigExtra_reducedVec_2, notCDom_reduced4SigExtra_reducedVec_1}; // @[primitives.scala:101:30, :107:20]
wire [2:0] notCDom_reduced4SigExtra_lo_lo = {notCDom_reduced4SigExtra_lo_lo_hi, notCDom_reduced4SigExtra_reducedVec_0}; // @[primitives.scala:101:30, :107:20]
wire [1:0] notCDom_reduced4SigExtra_lo_hi_lo = {notCDom_reduced4SigExtra_reducedVec_4, notCDom_reduced4SigExtra_reducedVec_3}; // @[primitives.scala:101:30, :107:20]
wire [1:0] notCDom_reduced4SigExtra_lo_hi_hi = {notCDom_reduced4SigExtra_reducedVec_6, notCDom_reduced4SigExtra_reducedVec_5}; // @[primitives.scala:101:30, :107:20]
wire [3:0] notCDom_reduced4SigExtra_lo_hi = {notCDom_reduced4SigExtra_lo_hi_hi, notCDom_reduced4SigExtra_lo_hi_lo}; // @[primitives.scala:107:20]
wire [6:0] notCDom_reduced4SigExtra_lo = {notCDom_reduced4SigExtra_lo_hi, notCDom_reduced4SigExtra_lo_lo}; // @[primitives.scala:107:20]
wire [1:0] notCDom_reduced4SigExtra_hi_lo_hi = {notCDom_reduced4SigExtra_reducedVec_9, notCDom_reduced4SigExtra_reducedVec_8}; // @[primitives.scala:101:30, :107:20]
wire [2:0] notCDom_reduced4SigExtra_hi_lo = {notCDom_reduced4SigExtra_hi_lo_hi, notCDom_reduced4SigExtra_reducedVec_7}; // @[primitives.scala:101:30, :107:20]
wire [1:0] notCDom_reduced4SigExtra_hi_hi_lo = {notCDom_reduced4SigExtra_reducedVec_11, notCDom_reduced4SigExtra_reducedVec_10}; // @[primitives.scala:101:30, :107:20]
wire [1:0] notCDom_reduced4SigExtra_hi_hi_hi = {notCDom_reduced4SigExtra_reducedVec_13, notCDom_reduced4SigExtra_reducedVec_12}; // @[primitives.scala:101:30, :107:20]
wire [3:0] notCDom_reduced4SigExtra_hi_hi = {notCDom_reduced4SigExtra_hi_hi_hi, notCDom_reduced4SigExtra_hi_hi_lo}; // @[primitives.scala:107:20]
wire [6:0] notCDom_reduced4SigExtra_hi = {notCDom_reduced4SigExtra_hi_hi, notCDom_reduced4SigExtra_hi_lo}; // @[primitives.scala:107:20]
wire [13:0] _notCDom_reduced4SigExtra_T_2 = {notCDom_reduced4SigExtra_hi, notCDom_reduced4SigExtra_lo}; // @[primitives.scala:107:20]
wire [4:0] _notCDom_reduced4SigExtra_T_3 = notCDom_normDistReduced2[5:1]; // @[Mux.scala:50:70]
wire [4:0] _notCDom_reduced4SigExtra_T_4 = ~_notCDom_reduced4SigExtra_T_3; // @[primitives.scala:52:21]
wire [32:0] notCDom_reduced4SigExtra_shift = $signed(33'sh100000000 >>> _notCDom_reduced4SigExtra_T_4); // @[primitives.scala:52:21, :76:56]
wire [12:0] _notCDom_reduced4SigExtra_T_5 = notCDom_reduced4SigExtra_shift[13:1]; // @[primitives.scala:76:56, :78:22]
wire [7:0] _notCDom_reduced4SigExtra_T_6 = _notCDom_reduced4SigExtra_T_5[7:0]; // @[primitives.scala:77:20, :78:22]
wire [3:0] _notCDom_reduced4SigExtra_T_9 = _notCDom_reduced4SigExtra_T_6[7:4]; // @[primitives.scala:77:20]
wire [7:0] _notCDom_reduced4SigExtra_T_10 = {4'h0, _notCDom_reduced4SigExtra_T_9}; // @[primitives.scala:77:20, :120:54]
wire [3:0] _notCDom_reduced4SigExtra_T_11 = _notCDom_reduced4SigExtra_T_6[3:0]; // @[primitives.scala:77:20]
wire [7:0] _notCDom_reduced4SigExtra_T_12 = {_notCDom_reduced4SigExtra_T_11, 4'h0}; // @[primitives.scala:77:20, :120:54]
wire [7:0] _notCDom_reduced4SigExtra_T_14 = _notCDom_reduced4SigExtra_T_12 & 8'hF0; // @[primitives.scala:77:20]
wire [7:0] _notCDom_reduced4SigExtra_T_15 = _notCDom_reduced4SigExtra_T_10 | _notCDom_reduced4SigExtra_T_14; // @[primitives.scala:77:20]
wire [5:0] _notCDom_reduced4SigExtra_T_19 = _notCDom_reduced4SigExtra_T_15[7:2]; // @[primitives.scala:77:20]
wire [7:0] _notCDom_reduced4SigExtra_T_20 = {2'h0, _notCDom_reduced4SigExtra_T_19 & 6'h33}; // @[primitives.scala:77:20]
wire [5:0] _notCDom_reduced4SigExtra_T_21 = _notCDom_reduced4SigExtra_T_15[5:0]; // @[primitives.scala:77:20]
wire [7:0] _notCDom_reduced4SigExtra_T_22 = {_notCDom_reduced4SigExtra_T_21, 2'h0}; // @[primitives.scala:77:20]
wire [7:0] _notCDom_reduced4SigExtra_T_24 = _notCDom_reduced4SigExtra_T_22 & 8'hCC; // @[primitives.scala:77:20]
wire [7:0] _notCDom_reduced4SigExtra_T_25 = _notCDom_reduced4SigExtra_T_20 | _notCDom_reduced4SigExtra_T_24; // @[primitives.scala:77:20]
wire [6:0] _notCDom_reduced4SigExtra_T_29 = _notCDom_reduced4SigExtra_T_25[7:1]; // @[primitives.scala:77:20]
wire [7:0] _notCDom_reduced4SigExtra_T_30 = {1'h0, _notCDom_reduced4SigExtra_T_29 & 7'h55}; // @[primitives.scala:77:20]
wire [6:0] _notCDom_reduced4SigExtra_T_31 = _notCDom_reduced4SigExtra_T_25[6:0]; // @[primitives.scala:77:20]
wire [7:0] _notCDom_reduced4SigExtra_T_32 = {_notCDom_reduced4SigExtra_T_31, 1'h0}; // @[primitives.scala:77:20]
wire [7:0] _notCDom_reduced4SigExtra_T_34 = _notCDom_reduced4SigExtra_T_32 & 8'hAA; // @[primitives.scala:77:20]
wire [7:0] _notCDom_reduced4SigExtra_T_35 = _notCDom_reduced4SigExtra_T_30 | _notCDom_reduced4SigExtra_T_34; // @[primitives.scala:77:20]
wire [4:0] _notCDom_reduced4SigExtra_T_36 = _notCDom_reduced4SigExtra_T_5[12:8]; // @[primitives.scala:77:20, :78:22]
wire [3:0] _notCDom_reduced4SigExtra_T_37 = _notCDom_reduced4SigExtra_T_36[3:0]; // @[primitives.scala:77:20]
wire [1:0] _notCDom_reduced4SigExtra_T_38 = _notCDom_reduced4SigExtra_T_37[1:0]; // @[primitives.scala:77:20]
wire _notCDom_reduced4SigExtra_T_39 = _notCDom_reduced4SigExtra_T_38[0]; // @[primitives.scala:77:20]
wire _notCDom_reduced4SigExtra_T_40 = _notCDom_reduced4SigExtra_T_38[1]; // @[primitives.scala:77:20]
wire [1:0] _notCDom_reduced4SigExtra_T_41 = {_notCDom_reduced4SigExtra_T_39, _notCDom_reduced4SigExtra_T_40}; // @[primitives.scala:77:20]
wire [1:0] _notCDom_reduced4SigExtra_T_42 = _notCDom_reduced4SigExtra_T_37[3:2]; // @[primitives.scala:77:20]
wire _notCDom_reduced4SigExtra_T_43 = _notCDom_reduced4SigExtra_T_42[0]; // @[primitives.scala:77:20]
wire _notCDom_reduced4SigExtra_T_44 = _notCDom_reduced4SigExtra_T_42[1]; // @[primitives.scala:77:20]
wire [1:0] _notCDom_reduced4SigExtra_T_45 = {_notCDom_reduced4SigExtra_T_43, _notCDom_reduced4SigExtra_T_44}; // @[primitives.scala:77:20]
wire [3:0] _notCDom_reduced4SigExtra_T_46 = {_notCDom_reduced4SigExtra_T_41, _notCDom_reduced4SigExtra_T_45}; // @[primitives.scala:77:20]
wire _notCDom_reduced4SigExtra_T_47 = _notCDom_reduced4SigExtra_T_36[4]; // @[primitives.scala:77:20]
wire [4:0] _notCDom_reduced4SigExtra_T_48 = {_notCDom_reduced4SigExtra_T_46, _notCDom_reduced4SigExtra_T_47}; // @[primitives.scala:77:20]
wire [12:0] _notCDom_reduced4SigExtra_T_49 = {_notCDom_reduced4SigExtra_T_35, _notCDom_reduced4SigExtra_T_48}; // @[primitives.scala:77:20]
wire [13:0] _notCDom_reduced4SigExtra_T_50 = {1'h0, _notCDom_reduced4SigExtra_T_2[12:0] & _notCDom_reduced4SigExtra_T_49}; // @[primitives.scala:77:20, :107:20]
wire notCDom_reduced4SigExtra = |_notCDom_reduced4SigExtra_T_50; // @[MulAddRecFN.scala:247:78, :249:11]
wire [54:0] _notCDom_sig_T = notCDom_mainSig[57:3]; // @[MulAddRecFN.scala:243:50, :251:28]
wire [2:0] _notCDom_sig_T_1 = notCDom_mainSig[2:0]; // @[MulAddRecFN.scala:243:50, :252:28]
wire _notCDom_sig_T_2 = |_notCDom_sig_T_1; // @[MulAddRecFN.scala:252:{28,35}]
wire _notCDom_sig_T_3 = _notCDom_sig_T_2 | notCDom_reduced4SigExtra; // @[MulAddRecFN.scala:249:11, :252:{35,39}]
wire [55:0] notCDom_sig = {_notCDom_sig_T, _notCDom_sig_T_3}; // @[MulAddRecFN.scala:251:{12,28}, :252:39]
wire [1:0] _notCDom_completeCancellation_T = notCDom_sig[55:54]; // @[MulAddRecFN.scala:251:12, :255:21]
wire notCDom_completeCancellation = _notCDom_completeCancellation_T == 2'h0; // @[MulAddRecFN.scala:222:53, :255:{21,50}]
wire _notCDom_sign_T = io_fromPreMul_signProd_0 ^ notCDom_signSigSum; // @[MulAddRecFN.scala:169:7, :232:36, :259:36]
wire notCDom_sign = notCDom_completeCancellation ? roundingMode_min : _notCDom_sign_T; // @[MulAddRecFN.scala:186:45, :255:50, :257:12, :259:36]
wire _GEN_0 = io_fromPreMul_isInfA_0 | io_fromPreMul_isInfB_0; // @[MulAddRecFN.scala:169:7, :264:49]
wire notNaN_isInfProd; // @[MulAddRecFN.scala:264:49]
assign notNaN_isInfProd = _GEN_0; // @[MulAddRecFN.scala:264:49]
wire _io_invalidExc_T_5; // @[MulAddRecFN.scala:275:36]
assign _io_invalidExc_T_5 = _GEN_0; // @[MulAddRecFN.scala:264:49, :275:36]
assign notNaN_isInfOut = notNaN_isInfProd | io_fromPreMul_isInfC_0; // @[MulAddRecFN.scala:169:7, :264:49, :265:44]
assign io_rawOut_isInf_0 = notNaN_isInfOut; // @[MulAddRecFN.scala:169:7, :265:44]
wire _notNaN_addZeros_T = io_fromPreMul_isZeroA_0 | io_fromPreMul_isZeroB_0; // @[MulAddRecFN.scala:169:7, :267:32]
wire notNaN_addZeros = _notNaN_addZeros_T & io_fromPreMul_isZeroC_0; // @[MulAddRecFN.scala:169:7, :267:{32,58}]
wire _io_invalidExc_T = io_fromPreMul_isInfA_0 & io_fromPreMul_isZeroB_0; // @[MulAddRecFN.scala:169:7, :272:31]
wire _io_invalidExc_T_1 = io_fromPreMul_isSigNaNAny_0 | _io_invalidExc_T; // @[MulAddRecFN.scala:169:7, :271:35, :272:31]
wire _io_invalidExc_T_2 = io_fromPreMul_isZeroA_0 & io_fromPreMul_isInfB_0; // @[MulAddRecFN.scala:169:7, :273:32]
wire _io_invalidExc_T_3 = _io_invalidExc_T_1 | _io_invalidExc_T_2; // @[MulAddRecFN.scala:271:35, :272:57, :273:32]
wire _io_invalidExc_T_4 = ~io_fromPreMul_isNaNAOrB_0; // @[MulAddRecFN.scala:169:7, :274:10]
wire _io_invalidExc_T_6 = _io_invalidExc_T_4 & _io_invalidExc_T_5; // @[MulAddRecFN.scala:274:{10,36}, :275:36]
wire _io_invalidExc_T_7 = _io_invalidExc_T_6 & io_fromPreMul_isInfC_0; // @[MulAddRecFN.scala:169:7, :274:36, :275:61]
wire _io_invalidExc_T_8 = _io_invalidExc_T_7 & io_fromPreMul_doSubMags_0; // @[MulAddRecFN.scala:169:7, :275:61, :276:35]
assign _io_invalidExc_T_9 = _io_invalidExc_T_3 | _io_invalidExc_T_8; // @[MulAddRecFN.scala:272:57, :273:57, :276:35]
assign io_invalidExc_0 = _io_invalidExc_T_9; // @[MulAddRecFN.scala:169:7, :273:57]
assign _io_rawOut_isNaN_T = io_fromPreMul_isNaNAOrB_0 | io_fromPreMul_isNaNC_0; // @[MulAddRecFN.scala:169:7, :278:48]
assign io_rawOut_isNaN_0 = _io_rawOut_isNaN_T; // @[MulAddRecFN.scala:169:7, :278:48]
wire _io_rawOut_isZero_T = ~io_fromPreMul_CIsDominant_0; // @[MulAddRecFN.scala:169:7, :283:14]
wire _io_rawOut_isZero_T_1 = _io_rawOut_isZero_T & notCDom_completeCancellation; // @[MulAddRecFN.scala:255:50, :283:{14,42}]
assign _io_rawOut_isZero_T_2 = notNaN_addZeros | _io_rawOut_isZero_T_1; // @[MulAddRecFN.scala:267:58, :282:25, :283:42]
assign io_rawOut_isZero_0 = _io_rawOut_isZero_T_2; // @[MulAddRecFN.scala:169:7, :282:25]
wire _io_rawOut_sign_T = notNaN_isInfProd & io_fromPreMul_signProd_0; // @[MulAddRecFN.scala:169:7, :264:49, :285:27]
wire _io_rawOut_sign_T_1 = io_fromPreMul_isInfC_0 & opSignC; // @[MulAddRecFN.scala:169:7, :190:42, :286:31]
wire _io_rawOut_sign_T_2 = _io_rawOut_sign_T | _io_rawOut_sign_T_1; // @[MulAddRecFN.scala:285:{27,54}, :286:31]
wire _io_rawOut_sign_T_3 = ~roundingMode_min; // @[MulAddRecFN.scala:186:45, :287:29]
wire _io_rawOut_sign_T_4 = notNaN_addZeros & _io_rawOut_sign_T_3; // @[MulAddRecFN.scala:267:58, :287:{26,29}]
wire _io_rawOut_sign_T_5 = _io_rawOut_sign_T_4 & io_fromPreMul_signProd_0; // @[MulAddRecFN.scala:169:7, :287:{26,48}]
wire _io_rawOut_sign_T_6 = _io_rawOut_sign_T_5 & opSignC; // @[MulAddRecFN.scala:190:42, :287:48, :288:36]
wire _io_rawOut_sign_T_7 = _io_rawOut_sign_T_2 | _io_rawOut_sign_T_6; // @[MulAddRecFN.scala:285:54, :286:43, :288:36]
wire _io_rawOut_sign_T_8 = notNaN_addZeros & roundingMode_min; // @[MulAddRecFN.scala:186:45, :267:58, :289:26]
wire _io_rawOut_sign_T_9 = io_fromPreMul_signProd_0 | opSignC; // @[MulAddRecFN.scala:169:7, :190:42, :290:37]
wire _io_rawOut_sign_T_10 = _io_rawOut_sign_T_8 & _io_rawOut_sign_T_9; // @[MulAddRecFN.scala:289:{26,46}, :290:37]
wire _io_rawOut_sign_T_11 = _io_rawOut_sign_T_7 | _io_rawOut_sign_T_10; // @[MulAddRecFN.scala:286:43, :288:48, :289:46]
wire _io_rawOut_sign_T_12 = ~notNaN_isInfOut; // @[MulAddRecFN.scala:265:44, :291:10]
wire _io_rawOut_sign_T_13 = ~notNaN_addZeros; // @[MulAddRecFN.scala:267:58, :291:31]
wire _io_rawOut_sign_T_14 = _io_rawOut_sign_T_12 & _io_rawOut_sign_T_13; // @[MulAddRecFN.scala:291:{10,28,31}]
wire _io_rawOut_sign_T_15 = io_fromPreMul_CIsDominant_0 ? opSignC : notCDom_sign; // @[MulAddRecFN.scala:169:7, :190:42, :257:12, :292:17]
wire _io_rawOut_sign_T_16 = _io_rawOut_sign_T_14 & _io_rawOut_sign_T_15; // @[MulAddRecFN.scala:291:{28,49}, :292:17]
assign _io_rawOut_sign_T_17 = _io_rawOut_sign_T_11 | _io_rawOut_sign_T_16; // @[MulAddRecFN.scala:288:48, :290:50, :291:49]
assign io_rawOut_sign_0 = _io_rawOut_sign_T_17; // @[MulAddRecFN.scala:169:7, :290:50]
assign _io_rawOut_sExp_T = io_fromPreMul_CIsDominant_0 ? CDom_sExp : notCDom_sExp; // @[MulAddRecFN.scala:169:7, :203:43, :241:46, :293:26]
assign io_rawOut_sExp_0 = _io_rawOut_sExp_T; // @[MulAddRecFN.scala:169:7, :293:26]
assign _io_rawOut_sig_T = io_fromPreMul_CIsDominant_0 ? CDom_sig : notCDom_sig; // @[MulAddRecFN.scala:169:7, :225:12, :251:12, :294:25]
assign io_rawOut_sig_0 = _io_rawOut_sig_T; // @[MulAddRecFN.scala:169:7, :294:25]
assign io_invalidExc = io_invalidExc_0; // @[MulAddRecFN.scala:169:7]
assign io_rawOut_isNaN = io_rawOut_isNaN_0; // @[MulAddRecFN.scala:169:7]
assign io_rawOut_isInf = io_rawOut_isInf_0; // @[MulAddRecFN.scala:169:7]
assign io_rawOut_isZero = io_rawOut_isZero_0; // @[MulAddRecFN.scala:169:7]
assign io_rawOut_sign = io_rawOut_sign_0; // @[MulAddRecFN.scala:169:7]
assign io_rawOut_sExp = io_rawOut_sExp_0; // @[MulAddRecFN.scala:169:7]
assign io_rawOut_sig = io_rawOut_sig_0; // @[MulAddRecFN.scala:169:7]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File Monitor.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceLine
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import freechips.rocketchip.diplomacy.EnableMonitors
import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode}
import freechips.rocketchip.util.PlusArg
case class TLMonitorArgs(edge: TLEdge)
abstract class TLMonitorBase(args: TLMonitorArgs) extends Module
{
val io = IO(new Bundle {
val in = Input(new TLBundle(args.edge.bundle))
})
def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit
legalize(io.in, args.edge, reset)
}
object TLMonitor {
def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = {
if (enable) {
EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) }
} else { node }
}
}
class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args)
{
require (args.edge.params(TLMonitorStrictMode) || (! args.edge.params(TestplanTestType).formal))
val cover_prop_class = PropertyClass.Default
//Like assert but can flip to being an assumption for formal verification
def monAssert(cond: Bool, message: String): Unit =
if (monitorDir == MonitorDirection.Monitor) {
assert(cond, message)
} else {
Property(monitorDir, cond, message, PropertyClass.Default)
}
def assume(cond: Bool, message: String): Unit =
if (monitorDir == MonitorDirection.Monitor) {
assert(cond, message)
} else {
Property(monitorDir.flip, cond, message, PropertyClass.Default)
}
def extra = {
args.edge.sourceInfo match {
case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)"
case _ => ""
}
}
def visible(address: UInt, source: UInt, edge: TLEdge) =
edge.client.clients.map { c =>
!c.sourceId.contains(source) ||
c.visibility.map(_.contains(address)).reduce(_ || _)
}.reduce(_ && _)
def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = {
//switch this flag to turn on diplomacy in error messages
def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n"
monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra)
// Reuse these subexpressions to save some firrtl lines
val source_ok = edge.client.contains(bundle.source)
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val mask = edge.full_mask(bundle)
monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility")
//The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B
//TODO: check for acquireT?
when (bundle.opcode === TLMessages.AcquireBlock) {
monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra)
monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra)
monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra)
monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra)
}
when (bundle.opcode === TLMessages.AcquirePerm) {
monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra)
monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra)
monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra)
monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra)
monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra)
}
when (bundle.opcode === TLMessages.Get) {
monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra)
monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra)
monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra)
}
when (bundle.opcode === TLMessages.PutFullData) {
monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra)
monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.PutPartialData) {
monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra)
monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.ArithmeticData) {
monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra)
monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.LogicalData) {
monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra)
monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.Hint) {
monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra)
monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra)
}
}
def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = {
monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra)
monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility")
// Reuse these subexpressions to save some firrtl lines
val address_ok = edge.manager.containsSafe(edge.address(bundle))
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val mask = edge.full_mask(bundle)
val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source
when (bundle.opcode === TLMessages.Probe) {
assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra)
assume (address_ok, "'B' channel Probe carries unmanaged address" + extra)
assume (legal_source, "'B' channel Probe carries source that is not first source" + extra)
assume (is_aligned, "'B' channel Probe address not aligned to size" + extra)
assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra)
assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra)
assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra)
}
when (bundle.opcode === TLMessages.Get) {
monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra)
monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra)
}
when (bundle.opcode === TLMessages.PutFullData) {
monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra)
monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.PutPartialData) {
monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra)
monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.ArithmeticData) {
monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra)
monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra)
monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.LogicalData) {
monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra)
monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra)
monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.Hint) {
monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra)
monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra)
monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra)
}
}
def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = {
monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra)
val source_ok = edge.client.contains(bundle.source)
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val address_ok = edge.manager.containsSafe(edge.address(bundle))
monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility")
when (bundle.opcode === TLMessages.ProbeAck) {
monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra)
monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra)
}
when (bundle.opcode === TLMessages.ProbeAckData) {
monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra)
}
when (bundle.opcode === TLMessages.Release) {
monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra)
monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra)
monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra)
}
when (bundle.opcode === TLMessages.ReleaseData) {
monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra)
monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra)
}
when (bundle.opcode === TLMessages.AccessAck) {
monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra)
monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra)
}
when (bundle.opcode === TLMessages.AccessAckData) {
monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra)
}
when (bundle.opcode === TLMessages.HintAck) {
monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra)
monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra)
}
}
def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = {
assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra)
val source_ok = edge.client.contains(bundle.source)
val sink_ok = bundle.sink < edge.manager.endSinkId.U
val deny_put_ok = edge.manager.mayDenyPut.B
val deny_get_ok = edge.manager.mayDenyGet.B
when (bundle.opcode === TLMessages.ReleaseAck) {
assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra)
assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra)
assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra)
}
when (bundle.opcode === TLMessages.Grant) {
assume (source_ok, "'D' channel Grant carries invalid source ID" + extra)
assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra)
assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra)
assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra)
assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel Grant is denied" + extra)
}
when (bundle.opcode === TLMessages.GrantData) {
assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra)
assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra)
assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra)
assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra)
assume (!bundle.denied || bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra)
assume (deny_get_ok || !bundle.denied, "'D' channel GrantData is denied" + extra)
}
when (bundle.opcode === TLMessages.AccessAck) {
assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel AccessAck is denied" + extra)
}
when (bundle.opcode === TLMessages.AccessAckData) {
assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra)
assume (!bundle.denied || bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra)
assume (deny_get_ok || !bundle.denied, "'D' channel AccessAckData is denied" + extra)
}
when (bundle.opcode === TLMessages.HintAck) {
assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel HintAck is denied" + extra)
}
}
def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = {
val sink_ok = bundle.sink < edge.manager.endSinkId.U
monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra)
}
def legalizeFormat(bundle: TLBundle, edge: TLEdge) = {
when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) }
when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) }
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) }
when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) }
when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) }
} else {
monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra)
monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra)
monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra)
}
}
def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = {
val a_first = edge.first(a.bits, a.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (a.valid && !a_first) {
monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra)
monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra)
monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra)
monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra)
monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra)
}
when (a.fire && a_first) {
opcode := a.bits.opcode
param := a.bits.param
size := a.bits.size
source := a.bits.source
address := a.bits.address
}
}
def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = {
val b_first = edge.first(b.bits, b.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (b.valid && !b_first) {
monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra)
monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra)
monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra)
monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra)
monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra)
}
when (b.fire && b_first) {
opcode := b.bits.opcode
param := b.bits.param
size := b.bits.size
source := b.bits.source
address := b.bits.address
}
}
def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = {
// Symbolic variable
val sym_source = Wire(UInt(edge.client.endSourceId.W))
// TODO: Connect sym_source to a fixed value for simulation and to a
// free wire in formal
sym_source := 0.U
// Type casting Int to UInt
val maxSourceId = Wire(UInt(edge.client.endSourceId.W))
maxSourceId := edge.client.endSourceId.U
// Delayed verison of sym_source
val sym_source_d = Reg(UInt(edge.client.endSourceId.W))
sym_source_d := sym_source
// These will be constraints for FV setup
Property(
MonitorDirection.Monitor,
(sym_source === sym_source_d),
"sym_source should remain stable",
PropertyClass.Default)
Property(
MonitorDirection.Monitor,
(sym_source <= maxSourceId),
"sym_source should take legal value",
PropertyClass.Default)
val my_resp_pend = RegInit(false.B)
val my_opcode = Reg(UInt())
val my_size = Reg(UInt())
val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire)
val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire)
val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source)
val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source)
val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat)
val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend)
when (my_set_resp_pend) {
my_resp_pend := true.B
} .elsewhen (my_clr_resp_pend) {
my_resp_pend := false.B
}
when (my_a_first_beat) {
my_opcode := bundle.a.bits.opcode
my_size := bundle.a.bits.size
}
val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size)
val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode)
val my_resp_opcode_legal = Wire(Bool())
when ((my_resp_opcode === TLMessages.Get) || (my_resp_opcode === TLMessages.ArithmeticData) ||
(my_resp_opcode === TLMessages.LogicalData)) {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData)
} .elsewhen ((my_resp_opcode === TLMessages.PutFullData) || (my_resp_opcode === TLMessages.PutPartialData)) {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck)
} .otherwise {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck)
}
monAssert (IfThen(my_resp_pend, !my_a_first_beat),
"Request message should not be sent with a source ID, for which a response message" +
"is already pending (not received until current cycle) for a prior request message" +
"with the same source ID" + extra)
assume (IfThen(my_clr_resp_pend, (my_set_resp_pend || my_resp_pend)),
"Response message should be accepted with a source ID only if a request message with the" +
"same source ID has been accepted or is being accepted in the current cycle" + extra)
assume (IfThen(my_d_first_beat, (my_a_first_beat || my_resp_pend)),
"Response message should be sent with a source ID only if a request message with the" +
"same source ID has been accepted or is being sent in the current cycle" + extra)
assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)),
"If d_valid is 1, then d_size should be same as a_size of the corresponding request" +
"message" + extra)
assume (IfThen(my_d_first_beat, my_resp_opcode_legal),
"If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" +
"request message" + extra)
}
def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = {
val c_first = edge.first(c.bits, c.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (c.valid && !c_first) {
monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra)
monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra)
monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra)
monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra)
monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra)
}
when (c.fire && c_first) {
opcode := c.bits.opcode
param := c.bits.param
size := c.bits.size
source := c.bits.source
address := c.bits.address
}
}
def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = {
val d_first = edge.first(d.bits, d.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val sink = Reg(UInt())
val denied = Reg(Bool())
when (d.valid && !d_first) {
assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra)
assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra)
assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra)
assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra)
assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra)
assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra)
}
when (d.fire && d_first) {
opcode := d.bits.opcode
param := d.bits.param
size := d.bits.size
source := d.bits.source
sink := d.bits.sink
denied := d.bits.denied
}
}
def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = {
legalizeMultibeatA(bundle.a, edge)
legalizeMultibeatD(bundle.d, edge)
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
legalizeMultibeatB(bundle.b, edge)
legalizeMultibeatC(bundle.c, edge)
}
}
//This is left in for almond which doesn't adhere to the tilelink protocol
@deprecated("Use legalizeADSource instead if possible","")
def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = {
val inflight = RegInit(0.U(edge.client.endSourceId.W))
val a_first = edge.first(bundle.a.bits, bundle.a.fire)
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
val a_set = WireInit(0.U(edge.client.endSourceId.W))
when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) {
a_set := UIntToOH(bundle.a.bits.source)
assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra)
}
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
assume((a_set | inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra)
}
if (edge.manager.minLatency > 0) {
assume(a_set =/= d_clr || !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra)
}
inflight := (inflight | a_set) & ~d_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
assert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = {
val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset)
val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything
val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size)
val log_a_size_bus_size = log2Ceil(a_size_bus_size)
def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits
val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error
inflight.suggestName("inflight")
val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
inflight_opcodes.suggestName("inflight_opcodes")
val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
inflight_sizes.suggestName("inflight_sizes")
val a_first = edge.first(bundle.a.bits, bundle.a.fire)
a_first.suggestName("a_first")
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
d_first.suggestName("d_first")
val a_set = WireInit(0.U(edge.client.endSourceId.W))
val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
a_set.suggestName("a_set")
a_set_wo_ready.suggestName("a_set_wo_ready")
val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
a_opcodes_set.suggestName("a_opcodes_set")
val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
a_sizes_set.suggestName("a_sizes_set")
val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W))
a_opcode_lookup.suggestName("a_opcode_lookup")
a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U
val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W))
a_size_lookup.suggestName("a_size_lookup")
a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U
val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant))
val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant))
val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W))
a_opcodes_set_interm.suggestName("a_opcodes_set_interm")
val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W))
a_sizes_set_interm.suggestName("a_sizes_set_interm")
when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) {
a_set_wo_ready := UIntToOH(bundle.a.bits.source)
}
when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) {
a_set := UIntToOH(bundle.a.bits.source)
a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) | 1.U
a_sizes_set_interm := (bundle.a.bits.size << 1.U) | 1.U
a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U)
a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U)
monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra)
}
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
d_clr.suggestName("d_clr")
d_clr_wo_ready.suggestName("d_clr_wo_ready")
val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
d_opcodes_clr.suggestName("d_opcodes_clr")
val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
d_sizes_clr.suggestName("d_sizes_clr")
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr_wo_ready := UIntToOH(bundle.d.bits.source)
}
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U)
d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U)
}
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source)
assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra)
when (same_cycle_resp) {
assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) ||
(bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra)
assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra)
} .otherwise {
assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) ||
(bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra)
assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra)
}
}
when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) {
assume((!bundle.d.ready) || bundle.a.ready, "ready check")
}
if (edge.manager.minLatency > 0) {
assume(a_set_wo_ready =/= d_clr_wo_ready || !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra)
}
inflight := (inflight | a_set) & ~d_clr
inflight_opcodes := (inflight_opcodes | a_opcodes_set) & ~d_opcodes_clr
inflight_sizes := (inflight_sizes | a_sizes_set) & ~d_sizes_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = {
val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset)
val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything
val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size)
val log_c_size_bus_size = log2Ceil(c_size_bus_size)
def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits
val inflight = RegInit(0.U((2 max edge.client.endSourceId).W))
val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
inflight.suggestName("inflight")
inflight_opcodes.suggestName("inflight_opcodes")
inflight_sizes.suggestName("inflight_sizes")
val c_first = edge.first(bundle.c.bits, bundle.c.fire)
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
c_first.suggestName("c_first")
d_first.suggestName("d_first")
val c_set = WireInit(0.U(edge.client.endSourceId.W))
val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
c_set.suggestName("c_set")
c_set_wo_ready.suggestName("c_set_wo_ready")
c_opcodes_set.suggestName("c_opcodes_set")
c_sizes_set.suggestName("c_sizes_set")
val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W))
val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W))
c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U
c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U
c_opcode_lookup.suggestName("c_opcode_lookup")
c_size_lookup.suggestName("c_size_lookup")
val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W))
val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W))
c_opcodes_set_interm.suggestName("c_opcodes_set_interm")
c_sizes_set_interm.suggestName("c_sizes_set_interm")
when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) {
c_set_wo_ready := UIntToOH(bundle.c.bits.source)
}
when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) {
c_set := UIntToOH(bundle.c.bits.source)
c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) | 1.U
c_sizes_set_interm := (bundle.c.bits.size << 1.U) | 1.U
c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U)
c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U)
monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra)
}
val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck || bundle.c.bits.opcode === TLMessages.ProbeAckData
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
d_clr.suggestName("d_clr")
d_clr_wo_ready.suggestName("d_clr_wo_ready")
d_opcodes_clr.suggestName("d_opcodes_clr")
d_sizes_clr.suggestName("d_sizes_clr")
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
d_clr_wo_ready := UIntToOH(bundle.d.bits.source)
}
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U)
d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U)
}
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source)
assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra)
when (same_cycle_resp) {
assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra)
} .otherwise {
assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra)
}
}
when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) {
assume((!bundle.d.ready) || bundle.c.ready, "ready check")
}
if (edge.manager.minLatency > 0) {
when (c_set_wo_ready.orR) {
assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra)
}
}
inflight := (inflight | c_set) & ~d_clr
inflight_opcodes := (inflight_opcodes | c_opcodes_set) & ~d_opcodes_clr
inflight_sizes := (inflight_sizes | c_sizes_set) & ~d_sizes_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.c.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = {
val inflight = RegInit(0.U(edge.manager.endSinkId.W))
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
val e_first = true.B
val d_set = WireInit(0.U(edge.manager.endSinkId.W))
when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) {
d_set := UIntToOH(bundle.d.bits.sink)
assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra)
}
val e_clr = WireInit(0.U(edge.manager.endSinkId.W))
when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) {
e_clr := UIntToOH(bundle.e.bits.sink)
monAssert((d_set | inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra)
}
// edge.client.minLatency applies to BC, not DE
inflight := (inflight | d_set) & ~e_clr
}
def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = {
val sourceBits = log2Ceil(edge.client.endSourceId)
val tooBig = 14 // >16kB worth of flight information gets to be too much
if (sourceBits > tooBig) {
println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked")
} else {
if (args.edge.params(TestplanTestType).simulation) {
if (args.edge.params(TLMonitorStrictMode)) {
legalizeADSource(bundle, edge)
legalizeCDSource(bundle, edge)
} else {
legalizeADSourceOld(bundle, edge)
}
}
if (args.edge.params(TestplanTestType).formal) {
legalizeADSourceFormal(bundle, edge)
}
}
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
// legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize...
val sinkBits = log2Ceil(edge.manager.endSinkId)
if (sinkBits > tooBig) {
println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked")
} else {
legalizeDESink(bundle, edge)
}
}
}
def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = {
legalizeFormat (bundle, edge)
legalizeMultibeat (bundle, edge)
legalizeUnique (bundle, edge)
}
}
File Misc.scala:
// See LICENSE.Berkeley for license details.
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util._
import chisel3.util.random.LFSR
import org.chipsalliance.cde.config.Parameters
import scala.math._
class ParameterizedBundle(implicit p: Parameters) extends Bundle
trait Clocked extends Bundle {
val clock = Clock()
val reset = Bool()
}
object DecoupledHelper {
def apply(rvs: Bool*) = new DecoupledHelper(rvs)
}
class DecoupledHelper(val rvs: Seq[Bool]) {
def fire(exclude: Bool, includes: Bool*) = {
require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!")
(rvs.filter(_ ne exclude) ++ includes).reduce(_ && _)
}
def fire() = {
rvs.reduce(_ && _)
}
}
object MuxT {
def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2))
def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3))
def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4))
}
/** Creates a cascade of n MuxTs to search for a key value. */
object MuxTLookup {
def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = {
var res = default
for ((k, v) <- mapping.reverse)
res = MuxT(k === key, v, res)
res
}
def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = {
var res = default
for ((k, v) <- mapping.reverse)
res = MuxT(k === key, v, res)
res
}
}
object ValidMux {
def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = {
apply(v1 +: v2.toSeq)
}
def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = {
val out = Wire(Valid(valids.head.bits.cloneType))
out.valid := valids.map(_.valid).reduce(_ || _)
out.bits := MuxCase(valids.head.bits,
valids.map(v => (v.valid -> v.bits)))
out
}
}
object Str
{
def apply(s: String): UInt = {
var i = BigInt(0)
require(s.forall(validChar _))
for (c <- s)
i = (i << 8) | c
i.U((s.length*8).W)
}
def apply(x: Char): UInt = {
require(validChar(x))
x.U(8.W)
}
def apply(x: UInt): UInt = apply(x, 10)
def apply(x: UInt, radix: Int): UInt = {
val rad = radix.U
val w = x.getWidth
require(w > 0)
var q = x
var s = digit(q % rad)
for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {
q = q / rad
s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s)
}
s
}
def apply(x: SInt): UInt = apply(x, 10)
def apply(x: SInt, radix: Int): UInt = {
val neg = x < 0.S
val abs = x.abs.asUInt
if (radix != 10) {
Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix))
} else {
val rad = radix.U
val w = abs.getWidth
require(w > 0)
var q = abs
var s = digit(q % rad)
var needSign = neg
for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {
q = q / rad
val placeSpace = q === 0.U
val space = Mux(needSign, Str('-'), Str(' '))
needSign = needSign && !placeSpace
s = Cat(Mux(placeSpace, space, digit(q % rad)), s)
}
Cat(Mux(needSign, Str('-'), Str(' ')), s)
}
}
private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0)
private def validChar(x: Char) = x == (x & 0xFF)
}
object Split
{
def apply(x: UInt, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n0), x.extract(n0-1,0))
}
def apply(x: UInt, n1: Int, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))
}
def apply(x: UInt, n2: Int, n1: Int, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))
}
}
object Random
{
def apply(mod: Int, random: UInt): UInt = {
if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0)
else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod))
}
def apply(mod: Int): UInt = apply(mod, randomizer)
def oneHot(mod: Int, random: UInt): UInt = {
if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0))
else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt
}
def oneHot(mod: Int): UInt = oneHot(mod, randomizer)
private def randomizer = LFSR(16)
private def partition(value: UInt, slices: Int) =
Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U)
}
object Majority {
def apply(in: Set[Bool]): Bool = {
val n = (in.size >> 1) + 1
val clauses = in.subsets(n).map(_.reduce(_ && _))
clauses.reduce(_ || _)
}
def apply(in: Seq[Bool]): Bool = apply(in.toSet)
def apply(in: UInt): Bool = apply(in.asBools.toSet)
}
object PopCountAtLeast {
private def two(x: UInt): (Bool, Bool) = x.getWidth match {
case 1 => (x.asBool, false.B)
case n =>
val half = x.getWidth / 2
val (leftOne, leftTwo) = two(x(half - 1, 0))
val (rightOne, rightTwo) = two(x(x.getWidth - 1, half))
(leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne))
}
def apply(x: UInt, n: Int): Bool = n match {
case 0 => true.B
case 1 => x.orR
case 2 => two(x)._2
case 3 => PopCount(x) >= n.U
}
}
// This gets used everywhere, so make the smallest circuit possible ...
// Given an address and size, create a mask of beatBytes size
// eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111
// groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01
object MaskGen {
def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = {
require (groupBy >= 1 && beatBytes >= groupBy)
require (isPow2(beatBytes) && isPow2(groupBy))
val lgBytes = log2Ceil(beatBytes)
val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U
def helper(i: Int): Seq[(Bool, Bool)] = {
if (i == 0) {
Seq((lgSize >= lgBytes.asUInt, true.B))
} else {
val sub = helper(i-1)
val size = sizeOH(lgBytes - i)
val bit = addr_lo(lgBytes - i)
val nbit = !bit
Seq.tabulate (1 << i) { j =>
val (sub_acc, sub_eq) = sub(j/2)
val eq = sub_eq && (if (j % 2 == 1) bit else nbit)
val acc = sub_acc || (size && eq)
(acc, eq)
}
}
}
if (groupBy == beatBytes) 1.U else
Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse)
}
}
File PlusArg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.experimental._
import chisel3.util.HasBlackBoxResource
@deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05")
case class PlusArgInfo(default: BigInt, docstring: String)
/** Case class for PlusArg information
*
* @tparam A scala type of the PlusArg value
* @param default optional default value
* @param docstring text to include in the help
* @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT)
*/
private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String)
/** Typeclass for converting a type to a doctype string
* @tparam A some type
*/
trait Doctypeable[A] {
/** Return the doctype string for some option */
def toDoctype(a: Option[A]): String
}
/** Object containing implementations of the Doctypeable typeclass */
object Doctypes {
/** Converts an Int => "INT" */
implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" }
/** Converts a BigInt => "INT" */
implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" }
/** Converts a String => "STRING" */
implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" }
}
class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map(
"FORMAT" -> StringParam(format),
"DEFAULT" -> IntParam(default),
"WIDTH" -> IntParam(width)
)) with HasBlackBoxResource {
val io = IO(new Bundle {
val out = Output(UInt(width.W))
})
addResource("/vsrc/plusarg_reader.v")
}
/* This wrapper class has no outputs, making it clear it is a simulation-only construct */
class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module {
val io = IO(new Bundle {
val count = Input(UInt(width.W))
})
val max = Module(new plusarg_reader(format, default, docstring, width)).io.out
when (max > 0.U) {
assert (io.count < max, s"Timeout exceeded: $docstring")
}
}
import Doctypes._
object PlusArg
{
/** PlusArg("foo") will return 42.U if the simulation is run with +foo=42
* Do not use this as an initial register value. The value is set in an
* initial block and thus accessing it from another initial is racey.
* Add a docstring to document the arg, which can be dumped in an elaboration
* pass.
*/
def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = {
PlusArgArtefacts.append(name, Some(default), docstring)
Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out
}
/** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert
* to kill the simulation when count exceeds the specified integer argument.
* Default 0 will never assert.
*/
def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = {
PlusArgArtefacts.append(name, Some(default), docstring)
Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count
}
}
object PlusArgArtefacts {
private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty
/* Add a new PlusArg */
@deprecated(
"Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08",
"Rocket Chip 2020.05"
)
def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring)
/** Add a new PlusArg
*
* @tparam A scala type of the PlusArg value
* @param name name for the PlusArg
* @param default optional default value
* @param docstring text to include in the help
*/
def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit =
artefacts = artefacts ++
Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default)))
/* From plus args, generate help text */
private def serializeHelp_cHeader(tab: String = ""): String = artefacts
.map{ case(arg, info) =>
s"""|$tab+$arg=${info.doctype}\\n\\
|$tab${" "*20}${info.docstring}\\n\\
|""".stripMargin ++ info.default.map{ case default =>
s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("")
}.toSeq.mkString("\\n\\\n") ++ "\""
/* From plus args, generate a char array of their names */
private def serializeArray_cHeader(tab: String = ""): String = {
val prettyTab = tab + " " * 44 // Length of 'static const ...'
s"${tab}static const char * verilog_plusargs [] = {\\\n" ++
artefacts
.map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" }
.mkString("")++
s"${prettyTab}0};"
}
/* Generate C code to be included in emulator.cc that helps with
* argument parsing based on available Verilog PlusArgs */
def serialize_cHeader(): String =
s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\
|${serializeHelp_cHeader(" "*7)}
|${serializeArray_cHeader()}
|""".stripMargin
}
File package.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip
import chisel3._
import chisel3.util._
import scala.math.min
import scala.collection.{immutable, mutable}
package object util {
implicit class UnzippableOption[S, T](val x: Option[(S, T)]) {
def unzip = (x.map(_._1), x.map(_._2))
}
implicit class UIntIsOneOf(private val x: UInt) extends AnyVal {
def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR
def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq)
}
implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal {
/** Like Vec.apply(idx), but tolerates indices of mismatched width */
def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0))
}
implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal {
def apply(idx: UInt): T = {
if (x.size <= 1) {
x.head
} else if (!isPow2(x.size)) {
// For non-power-of-2 seqs, reflect elements to simplify decoder
(x ++ x.takeRight(x.size & -x.size)).toSeq(idx)
} else {
// Ignore MSBs of idx
val truncIdx =
if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx
else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0)
x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) }
}
}
def extract(idx: UInt): T = VecInit(x).extract(idx)
def asUInt: UInt = Cat(x.map(_.asUInt).reverse)
def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n)
def rotate(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n)
def rotateRight(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
}
// allow bitwise ops on Seq[Bool] just like UInt
implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal {
def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b }
def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b }
def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b }
def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x
def >> (n: Int): Seq[Bool] = x drop n
def unary_~ : Seq[Bool] = x.map(!_)
def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_)
def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_)
def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_)
private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B)
}
implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal {
def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable))
def getElements: Seq[Element] = x match {
case e: Element => Seq(e)
case a: Aggregate => a.getElements.flatMap(_.getElements)
}
}
/** Any Data subtype that has a Bool member named valid. */
type DataCanBeValid = Data { val valid: Bool }
implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal {
def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable)
}
implicit class StringToAugmentedString(private val x: String) extends AnyVal {
/** converts from camel case to to underscores, also removing all spaces */
def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") {
case (acc, c) if c.isUpper => acc + "_" + c.toLower
case (acc, c) if c == ' ' => acc
case (acc, c) => acc + c
}
/** converts spaces or underscores to hyphens, also lowering case */
def kebab: String = x.toLowerCase map {
case ' ' => '-'
case '_' => '-'
case c => c
}
def named(name: Option[String]): String = {
x + name.map("_named_" + _ ).getOrElse("_with_no_name")
}
def named(name: String): String = named(Some(name))
}
implicit def uintToBitPat(x: UInt): BitPat = BitPat(x)
implicit def wcToUInt(c: WideCounter): UInt = c.value
implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal {
def sextTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x)
}
def padTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(0.U((n - x.getWidth).W), x)
}
// shifts left by n if n >= 0, or right by -n if n < 0
def << (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << n(w-1, 0)
Mux(n(w), shifted >> (1 << w), shifted)
}
// shifts right by n if n >= 0, or left by -n if n < 0
def >> (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << (1 << w) >> n(w-1, 0)
Mux(n(w), shifted, shifted >> (1 << w))
}
// Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts
def extract(hi: Int, lo: Int): UInt = {
require(hi >= lo-1)
if (hi == lo-1) 0.U
else x(hi, lo)
}
// Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts
def extractOption(hi: Int, lo: Int): Option[UInt] = {
require(hi >= lo-1)
if (hi == lo-1) None
else Some(x(hi, lo))
}
// like x & ~y, but first truncate or zero-extend y to x's width
def andNot(y: UInt): UInt = x & ~(y | (x & 0.U))
def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n)
def rotateRight(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r))
}
}
def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n))
def rotateLeft(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r))
}
}
// compute (this + y) % n, given (this < n) and (y < n)
def addWrap(y: UInt, n: Int): UInt = {
val z = x +& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0)
}
// compute (this - y) % n, given (this < n) and (y < n)
def subWrap(y: UInt, n: Int): UInt = {
val z = x -& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0)
}
def grouped(width: Int): Seq[UInt] =
(0 until x.getWidth by width).map(base => x(base + width - 1, base))
def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds
def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x)
// Like >=, but prevents x-prop for ('x >= 0)
def >== (y: UInt): Bool = x >= y || y === 0.U
}
implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal {
def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y)
def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y)
}
implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal {
def toInt: Int = if (x) 1 else 0
// this one's snagged from scalaz
def option[T](z: => T): Option[T] = if (x) Some(z) else None
}
implicit class IntToAugmentedInt(private val x: Int) extends AnyVal {
// exact log2
def log2: Int = {
require(isPow2(x))
log2Ceil(x)
}
}
def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x)
def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x))
def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0)
def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1)
def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None
// Fill 1s from low bits to high bits
def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth)
def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0))
helper(1, x)(width-1, 0)
}
// Fill 1s form high bits to low bits
def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth)
def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x >> s))
helper(1, x)(width-1, 0)
}
def OptimizationBarrier[T <: Data](in: T): T = {
val barrier = Module(new Module {
val io = IO(new Bundle {
val x = Input(chiselTypeOf(in))
val y = Output(chiselTypeOf(in))
})
io.y := io.x
override def desiredName = s"OptimizationBarrier_${in.typeName}"
})
barrier.io.x := in
barrier.io.y
}
/** Similar to Seq.groupBy except this returns a Seq instead of a Map
* Useful for deterministic code generation
*/
def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = {
val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]]
for (x <- xs) {
val key = f(x)
val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A])
l += x
}
map.view.map({ case (k, vs) => k -> vs.toList }).toList
}
def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match {
case 1 => List.fill(n)(in.head)
case x if x == n => in
case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in")
}
// HeterogeneousBag moved to standalond diplomacy
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts)
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag
}
File Bundles.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import freechips.rocketchip.util._
import scala.collection.immutable.ListMap
import chisel3.util.Decoupled
import chisel3.util.DecoupledIO
import chisel3.reflect.DataMirror
abstract class TLBundleBase(val params: TLBundleParameters) extends Bundle
// common combos in lazy policy:
// Put + Acquire
// Release + AccessAck
object TLMessages
{
// A B C D E
def PutFullData = 0.U // . . => AccessAck
def PutPartialData = 1.U // . . => AccessAck
def ArithmeticData = 2.U // . . => AccessAckData
def LogicalData = 3.U // . . => AccessAckData
def Get = 4.U // . . => AccessAckData
def Hint = 5.U // . . => HintAck
def AcquireBlock = 6.U // . => Grant[Data]
def AcquirePerm = 7.U // . => Grant[Data]
def Probe = 6.U // . => ProbeAck[Data]
def AccessAck = 0.U // . .
def AccessAckData = 1.U // . .
def HintAck = 2.U // . .
def ProbeAck = 4.U // .
def ProbeAckData = 5.U // .
def Release = 6.U // . => ReleaseAck
def ReleaseData = 7.U // . => ReleaseAck
def Grant = 4.U // . => GrantAck
def GrantData = 5.U // . => GrantAck
def ReleaseAck = 6.U // .
def GrantAck = 0.U // .
def isA(x: UInt) = x <= AcquirePerm
def isB(x: UInt) = x <= Probe
def isC(x: UInt) = x <= ReleaseData
def isD(x: UInt) = x <= ReleaseAck
def adResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant, Grant)
def bcResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, ProbeAck, ProbeAck)
def a = Seq( ("PutFullData",TLPermissions.PermMsgReserved),
("PutPartialData",TLPermissions.PermMsgReserved),
("ArithmeticData",TLAtomics.ArithMsg),
("LogicalData",TLAtomics.LogicMsg),
("Get",TLPermissions.PermMsgReserved),
("Hint",TLHints.HintsMsg),
("AcquireBlock",TLPermissions.PermMsgGrow),
("AcquirePerm",TLPermissions.PermMsgGrow))
def b = Seq( ("PutFullData",TLPermissions.PermMsgReserved),
("PutPartialData",TLPermissions.PermMsgReserved),
("ArithmeticData",TLAtomics.ArithMsg),
("LogicalData",TLAtomics.LogicMsg),
("Get",TLPermissions.PermMsgReserved),
("Hint",TLHints.HintsMsg),
("Probe",TLPermissions.PermMsgCap))
def c = Seq( ("AccessAck",TLPermissions.PermMsgReserved),
("AccessAckData",TLPermissions.PermMsgReserved),
("HintAck",TLPermissions.PermMsgReserved),
("Invalid Opcode",TLPermissions.PermMsgReserved),
("ProbeAck",TLPermissions.PermMsgReport),
("ProbeAckData",TLPermissions.PermMsgReport),
("Release",TLPermissions.PermMsgReport),
("ReleaseData",TLPermissions.PermMsgReport))
def d = Seq( ("AccessAck",TLPermissions.PermMsgReserved),
("AccessAckData",TLPermissions.PermMsgReserved),
("HintAck",TLPermissions.PermMsgReserved),
("Invalid Opcode",TLPermissions.PermMsgReserved),
("Grant",TLPermissions.PermMsgCap),
("GrantData",TLPermissions.PermMsgCap),
("ReleaseAck",TLPermissions.PermMsgReserved))
}
/**
* The three primary TileLink permissions are:
* (T)runk: the agent is (or is on inwards path to) the global point of serialization.
* (B)ranch: the agent is on an outwards path to
* (N)one:
* These permissions are permuted by transfer operations in various ways.
* Operations can cap permissions, request for them to be grown or shrunk,
* or for a report on their current status.
*/
object TLPermissions
{
val aWidth = 2
val bdWidth = 2
val cWidth = 3
// Cap types (Grant = new permissions, Probe = permisions <= target)
def toT = 0.U(bdWidth.W)
def toB = 1.U(bdWidth.W)
def toN = 2.U(bdWidth.W)
def isCap(x: UInt) = x <= toN
// Grow types (Acquire = permissions >= target)
def NtoB = 0.U(aWidth.W)
def NtoT = 1.U(aWidth.W)
def BtoT = 2.U(aWidth.W)
def isGrow(x: UInt) = x <= BtoT
// Shrink types (ProbeAck, Release)
def TtoB = 0.U(cWidth.W)
def TtoN = 1.U(cWidth.W)
def BtoN = 2.U(cWidth.W)
def isShrink(x: UInt) = x <= BtoN
// Report types (ProbeAck, Release)
def TtoT = 3.U(cWidth.W)
def BtoB = 4.U(cWidth.W)
def NtoN = 5.U(cWidth.W)
def isReport(x: UInt) = x <= NtoN
def PermMsgGrow:Seq[String] = Seq("Grow NtoB", "Grow NtoT", "Grow BtoT")
def PermMsgCap:Seq[String] = Seq("Cap toT", "Cap toB", "Cap toN")
def PermMsgReport:Seq[String] = Seq("Shrink TtoB", "Shrink TtoN", "Shrink BtoN", "Report TotT", "Report BtoB", "Report NtoN")
def PermMsgReserved:Seq[String] = Seq("Reserved")
}
object TLAtomics
{
val width = 3
// Arithmetic types
def MIN = 0.U(width.W)
def MAX = 1.U(width.W)
def MINU = 2.U(width.W)
def MAXU = 3.U(width.W)
def ADD = 4.U(width.W)
def isArithmetic(x: UInt) = x <= ADD
// Logical types
def XOR = 0.U(width.W)
def OR = 1.U(width.W)
def AND = 2.U(width.W)
def SWAP = 3.U(width.W)
def isLogical(x: UInt) = x <= SWAP
def ArithMsg:Seq[String] = Seq("MIN", "MAX", "MINU", "MAXU", "ADD")
def LogicMsg:Seq[String] = Seq("XOR", "OR", "AND", "SWAP")
}
object TLHints
{
val width = 1
def PREFETCH_READ = 0.U(width.W)
def PREFETCH_WRITE = 1.U(width.W)
def isHints(x: UInt) = x <= PREFETCH_WRITE
def HintsMsg:Seq[String] = Seq("PrefetchRead", "PrefetchWrite")
}
sealed trait TLChannel extends TLBundleBase {
val channelName: String
}
sealed trait TLDataChannel extends TLChannel
sealed trait TLAddrChannel extends TLDataChannel
final class TLBundleA(params: TLBundleParameters)
extends TLBundleBase(params) with TLAddrChannel
{
override def typeName = s"TLBundleA_${params.shortName}"
val channelName = "'A' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(List(TLAtomics.width, TLPermissions.aWidth, TLHints.width).max.W) // amo_opcode || grow perms || hint
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // from
val address = UInt(params.addressBits.W) // to
val user = BundleMap(params.requestFields)
val echo = BundleMap(params.echoFields)
// variable fields during multibeat:
val mask = UInt((params.dataBits/8).W)
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleB(params: TLBundleParameters)
extends TLBundleBase(params) with TLAddrChannel
{
override def typeName = s"TLBundleB_${params.shortName}"
val channelName = "'B' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(TLPermissions.bdWidth.W) // cap perms
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // to
val address = UInt(params.addressBits.W) // from
// variable fields during multibeat:
val mask = UInt((params.dataBits/8).W)
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleC(params: TLBundleParameters)
extends TLBundleBase(params) with TLAddrChannel
{
override def typeName = s"TLBundleC_${params.shortName}"
val channelName = "'C' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(TLPermissions.cWidth.W) // shrink or report perms
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // from
val address = UInt(params.addressBits.W) // to
val user = BundleMap(params.requestFields)
val echo = BundleMap(params.echoFields)
// variable fields during multibeat:
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleD(params: TLBundleParameters)
extends TLBundleBase(params) with TLDataChannel
{
override def typeName = s"TLBundleD_${params.shortName}"
val channelName = "'D' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(TLPermissions.bdWidth.W) // cap perms
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // to
val sink = UInt(params.sinkBits.W) // from
val denied = Bool() // implies corrupt iff *Data
val user = BundleMap(params.responseFields)
val echo = BundleMap(params.echoFields)
// variable fields during multibeat:
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleE(params: TLBundleParameters)
extends TLBundleBase(params) with TLChannel
{
override def typeName = s"TLBundleE_${params.shortName}"
val channelName = "'E' channel"
val sink = UInt(params.sinkBits.W) // to
}
class TLBundle(val params: TLBundleParameters) extends Record
{
// Emulate a Bundle with elements abcde or ad depending on params.hasBCE
private val optA = Some (Decoupled(new TLBundleA(params)))
private val optB = params.hasBCE.option(Flipped(Decoupled(new TLBundleB(params))))
private val optC = params.hasBCE.option(Decoupled(new TLBundleC(params)))
private val optD = Some (Flipped(Decoupled(new TLBundleD(params))))
private val optE = params.hasBCE.option(Decoupled(new TLBundleE(params)))
def a: DecoupledIO[TLBundleA] = optA.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleA(params)))))
def b: DecoupledIO[TLBundleB] = optB.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleB(params)))))
def c: DecoupledIO[TLBundleC] = optC.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleC(params)))))
def d: DecoupledIO[TLBundleD] = optD.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleD(params)))))
def e: DecoupledIO[TLBundleE] = optE.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleE(params)))))
val elements =
if (params.hasBCE) ListMap("e" -> e, "d" -> d, "c" -> c, "b" -> b, "a" -> a)
else ListMap("d" -> d, "a" -> a)
def tieoff(): Unit = {
DataMirror.specifiedDirectionOf(a.ready) match {
case SpecifiedDirection.Input =>
a.ready := false.B
c.ready := false.B
e.ready := false.B
b.valid := false.B
d.valid := false.B
case SpecifiedDirection.Output =>
a.valid := false.B
c.valid := false.B
e.valid := false.B
b.ready := false.B
d.ready := false.B
case _ =>
}
}
}
object TLBundle
{
def apply(params: TLBundleParameters) = new TLBundle(params)
}
class TLAsyncBundleBase(val params: TLAsyncBundleParameters) extends Bundle
class TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params)
{
val a = new AsyncBundle(new TLBundleA(params.base), params.async)
val b = Flipped(new AsyncBundle(new TLBundleB(params.base), params.async))
val c = new AsyncBundle(new TLBundleC(params.base), params.async)
val d = Flipped(new AsyncBundle(new TLBundleD(params.base), params.async))
val e = new AsyncBundle(new TLBundleE(params.base), params.async)
}
class TLRationalBundle(params: TLBundleParameters) extends TLBundleBase(params)
{
val a = RationalIO(new TLBundleA(params))
val b = Flipped(RationalIO(new TLBundleB(params)))
val c = RationalIO(new TLBundleC(params))
val d = Flipped(RationalIO(new TLBundleD(params)))
val e = RationalIO(new TLBundleE(params))
}
class TLCreditedBundle(params: TLBundleParameters) extends TLBundleBase(params)
{
val a = CreditedIO(new TLBundleA(params))
val b = Flipped(CreditedIO(new TLBundleB(params)))
val c = CreditedIO(new TLBundleC(params))
val d = Flipped(CreditedIO(new TLBundleD(params)))
val e = CreditedIO(new TLBundleE(params))
}
File Parameters.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.diplomacy
import chisel3._
import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor}
import freechips.rocketchip.util.ShiftQueue
/** Options for describing the attributes of memory regions */
object RegionType {
// Define the 'more relaxed than' ordering
val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS)
sealed trait T extends Ordered[T] {
def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this)
}
case object CACHED extends T // an intermediate agent may have cached a copy of the region for you
case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided
case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible
case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached
case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects
case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed
case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively
}
// A non-empty half-open range; [start, end)
case class IdRange(start: Int, end: Int) extends Ordered[IdRange]
{
require (start >= 0, s"Ids cannot be negative, but got: $start.")
require (start <= end, "Id ranges cannot be negative.")
def compare(x: IdRange) = {
val primary = (this.start - x.start).signum
val secondary = (x.end - this.end).signum
if (primary != 0) primary else secondary
}
def overlaps(x: IdRange) = start < x.end && x.start < end
def contains(x: IdRange) = start <= x.start && x.end <= end
def contains(x: Int) = start <= x && x < end
def contains(x: UInt) =
if (size == 0) {
false.B
} else if (size == 1) { // simple comparison
x === start.U
} else {
// find index of largest different bit
val largestDeltaBit = log2Floor(start ^ (end-1))
val smallestCommonBit = largestDeltaBit + 1 // may not exist in x
val uncommonMask = (1 << smallestCommonBit) - 1
val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0)
// the prefix must match exactly (note: may shift ALL bits away)
(x >> smallestCommonBit) === (start >> smallestCommonBit).U &&
// firrtl constant prop range analysis can eliminate these two:
(start & uncommonMask).U <= uncommonBits &&
uncommonBits <= ((end-1) & uncommonMask).U
}
def shift(x: Int) = IdRange(start+x, end+x)
def size = end - start
def isEmpty = end == start
def range = start until end
}
object IdRange
{
def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else {
val ranges = s.sorted
(ranges.tail zip ranges.init) find { case (a, b) => a overlaps b }
}
}
// An potentially empty inclusive range of 2-powers [min, max] (in bytes)
case class TransferSizes(min: Int, max: Int)
{
def this(x: Int) = this(x, x)
require (min <= max, s"Min transfer $min > max transfer $max")
require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)")
require (max == 0 || isPow2(max), s"TransferSizes must be a power of 2, got: $max")
require (min == 0 || isPow2(min), s"TransferSizes must be a power of 2, got: $min")
require (max == 0 || min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)")
def none = min == 0
def contains(x: Int) = isPow2(x) && min <= x && x <= max
def containsLg(x: Int) = contains(1 << x)
def containsLg(x: UInt) =
if (none) false.B
else if (min == max) { log2Ceil(min).U === x }
else { log2Ceil(min).U <= x && x <= log2Ceil(max).U }
def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max)
def intersect(x: TransferSizes) =
if (x.max < min || max < x.min) TransferSizes.none
else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max))
// Not a union, because the result may contain sizes contained by neither term
// NOT TO BE CONFUSED WITH COVERPOINTS
def mincover(x: TransferSizes) = {
if (none) {
x
} else if (x.none) {
this
} else {
TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max))
}
}
override def toString() = "TransferSizes[%d, %d]".format(min, max)
}
object TransferSizes {
def apply(x: Int) = new TransferSizes(x)
val none = new TransferSizes(0)
def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _)
def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _)
implicit def asBool(x: TransferSizes) = !x.none
}
// AddressSets specify the address space managed by the manager
// Base is the base address, and mask are the bits consumed by the manager
// e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff
// e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ...
case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet]
{
// Forbid misaligned base address (and empty sets)
require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}")
require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous
// We do allow negative mask (=> ignore all high bits)
def contains(x: BigInt) = ((x ^ base) & ~mask) == 0
def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S
// turn x into an address contained in this set
def legalize(x: UInt): UInt = base.U | (mask.U & x)
// overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1)
def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0
// contains iff bitwise: x.mask => mask && contains(x.base)
def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0
// The number of bytes to which the manager must be aligned
def alignment = ((mask + 1) & ~mask)
// Is this a contiguous memory range
def contiguous = alignment == mask+1
def finite = mask >= 0
def max = { require (finite, "Max cannot be calculated on infinite mask"); base | mask }
// Widen the match function to ignore all bits in imask
def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask)
// Return an AddressSet that only contains the addresses both sets contain
def intersect(x: AddressSet): Option[AddressSet] = {
if (!overlaps(x)) {
None
} else {
val r_mask = mask & x.mask
val r_base = base | x.base
Some(AddressSet(r_base, r_mask))
}
}
def subtract(x: AddressSet): Seq[AddressSet] = {
intersect(x) match {
case None => Seq(this)
case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit =>
val nmask = (mask & (bit-1)) | remove.mask
val nbase = (remove.base ^ bit) & ~nmask
AddressSet(nbase, nmask)
}
}
}
// AddressSets have one natural Ordering (the containment order, if contiguous)
def compare(x: AddressSet) = {
val primary = (this.base - x.base).signum // smallest address first
val secondary = (x.mask - this.mask).signum // largest mask first
if (primary != 0) primary else secondary
}
// We always want to see things in hex
override def toString() = {
if (mask >= 0) {
"AddressSet(0x%x, 0x%x)".format(base, mask)
} else {
"AddressSet(0x%x, ~0x%x)".format(base, ~mask)
}
}
def toRanges = {
require (finite, "Ranges cannot be calculated on infinite mask")
val size = alignment
val fragments = mask & ~(size-1)
val bits = bitIndexes(fragments)
(BigInt(0) until (BigInt(1) << bits.size)).map { i =>
val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) }
AddressRange(off, size)
}
}
}
object AddressSet
{
val everything = AddressSet(0, -1)
def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = {
if (size == 0) tail.reverse else {
val maxBaseAlignment = base & (-base) // 0 for infinite (LSB)
val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size
val step =
if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment)
maxSizeAlignment else maxBaseAlignment
misaligned(base+step, size-step, AddressSet(base, step-1) +: tail)
}
}
def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = {
// Pair terms up by ignoring 'bit'
seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) =>
if (seq.size == 1) {
seq.head // singleton -> unaffected
} else {
key.copy(mask = key.mask | bit) // pair - widen mask by bit
}
}.toList
}
def unify(seq: Seq[AddressSet]): Seq[AddressSet] = {
val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _)
AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted
}
def enumerateMask(mask: BigInt): Seq[BigInt] = {
def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] =
if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail)
helper(0, Nil)
}
def enumerateBits(mask: BigInt): Seq[BigInt] = {
def helper(x: BigInt): Seq[BigInt] = {
if (x == 0) {
Nil
} else {
val bit = x & (-x)
bit +: helper(x & ~bit)
}
}
helper(mask)
}
}
case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean)
{
require (depth >= 0, "Buffer depth must be >= 0")
def isDefined = depth > 0
def latency = if (isDefined && !flow) 1 else 0
def apply[T <: Data](x: DecoupledIO[T]) =
if (isDefined) Queue(x, depth, flow=flow, pipe=pipe)
else x
def irrevocable[T <: Data](x: ReadyValidIO[T]) =
if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe)
else x
def sq[T <: Data](x: DecoupledIO[T]) =
if (!isDefined) x else {
val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe))
sq.io.enq <> x
sq.io.deq
}
override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "")
}
object BufferParams
{
implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false)
val default = BufferParams(2)
val none = BufferParams(0)
val flow = BufferParams(1, true, false)
val pipe = BufferParams(1, false, true)
}
case class TriStateValue(value: Boolean, set: Boolean)
{
def update(orig: Boolean) = if (set) value else orig
}
object TriStateValue
{
implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true)
def unset = TriStateValue(false, false)
}
trait DirectedBuffers[T] {
def copyIn(x: BufferParams): T
def copyOut(x: BufferParams): T
def copyInOut(x: BufferParams): T
}
trait IdMapEntry {
def name: String
def from: IdRange
def to: IdRange
def isCache: Boolean
def requestFifo: Boolean
def maxTransactionsInFlight: Option[Int]
def pretty(fmt: String) =
if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5
fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "")
} else {
fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "")
}
}
abstract class IdMap[T <: IdMapEntry] {
protected val fmt: String
val mapping: Seq[T]
def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n")
}
File Edges.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.util._
class TLEdge(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdgeParameters(client, manager, params, sourceInfo)
{
def isAligned(address: UInt, lgSize: UInt): Bool = {
if (maxLgSize == 0) true.B else {
val mask = UIntToOH1(lgSize, maxLgSize)
(address & mask) === 0.U
}
}
def mask(address: UInt, lgSize: UInt): UInt =
MaskGen(address, lgSize, manager.beatBytes)
def staticHasData(bundle: TLChannel): Option[Boolean] = {
bundle match {
case _:TLBundleA => {
// Do there exist A messages with Data?
val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial
// Do there exist A messages without Data?
val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint
// Statically optimize the case where hasData is a constant
if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None
}
case _:TLBundleB => {
// Do there exist B messages with Data?
val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial
// Do there exist B messages without Data?
val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint
// Statically optimize the case where hasData is a constant
if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None
}
case _:TLBundleC => {
// Do there eixst C messages with Data?
val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe
// Do there exist C messages without Data?
val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe
if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None
}
case _:TLBundleD => {
// Do there eixst D messages with Data?
val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB
// Do there exist D messages without Data?
val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT
if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None
}
case _:TLBundleE => Some(false)
}
}
def isRequest(x: TLChannel): Bool = {
x match {
case a: TLBundleA => true.B
case b: TLBundleB => true.B
case c: TLBundleC => c.opcode(2) && c.opcode(1)
// opcode === TLMessages.Release ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(2) && !d.opcode(1)
// opcode === TLMessages.Grant ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
}
def isResponse(x: TLChannel): Bool = {
x match {
case a: TLBundleA => false.B
case b: TLBundleB => false.B
case c: TLBundleC => !c.opcode(2) || !c.opcode(1)
// opcode =/= TLMessages.Release &&
// opcode =/= TLMessages.ReleaseData
case d: TLBundleD => true.B // Grant isResponse + isRequest
case e: TLBundleE => true.B
}
}
def hasData(x: TLChannel): Bool = {
val opdata = x match {
case a: TLBundleA => !a.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case b: TLBundleB => !b.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case c: TLBundleC => c.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.ProbeAckData ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
staticHasData(x).map(_.B).getOrElse(opdata)
}
def opcode(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.opcode
case b: TLBundleB => b.opcode
case c: TLBundleC => c.opcode
case d: TLBundleD => d.opcode
}
}
def param(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.param
case b: TLBundleB => b.param
case c: TLBundleC => c.param
case d: TLBundleD => d.param
}
}
def size(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.size
case b: TLBundleB => b.size
case c: TLBundleC => c.size
case d: TLBundleD => d.size
}
}
def data(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.data
case b: TLBundleB => b.data
case c: TLBundleC => c.data
case d: TLBundleD => d.data
}
}
def corrupt(x: TLDataChannel): Bool = {
x match {
case a: TLBundleA => a.corrupt
case b: TLBundleB => b.corrupt
case c: TLBundleC => c.corrupt
case d: TLBundleD => d.corrupt
}
}
def mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.mask
case b: TLBundleB => b.mask
case c: TLBundleC => mask(c.address, c.size)
}
}
def full_mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => mask(a.address, a.size)
case b: TLBundleB => mask(b.address, b.size)
case c: TLBundleC => mask(c.address, c.size)
}
}
def address(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.address
case b: TLBundleB => b.address
case c: TLBundleC => c.address
}
}
def source(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.source
case b: TLBundleB => b.source
case c: TLBundleC => c.source
case d: TLBundleD => d.source
}
}
def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes)
def addr_lo(x: UInt): UInt =
if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0)
def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x))
def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x))
def numBeats(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 1.U
case bundle: TLDataChannel => {
val hasData = this.hasData(bundle)
val size = this.size(bundle)
val cutoff = log2Ceil(manager.beatBytes)
val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U
val decode = UIntToOH(size, maxLgSize+1) >> cutoff
Mux(hasData, decode | small.asUInt, 1.U)
}
}
}
def numBeats1(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 0.U
case bundle: TLDataChannel => {
if (maxLgSize == 0) {
0.U
} else {
val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes)
Mux(hasData(bundle), decode, 0.U)
}
}
}
}
def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val beats1 = numBeats1(bits)
val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W))
val counter1 = counter - 1.U
val first = counter === 0.U
val last = counter === 1.U || beats1 === 0.U
val done = last && fire
val count = (beats1 & ~counter1)
when (fire) {
counter := Mux(first, beats1, counter1)
}
(first, last, done, count)
}
def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1
def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire)
def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid)
def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2
def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire)
def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid)
def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3
def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire)
def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid)
def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3)
}
def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire)
def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid)
def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4)
}
def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire)
def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid)
def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes))
}
def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire)
def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid)
// Does the request need T permissions to be executed?
def needT(a: TLBundleA): Bool = {
val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLPermissions.NtoB -> false.B,
TLPermissions.NtoT -> true.B,
TLPermissions.BtoT -> true.B))
MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array(
TLMessages.PutFullData -> true.B,
TLMessages.PutPartialData -> true.B,
TLMessages.ArithmeticData -> true.B,
TLMessages.LogicalData -> true.B,
TLMessages.Get -> false.B,
TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLHints.PREFETCH_READ -> false.B,
TLHints.PREFETCH_WRITE -> true.B)),
TLMessages.AcquireBlock -> acq_needT,
TLMessages.AcquirePerm -> acq_needT))
}
// This is a very expensive circuit; use only if you really mean it!
def inFlight(x: TLBundle): (UInt, UInt) = {
val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W))
val bce = manager.anySupportAcquireB && client.anySupportProbe
val (a_first, a_last, _) = firstlast(x.a)
val (b_first, b_last, _) = firstlast(x.b)
val (c_first, c_last, _) = firstlast(x.c)
val (d_first, d_last, _) = firstlast(x.d)
val (e_first, e_last, _) = firstlast(x.e)
val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits))
val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits))
val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits))
val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits))
val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits))
val a_inc = x.a.fire && a_first && a_request
val b_inc = x.b.fire && b_first && b_request
val c_inc = x.c.fire && c_first && c_request
val d_inc = x.d.fire && d_first && d_request
val e_inc = x.e.fire && e_first && e_request
val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil))
val a_dec = x.a.fire && a_last && a_response
val b_dec = x.b.fire && b_last && b_response
val c_dec = x.c.fire && c_last && c_response
val d_dec = x.d.fire && d_last && d_response
val e_dec = x.e.fire && e_last && e_response
val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil))
val next_flight = flight + PopCount(inc) - PopCount(dec)
flight := next_flight
(flight, next_flight)
}
def prettySourceMapping(context: String): String = {
s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n"
}
}
class TLEdgeOut(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
// Transfers
def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquireBlock
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquirePerm
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.Release
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ReleaseData
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) =
Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B)
def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAck
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions, data)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAckData
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B)
def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink)
def GrantAck(toSink: UInt): TLBundleE = {
val e = Wire(new TLBundleE(bundle))
e.sink := toSink
e
}
// Accesses
def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsGetFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Get
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutFullFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutFullData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, mask, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutPartialFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutPartialData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = {
require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsArithmeticFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.ArithmeticData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsLogicalFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.LogicalData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = {
require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsHintFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Hint
a.param := param
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data)
def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAckData
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size)
def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.HintAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
}
class TLEdgeIn(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = {
val todo = x.filter(!_.isEmpty)
val heads = todo.map(_.head)
val tails = todo.map(_.tail)
if (todo.isEmpty) Nil else { heads +: myTranspose(tails) }
}
// Transfers
def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = {
require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}")
val legal = client.supportsProbe(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Probe
b.param := capPermissions
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.Grant
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.GrantData
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B)
def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.ReleaseAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
// Accesses
def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = {
require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsGet(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Get
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsPutFull(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutFullData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, mask, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsPutPartial(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutPartialData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsArithmetic(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.ArithmeticData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsLogical(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.LogicalData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = {
require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsHint(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Hint
b.param := param
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size)
def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied)
def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data)
def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAckData
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B)
def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied)
def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B)
def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.HintAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
}
| module TLMonitor_29( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14]
input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input [4:0] io_in_a_bits_source, // @[Monitor.scala:20:14]
input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14]
input io_in_a_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14]
input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input [4:0] io_in_d_bits_source, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_sink, // @[Monitor.scala:20:14]
input io_in_d_bits_denied, // @[Monitor.scala:20:14]
input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14]
input io_in_d_bits_corrupt // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7]
wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7]
wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7]
wire [4:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7]
wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7]
wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7]
wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7]
wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7]
wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7]
wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7]
wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7]
wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7]
wire [4:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7]
wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7]
wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7]
wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7]
wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35]
wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36]
wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25]
wire c_first_done = 1'h0; // @[Edges.scala:233:22]
wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47]
wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95]
wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71]
wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44]
wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36]
wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51]
wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40]
wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55]
wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88]
wire [8:0] c_first_beats1_decode = 9'h0; // @[Edges.scala:220:59]
wire [8:0] c_first_beats1 = 9'h0; // @[Edges.scala:221:14]
wire [8:0] _c_first_count_T = 9'h0; // @[Edges.scala:234:27]
wire [8:0] c_first_count = 9'h0; // @[Edges.scala:234:25]
wire [8:0] _c_first_counter_T = 9'h0; // @[Edges.scala:236:21]
wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_17 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_21 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_23 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_31 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_33 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_37 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_39 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_43 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_45 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_49 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_51 = 1'h1; // @[Parameters.scala:57:20]
wire sink_ok = 1'h1; // @[Monitor.scala:309:31]
wire c_first = 1'h1; // @[Edges.scala:231:25]
wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire c_first_last = 1'h1; // @[Edges.scala:232:33]
wire [8:0] c_first_counter1 = 9'h1FF; // @[Edges.scala:230:28]
wire [9:0] _c_first_counter1_T = 10'h3FF; // @[Edges.scala:230:28]
wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_first_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_first_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_first_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_first_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_set_wo_ready_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_set_wo_ready_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_opcodes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_opcodes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_sizes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_sizes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_opcodes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_opcodes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_sizes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_sizes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_probe_ack_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_probe_ack_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_probe_ack_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_probe_ack_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _same_cycle_resp_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _same_cycle_resp_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _same_cycle_resp_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _same_cycle_resp_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _same_cycle_resp_WIRE_4_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _same_cycle_resp_WIRE_5_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [4:0] _c_first_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _c_first_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _c_first_WIRE_2_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _c_first_WIRE_3_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] c_sizes_set_interm = 5'h0; // @[Monitor.scala:755:40]
wire [4:0] _c_set_wo_ready_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _c_set_wo_ready_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _c_set_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _c_set_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _c_opcodes_set_interm_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _c_opcodes_set_interm_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _c_sizes_set_interm_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _c_sizes_set_interm_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _c_sizes_set_interm_T = 5'h0; // @[Monitor.scala:766:51]
wire [4:0] _c_opcodes_set_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _c_opcodes_set_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _c_sizes_set_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _c_sizes_set_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _c_probe_ack_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _c_probe_ack_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _c_probe_ack_WIRE_2_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _c_probe_ack_WIRE_3_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _same_cycle_resp_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _same_cycle_resp_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _same_cycle_resp_WIRE_2_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _same_cycle_resp_WIRE_3_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _same_cycle_resp_WIRE_4_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _same_cycle_resp_WIRE_5_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_first_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_first_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_first_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_first_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40]
wire [3:0] _c_set_wo_ready_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_set_wo_ready_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53]
wire [3:0] _c_sizes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_sizes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_opcodes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_sizes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_sizes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_probe_ack_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_probe_ack_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_probe_ack_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_probe_ack_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_4_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_5_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57]
wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57]
wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57]
wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57]
wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57]
wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57]
wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57]
wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57]
wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51]
wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51]
wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51]
wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51]
wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [259:0] _c_sizes_set_T_1 = 260'h0; // @[Monitor.scala:768:52]
wire [7:0] _c_opcodes_set_T = 8'h0; // @[Monitor.scala:767:79]
wire [7:0] _c_sizes_set_T = 8'h0; // @[Monitor.scala:768:77]
wire [258:0] _c_opcodes_set_T_1 = 259'h0; // @[Monitor.scala:767:54]
wire [4:0] _c_sizes_set_interm_T_1 = 5'h1; // @[Monitor.scala:766:59]
wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61]
wire [31:0] _c_set_wo_ready_T = 32'h1; // @[OneHot.scala:58:35]
wire [31:0] _c_set_T = 32'h1; // @[OneHot.scala:58:35]
wire [135:0] c_sizes_set = 136'h0; // @[Monitor.scala:741:34]
wire [67:0] c_opcodes_set = 68'h0; // @[Monitor.scala:740:34]
wire [16:0] c_set = 17'h0; // @[Monitor.scala:738:34]
wire [16:0] c_set_wo_ready = 17'h0; // @[Monitor.scala:739:34]
wire [11:0] _c_first_beats1_decode_T_2 = 12'h0; // @[package.scala:243:46]
wire [11:0] _c_first_beats1_decode_T_1 = 12'hFFF; // @[package.scala:243:76]
wire [26:0] _c_first_beats1_decode_T = 27'hFFF; // @[package.scala:243:71]
wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42]
wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42]
wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42]
wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117]
wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48]
wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119]
wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48]
wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123]
wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48]
wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123]
wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48]
wire [3:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34]
wire [4:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_uncommonBits_T_4 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_uncommonBits_T_5 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_uncommonBits_T_6 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_uncommonBits_T_7 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire _source_ok_T = io_in_a_bits_source_0 == 5'h10; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] _source_ok_T_1 = io_in_a_bits_source_0[4:2]; // @[Monitor.scala:36:7]
wire [2:0] _source_ok_T_7 = io_in_a_bits_source_0[4:2]; // @[Monitor.scala:36:7]
wire [2:0] _source_ok_T_13 = io_in_a_bits_source_0[4:2]; // @[Monitor.scala:36:7]
wire [2:0] _source_ok_T_19 = io_in_a_bits_source_0[4:2]; // @[Monitor.scala:36:7]
wire _source_ok_T_2 = _source_ok_T_1 == 3'h0; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_4 = _source_ok_T_2; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_6 = _source_ok_T_4; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_8 = _source_ok_T_7 == 3'h1; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_10 = _source_ok_T_8; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_12 = _source_ok_T_10; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_2 = _source_ok_T_12; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_14 = _source_ok_T_13 == 3'h2; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_16 = _source_ok_T_14; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_18 = _source_ok_T_16; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_3 = _source_ok_T_18; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_20 = _source_ok_T_19 == 3'h3; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_22 = _source_ok_T_20; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_24 = _source_ok_T_22; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_4 = _source_ok_T_24; // @[Parameters.scala:1138:31]
wire _source_ok_T_25 = _source_ok_WIRE_0 | _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_26 = _source_ok_T_25 | _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_27 = _source_ok_T_26 | _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46]
wire source_ok = _source_ok_T_27 | _source_ok_WIRE_4; // @[Parameters.scala:1138:31, :1139:46]
wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71]
wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71]
assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71]
wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71]
assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71]
wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71]
wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}]
wire [31:0] _is_aligned_T = {20'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46]
wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}]
wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12]
wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}]
wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27]
wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 4'h2; // @[Misc.scala:206:21]
wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26]
wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}]
wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}]
wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26]
wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26]
wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26]
wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20]
wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}]
wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}]
wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}]
wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}]
wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10]
wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10]
wire [1:0] uncommonBits = _uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_4 = _uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_5 = _uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_6 = _uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_7 = _uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_9 = _uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_10 = _uncommonBits_T_10[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_11 = _uncommonBits_T_11[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_12 = _uncommonBits_T_12[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_13 = _uncommonBits_T_13[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_14 = _uncommonBits_T_14[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_16 = _uncommonBits_T_16[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_17 = _uncommonBits_T_17[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_18 = _uncommonBits_T_18[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_19 = _uncommonBits_T_19[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_20 = _uncommonBits_T_20[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_21 = _uncommonBits_T_21[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_22 = _uncommonBits_T_22[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_23 = _uncommonBits_T_23[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_24 = _uncommonBits_T_24[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_25 = _uncommonBits_T_25[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_26 = _uncommonBits_T_26[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_27 = _uncommonBits_T_27[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_28 = _uncommonBits_T_28[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_29 = _uncommonBits_T_29[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_30 = _uncommonBits_T_30[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_31 = _uncommonBits_T_31[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_32 = _uncommonBits_T_32[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_33 = _uncommonBits_T_33[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_34 = _uncommonBits_T_34[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_35 = _uncommonBits_T_35[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_28 = io_in_d_bits_source_0 == 5'h10; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_0 = _source_ok_T_28; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] _source_ok_T_29 = io_in_d_bits_source_0[4:2]; // @[Monitor.scala:36:7]
wire [2:0] _source_ok_T_35 = io_in_d_bits_source_0[4:2]; // @[Monitor.scala:36:7]
wire [2:0] _source_ok_T_41 = io_in_d_bits_source_0[4:2]; // @[Monitor.scala:36:7]
wire [2:0] _source_ok_T_47 = io_in_d_bits_source_0[4:2]; // @[Monitor.scala:36:7]
wire _source_ok_T_30 = _source_ok_T_29 == 3'h0; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_32 = _source_ok_T_30; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_34 = _source_ok_T_32; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_1 = _source_ok_T_34; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_36 = _source_ok_T_35 == 3'h1; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_38 = _source_ok_T_36; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_40 = _source_ok_T_38; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_2 = _source_ok_T_40; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_42 = _source_ok_T_41 == 3'h2; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_44 = _source_ok_T_42; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_46 = _source_ok_T_44; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_3 = _source_ok_T_46; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_48 = _source_ok_T_47 == 3'h3; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_50 = _source_ok_T_48; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_52 = _source_ok_T_50; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_4 = _source_ok_T_52; // @[Parameters.scala:1138:31]
wire _source_ok_T_53 = _source_ok_WIRE_1_0 | _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_54 = _source_ok_T_53 | _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_55 = _source_ok_T_54 | _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46]
wire source_ok_1 = _source_ok_T_55 | _source_ok_WIRE_1_4; // @[Parameters.scala:1138:31, :1139:46]
wire _T_1492 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35]
wire _a_first_T; // @[Decoupled.scala:51:35]
assign _a_first_T = _T_1492; // @[Decoupled.scala:51:35]
wire _a_first_T_1; // @[Decoupled.scala:51:35]
assign _a_first_T_1 = _T_1492; // @[Decoupled.scala:51:35]
wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [8:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46]
wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}]
wire [8:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [8:0] a_first_counter; // @[Edges.scala:229:27]
wire [9:0] _a_first_counter1_T = {1'h0, a_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] a_first_counter1 = _a_first_counter1_T[8:0]; // @[Edges.scala:230:28]
wire a_first = a_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T = a_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_1 = a_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35]
wire [8:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [8:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [2:0] param; // @[Monitor.scala:388:22]
reg [3:0] size; // @[Monitor.scala:389:22]
reg [4:0] source; // @[Monitor.scala:390:22]
reg [31:0] address; // @[Monitor.scala:391:22]
wire _T_1565 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35]
wire _d_first_T; // @[Decoupled.scala:51:35]
assign _d_first_T = _T_1565; // @[Decoupled.scala:51:35]
wire _d_first_T_1; // @[Decoupled.scala:51:35]
assign _d_first_T_1 = _T_1565; // @[Decoupled.scala:51:35]
wire _d_first_T_2; // @[Decoupled.scala:51:35]
assign _d_first_T_2 = _T_1565; // @[Decoupled.scala:51:35]
wire [26:0] _GEN_0 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71]
assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71]
wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [8:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46]
wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire [8:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [8:0] d_first_counter; // @[Edges.scala:229:27]
wire [9:0] _d_first_counter1_T = {1'h0, d_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] d_first_counter1 = _d_first_counter1_T[8:0]; // @[Edges.scala:230:28]
wire d_first = d_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T = d_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_1 = d_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35]
wire [8:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [8:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [1:0] param_1; // @[Monitor.scala:539:22]
reg [3:0] size_1; // @[Monitor.scala:540:22]
reg [4:0] source_1; // @[Monitor.scala:541:22]
reg [2:0] sink; // @[Monitor.scala:542:22]
reg denied; // @[Monitor.scala:543:22]
reg [16:0] inflight; // @[Monitor.scala:614:27]
reg [67:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [135:0] inflight_sizes; // @[Monitor.scala:618:33]
wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [8:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46]
wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}]
wire [8:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [8:0] a_first_counter_1; // @[Edges.scala:229:27]
wire [9:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] a_first_counter1_1 = _a_first_counter1_T_1[8:0]; // @[Edges.scala:230:28]
wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T_2 = a_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_3 = a_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35]
wire [8:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [8:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [8:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46]
wire [8:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [8:0] d_first_counter_1; // @[Edges.scala:229:27]
wire [9:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] d_first_counter1_1 = _d_first_counter1_T_1[8:0]; // @[Edges.scala:230:28]
wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_2 = d_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_3 = d_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35]
wire [8:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [8:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [16:0] a_set; // @[Monitor.scala:626:34]
wire [16:0] a_set_wo_ready; // @[Monitor.scala:627:34]
wire [67:0] a_opcodes_set; // @[Monitor.scala:630:33]
wire [135:0] a_sizes_set; // @[Monitor.scala:632:31]
wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35]
wire [7:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69]
wire [7:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69]
assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69]
wire [7:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101]
assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101]
wire [7:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69]
assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69]
wire [7:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101]
assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101]
wire [67:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}]
wire [67:0] _a_opcode_lookup_T_6 = {64'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}]
wire [67:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[67:1]}; // @[Monitor.scala:637:{97,152}]
assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}]
wire [7:0] a_size_lookup; // @[Monitor.scala:639:33]
wire [7:0] _GEN_2 = {io_in_d_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :641:65]
wire [7:0] _a_size_lookup_T; // @[Monitor.scala:641:65]
assign _a_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65]
wire [7:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99]
assign _d_sizes_clr_T_4 = _GEN_2; // @[Monitor.scala:641:65, :681:99]
wire [7:0] _c_size_lookup_T; // @[Monitor.scala:750:67]
assign _c_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65, :750:67]
wire [7:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99]
assign _d_sizes_clr_T_10 = _GEN_2; // @[Monitor.scala:641:65, :791:99]
wire [135:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}]
wire [135:0] _a_size_lookup_T_6 = {128'h0, _a_size_lookup_T_1[7:0]}; // @[Monitor.scala:641:{40,91}]
wire [135:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[135:1]}; // @[Monitor.scala:641:{91,144}]
assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}]
wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40]
wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38]
wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44]
wire [31:0] _GEN_3 = 32'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35]
wire [31:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35]
assign _a_set_wo_ready_T = _GEN_3; // @[OneHot.scala:58:35]
wire [31:0] _a_set_T; // @[OneHot.scala:58:35]
assign _a_set_T = _GEN_3; // @[OneHot.scala:58:35]
assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[16:0] : 17'h0; // @[OneHot.scala:58:35]
wire _T_1418 = _T_1492 & a_first_1; // @[Decoupled.scala:51:35]
assign a_set = _T_1418 ? _a_set_T[16:0] : 17'h0; // @[OneHot.scala:58:35]
wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53]
wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}]
assign a_opcodes_set_interm = _T_1418 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}]
wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51]
wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}]
assign a_sizes_set_interm = _T_1418 ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}]
wire [7:0] _a_opcodes_set_T = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79]
wire [258:0] _a_opcodes_set_T_1 = {255'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}]
assign a_opcodes_set = _T_1418 ? _a_opcodes_set_T_1[67:0] : 68'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}]
wire [7:0] _a_sizes_set_T = {io_in_a_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :660:77]
wire [259:0] _a_sizes_set_T_1 = {255'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}]
assign a_sizes_set = _T_1418 ? _a_sizes_set_T_1[135:0] : 136'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}]
wire [16:0] d_clr; // @[Monitor.scala:664:34]
wire [16:0] d_clr_wo_ready; // @[Monitor.scala:665:34]
wire [67:0] d_opcodes_clr; // @[Monitor.scala:668:33]
wire [135:0] d_sizes_clr; // @[Monitor.scala:670:31]
wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46]
wire d_release_ack; // @[Monitor.scala:673:46]
assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46]
wire d_release_ack_1; // @[Monitor.scala:783:46]
assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46]
wire _T_1464 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26]
wire [31:0] _GEN_5 = 32'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35]
wire [31:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35]
wire [31:0] _d_clr_T; // @[OneHot.scala:58:35]
assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35]
wire [31:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35]
wire [31:0] _d_clr_T_1; // @[OneHot.scala:58:35]
assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35]
assign d_clr_wo_ready = _T_1464 & ~d_release_ack ? _d_clr_wo_ready_T[16:0] : 17'h0; // @[OneHot.scala:58:35]
wire _T_1433 = _T_1565 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35]
assign d_clr = _T_1433 ? _d_clr_T[16:0] : 17'h0; // @[OneHot.scala:58:35]
wire [270:0] _d_opcodes_clr_T_5 = 271'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}]
assign d_opcodes_clr = _T_1433 ? _d_opcodes_clr_T_5[67:0] : 68'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}]
wire [270:0] _d_sizes_clr_T_5 = 271'hFF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}]
assign d_sizes_clr = _T_1433 ? _d_sizes_clr_T_5[135:0] : 136'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}]
wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}]
wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113]
wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}]
wire [16:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27]
wire [16:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38]
wire [16:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}]
wire [67:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43]
wire [67:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62]
wire [67:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}]
wire [135:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39]
wire [135:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56]
wire [135:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26]
wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26]
reg [16:0] inflight_1; // @[Monitor.scala:726:35]
wire [16:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35]
reg [67:0] inflight_opcodes_1; // @[Monitor.scala:727:35]
wire [67:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43]
reg [135:0] inflight_sizes_1; // @[Monitor.scala:728:35]
wire [135:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41]
wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}]
wire [8:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:3]; // @[package.scala:243:46]
wire [8:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [8:0] d_first_counter_2; // @[Edges.scala:229:27]
wire [9:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] d_first_counter1_2 = _d_first_counter1_T_2[8:0]; // @[Edges.scala:230:28]
wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_4 = d_first_counter_2 == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_5 = d_first_beats1_2 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35]
wire [8:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27]
wire [8:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35]
wire [7:0] c_size_lookup; // @[Monitor.scala:748:35]
wire [67:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}]
wire [67:0] _c_opcode_lookup_T_6 = {64'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}]
wire [67:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[67:1]}; // @[Monitor.scala:749:{97,152}]
assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}]
wire [135:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}]
wire [135:0] _c_size_lookup_T_6 = {128'h0, _c_size_lookup_T_1[7:0]}; // @[Monitor.scala:750:{42,93}]
wire [135:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[135:1]}; // @[Monitor.scala:750:{93,146}]
assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}]
wire [16:0] d_clr_1; // @[Monitor.scala:774:34]
wire [16:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34]
wire [67:0] d_opcodes_clr_1; // @[Monitor.scala:776:34]
wire [135:0] d_sizes_clr_1; // @[Monitor.scala:777:34]
wire _T_1536 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26]
assign d_clr_wo_ready_1 = _T_1536 & d_release_ack_1 ? _d_clr_wo_ready_T_1[16:0] : 17'h0; // @[OneHot.scala:58:35]
wire _T_1518 = _T_1565 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35]
assign d_clr_1 = _T_1518 ? _d_clr_T_1[16:0] : 17'h0; // @[OneHot.scala:58:35]
wire [270:0] _d_opcodes_clr_T_11 = 271'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}]
assign d_opcodes_clr_1 = _T_1518 ? _d_opcodes_clr_T_11[67:0] : 68'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}]
wire [270:0] _d_sizes_clr_T_11 = 271'hFF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}]
assign d_sizes_clr_1 = _T_1518 ? _d_sizes_clr_T_11[135:0] : 136'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}]
wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 5'h0; // @[Monitor.scala:36:7, :795:113]
wire [16:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46]
wire [16:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}]
wire [67:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62]
wire [67:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}]
wire [135:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58]
wire [135:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27] |
Generate the Verilog code corresponding to the following Chisel files.
File PE.scala:
// See README.md for license details.
package gemmini
import chisel3._
import chisel3.util._
class PEControl[T <: Data : Arithmetic](accType: T) extends Bundle {
val dataflow = UInt(1.W) // TODO make this an Enum
val propagate = UInt(1.W) // Which register should be propagated (and which should be accumulated)?
val shift = UInt(log2Up(accType.getWidth).W) // TODO this isn't correct for Floats
}
class MacUnit[T <: Data](inputType: T, cType: T, dType: T) (implicit ev: Arithmetic[T]) extends Module {
import ev._
val io = IO(new Bundle {
val in_a = Input(inputType)
val in_b = Input(inputType)
val in_c = Input(cType)
val out_d = Output(dType)
})
io.out_d := io.in_c.mac(io.in_a, io.in_b)
}
// TODO update documentation
/**
* A PE implementing a MAC operation. Configured as fully combinational when integrated into a Mesh.
* @param width Data width of operands
*/
class PE[T <: Data](inputType: T, outputType: T, accType: T, df: Dataflow.Value, max_simultaneous_matmuls: Int)
(implicit ev: Arithmetic[T]) extends Module { // Debugging variables
import ev._
val io = IO(new Bundle {
val in_a = Input(inputType)
val in_b = Input(outputType)
val in_d = Input(outputType)
val out_a = Output(inputType)
val out_b = Output(outputType)
val out_c = Output(outputType)
val in_control = Input(new PEControl(accType))
val out_control = Output(new PEControl(accType))
val in_id = Input(UInt(log2Up(max_simultaneous_matmuls).W))
val out_id = Output(UInt(log2Up(max_simultaneous_matmuls).W))
val in_last = Input(Bool())
val out_last = Output(Bool())
val in_valid = Input(Bool())
val out_valid = Output(Bool())
val bad_dataflow = Output(Bool())
})
val cType = if (df == Dataflow.WS) inputType else accType
// When creating PEs that support multiple dataflows, the
// elaboration/synthesis tools often fail to consolidate and de-duplicate
// MAC units. To force mac circuitry to be re-used, we create a "mac_unit"
// module here which just performs a single MAC operation
val mac_unit = Module(new MacUnit(inputType,
if (df == Dataflow.WS) outputType else accType, outputType))
val a = io.in_a
val b = io.in_b
val d = io.in_d
val c1 = Reg(cType)
val c2 = Reg(cType)
val dataflow = io.in_control.dataflow
val prop = io.in_control.propagate
val shift = io.in_control.shift
val id = io.in_id
val last = io.in_last
val valid = io.in_valid
io.out_a := a
io.out_control.dataflow := dataflow
io.out_control.propagate := prop
io.out_control.shift := shift
io.out_id := id
io.out_last := last
io.out_valid := valid
mac_unit.io.in_a := a
val last_s = RegEnable(prop, valid)
val flip = last_s =/= prop
val shift_offset = Mux(flip, shift, 0.U)
// Which dataflow are we using?
val OUTPUT_STATIONARY = Dataflow.OS.id.U(1.W)
val WEIGHT_STATIONARY = Dataflow.WS.id.U(1.W)
// Is c1 being computed on, or propagated forward (in the output-stationary dataflow)?
val COMPUTE = 0.U(1.W)
val PROPAGATE = 1.U(1.W)
io.bad_dataflow := false.B
when ((df == Dataflow.OS).B || ((df == Dataflow.BOTH).B && dataflow === OUTPUT_STATIONARY)) {
when(prop === PROPAGATE) {
io.out_c := (c1 >> shift_offset).clippedToWidthOf(outputType)
io.out_b := b
mac_unit.io.in_b := b.asTypeOf(inputType)
mac_unit.io.in_c := c2
c2 := mac_unit.io.out_d
c1 := d.withWidthOf(cType)
}.otherwise {
io.out_c := (c2 >> shift_offset).clippedToWidthOf(outputType)
io.out_b := b
mac_unit.io.in_b := b.asTypeOf(inputType)
mac_unit.io.in_c := c1
c1 := mac_unit.io.out_d
c2 := d.withWidthOf(cType)
}
}.elsewhen ((df == Dataflow.WS).B || ((df == Dataflow.BOTH).B && dataflow === WEIGHT_STATIONARY)) {
when(prop === PROPAGATE) {
io.out_c := c1
mac_unit.io.in_b := c2.asTypeOf(inputType)
mac_unit.io.in_c := b
io.out_b := mac_unit.io.out_d
c1 := d
}.otherwise {
io.out_c := c2
mac_unit.io.in_b := c1.asTypeOf(inputType)
mac_unit.io.in_c := b
io.out_b := mac_unit.io.out_d
c2 := d
}
}.otherwise {
io.bad_dataflow := true.B
//assert(false.B, "unknown dataflow")
io.out_c := DontCare
io.out_b := DontCare
mac_unit.io.in_b := b.asTypeOf(inputType)
mac_unit.io.in_c := c2
}
when (!valid) {
c1 := c1
c2 := c2
mac_unit.io.in_b := DontCare
mac_unit.io.in_c := DontCare
}
}
File Arithmetic.scala:
// A simple type class for Chisel datatypes that can add and multiply. To add your own type, simply create your own:
// implicit MyTypeArithmetic extends Arithmetic[MyType] { ... }
package gemmini
import chisel3._
import chisel3.util._
import hardfloat._
// Bundles that represent the raw bits of custom datatypes
case class Float(expWidth: Int, sigWidth: Int) extends Bundle {
val bits = UInt((expWidth + sigWidth).W)
val bias: Int = (1 << (expWidth-1)) - 1
}
case class DummySInt(w: Int) extends Bundle {
val bits = UInt(w.W)
def dontCare: DummySInt = {
val o = Wire(new DummySInt(w))
o.bits := 0.U
o
}
}
// The Arithmetic typeclass which implements various arithmetic operations on custom datatypes
abstract class Arithmetic[T <: Data] {
implicit def cast(t: T): ArithmeticOps[T]
}
abstract class ArithmeticOps[T <: Data](self: T) {
def *(t: T): T
def mac(m1: T, m2: T): T // Returns (m1 * m2 + self)
def +(t: T): T
def -(t: T): T
def >>(u: UInt): T // This is a rounding shift! Rounds away from 0
def >(t: T): Bool
def identity: T
def withWidthOf(t: T): T
def clippedToWidthOf(t: T): T // Like "withWidthOf", except that it saturates
def relu: T
def zero: T
def minimum: T
// Optional parameters, which only need to be defined if you want to enable various optimizations for transformers
def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[T])] = None
def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[T])] = None
def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = None
def mult_with_reciprocal[U <: Data](reciprocal: U) = self
}
object Arithmetic {
implicit object UIntArithmetic extends Arithmetic[UInt] {
override implicit def cast(self: UInt) = new ArithmeticOps(self) {
override def *(t: UInt) = self * t
override def mac(m1: UInt, m2: UInt) = m1 * m2 + self
override def +(t: UInt) = self + t
override def -(t: UInt) = self - t
override def >>(u: UInt) = {
// The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm
// TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here?
val point_five = Mux(u === 0.U, 0.U, self(u - 1.U))
val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U
val ones_digit = self(u)
val r = point_five & (zeros | ones_digit)
(self >> u).asUInt + r
}
override def >(t: UInt): Bool = self > t
override def withWidthOf(t: UInt) = self.asTypeOf(t)
override def clippedToWidthOf(t: UInt) = {
val sat = ((1 << (t.getWidth-1))-1).U
Mux(self > sat, sat, self)(t.getWidth-1, 0)
}
override def relu: UInt = self
override def zero: UInt = 0.U
override def identity: UInt = 1.U
override def minimum: UInt = 0.U
}
}
implicit object SIntArithmetic extends Arithmetic[SInt] {
override implicit def cast(self: SInt) = new ArithmeticOps(self) {
override def *(t: SInt) = self * t
override def mac(m1: SInt, m2: SInt) = m1 * m2 + self
override def +(t: SInt) = self + t
override def -(t: SInt) = self - t
override def >>(u: UInt) = {
// The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm
// TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here?
val point_five = Mux(u === 0.U, 0.U, self(u - 1.U))
val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U
val ones_digit = self(u)
val r = (point_five & (zeros | ones_digit)).asBool
(self >> u).asSInt + Mux(r, 1.S, 0.S)
}
override def >(t: SInt): Bool = self > t
override def withWidthOf(t: SInt) = {
if (self.getWidth >= t.getWidth)
self(t.getWidth-1, 0).asSInt
else {
val sign_bits = t.getWidth - self.getWidth
val sign = self(self.getWidth-1)
Cat(Cat(Seq.fill(sign_bits)(sign)), self).asTypeOf(t)
}
}
override def clippedToWidthOf(t: SInt): SInt = {
val maxsat = ((1 << (t.getWidth-1))-1).S
val minsat = (-(1 << (t.getWidth-1))).S
MuxCase(self, Seq((self > maxsat) -> maxsat, (self < minsat) -> minsat))(t.getWidth-1, 0).asSInt
}
override def relu: SInt = Mux(self >= 0.S, self, 0.S)
override def zero: SInt = 0.S
override def identity: SInt = 1.S
override def minimum: SInt = (-(1 << (self.getWidth-1))).S
override def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = {
// TODO this uses a floating point divider, but we should use an integer divider instead
val input = Wire(Decoupled(denom_t.cloneType))
val output = Wire(Decoupled(self.cloneType))
// We translate our integer to floating-point form so that we can use the hardfloat divider
val expWidth = log2Up(self.getWidth) + 1
val sigWidth = self.getWidth
def sin_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def uin_to_float(x: UInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := false.B
in_to_rec_fn.io.in := x
in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def float_to_in(x: UInt) = {
val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth))
rec_fn_to_in.io.signedOut := true.B
rec_fn_to_in.io.in := x
rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
rec_fn_to_in.io.out.asSInt
}
val self_rec = sin_to_float(self)
val denom_rec = uin_to_float(input.bits)
// Instantiate the hardloat divider
val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options))
input.ready := divider.io.inReady
divider.io.inValid := input.valid
divider.io.sqrtOp := false.B
divider.io.a := self_rec
divider.io.b := denom_rec
divider.io.roundingMode := consts.round_minMag
divider.io.detectTininess := consts.tininess_afterRounding
output.valid := divider.io.outValid_div
output.bits := float_to_in(divider.io.out)
assert(!output.valid || output.ready)
Some((input, output))
}
override def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = {
// TODO this uses a floating point divider, but we should use an integer divider instead
val input = Wire(Decoupled(UInt(0.W)))
val output = Wire(Decoupled(self.cloneType))
input.bits := DontCare
// We translate our integer to floating-point form so that we can use the hardfloat divider
val expWidth = log2Up(self.getWidth) + 1
val sigWidth = self.getWidth
def in_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def float_to_in(x: UInt) = {
val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth))
rec_fn_to_in.io.signedOut := true.B
rec_fn_to_in.io.in := x
rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
rec_fn_to_in.io.out.asSInt
}
val self_rec = in_to_float(self)
// Instantiate the hardloat sqrt
val sqrter = Module(new DivSqrtRecFN_small(expWidth, sigWidth, 0))
input.ready := sqrter.io.inReady
sqrter.io.inValid := input.valid
sqrter.io.sqrtOp := true.B
sqrter.io.a := self_rec
sqrter.io.b := DontCare
sqrter.io.roundingMode := consts.round_minMag
sqrter.io.detectTininess := consts.tininess_afterRounding
output.valid := sqrter.io.outValid_sqrt
output.bits := float_to_in(sqrter.io.out)
assert(!output.valid || output.ready)
Some((input, output))
}
override def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = u match {
case Float(expWidth, sigWidth) =>
val input = Wire(Decoupled(UInt(0.W)))
val output = Wire(Decoupled(u.cloneType))
input.bits := DontCare
// We translate our integer to floating-point form so that we can use the hardfloat divider
def in_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
val self_rec = in_to_float(self)
val one_rec = in_to_float(1.S)
// Instantiate the hardloat divider
val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options))
input.ready := divider.io.inReady
divider.io.inValid := input.valid
divider.io.sqrtOp := false.B
divider.io.a := one_rec
divider.io.b := self_rec
divider.io.roundingMode := consts.round_near_even
divider.io.detectTininess := consts.tininess_afterRounding
output.valid := divider.io.outValid_div
output.bits := fNFromRecFN(expWidth, sigWidth, divider.io.out).asTypeOf(u)
assert(!output.valid || output.ready)
Some((input, output))
case _ => None
}
override def mult_with_reciprocal[U <: Data](reciprocal: U): SInt = reciprocal match {
case recip @ Float(expWidth, sigWidth) =>
def in_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def float_to_in(x: UInt) = {
val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth))
rec_fn_to_in.io.signedOut := true.B
rec_fn_to_in.io.in := x
rec_fn_to_in.io.roundingMode := consts.round_minMag
rec_fn_to_in.io.out.asSInt
}
val self_rec = in_to_float(self)
val reciprocal_rec = recFNFromFN(expWidth, sigWidth, recip.bits)
// Instantiate the hardloat divider
val muladder = Module(new MulRecFN(expWidth, sigWidth))
muladder.io.roundingMode := consts.round_near_even
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := self_rec
muladder.io.b := reciprocal_rec
float_to_in(muladder.io.out)
case _ => self
}
}
}
implicit object FloatArithmetic extends Arithmetic[Float] {
// TODO Floating point arithmetic currently switches between recoded and standard formats for every operation. However, it should stay in the recoded format as it travels through the systolic array
override implicit def cast(self: Float): ArithmeticOps[Float] = new ArithmeticOps(self) {
override def *(t: Float): Float = {
val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth))
t_resizer.io.in := t_rec
t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
t_resizer.io.detectTininess := consts.tininess_afterRounding
val t_rec_resized = t_resizer.io.out
val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth))
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := self_rec
muladder.io.b := t_rec_resized
val out = Wire(Float(self.expWidth, self.sigWidth))
out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
out
}
override def mac(m1: Float, m2: Float): Float = {
// Recode all operands
val m1_rec = recFNFromFN(m1.expWidth, m1.sigWidth, m1.bits)
val m2_rec = recFNFromFN(m2.expWidth, m2.sigWidth, m2.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Resize m1 to self's width
val m1_resizer = Module(new RecFNToRecFN(m1.expWidth, m1.sigWidth, self.expWidth, self.sigWidth))
m1_resizer.io.in := m1_rec
m1_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
m1_resizer.io.detectTininess := consts.tininess_afterRounding
val m1_rec_resized = m1_resizer.io.out
// Resize m2 to self's width
val m2_resizer = Module(new RecFNToRecFN(m2.expWidth, m2.sigWidth, self.expWidth, self.sigWidth))
m2_resizer.io.in := m2_rec
m2_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
m2_resizer.io.detectTininess := consts.tininess_afterRounding
val m2_rec_resized = m2_resizer.io.out
// Perform multiply-add
val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth))
muladder.io.op := 0.U
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := m1_rec_resized
muladder.io.b := m2_rec_resized
muladder.io.c := self_rec
// Convert result to standard format // TODO remove these intermediate recodings
val out = Wire(Float(self.expWidth, self.sigWidth))
out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
out
}
override def +(t: Float): Float = {
require(self.getWidth >= t.getWidth) // This just makes it easier to write the resizing code
// Recode all operands
val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Generate 1 as a float
val in_to_rec_fn = Module(new INToRecFN(1, self.expWidth, self.sigWidth))
in_to_rec_fn.io.signedIn := false.B
in_to_rec_fn.io.in := 1.U
in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
val one_rec = in_to_rec_fn.io.out
// Resize t
val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth))
t_resizer.io.in := t_rec
t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
t_resizer.io.detectTininess := consts.tininess_afterRounding
val t_rec_resized = t_resizer.io.out
// Perform addition
val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth))
muladder.io.op := 0.U
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := t_rec_resized
muladder.io.b := one_rec
muladder.io.c := self_rec
val result = Wire(Float(self.expWidth, self.sigWidth))
result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
result
}
override def -(t: Float): Float = {
val t_sgn = t.bits(t.getWidth-1)
val neg_t = Cat(~t_sgn, t.bits(t.getWidth-2,0)).asTypeOf(t)
self + neg_t
}
override def >>(u: UInt): Float = {
// Recode self
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Get 2^(-u) as a recoded float
val shift_exp = Wire(UInt(self.expWidth.W))
shift_exp := self.bias.U - u
val shift_fn = Cat(0.U(1.W), shift_exp, 0.U((self.sigWidth-1).W))
val shift_rec = recFNFromFN(self.expWidth, self.sigWidth, shift_fn)
assert(shift_exp =/= 0.U, "scaling by denormalized numbers is not currently supported")
// Multiply self and 2^(-u)
val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth))
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := self_rec
muladder.io.b := shift_rec
val result = Wire(Float(self.expWidth, self.sigWidth))
result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
result
}
override def >(t: Float): Bool = {
// Recode all operands
val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Resize t to self's width
val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth))
t_resizer.io.in := t_rec
t_resizer.io.roundingMode := consts.round_near_even
t_resizer.io.detectTininess := consts.tininess_afterRounding
val t_rec_resized = t_resizer.io.out
val comparator = Module(new CompareRecFN(self.expWidth, self.sigWidth))
comparator.io.a := self_rec
comparator.io.b := t_rec_resized
comparator.io.signaling := false.B
comparator.io.gt
}
override def withWidthOf(t: Float): Float = {
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth))
resizer.io.in := self_rec
resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
resizer.io.detectTininess := consts.tininess_afterRounding
val result = Wire(Float(t.expWidth, t.sigWidth))
result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out)
result
}
override def clippedToWidthOf(t: Float): Float = {
// TODO check for overflow. Right now, we just assume that overflow doesn't happen
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth))
resizer.io.in := self_rec
resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
resizer.io.detectTininess := consts.tininess_afterRounding
val result = Wire(Float(t.expWidth, t.sigWidth))
result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out)
result
}
override def relu: Float = {
val raw = rawFloatFromFN(self.expWidth, self.sigWidth, self.bits)
val result = Wire(Float(self.expWidth, self.sigWidth))
result.bits := Mux(!raw.isZero && raw.sign, 0.U, self.bits)
result
}
override def zero: Float = 0.U.asTypeOf(self)
override def identity: Float = Cat(0.U(2.W), ~(0.U((self.expWidth-1).W)), 0.U((self.sigWidth-1).W)).asTypeOf(self)
override def minimum: Float = Cat(1.U, ~(0.U(self.expWidth.W)), 0.U((self.sigWidth-1).W)).asTypeOf(self)
}
}
implicit object DummySIntArithmetic extends Arithmetic[DummySInt] {
override implicit def cast(self: DummySInt) = new ArithmeticOps(self) {
override def *(t: DummySInt) = self.dontCare
override def mac(m1: DummySInt, m2: DummySInt) = self.dontCare
override def +(t: DummySInt) = self.dontCare
override def -(t: DummySInt) = self.dontCare
override def >>(t: UInt) = self.dontCare
override def >(t: DummySInt): Bool = false.B
override def identity = self.dontCare
override def withWidthOf(t: DummySInt) = self.dontCare
override def clippedToWidthOf(t: DummySInt) = self.dontCare
override def relu = self.dontCare
override def zero = self.dontCare
override def minimum: DummySInt = self.dontCare
}
}
}
| module PE_380( // @[PE.scala:31:7]
input clock, // @[PE.scala:31:7]
input reset, // @[PE.scala:31:7]
input [7:0] io_in_a, // @[PE.scala:35:14]
input [19:0] io_in_b, // @[PE.scala:35:14]
input [19:0] io_in_d, // @[PE.scala:35:14]
output [7:0] io_out_a, // @[PE.scala:35:14]
output [19:0] io_out_b, // @[PE.scala:35:14]
output [19:0] io_out_c, // @[PE.scala:35:14]
input io_in_control_dataflow, // @[PE.scala:35:14]
input io_in_control_propagate, // @[PE.scala:35:14]
input [4:0] io_in_control_shift, // @[PE.scala:35:14]
output io_out_control_dataflow, // @[PE.scala:35:14]
output io_out_control_propagate, // @[PE.scala:35:14]
output [4:0] io_out_control_shift, // @[PE.scala:35:14]
input [2:0] io_in_id, // @[PE.scala:35:14]
output [2:0] io_out_id, // @[PE.scala:35:14]
input io_in_last, // @[PE.scala:35:14]
output io_out_last, // @[PE.scala:35:14]
input io_in_valid, // @[PE.scala:35:14]
output io_out_valid, // @[PE.scala:35:14]
output io_bad_dataflow // @[PE.scala:35:14]
);
wire [19:0] _mac_unit_io_out_d; // @[PE.scala:64:24]
wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:31:7]
wire [19:0] io_in_b_0 = io_in_b; // @[PE.scala:31:7]
wire [19:0] io_in_d_0 = io_in_d; // @[PE.scala:31:7]
wire io_in_control_dataflow_0 = io_in_control_dataflow; // @[PE.scala:31:7]
wire io_in_control_propagate_0 = io_in_control_propagate; // @[PE.scala:31:7]
wire [4:0] io_in_control_shift_0 = io_in_control_shift; // @[PE.scala:31:7]
wire [2:0] io_in_id_0 = io_in_id; // @[PE.scala:31:7]
wire io_in_last_0 = io_in_last; // @[PE.scala:31:7]
wire io_in_valid_0 = io_in_valid; // @[PE.scala:31:7]
wire io_bad_dataflow_0 = 1'h0; // @[PE.scala:31:7]
wire [7:0] io_out_a_0 = io_in_a_0; // @[PE.scala:31:7]
wire [19:0] _mac_unit_io_in_b_T = io_in_b_0; // @[PE.scala:31:7, :106:37]
wire [19:0] _mac_unit_io_in_b_T_2 = io_in_b_0; // @[PE.scala:31:7, :113:37]
wire [19:0] _mac_unit_io_in_b_T_8 = io_in_b_0; // @[PE.scala:31:7, :137:35]
wire [19:0] c1_lo_1 = io_in_d_0; // @[PE.scala:31:7]
wire [19:0] c2_lo_1 = io_in_d_0; // @[PE.scala:31:7]
wire io_out_control_dataflow_0 = io_in_control_dataflow_0; // @[PE.scala:31:7]
wire io_out_control_propagate_0 = io_in_control_propagate_0; // @[PE.scala:31:7]
wire [4:0] io_out_control_shift_0 = io_in_control_shift_0; // @[PE.scala:31:7]
wire [2:0] io_out_id_0 = io_in_id_0; // @[PE.scala:31:7]
wire io_out_last_0 = io_in_last_0; // @[PE.scala:31:7]
wire io_out_valid_0 = io_in_valid_0; // @[PE.scala:31:7]
wire [19:0] io_out_b_0; // @[PE.scala:31:7]
wire [19:0] io_out_c_0; // @[PE.scala:31:7]
reg [31:0] c1; // @[PE.scala:70:15]
wire [31:0] _io_out_c_zeros_T_1 = c1; // @[PE.scala:70:15]
wire [31:0] _mac_unit_io_in_b_T_6 = c1; // @[PE.scala:70:15, :127:38]
reg [31:0] c2; // @[PE.scala:71:15]
wire [31:0] _io_out_c_zeros_T_10 = c2; // @[PE.scala:71:15]
wire [31:0] _mac_unit_io_in_b_T_4 = c2; // @[PE.scala:71:15, :121:38]
reg last_s; // @[PE.scala:89:25]
wire flip = last_s != io_in_control_propagate_0; // @[PE.scala:31:7, :89:25, :90:21]
wire [4:0] shift_offset = flip ? io_in_control_shift_0 : 5'h0; // @[PE.scala:31:7, :90:21, :91:25]
wire _GEN = shift_offset == 5'h0; // @[PE.scala:91:25]
wire _io_out_c_point_five_T; // @[Arithmetic.scala:101:32]
assign _io_out_c_point_five_T = _GEN; // @[Arithmetic.scala:101:32]
wire _io_out_c_point_five_T_5; // @[Arithmetic.scala:101:32]
assign _io_out_c_point_five_T_5 = _GEN; // @[Arithmetic.scala:101:32]
wire [5:0] _GEN_0 = {1'h0, shift_offset} - 6'h1; // @[PE.scala:91:25]
wire [5:0] _io_out_c_point_five_T_1; // @[Arithmetic.scala:101:53]
assign _io_out_c_point_five_T_1 = _GEN_0; // @[Arithmetic.scala:101:53]
wire [5:0] _io_out_c_zeros_T_2; // @[Arithmetic.scala:102:66]
assign _io_out_c_zeros_T_2 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66]
wire [5:0] _io_out_c_point_five_T_6; // @[Arithmetic.scala:101:53]
assign _io_out_c_point_five_T_6 = _GEN_0; // @[Arithmetic.scala:101:53]
wire [5:0] _io_out_c_zeros_T_11; // @[Arithmetic.scala:102:66]
assign _io_out_c_zeros_T_11 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66]
wire [4:0] _io_out_c_point_five_T_2 = _io_out_c_point_five_T_1[4:0]; // @[Arithmetic.scala:101:53]
wire [31:0] _io_out_c_point_five_T_3 = $signed($signed(c1) >>> _io_out_c_point_five_T_2); // @[PE.scala:70:15]
wire _io_out_c_point_five_T_4 = _io_out_c_point_five_T_3[0]; // @[Arithmetic.scala:101:50]
wire io_out_c_point_five = ~_io_out_c_point_five_T & _io_out_c_point_five_T_4; // @[Arithmetic.scala:101:{29,32,50}]
wire _GEN_1 = shift_offset < 5'h2; // @[PE.scala:91:25]
wire _io_out_c_zeros_T; // @[Arithmetic.scala:102:27]
assign _io_out_c_zeros_T = _GEN_1; // @[Arithmetic.scala:102:27]
wire _io_out_c_zeros_T_9; // @[Arithmetic.scala:102:27]
assign _io_out_c_zeros_T_9 = _GEN_1; // @[Arithmetic.scala:102:27]
wire [4:0] _io_out_c_zeros_T_3 = _io_out_c_zeros_T_2[4:0]; // @[Arithmetic.scala:102:66]
wire [31:0] _io_out_c_zeros_T_4 = 32'h1 << _io_out_c_zeros_T_3; // @[Arithmetic.scala:102:{60,66}]
wire [32:0] _io_out_c_zeros_T_5 = {1'h0, _io_out_c_zeros_T_4} - 33'h1; // @[Arithmetic.scala:102:{60,81}]
wire [31:0] _io_out_c_zeros_T_6 = _io_out_c_zeros_T_5[31:0]; // @[Arithmetic.scala:102:81]
wire [31:0] _io_out_c_zeros_T_7 = _io_out_c_zeros_T_1 & _io_out_c_zeros_T_6; // @[Arithmetic.scala:102:{45,52,81}]
wire [31:0] _io_out_c_zeros_T_8 = _io_out_c_zeros_T ? 32'h0 : _io_out_c_zeros_T_7; // @[Arithmetic.scala:102:{24,27,52}]
wire io_out_c_zeros = |_io_out_c_zeros_T_8; // @[Arithmetic.scala:102:{24,89}]
wire [31:0] _GEN_2 = {27'h0, shift_offset}; // @[PE.scala:91:25]
wire [31:0] _GEN_3 = $signed($signed(c1) >>> _GEN_2); // @[PE.scala:70:15]
wire [31:0] _io_out_c_ones_digit_T; // @[Arithmetic.scala:103:30]
assign _io_out_c_ones_digit_T = _GEN_3; // @[Arithmetic.scala:103:30]
wire [31:0] _io_out_c_T; // @[Arithmetic.scala:107:15]
assign _io_out_c_T = _GEN_3; // @[Arithmetic.scala:103:30, :107:15]
wire io_out_c_ones_digit = _io_out_c_ones_digit_T[0]; // @[Arithmetic.scala:103:30]
wire _io_out_c_r_T = io_out_c_zeros | io_out_c_ones_digit; // @[Arithmetic.scala:102:89, :103:30, :105:38]
wire _io_out_c_r_T_1 = io_out_c_point_five & _io_out_c_r_T; // @[Arithmetic.scala:101:29, :105:{29,38}]
wire io_out_c_r = _io_out_c_r_T_1; // @[Arithmetic.scala:105:{29,53}]
wire [1:0] _io_out_c_T_1 = {1'h0, io_out_c_r}; // @[Arithmetic.scala:105:53, :107:33]
wire [32:0] _io_out_c_T_2 = {_io_out_c_T[31], _io_out_c_T} + {{31{_io_out_c_T_1[1]}}, _io_out_c_T_1}; // @[Arithmetic.scala:107:{15,28,33}]
wire [31:0] _io_out_c_T_3 = _io_out_c_T_2[31:0]; // @[Arithmetic.scala:107:28]
wire [31:0] _io_out_c_T_4 = _io_out_c_T_3; // @[Arithmetic.scala:107:28]
wire _io_out_c_T_5 = $signed(_io_out_c_T_4) > 32'sh7FFFF; // @[Arithmetic.scala:107:28, :125:33]
wire _io_out_c_T_6 = $signed(_io_out_c_T_4) < -32'sh80000; // @[Arithmetic.scala:107:28, :125:60]
wire [31:0] _io_out_c_T_7 = _io_out_c_T_6 ? 32'hFFF80000 : _io_out_c_T_4; // @[Mux.scala:126:16]
wire [31:0] _io_out_c_T_8 = _io_out_c_T_5 ? 32'h7FFFF : _io_out_c_T_7; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_9 = _io_out_c_T_8[19:0]; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_10 = _io_out_c_T_9; // @[Arithmetic.scala:125:{81,99}]
wire [19:0] _mac_unit_io_in_b_T_1 = _mac_unit_io_in_b_T; // @[PE.scala:106:37]
wire [7:0] _mac_unit_io_in_b_WIRE = _mac_unit_io_in_b_T_1[7:0]; // @[PE.scala:106:37]
wire c1_sign = io_in_d_0[19]; // @[PE.scala:31:7]
wire c2_sign = io_in_d_0[19]; // @[PE.scala:31:7]
wire [1:0] _GEN_4 = {2{c1_sign}}; // @[Arithmetic.scala:117:26, :118:18]
wire [1:0] c1_lo_lo_hi; // @[Arithmetic.scala:118:18]
assign c1_lo_lo_hi = _GEN_4; // @[Arithmetic.scala:118:18]
wire [1:0] c1_lo_hi_hi; // @[Arithmetic.scala:118:18]
assign c1_lo_hi_hi = _GEN_4; // @[Arithmetic.scala:118:18]
wire [1:0] c1_hi_lo_hi; // @[Arithmetic.scala:118:18]
assign c1_hi_lo_hi = _GEN_4; // @[Arithmetic.scala:118:18]
wire [1:0] c1_hi_hi_hi; // @[Arithmetic.scala:118:18]
assign c1_hi_hi_hi = _GEN_4; // @[Arithmetic.scala:118:18]
wire [2:0] c1_lo_lo = {c1_lo_lo_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [2:0] c1_lo_hi = {c1_lo_hi_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [5:0] c1_lo = {c1_lo_hi, c1_lo_lo}; // @[Arithmetic.scala:118:18]
wire [2:0] c1_hi_lo = {c1_hi_lo_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [2:0] c1_hi_hi = {c1_hi_hi_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [5:0] c1_hi = {c1_hi_hi, c1_hi_lo}; // @[Arithmetic.scala:118:18]
wire [11:0] _c1_T = {c1_hi, c1_lo}; // @[Arithmetic.scala:118:18]
wire [31:0] _c1_T_1 = {_c1_T, c1_lo_1}; // @[Arithmetic.scala:118:{14,18}]
wire [31:0] _c1_T_2 = _c1_T_1; // @[Arithmetic.scala:118:{14,61}]
wire [31:0] _c1_WIRE = _c1_T_2; // @[Arithmetic.scala:118:61]
wire [4:0] _io_out_c_point_five_T_7 = _io_out_c_point_five_T_6[4:0]; // @[Arithmetic.scala:101:53]
wire [31:0] _io_out_c_point_five_T_8 = $signed($signed(c2) >>> _io_out_c_point_five_T_7); // @[PE.scala:71:15]
wire _io_out_c_point_five_T_9 = _io_out_c_point_five_T_8[0]; // @[Arithmetic.scala:101:50]
wire io_out_c_point_five_1 = ~_io_out_c_point_five_T_5 & _io_out_c_point_five_T_9; // @[Arithmetic.scala:101:{29,32,50}]
wire [4:0] _io_out_c_zeros_T_12 = _io_out_c_zeros_T_11[4:0]; // @[Arithmetic.scala:102:66]
wire [31:0] _io_out_c_zeros_T_13 = 32'h1 << _io_out_c_zeros_T_12; // @[Arithmetic.scala:102:{60,66}]
wire [32:0] _io_out_c_zeros_T_14 = {1'h0, _io_out_c_zeros_T_13} - 33'h1; // @[Arithmetic.scala:102:{60,81}]
wire [31:0] _io_out_c_zeros_T_15 = _io_out_c_zeros_T_14[31:0]; // @[Arithmetic.scala:102:81]
wire [31:0] _io_out_c_zeros_T_16 = _io_out_c_zeros_T_10 & _io_out_c_zeros_T_15; // @[Arithmetic.scala:102:{45,52,81}]
wire [31:0] _io_out_c_zeros_T_17 = _io_out_c_zeros_T_9 ? 32'h0 : _io_out_c_zeros_T_16; // @[Arithmetic.scala:102:{24,27,52}]
wire io_out_c_zeros_1 = |_io_out_c_zeros_T_17; // @[Arithmetic.scala:102:{24,89}]
wire [31:0] _GEN_5 = $signed($signed(c2) >>> _GEN_2); // @[PE.scala:71:15]
wire [31:0] _io_out_c_ones_digit_T_1; // @[Arithmetic.scala:103:30]
assign _io_out_c_ones_digit_T_1 = _GEN_5; // @[Arithmetic.scala:103:30]
wire [31:0] _io_out_c_T_11; // @[Arithmetic.scala:107:15]
assign _io_out_c_T_11 = _GEN_5; // @[Arithmetic.scala:103:30, :107:15]
wire io_out_c_ones_digit_1 = _io_out_c_ones_digit_T_1[0]; // @[Arithmetic.scala:103:30]
wire _io_out_c_r_T_2 = io_out_c_zeros_1 | io_out_c_ones_digit_1; // @[Arithmetic.scala:102:89, :103:30, :105:38]
wire _io_out_c_r_T_3 = io_out_c_point_five_1 & _io_out_c_r_T_2; // @[Arithmetic.scala:101:29, :105:{29,38}]
wire io_out_c_r_1 = _io_out_c_r_T_3; // @[Arithmetic.scala:105:{29,53}]
wire [1:0] _io_out_c_T_12 = {1'h0, io_out_c_r_1}; // @[Arithmetic.scala:105:53, :107:33]
wire [32:0] _io_out_c_T_13 = {_io_out_c_T_11[31], _io_out_c_T_11} + {{31{_io_out_c_T_12[1]}}, _io_out_c_T_12}; // @[Arithmetic.scala:107:{15,28,33}]
wire [31:0] _io_out_c_T_14 = _io_out_c_T_13[31:0]; // @[Arithmetic.scala:107:28]
wire [31:0] _io_out_c_T_15 = _io_out_c_T_14; // @[Arithmetic.scala:107:28]
wire _io_out_c_T_16 = $signed(_io_out_c_T_15) > 32'sh7FFFF; // @[Arithmetic.scala:107:28, :125:33]
wire _io_out_c_T_17 = $signed(_io_out_c_T_15) < -32'sh80000; // @[Arithmetic.scala:107:28, :125:60]
wire [31:0] _io_out_c_T_18 = _io_out_c_T_17 ? 32'hFFF80000 : _io_out_c_T_15; // @[Mux.scala:126:16]
wire [31:0] _io_out_c_T_19 = _io_out_c_T_16 ? 32'h7FFFF : _io_out_c_T_18; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_20 = _io_out_c_T_19[19:0]; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_21 = _io_out_c_T_20; // @[Arithmetic.scala:125:{81,99}]
wire [19:0] _mac_unit_io_in_b_T_3 = _mac_unit_io_in_b_T_2; // @[PE.scala:113:37]
wire [7:0] _mac_unit_io_in_b_WIRE_1 = _mac_unit_io_in_b_T_3[7:0]; // @[PE.scala:113:37]
wire [1:0] _GEN_6 = {2{c2_sign}}; // @[Arithmetic.scala:117:26, :118:18]
wire [1:0] c2_lo_lo_hi; // @[Arithmetic.scala:118:18]
assign c2_lo_lo_hi = _GEN_6; // @[Arithmetic.scala:118:18]
wire [1:0] c2_lo_hi_hi; // @[Arithmetic.scala:118:18]
assign c2_lo_hi_hi = _GEN_6; // @[Arithmetic.scala:118:18]
wire [1:0] c2_hi_lo_hi; // @[Arithmetic.scala:118:18]
assign c2_hi_lo_hi = _GEN_6; // @[Arithmetic.scala:118:18]
wire [1:0] c2_hi_hi_hi; // @[Arithmetic.scala:118:18]
assign c2_hi_hi_hi = _GEN_6; // @[Arithmetic.scala:118:18]
wire [2:0] c2_lo_lo = {c2_lo_lo_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [2:0] c2_lo_hi = {c2_lo_hi_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [5:0] c2_lo = {c2_lo_hi, c2_lo_lo}; // @[Arithmetic.scala:118:18]
wire [2:0] c2_hi_lo = {c2_hi_lo_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [2:0] c2_hi_hi = {c2_hi_hi_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [5:0] c2_hi = {c2_hi_hi, c2_hi_lo}; // @[Arithmetic.scala:118:18]
wire [11:0] _c2_T = {c2_hi, c2_lo}; // @[Arithmetic.scala:118:18]
wire [31:0] _c2_T_1 = {_c2_T, c2_lo_1}; // @[Arithmetic.scala:118:{14,18}]
wire [31:0] _c2_T_2 = _c2_T_1; // @[Arithmetic.scala:118:{14,61}]
wire [31:0] _c2_WIRE = _c2_T_2; // @[Arithmetic.scala:118:61]
wire [31:0] _mac_unit_io_in_b_T_5 = _mac_unit_io_in_b_T_4; // @[PE.scala:121:38]
wire [7:0] _mac_unit_io_in_b_WIRE_2 = _mac_unit_io_in_b_T_5[7:0]; // @[PE.scala:121:38]
wire [31:0] _mac_unit_io_in_b_T_7 = _mac_unit_io_in_b_T_6; // @[PE.scala:127:38]
wire [7:0] _mac_unit_io_in_b_WIRE_3 = _mac_unit_io_in_b_T_7[7:0]; // @[PE.scala:127:38]
assign io_out_c_0 = io_in_control_dataflow_0 ? (io_in_control_propagate_0 ? c1[19:0] : c2[19:0]) : io_in_control_propagate_0 ? _io_out_c_T_10 : _io_out_c_T_21; // @[PE.scala:31:7, :70:15, :71:15, :102:95, :103:30, :104:16, :111:16, :118:101, :119:30, :120:16, :126:16]
assign io_out_b_0 = io_in_control_dataflow_0 ? _mac_unit_io_out_d : io_in_b_0; // @[PE.scala:31:7, :64:24, :102:95, :103:30, :118:101]
wire [19:0] _mac_unit_io_in_b_T_9 = _mac_unit_io_in_b_T_8; // @[PE.scala:137:35]
wire [7:0] _mac_unit_io_in_b_WIRE_4 = _mac_unit_io_in_b_T_9[7:0]; // @[PE.scala:137:35]
wire [31:0] _GEN_7 = {{12{io_in_d_0[19]}}, io_in_d_0}; // @[PE.scala:31:7, :124:10]
wire [31:0] _GEN_8 = {{12{_mac_unit_io_out_d[19]}}, _mac_unit_io_out_d}; // @[PE.scala:64:24, :108:10]
always @(posedge clock) begin // @[PE.scala:31:7]
if (io_in_valid_0) begin // @[PE.scala:31:7]
if (io_in_control_dataflow_0) begin // @[PE.scala:31:7]
if (io_in_control_dataflow_0 & io_in_control_propagate_0) // @[PE.scala:31:7, :70:15, :118:101, :119:30, :124:10]
c1 <= _GEN_7; // @[PE.scala:70:15, :124:10]
if (~io_in_control_dataflow_0 | io_in_control_propagate_0) begin // @[PE.scala:31:7, :71:15, :118:101, :119:30]
end
else // @[PE.scala:71:15, :118:101, :119:30]
c2 <= _GEN_7; // @[PE.scala:71:15, :124:10]
end
else begin // @[PE.scala:31:7]
c1 <= io_in_control_propagate_0 ? _c1_WIRE : _GEN_8; // @[PE.scala:31:7, :70:15, :103:30, :108:10, :109:10, :115:10]
c2 <= io_in_control_propagate_0 ? _GEN_8 : _c2_WIRE; // @[PE.scala:31:7, :71:15, :103:30, :108:10, :116:10]
end
last_s <= io_in_control_propagate_0; // @[PE.scala:31:7, :89:25]
end
always @(posedge)
MacUnit_124 mac_unit ( // @[PE.scala:64:24]
.clock (clock),
.reset (reset),
.io_in_a (io_in_a_0), // @[PE.scala:31:7]
.io_in_b (io_in_control_dataflow_0 ? (io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE_2 : _mac_unit_io_in_b_WIRE_3) : io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE : _mac_unit_io_in_b_WIRE_1), // @[PE.scala:31:7, :102:95, :103:30, :106:{24,37}, :113:{24,37}, :118:101, :119:30, :121:{24,38}, :127:{24,38}]
.io_in_c (io_in_control_dataflow_0 ? {{12{io_in_b_0[19]}}, io_in_b_0} : io_in_control_propagate_0 ? c2 : c1), // @[PE.scala:31:7, :70:15, :71:15, :102:95, :103:30, :107:24, :114:24, :118:101, :122:24]
.io_out_d (_mac_unit_io_out_d)
); // @[PE.scala:64:24]
assign io_out_a = io_out_a_0; // @[PE.scala:31:7]
assign io_out_b = io_out_b_0; // @[PE.scala:31:7]
assign io_out_c = io_out_c_0; // @[PE.scala:31:7]
assign io_out_control_dataflow = io_out_control_dataflow_0; // @[PE.scala:31:7]
assign io_out_control_propagate = io_out_control_propagate_0; // @[PE.scala:31:7]
assign io_out_control_shift = io_out_control_shift_0; // @[PE.scala:31:7]
assign io_out_id = io_out_id_0; // @[PE.scala:31:7]
assign io_out_last = io_out_last_0; // @[PE.scala:31:7]
assign io_out_valid = io_out_valid_0; // @[PE.scala:31:7]
assign io_bad_dataflow = io_bad_dataflow_0; // @[PE.scala:31:7]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File primitives.scala:
/*============================================================================
This Chisel source file is part of a pre-release version of the HardFloat IEEE
Floating-Point Arithmetic Package, by John R. Hauser (with some contributions
from Yunsup Lee and Andrew Waterman, mainly concerning testing).
Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
University of California. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
package hardfloat
import chisel3._
import chisel3.util._
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
object lowMask
{
def apply(in: UInt, topBound: BigInt, bottomBound: BigInt): UInt =
{
require(topBound != bottomBound)
val numInVals = BigInt(1)<<in.getWidth
if (topBound < bottomBound) {
lowMask(~in, numInVals - 1 - topBound, numInVals - 1 - bottomBound)
} else if (numInVals > 64 /* Empirical */) {
// For simulation performance, we should avoid generating
// exteremely wide shifters, so we divide and conquer.
// Empirically, this does not impact synthesis QoR.
val mid = numInVals / 2
val msb = in(in.getWidth - 1)
val lsbs = in(in.getWidth - 2, 0)
if (mid < topBound) {
if (mid <= bottomBound) {
Mux(msb,
lowMask(lsbs, topBound - mid, bottomBound - mid),
0.U
)
} else {
Mux(msb,
lowMask(lsbs, topBound - mid, 0) ## ((BigInt(1)<<(mid - bottomBound).toInt) - 1).U,
lowMask(lsbs, mid, bottomBound)
)
}
} else {
~Mux(msb, 0.U, ~lowMask(lsbs, topBound, bottomBound))
}
} else {
val shift = (BigInt(-1)<<numInVals.toInt).S>>in
Reverse(
shift(
(numInVals - 1 - bottomBound).toInt,
(numInVals - topBound).toInt
)
)
}
}
}
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
object countLeadingZeros
{
def apply(in: UInt): UInt = PriorityEncoder(in.asBools.reverse)
}
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
object orReduceBy2
{
def apply(in: UInt): UInt =
{
val reducedWidth = (in.getWidth + 1)>>1
val reducedVec = Wire(Vec(reducedWidth, Bool()))
for (ix <- 0 until reducedWidth - 1) {
reducedVec(ix) := in(ix * 2 + 1, ix * 2).orR
}
reducedVec(reducedWidth - 1) :=
in(in.getWidth - 1, (reducedWidth - 1) * 2).orR
reducedVec.asUInt
}
}
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
object orReduceBy4
{
def apply(in: UInt): UInt =
{
val reducedWidth = (in.getWidth + 3)>>2
val reducedVec = Wire(Vec(reducedWidth, Bool()))
for (ix <- 0 until reducedWidth - 1) {
reducedVec(ix) := in(ix * 4 + 3, ix * 4).orR
}
reducedVec(reducedWidth - 1) :=
in(in.getWidth - 1, (reducedWidth - 1) * 4).orR
reducedVec.asUInt
}
}
File MulAddRecFN.scala:
/*============================================================================
This Chisel source file is part of a pre-release version of the HardFloat IEEE
Floating-Point Arithmetic Package, by John R. Hauser (with some contributions
from Yunsup Lee and Andrew Waterman, mainly concerning testing).
Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
University of California. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
package hardfloat
import chisel3._
import chisel3.util._
import consts._
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
class MulAddRecFN_interIo(expWidth: Int, sigWidth: Int) extends Bundle
{
//*** ENCODE SOME OF THESE CASES IN FEWER BITS?:
val isSigNaNAny = Bool()
val isNaNAOrB = Bool()
val isInfA = Bool()
val isZeroA = Bool()
val isInfB = Bool()
val isZeroB = Bool()
val signProd = Bool()
val isNaNC = Bool()
val isInfC = Bool()
val isZeroC = Bool()
val sExpSum = SInt((expWidth + 2).W)
val doSubMags = Bool()
val CIsDominant = Bool()
val CDom_CAlignDist = UInt(log2Ceil(sigWidth + 1).W)
val highAlignedSigC = UInt((sigWidth + 2).W)
val bit0AlignedSigC = UInt(1.W)
}
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
class MulAddRecFNToRaw_preMul(expWidth: Int, sigWidth: Int) extends RawModule
{
override def desiredName = s"MulAddRecFNToRaw_preMul_e${expWidth}_s${sigWidth}"
val io = IO(new Bundle {
val op = Input(Bits(2.W))
val a = Input(Bits((expWidth + sigWidth + 1).W))
val b = Input(Bits((expWidth + sigWidth + 1).W))
val c = Input(Bits((expWidth + sigWidth + 1).W))
val mulAddA = Output(UInt(sigWidth.W))
val mulAddB = Output(UInt(sigWidth.W))
val mulAddC = Output(UInt((sigWidth * 2).W))
val toPostMul = Output(new MulAddRecFN_interIo(expWidth, sigWidth))
})
//------------------------------------------------------------------------
//------------------------------------------------------------------------
//*** POSSIBLE TO REDUCE THIS BY 1 OR 2 BITS? (CURRENTLY 2 BITS BETWEEN
//*** UNSHIFTED C AND PRODUCT):
val sigSumWidth = sigWidth * 3 + 3
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val rawA = rawFloatFromRecFN(expWidth, sigWidth, io.a)
val rawB = rawFloatFromRecFN(expWidth, sigWidth, io.b)
val rawC = rawFloatFromRecFN(expWidth, sigWidth, io.c)
val signProd = rawA.sign ^ rawB.sign ^ io.op(1)
//*** REVIEW THE BIAS FOR 'sExpAlignedProd':
val sExpAlignedProd =
rawA.sExp +& rawB.sExp + (-(BigInt(1)<<expWidth) + sigWidth + 3).S
val doSubMags = signProd ^ rawC.sign ^ io.op(0)
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val sNatCAlignDist = sExpAlignedProd - rawC.sExp
val posNatCAlignDist = sNatCAlignDist(expWidth + 1, 0)
val isMinCAlign = rawA.isZero || rawB.isZero || (sNatCAlignDist < 0.S)
val CIsDominant =
! rawC.isZero && (isMinCAlign || (posNatCAlignDist <= sigWidth.U))
val CAlignDist =
Mux(isMinCAlign,
0.U,
Mux(posNatCAlignDist < (sigSumWidth - 1).U,
posNatCAlignDist(log2Ceil(sigSumWidth) - 1, 0),
(sigSumWidth - 1).U
)
)
val mainAlignedSigC =
(Mux(doSubMags, ~rawC.sig, rawC.sig) ## Fill(sigSumWidth - sigWidth + 2, doSubMags)).asSInt>>CAlignDist
val reduced4CExtra =
(orReduceBy4(rawC.sig<<((sigSumWidth - sigWidth - 1) & 3)) &
lowMask(
CAlignDist>>2,
//*** NOT NEEDED?:
// (sigSumWidth + 2)>>2,
(sigSumWidth - 1)>>2,
(sigSumWidth - sigWidth - 1)>>2
)
).orR
val alignedSigC =
Cat(mainAlignedSigC>>3,
Mux(doSubMags,
mainAlignedSigC(2, 0).andR && ! reduced4CExtra,
mainAlignedSigC(2, 0).orR || reduced4CExtra
)
)
//------------------------------------------------------------------------
//------------------------------------------------------------------------
io.mulAddA := rawA.sig
io.mulAddB := rawB.sig
io.mulAddC := alignedSigC(sigWidth * 2, 1)
io.toPostMul.isSigNaNAny :=
isSigNaNRawFloat(rawA) || isSigNaNRawFloat(rawB) ||
isSigNaNRawFloat(rawC)
io.toPostMul.isNaNAOrB := rawA.isNaN || rawB.isNaN
io.toPostMul.isInfA := rawA.isInf
io.toPostMul.isZeroA := rawA.isZero
io.toPostMul.isInfB := rawB.isInf
io.toPostMul.isZeroB := rawB.isZero
io.toPostMul.signProd := signProd
io.toPostMul.isNaNC := rawC.isNaN
io.toPostMul.isInfC := rawC.isInf
io.toPostMul.isZeroC := rawC.isZero
io.toPostMul.sExpSum :=
Mux(CIsDominant, rawC.sExp, sExpAlignedProd - sigWidth.S)
io.toPostMul.doSubMags := doSubMags
io.toPostMul.CIsDominant := CIsDominant
io.toPostMul.CDom_CAlignDist := CAlignDist(log2Ceil(sigWidth + 1) - 1, 0)
io.toPostMul.highAlignedSigC :=
alignedSigC(sigSumWidth - 1, sigWidth * 2 + 1)
io.toPostMul.bit0AlignedSigC := alignedSigC(0)
}
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
class MulAddRecFNToRaw_postMul(expWidth: Int, sigWidth: Int) extends RawModule
{
override def desiredName = s"MulAddRecFNToRaw_postMul_e${expWidth}_s${sigWidth}"
val io = IO(new Bundle {
val fromPreMul = Input(new MulAddRecFN_interIo(expWidth, sigWidth))
val mulAddResult = Input(UInt((sigWidth * 2 + 1).W))
val roundingMode = Input(UInt(3.W))
val invalidExc = Output(Bool())
val rawOut = Output(new RawFloat(expWidth, sigWidth + 2))
})
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val sigSumWidth = sigWidth * 3 + 3
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val roundingMode_min = (io.roundingMode === round_min)
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val opSignC = io.fromPreMul.signProd ^ io.fromPreMul.doSubMags
val sigSum =
Cat(Mux(io.mulAddResult(sigWidth * 2),
io.fromPreMul.highAlignedSigC + 1.U,
io.fromPreMul.highAlignedSigC
),
io.mulAddResult(sigWidth * 2 - 1, 0),
io.fromPreMul.bit0AlignedSigC
)
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val CDom_sign = opSignC
val CDom_sExp = io.fromPreMul.sExpSum - io.fromPreMul.doSubMags.zext
val CDom_absSigSum =
Mux(io.fromPreMul.doSubMags,
~sigSum(sigSumWidth - 1, sigWidth + 1),
0.U(1.W) ##
//*** IF GAP IS REDUCED TO 1 BIT, MUST REDUCE THIS COMPONENT TO 1 BIT TOO:
io.fromPreMul.highAlignedSigC(sigWidth + 1, sigWidth) ##
sigSum(sigSumWidth - 3, sigWidth + 2)
)
val CDom_absSigSumExtra =
Mux(io.fromPreMul.doSubMags,
(~sigSum(sigWidth, 1)).orR,
sigSum(sigWidth + 1, 1).orR
)
val CDom_mainSig =
(CDom_absSigSum<<io.fromPreMul.CDom_CAlignDist)(
sigWidth * 2 + 1, sigWidth - 3)
val CDom_reduced4SigExtra =
(orReduceBy4(CDom_absSigSum(sigWidth - 1, 0)<<(~sigWidth & 3)) &
lowMask(io.fromPreMul.CDom_CAlignDist>>2, 0, sigWidth>>2)).orR
val CDom_sig =
Cat(CDom_mainSig>>3,
CDom_mainSig(2, 0).orR || CDom_reduced4SigExtra ||
CDom_absSigSumExtra
)
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val notCDom_signSigSum = sigSum(sigWidth * 2 + 3)
val notCDom_absSigSum =
Mux(notCDom_signSigSum,
~sigSum(sigWidth * 2 + 2, 0),
sigSum(sigWidth * 2 + 2, 0) + io.fromPreMul.doSubMags
)
val notCDom_reduced2AbsSigSum = orReduceBy2(notCDom_absSigSum)
val notCDom_normDistReduced2 = countLeadingZeros(notCDom_reduced2AbsSigSum)
val notCDom_nearNormDist = notCDom_normDistReduced2<<1
val notCDom_sExp = io.fromPreMul.sExpSum - notCDom_nearNormDist.asUInt.zext
val notCDom_mainSig =
(notCDom_absSigSum<<notCDom_nearNormDist)(
sigWidth * 2 + 3, sigWidth - 1)
val notCDom_reduced4SigExtra =
(orReduceBy2(
notCDom_reduced2AbsSigSum(sigWidth>>1, 0)<<((sigWidth>>1) & 1)) &
lowMask(notCDom_normDistReduced2>>1, 0, (sigWidth + 2)>>2)
).orR
val notCDom_sig =
Cat(notCDom_mainSig>>3,
notCDom_mainSig(2, 0).orR || notCDom_reduced4SigExtra
)
val notCDom_completeCancellation =
(notCDom_sig(sigWidth + 2, sigWidth + 1) === 0.U)
val notCDom_sign =
Mux(notCDom_completeCancellation,
roundingMode_min,
io.fromPreMul.signProd ^ notCDom_signSigSum
)
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val notNaN_isInfProd = io.fromPreMul.isInfA || io.fromPreMul.isInfB
val notNaN_isInfOut = notNaN_isInfProd || io.fromPreMul.isInfC
val notNaN_addZeros =
(io.fromPreMul.isZeroA || io.fromPreMul.isZeroB) &&
io.fromPreMul.isZeroC
io.invalidExc :=
io.fromPreMul.isSigNaNAny ||
(io.fromPreMul.isInfA && io.fromPreMul.isZeroB) ||
(io.fromPreMul.isZeroA && io.fromPreMul.isInfB) ||
(! io.fromPreMul.isNaNAOrB &&
(io.fromPreMul.isInfA || io.fromPreMul.isInfB) &&
io.fromPreMul.isInfC &&
io.fromPreMul.doSubMags)
io.rawOut.isNaN := io.fromPreMul.isNaNAOrB || io.fromPreMul.isNaNC
io.rawOut.isInf := notNaN_isInfOut
//*** IMPROVE?:
io.rawOut.isZero :=
notNaN_addZeros ||
(! io.fromPreMul.CIsDominant && notCDom_completeCancellation)
io.rawOut.sign :=
(notNaN_isInfProd && io.fromPreMul.signProd) ||
(io.fromPreMul.isInfC && opSignC) ||
(notNaN_addZeros && ! roundingMode_min &&
io.fromPreMul.signProd && opSignC) ||
(notNaN_addZeros && roundingMode_min &&
(io.fromPreMul.signProd || opSignC)) ||
(! notNaN_isInfOut && ! notNaN_addZeros &&
Mux(io.fromPreMul.CIsDominant, CDom_sign, notCDom_sign))
io.rawOut.sExp := Mux(io.fromPreMul.CIsDominant, CDom_sExp, notCDom_sExp)
io.rawOut.sig := Mux(io.fromPreMul.CIsDominant, CDom_sig, notCDom_sig)
}
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
class MulAddRecFN(expWidth: Int, sigWidth: Int) extends RawModule
{
override def desiredName = s"MulAddRecFN_e${expWidth}_s${sigWidth}"
val io = IO(new Bundle {
val op = Input(Bits(2.W))
val a = Input(Bits((expWidth + sigWidth + 1).W))
val b = Input(Bits((expWidth + sigWidth + 1).W))
val c = Input(Bits((expWidth + sigWidth + 1).W))
val roundingMode = Input(UInt(3.W))
val detectTininess = Input(UInt(1.W))
val out = Output(Bits((expWidth + sigWidth + 1).W))
val exceptionFlags = Output(Bits(5.W))
})
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val mulAddRecFNToRaw_preMul =
Module(new MulAddRecFNToRaw_preMul(expWidth, sigWidth))
val mulAddRecFNToRaw_postMul =
Module(new MulAddRecFNToRaw_postMul(expWidth, sigWidth))
mulAddRecFNToRaw_preMul.io.op := io.op
mulAddRecFNToRaw_preMul.io.a := io.a
mulAddRecFNToRaw_preMul.io.b := io.b
mulAddRecFNToRaw_preMul.io.c := io.c
val mulAddResult =
(mulAddRecFNToRaw_preMul.io.mulAddA *
mulAddRecFNToRaw_preMul.io.mulAddB) +&
mulAddRecFNToRaw_preMul.io.mulAddC
mulAddRecFNToRaw_postMul.io.fromPreMul :=
mulAddRecFNToRaw_preMul.io.toPostMul
mulAddRecFNToRaw_postMul.io.mulAddResult := mulAddResult
mulAddRecFNToRaw_postMul.io.roundingMode := io.roundingMode
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val roundRawFNToRecFN =
Module(new RoundRawFNToRecFN(expWidth, sigWidth, 0))
roundRawFNToRecFN.io.invalidExc := mulAddRecFNToRaw_postMul.io.invalidExc
roundRawFNToRecFN.io.infiniteExc := false.B
roundRawFNToRecFN.io.in := mulAddRecFNToRaw_postMul.io.rawOut
roundRawFNToRecFN.io.roundingMode := io.roundingMode
roundRawFNToRecFN.io.detectTininess := io.detectTininess
io.out := roundRawFNToRecFN.io.out
io.exceptionFlags := roundRawFNToRecFN.io.exceptionFlags
}
File rawFloatFromRecFN.scala:
/*============================================================================
This Chisel source file is part of a pre-release version of the HardFloat IEEE
Floating-Point Arithmetic Package, by John R. Hauser (with some contributions
from Yunsup Lee and Andrew Waterman, mainly concerning testing).
Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the
University of California. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
package hardfloat
import chisel3._
import chisel3.util._
/*----------------------------------------------------------------------------
| In the result, no more than one of 'isNaN', 'isInf', and 'isZero' will be
| set.
*----------------------------------------------------------------------------*/
object rawFloatFromRecFN
{
def apply(expWidth: Int, sigWidth: Int, in: Bits): RawFloat =
{
val exp = in(expWidth + sigWidth - 1, sigWidth - 1)
val isZero = exp(expWidth, expWidth - 2) === 0.U
val isSpecial = exp(expWidth, expWidth - 1) === 3.U
val out = Wire(new RawFloat(expWidth, sigWidth))
out.isNaN := isSpecial && exp(expWidth - 2)
out.isInf := isSpecial && ! exp(expWidth - 2)
out.isZero := isZero
out.sign := in(expWidth + sigWidth)
out.sExp := exp.zext
out.sig := 0.U(1.W) ## ! isZero ## in(sigWidth - 2, 0)
out
}
}
| module MulAddRecFNToRaw_preMul_e8_s24_1(); // @[MulAddRecFN.scala:71:7]
wire [8:0] rawA_exp = 9'h100; // @[rawFloatFromRecFN.scala:51:21]
wire [8:0] rawB_exp = 9'h100; // @[rawFloatFromRecFN.scala:51:21]
wire [2:0] _rawA_isZero_T = 3'h4; // @[rawFloatFromRecFN.scala:52:28]
wire [2:0] _rawB_isZero_T = 3'h4; // @[rawFloatFromRecFN.scala:52:28]
wire [1:0] _rawA_isSpecial_T = 2'h2; // @[rawFloatFromRecFN.scala:53:28]
wire [1:0] _rawB_isSpecial_T = 2'h2; // @[rawFloatFromRecFN.scala:53:28]
wire [9:0] rawA_sExp = 10'h100; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire [9:0] _rawA_out_sExp_T = 10'h100; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire [9:0] rawB_sExp = 10'h100; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire [9:0] _rawB_out_sExp_T = 10'h100; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire [1:0] _rawA_out_sig_T_1 = 2'h1; // @[rawFloatFromRecFN.scala:61:32]
wire [1:0] _rawB_out_sig_T_1 = 2'h1; // @[rawFloatFromRecFN.scala:61:32]
wire [24:0] rawA_sig = 25'h800000; // @[rawFloatFromRecFN.scala:55:23, :61:44]
wire [24:0] _rawA_out_sig_T_3 = 25'h800000; // @[rawFloatFromRecFN.scala:55:23, :61:44]
wire [24:0] rawB_sig = 25'h800000; // @[rawFloatFromRecFN.scala:55:23, :61:44]
wire [24:0] _rawB_out_sig_T_3 = 25'h800000; // @[rawFloatFromRecFN.scala:55:23, :61:44]
wire [8:0] rawC_exp = 9'h2B; // @[rawFloatFromRecFN.scala:51:21]
wire [9:0] rawC_sExp = 10'h2B; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire [9:0] _rawC_out_sExp_T = 10'h2B; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire [22:0] _rawA_out_sig_T_2 = 23'h0; // @[rawFloatFromRecFN.scala:61:49]
wire [22:0] _rawB_out_sig_T_2 = 23'h0; // @[rawFloatFromRecFN.scala:61:49]
wire [22:0] _rawC_out_sig_T_2 = 23'h0; // @[rawFloatFromRecFN.scala:61:49]
wire [24:0] rawC_sig = 25'h0; // @[rawFloatFromRecFN.scala:55:23, :61:44]
wire [24:0] _rawC_out_sig_T_3 = 25'h0; // @[rawFloatFromRecFN.scala:55:23, :61:44]
wire [10:0] _sExpAlignedProd_T = 11'h200; // @[MulAddRecFN.scala:100:19]
wire [11:0] _sExpAlignedProd_T_1 = 12'h11B; // @[MulAddRecFN.scala:100:32]
wire [10:0] _sExpAlignedProd_T_2 = 11'h11B; // @[MulAddRecFN.scala:100:32]
wire [10:0] sExpAlignedProd = 11'h11B; // @[MulAddRecFN.scala:100:32]
wire [11:0] _sNatCAlignDist_T = 12'hF0; // @[MulAddRecFN.scala:106:42]
wire [10:0] _sNatCAlignDist_T_1 = 11'hF0; // @[MulAddRecFN.scala:106:42]
wire [10:0] sNatCAlignDist = 11'hF0; // @[MulAddRecFN.scala:106:42]
wire [9:0] posNatCAlignDist = 10'hF0; // @[MulAddRecFN.scala:107:42]
wire [6:0] _CAlignDist_T_1 = 7'h70; // @[MulAddRecFN.scala:115:33]
wire [6:0] _CAlignDist_T_2 = 7'h4A; // @[MulAddRecFN.scala:112:12, :114:16]
wire [6:0] CAlignDist = 7'h4A; // @[MulAddRecFN.scala:112:12, :114:16]
wire [24:0] _mainAlignedSigC_T = 25'h1FFFFFF; // @[MulAddRecFN.scala:120:{13,25}]
wire [24:0] _mainAlignedSigC_T_1 = 25'h1FFFFFF; // @[MulAddRecFN.scala:120:{13,25}]
wire [52:0] _mainAlignedSigC_T_2 = 53'h1FFFFFFFFFFFFF; // @[MulAddRecFN.scala:120:53]
wire [77:0] _mainAlignedSigC_T_3 = 78'h3FFFFFFFFFFFFFFFFFFF; // @[MulAddRecFN.scala:120:{46,94,100}]
wire [77:0] _mainAlignedSigC_T_4 = 78'h3FFFFFFFFFFFFFFFFFFF; // @[MulAddRecFN.scala:120:{94,100}]
wire [77:0] mainAlignedSigC = 78'h3FFFFFFFFFFFFFFFFFFF; // @[MulAddRecFN.scala:120:{94,100}]
wire [26:0] _reduced4CExtra_T = 27'h0; // @[MulAddRecFN.scala:122:30]
wire [2:0] _rawC_isZero_T = 3'h0; // @[rawFloatFromRecFN.scala:52:28]
wire [2:0] _reduced4CExtra_reducedVec_6_T = 3'h0; // @[rawFloatFromRecFN.scala:52:28]
wire [2:0] reduced4CExtra_lo = 3'h0; // @[rawFloatFromRecFN.scala:52:28]
wire [3:0] _reduced4CExtra_reducedVec_0_T = 4'h0; // @[primitives.scala:120:33, :124:20]
wire [3:0] _reduced4CExtra_reducedVec_1_T = 4'h0; // @[primitives.scala:120:33, :124:20]
wire [3:0] _reduced4CExtra_reducedVec_2_T = 4'h0; // @[primitives.scala:120:33, :124:20]
wire [3:0] _reduced4CExtra_reducedVec_3_T = 4'h0; // @[primitives.scala:120:33, :124:20]
wire [3:0] _reduced4CExtra_reducedVec_4_T = 4'h0; // @[primitives.scala:120:33, :124:20]
wire [3:0] _reduced4CExtra_reducedVec_5_T = 4'h0; // @[primitives.scala:120:33, :124:20]
wire [3:0] reduced4CExtra_hi = 4'h0; // @[primitives.scala:120:33, :124:20]
wire [4:0] _reduced4CExtra_T_2 = 5'h12; // @[MulAddRecFN.scala:124:28]
wire [32:0] reduced4CExtra_shift = 33'h1FFFFC000; // @[primitives.scala:76:56]
wire [3:0] _reduced4CExtra_T_4 = 4'hF; // @[primitives.scala:77:20]
wire [3:0] _reduced4CExtra_T_13 = 4'hF; // @[primitives.scala:77:20]
wire [1:0] _reduced4CExtra_T_5 = 2'h3; // @[primitives.scala:77:20]
wire [1:0] _reduced4CExtra_T_8 = 2'h3; // @[primitives.scala:77:20]
wire [1:0] _reduced4CExtra_T_9 = 2'h3; // @[primitives.scala:77:20]
wire [1:0] _reduced4CExtra_T_12 = 2'h3; // @[primitives.scala:77:20]
wire [1:0] _reduced4CExtra_T_14 = 2'h3; // @[primitives.scala:77:20]
wire [1:0] _reduced4CExtra_T_17 = 2'h3; // @[primitives.scala:77:20]
wire [5:0] _reduced4CExtra_T_3 = 6'h3F; // @[primitives.scala:77:20, :78:22]
wire [5:0] _reduced4CExtra_T_18 = 6'h3F; // @[primitives.scala:77:20, :78:22]
wire [6:0] _reduced4CExtra_T_1 = 7'h0; // @[primitives.scala:124:20]
wire [6:0] _reduced4CExtra_T_19 = 7'h0; // @[primitives.scala:124:20]
wire [2:0] _alignedSigC_T_1 = 3'h7; // @[MulAddRecFN.scala:134:32, :135:32]
wire [2:0] _alignedSigC_T_5 = 3'h7; // @[MulAddRecFN.scala:134:32, :135:32]
wire [74:0] _alignedSigC_T = 75'h7FFFFFFFFFFFFFFFFFF; // @[MulAddRecFN.scala:132:{12,28}]
wire [74:0] alignedSigC_hi = 75'h7FFFFFFFFFFFFFFFFFF; // @[MulAddRecFN.scala:132:12]
wire [75:0] alignedSigC = 76'hFFFFFFFFFFFFFFFFFFF; // @[MulAddRecFN.scala:132:12]
wire [11:0] _io_toPostMul_sExpSum_T = 12'h103; // @[MulAddRecFN.scala:158:53]
wire [10:0] _io_toPostMul_sExpSum_T_1 = 11'h103; // @[MulAddRecFN.scala:158:{12,53}]
wire [10:0] _io_toPostMul_sExpSum_T_2 = 11'h103; // @[MulAddRecFN.scala:158:{12,53}]
wire [10:0] _io_toPostMul_sExpSum_T_3 = 11'h103; // @[MulAddRecFN.scala:158:{12,53}]
wire [25:0] io_toPostMul_highAlignedSigC = 26'h3FFFFFF; // @[MulAddRecFN.scala:71:7, :74:16, :163:20]
wire [25:0] _io_toPostMul_highAlignedSigC_T = 26'h3FFFFFF; // @[MulAddRecFN.scala:71:7, :74:16, :163:20]
wire [4:0] io_toPostMul_CDom_CAlignDist = 5'hA; // @[MulAddRecFN.scala:71:7, :74:16, :161:47]
wire [4:0] _io_toPostMul_CDom_CAlignDist_T = 5'hA; // @[MulAddRecFN.scala:71:7, :74:16, :161:47]
wire [9:0] io_toPostMul_sExpSum = 10'h103; // @[MulAddRecFN.scala:71:7, :74:16, :157:28]
wire io_toPostMul_signProd = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36, :59:25, :61:35]
wire io_toPostMul_isZeroC = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36, :59:25, :61:35]
wire io_toPostMul_doSubMags = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36, :59:25, :61:35]
wire io_toPostMul_bit0AlignedSigC = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36, :59:25, :61:35]
wire rawA_sign = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36, :59:25, :61:35]
wire _rawA_out_isInf_T_1 = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36, :59:25, :61:35]
wire _rawA_out_sign_T = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36, :59:25, :61:35]
wire _rawA_out_sig_T = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36, :59:25, :61:35]
wire _rawB_out_isInf_T_1 = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36, :59:25, :61:35]
wire _rawB_out_sig_T = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36, :59:25, :61:35]
wire rawC_isZero = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36, :59:25, :61:35]
wire rawC_isZero_0 = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36, :59:25, :61:35]
wire _rawC_out_isInf_T_1 = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36, :59:25, :61:35]
wire _signProd_T = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36, :59:25, :61:35]
wire signProd = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36, :59:25, :61:35]
wire _doSubMags_T = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36, :59:25, :61:35]
wire doSubMags = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36, :59:25, :61:35]
wire _reduced4CExtra_T_6 = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36, :59:25, :61:35]
wire _reduced4CExtra_T_7 = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36, :59:25, :61:35]
wire _reduced4CExtra_T_10 = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36, :59:25, :61:35]
wire _reduced4CExtra_T_11 = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36, :59:25, :61:35]
wire _reduced4CExtra_T_15 = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36, :59:25, :61:35]
wire _reduced4CExtra_T_16 = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36, :59:25, :61:35]
wire _alignedSigC_T_2 = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36, :59:25, :61:35]
wire _alignedSigC_T_3 = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36, :59:25, :61:35]
wire _alignedSigC_T_4 = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36, :59:25, :61:35]
wire _alignedSigC_T_6 = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36, :59:25, :61:35]
wire _alignedSigC_T_7 = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36, :59:25, :61:35]
wire _alignedSigC_T_8 = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36, :59:25, :61:35]
wire _io_toPostMul_isSigNaNAny_T_1 = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36, :59:25, :61:35]
wire _io_toPostMul_isSigNaNAny_T_4 = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36, :59:25, :61:35]
wire _io_toPostMul_isSigNaNAny_T_8 = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36, :59:25, :61:35]
wire _io_toPostMul_bit0AlignedSigC_T = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36, :59:25, :61:35]
wire io_toPostMul_isSigNaNAny = 1'h0; // @[rawFloatFromRecFN.scala:52:53, :53:53, :55:23, :56:{33,41}, :57:{33,41}, :59:25, :61:35]
wire io_toPostMul_isNaNAOrB = 1'h0; // @[rawFloatFromRecFN.scala:52:53, :53:53, :55:23, :56:{33,41}, :57:{33,41}, :59:25, :61:35]
wire io_toPostMul_isInfA = 1'h0; // @[rawFloatFromRecFN.scala:52:53, :53:53, :55:23, :56:{33,41}, :57:{33,41}, :59:25, :61:35]
wire io_toPostMul_isZeroA = 1'h0; // @[rawFloatFromRecFN.scala:52:53, :53:53, :55:23, :56:{33,41}, :57:{33,41}, :59:25, :61:35]
wire io_toPostMul_isInfB = 1'h0; // @[rawFloatFromRecFN.scala:52:53, :53:53, :55:23, :56:{33,41}, :57:{33,41}, :59:25, :61:35]
wire io_toPostMul_isZeroB = 1'h0; // @[rawFloatFromRecFN.scala:52:53, :53:53, :55:23, :56:{33,41}, :57:{33,41}, :59:25, :61:35]
wire io_toPostMul_isNaNC = 1'h0; // @[rawFloatFromRecFN.scala:52:53, :53:53, :55:23, :56:{33,41}, :57:{33,41}, :59:25, :61:35]
wire io_toPostMul_isInfC = 1'h0; // @[rawFloatFromRecFN.scala:52:53, :53:53, :55:23, :56:{33,41}, :57:{33,41}, :59:25, :61:35]
wire io_toPostMul_CIsDominant = 1'h0; // @[rawFloatFromRecFN.scala:52:53, :53:53, :55:23, :56:{33,41}, :57:{33,41}, :59:25, :61:35]
wire rawA_isZero = 1'h0; // @[rawFloatFromRecFN.scala:52:53, :53:53, :55:23, :56:{33,41}, :57:{33,41}, :59:25, :61:35]
wire rawA_isSpecial = 1'h0; // @[rawFloatFromRecFN.scala:52:53, :53:53, :55:23, :56:{33,41}, :57:{33,41}, :59:25, :61:35]
wire rawA_isNaN = 1'h0; // @[rawFloatFromRecFN.scala:52:53, :53:53, :55:23, :56:{33,41}, :57:{33,41}, :59:25, :61:35]
wire rawA_isInf = 1'h0; // @[rawFloatFromRecFN.scala:52:53, :53:53, :55:23, :56:{33,41}, :57:{33,41}, :59:25, :61:35]
wire rawA_isZero_0 = 1'h0; // @[rawFloatFromRecFN.scala:52:53, :53:53, :55:23, :56:{33,41}, :57:{33,41}, :59:25, :61:35]
wire _rawA_out_isNaN_T = 1'h0; // @[rawFloatFromRecFN.scala:52:53, :53:53, :55:23, :56:{33,41}, :57:{33,41}, :59:25, :61:35]
wire _rawA_out_isNaN_T_1 = 1'h0; // @[rawFloatFromRecFN.scala:52:53, :53:53, :55:23, :56:{33,41}, :57:{33,41}, :59:25, :61:35]
wire _rawA_out_isInf_T = 1'h0; // @[rawFloatFromRecFN.scala:52:53, :53:53, :55:23, :56:{33,41}, :57:{33,41}, :59:25, :61:35]
wire _rawA_out_isInf_T_2 = 1'h0; // @[rawFloatFromRecFN.scala:52:53, :53:53, :55:23, :56:{33,41}, :57:{33,41}, :59:25, :61:35]
wire rawB_isZero = 1'h0; // @[rawFloatFromRecFN.scala:52:53, :53:53, :55:23, :56:{33,41}, :57:{33,41}, :59:25, :61:35]
wire rawB_isSpecial = 1'h0; // @[rawFloatFromRecFN.scala:52:53, :53:53, :55:23, :56:{33,41}, :57:{33,41}, :59:25, :61:35]
wire rawB_isNaN = 1'h0; // @[rawFloatFromRecFN.scala:52:53, :53:53, :55:23, :56:{33,41}, :57:{33,41}, :59:25, :61:35]
wire rawB_isInf = 1'h0; // @[rawFloatFromRecFN.scala:52:53, :53:53, :55:23, :56:{33,41}, :57:{33,41}, :59:25, :61:35]
wire rawB_isZero_0 = 1'h0; // @[rawFloatFromRecFN.scala:52:53, :53:53, :55:23, :56:{33,41}, :57:{33,41}, :59:25, :61:35]
wire rawB_sign = 1'h0; // @[rawFloatFromRecFN.scala:52:53, :53:53, :55:23, :56:{33,41}, :57:{33,41}, :59:25, :61:35]
wire _rawB_out_isNaN_T = 1'h0; // @[rawFloatFromRecFN.scala:52:53, :53:53, :55:23, :56:{33,41}, :57:{33,41}, :59:25, :61:35]
wire _rawB_out_isNaN_T_1 = 1'h0; // @[rawFloatFromRecFN.scala:52:53, :53:53, :55:23, :56:{33,41}, :57:{33,41}, :59:25, :61:35]
wire _rawB_out_isInf_T = 1'h0; // @[rawFloatFromRecFN.scala:52:53, :53:53, :55:23, :56:{33,41}, :57:{33,41}, :59:25, :61:35]
wire _rawB_out_isInf_T_2 = 1'h0; // @[rawFloatFromRecFN.scala:52:53, :53:53, :55:23, :56:{33,41}, :57:{33,41}, :59:25, :61:35]
wire _rawB_out_sign_T = 1'h0; // @[rawFloatFromRecFN.scala:52:53, :53:53, :55:23, :56:{33,41}, :57:{33,41}, :59:25, :61:35]
wire rawC_isSpecial = 1'h0; // @[rawFloatFromRecFN.scala:52:53, :53:53, :55:23, :56:{33,41}, :57:{33,41}, :59:25, :61:35]
wire rawC_isNaN = 1'h0; // @[rawFloatFromRecFN.scala:52:53, :53:53, :55:23, :56:{33,41}, :57:{33,41}, :59:25, :61:35]
wire rawC_isInf = 1'h0; // @[rawFloatFromRecFN.scala:52:53, :53:53, :55:23, :56:{33,41}, :57:{33,41}, :59:25, :61:35]
wire rawC_sign = 1'h0; // @[rawFloatFromRecFN.scala:52:53, :53:53, :55:23, :56:{33,41}, :57:{33,41}, :59:25, :61:35]
wire _rawC_out_isNaN_T = 1'h0; // @[rawFloatFromRecFN.scala:52:53, :53:53, :55:23, :56:{33,41}, :57:{33,41}, :59:25, :61:35]
wire _rawC_out_isNaN_T_1 = 1'h0; // @[rawFloatFromRecFN.scala:52:53, :53:53, :55:23, :56:{33,41}, :57:{33,41}, :59:25, :61:35]
wire _rawC_out_isInf_T = 1'h0; // @[rawFloatFromRecFN.scala:52:53, :53:53, :55:23, :56:{33,41}, :57:{33,41}, :59:25, :61:35]
wire _rawC_out_isInf_T_2 = 1'h0; // @[rawFloatFromRecFN.scala:52:53, :53:53, :55:23, :56:{33,41}, :57:{33,41}, :59:25, :61:35]
wire _rawC_out_sign_T = 1'h0; // @[rawFloatFromRecFN.scala:52:53, :53:53, :55:23, :56:{33,41}, :57:{33,41}, :59:25, :61:35]
wire _rawC_out_sig_T = 1'h0; // @[rawFloatFromRecFN.scala:52:53, :53:53, :55:23, :56:{33,41}, :57:{33,41}, :59:25, :61:35]
wire _signProd_T_1 = 1'h0; // @[rawFloatFromRecFN.scala:52:53, :53:53, :55:23, :56:{33,41}, :57:{33,41}, :59:25, :61:35]
wire _doSubMags_T_1 = 1'h0; // @[rawFloatFromRecFN.scala:52:53, :53:53, :55:23, :56:{33,41}, :57:{33,41}, :59:25, :61:35]
wire _isMinCAlign_T = 1'h0; // @[rawFloatFromRecFN.scala:52:53, :53:53, :55:23, :56:{33,41}, :57:{33,41}, :59:25, :61:35]
wire _isMinCAlign_T_1 = 1'h0; // @[rawFloatFromRecFN.scala:52:53, :53:53, :55:23, :56:{33,41}, :57:{33,41}, :59:25, :61:35]
wire isMinCAlign = 1'h0; // @[rawFloatFromRecFN.scala:52:53, :53:53, :55:23, :56:{33,41}, :57:{33,41}, :59:25, :61:35]
wire _CIsDominant_T = 1'h0; // @[rawFloatFromRecFN.scala:52:53, :53:53, :55:23, :56:{33,41}, :57:{33,41}, :59:25, :61:35]
wire _CIsDominant_T_1 = 1'h0; // @[rawFloatFromRecFN.scala:52:53, :53:53, :55:23, :56:{33,41}, :57:{33,41}, :59:25, :61:35]
wire _CIsDominant_T_2 = 1'h0; // @[rawFloatFromRecFN.scala:52:53, :53:53, :55:23, :56:{33,41}, :57:{33,41}, :59:25, :61:35]
wire CIsDominant = 1'h0; // @[rawFloatFromRecFN.scala:52:53, :53:53, :55:23, :56:{33,41}, :57:{33,41}, :59:25, :61:35]
wire _CAlignDist_T = 1'h0; // @[rawFloatFromRecFN.scala:52:53, :53:53, :55:23, :56:{33,41}, :57:{33,41}, :59:25, :61:35]
wire reduced4CExtra_reducedVec_0 = 1'h0; // @[rawFloatFromRecFN.scala:52:53, :53:53, :55:23, :56:{33,41}, :57:{33,41}, :59:25, :61:35]
wire reduced4CExtra_reducedVec_1 = 1'h0; // @[rawFloatFromRecFN.scala:52:53, :53:53, :55:23, :56:{33,41}, :57:{33,41}, :59:25, :61:35]
wire reduced4CExtra_reducedVec_2 = 1'h0; // @[rawFloatFromRecFN.scala:52:53, :53:53, :55:23, :56:{33,41}, :57:{33,41}, :59:25, :61:35]
wire reduced4CExtra_reducedVec_3 = 1'h0; // @[rawFloatFromRecFN.scala:52:53, :53:53, :55:23, :56:{33,41}, :57:{33,41}, :59:25, :61:35]
wire reduced4CExtra_reducedVec_4 = 1'h0; // @[rawFloatFromRecFN.scala:52:53, :53:53, :55:23, :56:{33,41}, :57:{33,41}, :59:25, :61:35]
wire reduced4CExtra_reducedVec_5 = 1'h0; // @[rawFloatFromRecFN.scala:52:53, :53:53, :55:23, :56:{33,41}, :57:{33,41}, :59:25, :61:35]
wire reduced4CExtra_reducedVec_6 = 1'h0; // @[rawFloatFromRecFN.scala:52:53, :53:53, :55:23, :56:{33,41}, :57:{33,41}, :59:25, :61:35]
wire _reduced4CExtra_reducedVec_0_T_1 = 1'h0; // @[rawFloatFromRecFN.scala:52:53, :53:53, :55:23, :56:{33,41}, :57:{33,41}, :59:25, :61:35]
wire _reduced4CExtra_reducedVec_1_T_1 = 1'h0; // @[rawFloatFromRecFN.scala:52:53, :53:53, :55:23, :56:{33,41}, :57:{33,41}, :59:25, :61:35]
wire _reduced4CExtra_reducedVec_2_T_1 = 1'h0; // @[rawFloatFromRecFN.scala:52:53, :53:53, :55:23, :56:{33,41}, :57:{33,41}, :59:25, :61:35]
wire _reduced4CExtra_reducedVec_3_T_1 = 1'h0; // @[rawFloatFromRecFN.scala:52:53, :53:53, :55:23, :56:{33,41}, :57:{33,41}, :59:25, :61:35]
wire _reduced4CExtra_reducedVec_4_T_1 = 1'h0; // @[rawFloatFromRecFN.scala:52:53, :53:53, :55:23, :56:{33,41}, :57:{33,41}, :59:25, :61:35]
wire _reduced4CExtra_reducedVec_5_T_1 = 1'h0; // @[rawFloatFromRecFN.scala:52:53, :53:53, :55:23, :56:{33,41}, :57:{33,41}, :59:25, :61:35]
wire _reduced4CExtra_reducedVec_6_T_1 = 1'h0; // @[rawFloatFromRecFN.scala:52:53, :53:53, :55:23, :56:{33,41}, :57:{33,41}, :59:25, :61:35]
wire reduced4CExtra = 1'h0; // @[rawFloatFromRecFN.scala:52:53, :53:53, :55:23, :56:{33,41}, :57:{33,41}, :59:25, :61:35]
wire _io_toPostMul_isSigNaNAny_T = 1'h0; // @[rawFloatFromRecFN.scala:52:53, :53:53, :55:23, :56:{33,41}, :57:{33,41}, :59:25, :61:35]
wire _io_toPostMul_isSigNaNAny_T_2 = 1'h0; // @[rawFloatFromRecFN.scala:52:53, :53:53, :55:23, :56:{33,41}, :57:{33,41}, :59:25, :61:35]
wire _io_toPostMul_isSigNaNAny_T_3 = 1'h0; // @[rawFloatFromRecFN.scala:52:53, :53:53, :55:23, :56:{33,41}, :57:{33,41}, :59:25, :61:35]
wire _io_toPostMul_isSigNaNAny_T_5 = 1'h0; // @[rawFloatFromRecFN.scala:52:53, :53:53, :55:23, :56:{33,41}, :57:{33,41}, :59:25, :61:35]
wire _io_toPostMul_isSigNaNAny_T_6 = 1'h0; // @[rawFloatFromRecFN.scala:52:53, :53:53, :55:23, :56:{33,41}, :57:{33,41}, :59:25, :61:35]
wire _io_toPostMul_isSigNaNAny_T_7 = 1'h0; // @[rawFloatFromRecFN.scala:52:53, :53:53, :55:23, :56:{33,41}, :57:{33,41}, :59:25, :61:35]
wire _io_toPostMul_isSigNaNAny_T_9 = 1'h0; // @[rawFloatFromRecFN.scala:52:53, :53:53, :55:23, :56:{33,41}, :57:{33,41}, :59:25, :61:35]
wire _io_toPostMul_isSigNaNAny_T_10 = 1'h0; // @[rawFloatFromRecFN.scala:52:53, :53:53, :55:23, :56:{33,41}, :57:{33,41}, :59:25, :61:35]
wire _io_toPostMul_isNaNAOrB_T = 1'h0; // @[rawFloatFromRecFN.scala:52:53, :53:53, :55:23, :56:{33,41}, :57:{33,41}, :59:25, :61:35]
wire [47:0] io_mulAddC = 48'hFFFFFFFFFFFF; // @[MulAddRecFN.scala:71:7, :74:16, :143:30]
wire [47:0] _io_mulAddC_T = 48'hFFFFFFFFFFFF; // @[MulAddRecFN.scala:71:7, :74:16, :143:30]
wire [23:0] io_mulAddA = 24'h800000; // @[MulAddRecFN.scala:71:7, :74:16, :141:16, :142:16]
wire [23:0] io_mulAddB = 24'h800000; // @[MulAddRecFN.scala:71:7, :74:16, :141:16, :142:16]
wire [32:0] io_c = 33'h15800000; // @[MulAddRecFN.scala:71:7, :74:16]
wire [32:0] io_b = 33'h80000000; // @[MulAddRecFN.scala:71:7, :74:16]
wire [32:0] io_a = 33'h180000000; // @[MulAddRecFN.scala:71:7, :74:16]
wire [1:0] io_op = 2'h0; // @[rawFloatFromRecFN.scala:53:28, :61:32]
wire [1:0] _rawC_isSpecial_T = 2'h0; // @[rawFloatFromRecFN.scala:53:28, :61:32]
wire [1:0] _rawC_out_sig_T_1 = 2'h0; // @[rawFloatFromRecFN.scala:53:28, :61:32]
wire [1:0] reduced4CExtra_lo_hi = 2'h0; // @[rawFloatFromRecFN.scala:53:28, :61:32]
wire [1:0] reduced4CExtra_hi_lo = 2'h0; // @[rawFloatFromRecFN.scala:53:28, :61:32]
wire [1:0] reduced4CExtra_hi_hi = 2'h0; // @[rawFloatFromRecFN.scala:53:28, :61:32]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File PlusArg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.experimental._
import chisel3.util.HasBlackBoxResource
@deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05")
case class PlusArgInfo(default: BigInt, docstring: String)
/** Case class for PlusArg information
*
* @tparam A scala type of the PlusArg value
* @param default optional default value
* @param docstring text to include in the help
* @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT)
*/
private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String)
/** Typeclass for converting a type to a doctype string
* @tparam A some type
*/
trait Doctypeable[A] {
/** Return the doctype string for some option */
def toDoctype(a: Option[A]): String
}
/** Object containing implementations of the Doctypeable typeclass */
object Doctypes {
/** Converts an Int => "INT" */
implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" }
/** Converts a BigInt => "INT" */
implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" }
/** Converts a String => "STRING" */
implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" }
}
class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map(
"FORMAT" -> StringParam(format),
"DEFAULT" -> IntParam(default),
"WIDTH" -> IntParam(width)
)) with HasBlackBoxResource {
val io = IO(new Bundle {
val out = Output(UInt(width.W))
})
addResource("/vsrc/plusarg_reader.v")
}
/* This wrapper class has no outputs, making it clear it is a simulation-only construct */
class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module {
val io = IO(new Bundle {
val count = Input(UInt(width.W))
})
val max = Module(new plusarg_reader(format, default, docstring, width)).io.out
when (max > 0.U) {
assert (io.count < max, s"Timeout exceeded: $docstring")
}
}
import Doctypes._
object PlusArg
{
/** PlusArg("foo") will return 42.U if the simulation is run with +foo=42
* Do not use this as an initial register value. The value is set in an
* initial block and thus accessing it from another initial is racey.
* Add a docstring to document the arg, which can be dumped in an elaboration
* pass.
*/
def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = {
PlusArgArtefacts.append(name, Some(default), docstring)
Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out
}
/** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert
* to kill the simulation when count exceeds the specified integer argument.
* Default 0 will never assert.
*/
def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = {
PlusArgArtefacts.append(name, Some(default), docstring)
Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count
}
}
object PlusArgArtefacts {
private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty
/* Add a new PlusArg */
@deprecated(
"Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08",
"Rocket Chip 2020.05"
)
def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring)
/** Add a new PlusArg
*
* @tparam A scala type of the PlusArg value
* @param name name for the PlusArg
* @param default optional default value
* @param docstring text to include in the help
*/
def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit =
artefacts = artefacts ++
Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default)))
/* From plus args, generate help text */
private def serializeHelp_cHeader(tab: String = ""): String = artefacts
.map{ case(arg, info) =>
s"""|$tab+$arg=${info.doctype}\\n\\
|$tab${" "*20}${info.docstring}\\n\\
|""".stripMargin ++ info.default.map{ case default =>
s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("")
}.toSeq.mkString("\\n\\\n") ++ "\""
/* From plus args, generate a char array of their names */
private def serializeArray_cHeader(tab: String = ""): String = {
val prettyTab = tab + " " * 44 // Length of 'static const ...'
s"${tab}static const char * verilog_plusargs [] = {\\\n" ++
artefacts
.map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" }
.mkString("")++
s"${prettyTab}0};"
}
/* Generate C code to be included in emulator.cc that helps with
* argument parsing based on available Verilog PlusArgs */
def serialize_cHeader(): String =
s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\
|${serializeHelp_cHeader(" "*7)}
|${serializeArray_cHeader()}
|""".stripMargin
}
File Nodes.scala:
package constellation.channel
import chisel3._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.{Parameters, Field}
import freechips.rocketchip.diplomacy._
case class EmptyParams()
case class ChannelEdgeParams(cp: ChannelParams, p: Parameters)
object ChannelImp extends SimpleNodeImp[EmptyParams, ChannelParams, ChannelEdgeParams, Channel] {
def edge(pd: EmptyParams, pu: ChannelParams, p: Parameters, sourceInfo: SourceInfo) = {
ChannelEdgeParams(pu, p)
}
def bundle(e: ChannelEdgeParams) = new Channel(e.cp)(e.p)
def render(e: ChannelEdgeParams) = if (e.cp.possibleFlows.size == 0) {
RenderedEdge(colour = "ffffff", label = "X")
} else {
RenderedEdge(colour = "#0000ff", label = e.cp.payloadBits.toString)
}
override def monitor(bundle: Channel, edge: ChannelEdgeParams): Unit = {
val monitor = Module(new NoCMonitor(edge.cp)(edge.p))
monitor.io.in := bundle
}
// TODO: Add nodepath stuff? override def mixO, override def mixI
}
case class ChannelSourceNode(val destId: Int)(implicit valName: ValName) extends SourceNode(ChannelImp)(Seq(EmptyParams()))
case class ChannelDestNode(val destParams: ChannelParams)(implicit valName: ValName) extends SinkNode(ChannelImp)(Seq(destParams))
case class ChannelAdapterNode(
slaveFn: ChannelParams => ChannelParams = { d => d })(
implicit valName: ValName) extends AdapterNode(ChannelImp)((e: EmptyParams) => e, slaveFn)
case class ChannelIdentityNode()(implicit valName: ValName) extends IdentityNode(ChannelImp)()
case class ChannelEphemeralNode()(implicit valName: ValName) extends EphemeralNode(ChannelImp)()
case class IngressChannelEdgeParams(cp: IngressChannelParams, p: Parameters)
case class EgressChannelEdgeParams(cp: EgressChannelParams, p: Parameters)
object IngressChannelImp extends SimpleNodeImp[EmptyParams, IngressChannelParams, IngressChannelEdgeParams, IngressChannel] {
def edge(pd: EmptyParams, pu: IngressChannelParams, p: Parameters, sourceInfo: SourceInfo) = {
IngressChannelEdgeParams(pu, p)
}
def bundle(e: IngressChannelEdgeParams) = new IngressChannel(e.cp)(e.p)
def render(e: IngressChannelEdgeParams) = if (e.cp.possibleFlows.size == 0) {
RenderedEdge(colour = "ffffff", label = "X")
} else {
RenderedEdge(colour = "#00ff00", label = e.cp.payloadBits.toString)
}
}
object EgressChannelImp extends SimpleNodeImp[EmptyParams, EgressChannelParams, EgressChannelEdgeParams, EgressChannel] {
def edge(pd: EmptyParams, pu: EgressChannelParams, p: Parameters, sourceInfo: SourceInfo) = {
EgressChannelEdgeParams(pu, p)
}
def bundle(e: EgressChannelEdgeParams) = new EgressChannel(e.cp)(e.p)
def render(e: EgressChannelEdgeParams) = if (e.cp.possibleFlows.size == 0) {
RenderedEdge(colour = "ffffff", label = "X")
} else {
RenderedEdge(colour = "#ff0000", label = e.cp.payloadBits.toString)
}
}
case class IngressChannelSourceNode(val destId: Int)(implicit valName: ValName) extends SourceNode(IngressChannelImp)(Seq(EmptyParams()))
case class IngressChannelDestNode(val destParams: IngressChannelParams)(implicit valName: ValName) extends SinkNode(IngressChannelImp)(Seq(destParams))
case class EgressChannelSourceNode(val egressId: Int)(implicit valName: ValName) extends SourceNode(EgressChannelImp)(Seq(EmptyParams()))
case class EgressChannelDestNode(val destParams: EgressChannelParams)(implicit valName: ValName) extends SinkNode(EgressChannelImp)(Seq(destParams))
case class IngressChannelAdapterNode(
slaveFn: IngressChannelParams => IngressChannelParams = { d => d })(
implicit valName: ValName) extends AdapterNode(IngressChannelImp)(m => m, slaveFn)
case class EgressChannelAdapterNode(
slaveFn: EgressChannelParams => EgressChannelParams = { d => d })(
implicit valName: ValName) extends AdapterNode(EgressChannelImp)(m => m, slaveFn)
case class IngressChannelIdentityNode()(implicit valName: ValName) extends IdentityNode(IngressChannelImp)()
case class EgressChannelIdentityNode()(implicit valName: ValName) extends IdentityNode(EgressChannelImp)()
case class IngressChannelEphemeralNode()(implicit valName: ValName) extends EphemeralNode(IngressChannelImp)()
case class EgressChannelEphemeralNode()(implicit valName: ValName) extends EphemeralNode(EgressChannelImp)()
File Router.scala:
package constellation.router
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.{Field, Parameters}
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.util._
import constellation.channel._
import constellation.routing.{RoutingRelation}
import constellation.noc.{HasNoCParams}
case class UserRouterParams(
// Payload width. Must match payload width on all channels attached to this routing node
payloadBits: Int = 64,
// Combines SA and ST stages (removes pipeline register)
combineSAST: Boolean = false,
// Combines RC and VA stages (removes pipeline register)
combineRCVA: Boolean = false,
// Adds combinational path from SA to VA
coupleSAVA: Boolean = false,
vcAllocator: VCAllocatorParams => Parameters => VCAllocator = (vP) => (p) => new RotatingSingleVCAllocator(vP)(p)
)
case class RouterParams(
nodeId: Int,
nIngress: Int,
nEgress: Int,
user: UserRouterParams
)
trait HasRouterOutputParams {
def outParams: Seq[ChannelParams]
def egressParams: Seq[EgressChannelParams]
def allOutParams = outParams ++ egressParams
def nOutputs = outParams.size
def nEgress = egressParams.size
def nAllOutputs = allOutParams.size
}
trait HasRouterInputParams {
def inParams: Seq[ChannelParams]
def ingressParams: Seq[IngressChannelParams]
def allInParams = inParams ++ ingressParams
def nInputs = inParams.size
def nIngress = ingressParams.size
def nAllInputs = allInParams.size
}
trait HasRouterParams
{
def routerParams: RouterParams
def nodeId = routerParams.nodeId
def payloadBits = routerParams.user.payloadBits
}
class DebugBundle(val nIn: Int) extends Bundle {
val va_stall = Vec(nIn, UInt())
val sa_stall = Vec(nIn, UInt())
}
class Router(
val routerParams: RouterParams,
preDiplomaticInParams: Seq[ChannelParams],
preDiplomaticIngressParams: Seq[IngressChannelParams],
outDests: Seq[Int],
egressIds: Seq[Int]
)(implicit p: Parameters) extends LazyModule with HasNoCParams with HasRouterParams {
val allPreDiplomaticInParams = preDiplomaticInParams ++ preDiplomaticIngressParams
val destNodes = preDiplomaticInParams.map(u => ChannelDestNode(u))
val sourceNodes = outDests.map(u => ChannelSourceNode(u))
val ingressNodes = preDiplomaticIngressParams.map(u => IngressChannelDestNode(u))
val egressNodes = egressIds.map(u => EgressChannelSourceNode(u))
val debugNode = BundleBridgeSource(() => new DebugBundle(allPreDiplomaticInParams.size))
val ctrlNode = if (hasCtrl) Some(BundleBridgeSource(() => new RouterCtrlBundle)) else None
def inParams = module.inParams
def outParams = module.outParams
def ingressParams = module.ingressParams
def egressParams = module.egressParams
lazy val module = new LazyModuleImp(this) with HasRouterInputParams with HasRouterOutputParams {
val (io_in, edgesIn) = destNodes.map(_.in(0)).unzip
val (io_out, edgesOut) = sourceNodes.map(_.out(0)).unzip
val (io_ingress, edgesIngress) = ingressNodes.map(_.in(0)).unzip
val (io_egress, edgesEgress) = egressNodes.map(_.out(0)).unzip
val io_debug = debugNode.out(0)._1
val inParams = edgesIn.map(_.cp)
val outParams = edgesOut.map(_.cp)
val ingressParams = edgesIngress.map(_.cp)
val egressParams = edgesEgress.map(_.cp)
allOutParams.foreach(u => require(u.srcId == nodeId && u.payloadBits == routerParams.user.payloadBits))
allInParams.foreach(u => require(u.destId == nodeId && u.payloadBits == routerParams.user.payloadBits))
require(nIngress == routerParams.nIngress)
require(nEgress == routerParams.nEgress)
require(nAllInputs >= 1)
require(nAllOutputs >= 1)
require(nodeId < (1 << nodeIdBits))
val input_units = inParams.zipWithIndex.map { case (u,i) =>
Module(new InputUnit(u, outParams, egressParams,
routerParams.user.combineRCVA, routerParams.user.combineSAST))
.suggestName(s"input_unit_${i}_from_${u.srcId}") }
val ingress_units = ingressParams.zipWithIndex.map { case (u,i) =>
Module(new IngressUnit(i, u, outParams, egressParams,
routerParams.user.combineRCVA, routerParams.user.combineSAST))
.suggestName(s"ingress_unit_${i+nInputs}_from_${u.ingressId}") }
val all_input_units = input_units ++ ingress_units
val output_units = outParams.zipWithIndex.map { case (u,i) =>
Module(new OutputUnit(inParams, ingressParams, u))
.suggestName(s"output_unit_${i}_to_${u.destId}")}
val egress_units = egressParams.zipWithIndex.map { case (u,i) =>
Module(new EgressUnit(routerParams.user.coupleSAVA && all_input_units.size == 1,
routerParams.user.combineSAST,
inParams, ingressParams, u))
.suggestName(s"egress_unit_${i+nOutputs}_to_${u.egressId}")}
val all_output_units = output_units ++ egress_units
val switch = Module(new Switch(routerParams, inParams, outParams, ingressParams, egressParams))
val switch_allocator = Module(new SwitchAllocator(routerParams, inParams, outParams, ingressParams, egressParams))
val vc_allocator = Module(routerParams.user.vcAllocator(
VCAllocatorParams(routerParams, inParams, outParams, ingressParams, egressParams)
)(p))
val route_computer = Module(new RouteComputer(routerParams, inParams, outParams, ingressParams, egressParams))
val fires_count = WireInit(PopCount(vc_allocator.io.req.map(_.fire)))
dontTouch(fires_count)
(io_in zip input_units ).foreach { case (i,u) => u.io.in <> i }
(io_ingress zip ingress_units).foreach { case (i,u) => u.io.in <> i.flit }
(output_units zip io_out ).foreach { case (u,o) => o <> u.io.out }
(egress_units zip io_egress).foreach { case (u,o) => o.flit <> u.io.out }
(route_computer.io.req zip all_input_units).foreach {
case (i,u) => i <> u.io.router_req }
(all_input_units zip route_computer.io.resp).foreach {
case (u,o) => u.io.router_resp <> o }
(vc_allocator.io.req zip all_input_units).foreach {
case (i,u) => i <> u.io.vcalloc_req }
(all_input_units zip vc_allocator.io.resp).foreach {
case (u,o) => u.io.vcalloc_resp <> o }
(all_output_units zip vc_allocator.io.out_allocs).foreach {
case (u,a) => u.io.allocs <> a }
(vc_allocator.io.channel_status zip all_output_units).foreach {
case (a,u) => a := u.io.channel_status }
all_input_units.foreach(in => all_output_units.zipWithIndex.foreach { case (out,outIdx) =>
in.io.out_credit_available(outIdx) := out.io.credit_available
})
(all_input_units zip switch_allocator.io.req).foreach {
case (u,r) => r <> u.io.salloc_req }
(all_output_units zip switch_allocator.io.credit_alloc).foreach {
case (u,a) => u.io.credit_alloc := a }
(switch.io.in zip all_input_units).foreach {
case (i,u) => i <> u.io.out }
(all_output_units zip switch.io.out).foreach {
case (u,o) => u.io.in <> o }
switch.io.sel := (if (routerParams.user.combineSAST) {
switch_allocator.io.switch_sel
} else {
RegNext(switch_allocator.io.switch_sel)
})
if (hasCtrl) {
val io_ctrl = ctrlNode.get.out(0)._1
val ctrl = Module(new RouterControlUnit(routerParams, inParams, outParams, ingressParams, egressParams))
io_ctrl <> ctrl.io.ctrl
(all_input_units zip ctrl.io.in_block ).foreach { case (l,r) => l.io.block := r }
(all_input_units zip ctrl.io.in_fire ).foreach { case (l,r) => r := l.io.out.map(_.valid) }
} else {
input_units.foreach(_.io.block := false.B)
ingress_units.foreach(_.io.block := false.B)
}
(io_debug.va_stall zip all_input_units.map(_.io.debug.va_stall)).map { case (l,r) => l := r }
(io_debug.sa_stall zip all_input_units.map(_.io.debug.sa_stall)).map { case (l,r) => l := r }
val debug_tsc = RegInit(0.U(64.W))
debug_tsc := debug_tsc + 1.U
val debug_sample = RegInit(0.U(64.W))
debug_sample := debug_sample + 1.U
val sample_rate = PlusArg("noc_util_sample_rate", width=20)
when (debug_sample === sample_rate - 1.U) { debug_sample := 0.U }
def sample(fire: Bool, s: String) = {
val util_ctr = RegInit(0.U(64.W))
val fired = RegInit(false.B)
util_ctr := util_ctr + fire
fired := fired || fire
when (sample_rate =/= 0.U && debug_sample === sample_rate - 1.U && fired) {
val fmtStr = s"nocsample %d $s %d\n"
printf(fmtStr, debug_tsc, util_ctr);
fired := fire
}
}
destNodes.map(_.in(0)).foreach { case (in, edge) => in.flit.map { f =>
sample(f.fire, s"${edge.cp.srcId} $nodeId")
} }
ingressNodes.map(_.in(0)).foreach { case (in, edge) =>
sample(in.flit.fire, s"i${edge.cp.asInstanceOf[IngressChannelParams].ingressId} $nodeId")
}
egressNodes.map(_.out(0)).foreach { case (out, edge) =>
sample(out.flit.fire, s"$nodeId e${edge.cp.asInstanceOf[EgressChannelParams].egressId}")
}
}
}
File LazyModuleImp.scala:
package org.chipsalliance.diplomacy.lazymodule
import chisel3.{withClockAndReset, Module, RawModule, Reset, _}
import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo}
import firrtl.passes.InlineAnnotation
import org.chipsalliance.cde.config.Parameters
import org.chipsalliance.diplomacy.nodes.Dangle
import scala.collection.immutable.SortedMap
/** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]].
*
* This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy.
*/
sealed trait LazyModuleImpLike extends RawModule {
/** [[LazyModule]] that contains this instance. */
val wrapper: LazyModule
/** IOs that will be automatically "punched" for this instance. */
val auto: AutoBundle
/** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */
protected[diplomacy] val dangles: Seq[Dangle]
// [[wrapper.module]] had better not be accessed while LazyModules are still being built!
require(
LazyModule.scope.isEmpty,
s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}"
)
/** Set module name. Defaults to the containing LazyModule's desiredName. */
override def desiredName: String = wrapper.desiredName
suggestName(wrapper.suggestedName)
/** [[Parameters]] for chisel [[Module]]s. */
implicit val p: Parameters = wrapper.p
/** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and
* submodules.
*/
protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = {
// 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]],
// 2. return [[Dangle]]s from each module.
val childDangles = wrapper.children.reverse.flatMap { c =>
implicit val sourceInfo: SourceInfo = c.info
c.cloneProto.map { cp =>
// If the child is a clone, then recursively set cloneProto of its children as well
def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = {
require(bases.size == clones.size)
(bases.zip(clones)).map { case (l, r) =>
require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}")
l.cloneProto = Some(r)
assignCloneProtos(l.children, r.children)
}
}
assignCloneProtos(c.children, cp.children)
// Clone the child module as a record, and get its [[AutoBundle]]
val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName)
val clonedAuto = clone("auto").asInstanceOf[AutoBundle]
// Get the empty [[Dangle]]'s of the cloned child
val rawDangles = c.cloneDangles()
require(rawDangles.size == clonedAuto.elements.size)
// Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s
val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) }
dangles
}.getOrElse {
// For non-clones, instantiate the child module
val mod = try {
Module(c.module)
} catch {
case e: ChiselException => {
println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}")
throw e
}
}
mod.dangles
}
}
// Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]].
// This will result in a sequence of [[Dangle]] from these [[BaseNode]]s.
val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate())
// Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]]
val allDangles = nodeDangles ++ childDangles
// Group [[allDangles]] by their [[source]].
val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*)
// For each [[source]] set of [[Dangle]]s of size 2, ensure that these
// can be connected as a source-sink pair (have opposite flipped value).
// Make the connection and mark them as [[done]].
val done = Set() ++ pairing.values.filter(_.size == 2).map {
case Seq(a, b) =>
require(a.flipped != b.flipped)
// @todo <> in chisel3 makes directionless connection.
if (a.flipped) {
a.data <> b.data
} else {
b.data <> a.data
}
a.source
case _ => None
}
// Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module.
val forward = allDangles.filter(d => !done(d.source))
// Generate [[AutoBundle]] IO from [[forward]].
val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*))
// Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]]
val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) =>
if (d.flipped) {
d.data <> io
} else {
io <> d.data
}
d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name)
}
// Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]].
wrapper.inModuleBody.reverse.foreach {
_()
}
if (wrapper.shouldBeInlined) {
chisel3.experimental.annotate(new ChiselAnnotation {
def toFirrtl = InlineAnnotation(toNamed)
})
}
// Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]].
(auto, dangles)
}
}
/** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike {
/** Instantiate hardware of this `Module`. */
val (auto, dangles) = instantiate()
}
/** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike {
// These wires are the default clock+reset for all LazyModule children.
// It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the
// [[LazyRawModuleImp]] children.
// Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly.
/** drive clock explicitly. */
val childClock: Clock = Wire(Clock())
/** drive reset explicitly. */
val childReset: Reset = Wire(Reset())
// the default is that these are disabled
childClock := false.B.asClock
childReset := chisel3.DontCare
def provideImplicitClockToLazyChildren: Boolean = false
val (auto, dangles) =
if (provideImplicitClockToLazyChildren) {
withClockAndReset(childClock, childReset) { instantiate() }
} else {
instantiate()
}
}
| module Router_26( // @[Router.scala:89:25]
input clock, // @[Router.scala:89:25]
input reset, // @[Router.scala:89:25]
output auto_debug_out_va_stall_0, // @[LazyModuleImp.scala:107:25]
output auto_debug_out_va_stall_1, // @[LazyModuleImp.scala:107:25]
output auto_debug_out_va_stall_2, // @[LazyModuleImp.scala:107:25]
output auto_debug_out_va_stall_3, // @[LazyModuleImp.scala:107:25]
output auto_debug_out_va_stall_4, // @[LazyModuleImp.scala:107:25]
output auto_debug_out_sa_stall_0, // @[LazyModuleImp.scala:107:25]
output auto_debug_out_sa_stall_1, // @[LazyModuleImp.scala:107:25]
output auto_debug_out_sa_stall_2, // @[LazyModuleImp.scala:107:25]
output auto_debug_out_sa_stall_3, // @[LazyModuleImp.scala:107:25]
output auto_debug_out_sa_stall_4, // @[LazyModuleImp.scala:107:25]
input auto_egress_nodes_out_flit_ready, // @[LazyModuleImp.scala:107:25]
output auto_egress_nodes_out_flit_valid, // @[LazyModuleImp.scala:107:25]
output auto_egress_nodes_out_flit_bits_head, // @[LazyModuleImp.scala:107:25]
output auto_egress_nodes_out_flit_bits_tail, // @[LazyModuleImp.scala:107:25]
output [36:0] auto_egress_nodes_out_flit_bits_payload, // @[LazyModuleImp.scala:107:25]
output auto_ingress_nodes_in_flit_ready, // @[LazyModuleImp.scala:107:25]
input auto_ingress_nodes_in_flit_valid, // @[LazyModuleImp.scala:107:25]
input auto_ingress_nodes_in_flit_bits_head, // @[LazyModuleImp.scala:107:25]
input auto_ingress_nodes_in_flit_bits_tail, // @[LazyModuleImp.scala:107:25]
input [36:0] auto_ingress_nodes_in_flit_bits_payload, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_ingress_nodes_in_flit_bits_egress_id, // @[LazyModuleImp.scala:107:25]
output auto_source_nodes_out_3_flit_0_valid, // @[LazyModuleImp.scala:107:25]
output auto_source_nodes_out_3_flit_0_bits_head, // @[LazyModuleImp.scala:107:25]
output auto_source_nodes_out_3_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25]
output [36:0] auto_source_nodes_out_3_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25]
output auto_source_nodes_out_3_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_source_nodes_out_3_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_source_nodes_out_3_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_source_nodes_out_3_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_source_nodes_out_3_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25]
output auto_source_nodes_out_3_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_source_nodes_out_3_credit_return, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_source_nodes_out_3_vc_free, // @[LazyModuleImp.scala:107:25]
output auto_source_nodes_out_2_flit_0_valid, // @[LazyModuleImp.scala:107:25]
output auto_source_nodes_out_2_flit_0_bits_head, // @[LazyModuleImp.scala:107:25]
output auto_source_nodes_out_2_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25]
output [36:0] auto_source_nodes_out_2_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25]
output auto_source_nodes_out_2_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_source_nodes_out_2_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_source_nodes_out_2_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_source_nodes_out_2_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_source_nodes_out_2_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25]
output auto_source_nodes_out_2_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_source_nodes_out_2_credit_return, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_source_nodes_out_2_vc_free, // @[LazyModuleImp.scala:107:25]
output auto_source_nodes_out_1_flit_0_valid, // @[LazyModuleImp.scala:107:25]
output auto_source_nodes_out_1_flit_0_bits_head, // @[LazyModuleImp.scala:107:25]
output auto_source_nodes_out_1_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25]
output [36:0] auto_source_nodes_out_1_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25]
output auto_source_nodes_out_1_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_source_nodes_out_1_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_source_nodes_out_1_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_source_nodes_out_1_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_source_nodes_out_1_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25]
output auto_source_nodes_out_1_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_source_nodes_out_1_credit_return, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_source_nodes_out_1_vc_free, // @[LazyModuleImp.scala:107:25]
output auto_source_nodes_out_0_flit_0_valid, // @[LazyModuleImp.scala:107:25]
output auto_source_nodes_out_0_flit_0_bits_head, // @[LazyModuleImp.scala:107:25]
output auto_source_nodes_out_0_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25]
output [36:0] auto_source_nodes_out_0_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25]
output auto_source_nodes_out_0_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_source_nodes_out_0_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_source_nodes_out_0_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_source_nodes_out_0_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_source_nodes_out_0_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25]
output auto_source_nodes_out_0_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_source_nodes_out_0_credit_return, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_source_nodes_out_0_vc_free, // @[LazyModuleImp.scala:107:25]
input auto_dest_nodes_in_3_flit_0_valid, // @[LazyModuleImp.scala:107:25]
input auto_dest_nodes_in_3_flit_0_bits_head, // @[LazyModuleImp.scala:107:25]
input auto_dest_nodes_in_3_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25]
input [36:0] auto_dest_nodes_in_3_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25]
input auto_dest_nodes_in_3_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_dest_nodes_in_3_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_dest_nodes_in_3_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_dest_nodes_in_3_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_dest_nodes_in_3_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25]
input auto_dest_nodes_in_3_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_dest_nodes_in_3_credit_return, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_dest_nodes_in_3_vc_free, // @[LazyModuleImp.scala:107:25]
input auto_dest_nodes_in_2_flit_0_valid, // @[LazyModuleImp.scala:107:25]
input auto_dest_nodes_in_2_flit_0_bits_head, // @[LazyModuleImp.scala:107:25]
input auto_dest_nodes_in_2_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25]
input [36:0] auto_dest_nodes_in_2_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25]
input auto_dest_nodes_in_2_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_dest_nodes_in_2_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_dest_nodes_in_2_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_dest_nodes_in_2_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_dest_nodes_in_2_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25]
input auto_dest_nodes_in_2_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_dest_nodes_in_2_credit_return, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_dest_nodes_in_2_vc_free, // @[LazyModuleImp.scala:107:25]
input auto_dest_nodes_in_1_flit_0_valid, // @[LazyModuleImp.scala:107:25]
input auto_dest_nodes_in_1_flit_0_bits_head, // @[LazyModuleImp.scala:107:25]
input auto_dest_nodes_in_1_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25]
input [36:0] auto_dest_nodes_in_1_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25]
input auto_dest_nodes_in_1_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_dest_nodes_in_1_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_dest_nodes_in_1_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_dest_nodes_in_1_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_dest_nodes_in_1_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25]
input auto_dest_nodes_in_1_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_dest_nodes_in_1_credit_return, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_dest_nodes_in_1_vc_free, // @[LazyModuleImp.scala:107:25]
input auto_dest_nodes_in_0_flit_0_valid, // @[LazyModuleImp.scala:107:25]
input auto_dest_nodes_in_0_flit_0_bits_head, // @[LazyModuleImp.scala:107:25]
input auto_dest_nodes_in_0_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25]
input [36:0] auto_dest_nodes_in_0_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25]
input auto_dest_nodes_in_0_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_dest_nodes_in_0_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_dest_nodes_in_0_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_dest_nodes_in_0_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_dest_nodes_in_0_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25]
input auto_dest_nodes_in_0_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_dest_nodes_in_0_credit_return, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_dest_nodes_in_0_vc_free // @[LazyModuleImp.scala:107:25]
);
wire [19:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire _route_computer_io_resp_4_vc_sel_3_0; // @[Router.scala:136:32]
wire _route_computer_io_resp_4_vc_sel_3_1; // @[Router.scala:136:32]
wire _route_computer_io_resp_4_vc_sel_2_0; // @[Router.scala:136:32]
wire _route_computer_io_resp_4_vc_sel_2_1; // @[Router.scala:136:32]
wire _route_computer_io_resp_4_vc_sel_1_0; // @[Router.scala:136:32]
wire _route_computer_io_resp_4_vc_sel_1_1; // @[Router.scala:136:32]
wire _route_computer_io_resp_4_vc_sel_0_0; // @[Router.scala:136:32]
wire _route_computer_io_resp_4_vc_sel_0_1; // @[Router.scala:136:32]
wire _route_computer_io_resp_3_vc_sel_3_0; // @[Router.scala:136:32]
wire _route_computer_io_resp_3_vc_sel_3_1; // @[Router.scala:136:32]
wire _route_computer_io_resp_3_vc_sel_2_0; // @[Router.scala:136:32]
wire _route_computer_io_resp_3_vc_sel_2_1; // @[Router.scala:136:32]
wire _route_computer_io_resp_3_vc_sel_1_0; // @[Router.scala:136:32]
wire _route_computer_io_resp_3_vc_sel_1_1; // @[Router.scala:136:32]
wire _route_computer_io_resp_3_vc_sel_0_0; // @[Router.scala:136:32]
wire _route_computer_io_resp_3_vc_sel_0_1; // @[Router.scala:136:32]
wire _route_computer_io_resp_2_vc_sel_3_0; // @[Router.scala:136:32]
wire _route_computer_io_resp_2_vc_sel_3_1; // @[Router.scala:136:32]
wire _route_computer_io_resp_2_vc_sel_2_0; // @[Router.scala:136:32]
wire _route_computer_io_resp_2_vc_sel_2_1; // @[Router.scala:136:32]
wire _route_computer_io_resp_2_vc_sel_1_0; // @[Router.scala:136:32]
wire _route_computer_io_resp_2_vc_sel_1_1; // @[Router.scala:136:32]
wire _route_computer_io_resp_2_vc_sel_0_0; // @[Router.scala:136:32]
wire _route_computer_io_resp_2_vc_sel_0_1; // @[Router.scala:136:32]
wire _route_computer_io_resp_1_vc_sel_3_0; // @[Router.scala:136:32]
wire _route_computer_io_resp_1_vc_sel_3_1; // @[Router.scala:136:32]
wire _route_computer_io_resp_1_vc_sel_2_0; // @[Router.scala:136:32]
wire _route_computer_io_resp_1_vc_sel_2_1; // @[Router.scala:136:32]
wire _route_computer_io_resp_1_vc_sel_1_0; // @[Router.scala:136:32]
wire _route_computer_io_resp_1_vc_sel_1_1; // @[Router.scala:136:32]
wire _route_computer_io_resp_1_vc_sel_0_0; // @[Router.scala:136:32]
wire _route_computer_io_resp_1_vc_sel_0_1; // @[Router.scala:136:32]
wire _route_computer_io_resp_0_vc_sel_3_0; // @[Router.scala:136:32]
wire _route_computer_io_resp_0_vc_sel_3_1; // @[Router.scala:136:32]
wire _route_computer_io_resp_0_vc_sel_2_0; // @[Router.scala:136:32]
wire _route_computer_io_resp_0_vc_sel_2_1; // @[Router.scala:136:32]
wire _route_computer_io_resp_0_vc_sel_1_0; // @[Router.scala:136:32]
wire _route_computer_io_resp_0_vc_sel_1_1; // @[Router.scala:136:32]
wire _route_computer_io_resp_0_vc_sel_0_0; // @[Router.scala:136:32]
wire _route_computer_io_resp_0_vc_sel_0_1; // @[Router.scala:136:32]
wire _vc_allocator_io_req_4_ready; // @[Router.scala:133:30]
wire _vc_allocator_io_req_3_ready; // @[Router.scala:133:30]
wire _vc_allocator_io_req_2_ready; // @[Router.scala:133:30]
wire _vc_allocator_io_req_1_ready; // @[Router.scala:133:30]
wire _vc_allocator_io_req_0_ready; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_4_vc_sel_4_0; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_4_vc_sel_3_0; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_4_vc_sel_3_1; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_4_vc_sel_2_0; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_4_vc_sel_2_1; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_4_vc_sel_1_0; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_4_vc_sel_1_1; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_4_vc_sel_0_0; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_4_vc_sel_0_1; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_3_vc_sel_4_0; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_3_vc_sel_0_0; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_2_vc_sel_4_0; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_2_vc_sel_1_0; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_2_vc_sel_0_0; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_1_vc_sel_4_0; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_1_vc_sel_3_1; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_1_vc_sel_2_1; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_1_vc_sel_0_0; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_1_vc_sel_0_1; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_0_vc_sel_4_0; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_0_vc_sel_3_1; // @[Router.scala:133:30]
wire _vc_allocator_io_out_allocs_4_0_alloc; // @[Router.scala:133:30]
wire _vc_allocator_io_out_allocs_3_1_alloc; // @[Router.scala:133:30]
wire _vc_allocator_io_out_allocs_2_1_alloc; // @[Router.scala:133:30]
wire _vc_allocator_io_out_allocs_1_0_alloc; // @[Router.scala:133:30]
wire _vc_allocator_io_out_allocs_1_1_alloc; // @[Router.scala:133:30]
wire _vc_allocator_io_out_allocs_0_0_alloc; // @[Router.scala:133:30]
wire _vc_allocator_io_out_allocs_0_1_alloc; // @[Router.scala:133:30]
wire _switch_allocator_io_req_4_0_ready; // @[Router.scala:132:34]
wire _switch_allocator_io_req_3_0_ready; // @[Router.scala:132:34]
wire _switch_allocator_io_req_2_0_ready; // @[Router.scala:132:34]
wire _switch_allocator_io_req_1_0_ready; // @[Router.scala:132:34]
wire _switch_allocator_io_req_0_0_ready; // @[Router.scala:132:34]
wire _switch_allocator_io_credit_alloc_4_0_alloc; // @[Router.scala:132:34]
wire _switch_allocator_io_credit_alloc_4_0_tail; // @[Router.scala:132:34]
wire _switch_allocator_io_credit_alloc_3_1_alloc; // @[Router.scala:132:34]
wire _switch_allocator_io_credit_alloc_2_1_alloc; // @[Router.scala:132:34]
wire _switch_allocator_io_credit_alloc_1_0_alloc; // @[Router.scala:132:34]
wire _switch_allocator_io_credit_alloc_1_1_alloc; // @[Router.scala:132:34]
wire _switch_allocator_io_credit_alloc_0_0_alloc; // @[Router.scala:132:34]
wire _switch_allocator_io_credit_alloc_0_1_alloc; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_4_0_4_0; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_4_0_3_0; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_4_0_2_0; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_4_0_1_0; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_4_0_0_0; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_3_0_4_0; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_3_0_3_0; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_3_0_2_0; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_3_0_1_0; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_3_0_0_0; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_2_0_4_0; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_2_0_3_0; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_2_0_2_0; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_2_0_1_0; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_2_0_0_0; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_1_0_4_0; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_1_0_3_0; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_1_0_2_0; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_1_0_1_0; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_1_0_0_0; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_0_0_4_0; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_0_0_3_0; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_0_0_2_0; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_0_0_1_0; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_0_0_0_0; // @[Router.scala:132:34]
wire _switch_io_out_4_0_valid; // @[Router.scala:131:24]
wire _switch_io_out_4_0_bits_head; // @[Router.scala:131:24]
wire _switch_io_out_4_0_bits_tail; // @[Router.scala:131:24]
wire [36:0] _switch_io_out_4_0_bits_payload; // @[Router.scala:131:24]
wire [3:0] _switch_io_out_4_0_bits_flow_ingress_node; // @[Router.scala:131:24]
wire [1:0] _switch_io_out_4_0_bits_flow_ingress_node_id; // @[Router.scala:131:24]
wire _switch_io_out_3_0_valid; // @[Router.scala:131:24]
wire _switch_io_out_3_0_bits_head; // @[Router.scala:131:24]
wire _switch_io_out_3_0_bits_tail; // @[Router.scala:131:24]
wire [36:0] _switch_io_out_3_0_bits_payload; // @[Router.scala:131:24]
wire _switch_io_out_3_0_bits_flow_vnet_id; // @[Router.scala:131:24]
wire [3:0] _switch_io_out_3_0_bits_flow_ingress_node; // @[Router.scala:131:24]
wire [1:0] _switch_io_out_3_0_bits_flow_ingress_node_id; // @[Router.scala:131:24]
wire [3:0] _switch_io_out_3_0_bits_flow_egress_node; // @[Router.scala:131:24]
wire [1:0] _switch_io_out_3_0_bits_flow_egress_node_id; // @[Router.scala:131:24]
wire _switch_io_out_3_0_bits_virt_channel_id; // @[Router.scala:131:24]
wire _switch_io_out_2_0_valid; // @[Router.scala:131:24]
wire _switch_io_out_2_0_bits_head; // @[Router.scala:131:24]
wire _switch_io_out_2_0_bits_tail; // @[Router.scala:131:24]
wire [36:0] _switch_io_out_2_0_bits_payload; // @[Router.scala:131:24]
wire _switch_io_out_2_0_bits_flow_vnet_id; // @[Router.scala:131:24]
wire [3:0] _switch_io_out_2_0_bits_flow_ingress_node; // @[Router.scala:131:24]
wire [1:0] _switch_io_out_2_0_bits_flow_ingress_node_id; // @[Router.scala:131:24]
wire [3:0] _switch_io_out_2_0_bits_flow_egress_node; // @[Router.scala:131:24]
wire [1:0] _switch_io_out_2_0_bits_flow_egress_node_id; // @[Router.scala:131:24]
wire _switch_io_out_2_0_bits_virt_channel_id; // @[Router.scala:131:24]
wire _switch_io_out_1_0_valid; // @[Router.scala:131:24]
wire _switch_io_out_1_0_bits_head; // @[Router.scala:131:24]
wire _switch_io_out_1_0_bits_tail; // @[Router.scala:131:24]
wire [36:0] _switch_io_out_1_0_bits_payload; // @[Router.scala:131:24]
wire _switch_io_out_1_0_bits_flow_vnet_id; // @[Router.scala:131:24]
wire [3:0] _switch_io_out_1_0_bits_flow_ingress_node; // @[Router.scala:131:24]
wire [1:0] _switch_io_out_1_0_bits_flow_ingress_node_id; // @[Router.scala:131:24]
wire [3:0] _switch_io_out_1_0_bits_flow_egress_node; // @[Router.scala:131:24]
wire [1:0] _switch_io_out_1_0_bits_flow_egress_node_id; // @[Router.scala:131:24]
wire _switch_io_out_1_0_bits_virt_channel_id; // @[Router.scala:131:24]
wire _switch_io_out_0_0_valid; // @[Router.scala:131:24]
wire _switch_io_out_0_0_bits_head; // @[Router.scala:131:24]
wire _switch_io_out_0_0_bits_tail; // @[Router.scala:131:24]
wire [36:0] _switch_io_out_0_0_bits_payload; // @[Router.scala:131:24]
wire _switch_io_out_0_0_bits_flow_vnet_id; // @[Router.scala:131:24]
wire [3:0] _switch_io_out_0_0_bits_flow_ingress_node; // @[Router.scala:131:24]
wire [1:0] _switch_io_out_0_0_bits_flow_ingress_node_id; // @[Router.scala:131:24]
wire [3:0] _switch_io_out_0_0_bits_flow_egress_node; // @[Router.scala:131:24]
wire [1:0] _switch_io_out_0_0_bits_flow_egress_node_id; // @[Router.scala:131:24]
wire _switch_io_out_0_0_bits_virt_channel_id; // @[Router.scala:131:24]
wire _egress_unit_4_to_17_io_credit_available_0; // @[Router.scala:125:13]
wire _egress_unit_4_to_17_io_channel_status_0_occupied; // @[Router.scala:125:13]
wire _egress_unit_4_to_17_io_out_valid; // @[Router.scala:125:13]
wire _output_unit_3_to_14_io_credit_available_1; // @[Router.scala:122:13]
wire _output_unit_3_to_14_io_channel_status_1_occupied; // @[Router.scala:122:13]
wire _output_unit_2_to_11_io_credit_available_1; // @[Router.scala:122:13]
wire _output_unit_2_to_11_io_channel_status_1_occupied; // @[Router.scala:122:13]
wire _output_unit_1_to_9_io_credit_available_0; // @[Router.scala:122:13]
wire _output_unit_1_to_9_io_credit_available_1; // @[Router.scala:122:13]
wire _output_unit_1_to_9_io_channel_status_0_occupied; // @[Router.scala:122:13]
wire _output_unit_1_to_9_io_channel_status_1_occupied; // @[Router.scala:122:13]
wire _output_unit_0_to_6_io_credit_available_0; // @[Router.scala:122:13]
wire _output_unit_0_to_6_io_credit_available_1; // @[Router.scala:122:13]
wire _output_unit_0_to_6_io_channel_status_0_occupied; // @[Router.scala:122:13]
wire _output_unit_0_to_6_io_channel_status_1_occupied; // @[Router.scala:122:13]
wire [3:0] _ingress_unit_4_from_17_io_router_req_bits_flow_egress_node; // @[Router.scala:116:13]
wire [1:0] _ingress_unit_4_from_17_io_router_req_bits_flow_egress_node_id; // @[Router.scala:116:13]
wire _ingress_unit_4_from_17_io_vcalloc_req_valid; // @[Router.scala:116:13]
wire _ingress_unit_4_from_17_io_vcalloc_req_bits_vc_sel_4_0; // @[Router.scala:116:13]
wire _ingress_unit_4_from_17_io_vcalloc_req_bits_vc_sel_3_0; // @[Router.scala:116:13]
wire _ingress_unit_4_from_17_io_vcalloc_req_bits_vc_sel_3_1; // @[Router.scala:116:13]
wire _ingress_unit_4_from_17_io_vcalloc_req_bits_vc_sel_2_0; // @[Router.scala:116:13]
wire _ingress_unit_4_from_17_io_vcalloc_req_bits_vc_sel_2_1; // @[Router.scala:116:13]
wire _ingress_unit_4_from_17_io_vcalloc_req_bits_vc_sel_1_0; // @[Router.scala:116:13]
wire _ingress_unit_4_from_17_io_vcalloc_req_bits_vc_sel_1_1; // @[Router.scala:116:13]
wire _ingress_unit_4_from_17_io_vcalloc_req_bits_vc_sel_0_0; // @[Router.scala:116:13]
wire _ingress_unit_4_from_17_io_vcalloc_req_bits_vc_sel_0_1; // @[Router.scala:116:13]
wire _ingress_unit_4_from_17_io_salloc_req_0_valid; // @[Router.scala:116:13]
wire _ingress_unit_4_from_17_io_salloc_req_0_bits_vc_sel_4_0; // @[Router.scala:116:13]
wire _ingress_unit_4_from_17_io_salloc_req_0_bits_vc_sel_3_0; // @[Router.scala:116:13]
wire _ingress_unit_4_from_17_io_salloc_req_0_bits_vc_sel_3_1; // @[Router.scala:116:13]
wire _ingress_unit_4_from_17_io_salloc_req_0_bits_vc_sel_2_0; // @[Router.scala:116:13]
wire _ingress_unit_4_from_17_io_salloc_req_0_bits_vc_sel_2_1; // @[Router.scala:116:13]
wire _ingress_unit_4_from_17_io_salloc_req_0_bits_vc_sel_1_0; // @[Router.scala:116:13]
wire _ingress_unit_4_from_17_io_salloc_req_0_bits_vc_sel_1_1; // @[Router.scala:116:13]
wire _ingress_unit_4_from_17_io_salloc_req_0_bits_vc_sel_0_0; // @[Router.scala:116:13]
wire _ingress_unit_4_from_17_io_salloc_req_0_bits_vc_sel_0_1; // @[Router.scala:116:13]
wire _ingress_unit_4_from_17_io_salloc_req_0_bits_tail; // @[Router.scala:116:13]
wire _ingress_unit_4_from_17_io_out_0_valid; // @[Router.scala:116:13]
wire _ingress_unit_4_from_17_io_out_0_bits_flit_head; // @[Router.scala:116:13]
wire _ingress_unit_4_from_17_io_out_0_bits_flit_tail; // @[Router.scala:116:13]
wire [36:0] _ingress_unit_4_from_17_io_out_0_bits_flit_payload; // @[Router.scala:116:13]
wire _ingress_unit_4_from_17_io_out_0_bits_flit_flow_vnet_id; // @[Router.scala:116:13]
wire [3:0] _ingress_unit_4_from_17_io_out_0_bits_flit_flow_ingress_node; // @[Router.scala:116:13]
wire [1:0] _ingress_unit_4_from_17_io_out_0_bits_flit_flow_ingress_node_id; // @[Router.scala:116:13]
wire [3:0] _ingress_unit_4_from_17_io_out_0_bits_flit_flow_egress_node; // @[Router.scala:116:13]
wire [1:0] _ingress_unit_4_from_17_io_out_0_bits_flit_flow_egress_node_id; // @[Router.scala:116:13]
wire _ingress_unit_4_from_17_io_out_0_bits_out_virt_channel; // @[Router.scala:116:13]
wire _ingress_unit_4_from_17_io_in_ready; // @[Router.scala:116:13]
wire _input_unit_3_from_14_io_router_req_bits_src_virt_id; // @[Router.scala:112:13]
wire _input_unit_3_from_14_io_router_req_bits_flow_vnet_id; // @[Router.scala:112:13]
wire [3:0] _input_unit_3_from_14_io_router_req_bits_flow_ingress_node; // @[Router.scala:112:13]
wire [1:0] _input_unit_3_from_14_io_router_req_bits_flow_ingress_node_id; // @[Router.scala:112:13]
wire [3:0] _input_unit_3_from_14_io_router_req_bits_flow_egress_node; // @[Router.scala:112:13]
wire [1:0] _input_unit_3_from_14_io_router_req_bits_flow_egress_node_id; // @[Router.scala:112:13]
wire _input_unit_3_from_14_io_vcalloc_req_valid; // @[Router.scala:112:13]
wire _input_unit_3_from_14_io_vcalloc_req_bits_vc_sel_4_0; // @[Router.scala:112:13]
wire _input_unit_3_from_14_io_vcalloc_req_bits_vc_sel_3_0; // @[Router.scala:112:13]
wire _input_unit_3_from_14_io_vcalloc_req_bits_vc_sel_3_1; // @[Router.scala:112:13]
wire _input_unit_3_from_14_io_vcalloc_req_bits_vc_sel_2_0; // @[Router.scala:112:13]
wire _input_unit_3_from_14_io_vcalloc_req_bits_vc_sel_2_1; // @[Router.scala:112:13]
wire _input_unit_3_from_14_io_vcalloc_req_bits_vc_sel_1_0; // @[Router.scala:112:13]
wire _input_unit_3_from_14_io_vcalloc_req_bits_vc_sel_1_1; // @[Router.scala:112:13]
wire _input_unit_3_from_14_io_vcalloc_req_bits_vc_sel_0_0; // @[Router.scala:112:13]
wire _input_unit_3_from_14_io_vcalloc_req_bits_vc_sel_0_1; // @[Router.scala:112:13]
wire _input_unit_3_from_14_io_salloc_req_0_valid; // @[Router.scala:112:13]
wire _input_unit_3_from_14_io_salloc_req_0_bits_vc_sel_4_0; // @[Router.scala:112:13]
wire _input_unit_3_from_14_io_salloc_req_0_bits_vc_sel_3_0; // @[Router.scala:112:13]
wire _input_unit_3_from_14_io_salloc_req_0_bits_vc_sel_3_1; // @[Router.scala:112:13]
wire _input_unit_3_from_14_io_salloc_req_0_bits_vc_sel_2_0; // @[Router.scala:112:13]
wire _input_unit_3_from_14_io_salloc_req_0_bits_vc_sel_2_1; // @[Router.scala:112:13]
wire _input_unit_3_from_14_io_salloc_req_0_bits_vc_sel_1_0; // @[Router.scala:112:13]
wire _input_unit_3_from_14_io_salloc_req_0_bits_vc_sel_1_1; // @[Router.scala:112:13]
wire _input_unit_3_from_14_io_salloc_req_0_bits_vc_sel_0_0; // @[Router.scala:112:13]
wire _input_unit_3_from_14_io_salloc_req_0_bits_vc_sel_0_1; // @[Router.scala:112:13]
wire _input_unit_3_from_14_io_salloc_req_0_bits_tail; // @[Router.scala:112:13]
wire _input_unit_3_from_14_io_out_0_valid; // @[Router.scala:112:13]
wire _input_unit_3_from_14_io_out_0_bits_flit_head; // @[Router.scala:112:13]
wire _input_unit_3_from_14_io_out_0_bits_flit_tail; // @[Router.scala:112:13]
wire [36:0] _input_unit_3_from_14_io_out_0_bits_flit_payload; // @[Router.scala:112:13]
wire _input_unit_3_from_14_io_out_0_bits_flit_flow_vnet_id; // @[Router.scala:112:13]
wire [3:0] _input_unit_3_from_14_io_out_0_bits_flit_flow_ingress_node; // @[Router.scala:112:13]
wire [1:0] _input_unit_3_from_14_io_out_0_bits_flit_flow_ingress_node_id; // @[Router.scala:112:13]
wire [3:0] _input_unit_3_from_14_io_out_0_bits_flit_flow_egress_node; // @[Router.scala:112:13]
wire [1:0] _input_unit_3_from_14_io_out_0_bits_flit_flow_egress_node_id; // @[Router.scala:112:13]
wire _input_unit_3_from_14_io_out_0_bits_out_virt_channel; // @[Router.scala:112:13]
wire _input_unit_2_from_11_io_router_req_bits_src_virt_id; // @[Router.scala:112:13]
wire _input_unit_2_from_11_io_router_req_bits_flow_vnet_id; // @[Router.scala:112:13]
wire [3:0] _input_unit_2_from_11_io_router_req_bits_flow_ingress_node; // @[Router.scala:112:13]
wire [1:0] _input_unit_2_from_11_io_router_req_bits_flow_ingress_node_id; // @[Router.scala:112:13]
wire [3:0] _input_unit_2_from_11_io_router_req_bits_flow_egress_node; // @[Router.scala:112:13]
wire [1:0] _input_unit_2_from_11_io_router_req_bits_flow_egress_node_id; // @[Router.scala:112:13]
wire _input_unit_2_from_11_io_vcalloc_req_valid; // @[Router.scala:112:13]
wire _input_unit_2_from_11_io_vcalloc_req_bits_vc_sel_4_0; // @[Router.scala:112:13]
wire _input_unit_2_from_11_io_vcalloc_req_bits_vc_sel_3_0; // @[Router.scala:112:13]
wire _input_unit_2_from_11_io_vcalloc_req_bits_vc_sel_3_1; // @[Router.scala:112:13]
wire _input_unit_2_from_11_io_vcalloc_req_bits_vc_sel_2_0; // @[Router.scala:112:13]
wire _input_unit_2_from_11_io_vcalloc_req_bits_vc_sel_2_1; // @[Router.scala:112:13]
wire _input_unit_2_from_11_io_vcalloc_req_bits_vc_sel_1_0; // @[Router.scala:112:13]
wire _input_unit_2_from_11_io_vcalloc_req_bits_vc_sel_1_1; // @[Router.scala:112:13]
wire _input_unit_2_from_11_io_vcalloc_req_bits_vc_sel_0_0; // @[Router.scala:112:13]
wire _input_unit_2_from_11_io_vcalloc_req_bits_vc_sel_0_1; // @[Router.scala:112:13]
wire _input_unit_2_from_11_io_salloc_req_0_valid; // @[Router.scala:112:13]
wire _input_unit_2_from_11_io_salloc_req_0_bits_vc_sel_4_0; // @[Router.scala:112:13]
wire _input_unit_2_from_11_io_salloc_req_0_bits_vc_sel_3_0; // @[Router.scala:112:13]
wire _input_unit_2_from_11_io_salloc_req_0_bits_vc_sel_3_1; // @[Router.scala:112:13]
wire _input_unit_2_from_11_io_salloc_req_0_bits_vc_sel_2_0; // @[Router.scala:112:13]
wire _input_unit_2_from_11_io_salloc_req_0_bits_vc_sel_2_1; // @[Router.scala:112:13]
wire _input_unit_2_from_11_io_salloc_req_0_bits_vc_sel_1_0; // @[Router.scala:112:13]
wire _input_unit_2_from_11_io_salloc_req_0_bits_vc_sel_1_1; // @[Router.scala:112:13]
wire _input_unit_2_from_11_io_salloc_req_0_bits_vc_sel_0_0; // @[Router.scala:112:13]
wire _input_unit_2_from_11_io_salloc_req_0_bits_vc_sel_0_1; // @[Router.scala:112:13]
wire _input_unit_2_from_11_io_salloc_req_0_bits_tail; // @[Router.scala:112:13]
wire _input_unit_2_from_11_io_out_0_valid; // @[Router.scala:112:13]
wire _input_unit_2_from_11_io_out_0_bits_flit_head; // @[Router.scala:112:13]
wire _input_unit_2_from_11_io_out_0_bits_flit_tail; // @[Router.scala:112:13]
wire [36:0] _input_unit_2_from_11_io_out_0_bits_flit_payload; // @[Router.scala:112:13]
wire _input_unit_2_from_11_io_out_0_bits_flit_flow_vnet_id; // @[Router.scala:112:13]
wire [3:0] _input_unit_2_from_11_io_out_0_bits_flit_flow_ingress_node; // @[Router.scala:112:13]
wire [1:0] _input_unit_2_from_11_io_out_0_bits_flit_flow_ingress_node_id; // @[Router.scala:112:13]
wire [3:0] _input_unit_2_from_11_io_out_0_bits_flit_flow_egress_node; // @[Router.scala:112:13]
wire [1:0] _input_unit_2_from_11_io_out_0_bits_flit_flow_egress_node_id; // @[Router.scala:112:13]
wire _input_unit_2_from_11_io_out_0_bits_out_virt_channel; // @[Router.scala:112:13]
wire _input_unit_1_from_9_io_router_req_bits_src_virt_id; // @[Router.scala:112:13]
wire _input_unit_1_from_9_io_router_req_bits_flow_vnet_id; // @[Router.scala:112:13]
wire [3:0] _input_unit_1_from_9_io_router_req_bits_flow_ingress_node; // @[Router.scala:112:13]
wire [1:0] _input_unit_1_from_9_io_router_req_bits_flow_ingress_node_id; // @[Router.scala:112:13]
wire [3:0] _input_unit_1_from_9_io_router_req_bits_flow_egress_node; // @[Router.scala:112:13]
wire [1:0] _input_unit_1_from_9_io_router_req_bits_flow_egress_node_id; // @[Router.scala:112:13]
wire _input_unit_1_from_9_io_vcalloc_req_valid; // @[Router.scala:112:13]
wire _input_unit_1_from_9_io_vcalloc_req_bits_vc_sel_4_0; // @[Router.scala:112:13]
wire _input_unit_1_from_9_io_vcalloc_req_bits_vc_sel_3_0; // @[Router.scala:112:13]
wire _input_unit_1_from_9_io_vcalloc_req_bits_vc_sel_3_1; // @[Router.scala:112:13]
wire _input_unit_1_from_9_io_vcalloc_req_bits_vc_sel_2_0; // @[Router.scala:112:13]
wire _input_unit_1_from_9_io_vcalloc_req_bits_vc_sel_2_1; // @[Router.scala:112:13]
wire _input_unit_1_from_9_io_vcalloc_req_bits_vc_sel_1_0; // @[Router.scala:112:13]
wire _input_unit_1_from_9_io_vcalloc_req_bits_vc_sel_1_1; // @[Router.scala:112:13]
wire _input_unit_1_from_9_io_vcalloc_req_bits_vc_sel_0_0; // @[Router.scala:112:13]
wire _input_unit_1_from_9_io_vcalloc_req_bits_vc_sel_0_1; // @[Router.scala:112:13]
wire _input_unit_1_from_9_io_salloc_req_0_valid; // @[Router.scala:112:13]
wire _input_unit_1_from_9_io_salloc_req_0_bits_vc_sel_4_0; // @[Router.scala:112:13]
wire _input_unit_1_from_9_io_salloc_req_0_bits_vc_sel_3_0; // @[Router.scala:112:13]
wire _input_unit_1_from_9_io_salloc_req_0_bits_vc_sel_3_1; // @[Router.scala:112:13]
wire _input_unit_1_from_9_io_salloc_req_0_bits_vc_sel_2_0; // @[Router.scala:112:13]
wire _input_unit_1_from_9_io_salloc_req_0_bits_vc_sel_2_1; // @[Router.scala:112:13]
wire _input_unit_1_from_9_io_salloc_req_0_bits_vc_sel_1_0; // @[Router.scala:112:13]
wire _input_unit_1_from_9_io_salloc_req_0_bits_vc_sel_1_1; // @[Router.scala:112:13]
wire _input_unit_1_from_9_io_salloc_req_0_bits_vc_sel_0_0; // @[Router.scala:112:13]
wire _input_unit_1_from_9_io_salloc_req_0_bits_vc_sel_0_1; // @[Router.scala:112:13]
wire _input_unit_1_from_9_io_salloc_req_0_bits_tail; // @[Router.scala:112:13]
wire _input_unit_1_from_9_io_out_0_valid; // @[Router.scala:112:13]
wire _input_unit_1_from_9_io_out_0_bits_flit_head; // @[Router.scala:112:13]
wire _input_unit_1_from_9_io_out_0_bits_flit_tail; // @[Router.scala:112:13]
wire [36:0] _input_unit_1_from_9_io_out_0_bits_flit_payload; // @[Router.scala:112:13]
wire _input_unit_1_from_9_io_out_0_bits_flit_flow_vnet_id; // @[Router.scala:112:13]
wire [3:0] _input_unit_1_from_9_io_out_0_bits_flit_flow_ingress_node; // @[Router.scala:112:13]
wire [1:0] _input_unit_1_from_9_io_out_0_bits_flit_flow_ingress_node_id; // @[Router.scala:112:13]
wire [3:0] _input_unit_1_from_9_io_out_0_bits_flit_flow_egress_node; // @[Router.scala:112:13]
wire [1:0] _input_unit_1_from_9_io_out_0_bits_flit_flow_egress_node_id; // @[Router.scala:112:13]
wire _input_unit_1_from_9_io_out_0_bits_out_virt_channel; // @[Router.scala:112:13]
wire _input_unit_0_from_6_io_router_req_bits_src_virt_id; // @[Router.scala:112:13]
wire _input_unit_0_from_6_io_router_req_bits_flow_vnet_id; // @[Router.scala:112:13]
wire [3:0] _input_unit_0_from_6_io_router_req_bits_flow_ingress_node; // @[Router.scala:112:13]
wire [1:0] _input_unit_0_from_6_io_router_req_bits_flow_ingress_node_id; // @[Router.scala:112:13]
wire [3:0] _input_unit_0_from_6_io_router_req_bits_flow_egress_node; // @[Router.scala:112:13]
wire [1:0] _input_unit_0_from_6_io_router_req_bits_flow_egress_node_id; // @[Router.scala:112:13]
wire _input_unit_0_from_6_io_vcalloc_req_valid; // @[Router.scala:112:13]
wire _input_unit_0_from_6_io_vcalloc_req_bits_vc_sel_4_0; // @[Router.scala:112:13]
wire _input_unit_0_from_6_io_vcalloc_req_bits_vc_sel_3_0; // @[Router.scala:112:13]
wire _input_unit_0_from_6_io_vcalloc_req_bits_vc_sel_3_1; // @[Router.scala:112:13]
wire _input_unit_0_from_6_io_vcalloc_req_bits_vc_sel_2_0; // @[Router.scala:112:13]
wire _input_unit_0_from_6_io_vcalloc_req_bits_vc_sel_2_1; // @[Router.scala:112:13]
wire _input_unit_0_from_6_io_vcalloc_req_bits_vc_sel_1_0; // @[Router.scala:112:13]
wire _input_unit_0_from_6_io_vcalloc_req_bits_vc_sel_1_1; // @[Router.scala:112:13]
wire _input_unit_0_from_6_io_vcalloc_req_bits_vc_sel_0_0; // @[Router.scala:112:13]
wire _input_unit_0_from_6_io_vcalloc_req_bits_vc_sel_0_1; // @[Router.scala:112:13]
wire _input_unit_0_from_6_io_salloc_req_0_valid; // @[Router.scala:112:13]
wire _input_unit_0_from_6_io_salloc_req_0_bits_vc_sel_4_0; // @[Router.scala:112:13]
wire _input_unit_0_from_6_io_salloc_req_0_bits_vc_sel_3_0; // @[Router.scala:112:13]
wire _input_unit_0_from_6_io_salloc_req_0_bits_vc_sel_3_1; // @[Router.scala:112:13]
wire _input_unit_0_from_6_io_salloc_req_0_bits_vc_sel_2_0; // @[Router.scala:112:13]
wire _input_unit_0_from_6_io_salloc_req_0_bits_vc_sel_2_1; // @[Router.scala:112:13]
wire _input_unit_0_from_6_io_salloc_req_0_bits_vc_sel_1_0; // @[Router.scala:112:13]
wire _input_unit_0_from_6_io_salloc_req_0_bits_vc_sel_1_1; // @[Router.scala:112:13]
wire _input_unit_0_from_6_io_salloc_req_0_bits_vc_sel_0_0; // @[Router.scala:112:13]
wire _input_unit_0_from_6_io_salloc_req_0_bits_vc_sel_0_1; // @[Router.scala:112:13]
wire _input_unit_0_from_6_io_salloc_req_0_bits_tail; // @[Router.scala:112:13]
wire _input_unit_0_from_6_io_out_0_valid; // @[Router.scala:112:13]
wire _input_unit_0_from_6_io_out_0_bits_flit_head; // @[Router.scala:112:13]
wire _input_unit_0_from_6_io_out_0_bits_flit_tail; // @[Router.scala:112:13]
wire [36:0] _input_unit_0_from_6_io_out_0_bits_flit_payload; // @[Router.scala:112:13]
wire _input_unit_0_from_6_io_out_0_bits_flit_flow_vnet_id; // @[Router.scala:112:13]
wire [3:0] _input_unit_0_from_6_io_out_0_bits_flit_flow_ingress_node; // @[Router.scala:112:13]
wire [1:0] _input_unit_0_from_6_io_out_0_bits_flit_flow_ingress_node_id; // @[Router.scala:112:13]
wire [3:0] _input_unit_0_from_6_io_out_0_bits_flit_flow_egress_node; // @[Router.scala:112:13]
wire [1:0] _input_unit_0_from_6_io_out_0_bits_flit_flow_egress_node_id; // @[Router.scala:112:13]
wire _input_unit_0_from_6_io_out_0_bits_out_virt_channel; // @[Router.scala:112:13]
wire [2:0] fires_count = {1'h0, {1'h0, _vc_allocator_io_req_0_ready & _input_unit_0_from_6_io_vcalloc_req_valid} + {1'h0, _vc_allocator_io_req_1_ready & _input_unit_1_from_9_io_vcalloc_req_valid}} + {1'h0, {1'h0, _vc_allocator_io_req_2_ready & _input_unit_2_from_11_io_vcalloc_req_valid} + {1'h0, _vc_allocator_io_req_3_ready & _input_unit_3_from_14_io_vcalloc_req_valid} + {1'h0, _vc_allocator_io_req_4_ready & _ingress_unit_4_from_17_io_vcalloc_req_valid}}; // @[Decoupled.scala:51:35]
reg [63:0] debug_tsc; // @[Router.scala:195:28]
reg [63:0] debug_sample; // @[Router.scala:197:31]
wire _GEN = debug_sample == {44'h0, _plusarg_reader_out - 20'h1}; // @[PlusArg.scala:80:11]
reg [63:0] util_ctr; // @[Router.scala:203:29]
reg fired; // @[Router.scala:204:26]
wire _GEN_0 = (|_plusarg_reader_out) & _GEN; // @[PlusArg.scala:80:11]
wire _GEN_1 = _GEN_0 & fired; // @[Router.scala:204:26, :207:{33,71}]
reg [63:0] util_ctr_1; // @[Router.scala:203:29]
reg fired_1; // @[Router.scala:204:26]
wire _GEN_2 = _GEN_0 & fired_1; // @[Router.scala:204:26, :207:{33,71}]
reg [63:0] util_ctr_2; // @[Router.scala:203:29]
reg fired_2; // @[Router.scala:204:26]
wire _GEN_3 = _GEN_0 & fired_2; // @[Router.scala:204:26, :207:{33,71}]
reg [63:0] util_ctr_3; // @[Router.scala:203:29]
reg fired_3; // @[Router.scala:204:26]
wire _GEN_4 = _GEN_0 & fired_3; // @[Router.scala:204:26, :207:{33,71}]
reg [63:0] util_ctr_4; // @[Router.scala:203:29]
reg fired_4; // @[Router.scala:204:26]
wire _GEN_5 = _GEN_0 & fired_4; // @[Router.scala:204:26, :207:{33,71}]
reg [63:0] util_ctr_5; // @[Router.scala:203:29]
reg fired_5; // @[Router.scala:204:26]
wire _GEN_6 = _GEN_0 & fired_5; // @[Router.scala:204:26, :207:{33,71}] |
Generate the Verilog code corresponding to the following Chisel files.
File Monitor.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceLine
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import freechips.rocketchip.diplomacy.EnableMonitors
import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode}
import freechips.rocketchip.util.PlusArg
case class TLMonitorArgs(edge: TLEdge)
abstract class TLMonitorBase(args: TLMonitorArgs) extends Module
{
val io = IO(new Bundle {
val in = Input(new TLBundle(args.edge.bundle))
})
def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit
legalize(io.in, args.edge, reset)
}
object TLMonitor {
def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = {
if (enable) {
EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) }
} else { node }
}
}
class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args)
{
require (args.edge.params(TLMonitorStrictMode) || (! args.edge.params(TestplanTestType).formal))
val cover_prop_class = PropertyClass.Default
//Like assert but can flip to being an assumption for formal verification
def monAssert(cond: Bool, message: String): Unit =
if (monitorDir == MonitorDirection.Monitor) {
assert(cond, message)
} else {
Property(monitorDir, cond, message, PropertyClass.Default)
}
def assume(cond: Bool, message: String): Unit =
if (monitorDir == MonitorDirection.Monitor) {
assert(cond, message)
} else {
Property(monitorDir.flip, cond, message, PropertyClass.Default)
}
def extra = {
args.edge.sourceInfo match {
case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)"
case _ => ""
}
}
def visible(address: UInt, source: UInt, edge: TLEdge) =
edge.client.clients.map { c =>
!c.sourceId.contains(source) ||
c.visibility.map(_.contains(address)).reduce(_ || _)
}.reduce(_ && _)
def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = {
//switch this flag to turn on diplomacy in error messages
def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n"
monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra)
// Reuse these subexpressions to save some firrtl lines
val source_ok = edge.client.contains(bundle.source)
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val mask = edge.full_mask(bundle)
monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility")
//The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B
//TODO: check for acquireT?
when (bundle.opcode === TLMessages.AcquireBlock) {
monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra)
monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra)
monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra)
monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra)
}
when (bundle.opcode === TLMessages.AcquirePerm) {
monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra)
monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra)
monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra)
monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra)
monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra)
}
when (bundle.opcode === TLMessages.Get) {
monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra)
monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra)
monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra)
}
when (bundle.opcode === TLMessages.PutFullData) {
monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra)
monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.PutPartialData) {
monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra)
monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.ArithmeticData) {
monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra)
monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.LogicalData) {
monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra)
monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.Hint) {
monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra)
monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra)
}
}
def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = {
monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra)
monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility")
// Reuse these subexpressions to save some firrtl lines
val address_ok = edge.manager.containsSafe(edge.address(bundle))
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val mask = edge.full_mask(bundle)
val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source
when (bundle.opcode === TLMessages.Probe) {
assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra)
assume (address_ok, "'B' channel Probe carries unmanaged address" + extra)
assume (legal_source, "'B' channel Probe carries source that is not first source" + extra)
assume (is_aligned, "'B' channel Probe address not aligned to size" + extra)
assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra)
assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra)
assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra)
}
when (bundle.opcode === TLMessages.Get) {
monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra)
monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra)
}
when (bundle.opcode === TLMessages.PutFullData) {
monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra)
monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.PutPartialData) {
monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra)
monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.ArithmeticData) {
monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra)
monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra)
monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.LogicalData) {
monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra)
monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra)
monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.Hint) {
monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra)
monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra)
monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra)
}
}
def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = {
monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra)
val source_ok = edge.client.contains(bundle.source)
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val address_ok = edge.manager.containsSafe(edge.address(bundle))
monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility")
when (bundle.opcode === TLMessages.ProbeAck) {
monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra)
monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra)
}
when (bundle.opcode === TLMessages.ProbeAckData) {
monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra)
}
when (bundle.opcode === TLMessages.Release) {
monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra)
monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra)
monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra)
}
when (bundle.opcode === TLMessages.ReleaseData) {
monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra)
monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra)
}
when (bundle.opcode === TLMessages.AccessAck) {
monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra)
monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra)
}
when (bundle.opcode === TLMessages.AccessAckData) {
monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra)
}
when (bundle.opcode === TLMessages.HintAck) {
monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra)
monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra)
}
}
def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = {
assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra)
val source_ok = edge.client.contains(bundle.source)
val sink_ok = bundle.sink < edge.manager.endSinkId.U
val deny_put_ok = edge.manager.mayDenyPut.B
val deny_get_ok = edge.manager.mayDenyGet.B
when (bundle.opcode === TLMessages.ReleaseAck) {
assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra)
assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra)
assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra)
}
when (bundle.opcode === TLMessages.Grant) {
assume (source_ok, "'D' channel Grant carries invalid source ID" + extra)
assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra)
assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra)
assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra)
assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel Grant is denied" + extra)
}
when (bundle.opcode === TLMessages.GrantData) {
assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra)
assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra)
assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra)
assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra)
assume (!bundle.denied || bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra)
assume (deny_get_ok || !bundle.denied, "'D' channel GrantData is denied" + extra)
}
when (bundle.opcode === TLMessages.AccessAck) {
assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel AccessAck is denied" + extra)
}
when (bundle.opcode === TLMessages.AccessAckData) {
assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra)
assume (!bundle.denied || bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra)
assume (deny_get_ok || !bundle.denied, "'D' channel AccessAckData is denied" + extra)
}
when (bundle.opcode === TLMessages.HintAck) {
assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel HintAck is denied" + extra)
}
}
def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = {
val sink_ok = bundle.sink < edge.manager.endSinkId.U
monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra)
}
def legalizeFormat(bundle: TLBundle, edge: TLEdge) = {
when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) }
when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) }
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) }
when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) }
when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) }
} else {
monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra)
monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra)
monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra)
}
}
def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = {
val a_first = edge.first(a.bits, a.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (a.valid && !a_first) {
monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra)
monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra)
monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra)
monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra)
monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra)
}
when (a.fire && a_first) {
opcode := a.bits.opcode
param := a.bits.param
size := a.bits.size
source := a.bits.source
address := a.bits.address
}
}
def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = {
val b_first = edge.first(b.bits, b.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (b.valid && !b_first) {
monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra)
monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra)
monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra)
monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra)
monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra)
}
when (b.fire && b_first) {
opcode := b.bits.opcode
param := b.bits.param
size := b.bits.size
source := b.bits.source
address := b.bits.address
}
}
def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = {
// Symbolic variable
val sym_source = Wire(UInt(edge.client.endSourceId.W))
// TODO: Connect sym_source to a fixed value for simulation and to a
// free wire in formal
sym_source := 0.U
// Type casting Int to UInt
val maxSourceId = Wire(UInt(edge.client.endSourceId.W))
maxSourceId := edge.client.endSourceId.U
// Delayed verison of sym_source
val sym_source_d = Reg(UInt(edge.client.endSourceId.W))
sym_source_d := sym_source
// These will be constraints for FV setup
Property(
MonitorDirection.Monitor,
(sym_source === sym_source_d),
"sym_source should remain stable",
PropertyClass.Default)
Property(
MonitorDirection.Monitor,
(sym_source <= maxSourceId),
"sym_source should take legal value",
PropertyClass.Default)
val my_resp_pend = RegInit(false.B)
val my_opcode = Reg(UInt())
val my_size = Reg(UInt())
val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire)
val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire)
val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source)
val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source)
val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat)
val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend)
when (my_set_resp_pend) {
my_resp_pend := true.B
} .elsewhen (my_clr_resp_pend) {
my_resp_pend := false.B
}
when (my_a_first_beat) {
my_opcode := bundle.a.bits.opcode
my_size := bundle.a.bits.size
}
val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size)
val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode)
val my_resp_opcode_legal = Wire(Bool())
when ((my_resp_opcode === TLMessages.Get) || (my_resp_opcode === TLMessages.ArithmeticData) ||
(my_resp_opcode === TLMessages.LogicalData)) {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData)
} .elsewhen ((my_resp_opcode === TLMessages.PutFullData) || (my_resp_opcode === TLMessages.PutPartialData)) {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck)
} .otherwise {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck)
}
monAssert (IfThen(my_resp_pend, !my_a_first_beat),
"Request message should not be sent with a source ID, for which a response message" +
"is already pending (not received until current cycle) for a prior request message" +
"with the same source ID" + extra)
assume (IfThen(my_clr_resp_pend, (my_set_resp_pend || my_resp_pend)),
"Response message should be accepted with a source ID only if a request message with the" +
"same source ID has been accepted or is being accepted in the current cycle" + extra)
assume (IfThen(my_d_first_beat, (my_a_first_beat || my_resp_pend)),
"Response message should be sent with a source ID only if a request message with the" +
"same source ID has been accepted or is being sent in the current cycle" + extra)
assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)),
"If d_valid is 1, then d_size should be same as a_size of the corresponding request" +
"message" + extra)
assume (IfThen(my_d_first_beat, my_resp_opcode_legal),
"If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" +
"request message" + extra)
}
def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = {
val c_first = edge.first(c.bits, c.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (c.valid && !c_first) {
monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra)
monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra)
monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra)
monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra)
monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra)
}
when (c.fire && c_first) {
opcode := c.bits.opcode
param := c.bits.param
size := c.bits.size
source := c.bits.source
address := c.bits.address
}
}
def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = {
val d_first = edge.first(d.bits, d.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val sink = Reg(UInt())
val denied = Reg(Bool())
when (d.valid && !d_first) {
assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra)
assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra)
assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra)
assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra)
assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra)
assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra)
}
when (d.fire && d_first) {
opcode := d.bits.opcode
param := d.bits.param
size := d.bits.size
source := d.bits.source
sink := d.bits.sink
denied := d.bits.denied
}
}
def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = {
legalizeMultibeatA(bundle.a, edge)
legalizeMultibeatD(bundle.d, edge)
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
legalizeMultibeatB(bundle.b, edge)
legalizeMultibeatC(bundle.c, edge)
}
}
//This is left in for almond which doesn't adhere to the tilelink protocol
@deprecated("Use legalizeADSource instead if possible","")
def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = {
val inflight = RegInit(0.U(edge.client.endSourceId.W))
val a_first = edge.first(bundle.a.bits, bundle.a.fire)
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
val a_set = WireInit(0.U(edge.client.endSourceId.W))
when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) {
a_set := UIntToOH(bundle.a.bits.source)
assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra)
}
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
assume((a_set | inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra)
}
if (edge.manager.minLatency > 0) {
assume(a_set =/= d_clr || !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra)
}
inflight := (inflight | a_set) & ~d_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
assert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = {
val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset)
val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything
val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size)
val log_a_size_bus_size = log2Ceil(a_size_bus_size)
def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits
val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error
inflight.suggestName("inflight")
val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
inflight_opcodes.suggestName("inflight_opcodes")
val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
inflight_sizes.suggestName("inflight_sizes")
val a_first = edge.first(bundle.a.bits, bundle.a.fire)
a_first.suggestName("a_first")
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
d_first.suggestName("d_first")
val a_set = WireInit(0.U(edge.client.endSourceId.W))
val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
a_set.suggestName("a_set")
a_set_wo_ready.suggestName("a_set_wo_ready")
val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
a_opcodes_set.suggestName("a_opcodes_set")
val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
a_sizes_set.suggestName("a_sizes_set")
val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W))
a_opcode_lookup.suggestName("a_opcode_lookup")
a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U
val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W))
a_size_lookup.suggestName("a_size_lookup")
a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U
val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant))
val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant))
val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W))
a_opcodes_set_interm.suggestName("a_opcodes_set_interm")
val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W))
a_sizes_set_interm.suggestName("a_sizes_set_interm")
when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) {
a_set_wo_ready := UIntToOH(bundle.a.bits.source)
}
when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) {
a_set := UIntToOH(bundle.a.bits.source)
a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) | 1.U
a_sizes_set_interm := (bundle.a.bits.size << 1.U) | 1.U
a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U)
a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U)
monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra)
}
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
d_clr.suggestName("d_clr")
d_clr_wo_ready.suggestName("d_clr_wo_ready")
val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
d_opcodes_clr.suggestName("d_opcodes_clr")
val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
d_sizes_clr.suggestName("d_sizes_clr")
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr_wo_ready := UIntToOH(bundle.d.bits.source)
}
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U)
d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U)
}
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source)
assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra)
when (same_cycle_resp) {
assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) ||
(bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra)
assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra)
} .otherwise {
assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) ||
(bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra)
assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra)
}
}
when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) {
assume((!bundle.d.ready) || bundle.a.ready, "ready check")
}
if (edge.manager.minLatency > 0) {
assume(a_set_wo_ready =/= d_clr_wo_ready || !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra)
}
inflight := (inflight | a_set) & ~d_clr
inflight_opcodes := (inflight_opcodes | a_opcodes_set) & ~d_opcodes_clr
inflight_sizes := (inflight_sizes | a_sizes_set) & ~d_sizes_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = {
val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset)
val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything
val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size)
val log_c_size_bus_size = log2Ceil(c_size_bus_size)
def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits
val inflight = RegInit(0.U((2 max edge.client.endSourceId).W))
val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
inflight.suggestName("inflight")
inflight_opcodes.suggestName("inflight_opcodes")
inflight_sizes.suggestName("inflight_sizes")
val c_first = edge.first(bundle.c.bits, bundle.c.fire)
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
c_first.suggestName("c_first")
d_first.suggestName("d_first")
val c_set = WireInit(0.U(edge.client.endSourceId.W))
val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
c_set.suggestName("c_set")
c_set_wo_ready.suggestName("c_set_wo_ready")
c_opcodes_set.suggestName("c_opcodes_set")
c_sizes_set.suggestName("c_sizes_set")
val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W))
val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W))
c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U
c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U
c_opcode_lookup.suggestName("c_opcode_lookup")
c_size_lookup.suggestName("c_size_lookup")
val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W))
val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W))
c_opcodes_set_interm.suggestName("c_opcodes_set_interm")
c_sizes_set_interm.suggestName("c_sizes_set_interm")
when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) {
c_set_wo_ready := UIntToOH(bundle.c.bits.source)
}
when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) {
c_set := UIntToOH(bundle.c.bits.source)
c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) | 1.U
c_sizes_set_interm := (bundle.c.bits.size << 1.U) | 1.U
c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U)
c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U)
monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra)
}
val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck || bundle.c.bits.opcode === TLMessages.ProbeAckData
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
d_clr.suggestName("d_clr")
d_clr_wo_ready.suggestName("d_clr_wo_ready")
d_opcodes_clr.suggestName("d_opcodes_clr")
d_sizes_clr.suggestName("d_sizes_clr")
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
d_clr_wo_ready := UIntToOH(bundle.d.bits.source)
}
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U)
d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U)
}
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source)
assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra)
when (same_cycle_resp) {
assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra)
} .otherwise {
assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra)
}
}
when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) {
assume((!bundle.d.ready) || bundle.c.ready, "ready check")
}
if (edge.manager.minLatency > 0) {
when (c_set_wo_ready.orR) {
assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra)
}
}
inflight := (inflight | c_set) & ~d_clr
inflight_opcodes := (inflight_opcodes | c_opcodes_set) & ~d_opcodes_clr
inflight_sizes := (inflight_sizes | c_sizes_set) & ~d_sizes_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.c.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = {
val inflight = RegInit(0.U(edge.manager.endSinkId.W))
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
val e_first = true.B
val d_set = WireInit(0.U(edge.manager.endSinkId.W))
when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) {
d_set := UIntToOH(bundle.d.bits.sink)
assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra)
}
val e_clr = WireInit(0.U(edge.manager.endSinkId.W))
when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) {
e_clr := UIntToOH(bundle.e.bits.sink)
monAssert((d_set | inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra)
}
// edge.client.minLatency applies to BC, not DE
inflight := (inflight | d_set) & ~e_clr
}
def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = {
val sourceBits = log2Ceil(edge.client.endSourceId)
val tooBig = 14 // >16kB worth of flight information gets to be too much
if (sourceBits > tooBig) {
println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked")
} else {
if (args.edge.params(TestplanTestType).simulation) {
if (args.edge.params(TLMonitorStrictMode)) {
legalizeADSource(bundle, edge)
legalizeCDSource(bundle, edge)
} else {
legalizeADSourceOld(bundle, edge)
}
}
if (args.edge.params(TestplanTestType).formal) {
legalizeADSourceFormal(bundle, edge)
}
}
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
// legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize...
val sinkBits = log2Ceil(edge.manager.endSinkId)
if (sinkBits > tooBig) {
println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked")
} else {
legalizeDESink(bundle, edge)
}
}
}
def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = {
legalizeFormat (bundle, edge)
legalizeMultibeat (bundle, edge)
legalizeUnique (bundle, edge)
}
}
File Misc.scala:
// See LICENSE.Berkeley for license details.
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util._
import chisel3.util.random.LFSR
import org.chipsalliance.cde.config.Parameters
import scala.math._
class ParameterizedBundle(implicit p: Parameters) extends Bundle
trait Clocked extends Bundle {
val clock = Clock()
val reset = Bool()
}
object DecoupledHelper {
def apply(rvs: Bool*) = new DecoupledHelper(rvs)
}
class DecoupledHelper(val rvs: Seq[Bool]) {
def fire(exclude: Bool, includes: Bool*) = {
require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!")
(rvs.filter(_ ne exclude) ++ includes).reduce(_ && _)
}
def fire() = {
rvs.reduce(_ && _)
}
}
object MuxT {
def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2))
def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3))
def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4))
}
/** Creates a cascade of n MuxTs to search for a key value. */
object MuxTLookup {
def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = {
var res = default
for ((k, v) <- mapping.reverse)
res = MuxT(k === key, v, res)
res
}
def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = {
var res = default
for ((k, v) <- mapping.reverse)
res = MuxT(k === key, v, res)
res
}
}
object ValidMux {
def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = {
apply(v1 +: v2.toSeq)
}
def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = {
val out = Wire(Valid(valids.head.bits.cloneType))
out.valid := valids.map(_.valid).reduce(_ || _)
out.bits := MuxCase(valids.head.bits,
valids.map(v => (v.valid -> v.bits)))
out
}
}
object Str
{
def apply(s: String): UInt = {
var i = BigInt(0)
require(s.forall(validChar _))
for (c <- s)
i = (i << 8) | c
i.U((s.length*8).W)
}
def apply(x: Char): UInt = {
require(validChar(x))
x.U(8.W)
}
def apply(x: UInt): UInt = apply(x, 10)
def apply(x: UInt, radix: Int): UInt = {
val rad = radix.U
val w = x.getWidth
require(w > 0)
var q = x
var s = digit(q % rad)
for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {
q = q / rad
s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s)
}
s
}
def apply(x: SInt): UInt = apply(x, 10)
def apply(x: SInt, radix: Int): UInt = {
val neg = x < 0.S
val abs = x.abs.asUInt
if (radix != 10) {
Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix))
} else {
val rad = radix.U
val w = abs.getWidth
require(w > 0)
var q = abs
var s = digit(q % rad)
var needSign = neg
for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {
q = q / rad
val placeSpace = q === 0.U
val space = Mux(needSign, Str('-'), Str(' '))
needSign = needSign && !placeSpace
s = Cat(Mux(placeSpace, space, digit(q % rad)), s)
}
Cat(Mux(needSign, Str('-'), Str(' ')), s)
}
}
private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0)
private def validChar(x: Char) = x == (x & 0xFF)
}
object Split
{
def apply(x: UInt, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n0), x.extract(n0-1,0))
}
def apply(x: UInt, n1: Int, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))
}
def apply(x: UInt, n2: Int, n1: Int, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))
}
}
object Random
{
def apply(mod: Int, random: UInt): UInt = {
if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0)
else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod))
}
def apply(mod: Int): UInt = apply(mod, randomizer)
def oneHot(mod: Int, random: UInt): UInt = {
if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0))
else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt
}
def oneHot(mod: Int): UInt = oneHot(mod, randomizer)
private def randomizer = LFSR(16)
private def partition(value: UInt, slices: Int) =
Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U)
}
object Majority {
def apply(in: Set[Bool]): Bool = {
val n = (in.size >> 1) + 1
val clauses = in.subsets(n).map(_.reduce(_ && _))
clauses.reduce(_ || _)
}
def apply(in: Seq[Bool]): Bool = apply(in.toSet)
def apply(in: UInt): Bool = apply(in.asBools.toSet)
}
object PopCountAtLeast {
private def two(x: UInt): (Bool, Bool) = x.getWidth match {
case 1 => (x.asBool, false.B)
case n =>
val half = x.getWidth / 2
val (leftOne, leftTwo) = two(x(half - 1, 0))
val (rightOne, rightTwo) = two(x(x.getWidth - 1, half))
(leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne))
}
def apply(x: UInt, n: Int): Bool = n match {
case 0 => true.B
case 1 => x.orR
case 2 => two(x)._2
case 3 => PopCount(x) >= n.U
}
}
// This gets used everywhere, so make the smallest circuit possible ...
// Given an address and size, create a mask of beatBytes size
// eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111
// groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01
object MaskGen {
def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = {
require (groupBy >= 1 && beatBytes >= groupBy)
require (isPow2(beatBytes) && isPow2(groupBy))
val lgBytes = log2Ceil(beatBytes)
val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U
def helper(i: Int): Seq[(Bool, Bool)] = {
if (i == 0) {
Seq((lgSize >= lgBytes.asUInt, true.B))
} else {
val sub = helper(i-1)
val size = sizeOH(lgBytes - i)
val bit = addr_lo(lgBytes - i)
val nbit = !bit
Seq.tabulate (1 << i) { j =>
val (sub_acc, sub_eq) = sub(j/2)
val eq = sub_eq && (if (j % 2 == 1) bit else nbit)
val acc = sub_acc || (size && eq)
(acc, eq)
}
}
}
if (groupBy == beatBytes) 1.U else
Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse)
}
}
File PlusArg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.experimental._
import chisel3.util.HasBlackBoxResource
@deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05")
case class PlusArgInfo(default: BigInt, docstring: String)
/** Case class for PlusArg information
*
* @tparam A scala type of the PlusArg value
* @param default optional default value
* @param docstring text to include in the help
* @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT)
*/
private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String)
/** Typeclass for converting a type to a doctype string
* @tparam A some type
*/
trait Doctypeable[A] {
/** Return the doctype string for some option */
def toDoctype(a: Option[A]): String
}
/** Object containing implementations of the Doctypeable typeclass */
object Doctypes {
/** Converts an Int => "INT" */
implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" }
/** Converts a BigInt => "INT" */
implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" }
/** Converts a String => "STRING" */
implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" }
}
class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map(
"FORMAT" -> StringParam(format),
"DEFAULT" -> IntParam(default),
"WIDTH" -> IntParam(width)
)) with HasBlackBoxResource {
val io = IO(new Bundle {
val out = Output(UInt(width.W))
})
addResource("/vsrc/plusarg_reader.v")
}
/* This wrapper class has no outputs, making it clear it is a simulation-only construct */
class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module {
val io = IO(new Bundle {
val count = Input(UInt(width.W))
})
val max = Module(new plusarg_reader(format, default, docstring, width)).io.out
when (max > 0.U) {
assert (io.count < max, s"Timeout exceeded: $docstring")
}
}
import Doctypes._
object PlusArg
{
/** PlusArg("foo") will return 42.U if the simulation is run with +foo=42
* Do not use this as an initial register value. The value is set in an
* initial block and thus accessing it from another initial is racey.
* Add a docstring to document the arg, which can be dumped in an elaboration
* pass.
*/
def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = {
PlusArgArtefacts.append(name, Some(default), docstring)
Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out
}
/** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert
* to kill the simulation when count exceeds the specified integer argument.
* Default 0 will never assert.
*/
def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = {
PlusArgArtefacts.append(name, Some(default), docstring)
Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count
}
}
object PlusArgArtefacts {
private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty
/* Add a new PlusArg */
@deprecated(
"Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08",
"Rocket Chip 2020.05"
)
def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring)
/** Add a new PlusArg
*
* @tparam A scala type of the PlusArg value
* @param name name for the PlusArg
* @param default optional default value
* @param docstring text to include in the help
*/
def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit =
artefacts = artefacts ++
Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default)))
/* From plus args, generate help text */
private def serializeHelp_cHeader(tab: String = ""): String = artefacts
.map{ case(arg, info) =>
s"""|$tab+$arg=${info.doctype}\\n\\
|$tab${" "*20}${info.docstring}\\n\\
|""".stripMargin ++ info.default.map{ case default =>
s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("")
}.toSeq.mkString("\\n\\\n") ++ "\""
/* From plus args, generate a char array of their names */
private def serializeArray_cHeader(tab: String = ""): String = {
val prettyTab = tab + " " * 44 // Length of 'static const ...'
s"${tab}static const char * verilog_plusargs [] = {\\\n" ++
artefacts
.map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" }
.mkString("")++
s"${prettyTab}0};"
}
/* Generate C code to be included in emulator.cc that helps with
* argument parsing based on available Verilog PlusArgs */
def serialize_cHeader(): String =
s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\
|${serializeHelp_cHeader(" "*7)}
|${serializeArray_cHeader()}
|""".stripMargin
}
File package.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip
import chisel3._
import chisel3.util._
import scala.math.min
import scala.collection.{immutable, mutable}
package object util {
implicit class UnzippableOption[S, T](val x: Option[(S, T)]) {
def unzip = (x.map(_._1), x.map(_._2))
}
implicit class UIntIsOneOf(private val x: UInt) extends AnyVal {
def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR
def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq)
}
implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal {
/** Like Vec.apply(idx), but tolerates indices of mismatched width */
def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0))
}
implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal {
def apply(idx: UInt): T = {
if (x.size <= 1) {
x.head
} else if (!isPow2(x.size)) {
// For non-power-of-2 seqs, reflect elements to simplify decoder
(x ++ x.takeRight(x.size & -x.size)).toSeq(idx)
} else {
// Ignore MSBs of idx
val truncIdx =
if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx
else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0)
x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) }
}
}
def extract(idx: UInt): T = VecInit(x).extract(idx)
def asUInt: UInt = Cat(x.map(_.asUInt).reverse)
def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n)
def rotate(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n)
def rotateRight(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
}
// allow bitwise ops on Seq[Bool] just like UInt
implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal {
def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b }
def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b }
def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b }
def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x
def >> (n: Int): Seq[Bool] = x drop n
def unary_~ : Seq[Bool] = x.map(!_)
def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_)
def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_)
def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_)
private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B)
}
implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal {
def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable))
def getElements: Seq[Element] = x match {
case e: Element => Seq(e)
case a: Aggregate => a.getElements.flatMap(_.getElements)
}
}
/** Any Data subtype that has a Bool member named valid. */
type DataCanBeValid = Data { val valid: Bool }
implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal {
def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable)
}
implicit class StringToAugmentedString(private val x: String) extends AnyVal {
/** converts from camel case to to underscores, also removing all spaces */
def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") {
case (acc, c) if c.isUpper => acc + "_" + c.toLower
case (acc, c) if c == ' ' => acc
case (acc, c) => acc + c
}
/** converts spaces or underscores to hyphens, also lowering case */
def kebab: String = x.toLowerCase map {
case ' ' => '-'
case '_' => '-'
case c => c
}
def named(name: Option[String]): String = {
x + name.map("_named_" + _ ).getOrElse("_with_no_name")
}
def named(name: String): String = named(Some(name))
}
implicit def uintToBitPat(x: UInt): BitPat = BitPat(x)
implicit def wcToUInt(c: WideCounter): UInt = c.value
implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal {
def sextTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x)
}
def padTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(0.U((n - x.getWidth).W), x)
}
// shifts left by n if n >= 0, or right by -n if n < 0
def << (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << n(w-1, 0)
Mux(n(w), shifted >> (1 << w), shifted)
}
// shifts right by n if n >= 0, or left by -n if n < 0
def >> (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << (1 << w) >> n(w-1, 0)
Mux(n(w), shifted, shifted >> (1 << w))
}
// Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts
def extract(hi: Int, lo: Int): UInt = {
require(hi >= lo-1)
if (hi == lo-1) 0.U
else x(hi, lo)
}
// Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts
def extractOption(hi: Int, lo: Int): Option[UInt] = {
require(hi >= lo-1)
if (hi == lo-1) None
else Some(x(hi, lo))
}
// like x & ~y, but first truncate or zero-extend y to x's width
def andNot(y: UInt): UInt = x & ~(y | (x & 0.U))
def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n)
def rotateRight(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r))
}
}
def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n))
def rotateLeft(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r))
}
}
// compute (this + y) % n, given (this < n) and (y < n)
def addWrap(y: UInt, n: Int): UInt = {
val z = x +& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0)
}
// compute (this - y) % n, given (this < n) and (y < n)
def subWrap(y: UInt, n: Int): UInt = {
val z = x -& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0)
}
def grouped(width: Int): Seq[UInt] =
(0 until x.getWidth by width).map(base => x(base + width - 1, base))
def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds
def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x)
// Like >=, but prevents x-prop for ('x >= 0)
def >== (y: UInt): Bool = x >= y || y === 0.U
}
implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal {
def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y)
def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y)
}
implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal {
def toInt: Int = if (x) 1 else 0
// this one's snagged from scalaz
def option[T](z: => T): Option[T] = if (x) Some(z) else None
}
implicit class IntToAugmentedInt(private val x: Int) extends AnyVal {
// exact log2
def log2: Int = {
require(isPow2(x))
log2Ceil(x)
}
}
def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x)
def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x))
def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0)
def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1)
def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None
// Fill 1s from low bits to high bits
def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth)
def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0))
helper(1, x)(width-1, 0)
}
// Fill 1s form high bits to low bits
def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth)
def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x >> s))
helper(1, x)(width-1, 0)
}
def OptimizationBarrier[T <: Data](in: T): T = {
val barrier = Module(new Module {
val io = IO(new Bundle {
val x = Input(chiselTypeOf(in))
val y = Output(chiselTypeOf(in))
})
io.y := io.x
override def desiredName = s"OptimizationBarrier_${in.typeName}"
})
barrier.io.x := in
barrier.io.y
}
/** Similar to Seq.groupBy except this returns a Seq instead of a Map
* Useful for deterministic code generation
*/
def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = {
val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]]
for (x <- xs) {
val key = f(x)
val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A])
l += x
}
map.view.map({ case (k, vs) => k -> vs.toList }).toList
}
def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match {
case 1 => List.fill(n)(in.head)
case x if x == n => in
case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in")
}
// HeterogeneousBag moved to standalond diplomacy
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts)
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag
}
File Parameters.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.diplomacy
import chisel3._
import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor}
import freechips.rocketchip.util.ShiftQueue
/** Options for describing the attributes of memory regions */
object RegionType {
// Define the 'more relaxed than' ordering
val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS)
sealed trait T extends Ordered[T] {
def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this)
}
case object CACHED extends T // an intermediate agent may have cached a copy of the region for you
case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided
case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible
case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached
case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects
case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed
case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively
}
// A non-empty half-open range; [start, end)
case class IdRange(start: Int, end: Int) extends Ordered[IdRange]
{
require (start >= 0, s"Ids cannot be negative, but got: $start.")
require (start <= end, "Id ranges cannot be negative.")
def compare(x: IdRange) = {
val primary = (this.start - x.start).signum
val secondary = (x.end - this.end).signum
if (primary != 0) primary else secondary
}
def overlaps(x: IdRange) = start < x.end && x.start < end
def contains(x: IdRange) = start <= x.start && x.end <= end
def contains(x: Int) = start <= x && x < end
def contains(x: UInt) =
if (size == 0) {
false.B
} else if (size == 1) { // simple comparison
x === start.U
} else {
// find index of largest different bit
val largestDeltaBit = log2Floor(start ^ (end-1))
val smallestCommonBit = largestDeltaBit + 1 // may not exist in x
val uncommonMask = (1 << smallestCommonBit) - 1
val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0)
// the prefix must match exactly (note: may shift ALL bits away)
(x >> smallestCommonBit) === (start >> smallestCommonBit).U &&
// firrtl constant prop range analysis can eliminate these two:
(start & uncommonMask).U <= uncommonBits &&
uncommonBits <= ((end-1) & uncommonMask).U
}
def shift(x: Int) = IdRange(start+x, end+x)
def size = end - start
def isEmpty = end == start
def range = start until end
}
object IdRange
{
def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else {
val ranges = s.sorted
(ranges.tail zip ranges.init) find { case (a, b) => a overlaps b }
}
}
// An potentially empty inclusive range of 2-powers [min, max] (in bytes)
case class TransferSizes(min: Int, max: Int)
{
def this(x: Int) = this(x, x)
require (min <= max, s"Min transfer $min > max transfer $max")
require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)")
require (max == 0 || isPow2(max), s"TransferSizes must be a power of 2, got: $max")
require (min == 0 || isPow2(min), s"TransferSizes must be a power of 2, got: $min")
require (max == 0 || min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)")
def none = min == 0
def contains(x: Int) = isPow2(x) && min <= x && x <= max
def containsLg(x: Int) = contains(1 << x)
def containsLg(x: UInt) =
if (none) false.B
else if (min == max) { log2Ceil(min).U === x }
else { log2Ceil(min).U <= x && x <= log2Ceil(max).U }
def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max)
def intersect(x: TransferSizes) =
if (x.max < min || max < x.min) TransferSizes.none
else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max))
// Not a union, because the result may contain sizes contained by neither term
// NOT TO BE CONFUSED WITH COVERPOINTS
def mincover(x: TransferSizes) = {
if (none) {
x
} else if (x.none) {
this
} else {
TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max))
}
}
override def toString() = "TransferSizes[%d, %d]".format(min, max)
}
object TransferSizes {
def apply(x: Int) = new TransferSizes(x)
val none = new TransferSizes(0)
def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _)
def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _)
implicit def asBool(x: TransferSizes) = !x.none
}
// AddressSets specify the address space managed by the manager
// Base is the base address, and mask are the bits consumed by the manager
// e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff
// e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ...
case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet]
{
// Forbid misaligned base address (and empty sets)
require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}")
require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous
// We do allow negative mask (=> ignore all high bits)
def contains(x: BigInt) = ((x ^ base) & ~mask) == 0
def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S
// turn x into an address contained in this set
def legalize(x: UInt): UInt = base.U | (mask.U & x)
// overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1)
def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0
// contains iff bitwise: x.mask => mask && contains(x.base)
def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0
// The number of bytes to which the manager must be aligned
def alignment = ((mask + 1) & ~mask)
// Is this a contiguous memory range
def contiguous = alignment == mask+1
def finite = mask >= 0
def max = { require (finite, "Max cannot be calculated on infinite mask"); base | mask }
// Widen the match function to ignore all bits in imask
def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask)
// Return an AddressSet that only contains the addresses both sets contain
def intersect(x: AddressSet): Option[AddressSet] = {
if (!overlaps(x)) {
None
} else {
val r_mask = mask & x.mask
val r_base = base | x.base
Some(AddressSet(r_base, r_mask))
}
}
def subtract(x: AddressSet): Seq[AddressSet] = {
intersect(x) match {
case None => Seq(this)
case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit =>
val nmask = (mask & (bit-1)) | remove.mask
val nbase = (remove.base ^ bit) & ~nmask
AddressSet(nbase, nmask)
}
}
}
// AddressSets have one natural Ordering (the containment order, if contiguous)
def compare(x: AddressSet) = {
val primary = (this.base - x.base).signum // smallest address first
val secondary = (x.mask - this.mask).signum // largest mask first
if (primary != 0) primary else secondary
}
// We always want to see things in hex
override def toString() = {
if (mask >= 0) {
"AddressSet(0x%x, 0x%x)".format(base, mask)
} else {
"AddressSet(0x%x, ~0x%x)".format(base, ~mask)
}
}
def toRanges = {
require (finite, "Ranges cannot be calculated on infinite mask")
val size = alignment
val fragments = mask & ~(size-1)
val bits = bitIndexes(fragments)
(BigInt(0) until (BigInt(1) << bits.size)).map { i =>
val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) }
AddressRange(off, size)
}
}
}
object AddressSet
{
val everything = AddressSet(0, -1)
def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = {
if (size == 0) tail.reverse else {
val maxBaseAlignment = base & (-base) // 0 for infinite (LSB)
val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size
val step =
if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment)
maxSizeAlignment else maxBaseAlignment
misaligned(base+step, size-step, AddressSet(base, step-1) +: tail)
}
}
def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = {
// Pair terms up by ignoring 'bit'
seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) =>
if (seq.size == 1) {
seq.head // singleton -> unaffected
} else {
key.copy(mask = key.mask | bit) // pair - widen mask by bit
}
}.toList
}
def unify(seq: Seq[AddressSet]): Seq[AddressSet] = {
val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _)
AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted
}
def enumerateMask(mask: BigInt): Seq[BigInt] = {
def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] =
if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail)
helper(0, Nil)
}
def enumerateBits(mask: BigInt): Seq[BigInt] = {
def helper(x: BigInt): Seq[BigInt] = {
if (x == 0) {
Nil
} else {
val bit = x & (-x)
bit +: helper(x & ~bit)
}
}
helper(mask)
}
}
case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean)
{
require (depth >= 0, "Buffer depth must be >= 0")
def isDefined = depth > 0
def latency = if (isDefined && !flow) 1 else 0
def apply[T <: Data](x: DecoupledIO[T]) =
if (isDefined) Queue(x, depth, flow=flow, pipe=pipe)
else x
def irrevocable[T <: Data](x: ReadyValidIO[T]) =
if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe)
else x
def sq[T <: Data](x: DecoupledIO[T]) =
if (!isDefined) x else {
val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe))
sq.io.enq <> x
sq.io.deq
}
override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "")
}
object BufferParams
{
implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false)
val default = BufferParams(2)
val none = BufferParams(0)
val flow = BufferParams(1, true, false)
val pipe = BufferParams(1, false, true)
}
case class TriStateValue(value: Boolean, set: Boolean)
{
def update(orig: Boolean) = if (set) value else orig
}
object TriStateValue
{
implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true)
def unset = TriStateValue(false, false)
}
trait DirectedBuffers[T] {
def copyIn(x: BufferParams): T
def copyOut(x: BufferParams): T
def copyInOut(x: BufferParams): T
}
trait IdMapEntry {
def name: String
def from: IdRange
def to: IdRange
def isCache: Boolean
def requestFifo: Boolean
def maxTransactionsInFlight: Option[Int]
def pretty(fmt: String) =
if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5
fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "")
} else {
fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "")
}
}
abstract class IdMap[T <: IdMapEntry] {
protected val fmt: String
val mapping: Seq[T]
def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n")
}
File Edges.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.util._
class TLEdge(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdgeParameters(client, manager, params, sourceInfo)
{
def isAligned(address: UInt, lgSize: UInt): Bool = {
if (maxLgSize == 0) true.B else {
val mask = UIntToOH1(lgSize, maxLgSize)
(address & mask) === 0.U
}
}
def mask(address: UInt, lgSize: UInt): UInt =
MaskGen(address, lgSize, manager.beatBytes)
def staticHasData(bundle: TLChannel): Option[Boolean] = {
bundle match {
case _:TLBundleA => {
// Do there exist A messages with Data?
val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial
// Do there exist A messages without Data?
val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint
// Statically optimize the case where hasData is a constant
if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None
}
case _:TLBundleB => {
// Do there exist B messages with Data?
val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial
// Do there exist B messages without Data?
val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint
// Statically optimize the case where hasData is a constant
if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None
}
case _:TLBundleC => {
// Do there eixst C messages with Data?
val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe
// Do there exist C messages without Data?
val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe
if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None
}
case _:TLBundleD => {
// Do there eixst D messages with Data?
val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB
// Do there exist D messages without Data?
val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT
if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None
}
case _:TLBundleE => Some(false)
}
}
def isRequest(x: TLChannel): Bool = {
x match {
case a: TLBundleA => true.B
case b: TLBundleB => true.B
case c: TLBundleC => c.opcode(2) && c.opcode(1)
// opcode === TLMessages.Release ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(2) && !d.opcode(1)
// opcode === TLMessages.Grant ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
}
def isResponse(x: TLChannel): Bool = {
x match {
case a: TLBundleA => false.B
case b: TLBundleB => false.B
case c: TLBundleC => !c.opcode(2) || !c.opcode(1)
// opcode =/= TLMessages.Release &&
// opcode =/= TLMessages.ReleaseData
case d: TLBundleD => true.B // Grant isResponse + isRequest
case e: TLBundleE => true.B
}
}
def hasData(x: TLChannel): Bool = {
val opdata = x match {
case a: TLBundleA => !a.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case b: TLBundleB => !b.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case c: TLBundleC => c.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.ProbeAckData ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
staticHasData(x).map(_.B).getOrElse(opdata)
}
def opcode(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.opcode
case b: TLBundleB => b.opcode
case c: TLBundleC => c.opcode
case d: TLBundleD => d.opcode
}
}
def param(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.param
case b: TLBundleB => b.param
case c: TLBundleC => c.param
case d: TLBundleD => d.param
}
}
def size(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.size
case b: TLBundleB => b.size
case c: TLBundleC => c.size
case d: TLBundleD => d.size
}
}
def data(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.data
case b: TLBundleB => b.data
case c: TLBundleC => c.data
case d: TLBundleD => d.data
}
}
def corrupt(x: TLDataChannel): Bool = {
x match {
case a: TLBundleA => a.corrupt
case b: TLBundleB => b.corrupt
case c: TLBundleC => c.corrupt
case d: TLBundleD => d.corrupt
}
}
def mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.mask
case b: TLBundleB => b.mask
case c: TLBundleC => mask(c.address, c.size)
}
}
def full_mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => mask(a.address, a.size)
case b: TLBundleB => mask(b.address, b.size)
case c: TLBundleC => mask(c.address, c.size)
}
}
def address(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.address
case b: TLBundleB => b.address
case c: TLBundleC => c.address
}
}
def source(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.source
case b: TLBundleB => b.source
case c: TLBundleC => c.source
case d: TLBundleD => d.source
}
}
def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes)
def addr_lo(x: UInt): UInt =
if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0)
def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x))
def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x))
def numBeats(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 1.U
case bundle: TLDataChannel => {
val hasData = this.hasData(bundle)
val size = this.size(bundle)
val cutoff = log2Ceil(manager.beatBytes)
val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U
val decode = UIntToOH(size, maxLgSize+1) >> cutoff
Mux(hasData, decode | small.asUInt, 1.U)
}
}
}
def numBeats1(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 0.U
case bundle: TLDataChannel => {
if (maxLgSize == 0) {
0.U
} else {
val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes)
Mux(hasData(bundle), decode, 0.U)
}
}
}
}
def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val beats1 = numBeats1(bits)
val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W))
val counter1 = counter - 1.U
val first = counter === 0.U
val last = counter === 1.U || beats1 === 0.U
val done = last && fire
val count = (beats1 & ~counter1)
when (fire) {
counter := Mux(first, beats1, counter1)
}
(first, last, done, count)
}
def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1
def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire)
def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid)
def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2
def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire)
def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid)
def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3
def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire)
def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid)
def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3)
}
def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire)
def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid)
def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4)
}
def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire)
def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid)
def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes))
}
def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire)
def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid)
// Does the request need T permissions to be executed?
def needT(a: TLBundleA): Bool = {
val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLPermissions.NtoB -> false.B,
TLPermissions.NtoT -> true.B,
TLPermissions.BtoT -> true.B))
MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array(
TLMessages.PutFullData -> true.B,
TLMessages.PutPartialData -> true.B,
TLMessages.ArithmeticData -> true.B,
TLMessages.LogicalData -> true.B,
TLMessages.Get -> false.B,
TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLHints.PREFETCH_READ -> false.B,
TLHints.PREFETCH_WRITE -> true.B)),
TLMessages.AcquireBlock -> acq_needT,
TLMessages.AcquirePerm -> acq_needT))
}
// This is a very expensive circuit; use only if you really mean it!
def inFlight(x: TLBundle): (UInt, UInt) = {
val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W))
val bce = manager.anySupportAcquireB && client.anySupportProbe
val (a_first, a_last, _) = firstlast(x.a)
val (b_first, b_last, _) = firstlast(x.b)
val (c_first, c_last, _) = firstlast(x.c)
val (d_first, d_last, _) = firstlast(x.d)
val (e_first, e_last, _) = firstlast(x.e)
val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits))
val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits))
val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits))
val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits))
val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits))
val a_inc = x.a.fire && a_first && a_request
val b_inc = x.b.fire && b_first && b_request
val c_inc = x.c.fire && c_first && c_request
val d_inc = x.d.fire && d_first && d_request
val e_inc = x.e.fire && e_first && e_request
val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil))
val a_dec = x.a.fire && a_last && a_response
val b_dec = x.b.fire && b_last && b_response
val c_dec = x.c.fire && c_last && c_response
val d_dec = x.d.fire && d_last && d_response
val e_dec = x.e.fire && e_last && e_response
val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil))
val next_flight = flight + PopCount(inc) - PopCount(dec)
flight := next_flight
(flight, next_flight)
}
def prettySourceMapping(context: String): String = {
s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n"
}
}
class TLEdgeOut(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
// Transfers
def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquireBlock
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquirePerm
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.Release
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ReleaseData
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) =
Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B)
def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAck
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions, data)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAckData
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B)
def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink)
def GrantAck(toSink: UInt): TLBundleE = {
val e = Wire(new TLBundleE(bundle))
e.sink := toSink
e
}
// Accesses
def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsGetFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Get
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutFullFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutFullData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, mask, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutPartialFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutPartialData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = {
require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsArithmeticFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.ArithmeticData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsLogicalFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.LogicalData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = {
require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsHintFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Hint
a.param := param
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data)
def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAckData
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size)
def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.HintAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
}
class TLEdgeIn(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = {
val todo = x.filter(!_.isEmpty)
val heads = todo.map(_.head)
val tails = todo.map(_.tail)
if (todo.isEmpty) Nil else { heads +: myTranspose(tails) }
}
// Transfers
def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = {
require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}")
val legal = client.supportsProbe(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Probe
b.param := capPermissions
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.Grant
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.GrantData
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B)
def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.ReleaseAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
// Accesses
def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = {
require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsGet(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Get
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsPutFull(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutFullData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, mask, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsPutPartial(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutPartialData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsArithmetic(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.ArithmeticData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsLogical(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.LogicalData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = {
require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsHint(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Hint
b.param := param
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size)
def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied)
def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data)
def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAckData
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B)
def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied)
def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B)
def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.HintAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
}
| module TLMonitor_17( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_source, // @[Monitor.scala:20:14]
input [28:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input io_in_a_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input [7:0] io_in_d_bits_source, // @[Monitor.scala:20:14]
input io_in_d_bits_sink, // @[Monitor.scala:20:14]
input io_in_d_bits_denied, // @[Monitor.scala:20:14]
input io_in_d_bits_corrupt // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire [12:0] _GEN = {10'h0, io_in_a_bits_size}; // @[package.scala:243:71]
wire _a_first_T_1 = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35]
reg [2:0] a_first_counter; // @[Edges.scala:229:27]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [2:0] param; // @[Monitor.scala:388:22]
reg [2:0] size; // @[Monitor.scala:389:22]
reg [7:0] source; // @[Monitor.scala:390:22]
reg [28:0] address; // @[Monitor.scala:391:22]
reg [2:0] d_first_counter; // @[Edges.scala:229:27]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [1:0] param_1; // @[Monitor.scala:539:22]
reg [2:0] size_1; // @[Monitor.scala:540:22]
reg [7:0] source_1; // @[Monitor.scala:541:22]
reg sink; // @[Monitor.scala:542:22]
reg denied; // @[Monitor.scala:543:22]
reg [128:0] inflight; // @[Monitor.scala:614:27]
reg [515:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [515:0] inflight_sizes; // @[Monitor.scala:618:33]
reg [2:0] a_first_counter_1; // @[Edges.scala:229:27]
wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25]
reg [2:0] d_first_counter_1; // @[Edges.scala:229:27]
wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire [255:0] _GEN_0 = {248'h0, io_in_a_bits_source}; // @[OneHot.scala:58:35]
wire _GEN_1 = _a_first_T_1 & a_first_1; // @[Decoupled.scala:51:35]
wire d_release_ack = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala:673:46]
wire _GEN_2 = io_in_d_bits_opcode != 3'h6; // @[Monitor.scala:673:46, :674:74]
wire [255:0] _GEN_3 = {248'h0, io_in_d_bits_source}; // @[OneHot.scala:58:35]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
reg [128:0] inflight_1; // @[Monitor.scala:726:35]
reg [515:0] inflight_sizes_1; // @[Monitor.scala:728:35]
reg [2:0] d_first_counter_2; // @[Edges.scala:229:27]
wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27] |
Generate the Verilog code corresponding to the following Chisel files.
File ShiftReg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
// Similar to the Chisel ShiftRegister but allows the user to suggest a
// name to the registers that get instantiated, and
// to provide a reset value.
object ShiftRegInit {
def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T =
(0 until n).foldRight(in) {
case (i, next) => {
val r = RegNext(next, init)
name.foreach { na => r.suggestName(s"${na}_${i}") }
r
}
}
}
/** These wrap behavioral
* shift registers into specific modules to allow for
* backend flows to replace or constrain
* them properly when used for CDC synchronization,
* rather than buffering.
*
* The different types vary in their reset behavior:
* AsyncResetShiftReg -- Asynchronously reset register array
* A W(width) x D(depth) sized array is constructed from D instantiations of a
* W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg,
* but only used for timing applications
*/
abstract class AbstractPipelineReg(w: Int = 1) extends Module {
val io = IO(new Bundle {
val d = Input(UInt(w.W))
val q = Output(UInt(w.W))
}
)
}
object AbstractPipelineReg {
def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = {
val chain = Module(gen)
name.foreach{ chain.suggestName(_) }
chain.io.d := in.asUInt
chain.io.q.asTypeOf(in)
}
}
class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) {
require(depth > 0, "Depth must be greater than 0.")
override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}"
val chain = List.tabulate(depth) { i =>
Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}")
}
chain.last.io.d := io.d
chain.last.io.en := true.B
(chain.init zip chain.tail).foreach { case (sink, source) =>
sink.io.d := source.io.q
sink.io.en := true.B
}
io.q := chain.head.io.q
}
object AsyncResetShiftReg {
def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T =
AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name)
def apply [T <: Data](in: T, depth: Int, name: Option[String]): T =
apply(in, depth, 0, name)
def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T =
apply(in, depth, init.litValue.toInt, name)
def apply [T <: Data](in: T, depth: Int, init: T): T =
apply (in, depth, init.litValue.toInt, None)
}
File AsyncQueue.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util._
case class AsyncQueueParams(
depth: Int = 8,
sync: Int = 3,
safe: Boolean = true,
// If safe is true, then effort is made to resynchronize the crossing indices when either side is reset.
// This makes it safe/possible to reset one side of the crossing (but not the other) when the queue is empty.
narrow: Boolean = false)
// If narrow is true then the read mux is moved to the source side of the crossing.
// This reduces the number of level shifters in the case where the clock crossing is also a voltage crossing,
// at the expense of a combinational path from the sink to the source and back to the sink.
{
require (depth > 0 && isPow2(depth))
require (sync >= 2)
val bits = log2Ceil(depth)
val wires = if (narrow) 1 else depth
}
object AsyncQueueParams {
// When there is only one entry, we don't need narrow.
def singleton(sync: Int = 3, safe: Boolean = true) = AsyncQueueParams(1, sync, safe, false)
}
class AsyncBundleSafety extends Bundle {
val ridx_valid = Input (Bool())
val widx_valid = Output(Bool())
val source_reset_n = Output(Bool())
val sink_reset_n = Input (Bool())
}
class AsyncBundle[T <: Data](private val gen: T, val params: AsyncQueueParams = AsyncQueueParams()) extends Bundle {
// Data-path synchronization
val mem = Output(Vec(params.wires, gen))
val ridx = Input (UInt((params.bits+1).W))
val widx = Output(UInt((params.bits+1).W))
val index = params.narrow.option(Input(UInt(params.bits.W)))
// Signals used to self-stabilize a safe AsyncQueue
val safe = params.safe.option(new AsyncBundleSafety)
}
object GrayCounter {
def apply(bits: Int, increment: Bool = true.B, clear: Bool = false.B, name: String = "binary"): UInt = {
val incremented = Wire(UInt(bits.W))
val binary = RegNext(next=incremented, init=0.U).suggestName(name)
incremented := Mux(clear, 0.U, binary + increment.asUInt)
incremented ^ (incremented >> 1)
}
}
class AsyncValidSync(sync: Int, desc: String) extends RawModule {
val io = IO(new Bundle {
val in = Input(Bool())
val out = Output(Bool())
})
val clock = IO(Input(Clock()))
val reset = IO(Input(AsyncReset()))
withClockAndReset(clock, reset){
io.out := AsyncResetSynchronizerShiftReg(io.in, sync, Some(desc))
}
}
class AsyncQueueSource[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module {
override def desiredName = s"AsyncQueueSource_${gen.typeName}"
val io = IO(new Bundle {
// These come from the source domain
val enq = Flipped(Decoupled(gen))
// These cross to the sink clock domain
val async = new AsyncBundle(gen, params)
})
val bits = params.bits
val sink_ready = WireInit(true.B)
val mem = Reg(Vec(params.depth, gen)) // This does NOT need to be reset at all.
val widx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.enq.fire, !sink_ready, "widx_bin"))
val ridx = AsyncResetSynchronizerShiftReg(io.async.ridx, params.sync, Some("ridx_gray"))
val ready = sink_ready && widx =/= (ridx ^ (params.depth | params.depth >> 1).U)
val index = if (bits == 0) 0.U else io.async.widx(bits-1, 0) ^ (io.async.widx(bits, bits) << (bits-1))
when (io.enq.fire) { mem(index) := io.enq.bits }
val ready_reg = withReset(reset.asAsyncReset)(RegNext(next=ready, init=false.B).suggestName("ready_reg"))
io.enq.ready := ready_reg && sink_ready
val widx_reg = withReset(reset.asAsyncReset)(RegNext(next=widx, init=0.U).suggestName("widx_gray"))
io.async.widx := widx_reg
io.async.index match {
case Some(index) => io.async.mem(0) := mem(index)
case None => io.async.mem := mem
}
io.async.safe.foreach { sio =>
val source_valid_0 = Module(new AsyncValidSync(params.sync, "source_valid_0"))
val source_valid_1 = Module(new AsyncValidSync(params.sync, "source_valid_1"))
val sink_extend = Module(new AsyncValidSync(params.sync, "sink_extend"))
val sink_valid = Module(new AsyncValidSync(params.sync, "sink_valid"))
source_valid_0.reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset
source_valid_1.reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset
sink_extend .reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset
sink_valid .reset := reset.asAsyncReset
source_valid_0.clock := clock
source_valid_1.clock := clock
sink_extend .clock := clock
sink_valid .clock := clock
source_valid_0.io.in := true.B
source_valid_1.io.in := source_valid_0.io.out
sio.widx_valid := source_valid_1.io.out
sink_extend.io.in := sio.ridx_valid
sink_valid.io.in := sink_extend.io.out
sink_ready := sink_valid.io.out
sio.source_reset_n := !reset.asBool
// Assert that if there is stuff in the queue, then reset cannot happen
// Impossible to write because dequeue can occur on the receiving side,
// then reset allowed to happen, but write side cannot know that dequeue
// occurred.
// TODO: write some sort of sanity check assertion for users
// that denote don't reset when there is activity
// assert (!(reset || !sio.sink_reset_n) || !io.enq.valid, "Enqueue while sink is reset and AsyncQueueSource is unprotected")
// assert (!reset_rise || prev_idx_match.asBool, "Sink reset while AsyncQueueSource not empty")
}
}
class AsyncQueueSink[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module {
override def desiredName = s"AsyncQueueSink_${gen.typeName}"
val io = IO(new Bundle {
// These come from the sink domain
val deq = Decoupled(gen)
// These cross to the source clock domain
val async = Flipped(new AsyncBundle(gen, params))
})
val bits = params.bits
val source_ready = WireInit(true.B)
val ridx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.deq.fire, !source_ready, "ridx_bin"))
val widx = AsyncResetSynchronizerShiftReg(io.async.widx, params.sync, Some("widx_gray"))
val valid = source_ready && ridx =/= widx
// The mux is safe because timing analysis ensures ridx has reached the register
// On an ASIC, changes to the unread location cannot affect the selected value
// On an FPGA, only one input changes at a time => mem updates don't cause glitches
// The register only latches when the selected valued is not being written
val index = if (bits == 0) 0.U else ridx(bits-1, 0) ^ (ridx(bits, bits) << (bits-1))
io.async.index.foreach { _ := index }
// This register does not NEED to be reset, as its contents will not
// be considered unless the asynchronously reset deq valid register is set.
// It is possible that bits latches when the source domain is reset / has power cut
// This is safe, because isolation gates brought mem low before the zeroed widx reached us
val deq_bits_nxt = io.async.mem(if (params.narrow) 0.U else index)
io.deq.bits := ClockCrossingReg(deq_bits_nxt, en = valid, doInit = false, name = Some("deq_bits_reg"))
val valid_reg = withReset(reset.asAsyncReset)(RegNext(next=valid, init=false.B).suggestName("valid_reg"))
io.deq.valid := valid_reg && source_ready
val ridx_reg = withReset(reset.asAsyncReset)(RegNext(next=ridx, init=0.U).suggestName("ridx_gray"))
io.async.ridx := ridx_reg
io.async.safe.foreach { sio =>
val sink_valid_0 = Module(new AsyncValidSync(params.sync, "sink_valid_0"))
val sink_valid_1 = Module(new AsyncValidSync(params.sync, "sink_valid_1"))
val source_extend = Module(new AsyncValidSync(params.sync, "source_extend"))
val source_valid = Module(new AsyncValidSync(params.sync, "source_valid"))
sink_valid_0 .reset := (reset.asBool || !sio.source_reset_n).asAsyncReset
sink_valid_1 .reset := (reset.asBool || !sio.source_reset_n).asAsyncReset
source_extend.reset := (reset.asBool || !sio.source_reset_n).asAsyncReset
source_valid .reset := reset.asAsyncReset
sink_valid_0 .clock := clock
sink_valid_1 .clock := clock
source_extend.clock := clock
source_valid .clock := clock
sink_valid_0.io.in := true.B
sink_valid_1.io.in := sink_valid_0.io.out
sio.ridx_valid := sink_valid_1.io.out
source_extend.io.in := sio.widx_valid
source_valid.io.in := source_extend.io.out
source_ready := source_valid.io.out
sio.sink_reset_n := !reset.asBool
// TODO: write some sort of sanity check assertion for users
// that denote don't reset when there is activity
//
// val reset_and_extend = !source_ready || !sio.source_reset_n || reset.asBool
// val reset_and_extend_prev = RegNext(reset_and_extend, true.B)
// val reset_rise = !reset_and_extend_prev && reset_and_extend
// val prev_idx_match = AsyncResetReg(updateData=(io.async.widx===io.async.ridx), resetData=0)
// assert (!reset_rise || prev_idx_match.asBool, "Source reset while AsyncQueueSink not empty")
}
}
object FromAsyncBundle
{
// Sometimes it makes sense for the sink to have different sync than the source
def apply[T <: Data](x: AsyncBundle[T]): DecoupledIO[T] = apply(x, x.params.sync)
def apply[T <: Data](x: AsyncBundle[T], sync: Int): DecoupledIO[T] = {
val sink = Module(new AsyncQueueSink(chiselTypeOf(x.mem(0)), x.params.copy(sync = sync)))
sink.io.async <> x
sink.io.deq
}
}
object ToAsyncBundle
{
def apply[T <: Data](x: ReadyValidIO[T], params: AsyncQueueParams = AsyncQueueParams()): AsyncBundle[T] = {
val source = Module(new AsyncQueueSource(chiselTypeOf(x.bits), params))
source.io.enq <> x
source.io.async
}
}
class AsyncQueue[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Crossing[T] {
val io = IO(new CrossingIO(gen))
val source = withClockAndReset(io.enq_clock, io.enq_reset) { Module(new AsyncQueueSource(gen, params)) }
val sink = withClockAndReset(io.deq_clock, io.deq_reset) { Module(new AsyncQueueSink (gen, params)) }
source.io.enq <> io.enq
io.deq <> sink.io.deq
sink.io.async <> source.io.async
}
| module AsyncValidSync_144( // @[AsyncQueue.scala:58:7]
output io_out, // @[AsyncQueue.scala:59:14]
input clock, // @[AsyncQueue.scala:63:17]
input reset // @[AsyncQueue.scala:64:17]
);
wire io_in = 1'h1; // @[ShiftReg.scala:45:23]
wire _io_out_WIRE; // @[ShiftReg.scala:48:24]
wire io_out_0; // @[AsyncQueue.scala:58:7]
assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24]
AsyncResetSynchronizerShiftReg_w1_d3_i0_165 io_out_source_valid_0 ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (reset),
.io_q (_io_out_WIRE)
); // @[ShiftReg.scala:45:23]
assign io_out = io_out_0; // @[AsyncQueue.scala:58:7]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File package.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip
import chisel3._
import chisel3.util._
import scala.math.min
import scala.collection.{immutable, mutable}
package object util {
implicit class UnzippableOption[S, T](val x: Option[(S, T)]) {
def unzip = (x.map(_._1), x.map(_._2))
}
implicit class UIntIsOneOf(private val x: UInt) extends AnyVal {
def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR
def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq)
}
implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal {
/** Like Vec.apply(idx), but tolerates indices of mismatched width */
def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0))
}
implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal {
def apply(idx: UInt): T = {
if (x.size <= 1) {
x.head
} else if (!isPow2(x.size)) {
// For non-power-of-2 seqs, reflect elements to simplify decoder
(x ++ x.takeRight(x.size & -x.size)).toSeq(idx)
} else {
// Ignore MSBs of idx
val truncIdx =
if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx
else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0)
x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) }
}
}
def extract(idx: UInt): T = VecInit(x).extract(idx)
def asUInt: UInt = Cat(x.map(_.asUInt).reverse)
def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n)
def rotate(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n)
def rotateRight(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
}
// allow bitwise ops on Seq[Bool] just like UInt
implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal {
def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b }
def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b }
def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b }
def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x
def >> (n: Int): Seq[Bool] = x drop n
def unary_~ : Seq[Bool] = x.map(!_)
def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_)
def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_)
def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_)
private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B)
}
implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal {
def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable))
def getElements: Seq[Element] = x match {
case e: Element => Seq(e)
case a: Aggregate => a.getElements.flatMap(_.getElements)
}
}
/** Any Data subtype that has a Bool member named valid. */
type DataCanBeValid = Data { val valid: Bool }
implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal {
def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable)
}
implicit class StringToAugmentedString(private val x: String) extends AnyVal {
/** converts from camel case to to underscores, also removing all spaces */
def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") {
case (acc, c) if c.isUpper => acc + "_" + c.toLower
case (acc, c) if c == ' ' => acc
case (acc, c) => acc + c
}
/** converts spaces or underscores to hyphens, also lowering case */
def kebab: String = x.toLowerCase map {
case ' ' => '-'
case '_' => '-'
case c => c
}
def named(name: Option[String]): String = {
x + name.map("_named_" + _ ).getOrElse("_with_no_name")
}
def named(name: String): String = named(Some(name))
}
implicit def uintToBitPat(x: UInt): BitPat = BitPat(x)
implicit def wcToUInt(c: WideCounter): UInt = c.value
implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal {
def sextTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x)
}
def padTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(0.U((n - x.getWidth).W), x)
}
// shifts left by n if n >= 0, or right by -n if n < 0
def << (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << n(w-1, 0)
Mux(n(w), shifted >> (1 << w), shifted)
}
// shifts right by n if n >= 0, or left by -n if n < 0
def >> (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << (1 << w) >> n(w-1, 0)
Mux(n(w), shifted, shifted >> (1 << w))
}
// Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts
def extract(hi: Int, lo: Int): UInt = {
require(hi >= lo-1)
if (hi == lo-1) 0.U
else x(hi, lo)
}
// Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts
def extractOption(hi: Int, lo: Int): Option[UInt] = {
require(hi >= lo-1)
if (hi == lo-1) None
else Some(x(hi, lo))
}
// like x & ~y, but first truncate or zero-extend y to x's width
def andNot(y: UInt): UInt = x & ~(y | (x & 0.U))
def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n)
def rotateRight(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r))
}
}
def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n))
def rotateLeft(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r))
}
}
// compute (this + y) % n, given (this < n) and (y < n)
def addWrap(y: UInt, n: Int): UInt = {
val z = x +& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0)
}
// compute (this - y) % n, given (this < n) and (y < n)
def subWrap(y: UInt, n: Int): UInt = {
val z = x -& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0)
}
def grouped(width: Int): Seq[UInt] =
(0 until x.getWidth by width).map(base => x(base + width - 1, base))
def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds
def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x)
// Like >=, but prevents x-prop for ('x >= 0)
def >== (y: UInt): Bool = x >= y || y === 0.U
}
implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal {
def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y)
def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y)
}
implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal {
def toInt: Int = if (x) 1 else 0
// this one's snagged from scalaz
def option[T](z: => T): Option[T] = if (x) Some(z) else None
}
implicit class IntToAugmentedInt(private val x: Int) extends AnyVal {
// exact log2
def log2: Int = {
require(isPow2(x))
log2Ceil(x)
}
}
def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x)
def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x))
def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0)
def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1)
def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None
// Fill 1s from low bits to high bits
def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth)
def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0))
helper(1, x)(width-1, 0)
}
// Fill 1s form high bits to low bits
def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth)
def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x >> s))
helper(1, x)(width-1, 0)
}
def OptimizationBarrier[T <: Data](in: T): T = {
val barrier = Module(new Module {
val io = IO(new Bundle {
val x = Input(chiselTypeOf(in))
val y = Output(chiselTypeOf(in))
})
io.y := io.x
override def desiredName = s"OptimizationBarrier_${in.typeName}"
})
barrier.io.x := in
barrier.io.y
}
/** Similar to Seq.groupBy except this returns a Seq instead of a Map
* Useful for deterministic code generation
*/
def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = {
val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]]
for (x <- xs) {
val key = f(x)
val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A])
l += x
}
map.view.map({ case (k, vs) => k -> vs.toList }).toList
}
def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match {
case 1 => List.fill(n)(in.head)
case x if x == n => in
case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in")
}
// HeterogeneousBag moved to standalond diplomacy
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts)
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag
}
| module OptimizationBarrier_TLBEntryData_31( // @[package.scala:267:30]
input clock, // @[package.scala:267:30]
input reset, // @[package.scala:267:30]
input [19:0] io_x_ppn, // @[package.scala:268:18]
input io_x_u, // @[package.scala:268:18]
input io_x_g, // @[package.scala:268:18]
input io_x_ae_ptw, // @[package.scala:268:18]
input io_x_ae_final, // @[package.scala:268:18]
input io_x_ae_stage2, // @[package.scala:268:18]
input io_x_pf, // @[package.scala:268:18]
input io_x_gf, // @[package.scala:268:18]
input io_x_sw, // @[package.scala:268:18]
input io_x_sx, // @[package.scala:268:18]
input io_x_sr, // @[package.scala:268:18]
input io_x_hw, // @[package.scala:268:18]
input io_x_hx, // @[package.scala:268:18]
input io_x_hr, // @[package.scala:268:18]
input io_x_pw, // @[package.scala:268:18]
input io_x_px, // @[package.scala:268:18]
input io_x_pr, // @[package.scala:268:18]
input io_x_ppp, // @[package.scala:268:18]
input io_x_pal, // @[package.scala:268:18]
input io_x_paa, // @[package.scala:268:18]
input io_x_eff, // @[package.scala:268:18]
input io_x_c, // @[package.scala:268:18]
input io_x_fragmented_superpage, // @[package.scala:268:18]
output io_y_u, // @[package.scala:268:18]
output io_y_ae_ptw, // @[package.scala:268:18]
output io_y_ae_final, // @[package.scala:268:18]
output io_y_ae_stage2, // @[package.scala:268:18]
output io_y_pf, // @[package.scala:268:18]
output io_y_gf, // @[package.scala:268:18]
output io_y_sw, // @[package.scala:268:18]
output io_y_sx, // @[package.scala:268:18]
output io_y_sr, // @[package.scala:268:18]
output io_y_hw, // @[package.scala:268:18]
output io_y_hx, // @[package.scala:268:18]
output io_y_hr, // @[package.scala:268:18]
output io_y_pw, // @[package.scala:268:18]
output io_y_px, // @[package.scala:268:18]
output io_y_pr, // @[package.scala:268:18]
output io_y_ppp, // @[package.scala:268:18]
output io_y_pal, // @[package.scala:268:18]
output io_y_paa, // @[package.scala:268:18]
output io_y_eff, // @[package.scala:268:18]
output io_y_c // @[package.scala:268:18]
);
wire [19:0] io_x_ppn_0 = io_x_ppn; // @[package.scala:267:30]
wire io_x_u_0 = io_x_u; // @[package.scala:267:30]
wire io_x_g_0 = io_x_g; // @[package.scala:267:30]
wire io_x_ae_ptw_0 = io_x_ae_ptw; // @[package.scala:267:30]
wire io_x_ae_final_0 = io_x_ae_final; // @[package.scala:267:30]
wire io_x_ae_stage2_0 = io_x_ae_stage2; // @[package.scala:267:30]
wire io_x_pf_0 = io_x_pf; // @[package.scala:267:30]
wire io_x_gf_0 = io_x_gf; // @[package.scala:267:30]
wire io_x_sw_0 = io_x_sw; // @[package.scala:267:30]
wire io_x_sx_0 = io_x_sx; // @[package.scala:267:30]
wire io_x_sr_0 = io_x_sr; // @[package.scala:267:30]
wire io_x_hw_0 = io_x_hw; // @[package.scala:267:30]
wire io_x_hx_0 = io_x_hx; // @[package.scala:267:30]
wire io_x_hr_0 = io_x_hr; // @[package.scala:267:30]
wire io_x_pw_0 = io_x_pw; // @[package.scala:267:30]
wire io_x_px_0 = io_x_px; // @[package.scala:267:30]
wire io_x_pr_0 = io_x_pr; // @[package.scala:267:30]
wire io_x_ppp_0 = io_x_ppp; // @[package.scala:267:30]
wire io_x_pal_0 = io_x_pal; // @[package.scala:267:30]
wire io_x_paa_0 = io_x_paa; // @[package.scala:267:30]
wire io_x_eff_0 = io_x_eff; // @[package.scala:267:30]
wire io_x_c_0 = io_x_c; // @[package.scala:267:30]
wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage; // @[package.scala:267:30]
wire [19:0] io_y_ppn = io_x_ppn_0; // @[package.scala:267:30]
wire io_y_u_0 = io_x_u_0; // @[package.scala:267:30]
wire io_y_g = io_x_g_0; // @[package.scala:267:30]
wire io_y_ae_ptw_0 = io_x_ae_ptw_0; // @[package.scala:267:30]
wire io_y_ae_final_0 = io_x_ae_final_0; // @[package.scala:267:30]
wire io_y_ae_stage2_0 = io_x_ae_stage2_0; // @[package.scala:267:30]
wire io_y_pf_0 = io_x_pf_0; // @[package.scala:267:30]
wire io_y_gf_0 = io_x_gf_0; // @[package.scala:267:30]
wire io_y_sw_0 = io_x_sw_0; // @[package.scala:267:30]
wire io_y_sx_0 = io_x_sx_0; // @[package.scala:267:30]
wire io_y_sr_0 = io_x_sr_0; // @[package.scala:267:30]
wire io_y_hw_0 = io_x_hw_0; // @[package.scala:267:30]
wire io_y_hx_0 = io_x_hx_0; // @[package.scala:267:30]
wire io_y_hr_0 = io_x_hr_0; // @[package.scala:267:30]
wire io_y_pw_0 = io_x_pw_0; // @[package.scala:267:30]
wire io_y_px_0 = io_x_px_0; // @[package.scala:267:30]
wire io_y_pr_0 = io_x_pr_0; // @[package.scala:267:30]
wire io_y_ppp_0 = io_x_ppp_0; // @[package.scala:267:30]
wire io_y_pal_0 = io_x_pal_0; // @[package.scala:267:30]
wire io_y_paa_0 = io_x_paa_0; // @[package.scala:267:30]
wire io_y_eff_0 = io_x_eff_0; // @[package.scala:267:30]
wire io_y_c_0 = io_x_c_0; // @[package.scala:267:30]
wire io_y_fragmented_superpage = io_x_fragmented_superpage_0; // @[package.scala:267:30]
assign io_y_u = io_y_u_0; // @[package.scala:267:30]
assign io_y_ae_ptw = io_y_ae_ptw_0; // @[package.scala:267:30]
assign io_y_ae_final = io_y_ae_final_0; // @[package.scala:267:30]
assign io_y_ae_stage2 = io_y_ae_stage2_0; // @[package.scala:267:30]
assign io_y_pf = io_y_pf_0; // @[package.scala:267:30]
assign io_y_gf = io_y_gf_0; // @[package.scala:267:30]
assign io_y_sw = io_y_sw_0; // @[package.scala:267:30]
assign io_y_sx = io_y_sx_0; // @[package.scala:267:30]
assign io_y_sr = io_y_sr_0; // @[package.scala:267:30]
assign io_y_hw = io_y_hw_0; // @[package.scala:267:30]
assign io_y_hx = io_y_hx_0; // @[package.scala:267:30]
assign io_y_hr = io_y_hr_0; // @[package.scala:267:30]
assign io_y_pw = io_y_pw_0; // @[package.scala:267:30]
assign io_y_px = io_y_px_0; // @[package.scala:267:30]
assign io_y_pr = io_y_pr_0; // @[package.scala:267:30]
assign io_y_ppp = io_y_ppp_0; // @[package.scala:267:30]
assign io_y_pal = io_y_pal_0; // @[package.scala:267:30]
assign io_y_paa = io_y_paa_0; // @[package.scala:267:30]
assign io_y_eff = io_y_eff_0; // @[package.scala:267:30]
assign io_y_c = io_y_c_0; // @[package.scala:267:30]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File primitives.scala:
/*============================================================================
This Chisel source file is part of a pre-release version of the HardFloat IEEE
Floating-Point Arithmetic Package, by John R. Hauser (with some contributions
from Yunsup Lee and Andrew Waterman, mainly concerning testing).
Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
University of California. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
package hardfloat
import chisel3._
import chisel3.util._
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
object lowMask
{
def apply(in: UInt, topBound: BigInt, bottomBound: BigInt): UInt =
{
require(topBound != bottomBound)
val numInVals = BigInt(1)<<in.getWidth
if (topBound < bottomBound) {
lowMask(~in, numInVals - 1 - topBound, numInVals - 1 - bottomBound)
} else if (numInVals > 64 /* Empirical */) {
// For simulation performance, we should avoid generating
// exteremely wide shifters, so we divide and conquer.
// Empirically, this does not impact synthesis QoR.
val mid = numInVals / 2
val msb = in(in.getWidth - 1)
val lsbs = in(in.getWidth - 2, 0)
if (mid < topBound) {
if (mid <= bottomBound) {
Mux(msb,
lowMask(lsbs, topBound - mid, bottomBound - mid),
0.U
)
} else {
Mux(msb,
lowMask(lsbs, topBound - mid, 0) ## ((BigInt(1)<<(mid - bottomBound).toInt) - 1).U,
lowMask(lsbs, mid, bottomBound)
)
}
} else {
~Mux(msb, 0.U, ~lowMask(lsbs, topBound, bottomBound))
}
} else {
val shift = (BigInt(-1)<<numInVals.toInt).S>>in
Reverse(
shift(
(numInVals - 1 - bottomBound).toInt,
(numInVals - topBound).toInt
)
)
}
}
}
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
object countLeadingZeros
{
def apply(in: UInt): UInt = PriorityEncoder(in.asBools.reverse)
}
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
object orReduceBy2
{
def apply(in: UInt): UInt =
{
val reducedWidth = (in.getWidth + 1)>>1
val reducedVec = Wire(Vec(reducedWidth, Bool()))
for (ix <- 0 until reducedWidth - 1) {
reducedVec(ix) := in(ix * 2 + 1, ix * 2).orR
}
reducedVec(reducedWidth - 1) :=
in(in.getWidth - 1, (reducedWidth - 1) * 2).orR
reducedVec.asUInt
}
}
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
object orReduceBy4
{
def apply(in: UInt): UInt =
{
val reducedWidth = (in.getWidth + 3)>>2
val reducedVec = Wire(Vec(reducedWidth, Bool()))
for (ix <- 0 until reducedWidth - 1) {
reducedVec(ix) := in(ix * 4 + 3, ix * 4).orR
}
reducedVec(reducedWidth - 1) :=
in(in.getWidth - 1, (reducedWidth - 1) * 4).orR
reducedVec.asUInt
}
}
File RoundAnyRawFNToRecFN.scala:
/*============================================================================
This Chisel source file is part of a pre-release version of the HardFloat IEEE
Floating-Point Arithmetic Package, by John R. Hauser (with some contributions
from Yunsup Lee and Andrew Waterman, mainly concerning testing).
Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
University of California. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
package hardfloat
import chisel3._
import chisel3.util.Fill
import consts._
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
class
RoundAnyRawFNToRecFN(
inExpWidth: Int,
inSigWidth: Int,
outExpWidth: Int,
outSigWidth: Int,
options: Int
)
extends RawModule
{
override def desiredName = s"RoundAnyRawFNToRecFN_ie${inExpWidth}_is${inSigWidth}_oe${outExpWidth}_os${outSigWidth}"
val io = IO(new Bundle {
val invalidExc = Input(Bool()) // overrides 'infiniteExc' and 'in'
val infiniteExc = Input(Bool()) // overrides 'in' except for 'in.sign'
val in = Input(new RawFloat(inExpWidth, inSigWidth))
// (allowed exponent range has limits)
val roundingMode = Input(UInt(3.W))
val detectTininess = Input(UInt(1.W))
val out = Output(Bits((outExpWidth + outSigWidth + 1).W))
val exceptionFlags = Output(Bits(5.W))
})
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val sigMSBitAlwaysZero = ((options & flRoundOpt_sigMSBitAlwaysZero) != 0)
val effectiveInSigWidth =
if (sigMSBitAlwaysZero) inSigWidth else inSigWidth + 1
val neverUnderflows =
((options &
(flRoundOpt_neverUnderflows | flRoundOpt_subnormsAlwaysExact)
) != 0) ||
(inExpWidth < outExpWidth)
val neverOverflows =
((options & flRoundOpt_neverOverflows) != 0) ||
(inExpWidth < outExpWidth)
val outNaNExp = BigInt(7)<<(outExpWidth - 2)
val outInfExp = BigInt(6)<<(outExpWidth - 2)
val outMaxFiniteExp = outInfExp - 1
val outMinNormExp = (BigInt(1)<<(outExpWidth - 1)) + 2
val outMinNonzeroExp = outMinNormExp - outSigWidth + 1
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val roundingMode_near_even = (io.roundingMode === round_near_even)
val roundingMode_minMag = (io.roundingMode === round_minMag)
val roundingMode_min = (io.roundingMode === round_min)
val roundingMode_max = (io.roundingMode === round_max)
val roundingMode_near_maxMag = (io.roundingMode === round_near_maxMag)
val roundingMode_odd = (io.roundingMode === round_odd)
val roundMagUp =
(roundingMode_min && io.in.sign) || (roundingMode_max && ! io.in.sign)
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val sAdjustedExp =
if (inExpWidth < outExpWidth)
(io.in.sExp +&
((BigInt(1)<<outExpWidth) - (BigInt(1)<<inExpWidth)).S
)(outExpWidth, 0).zext
else if (inExpWidth == outExpWidth)
io.in.sExp
else
io.in.sExp +&
((BigInt(1)<<outExpWidth) - (BigInt(1)<<inExpWidth)).S
val adjustedSig =
if (inSigWidth <= outSigWidth + 2)
io.in.sig<<(outSigWidth - inSigWidth + 2)
else
(io.in.sig(inSigWidth, inSigWidth - outSigWidth - 1) ##
io.in.sig(inSigWidth - outSigWidth - 2, 0).orR
)
val doShiftSigDown1 =
if (sigMSBitAlwaysZero) false.B else adjustedSig(outSigWidth + 2)
val common_expOut = Wire(UInt((outExpWidth + 1).W))
val common_fractOut = Wire(UInt((outSigWidth - 1).W))
val common_overflow = Wire(Bool())
val common_totalUnderflow = Wire(Bool())
val common_underflow = Wire(Bool())
val common_inexact = Wire(Bool())
if (
neverOverflows && neverUnderflows
&& (effectiveInSigWidth <= outSigWidth)
) {
//--------------------------------------------------------------------
//--------------------------------------------------------------------
common_expOut := sAdjustedExp(outExpWidth, 0) + doShiftSigDown1
common_fractOut :=
Mux(doShiftSigDown1,
adjustedSig(outSigWidth + 1, 3),
adjustedSig(outSigWidth, 2)
)
common_overflow := false.B
common_totalUnderflow := false.B
common_underflow := false.B
common_inexact := false.B
} else {
//--------------------------------------------------------------------
//--------------------------------------------------------------------
val roundMask =
if (neverUnderflows)
0.U(outSigWidth.W) ## doShiftSigDown1 ## 3.U(2.W)
else
(lowMask(
sAdjustedExp(outExpWidth, 0),
outMinNormExp - outSigWidth - 1,
outMinNormExp
) | doShiftSigDown1) ##
3.U(2.W)
val shiftedRoundMask = 0.U(1.W) ## roundMask>>1
val roundPosMask = ~shiftedRoundMask & roundMask
val roundPosBit = (adjustedSig & roundPosMask).orR
val anyRoundExtra = (adjustedSig & shiftedRoundMask).orR
val anyRound = roundPosBit || anyRoundExtra
val roundIncr =
((roundingMode_near_even || roundingMode_near_maxMag) &&
roundPosBit) ||
(roundMagUp && anyRound)
val roundedSig: Bits =
Mux(roundIncr,
(((adjustedSig | roundMask)>>2) +& 1.U) &
~Mux(roundingMode_near_even && roundPosBit &&
! anyRoundExtra,
roundMask>>1,
0.U((outSigWidth + 2).W)
),
(adjustedSig & ~roundMask)>>2 |
Mux(roundingMode_odd && anyRound, roundPosMask>>1, 0.U)
)
//*** IF SIG WIDTH IS VERY NARROW, NEED TO ACCOUNT FOR ROUND-EVEN ZEROING
//*** M.S. BIT OF SUBNORMAL SIG?
val sRoundedExp = sAdjustedExp +& (roundedSig>>outSigWidth).asUInt.zext
common_expOut := sRoundedExp(outExpWidth, 0)
common_fractOut :=
Mux(doShiftSigDown1,
roundedSig(outSigWidth - 1, 1),
roundedSig(outSigWidth - 2, 0)
)
common_overflow :=
(if (neverOverflows) false.B else
//*** REWRITE BASED ON BEFORE-ROUNDING EXPONENT?:
(sRoundedExp>>(outExpWidth - 1) >= 3.S))
common_totalUnderflow :=
(if (neverUnderflows) false.B else
//*** WOULD BE GOOD ENOUGH TO USE EXPONENT BEFORE ROUNDING?:
(sRoundedExp < outMinNonzeroExp.S))
val unboundedRange_roundPosBit =
Mux(doShiftSigDown1, adjustedSig(2), adjustedSig(1))
val unboundedRange_anyRound =
(doShiftSigDown1 && adjustedSig(2)) || adjustedSig(1, 0).orR
val unboundedRange_roundIncr =
((roundingMode_near_even || roundingMode_near_maxMag) &&
unboundedRange_roundPosBit) ||
(roundMagUp && unboundedRange_anyRound)
val roundCarry =
Mux(doShiftSigDown1,
roundedSig(outSigWidth + 1),
roundedSig(outSigWidth)
)
common_underflow :=
(if (neverUnderflows) false.B else
common_totalUnderflow ||
//*** IF SIG WIDTH IS VERY NARROW, NEED TO ACCOUNT FOR ROUND-EVEN ZEROING
//*** M.S. BIT OF SUBNORMAL SIG?
(anyRound && ((sAdjustedExp>>outExpWidth) <= 0.S) &&
Mux(doShiftSigDown1, roundMask(3), roundMask(2)) &&
! ((io.detectTininess === tininess_afterRounding) &&
! Mux(doShiftSigDown1,
roundMask(4),
roundMask(3)
) &&
roundCarry && roundPosBit &&
unboundedRange_roundIncr)))
common_inexact := common_totalUnderflow || anyRound
}
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val isNaNOut = io.invalidExc || io.in.isNaN
val notNaN_isSpecialInfOut = io.infiniteExc || io.in.isInf
val commonCase = ! isNaNOut && ! notNaN_isSpecialInfOut && ! io.in.isZero
val overflow = commonCase && common_overflow
val underflow = commonCase && common_underflow
val inexact = overflow || (commonCase && common_inexact)
val overflow_roundMagUp =
roundingMode_near_even || roundingMode_near_maxMag || roundMagUp
val pegMinNonzeroMagOut =
commonCase && common_totalUnderflow && (roundMagUp || roundingMode_odd)
val pegMaxFiniteMagOut = overflow && ! overflow_roundMagUp
val notNaN_isInfOut =
notNaN_isSpecialInfOut || (overflow && overflow_roundMagUp)
val signOut = Mux(isNaNOut, false.B, io.in.sign)
val expOut =
(common_expOut &
~Mux(io.in.isZero || common_totalUnderflow,
(BigInt(7)<<(outExpWidth - 2)).U((outExpWidth + 1).W),
0.U
) &
~Mux(pegMinNonzeroMagOut,
~outMinNonzeroExp.U((outExpWidth + 1).W),
0.U
) &
~Mux(pegMaxFiniteMagOut,
(BigInt(1)<<(outExpWidth - 1)).U((outExpWidth + 1).W),
0.U
) &
~Mux(notNaN_isInfOut,
(BigInt(1)<<(outExpWidth - 2)).U((outExpWidth + 1).W),
0.U
)) |
Mux(pegMinNonzeroMagOut,
outMinNonzeroExp.U((outExpWidth + 1).W),
0.U
) |
Mux(pegMaxFiniteMagOut,
outMaxFiniteExp.U((outExpWidth + 1).W),
0.U
) |
Mux(notNaN_isInfOut, outInfExp.U((outExpWidth + 1).W), 0.U) |
Mux(isNaNOut, outNaNExp.U((outExpWidth + 1).W), 0.U)
val fractOut =
Mux(isNaNOut || io.in.isZero || common_totalUnderflow,
Mux(isNaNOut, (BigInt(1)<<(outSigWidth - 2)).U, 0.U),
common_fractOut
) |
Fill(outSigWidth - 1, pegMaxFiniteMagOut)
io.out := signOut ## expOut ## fractOut
io.exceptionFlags :=
io.invalidExc ## io.infiniteExc ## overflow ## underflow ## inexact
}
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
class
RoundRawFNToRecFN(expWidth: Int, sigWidth: Int, options: Int)
extends RawModule
{
override def desiredName = s"RoundRawFNToRecFN_e${expWidth}_s${sigWidth}"
val io = IO(new Bundle {
val invalidExc = Input(Bool()) // overrides 'infiniteExc' and 'in'
val infiniteExc = Input(Bool()) // overrides 'in' except for 'in.sign'
val in = Input(new RawFloat(expWidth, sigWidth + 2))
val roundingMode = Input(UInt(3.W))
val detectTininess = Input(UInt(1.W))
val out = Output(Bits((expWidth + sigWidth + 1).W))
val exceptionFlags = Output(Bits(5.W))
})
val roundAnyRawFNToRecFN =
Module(
new RoundAnyRawFNToRecFN(
expWidth, sigWidth + 2, expWidth, sigWidth, options))
roundAnyRawFNToRecFN.io.invalidExc := io.invalidExc
roundAnyRawFNToRecFN.io.infiniteExc := io.infiniteExc
roundAnyRawFNToRecFN.io.in := io.in
roundAnyRawFNToRecFN.io.roundingMode := io.roundingMode
roundAnyRawFNToRecFN.io.detectTininess := io.detectTininess
io.out := roundAnyRawFNToRecFN.io.out
io.exceptionFlags := roundAnyRawFNToRecFN.io.exceptionFlags
}
| module RoundAnyRawFNToRecFN_ie8_is26_oe8_os24_5( // @[RoundAnyRawFNToRecFN.scala:48:5]
input io_invalidExc, // @[RoundAnyRawFNToRecFN.scala:58:16]
input io_infiniteExc, // @[RoundAnyRawFNToRecFN.scala:58:16]
input io_in_isNaN, // @[RoundAnyRawFNToRecFN.scala:58:16]
input io_in_isInf, // @[RoundAnyRawFNToRecFN.scala:58:16]
input io_in_isZero, // @[RoundAnyRawFNToRecFN.scala:58:16]
input io_in_sign, // @[RoundAnyRawFNToRecFN.scala:58:16]
input [9:0] io_in_sExp, // @[RoundAnyRawFNToRecFN.scala:58:16]
input [26:0] io_in_sig, // @[RoundAnyRawFNToRecFN.scala:58:16]
input [2:0] io_roundingMode, // @[RoundAnyRawFNToRecFN.scala:58:16]
output [32:0] io_out, // @[RoundAnyRawFNToRecFN.scala:58:16]
output [4:0] io_exceptionFlags // @[RoundAnyRawFNToRecFN.scala:58:16]
);
wire io_invalidExc_0 = io_invalidExc; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire io_infiniteExc_0 = io_infiniteExc; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire io_in_isNaN_0 = io_in_isNaN; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire io_in_isInf_0 = io_in_isInf; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire io_in_isZero_0 = io_in_isZero; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire io_in_sign_0 = io_in_sign; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire [9:0] io_in_sExp_0 = io_in_sExp; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire [26:0] io_in_sig_0 = io_in_sig; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire [2:0] io_roundingMode_0 = io_roundingMode; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire [15:0] _roundMask_T_5 = 16'hFF; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_4 = 16'hFF00; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_10 = 16'hFF00; // @[primitives.scala:77:20]
wire [11:0] _roundMask_T_13 = 12'hFF; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_14 = 16'hFF0; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_15 = 16'hF0F; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_20 = 16'hF0F0; // @[primitives.scala:77:20]
wire [13:0] _roundMask_T_23 = 14'hF0F; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_24 = 16'h3C3C; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_25 = 16'h3333; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_30 = 16'hCCCC; // @[primitives.scala:77:20]
wire [14:0] _roundMask_T_33 = 15'h3333; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_34 = 16'h6666; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_35 = 16'h5555; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_40 = 16'hAAAA; // @[primitives.scala:77:20]
wire [8:0] _expOut_T_4 = 9'h194; // @[RoundAnyRawFNToRecFN.scala:258:19]
wire io_detectTininess = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire _common_underflow_T_7 = 1'h1; // @[RoundAnyRawFNToRecFN.scala:222:49]
wire [26:0] adjustedSig = io_in_sig_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :114:22]
wire [32:0] _io_out_T_1; // @[RoundAnyRawFNToRecFN.scala:286:33]
wire [4:0] _io_exceptionFlags_T_3; // @[RoundAnyRawFNToRecFN.scala:288:66]
wire [32:0] io_out_0; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire [4:0] io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire roundingMode_near_even = io_roundingMode_0 == 3'h0; // @[RoundAnyRawFNToRecFN.scala:48:5, :90:53]
wire roundingMode_minMag = io_roundingMode_0 == 3'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :91:53]
wire roundingMode_min = io_roundingMode_0 == 3'h2; // @[RoundAnyRawFNToRecFN.scala:48:5, :92:53]
wire roundingMode_max = io_roundingMode_0 == 3'h3; // @[RoundAnyRawFNToRecFN.scala:48:5, :93:53]
wire roundingMode_near_maxMag = io_roundingMode_0 == 3'h4; // @[RoundAnyRawFNToRecFN.scala:48:5, :94:53]
wire roundingMode_odd = io_roundingMode_0 == 3'h6; // @[RoundAnyRawFNToRecFN.scala:48:5, :95:53]
wire _roundMagUp_T = roundingMode_min & io_in_sign_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :92:53, :98:27]
wire _roundMagUp_T_1 = ~io_in_sign_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :98:66]
wire _roundMagUp_T_2 = roundingMode_max & _roundMagUp_T_1; // @[RoundAnyRawFNToRecFN.scala:93:53, :98:{63,66}]
wire roundMagUp = _roundMagUp_T | _roundMagUp_T_2; // @[RoundAnyRawFNToRecFN.scala:98:{27,42,63}]
wire doShiftSigDown1 = adjustedSig[26]; // @[RoundAnyRawFNToRecFN.scala:114:22, :120:57]
wire [8:0] _common_expOut_T; // @[RoundAnyRawFNToRecFN.scala:187:37]
wire [8:0] common_expOut; // @[RoundAnyRawFNToRecFN.scala:122:31]
wire [22:0] _common_fractOut_T_2; // @[RoundAnyRawFNToRecFN.scala:189:16]
wire [22:0] common_fractOut; // @[RoundAnyRawFNToRecFN.scala:123:31]
wire _common_overflow_T_1; // @[RoundAnyRawFNToRecFN.scala:196:50]
wire common_overflow; // @[RoundAnyRawFNToRecFN.scala:124:37]
wire _common_totalUnderflow_T; // @[RoundAnyRawFNToRecFN.scala:200:31]
wire common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:125:37]
wire _common_underflow_T_18; // @[RoundAnyRawFNToRecFN.scala:217:40]
wire common_underflow; // @[RoundAnyRawFNToRecFN.scala:126:37]
wire _common_inexact_T; // @[RoundAnyRawFNToRecFN.scala:230:49]
wire common_inexact; // @[RoundAnyRawFNToRecFN.scala:127:37]
wire [8:0] _roundMask_T = io_in_sExp_0[8:0]; // @[RoundAnyRawFNToRecFN.scala:48:5, :156:37]
wire [8:0] _roundMask_T_1 = ~_roundMask_T; // @[primitives.scala:52:21]
wire roundMask_msb = _roundMask_T_1[8]; // @[primitives.scala:52:21, :58:25]
wire [7:0] roundMask_lsbs = _roundMask_T_1[7:0]; // @[primitives.scala:52:21, :59:26]
wire roundMask_msb_1 = roundMask_lsbs[7]; // @[primitives.scala:58:25, :59:26]
wire [6:0] roundMask_lsbs_1 = roundMask_lsbs[6:0]; // @[primitives.scala:59:26]
wire roundMask_msb_2 = roundMask_lsbs_1[6]; // @[primitives.scala:58:25, :59:26]
wire roundMask_msb_3 = roundMask_lsbs_1[6]; // @[primitives.scala:58:25, :59:26]
wire [5:0] roundMask_lsbs_2 = roundMask_lsbs_1[5:0]; // @[primitives.scala:59:26]
wire [5:0] roundMask_lsbs_3 = roundMask_lsbs_1[5:0]; // @[primitives.scala:59:26]
wire [64:0] roundMask_shift = $signed(65'sh10000000000000000 >>> roundMask_lsbs_2); // @[primitives.scala:59:26, :76:56]
wire [21:0] _roundMask_T_2 = roundMask_shift[63:42]; // @[primitives.scala:76:56, :78:22]
wire [15:0] _roundMask_T_3 = _roundMask_T_2[15:0]; // @[primitives.scala:77:20, :78:22]
wire [7:0] _roundMask_T_6 = _roundMask_T_3[15:8]; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_7 = {8'h0, _roundMask_T_6}; // @[primitives.scala:77:20]
wire [7:0] _roundMask_T_8 = _roundMask_T_3[7:0]; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_9 = {_roundMask_T_8, 8'h0}; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_11 = _roundMask_T_9 & 16'hFF00; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_12 = _roundMask_T_7 | _roundMask_T_11; // @[primitives.scala:77:20]
wire [11:0] _roundMask_T_16 = _roundMask_T_12[15:4]; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_17 = {4'h0, _roundMask_T_16 & 12'hF0F}; // @[primitives.scala:77:20]
wire [11:0] _roundMask_T_18 = _roundMask_T_12[11:0]; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_19 = {_roundMask_T_18, 4'h0}; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_21 = _roundMask_T_19 & 16'hF0F0; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_22 = _roundMask_T_17 | _roundMask_T_21; // @[primitives.scala:77:20]
wire [13:0] _roundMask_T_26 = _roundMask_T_22[15:2]; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_27 = {2'h0, _roundMask_T_26 & 14'h3333}; // @[primitives.scala:77:20]
wire [13:0] _roundMask_T_28 = _roundMask_T_22[13:0]; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_29 = {_roundMask_T_28, 2'h0}; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_31 = _roundMask_T_29 & 16'hCCCC; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_32 = _roundMask_T_27 | _roundMask_T_31; // @[primitives.scala:77:20]
wire [14:0] _roundMask_T_36 = _roundMask_T_32[15:1]; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_37 = {1'h0, _roundMask_T_36 & 15'h5555}; // @[primitives.scala:77:20]
wire [14:0] _roundMask_T_38 = _roundMask_T_32[14:0]; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_39 = {_roundMask_T_38, 1'h0}; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_41 = _roundMask_T_39 & 16'hAAAA; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_42 = _roundMask_T_37 | _roundMask_T_41; // @[primitives.scala:77:20]
wire [5:0] _roundMask_T_43 = _roundMask_T_2[21:16]; // @[primitives.scala:77:20, :78:22]
wire [3:0] _roundMask_T_44 = _roundMask_T_43[3:0]; // @[primitives.scala:77:20]
wire [1:0] _roundMask_T_45 = _roundMask_T_44[1:0]; // @[primitives.scala:77:20]
wire _roundMask_T_46 = _roundMask_T_45[0]; // @[primitives.scala:77:20]
wire _roundMask_T_47 = _roundMask_T_45[1]; // @[primitives.scala:77:20]
wire [1:0] _roundMask_T_48 = {_roundMask_T_46, _roundMask_T_47}; // @[primitives.scala:77:20]
wire [1:0] _roundMask_T_49 = _roundMask_T_44[3:2]; // @[primitives.scala:77:20]
wire _roundMask_T_50 = _roundMask_T_49[0]; // @[primitives.scala:77:20]
wire _roundMask_T_51 = _roundMask_T_49[1]; // @[primitives.scala:77:20]
wire [1:0] _roundMask_T_52 = {_roundMask_T_50, _roundMask_T_51}; // @[primitives.scala:77:20]
wire [3:0] _roundMask_T_53 = {_roundMask_T_48, _roundMask_T_52}; // @[primitives.scala:77:20]
wire [1:0] _roundMask_T_54 = _roundMask_T_43[5:4]; // @[primitives.scala:77:20]
wire _roundMask_T_55 = _roundMask_T_54[0]; // @[primitives.scala:77:20]
wire _roundMask_T_56 = _roundMask_T_54[1]; // @[primitives.scala:77:20]
wire [1:0] _roundMask_T_57 = {_roundMask_T_55, _roundMask_T_56}; // @[primitives.scala:77:20]
wire [5:0] _roundMask_T_58 = {_roundMask_T_53, _roundMask_T_57}; // @[primitives.scala:77:20]
wire [21:0] _roundMask_T_59 = {_roundMask_T_42, _roundMask_T_58}; // @[primitives.scala:77:20]
wire [21:0] _roundMask_T_60 = ~_roundMask_T_59; // @[primitives.scala:73:32, :77:20]
wire [21:0] _roundMask_T_61 = roundMask_msb_2 ? 22'h0 : _roundMask_T_60; // @[primitives.scala:58:25, :73:{21,32}]
wire [21:0] _roundMask_T_62 = ~_roundMask_T_61; // @[primitives.scala:73:{17,21}]
wire [24:0] _roundMask_T_63 = {_roundMask_T_62, 3'h7}; // @[primitives.scala:68:58, :73:17]
wire [64:0] roundMask_shift_1 = $signed(65'sh10000000000000000 >>> roundMask_lsbs_3); // @[primitives.scala:59:26, :76:56]
wire [2:0] _roundMask_T_64 = roundMask_shift_1[2:0]; // @[primitives.scala:76:56, :78:22]
wire [1:0] _roundMask_T_65 = _roundMask_T_64[1:0]; // @[primitives.scala:77:20, :78:22]
wire _roundMask_T_66 = _roundMask_T_65[0]; // @[primitives.scala:77:20]
wire _roundMask_T_67 = _roundMask_T_65[1]; // @[primitives.scala:77:20]
wire [1:0] _roundMask_T_68 = {_roundMask_T_66, _roundMask_T_67}; // @[primitives.scala:77:20]
wire _roundMask_T_69 = _roundMask_T_64[2]; // @[primitives.scala:77:20, :78:22]
wire [2:0] _roundMask_T_70 = {_roundMask_T_68, _roundMask_T_69}; // @[primitives.scala:77:20]
wire [2:0] _roundMask_T_71 = roundMask_msb_3 ? _roundMask_T_70 : 3'h0; // @[primitives.scala:58:25, :62:24, :77:20]
wire [24:0] _roundMask_T_72 = roundMask_msb_1 ? _roundMask_T_63 : {22'h0, _roundMask_T_71}; // @[primitives.scala:58:25, :62:24, :67:24, :68:58]
wire [24:0] _roundMask_T_73 = roundMask_msb ? _roundMask_T_72 : 25'h0; // @[primitives.scala:58:25, :62:24, :67:24]
wire [24:0] _roundMask_T_74 = {_roundMask_T_73[24:1], _roundMask_T_73[0] | doShiftSigDown1}; // @[primitives.scala:62:24]
wire [26:0] roundMask = {_roundMask_T_74, 2'h3}; // @[RoundAnyRawFNToRecFN.scala:159:{23,42}]
wire [27:0] _shiftedRoundMask_T = {1'h0, roundMask}; // @[RoundAnyRawFNToRecFN.scala:159:42, :162:41]
wire [26:0] shiftedRoundMask = _shiftedRoundMask_T[27:1]; // @[RoundAnyRawFNToRecFN.scala:162:{41,53}]
wire [26:0] _roundPosMask_T = ~shiftedRoundMask; // @[RoundAnyRawFNToRecFN.scala:162:53, :163:28]
wire [26:0] roundPosMask = _roundPosMask_T & roundMask; // @[RoundAnyRawFNToRecFN.scala:159:42, :163:{28,46}]
wire [26:0] _roundPosBit_T = adjustedSig & roundPosMask; // @[RoundAnyRawFNToRecFN.scala:114:22, :163:46, :164:40]
wire roundPosBit = |_roundPosBit_T; // @[RoundAnyRawFNToRecFN.scala:164:{40,56}]
wire [26:0] _anyRoundExtra_T = adjustedSig & shiftedRoundMask; // @[RoundAnyRawFNToRecFN.scala:114:22, :162:53, :165:42]
wire anyRoundExtra = |_anyRoundExtra_T; // @[RoundAnyRawFNToRecFN.scala:165:{42,62}]
wire anyRound = roundPosBit | anyRoundExtra; // @[RoundAnyRawFNToRecFN.scala:164:56, :165:62, :166:36]
wire _GEN = roundingMode_near_even | roundingMode_near_maxMag; // @[RoundAnyRawFNToRecFN.scala:90:53, :94:53, :169:38]
wire _roundIncr_T; // @[RoundAnyRawFNToRecFN.scala:169:38]
assign _roundIncr_T = _GEN; // @[RoundAnyRawFNToRecFN.scala:169:38]
wire _unboundedRange_roundIncr_T; // @[RoundAnyRawFNToRecFN.scala:207:38]
assign _unboundedRange_roundIncr_T = _GEN; // @[RoundAnyRawFNToRecFN.scala:169:38, :207:38]
wire _overflow_roundMagUp_T; // @[RoundAnyRawFNToRecFN.scala:243:32]
assign _overflow_roundMagUp_T = _GEN; // @[RoundAnyRawFNToRecFN.scala:169:38, :243:32]
wire _roundIncr_T_1 = _roundIncr_T & roundPosBit; // @[RoundAnyRawFNToRecFN.scala:164:56, :169:{38,67}]
wire _roundIncr_T_2 = roundMagUp & anyRound; // @[RoundAnyRawFNToRecFN.scala:98:42, :166:36, :171:29]
wire roundIncr = _roundIncr_T_1 | _roundIncr_T_2; // @[RoundAnyRawFNToRecFN.scala:169:67, :170:31, :171:29]
wire [26:0] _roundedSig_T = adjustedSig | roundMask; // @[RoundAnyRawFNToRecFN.scala:114:22, :159:42, :174:32]
wire [24:0] _roundedSig_T_1 = _roundedSig_T[26:2]; // @[RoundAnyRawFNToRecFN.scala:174:{32,44}]
wire [25:0] _roundedSig_T_2 = {1'h0, _roundedSig_T_1} + 26'h1; // @[RoundAnyRawFNToRecFN.scala:174:{44,49}]
wire _roundedSig_T_3 = roundingMode_near_even & roundPosBit; // @[RoundAnyRawFNToRecFN.scala:90:53, :164:56, :175:49]
wire _roundedSig_T_4 = ~anyRoundExtra; // @[RoundAnyRawFNToRecFN.scala:165:62, :176:30]
wire _roundedSig_T_5 = _roundedSig_T_3 & _roundedSig_T_4; // @[RoundAnyRawFNToRecFN.scala:175:{49,64}, :176:30]
wire [25:0] _roundedSig_T_6 = roundMask[26:1]; // @[RoundAnyRawFNToRecFN.scala:159:42, :177:35]
wire [25:0] _roundedSig_T_7 = _roundedSig_T_5 ? _roundedSig_T_6 : 26'h0; // @[RoundAnyRawFNToRecFN.scala:175:{25,64}, :177:35]
wire [25:0] _roundedSig_T_8 = ~_roundedSig_T_7; // @[RoundAnyRawFNToRecFN.scala:175:{21,25}]
wire [25:0] _roundedSig_T_9 = _roundedSig_T_2 & _roundedSig_T_8; // @[RoundAnyRawFNToRecFN.scala:174:{49,57}, :175:21]
wire [26:0] _roundedSig_T_10 = ~roundMask; // @[RoundAnyRawFNToRecFN.scala:159:42, :180:32]
wire [26:0] _roundedSig_T_11 = adjustedSig & _roundedSig_T_10; // @[RoundAnyRawFNToRecFN.scala:114:22, :180:{30,32}]
wire [24:0] _roundedSig_T_12 = _roundedSig_T_11[26:2]; // @[RoundAnyRawFNToRecFN.scala:180:{30,43}]
wire _roundedSig_T_13 = roundingMode_odd & anyRound; // @[RoundAnyRawFNToRecFN.scala:95:53, :166:36, :181:42]
wire [25:0] _roundedSig_T_14 = roundPosMask[26:1]; // @[RoundAnyRawFNToRecFN.scala:163:46, :181:67]
wire [25:0] _roundedSig_T_15 = _roundedSig_T_13 ? _roundedSig_T_14 : 26'h0; // @[RoundAnyRawFNToRecFN.scala:181:{24,42,67}]
wire [25:0] _roundedSig_T_16 = {1'h0, _roundedSig_T_12} | _roundedSig_T_15; // @[RoundAnyRawFNToRecFN.scala:180:{43,47}, :181:24]
wire [25:0] roundedSig = roundIncr ? _roundedSig_T_9 : _roundedSig_T_16; // @[RoundAnyRawFNToRecFN.scala:170:31, :173:16, :174:57, :180:47]
wire [1:0] _sRoundedExp_T = roundedSig[25:24]; // @[RoundAnyRawFNToRecFN.scala:173:16, :185:54]
wire [2:0] _sRoundedExp_T_1 = {1'h0, _sRoundedExp_T}; // @[RoundAnyRawFNToRecFN.scala:185:{54,76}]
wire [10:0] sRoundedExp = {io_in_sExp_0[9], io_in_sExp_0} + {{8{_sRoundedExp_T_1[2]}}, _sRoundedExp_T_1}; // @[RoundAnyRawFNToRecFN.scala:48:5, :185:{40,76}]
assign _common_expOut_T = sRoundedExp[8:0]; // @[RoundAnyRawFNToRecFN.scala:185:40, :187:37]
assign common_expOut = _common_expOut_T; // @[RoundAnyRawFNToRecFN.scala:122:31, :187:37]
wire [22:0] _common_fractOut_T = roundedSig[23:1]; // @[RoundAnyRawFNToRecFN.scala:173:16, :190:27]
wire [22:0] _common_fractOut_T_1 = roundedSig[22:0]; // @[RoundAnyRawFNToRecFN.scala:173:16, :191:27]
assign _common_fractOut_T_2 = doShiftSigDown1 ? _common_fractOut_T : _common_fractOut_T_1; // @[RoundAnyRawFNToRecFN.scala:120:57, :189:16, :190:27, :191:27]
assign common_fractOut = _common_fractOut_T_2; // @[RoundAnyRawFNToRecFN.scala:123:31, :189:16]
wire [3:0] _common_overflow_T = sRoundedExp[10:7]; // @[RoundAnyRawFNToRecFN.scala:185:40, :196:30]
assign _common_overflow_T_1 = $signed(_common_overflow_T) > 4'sh2; // @[RoundAnyRawFNToRecFN.scala:196:{30,50}]
assign common_overflow = _common_overflow_T_1; // @[RoundAnyRawFNToRecFN.scala:124:37, :196:50]
assign _common_totalUnderflow_T = $signed(sRoundedExp) < 11'sh6B; // @[RoundAnyRawFNToRecFN.scala:185:40, :200:31]
assign common_totalUnderflow = _common_totalUnderflow_T; // @[RoundAnyRawFNToRecFN.scala:125:37, :200:31]
wire _unboundedRange_roundPosBit_T = adjustedSig[2]; // @[RoundAnyRawFNToRecFN.scala:114:22, :203:45]
wire _unboundedRange_anyRound_T = adjustedSig[2]; // @[RoundAnyRawFNToRecFN.scala:114:22, :203:45, :205:44]
wire _unboundedRange_roundPosBit_T_1 = adjustedSig[1]; // @[RoundAnyRawFNToRecFN.scala:114:22, :203:61]
wire unboundedRange_roundPosBit = doShiftSigDown1 ? _unboundedRange_roundPosBit_T : _unboundedRange_roundPosBit_T_1; // @[RoundAnyRawFNToRecFN.scala:120:57, :203:{16,45,61}]
wire _unboundedRange_anyRound_T_1 = doShiftSigDown1 & _unboundedRange_anyRound_T; // @[RoundAnyRawFNToRecFN.scala:120:57, :205:{30,44}]
wire [1:0] _unboundedRange_anyRound_T_2 = adjustedSig[1:0]; // @[RoundAnyRawFNToRecFN.scala:114:22, :205:63]
wire _unboundedRange_anyRound_T_3 = |_unboundedRange_anyRound_T_2; // @[RoundAnyRawFNToRecFN.scala:205:{63,70}]
wire unboundedRange_anyRound = _unboundedRange_anyRound_T_1 | _unboundedRange_anyRound_T_3; // @[RoundAnyRawFNToRecFN.scala:205:{30,49,70}]
wire _unboundedRange_roundIncr_T_1 = _unboundedRange_roundIncr_T & unboundedRange_roundPosBit; // @[RoundAnyRawFNToRecFN.scala:203:16, :207:{38,67}]
wire _unboundedRange_roundIncr_T_2 = roundMagUp & unboundedRange_anyRound; // @[RoundAnyRawFNToRecFN.scala:98:42, :205:49, :209:29]
wire unboundedRange_roundIncr = _unboundedRange_roundIncr_T_1 | _unboundedRange_roundIncr_T_2; // @[RoundAnyRawFNToRecFN.scala:207:67, :208:46, :209:29]
wire _roundCarry_T = roundedSig[25]; // @[RoundAnyRawFNToRecFN.scala:173:16, :212:27]
wire _roundCarry_T_1 = roundedSig[24]; // @[RoundAnyRawFNToRecFN.scala:173:16, :213:27]
wire roundCarry = doShiftSigDown1 ? _roundCarry_T : _roundCarry_T_1; // @[RoundAnyRawFNToRecFN.scala:120:57, :211:16, :212:27, :213:27]
wire [1:0] _common_underflow_T = io_in_sExp_0[9:8]; // @[RoundAnyRawFNToRecFN.scala:48:5, :220:49]
wire _common_underflow_T_1 = _common_underflow_T != 2'h1; // @[RoundAnyRawFNToRecFN.scala:220:{49,64}]
wire _common_underflow_T_2 = anyRound & _common_underflow_T_1; // @[RoundAnyRawFNToRecFN.scala:166:36, :220:{32,64}]
wire _common_underflow_T_3 = roundMask[3]; // @[RoundAnyRawFNToRecFN.scala:159:42, :221:57]
wire _common_underflow_T_9 = roundMask[3]; // @[RoundAnyRawFNToRecFN.scala:159:42, :221:57, :225:49]
wire _common_underflow_T_4 = roundMask[2]; // @[RoundAnyRawFNToRecFN.scala:159:42, :221:71]
wire _common_underflow_T_5 = doShiftSigDown1 ? _common_underflow_T_3 : _common_underflow_T_4; // @[RoundAnyRawFNToRecFN.scala:120:57, :221:{30,57,71}]
wire _common_underflow_T_6 = _common_underflow_T_2 & _common_underflow_T_5; // @[RoundAnyRawFNToRecFN.scala:220:{32,72}, :221:30]
wire _common_underflow_T_8 = roundMask[4]; // @[RoundAnyRawFNToRecFN.scala:159:42, :224:49]
wire _common_underflow_T_10 = doShiftSigDown1 ? _common_underflow_T_8 : _common_underflow_T_9; // @[RoundAnyRawFNToRecFN.scala:120:57, :223:39, :224:49, :225:49]
wire _common_underflow_T_11 = ~_common_underflow_T_10; // @[RoundAnyRawFNToRecFN.scala:223:{34,39}]
wire _common_underflow_T_12 = _common_underflow_T_11; // @[RoundAnyRawFNToRecFN.scala:222:77, :223:34]
wire _common_underflow_T_13 = _common_underflow_T_12 & roundCarry; // @[RoundAnyRawFNToRecFN.scala:211:16, :222:77, :226:38]
wire _common_underflow_T_14 = _common_underflow_T_13 & roundPosBit; // @[RoundAnyRawFNToRecFN.scala:164:56, :226:38, :227:45]
wire _common_underflow_T_15 = _common_underflow_T_14 & unboundedRange_roundIncr; // @[RoundAnyRawFNToRecFN.scala:208:46, :227:{45,60}]
wire _common_underflow_T_16 = ~_common_underflow_T_15; // @[RoundAnyRawFNToRecFN.scala:222:27, :227:60]
wire _common_underflow_T_17 = _common_underflow_T_6 & _common_underflow_T_16; // @[RoundAnyRawFNToRecFN.scala:220:72, :221:76, :222:27]
assign _common_underflow_T_18 = common_totalUnderflow | _common_underflow_T_17; // @[RoundAnyRawFNToRecFN.scala:125:37, :217:40, :221:76]
assign common_underflow = _common_underflow_T_18; // @[RoundAnyRawFNToRecFN.scala:126:37, :217:40]
assign _common_inexact_T = common_totalUnderflow | anyRound; // @[RoundAnyRawFNToRecFN.scala:125:37, :166:36, :230:49]
assign common_inexact = _common_inexact_T; // @[RoundAnyRawFNToRecFN.scala:127:37, :230:49]
wire isNaNOut = io_invalidExc_0 | io_in_isNaN_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :235:34]
wire notNaN_isSpecialInfOut = io_infiniteExc_0 | io_in_isInf_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :236:49]
wire _commonCase_T = ~isNaNOut; // @[RoundAnyRawFNToRecFN.scala:235:34, :237:22]
wire _commonCase_T_1 = ~notNaN_isSpecialInfOut; // @[RoundAnyRawFNToRecFN.scala:236:49, :237:36]
wire _commonCase_T_2 = _commonCase_T & _commonCase_T_1; // @[RoundAnyRawFNToRecFN.scala:237:{22,33,36}]
wire _commonCase_T_3 = ~io_in_isZero_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :237:64]
wire commonCase = _commonCase_T_2 & _commonCase_T_3; // @[RoundAnyRawFNToRecFN.scala:237:{33,61,64}]
wire overflow = commonCase & common_overflow; // @[RoundAnyRawFNToRecFN.scala:124:37, :237:61, :238:32]
wire underflow = commonCase & common_underflow; // @[RoundAnyRawFNToRecFN.scala:126:37, :237:61, :239:32]
wire _inexact_T = commonCase & common_inexact; // @[RoundAnyRawFNToRecFN.scala:127:37, :237:61, :240:43]
wire inexact = overflow | _inexact_T; // @[RoundAnyRawFNToRecFN.scala:238:32, :240:{28,43}]
wire overflow_roundMagUp = _overflow_roundMagUp_T | roundMagUp; // @[RoundAnyRawFNToRecFN.scala:98:42, :243:{32,60}]
wire _pegMinNonzeroMagOut_T = commonCase & common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:125:37, :237:61, :245:20]
wire _pegMinNonzeroMagOut_T_1 = roundMagUp | roundingMode_odd; // @[RoundAnyRawFNToRecFN.scala:95:53, :98:42, :245:60]
wire pegMinNonzeroMagOut = _pegMinNonzeroMagOut_T & _pegMinNonzeroMagOut_T_1; // @[RoundAnyRawFNToRecFN.scala:245:{20,45,60}]
wire _pegMaxFiniteMagOut_T = ~overflow_roundMagUp; // @[RoundAnyRawFNToRecFN.scala:243:60, :246:42]
wire pegMaxFiniteMagOut = overflow & _pegMaxFiniteMagOut_T; // @[RoundAnyRawFNToRecFN.scala:238:32, :246:{39,42}]
wire _notNaN_isInfOut_T = overflow & overflow_roundMagUp; // @[RoundAnyRawFNToRecFN.scala:238:32, :243:60, :248:45]
wire notNaN_isInfOut = notNaN_isSpecialInfOut | _notNaN_isInfOut_T; // @[RoundAnyRawFNToRecFN.scala:236:49, :248:{32,45}]
wire signOut = ~isNaNOut & io_in_sign_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :235:34, :250:22]
wire _expOut_T = io_in_isZero_0 | common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:48:5, :125:37, :253:32]
wire [8:0] _expOut_T_1 = _expOut_T ? 9'h1C0 : 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:{18,32}]
wire [8:0] _expOut_T_2 = ~_expOut_T_1; // @[RoundAnyRawFNToRecFN.scala:253:{14,18}]
wire [8:0] _expOut_T_3 = common_expOut & _expOut_T_2; // @[RoundAnyRawFNToRecFN.scala:122:31, :252:24, :253:14]
wire [8:0] _expOut_T_5 = pegMinNonzeroMagOut ? 9'h194 : 9'h0; // @[RoundAnyRawFNToRecFN.scala:245:45, :257:18]
wire [8:0] _expOut_T_6 = ~_expOut_T_5; // @[RoundAnyRawFNToRecFN.scala:257:{14,18}]
wire [8:0] _expOut_T_7 = _expOut_T_3 & _expOut_T_6; // @[RoundAnyRawFNToRecFN.scala:252:24, :256:17, :257:14]
wire [8:0] _expOut_T_8 = {1'h0, pegMaxFiniteMagOut, 7'h0}; // @[RoundAnyRawFNToRecFN.scala:246:39, :261:18]
wire [8:0] _expOut_T_9 = ~_expOut_T_8; // @[RoundAnyRawFNToRecFN.scala:261:{14,18}]
wire [8:0] _expOut_T_10 = _expOut_T_7 & _expOut_T_9; // @[RoundAnyRawFNToRecFN.scala:256:17, :260:17, :261:14]
wire [8:0] _expOut_T_11 = {2'h0, notNaN_isInfOut, 6'h0}; // @[RoundAnyRawFNToRecFN.scala:248:32, :265:18]
wire [8:0] _expOut_T_12 = ~_expOut_T_11; // @[RoundAnyRawFNToRecFN.scala:265:{14,18}]
wire [8:0] _expOut_T_13 = _expOut_T_10 & _expOut_T_12; // @[RoundAnyRawFNToRecFN.scala:260:17, :264:17, :265:14]
wire [8:0] _expOut_T_14 = pegMinNonzeroMagOut ? 9'h6B : 9'h0; // @[RoundAnyRawFNToRecFN.scala:245:45, :269:16]
wire [8:0] _expOut_T_15 = _expOut_T_13 | _expOut_T_14; // @[RoundAnyRawFNToRecFN.scala:264:17, :268:18, :269:16]
wire [8:0] _expOut_T_16 = pegMaxFiniteMagOut ? 9'h17F : 9'h0; // @[RoundAnyRawFNToRecFN.scala:246:39, :273:16]
wire [8:0] _expOut_T_17 = _expOut_T_15 | _expOut_T_16; // @[RoundAnyRawFNToRecFN.scala:268:18, :272:15, :273:16]
wire [8:0] _expOut_T_18 = notNaN_isInfOut ? 9'h180 : 9'h0; // @[RoundAnyRawFNToRecFN.scala:248:32, :277:16]
wire [8:0] _expOut_T_19 = _expOut_T_17 | _expOut_T_18; // @[RoundAnyRawFNToRecFN.scala:272:15, :276:15, :277:16]
wire [8:0] _expOut_T_20 = isNaNOut ? 9'h1C0 : 9'h0; // @[RoundAnyRawFNToRecFN.scala:235:34, :278:16]
wire [8:0] expOut = _expOut_T_19 | _expOut_T_20; // @[RoundAnyRawFNToRecFN.scala:276:15, :277:73, :278:16]
wire _fractOut_T = isNaNOut | io_in_isZero_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :235:34, :280:22]
wire _fractOut_T_1 = _fractOut_T | common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:125:37, :280:{22,38}]
wire [22:0] _fractOut_T_2 = {isNaNOut, 22'h0}; // @[RoundAnyRawFNToRecFN.scala:235:34, :281:16]
wire [22:0] _fractOut_T_3 = _fractOut_T_1 ? _fractOut_T_2 : common_fractOut; // @[RoundAnyRawFNToRecFN.scala:123:31, :280:{12,38}, :281:16]
wire [22:0] _fractOut_T_4 = {23{pegMaxFiniteMagOut}}; // @[RoundAnyRawFNToRecFN.scala:246:39, :284:13]
wire [22:0] fractOut = _fractOut_T_3 | _fractOut_T_4; // @[RoundAnyRawFNToRecFN.scala:280:12, :283:11, :284:13]
wire [9:0] _io_out_T = {signOut, expOut}; // @[RoundAnyRawFNToRecFN.scala:250:22, :277:73, :286:23]
assign _io_out_T_1 = {_io_out_T, fractOut}; // @[RoundAnyRawFNToRecFN.scala:283:11, :286:{23,33}]
assign io_out_0 = _io_out_T_1; // @[RoundAnyRawFNToRecFN.scala:48:5, :286:33]
wire [1:0] _io_exceptionFlags_T = {io_invalidExc_0, io_infiniteExc_0}; // @[RoundAnyRawFNToRecFN.scala:48:5, :288:23]
wire [2:0] _io_exceptionFlags_T_1 = {_io_exceptionFlags_T, overflow}; // @[RoundAnyRawFNToRecFN.scala:238:32, :288:{23,41}]
wire [3:0] _io_exceptionFlags_T_2 = {_io_exceptionFlags_T_1, underflow}; // @[RoundAnyRawFNToRecFN.scala:239:32, :288:{41,53}]
assign _io_exceptionFlags_T_3 = {_io_exceptionFlags_T_2, inexact}; // @[RoundAnyRawFNToRecFN.scala:240:28, :288:{53,66}]
assign io_exceptionFlags_0 = _io_exceptionFlags_T_3; // @[RoundAnyRawFNToRecFN.scala:48:5, :288:66]
assign io_out = io_out_0; // @[RoundAnyRawFNToRecFN.scala:48:5]
assign io_exceptionFlags = io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:48:5]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File ClockDomain.scala:
package freechips.rocketchip.prci
import chisel3._
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy.lazymodule._
abstract class Domain(implicit p: Parameters) extends LazyModule with HasDomainCrossing
{
def clockBundle: ClockBundle
lazy val module = new Impl
class Impl extends LazyRawModuleImp(this) {
childClock := clockBundle.clock
childReset := clockBundle.reset
override def provideImplicitClockToLazyChildren = true
// these are just for backwards compatibility with external devices
// that were manually wiring themselves to the domain's clock/reset input:
val clock = IO(Output(chiselTypeOf(clockBundle.clock)))
val reset = IO(Output(chiselTypeOf(clockBundle.reset)))
clock := clockBundle.clock
reset := clockBundle.reset
}
}
abstract class ClockDomain(implicit p: Parameters) extends Domain with HasClockDomainCrossing
class ClockSinkDomain(val clockSinkParams: ClockSinkParameters)(implicit p: Parameters) extends ClockDomain
{
def this(take: Option[ClockParameters] = None, name: Option[String] = None)(implicit p: Parameters) = this(ClockSinkParameters(take = take, name = name))
val clockNode = ClockSinkNode(Seq(clockSinkParams))
def clockBundle = clockNode.in.head._1
override lazy val desiredName = (clockSinkParams.name.toSeq :+ "ClockSinkDomain").mkString
}
class ClockSourceDomain(val clockSourceParams: ClockSourceParameters)(implicit p: Parameters) extends ClockDomain
{
def this(give: Option[ClockParameters] = None, name: Option[String] = None)(implicit p: Parameters) = this(ClockSourceParameters(give = give, name = name))
val clockNode = ClockSourceNode(Seq(clockSourceParams))
def clockBundle = clockNode.out.head._1
override lazy val desiredName = (clockSourceParams.name.toSeq :+ "ClockSourceDomain").mkString
}
abstract class ResetDomain(implicit p: Parameters) extends Domain with HasResetDomainCrossing
File LazyModuleImp.scala:
package org.chipsalliance.diplomacy.lazymodule
import chisel3.{withClockAndReset, Module, RawModule, Reset, _}
import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo}
import firrtl.passes.InlineAnnotation
import org.chipsalliance.cde.config.Parameters
import org.chipsalliance.diplomacy.nodes.Dangle
import scala.collection.immutable.SortedMap
/** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]].
*
* This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy.
*/
sealed trait LazyModuleImpLike extends RawModule {
/** [[LazyModule]] that contains this instance. */
val wrapper: LazyModule
/** IOs that will be automatically "punched" for this instance. */
val auto: AutoBundle
/** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */
protected[diplomacy] val dangles: Seq[Dangle]
// [[wrapper.module]] had better not be accessed while LazyModules are still being built!
require(
LazyModule.scope.isEmpty,
s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}"
)
/** Set module name. Defaults to the containing LazyModule's desiredName. */
override def desiredName: String = wrapper.desiredName
suggestName(wrapper.suggestedName)
/** [[Parameters]] for chisel [[Module]]s. */
implicit val p: Parameters = wrapper.p
/** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and
* submodules.
*/
protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = {
// 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]],
// 2. return [[Dangle]]s from each module.
val childDangles = wrapper.children.reverse.flatMap { c =>
implicit val sourceInfo: SourceInfo = c.info
c.cloneProto.map { cp =>
// If the child is a clone, then recursively set cloneProto of its children as well
def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = {
require(bases.size == clones.size)
(bases.zip(clones)).map { case (l, r) =>
require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}")
l.cloneProto = Some(r)
assignCloneProtos(l.children, r.children)
}
}
assignCloneProtos(c.children, cp.children)
// Clone the child module as a record, and get its [[AutoBundle]]
val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName)
val clonedAuto = clone("auto").asInstanceOf[AutoBundle]
// Get the empty [[Dangle]]'s of the cloned child
val rawDangles = c.cloneDangles()
require(rawDangles.size == clonedAuto.elements.size)
// Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s
val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) }
dangles
}.getOrElse {
// For non-clones, instantiate the child module
val mod = try {
Module(c.module)
} catch {
case e: ChiselException => {
println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}")
throw e
}
}
mod.dangles
}
}
// Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]].
// This will result in a sequence of [[Dangle]] from these [[BaseNode]]s.
val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate())
// Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]]
val allDangles = nodeDangles ++ childDangles
// Group [[allDangles]] by their [[source]].
val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*)
// For each [[source]] set of [[Dangle]]s of size 2, ensure that these
// can be connected as a source-sink pair (have opposite flipped value).
// Make the connection and mark them as [[done]].
val done = Set() ++ pairing.values.filter(_.size == 2).map {
case Seq(a, b) =>
require(a.flipped != b.flipped)
// @todo <> in chisel3 makes directionless connection.
if (a.flipped) {
a.data <> b.data
} else {
b.data <> a.data
}
a.source
case _ => None
}
// Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module.
val forward = allDangles.filter(d => !done(d.source))
// Generate [[AutoBundle]] IO from [[forward]].
val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*))
// Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]]
val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) =>
if (d.flipped) {
d.data <> io
} else {
io <> d.data
}
d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name)
}
// Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]].
wrapper.inModuleBody.reverse.foreach {
_()
}
if (wrapper.shouldBeInlined) {
chisel3.experimental.annotate(new ChiselAnnotation {
def toFirrtl = InlineAnnotation(toNamed)
})
}
// Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]].
(auto, dangles)
}
}
/** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike {
/** Instantiate hardware of this `Module`. */
val (auto, dangles) = instantiate()
}
/** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike {
// These wires are the default clock+reset for all LazyModule children.
// It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the
// [[LazyRawModuleImp]] children.
// Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly.
/** drive clock explicitly. */
val childClock: Clock = Wire(Clock())
/** drive reset explicitly. */
val childReset: Reset = Wire(Reset())
// the default is that these are disabled
childClock := false.B.asClock
childReset := chisel3.DontCare
def provideImplicitClockToLazyChildren: Boolean = false
val (auto, dangles) =
if (provideImplicitClockToLazyChildren) {
withClockAndReset(childClock, childReset) { instantiate() }
} else {
instantiate()
}
}
File NoC.scala:
package constellation.noc
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.{Field, Parameters}
import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp, BundleBridgeSink, InModuleBody}
import freechips.rocketchip.util.ElaborationArtefacts
import freechips.rocketchip.prci._
import constellation.router._
import constellation.channel._
import constellation.routing.{RoutingRelation, ChannelRoutingInfo}
import constellation.topology.{PhysicalTopology, UnidirectionalLine}
class NoCTerminalIO(
val ingressParams: Seq[IngressChannelParams],
val egressParams: Seq[EgressChannelParams])(implicit val p: Parameters) extends Bundle {
val ingress = MixedVec(ingressParams.map { u => Flipped(new IngressChannel(u)) })
val egress = MixedVec(egressParams.map { u => new EgressChannel(u) })
}
class NoC(nocParams: NoCParams)(implicit p: Parameters) extends LazyModule {
override def shouldBeInlined = nocParams.inlineNoC
val internalParams = InternalNoCParams(nocParams)
val allChannelParams = internalParams.channelParams
val allIngressParams = internalParams.ingressParams
val allEgressParams = internalParams.egressParams
val allRouterParams = internalParams.routerParams
val iP = p.alterPartial({ case InternalNoCKey => internalParams })
val nNodes = nocParams.topology.nNodes
val nocName = nocParams.nocName
val skipValidationChecks = nocParams.skipValidationChecks
val clockSourceNodes = Seq.tabulate(nNodes) { i => ClockSourceNode(Seq(ClockSourceParameters())) }
val router_sink_domains = Seq.tabulate(nNodes) { i =>
val router_sink_domain = LazyModule(new ClockSinkDomain(ClockSinkParameters(
name = Some(s"${nocName}_router_$i")
)))
router_sink_domain.clockNode := clockSourceNodes(i)
router_sink_domain
}
val routers = Seq.tabulate(nNodes) { i => router_sink_domains(i) {
val inParams = allChannelParams.filter(_.destId == i).map(
_.copy(payloadBits=allRouterParams(i).user.payloadBits)
)
val outParams = allChannelParams.filter(_.srcId == i).map(
_.copy(payloadBits=allRouterParams(i).user.payloadBits)
)
val ingressParams = allIngressParams.filter(_.destId == i).map(
_.copy(payloadBits=allRouterParams(i).user.payloadBits)
)
val egressParams = allEgressParams.filter(_.srcId == i).map(
_.copy(payloadBits=allRouterParams(i).user.payloadBits)
)
val noIn = inParams.size + ingressParams.size == 0
val noOut = outParams.size + egressParams.size == 0
if (noIn || noOut) {
println(s"Constellation WARNING: $nocName router $i seems to be unused, it will not be generated")
None
} else {
Some(LazyModule(new Router(
routerParams = allRouterParams(i),
preDiplomaticInParams = inParams,
preDiplomaticIngressParams = ingressParams,
outDests = outParams.map(_.destId),
egressIds = egressParams.map(_.egressId)
)(iP)))
}
}}.flatten
val ingressNodes = allIngressParams.map { u => IngressChannelSourceNode(u.destId) }
val egressNodes = allEgressParams.map { u => EgressChannelDestNode(u) }
// Generate channels between routers diplomatically
Seq.tabulate(nNodes, nNodes) { case (i, j) => if (i != j) {
val routerI = routers.find(_.nodeId == i)
val routerJ = routers.find(_.nodeId == j)
if (routerI.isDefined && routerJ.isDefined) {
val sourceNodes: Seq[ChannelSourceNode] = routerI.get.sourceNodes.filter(_.destId == j)
val destNodes: Seq[ChannelDestNode] = routerJ.get.destNodes.filter(_.destParams.srcId == i)
require (sourceNodes.size == destNodes.size)
(sourceNodes zip destNodes).foreach { case (src, dst) =>
val channelParam = allChannelParams.find(c => c.srcId == i && c.destId == j).get
router_sink_domains(j) {
implicit val p: Parameters = iP
(dst
:= ChannelWidthWidget(routerJ.get.payloadBits, routerI.get.payloadBits)
:= channelParam.channelGen(p)(src)
)
}
}
}
}}
// Generate terminal channels diplomatically
routers.foreach { dst => router_sink_domains(dst.nodeId) {
implicit val p: Parameters = iP
dst.ingressNodes.foreach(n => {
val ingressId = n.destParams.ingressId
require(dst.payloadBits <= allIngressParams(ingressId).payloadBits)
(n
:= IngressWidthWidget(dst.payloadBits, allIngressParams(ingressId).payloadBits)
:= ingressNodes(ingressId)
)
})
dst.egressNodes.foreach(n => {
val egressId = n.egressId
require(dst.payloadBits <= allEgressParams(egressId).payloadBits)
(egressNodes(egressId)
:= EgressWidthWidget(allEgressParams(egressId).payloadBits, dst.payloadBits)
:= n
)
})
}}
val debugNodes = routers.map { r =>
val sink = BundleBridgeSink[DebugBundle]()
sink := r.debugNode
sink
}
val ctrlNodes = if (nocParams.hasCtrl) {
(0 until nNodes).map { i =>
routers.find(_.nodeId == i).map { r =>
val sink = BundleBridgeSink[RouterCtrlBundle]()
sink := r.ctrlNode.get
sink
}
}
} else {
Nil
}
println(s"Constellation: $nocName Finished parameter validation")
lazy val module = new Impl
class Impl extends LazyModuleImp(this) {
println(s"Constellation: $nocName Starting NoC RTL generation")
val io = IO(new NoCTerminalIO(allIngressParams, allEgressParams)(iP) {
val router_clocks = Vec(nNodes, Input(new ClockBundle(ClockBundleParameters())))
val router_ctrl = if (nocParams.hasCtrl) Vec(nNodes, new RouterCtrlBundle) else Nil
})
(io.ingress zip ingressNodes.map(_.out(0)._1)).foreach { case (l,r) => r <> l }
(io.egress zip egressNodes .map(_.in (0)._1)).foreach { case (l,r) => l <> r }
(io.router_clocks zip clockSourceNodes.map(_.out(0)._1)).foreach { case (l,r) => l <> r }
if (nocParams.hasCtrl) {
ctrlNodes.zipWithIndex.map { case (c,i) =>
if (c.isDefined) {
io.router_ctrl(i) <> c.get.in(0)._1
} else {
io.router_ctrl(i) <> DontCare
}
}
}
// TODO: These assume a single clock-domain across the entire noc
val debug_va_stall_ctr = RegInit(0.U(64.W))
val debug_sa_stall_ctr = RegInit(0.U(64.W))
val debug_any_stall_ctr = debug_va_stall_ctr + debug_sa_stall_ctr
debug_va_stall_ctr := debug_va_stall_ctr + debugNodes.map(_.in(0)._1.va_stall.reduce(_+_)).reduce(_+_)
debug_sa_stall_ctr := debug_sa_stall_ctr + debugNodes.map(_.in(0)._1.sa_stall.reduce(_+_)).reduce(_+_)
dontTouch(debug_va_stall_ctr)
dontTouch(debug_sa_stall_ctr)
dontTouch(debug_any_stall_ctr)
def prepend(s: String) = Seq(nocName, s).mkString(".")
ElaborationArtefacts.add(prepend("noc.graphml"), graphML)
val adjList = routers.map { r =>
val outs = r.outParams.map(o => s"${o.destId}").mkString(" ")
val egresses = r.egressParams.map(e => s"e${e.egressId}").mkString(" ")
val ingresses = r.ingressParams.map(i => s"i${i.ingressId} ${r.nodeId}")
(Seq(s"${r.nodeId} $outs $egresses") ++ ingresses).mkString("\n")
}.mkString("\n")
ElaborationArtefacts.add(prepend("noc.adjlist"), adjList)
val xys = routers.map(r => {
val n = r.nodeId
val ids = (Seq(r.nodeId.toString)
++ r.egressParams.map(e => s"e${e.egressId}")
++ r.ingressParams.map(i => s"i${i.ingressId}")
)
val plotter = nocParams.topology.plotter
val coords = (Seq(plotter.node(r.nodeId))
++ Seq.tabulate(r.egressParams.size ) { i => plotter. egress(i, r. egressParams.size, r.nodeId) }
++ Seq.tabulate(r.ingressParams.size) { i => plotter.ingress(i, r.ingressParams.size, r.nodeId) }
)
(ids zip coords).map { case (i, (x, y)) => s"$i $x $y" }.mkString("\n")
}).mkString("\n")
ElaborationArtefacts.add(prepend("noc.xy"), xys)
val edgeProps = routers.map { r =>
val outs = r.outParams.map { o =>
(Seq(s"${r.nodeId} ${o.destId}") ++ (if (o.possibleFlows.size == 0) Some("unused") else None))
.mkString(" ")
}
val egresses = r.egressParams.map { e =>
(Seq(s"${r.nodeId} e${e.egressId}") ++ (if (e.possibleFlows.size == 0) Some("unused") else None))
.mkString(" ")
}
val ingresses = r.ingressParams.map { i =>
(Seq(s"i${i.ingressId} ${r.nodeId}") ++ (if (i.possibleFlows.size == 0) Some("unused") else None))
.mkString(" ")
}
(outs ++ egresses ++ ingresses).mkString("\n")
}.mkString("\n")
ElaborationArtefacts.add(prepend("noc.edgeprops"), edgeProps)
println(s"Constellation: $nocName Finished NoC RTL generation")
}
}
| module TLNoC_1_router_8ClockSinkDomain( // @[ClockDomain.scala:14:9]
output [2:0] auto_routers_debug_out_va_stall_0, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_routers_debug_out_va_stall_2, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_routers_debug_out_sa_stall_0, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_routers_debug_out_sa_stall_2, // @[LazyModuleImp.scala:107:25]
input auto_routers_egress_nodes_out_2_flit_ready, // @[LazyModuleImp.scala:107:25]
output auto_routers_egress_nodes_out_2_flit_valid, // @[LazyModuleImp.scala:107:25]
output auto_routers_egress_nodes_out_2_flit_bits_head, // @[LazyModuleImp.scala:107:25]
output auto_routers_egress_nodes_out_2_flit_bits_tail, // @[LazyModuleImp.scala:107:25]
input auto_routers_egress_nodes_out_1_flit_ready, // @[LazyModuleImp.scala:107:25]
output auto_routers_egress_nodes_out_1_flit_valid, // @[LazyModuleImp.scala:107:25]
output auto_routers_egress_nodes_out_1_flit_bits_head, // @[LazyModuleImp.scala:107:25]
output auto_routers_egress_nodes_out_1_flit_bits_tail, // @[LazyModuleImp.scala:107:25]
input auto_routers_egress_nodes_out_0_flit_ready, // @[LazyModuleImp.scala:107:25]
output auto_routers_egress_nodes_out_0_flit_valid, // @[LazyModuleImp.scala:107:25]
output auto_routers_egress_nodes_out_0_flit_bits_head, // @[LazyModuleImp.scala:107:25]
output auto_routers_egress_nodes_out_0_flit_bits_tail, // @[LazyModuleImp.scala:107:25]
output [72:0] auto_routers_egress_nodes_out_0_flit_bits_payload, // @[LazyModuleImp.scala:107:25]
output auto_routers_ingress_nodes_in_1_flit_ready, // @[LazyModuleImp.scala:107:25]
input auto_routers_ingress_nodes_in_1_flit_valid, // @[LazyModuleImp.scala:107:25]
input auto_routers_ingress_nodes_in_1_flit_bits_head, // @[LazyModuleImp.scala:107:25]
input auto_routers_ingress_nodes_in_1_flit_bits_tail, // @[LazyModuleImp.scala:107:25]
input [72:0] auto_routers_ingress_nodes_in_1_flit_bits_payload, // @[LazyModuleImp.scala:107:25]
output auto_routers_source_nodes_out_flit_0_valid, // @[LazyModuleImp.scala:107:25]
output auto_routers_source_nodes_out_flit_0_bits_head, // @[LazyModuleImp.scala:107:25]
output auto_routers_source_nodes_out_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25]
output [72:0] auto_routers_source_nodes_out_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_routers_source_nodes_out_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25]
output [4:0] auto_routers_source_nodes_out_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_routers_source_nodes_out_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25]
output [4:0] auto_routers_source_nodes_out_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_routers_source_nodes_out_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_routers_source_nodes_out_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25]
input [4:0] auto_routers_source_nodes_out_credit_return, // @[LazyModuleImp.scala:107:25]
input [4:0] auto_routers_source_nodes_out_vc_free, // @[LazyModuleImp.scala:107:25]
input auto_routers_dest_nodes_in_flit_0_valid, // @[LazyModuleImp.scala:107:25]
input auto_routers_dest_nodes_in_flit_0_bits_head, // @[LazyModuleImp.scala:107:25]
input auto_routers_dest_nodes_in_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25]
input [72:0] auto_routers_dest_nodes_in_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_routers_dest_nodes_in_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25]
input [4:0] auto_routers_dest_nodes_in_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_routers_dest_nodes_in_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25]
input [4:0] auto_routers_dest_nodes_in_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_routers_dest_nodes_in_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_routers_dest_nodes_in_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25]
output [4:0] auto_routers_dest_nodes_in_credit_return, // @[LazyModuleImp.scala:107:25]
output [4:0] auto_routers_dest_nodes_in_vc_free, // @[LazyModuleImp.scala:107:25]
input auto_clock_in_clock, // @[LazyModuleImp.scala:107:25]
input auto_clock_in_reset // @[LazyModuleImp.scala:107:25]
);
Router_37 routers ( // @[NoC.scala:67:22]
.clock (auto_clock_in_clock),
.reset (auto_clock_in_reset),
.auto_debug_out_va_stall_0 (auto_routers_debug_out_va_stall_0),
.auto_debug_out_va_stall_2 (auto_routers_debug_out_va_stall_2),
.auto_debug_out_sa_stall_0 (auto_routers_debug_out_sa_stall_0),
.auto_debug_out_sa_stall_2 (auto_routers_debug_out_sa_stall_2),
.auto_egress_nodes_out_2_flit_ready (auto_routers_egress_nodes_out_2_flit_ready),
.auto_egress_nodes_out_2_flit_valid (auto_routers_egress_nodes_out_2_flit_valid),
.auto_egress_nodes_out_2_flit_bits_head (auto_routers_egress_nodes_out_2_flit_bits_head),
.auto_egress_nodes_out_2_flit_bits_tail (auto_routers_egress_nodes_out_2_flit_bits_tail),
.auto_egress_nodes_out_1_flit_ready (auto_routers_egress_nodes_out_1_flit_ready),
.auto_egress_nodes_out_1_flit_valid (auto_routers_egress_nodes_out_1_flit_valid),
.auto_egress_nodes_out_1_flit_bits_head (auto_routers_egress_nodes_out_1_flit_bits_head),
.auto_egress_nodes_out_1_flit_bits_tail (auto_routers_egress_nodes_out_1_flit_bits_tail),
.auto_egress_nodes_out_0_flit_ready (auto_routers_egress_nodes_out_0_flit_ready),
.auto_egress_nodes_out_0_flit_valid (auto_routers_egress_nodes_out_0_flit_valid),
.auto_egress_nodes_out_0_flit_bits_head (auto_routers_egress_nodes_out_0_flit_bits_head),
.auto_egress_nodes_out_0_flit_bits_tail (auto_routers_egress_nodes_out_0_flit_bits_tail),
.auto_egress_nodes_out_0_flit_bits_payload (auto_routers_egress_nodes_out_0_flit_bits_payload),
.auto_ingress_nodes_in_1_flit_ready (auto_routers_ingress_nodes_in_1_flit_ready),
.auto_ingress_nodes_in_1_flit_valid (auto_routers_ingress_nodes_in_1_flit_valid),
.auto_ingress_nodes_in_1_flit_bits_head (auto_routers_ingress_nodes_in_1_flit_bits_head),
.auto_ingress_nodes_in_1_flit_bits_tail (auto_routers_ingress_nodes_in_1_flit_bits_tail),
.auto_ingress_nodes_in_1_flit_bits_payload (auto_routers_ingress_nodes_in_1_flit_bits_payload),
.auto_source_nodes_out_flit_0_valid (auto_routers_source_nodes_out_flit_0_valid),
.auto_source_nodes_out_flit_0_bits_head (auto_routers_source_nodes_out_flit_0_bits_head),
.auto_source_nodes_out_flit_0_bits_tail (auto_routers_source_nodes_out_flit_0_bits_tail),
.auto_source_nodes_out_flit_0_bits_payload (auto_routers_source_nodes_out_flit_0_bits_payload),
.auto_source_nodes_out_flit_0_bits_flow_vnet_id (auto_routers_source_nodes_out_flit_0_bits_flow_vnet_id),
.auto_source_nodes_out_flit_0_bits_flow_ingress_node (auto_routers_source_nodes_out_flit_0_bits_flow_ingress_node),
.auto_source_nodes_out_flit_0_bits_flow_ingress_node_id (auto_routers_source_nodes_out_flit_0_bits_flow_ingress_node_id),
.auto_source_nodes_out_flit_0_bits_flow_egress_node (auto_routers_source_nodes_out_flit_0_bits_flow_egress_node),
.auto_source_nodes_out_flit_0_bits_flow_egress_node_id (auto_routers_source_nodes_out_flit_0_bits_flow_egress_node_id),
.auto_source_nodes_out_flit_0_bits_virt_channel_id (auto_routers_source_nodes_out_flit_0_bits_virt_channel_id),
.auto_source_nodes_out_credit_return (auto_routers_source_nodes_out_credit_return),
.auto_source_nodes_out_vc_free (auto_routers_source_nodes_out_vc_free),
.auto_dest_nodes_in_flit_0_valid (auto_routers_dest_nodes_in_flit_0_valid),
.auto_dest_nodes_in_flit_0_bits_head (auto_routers_dest_nodes_in_flit_0_bits_head),
.auto_dest_nodes_in_flit_0_bits_tail (auto_routers_dest_nodes_in_flit_0_bits_tail),
.auto_dest_nodes_in_flit_0_bits_payload (auto_routers_dest_nodes_in_flit_0_bits_payload),
.auto_dest_nodes_in_flit_0_bits_flow_vnet_id (auto_routers_dest_nodes_in_flit_0_bits_flow_vnet_id),
.auto_dest_nodes_in_flit_0_bits_flow_ingress_node (auto_routers_dest_nodes_in_flit_0_bits_flow_ingress_node),
.auto_dest_nodes_in_flit_0_bits_flow_ingress_node_id (auto_routers_dest_nodes_in_flit_0_bits_flow_ingress_node_id),
.auto_dest_nodes_in_flit_0_bits_flow_egress_node (auto_routers_dest_nodes_in_flit_0_bits_flow_egress_node),
.auto_dest_nodes_in_flit_0_bits_flow_egress_node_id (auto_routers_dest_nodes_in_flit_0_bits_flow_egress_node_id),
.auto_dest_nodes_in_flit_0_bits_virt_channel_id (auto_routers_dest_nodes_in_flit_0_bits_virt_channel_id),
.auto_dest_nodes_in_credit_return (auto_routers_dest_nodes_in_credit_return),
.auto_dest_nodes_in_vc_free (auto_routers_dest_nodes_in_vc_free)
); // @[NoC.scala:67:22]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File Monitor.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceLine
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import freechips.rocketchip.diplomacy.EnableMonitors
import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode}
import freechips.rocketchip.util.PlusArg
case class TLMonitorArgs(edge: TLEdge)
abstract class TLMonitorBase(args: TLMonitorArgs) extends Module
{
val io = IO(new Bundle {
val in = Input(new TLBundle(args.edge.bundle))
})
def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit
legalize(io.in, args.edge, reset)
}
object TLMonitor {
def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = {
if (enable) {
EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) }
} else { node }
}
}
class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args)
{
require (args.edge.params(TLMonitorStrictMode) || (! args.edge.params(TestplanTestType).formal))
val cover_prop_class = PropertyClass.Default
//Like assert but can flip to being an assumption for formal verification
def monAssert(cond: Bool, message: String): Unit =
if (monitorDir == MonitorDirection.Monitor) {
assert(cond, message)
} else {
Property(monitorDir, cond, message, PropertyClass.Default)
}
def assume(cond: Bool, message: String): Unit =
if (monitorDir == MonitorDirection.Monitor) {
assert(cond, message)
} else {
Property(monitorDir.flip, cond, message, PropertyClass.Default)
}
def extra = {
args.edge.sourceInfo match {
case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)"
case _ => ""
}
}
def visible(address: UInt, source: UInt, edge: TLEdge) =
edge.client.clients.map { c =>
!c.sourceId.contains(source) ||
c.visibility.map(_.contains(address)).reduce(_ || _)
}.reduce(_ && _)
def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = {
//switch this flag to turn on diplomacy in error messages
def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n"
monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra)
// Reuse these subexpressions to save some firrtl lines
val source_ok = edge.client.contains(bundle.source)
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val mask = edge.full_mask(bundle)
monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility")
//The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B
//TODO: check for acquireT?
when (bundle.opcode === TLMessages.AcquireBlock) {
monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra)
monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra)
monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra)
monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra)
}
when (bundle.opcode === TLMessages.AcquirePerm) {
monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra)
monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra)
monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra)
monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra)
monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra)
}
when (bundle.opcode === TLMessages.Get) {
monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra)
monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra)
monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra)
}
when (bundle.opcode === TLMessages.PutFullData) {
monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra)
monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.PutPartialData) {
monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra)
monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.ArithmeticData) {
monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra)
monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.LogicalData) {
monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra)
monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.Hint) {
monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra)
monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra)
}
}
def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = {
monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra)
monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility")
// Reuse these subexpressions to save some firrtl lines
val address_ok = edge.manager.containsSafe(edge.address(bundle))
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val mask = edge.full_mask(bundle)
val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source
when (bundle.opcode === TLMessages.Probe) {
assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra)
assume (address_ok, "'B' channel Probe carries unmanaged address" + extra)
assume (legal_source, "'B' channel Probe carries source that is not first source" + extra)
assume (is_aligned, "'B' channel Probe address not aligned to size" + extra)
assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra)
assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra)
assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra)
}
when (bundle.opcode === TLMessages.Get) {
monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra)
monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra)
}
when (bundle.opcode === TLMessages.PutFullData) {
monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra)
monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.PutPartialData) {
monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra)
monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.ArithmeticData) {
monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra)
monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra)
monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.LogicalData) {
monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra)
monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra)
monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.Hint) {
monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra)
monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra)
monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra)
}
}
def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = {
monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra)
val source_ok = edge.client.contains(bundle.source)
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val address_ok = edge.manager.containsSafe(edge.address(bundle))
monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility")
when (bundle.opcode === TLMessages.ProbeAck) {
monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra)
monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra)
}
when (bundle.opcode === TLMessages.ProbeAckData) {
monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra)
}
when (bundle.opcode === TLMessages.Release) {
monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra)
monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra)
monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra)
}
when (bundle.opcode === TLMessages.ReleaseData) {
monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra)
monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra)
}
when (bundle.opcode === TLMessages.AccessAck) {
monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra)
monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra)
}
when (bundle.opcode === TLMessages.AccessAckData) {
monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra)
}
when (bundle.opcode === TLMessages.HintAck) {
monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra)
monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra)
}
}
def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = {
assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra)
val source_ok = edge.client.contains(bundle.source)
val sink_ok = bundle.sink < edge.manager.endSinkId.U
val deny_put_ok = edge.manager.mayDenyPut.B
val deny_get_ok = edge.manager.mayDenyGet.B
when (bundle.opcode === TLMessages.ReleaseAck) {
assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra)
assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra)
assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra)
}
when (bundle.opcode === TLMessages.Grant) {
assume (source_ok, "'D' channel Grant carries invalid source ID" + extra)
assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra)
assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra)
assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra)
assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel Grant is denied" + extra)
}
when (bundle.opcode === TLMessages.GrantData) {
assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra)
assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra)
assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra)
assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra)
assume (!bundle.denied || bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra)
assume (deny_get_ok || !bundle.denied, "'D' channel GrantData is denied" + extra)
}
when (bundle.opcode === TLMessages.AccessAck) {
assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel AccessAck is denied" + extra)
}
when (bundle.opcode === TLMessages.AccessAckData) {
assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra)
assume (!bundle.denied || bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra)
assume (deny_get_ok || !bundle.denied, "'D' channel AccessAckData is denied" + extra)
}
when (bundle.opcode === TLMessages.HintAck) {
assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel HintAck is denied" + extra)
}
}
def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = {
val sink_ok = bundle.sink < edge.manager.endSinkId.U
monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra)
}
def legalizeFormat(bundle: TLBundle, edge: TLEdge) = {
when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) }
when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) }
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) }
when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) }
when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) }
} else {
monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra)
monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra)
monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra)
}
}
def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = {
val a_first = edge.first(a.bits, a.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (a.valid && !a_first) {
monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra)
monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra)
monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra)
monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra)
monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra)
}
when (a.fire && a_first) {
opcode := a.bits.opcode
param := a.bits.param
size := a.bits.size
source := a.bits.source
address := a.bits.address
}
}
def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = {
val b_first = edge.first(b.bits, b.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (b.valid && !b_first) {
monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra)
monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra)
monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra)
monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra)
monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra)
}
when (b.fire && b_first) {
opcode := b.bits.opcode
param := b.bits.param
size := b.bits.size
source := b.bits.source
address := b.bits.address
}
}
def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = {
// Symbolic variable
val sym_source = Wire(UInt(edge.client.endSourceId.W))
// TODO: Connect sym_source to a fixed value for simulation and to a
// free wire in formal
sym_source := 0.U
// Type casting Int to UInt
val maxSourceId = Wire(UInt(edge.client.endSourceId.W))
maxSourceId := edge.client.endSourceId.U
// Delayed verison of sym_source
val sym_source_d = Reg(UInt(edge.client.endSourceId.W))
sym_source_d := sym_source
// These will be constraints for FV setup
Property(
MonitorDirection.Monitor,
(sym_source === sym_source_d),
"sym_source should remain stable",
PropertyClass.Default)
Property(
MonitorDirection.Monitor,
(sym_source <= maxSourceId),
"sym_source should take legal value",
PropertyClass.Default)
val my_resp_pend = RegInit(false.B)
val my_opcode = Reg(UInt())
val my_size = Reg(UInt())
val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire)
val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire)
val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source)
val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source)
val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat)
val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend)
when (my_set_resp_pend) {
my_resp_pend := true.B
} .elsewhen (my_clr_resp_pend) {
my_resp_pend := false.B
}
when (my_a_first_beat) {
my_opcode := bundle.a.bits.opcode
my_size := bundle.a.bits.size
}
val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size)
val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode)
val my_resp_opcode_legal = Wire(Bool())
when ((my_resp_opcode === TLMessages.Get) || (my_resp_opcode === TLMessages.ArithmeticData) ||
(my_resp_opcode === TLMessages.LogicalData)) {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData)
} .elsewhen ((my_resp_opcode === TLMessages.PutFullData) || (my_resp_opcode === TLMessages.PutPartialData)) {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck)
} .otherwise {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck)
}
monAssert (IfThen(my_resp_pend, !my_a_first_beat),
"Request message should not be sent with a source ID, for which a response message" +
"is already pending (not received until current cycle) for a prior request message" +
"with the same source ID" + extra)
assume (IfThen(my_clr_resp_pend, (my_set_resp_pend || my_resp_pend)),
"Response message should be accepted with a source ID only if a request message with the" +
"same source ID has been accepted or is being accepted in the current cycle" + extra)
assume (IfThen(my_d_first_beat, (my_a_first_beat || my_resp_pend)),
"Response message should be sent with a source ID only if a request message with the" +
"same source ID has been accepted or is being sent in the current cycle" + extra)
assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)),
"If d_valid is 1, then d_size should be same as a_size of the corresponding request" +
"message" + extra)
assume (IfThen(my_d_first_beat, my_resp_opcode_legal),
"If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" +
"request message" + extra)
}
def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = {
val c_first = edge.first(c.bits, c.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (c.valid && !c_first) {
monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra)
monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra)
monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra)
monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra)
monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra)
}
when (c.fire && c_first) {
opcode := c.bits.opcode
param := c.bits.param
size := c.bits.size
source := c.bits.source
address := c.bits.address
}
}
def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = {
val d_first = edge.first(d.bits, d.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val sink = Reg(UInt())
val denied = Reg(Bool())
when (d.valid && !d_first) {
assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra)
assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra)
assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra)
assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra)
assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra)
assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra)
}
when (d.fire && d_first) {
opcode := d.bits.opcode
param := d.bits.param
size := d.bits.size
source := d.bits.source
sink := d.bits.sink
denied := d.bits.denied
}
}
def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = {
legalizeMultibeatA(bundle.a, edge)
legalizeMultibeatD(bundle.d, edge)
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
legalizeMultibeatB(bundle.b, edge)
legalizeMultibeatC(bundle.c, edge)
}
}
//This is left in for almond which doesn't adhere to the tilelink protocol
@deprecated("Use legalizeADSource instead if possible","")
def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = {
val inflight = RegInit(0.U(edge.client.endSourceId.W))
val a_first = edge.first(bundle.a.bits, bundle.a.fire)
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
val a_set = WireInit(0.U(edge.client.endSourceId.W))
when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) {
a_set := UIntToOH(bundle.a.bits.source)
assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra)
}
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
assume((a_set | inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra)
}
if (edge.manager.minLatency > 0) {
assume(a_set =/= d_clr || !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra)
}
inflight := (inflight | a_set) & ~d_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
assert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = {
val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset)
val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything
val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size)
val log_a_size_bus_size = log2Ceil(a_size_bus_size)
def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits
val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error
inflight.suggestName("inflight")
val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
inflight_opcodes.suggestName("inflight_opcodes")
val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
inflight_sizes.suggestName("inflight_sizes")
val a_first = edge.first(bundle.a.bits, bundle.a.fire)
a_first.suggestName("a_first")
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
d_first.suggestName("d_first")
val a_set = WireInit(0.U(edge.client.endSourceId.W))
val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
a_set.suggestName("a_set")
a_set_wo_ready.suggestName("a_set_wo_ready")
val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
a_opcodes_set.suggestName("a_opcodes_set")
val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
a_sizes_set.suggestName("a_sizes_set")
val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W))
a_opcode_lookup.suggestName("a_opcode_lookup")
a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U
val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W))
a_size_lookup.suggestName("a_size_lookup")
a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U
val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant))
val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant))
val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W))
a_opcodes_set_interm.suggestName("a_opcodes_set_interm")
val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W))
a_sizes_set_interm.suggestName("a_sizes_set_interm")
when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) {
a_set_wo_ready := UIntToOH(bundle.a.bits.source)
}
when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) {
a_set := UIntToOH(bundle.a.bits.source)
a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) | 1.U
a_sizes_set_interm := (bundle.a.bits.size << 1.U) | 1.U
a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U)
a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U)
monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra)
}
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
d_clr.suggestName("d_clr")
d_clr_wo_ready.suggestName("d_clr_wo_ready")
val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
d_opcodes_clr.suggestName("d_opcodes_clr")
val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
d_sizes_clr.suggestName("d_sizes_clr")
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr_wo_ready := UIntToOH(bundle.d.bits.source)
}
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U)
d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U)
}
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source)
assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra)
when (same_cycle_resp) {
assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) ||
(bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra)
assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra)
} .otherwise {
assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) ||
(bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra)
assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra)
}
}
when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) {
assume((!bundle.d.ready) || bundle.a.ready, "ready check")
}
if (edge.manager.minLatency > 0) {
assume(a_set_wo_ready =/= d_clr_wo_ready || !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra)
}
inflight := (inflight | a_set) & ~d_clr
inflight_opcodes := (inflight_opcodes | a_opcodes_set) & ~d_opcodes_clr
inflight_sizes := (inflight_sizes | a_sizes_set) & ~d_sizes_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = {
val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset)
val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything
val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size)
val log_c_size_bus_size = log2Ceil(c_size_bus_size)
def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits
val inflight = RegInit(0.U((2 max edge.client.endSourceId).W))
val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
inflight.suggestName("inflight")
inflight_opcodes.suggestName("inflight_opcodes")
inflight_sizes.suggestName("inflight_sizes")
val c_first = edge.first(bundle.c.bits, bundle.c.fire)
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
c_first.suggestName("c_first")
d_first.suggestName("d_first")
val c_set = WireInit(0.U(edge.client.endSourceId.W))
val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
c_set.suggestName("c_set")
c_set_wo_ready.suggestName("c_set_wo_ready")
c_opcodes_set.suggestName("c_opcodes_set")
c_sizes_set.suggestName("c_sizes_set")
val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W))
val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W))
c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U
c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U
c_opcode_lookup.suggestName("c_opcode_lookup")
c_size_lookup.suggestName("c_size_lookup")
val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W))
val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W))
c_opcodes_set_interm.suggestName("c_opcodes_set_interm")
c_sizes_set_interm.suggestName("c_sizes_set_interm")
when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) {
c_set_wo_ready := UIntToOH(bundle.c.bits.source)
}
when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) {
c_set := UIntToOH(bundle.c.bits.source)
c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) | 1.U
c_sizes_set_interm := (bundle.c.bits.size << 1.U) | 1.U
c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U)
c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U)
monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra)
}
val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck || bundle.c.bits.opcode === TLMessages.ProbeAckData
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
d_clr.suggestName("d_clr")
d_clr_wo_ready.suggestName("d_clr_wo_ready")
d_opcodes_clr.suggestName("d_opcodes_clr")
d_sizes_clr.suggestName("d_sizes_clr")
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
d_clr_wo_ready := UIntToOH(bundle.d.bits.source)
}
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U)
d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U)
}
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source)
assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra)
when (same_cycle_resp) {
assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra)
} .otherwise {
assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra)
}
}
when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) {
assume((!bundle.d.ready) || bundle.c.ready, "ready check")
}
if (edge.manager.minLatency > 0) {
when (c_set_wo_ready.orR) {
assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra)
}
}
inflight := (inflight | c_set) & ~d_clr
inflight_opcodes := (inflight_opcodes | c_opcodes_set) & ~d_opcodes_clr
inflight_sizes := (inflight_sizes | c_sizes_set) & ~d_sizes_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.c.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = {
val inflight = RegInit(0.U(edge.manager.endSinkId.W))
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
val e_first = true.B
val d_set = WireInit(0.U(edge.manager.endSinkId.W))
when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) {
d_set := UIntToOH(bundle.d.bits.sink)
assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra)
}
val e_clr = WireInit(0.U(edge.manager.endSinkId.W))
when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) {
e_clr := UIntToOH(bundle.e.bits.sink)
monAssert((d_set | inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra)
}
// edge.client.minLatency applies to BC, not DE
inflight := (inflight | d_set) & ~e_clr
}
def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = {
val sourceBits = log2Ceil(edge.client.endSourceId)
val tooBig = 14 // >16kB worth of flight information gets to be too much
if (sourceBits > tooBig) {
println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked")
} else {
if (args.edge.params(TestplanTestType).simulation) {
if (args.edge.params(TLMonitorStrictMode)) {
legalizeADSource(bundle, edge)
legalizeCDSource(bundle, edge)
} else {
legalizeADSourceOld(bundle, edge)
}
}
if (args.edge.params(TestplanTestType).formal) {
legalizeADSourceFormal(bundle, edge)
}
}
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
// legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize...
val sinkBits = log2Ceil(edge.manager.endSinkId)
if (sinkBits > tooBig) {
println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked")
} else {
legalizeDESink(bundle, edge)
}
}
}
def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = {
legalizeFormat (bundle, edge)
legalizeMultibeat (bundle, edge)
legalizeUnique (bundle, edge)
}
}
File PlusArg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.experimental._
import chisel3.util.HasBlackBoxResource
@deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05")
case class PlusArgInfo(default: BigInt, docstring: String)
/** Case class for PlusArg information
*
* @tparam A scala type of the PlusArg value
* @param default optional default value
* @param docstring text to include in the help
* @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT)
*/
private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String)
/** Typeclass for converting a type to a doctype string
* @tparam A some type
*/
trait Doctypeable[A] {
/** Return the doctype string for some option */
def toDoctype(a: Option[A]): String
}
/** Object containing implementations of the Doctypeable typeclass */
object Doctypes {
/** Converts an Int => "INT" */
implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" }
/** Converts a BigInt => "INT" */
implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" }
/** Converts a String => "STRING" */
implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" }
}
class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map(
"FORMAT" -> StringParam(format),
"DEFAULT" -> IntParam(default),
"WIDTH" -> IntParam(width)
)) with HasBlackBoxResource {
val io = IO(new Bundle {
val out = Output(UInt(width.W))
})
addResource("/vsrc/plusarg_reader.v")
}
/* This wrapper class has no outputs, making it clear it is a simulation-only construct */
class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module {
val io = IO(new Bundle {
val count = Input(UInt(width.W))
})
val max = Module(new plusarg_reader(format, default, docstring, width)).io.out
when (max > 0.U) {
assert (io.count < max, s"Timeout exceeded: $docstring")
}
}
import Doctypes._
object PlusArg
{
/** PlusArg("foo") will return 42.U if the simulation is run with +foo=42
* Do not use this as an initial register value. The value is set in an
* initial block and thus accessing it from another initial is racey.
* Add a docstring to document the arg, which can be dumped in an elaboration
* pass.
*/
def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = {
PlusArgArtefacts.append(name, Some(default), docstring)
Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out
}
/** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert
* to kill the simulation when count exceeds the specified integer argument.
* Default 0 will never assert.
*/
def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = {
PlusArgArtefacts.append(name, Some(default), docstring)
Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count
}
}
object PlusArgArtefacts {
private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty
/* Add a new PlusArg */
@deprecated(
"Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08",
"Rocket Chip 2020.05"
)
def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring)
/** Add a new PlusArg
*
* @tparam A scala type of the PlusArg value
* @param name name for the PlusArg
* @param default optional default value
* @param docstring text to include in the help
*/
def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit =
artefacts = artefacts ++
Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default)))
/* From plus args, generate help text */
private def serializeHelp_cHeader(tab: String = ""): String = artefacts
.map{ case(arg, info) =>
s"""|$tab+$arg=${info.doctype}\\n\\
|$tab${" "*20}${info.docstring}\\n\\
|""".stripMargin ++ info.default.map{ case default =>
s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("")
}.toSeq.mkString("\\n\\\n") ++ "\""
/* From plus args, generate a char array of their names */
private def serializeArray_cHeader(tab: String = ""): String = {
val prettyTab = tab + " " * 44 // Length of 'static const ...'
s"${tab}static const char * verilog_plusargs [] = {\\\n" ++
artefacts
.map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" }
.mkString("")++
s"${prettyTab}0};"
}
/* Generate C code to be included in emulator.cc that helps with
* argument parsing based on available Verilog PlusArgs */
def serialize_cHeader(): String =
s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\
|${serializeHelp_cHeader(" "*7)}
|${serializeArray_cHeader()}
|""".stripMargin
}
File Edges.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.util._
class TLEdge(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdgeParameters(client, manager, params, sourceInfo)
{
def isAligned(address: UInt, lgSize: UInt): Bool = {
if (maxLgSize == 0) true.B else {
val mask = UIntToOH1(lgSize, maxLgSize)
(address & mask) === 0.U
}
}
def mask(address: UInt, lgSize: UInt): UInt =
MaskGen(address, lgSize, manager.beatBytes)
def staticHasData(bundle: TLChannel): Option[Boolean] = {
bundle match {
case _:TLBundleA => {
// Do there exist A messages with Data?
val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial
// Do there exist A messages without Data?
val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint
// Statically optimize the case where hasData is a constant
if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None
}
case _:TLBundleB => {
// Do there exist B messages with Data?
val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial
// Do there exist B messages without Data?
val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint
// Statically optimize the case where hasData is a constant
if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None
}
case _:TLBundleC => {
// Do there eixst C messages with Data?
val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe
// Do there exist C messages without Data?
val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe
if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None
}
case _:TLBundleD => {
// Do there eixst D messages with Data?
val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB
// Do there exist D messages without Data?
val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT
if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None
}
case _:TLBundleE => Some(false)
}
}
def isRequest(x: TLChannel): Bool = {
x match {
case a: TLBundleA => true.B
case b: TLBundleB => true.B
case c: TLBundleC => c.opcode(2) && c.opcode(1)
// opcode === TLMessages.Release ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(2) && !d.opcode(1)
// opcode === TLMessages.Grant ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
}
def isResponse(x: TLChannel): Bool = {
x match {
case a: TLBundleA => false.B
case b: TLBundleB => false.B
case c: TLBundleC => !c.opcode(2) || !c.opcode(1)
// opcode =/= TLMessages.Release &&
// opcode =/= TLMessages.ReleaseData
case d: TLBundleD => true.B // Grant isResponse + isRequest
case e: TLBundleE => true.B
}
}
def hasData(x: TLChannel): Bool = {
val opdata = x match {
case a: TLBundleA => !a.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case b: TLBundleB => !b.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case c: TLBundleC => c.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.ProbeAckData ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
staticHasData(x).map(_.B).getOrElse(opdata)
}
def opcode(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.opcode
case b: TLBundleB => b.opcode
case c: TLBundleC => c.opcode
case d: TLBundleD => d.opcode
}
}
def param(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.param
case b: TLBundleB => b.param
case c: TLBundleC => c.param
case d: TLBundleD => d.param
}
}
def size(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.size
case b: TLBundleB => b.size
case c: TLBundleC => c.size
case d: TLBundleD => d.size
}
}
def data(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.data
case b: TLBundleB => b.data
case c: TLBundleC => c.data
case d: TLBundleD => d.data
}
}
def corrupt(x: TLDataChannel): Bool = {
x match {
case a: TLBundleA => a.corrupt
case b: TLBundleB => b.corrupt
case c: TLBundleC => c.corrupt
case d: TLBundleD => d.corrupt
}
}
def mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.mask
case b: TLBundleB => b.mask
case c: TLBundleC => mask(c.address, c.size)
}
}
def full_mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => mask(a.address, a.size)
case b: TLBundleB => mask(b.address, b.size)
case c: TLBundleC => mask(c.address, c.size)
}
}
def address(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.address
case b: TLBundleB => b.address
case c: TLBundleC => c.address
}
}
def source(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.source
case b: TLBundleB => b.source
case c: TLBundleC => c.source
case d: TLBundleD => d.source
}
}
def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes)
def addr_lo(x: UInt): UInt =
if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0)
def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x))
def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x))
def numBeats(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 1.U
case bundle: TLDataChannel => {
val hasData = this.hasData(bundle)
val size = this.size(bundle)
val cutoff = log2Ceil(manager.beatBytes)
val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U
val decode = UIntToOH(size, maxLgSize+1) >> cutoff
Mux(hasData, decode | small.asUInt, 1.U)
}
}
}
def numBeats1(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 0.U
case bundle: TLDataChannel => {
if (maxLgSize == 0) {
0.U
} else {
val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes)
Mux(hasData(bundle), decode, 0.U)
}
}
}
}
def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val beats1 = numBeats1(bits)
val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W))
val counter1 = counter - 1.U
val first = counter === 0.U
val last = counter === 1.U || beats1 === 0.U
val done = last && fire
val count = (beats1 & ~counter1)
when (fire) {
counter := Mux(first, beats1, counter1)
}
(first, last, done, count)
}
def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1
def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire)
def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid)
def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2
def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire)
def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid)
def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3
def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire)
def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid)
def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3)
}
def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire)
def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid)
def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4)
}
def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire)
def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid)
def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes))
}
def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire)
def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid)
// Does the request need T permissions to be executed?
def needT(a: TLBundleA): Bool = {
val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLPermissions.NtoB -> false.B,
TLPermissions.NtoT -> true.B,
TLPermissions.BtoT -> true.B))
MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array(
TLMessages.PutFullData -> true.B,
TLMessages.PutPartialData -> true.B,
TLMessages.ArithmeticData -> true.B,
TLMessages.LogicalData -> true.B,
TLMessages.Get -> false.B,
TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLHints.PREFETCH_READ -> false.B,
TLHints.PREFETCH_WRITE -> true.B)),
TLMessages.AcquireBlock -> acq_needT,
TLMessages.AcquirePerm -> acq_needT))
}
// This is a very expensive circuit; use only if you really mean it!
def inFlight(x: TLBundle): (UInt, UInt) = {
val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W))
val bce = manager.anySupportAcquireB && client.anySupportProbe
val (a_first, a_last, _) = firstlast(x.a)
val (b_first, b_last, _) = firstlast(x.b)
val (c_first, c_last, _) = firstlast(x.c)
val (d_first, d_last, _) = firstlast(x.d)
val (e_first, e_last, _) = firstlast(x.e)
val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits))
val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits))
val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits))
val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits))
val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits))
val a_inc = x.a.fire && a_first && a_request
val b_inc = x.b.fire && b_first && b_request
val c_inc = x.c.fire && c_first && c_request
val d_inc = x.d.fire && d_first && d_request
val e_inc = x.e.fire && e_first && e_request
val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil))
val a_dec = x.a.fire && a_last && a_response
val b_dec = x.b.fire && b_last && b_response
val c_dec = x.c.fire && c_last && c_response
val d_dec = x.d.fire && d_last && d_response
val e_dec = x.e.fire && e_last && e_response
val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil))
val next_flight = flight + PopCount(inc) - PopCount(dec)
flight := next_flight
(flight, next_flight)
}
def prettySourceMapping(context: String): String = {
s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n"
}
}
class TLEdgeOut(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
// Transfers
def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquireBlock
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquirePerm
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.Release
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ReleaseData
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) =
Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B)
def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAck
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions, data)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAckData
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B)
def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink)
def GrantAck(toSink: UInt): TLBundleE = {
val e = Wire(new TLBundleE(bundle))
e.sink := toSink
e
}
// Accesses
def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsGetFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Get
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutFullFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutFullData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, mask, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutPartialFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutPartialData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = {
require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsArithmeticFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.ArithmeticData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsLogicalFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.LogicalData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = {
require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsHintFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Hint
a.param := param
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data)
def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAckData
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size)
def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.HintAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
}
class TLEdgeIn(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = {
val todo = x.filter(!_.isEmpty)
val heads = todo.map(_.head)
val tails = todo.map(_.tail)
if (todo.isEmpty) Nil else { heads +: myTranspose(tails) }
}
// Transfers
def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = {
require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}")
val legal = client.supportsProbe(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Probe
b.param := capPermissions
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.Grant
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.GrantData
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B)
def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.ReleaseAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
// Accesses
def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = {
require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsGet(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Get
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsPutFull(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutFullData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, mask, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsPutPartial(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutPartialData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsArithmetic(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.ArithmeticData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsLogical(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.LogicalData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = {
require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsHint(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Hint
b.param := param
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size)
def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied)
def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data)
def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAckData
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B)
def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied)
def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B)
def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.HintAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
}
| module TLMonitor_71( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [6:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire a_first_done = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35]
reg a_first_counter; // @[Edges.scala:229:27]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [6:0] address; // @[Monitor.scala:391:22]
reg d_first_counter; // @[Edges.scala:229:27]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [1:0] inflight; // @[Monitor.scala:614:27]
reg [3:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [3:0] inflight_sizes; // @[Monitor.scala:618:33]
reg a_first_counter_1; // @[Edges.scala:229:27]
reg d_first_counter_1; // @[Edges.scala:229:27]
wire a_set = a_first_done & ~a_first_counter_1; // @[Decoupled.scala:51:35]
wire d_release_ack = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala:673:46]
wire _GEN = io_in_d_bits_opcode != 3'h6; // @[Monitor.scala:673:46, :674:74]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
reg [1:0] inflight_1; // @[Monitor.scala:726:35]
reg [3:0] inflight_sizes_1; // @[Monitor.scala:728:35]
reg d_first_counter_2; // @[Edges.scala:229:27]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27] |
Generate the Verilog code corresponding to the following Chisel files.
File Pipeline.scala:
package gemmini
import chisel3._
import chisel3.util._
class Pipeline[T <: Data] (gen: T, latency: Int)(comb: Seq[T => T] = Seq.fill(latency+1)((x: T) => x)) extends Module {
val io = IO(new Bundle {
val in = Flipped(Decoupled(gen))
val out = Decoupled(gen)
val busy = Output(Bool())
})
require(comb.size == latency+1, "length of combinational is incorrect")
if (latency == 0) {
io.in.ready := io.out.ready
io.out.valid := io.in.valid
io.out.bits := comb.head(io.in.bits)
io.busy := io.in.valid
} else {
val stages = Reg(Vec(latency, gen))
val valids = RegInit(VecInit(Seq.fill(latency)(false.B)))
val stalling = VecInit(Seq.fill(latency)(false.B))
io.busy := io.in.valid || valids.reduce(_||_)
// Stall signals
io.in.ready := !stalling.head
stalling.last := valids.last && !io.out.ready
(stalling.init, stalling.tail, valids.init).zipped.foreach { case (s1, s2, v1) =>
s1 := v1 && s2
}
// Valid signals
// When the pipeline stage ahead of you isn't stalling, then make yourself invalid
io.out.valid := valids.last
when(io.out.ready) {
valids.last := false.B
}
(valids.init, stalling.tail).zipped.foreach { case (v1, s2) =>
when(!s2) {
v1 := false.B
}
}
// When the pipeline stage behind you is valid then become true
when(io.in.fire) {
valids.head := true.B
}
(valids.tail, valids.init).zipped.foreach { case (v2, v1) =>
when(v1) {
v2 := true.B
}
}
// Stages
when(io.in.fire) {
stages.head := comb.head(io.in.bits)
}
io.out.bits := comb.last(stages.last)
((stages.tail zip stages.init) zip (stalling.tail zip comb.tail.init)).foreach { case ((st2, st1), (s2, c1)) =>
when(!s2) {
st2 := c1(st1)
}
}
}
}
object Pipeline {
def apply[T <: Data](in: ReadyValidIO[T], latency: Int, comb: Seq[T => T]): DecoupledIO[T] = {
val p = Module(new Pipeline(in.bits.cloneType, latency)(comb))
p.io.in <> in
p.io.out
}
def apply[T <: Data](in: ReadyValidIO[T], latency: Int): DecoupledIO[T] = {
val p = Module(new Pipeline(in.bits.cloneType, latency)())
p.io.in <> in
p.io.out
}
}
| module Pipeline_2( // @[Pipeline.scala:6:7]
input clock, // @[Pipeline.scala:6:7]
input reset, // @[Pipeline.scala:6:7]
output io_in_ready, // @[Pipeline.scala:7:14]
input io_in_valid, // @[Pipeline.scala:7:14]
input [127:0] io_in_bits_data, // @[Pipeline.scala:7:14]
input io_in_bits_fromDMA, // @[Pipeline.scala:7:14]
input io_out_ready, // @[Pipeline.scala:7:14]
output io_out_valid, // @[Pipeline.scala:7:14]
output [127:0] io_out_bits_data, // @[Pipeline.scala:7:14]
output io_out_bits_fromDMA // @[Pipeline.scala:7:14]
);
wire io_in_valid_0 = io_in_valid; // @[Pipeline.scala:6:7]
wire [127:0] io_in_bits_data_0 = io_in_bits_data; // @[Pipeline.scala:6:7]
wire io_in_bits_fromDMA_0 = io_in_bits_fromDMA; // @[Pipeline.scala:6:7]
wire io_out_ready_0 = io_out_ready; // @[Pipeline.scala:6:7]
wire _valids_WIRE_0 = 1'h0; // @[Pipeline.scala:22:33]
wire _valids_WIRE_1 = 1'h0; // @[Pipeline.scala:22:33]
wire _valids_WIRE_2 = 1'h0; // @[Pipeline.scala:22:33]
wire _valids_WIRE_3 = 1'h0; // @[Pipeline.scala:22:33]
wire _io_in_ready_T; // @[Pipeline.scala:27:20]
wire _io_busy_T_3; // @[Pipeline.scala:24:28]
wire io_in_ready_0; // @[Pipeline.scala:6:7]
wire [127:0] io_out_bits_data_0; // @[Pipeline.scala:6:7]
wire io_out_bits_fromDMA_0; // @[Pipeline.scala:6:7]
wire io_out_valid_0; // @[Pipeline.scala:6:7]
wire io_busy; // @[Pipeline.scala:6:7]
reg [127:0] stages_0_data; // @[Pipeline.scala:21:21]
reg stages_0_fromDMA; // @[Pipeline.scala:21:21]
reg [127:0] stages_1_data; // @[Pipeline.scala:21:21]
reg stages_1_fromDMA; // @[Pipeline.scala:21:21]
reg [127:0] stages_2_data; // @[Pipeline.scala:21:21]
reg stages_2_fromDMA; // @[Pipeline.scala:21:21]
reg [127:0] stages_3_data; // @[Pipeline.scala:21:21]
assign io_out_bits_data_0 = stages_3_data; // @[Pipeline.scala:6:7, :21:21]
reg stages_3_fromDMA; // @[Pipeline.scala:21:21]
assign io_out_bits_fromDMA_0 = stages_3_fromDMA; // @[Pipeline.scala:6:7, :21:21]
reg valids_0; // @[Pipeline.scala:22:25]
reg valids_1; // @[Pipeline.scala:22:25]
reg valids_2; // @[Pipeline.scala:22:25]
reg valids_3; // @[Pipeline.scala:22:25]
assign io_out_valid_0 = valids_3; // @[Pipeline.scala:6:7, :22:25]
wire _stalling_0_T; // @[Pipeline.scala:30:16]
wire _stalling_1_T; // @[Pipeline.scala:30:16]
wire _stalling_2_T; // @[Pipeline.scala:30:16]
wire _stalling_3_T_1; // @[Pipeline.scala:28:34]
wire stalling_0; // @[Pipeline.scala:23:27]
wire stalling_1; // @[Pipeline.scala:23:27]
wire stalling_2; // @[Pipeline.scala:23:27]
wire stalling_3; // @[Pipeline.scala:23:27]
wire _io_busy_T = valids_0 | valids_1; // @[Pipeline.scala:22:25, :24:46]
wire _io_busy_T_1 = _io_busy_T | valids_2; // @[Pipeline.scala:22:25, :24:46]
wire _io_busy_T_2 = _io_busy_T_1 | valids_3; // @[Pipeline.scala:22:25, :24:46]
assign _io_busy_T_3 = io_in_valid_0 | _io_busy_T_2; // @[Pipeline.scala:6:7, :24:{28,46}]
assign io_busy = _io_busy_T_3; // @[Pipeline.scala:6:7, :24:28]
assign _io_in_ready_T = ~stalling_0; // @[Pipeline.scala:23:27, :27:20]
assign io_in_ready_0 = _io_in_ready_T; // @[Pipeline.scala:6:7, :27:20]
wire _stalling_3_T = ~io_out_ready_0; // @[Pipeline.scala:6:7, :28:37]
assign _stalling_3_T_1 = valids_3 & _stalling_3_T; // @[Pipeline.scala:22:25, :28:{34,37}]
assign stalling_3 = _stalling_3_T_1; // @[Pipeline.scala:23:27, :28:34]
assign _stalling_0_T = valids_0 & stalling_1; // @[Pipeline.scala:22:25, :23:27, :30:16]
assign stalling_0 = _stalling_0_T; // @[Pipeline.scala:23:27, :30:16]
assign _stalling_1_T = valids_1 & stalling_2; // @[Pipeline.scala:22:25, :23:27, :30:16]
assign stalling_1 = _stalling_1_T; // @[Pipeline.scala:23:27, :30:16]
assign _stalling_2_T = valids_2 & stalling_3; // @[Pipeline.scala:22:25, :23:27, :30:16]
assign stalling_2 = _stalling_2_T; // @[Pipeline.scala:23:27, :30:16]
wire _T_4 = io_in_ready_0 & io_in_valid_0; // @[Decoupled.scala:51:35]
always @(posedge clock) begin // @[Pipeline.scala:6:7]
if (_T_4) begin // @[Decoupled.scala:51:35]
stages_0_data <= io_in_bits_data_0; // @[Pipeline.scala:6:7, :21:21]
stages_0_fromDMA <= io_in_bits_fromDMA_0; // @[Pipeline.scala:6:7, :21:21]
end
if (stalling_1) begin // @[Pipeline.scala:23:27]
end
else begin // @[Pipeline.scala:23:27]
stages_1_data <= stages_0_data; // @[Pipeline.scala:21:21]
stages_1_fromDMA <= stages_0_fromDMA; // @[Pipeline.scala:21:21]
end
if (stalling_2) begin // @[Pipeline.scala:23:27]
end
else begin // @[Pipeline.scala:23:27]
stages_2_data <= stages_1_data; // @[Pipeline.scala:21:21]
stages_2_fromDMA <= stages_1_fromDMA; // @[Pipeline.scala:21:21]
end
if (stalling_3) begin // @[Pipeline.scala:23:27]
end
else begin // @[Pipeline.scala:23:27]
stages_3_data <= stages_2_data; // @[Pipeline.scala:21:21]
stages_3_fromDMA <= stages_2_fromDMA; // @[Pipeline.scala:21:21]
end
if (reset) begin // @[Pipeline.scala:6:7]
valids_0 <= 1'h0; // @[Pipeline.scala:22:25]
valids_1 <= 1'h0; // @[Pipeline.scala:22:25]
valids_2 <= 1'h0; // @[Pipeline.scala:22:25]
valids_3 <= 1'h0; // @[Pipeline.scala:22:25]
end
else begin // @[Pipeline.scala:6:7]
valids_0 <= _T_4 | stalling_1 & valids_0; // @[Decoupled.scala:51:35]
valids_1 <= valids_0 | stalling_2 & valids_1; // @[Pipeline.scala:22:25, :23:27, :40:17, :41:12, :49:16, :50:12]
valids_2 <= valids_1 | stalling_3 & valids_2; // @[Pipeline.scala:22:25, :23:27, :40:17, :41:12, :49:16, :50:12]
valids_3 <= valids_2 | ~io_out_ready_0 & valids_3; // @[Pipeline.scala:6:7, :22:25, :36:24, :37:19, :49:16, :50:12]
end
always @(posedge)
assign io_in_ready = io_in_ready_0; // @[Pipeline.scala:6:7]
assign io_out_valid = io_out_valid_0; // @[Pipeline.scala:6:7]
assign io_out_bits_data = io_out_bits_data_0; // @[Pipeline.scala:6:7]
assign io_out_bits_fromDMA = io_out_bits_fromDMA_0; // @[Pipeline.scala:6:7]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File ShiftReg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
// Similar to the Chisel ShiftRegister but allows the user to suggest a
// name to the registers that get instantiated, and
// to provide a reset value.
object ShiftRegInit {
def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T =
(0 until n).foldRight(in) {
case (i, next) => {
val r = RegNext(next, init)
name.foreach { na => r.suggestName(s"${na}_${i}") }
r
}
}
}
/** These wrap behavioral
* shift registers into specific modules to allow for
* backend flows to replace or constrain
* them properly when used for CDC synchronization,
* rather than buffering.
*
* The different types vary in their reset behavior:
* AsyncResetShiftReg -- Asynchronously reset register array
* A W(width) x D(depth) sized array is constructed from D instantiations of a
* W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg,
* but only used for timing applications
*/
abstract class AbstractPipelineReg(w: Int = 1) extends Module {
val io = IO(new Bundle {
val d = Input(UInt(w.W))
val q = Output(UInt(w.W))
}
)
}
object AbstractPipelineReg {
def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = {
val chain = Module(gen)
name.foreach{ chain.suggestName(_) }
chain.io.d := in.asUInt
chain.io.q.asTypeOf(in)
}
}
class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) {
require(depth > 0, "Depth must be greater than 0.")
override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}"
val chain = List.tabulate(depth) { i =>
Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}")
}
chain.last.io.d := io.d
chain.last.io.en := true.B
(chain.init zip chain.tail).foreach { case (sink, source) =>
sink.io.d := source.io.q
sink.io.en := true.B
}
io.q := chain.head.io.q
}
object AsyncResetShiftReg {
def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T =
AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name)
def apply [T <: Data](in: T, depth: Int, name: Option[String]): T =
apply(in, depth, 0, name)
def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T =
apply(in, depth, init.litValue.toInt, name)
def apply [T <: Data](in: T, depth: Int, init: T): T =
apply (in, depth, init.litValue.toInt, None)
}
File SynchronizerReg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util.{RegEnable, Cat}
/** These wrap behavioral
* shift and next registers into specific modules to allow for
* backend flows to replace or constrain
* them properly when used for CDC synchronization,
* rather than buffering.
*
*
* These are built up of *ResetSynchronizerPrimitiveShiftReg,
* intended to be replaced by the integrator's metastable flops chains or replaced
* at this level if they have a multi-bit wide synchronizer primitive.
* The different types vary in their reset behavior:
* NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin
* AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep
* 1-bit-wide shift registers.
* SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg
*
* [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference.
*
* ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross
* Clock Domains.
*/
object SynchronizerResetType extends Enumeration {
val NonSync, Inferred, Sync, Async = Value
}
// Note: this should not be used directly.
// Use the companion object to generate this with the correct reset type mixin.
private class SynchronizerPrimitiveShiftReg(
sync: Int,
init: Boolean,
resetType: SynchronizerResetType.Value)
extends AbstractPipelineReg(1) {
val initInt = if (init) 1 else 0
val initPostfix = resetType match {
case SynchronizerResetType.NonSync => ""
case _ => s"_i${initInt}"
}
override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}"
val chain = List.tabulate(sync) { i =>
val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B)
reg.suggestName(s"sync_$i")
}
chain.last := io.d.asBool
(chain.init zip chain.tail).foreach { case (sink, source) =>
sink := source
}
io.q := chain.head.asUInt
}
private object SynchronizerPrimitiveShiftReg {
def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = {
val gen: () => SynchronizerPrimitiveShiftReg = resetType match {
case SynchronizerResetType.NonSync =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType)
case SynchronizerResetType.Async =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset
case SynchronizerResetType.Sync =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset
case SynchronizerResetType.Inferred =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType)
}
AbstractPipelineReg(gen(), in)
}
}
// Note: This module may end up with a non-AsyncReset type reset.
// But the Primitives within will always have AsyncReset type.
class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int)
extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
withReset(reset.asAsyncReset){
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async)
}
}
io.q := Cat(output.reverse)
}
object AsyncResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
// Note: This module may end up with a non-Bool type reset.
// But the Primitives within will always have Bool reset type.
@deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2")
class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
withReset(reset.asBool){
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync)
}
}
io.q := Cat(output.reverse)
}
object SyncResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred)
}
io.q := Cat(output.reverse)
}
object ResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}"
val output = Seq.tabulate(w) { i =>
SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync)
}
io.q := Cat(output.reverse)
}
object SynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T =
if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, None)
def apply [T <: Data](in: T): T =
apply (in, 3, None)
}
class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module {
override def desiredName = s"ClockCrossingReg_w${w}"
val io = IO(new Bundle{
val d = Input(UInt(w.W))
val q = Output(UInt(w.W))
val en = Input(Bool())
})
val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en)
io.q := cdc_reg
}
object ClockCrossingReg {
def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = {
val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit))
name.foreach{ cdc_reg.suggestName(_) }
cdc_reg.io.d := in.asUInt
cdc_reg.io.en := en
cdc_reg.io.q.asTypeOf(in)
}
}
| module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_312( // @[SynchronizerReg.scala:68:19]
input clock, // @[SynchronizerReg.scala:68:19]
input reset, // @[SynchronizerReg.scala:68:19]
input io_d, // @[ShiftReg.scala:36:14]
output io_q // @[ShiftReg.scala:36:14]
);
wire io_d_0 = io_d; // @[SynchronizerReg.scala:68:19]
wire _sync_2_T = io_d_0; // @[SynchronizerReg.scala:54:22, :68:19]
wire io_q_0; // @[SynchronizerReg.scala:68:19]
reg sync_0; // @[SynchronizerReg.scala:51:87]
assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19]
reg sync_1; // @[SynchronizerReg.scala:51:87]
reg sync_2; // @[SynchronizerReg.scala:51:87]
always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19]
if (reset) begin // @[SynchronizerReg.scala:68:19]
sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87]
sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87]
sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87]
end
else begin // @[SynchronizerReg.scala:68:19]
sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87]
sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87]
sync_2 <= _sync_2_T; // @[SynchronizerReg.scala:51:87, :54:22]
end
always @(posedge, posedge) |
Generate the Verilog code corresponding to the following Chisel files.
File ShiftRegisterPriorityQueue.scala:
package compressacc
import chisel3._
import chisel3.util._
import chisel3.util._
// TODO : support enq & deq at the same cycle
class PriorityQueueStageIO(keyWidth: Int, value: ValueInfo) extends Bundle {
val output_prev = KeyValue(keyWidth, value)
val output_nxt = KeyValue(keyWidth, value)
val input_prev = Flipped(KeyValue(keyWidth, value))
val input_nxt = Flipped(KeyValue(keyWidth, value))
val cmd = Flipped(Valid(UInt(1.W)))
val insert_here = Input(Bool())
val cur_input_keyval = Flipped(KeyValue(keyWidth, value))
val cur_output_keyval = KeyValue(keyWidth, value)
}
class PriorityQueueStage(keyWidth: Int, value: ValueInfo) extends Module {
val io = IO(new PriorityQueueStageIO(keyWidth, value))
dontTouch(io)
val CMD_DEQ = 0.U
val CMD_ENQ = 1.U
val MAX_VALUE = (1 << keyWidth) - 1
val key_reg = RegInit(MAX_VALUE.U(keyWidth.W))
val value_reg = Reg(value)
io.output_prev.key := key_reg
io.output_prev.value := value_reg
io.output_nxt.key := key_reg
io.output_nxt.value := value_reg
io.cur_output_keyval.key := key_reg
io.cur_output_keyval.value := value_reg
when (io.cmd.valid) {
switch (io.cmd.bits) {
is (CMD_DEQ) {
key_reg := io.input_nxt.key
value_reg := io.input_nxt.value
}
is (CMD_ENQ) {
when (io.insert_here) {
key_reg := io.cur_input_keyval.key
value_reg := io.cur_input_keyval.value
} .elsewhen (key_reg >= io.cur_input_keyval.key) {
key_reg := io.input_prev.key
value_reg := io.input_prev.value
} .otherwise {
// do nothing
}
}
}
}
}
object PriorityQueueStage {
def apply(keyWidth: Int, v: ValueInfo): PriorityQueueStage = new PriorityQueueStage(keyWidth, v)
}
// TODO
// - This design is not scalable as the enqued_keyval is broadcasted to all the stages
// - Add pipeline registers later
class PriorityQueueIO(queSize: Int, keyWidth: Int, value: ValueInfo) extends Bundle {
val cnt_bits = log2Ceil(queSize+1)
val counter = Output(UInt(cnt_bits.W))
val enq = Flipped(Decoupled(KeyValue(keyWidth, value)))
val deq = Decoupled(KeyValue(keyWidth, value))
}
class PriorityQueue(queSize: Int, keyWidth: Int, value: ValueInfo) extends Module {
val keyWidthInternal = keyWidth + 1
val CMD_DEQ = 0.U
val CMD_ENQ = 1.U
val io = IO(new PriorityQueueIO(queSize, keyWidthInternal, value))
dontTouch(io)
val MAX_VALUE = ((1 << keyWidthInternal) - 1).U
val cnt_bits = log2Ceil(queSize+1)
// do not consider cases where we are inserting more entries then the queSize
val counter = RegInit(0.U(cnt_bits.W))
io.counter := counter
val full = (counter === queSize.U)
val empty = (counter === 0.U)
io.deq.valid := !empty
io.enq.ready := !full
when (io.enq.fire) {
counter := counter + 1.U
}
when (io.deq.fire) {
counter := counter - 1.U
}
val cmd_valid = io.enq.valid || io.deq.ready
val cmd = Mux(io.enq.valid, CMD_ENQ, CMD_DEQ)
assert(!(io.enq.valid && io.deq.ready))
val stages = Seq.fill(queSize)(Module(new PriorityQueueStage(keyWidthInternal, value)))
for (i <- 0 until (queSize - 1)) {
stages(i+1).io.input_prev <> stages(i).io.output_nxt
stages(i).io.input_nxt <> stages(i+1).io.output_prev
}
stages(queSize-1).io.input_nxt.key := MAX_VALUE
// stages(queSize-1).io.input_nxt.value :=
stages(queSize-1).io.input_nxt.value.symbol := 0.U
// stages(queSize-1).io.input_nxt.value.child(0) := 0.U
// stages(queSize-1).io.input_nxt.value.child(1) := 0.U
stages(0).io.input_prev.key := io.enq.bits.key
stages(0).io.input_prev.value <> io.enq.bits.value
for (i <- 0 until queSize) {
stages(i).io.cmd.valid := cmd_valid
stages(i).io.cmd.bits := cmd
stages(i).io.cur_input_keyval <> io.enq.bits
}
val is_large_or_equal = WireInit(VecInit(Seq.fill(queSize)(false.B)))
for (i <- 0 until queSize) {
is_large_or_equal(i) := (stages(i).io.cur_output_keyval.key >= io.enq.bits.key)
}
val is_large_or_equal_cat = Wire(UInt(queSize.W))
is_large_or_equal_cat := Cat(is_large_or_equal.reverse)
val insert_here_idx = PriorityEncoder(is_large_or_equal_cat)
for (i <- 0 until queSize) {
when (i.U === insert_here_idx) {
stages(i).io.insert_here := true.B
} .otherwise {
stages(i).io.insert_here := false.B
}
}
io.deq.bits <> stages(0).io.output_prev
}
| module PriorityQueueStage_206( // @[ShiftRegisterPriorityQueue.scala:21:7]
input clock, // @[ShiftRegisterPriorityQueue.scala:21:7]
input reset, // @[ShiftRegisterPriorityQueue.scala:21:7]
output [30:0] io_output_prev_key, // @[ShiftRegisterPriorityQueue.scala:22:14]
output [9:0] io_output_prev_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14]
output [30:0] io_output_nxt_key, // @[ShiftRegisterPriorityQueue.scala:22:14]
output [9:0] io_output_nxt_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14]
input [30:0] io_input_prev_key, // @[ShiftRegisterPriorityQueue.scala:22:14]
input [9:0] io_input_prev_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14]
input [30:0] io_input_nxt_key, // @[ShiftRegisterPriorityQueue.scala:22:14]
input [9:0] io_input_nxt_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14]
input io_cmd_valid, // @[ShiftRegisterPriorityQueue.scala:22:14]
input io_cmd_bits, // @[ShiftRegisterPriorityQueue.scala:22:14]
input io_insert_here, // @[ShiftRegisterPriorityQueue.scala:22:14]
input [30:0] io_cur_input_keyval_key, // @[ShiftRegisterPriorityQueue.scala:22:14]
input [9:0] io_cur_input_keyval_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14]
output [30:0] io_cur_output_keyval_key, // @[ShiftRegisterPriorityQueue.scala:22:14]
output [9:0] io_cur_output_keyval_value_symbol // @[ShiftRegisterPriorityQueue.scala:22:14]
);
wire [30:0] io_input_prev_key_0 = io_input_prev_key; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [9:0] io_input_prev_value_symbol_0 = io_input_prev_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [30:0] io_input_nxt_key_0 = io_input_nxt_key; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [9:0] io_input_nxt_value_symbol_0 = io_input_nxt_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire io_cmd_valid_0 = io_cmd_valid; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire io_cmd_bits_0 = io_cmd_bits; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire io_insert_here_0 = io_insert_here; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [30:0] io_cur_input_keyval_key_0 = io_cur_input_keyval_key; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [9:0] io_cur_input_keyval_value_symbol_0 = io_cur_input_keyval_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [9:0] io_output_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [30:0] io_output_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [9:0] io_output_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [30:0] io_output_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [9:0] io_cur_output_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [30:0] io_cur_output_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
reg [30:0] key_reg; // @[ShiftRegisterPriorityQueue.scala:30:24]
assign io_output_prev_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]
assign io_output_nxt_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]
assign io_cur_output_keyval_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]
reg [9:0] value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:31:22]
assign io_output_prev_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]
assign io_output_nxt_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]
assign io_cur_output_keyval_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]
wire _T_2 = key_reg >= io_cur_input_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24, :52:30]
always @(posedge clock) begin // @[ShiftRegisterPriorityQueue.scala:21:7]
if (reset) // @[ShiftRegisterPriorityQueue.scala:21:7]
key_reg <= 31'h7FFFFFFF; // @[ShiftRegisterPriorityQueue.scala:30:24]
else if (io_cmd_valid_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7]
if (io_cmd_bits_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7]
if (io_insert_here_0) // @[ShiftRegisterPriorityQueue.scala:21:7]
key_reg <= io_cur_input_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]
else if (_T_2) // @[ShiftRegisterPriorityQueue.scala:52:30]
key_reg <= io_input_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]
end
else // @[ShiftRegisterPriorityQueue.scala:21:7]
key_reg <= io_input_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]
end
if (io_cmd_valid_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7]
if (io_cmd_bits_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7]
if (io_insert_here_0) // @[ShiftRegisterPriorityQueue.scala:21:7]
value_reg_symbol <= io_cur_input_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]
else if (_T_2) // @[ShiftRegisterPriorityQueue.scala:52:30]
value_reg_symbol <= io_input_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]
end
else // @[ShiftRegisterPriorityQueue.scala:21:7]
value_reg_symbol <= io_input_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]
end
always @(posedge)
assign io_output_prev_key = io_output_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
assign io_output_prev_value_symbol = io_output_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
assign io_output_nxt_key = io_output_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
assign io_output_nxt_value_symbol = io_output_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
assign io_cur_output_keyval_key = io_cur_output_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
assign io_cur_output_keyval_value_symbol = io_cur_output_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File Monitor.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceLine
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import freechips.rocketchip.diplomacy.EnableMonitors
import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode}
import freechips.rocketchip.util.PlusArg
case class TLMonitorArgs(edge: TLEdge)
abstract class TLMonitorBase(args: TLMonitorArgs) extends Module
{
val io = IO(new Bundle {
val in = Input(new TLBundle(args.edge.bundle))
})
def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit
legalize(io.in, args.edge, reset)
}
object TLMonitor {
def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = {
if (enable) {
EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) }
} else { node }
}
}
class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args)
{
require (args.edge.params(TLMonitorStrictMode) || (! args.edge.params(TestplanTestType).formal))
val cover_prop_class = PropertyClass.Default
//Like assert but can flip to being an assumption for formal verification
def monAssert(cond: Bool, message: String): Unit =
if (monitorDir == MonitorDirection.Monitor) {
assert(cond, message)
} else {
Property(monitorDir, cond, message, PropertyClass.Default)
}
def assume(cond: Bool, message: String): Unit =
if (monitorDir == MonitorDirection.Monitor) {
assert(cond, message)
} else {
Property(monitorDir.flip, cond, message, PropertyClass.Default)
}
def extra = {
args.edge.sourceInfo match {
case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)"
case _ => ""
}
}
def visible(address: UInt, source: UInt, edge: TLEdge) =
edge.client.clients.map { c =>
!c.sourceId.contains(source) ||
c.visibility.map(_.contains(address)).reduce(_ || _)
}.reduce(_ && _)
def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = {
//switch this flag to turn on diplomacy in error messages
def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n"
monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra)
// Reuse these subexpressions to save some firrtl lines
val source_ok = edge.client.contains(bundle.source)
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val mask = edge.full_mask(bundle)
monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility")
//The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B
//TODO: check for acquireT?
when (bundle.opcode === TLMessages.AcquireBlock) {
monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra)
monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra)
monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra)
monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra)
}
when (bundle.opcode === TLMessages.AcquirePerm) {
monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra)
monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra)
monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra)
monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra)
monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra)
}
when (bundle.opcode === TLMessages.Get) {
monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra)
monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra)
monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra)
}
when (bundle.opcode === TLMessages.PutFullData) {
monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra)
monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.PutPartialData) {
monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra)
monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.ArithmeticData) {
monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra)
monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.LogicalData) {
monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra)
monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.Hint) {
monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra)
monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra)
}
}
def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = {
monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra)
monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility")
// Reuse these subexpressions to save some firrtl lines
val address_ok = edge.manager.containsSafe(edge.address(bundle))
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val mask = edge.full_mask(bundle)
val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source
when (bundle.opcode === TLMessages.Probe) {
assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra)
assume (address_ok, "'B' channel Probe carries unmanaged address" + extra)
assume (legal_source, "'B' channel Probe carries source that is not first source" + extra)
assume (is_aligned, "'B' channel Probe address not aligned to size" + extra)
assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra)
assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra)
assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra)
}
when (bundle.opcode === TLMessages.Get) {
monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra)
monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra)
}
when (bundle.opcode === TLMessages.PutFullData) {
monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra)
monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.PutPartialData) {
monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra)
monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.ArithmeticData) {
monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra)
monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra)
monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.LogicalData) {
monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra)
monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra)
monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.Hint) {
monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra)
monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra)
monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra)
}
}
def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = {
monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra)
val source_ok = edge.client.contains(bundle.source)
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val address_ok = edge.manager.containsSafe(edge.address(bundle))
monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility")
when (bundle.opcode === TLMessages.ProbeAck) {
monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra)
monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra)
}
when (bundle.opcode === TLMessages.ProbeAckData) {
monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra)
}
when (bundle.opcode === TLMessages.Release) {
monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra)
monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra)
monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra)
}
when (bundle.opcode === TLMessages.ReleaseData) {
monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra)
monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra)
}
when (bundle.opcode === TLMessages.AccessAck) {
monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra)
monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra)
}
when (bundle.opcode === TLMessages.AccessAckData) {
monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra)
}
when (bundle.opcode === TLMessages.HintAck) {
monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra)
monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra)
}
}
def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = {
assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra)
val source_ok = edge.client.contains(bundle.source)
val sink_ok = bundle.sink < edge.manager.endSinkId.U
val deny_put_ok = edge.manager.mayDenyPut.B
val deny_get_ok = edge.manager.mayDenyGet.B
when (bundle.opcode === TLMessages.ReleaseAck) {
assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra)
assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra)
assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra)
}
when (bundle.opcode === TLMessages.Grant) {
assume (source_ok, "'D' channel Grant carries invalid source ID" + extra)
assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra)
assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra)
assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra)
assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel Grant is denied" + extra)
}
when (bundle.opcode === TLMessages.GrantData) {
assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra)
assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra)
assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra)
assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra)
assume (!bundle.denied || bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra)
assume (deny_get_ok || !bundle.denied, "'D' channel GrantData is denied" + extra)
}
when (bundle.opcode === TLMessages.AccessAck) {
assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel AccessAck is denied" + extra)
}
when (bundle.opcode === TLMessages.AccessAckData) {
assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra)
assume (!bundle.denied || bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra)
assume (deny_get_ok || !bundle.denied, "'D' channel AccessAckData is denied" + extra)
}
when (bundle.opcode === TLMessages.HintAck) {
assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel HintAck is denied" + extra)
}
}
def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = {
val sink_ok = bundle.sink < edge.manager.endSinkId.U
monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra)
}
def legalizeFormat(bundle: TLBundle, edge: TLEdge) = {
when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) }
when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) }
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) }
when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) }
when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) }
} else {
monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra)
monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra)
monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra)
}
}
def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = {
val a_first = edge.first(a.bits, a.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (a.valid && !a_first) {
monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra)
monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra)
monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra)
monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra)
monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra)
}
when (a.fire && a_first) {
opcode := a.bits.opcode
param := a.bits.param
size := a.bits.size
source := a.bits.source
address := a.bits.address
}
}
def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = {
val b_first = edge.first(b.bits, b.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (b.valid && !b_first) {
monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra)
monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra)
monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra)
monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra)
monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra)
}
when (b.fire && b_first) {
opcode := b.bits.opcode
param := b.bits.param
size := b.bits.size
source := b.bits.source
address := b.bits.address
}
}
def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = {
// Symbolic variable
val sym_source = Wire(UInt(edge.client.endSourceId.W))
// TODO: Connect sym_source to a fixed value for simulation and to a
// free wire in formal
sym_source := 0.U
// Type casting Int to UInt
val maxSourceId = Wire(UInt(edge.client.endSourceId.W))
maxSourceId := edge.client.endSourceId.U
// Delayed verison of sym_source
val sym_source_d = Reg(UInt(edge.client.endSourceId.W))
sym_source_d := sym_source
// These will be constraints for FV setup
Property(
MonitorDirection.Monitor,
(sym_source === sym_source_d),
"sym_source should remain stable",
PropertyClass.Default)
Property(
MonitorDirection.Monitor,
(sym_source <= maxSourceId),
"sym_source should take legal value",
PropertyClass.Default)
val my_resp_pend = RegInit(false.B)
val my_opcode = Reg(UInt())
val my_size = Reg(UInt())
val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire)
val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire)
val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source)
val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source)
val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat)
val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend)
when (my_set_resp_pend) {
my_resp_pend := true.B
} .elsewhen (my_clr_resp_pend) {
my_resp_pend := false.B
}
when (my_a_first_beat) {
my_opcode := bundle.a.bits.opcode
my_size := bundle.a.bits.size
}
val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size)
val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode)
val my_resp_opcode_legal = Wire(Bool())
when ((my_resp_opcode === TLMessages.Get) || (my_resp_opcode === TLMessages.ArithmeticData) ||
(my_resp_opcode === TLMessages.LogicalData)) {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData)
} .elsewhen ((my_resp_opcode === TLMessages.PutFullData) || (my_resp_opcode === TLMessages.PutPartialData)) {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck)
} .otherwise {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck)
}
monAssert (IfThen(my_resp_pend, !my_a_first_beat),
"Request message should not be sent with a source ID, for which a response message" +
"is already pending (not received until current cycle) for a prior request message" +
"with the same source ID" + extra)
assume (IfThen(my_clr_resp_pend, (my_set_resp_pend || my_resp_pend)),
"Response message should be accepted with a source ID only if a request message with the" +
"same source ID has been accepted or is being accepted in the current cycle" + extra)
assume (IfThen(my_d_first_beat, (my_a_first_beat || my_resp_pend)),
"Response message should be sent with a source ID only if a request message with the" +
"same source ID has been accepted or is being sent in the current cycle" + extra)
assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)),
"If d_valid is 1, then d_size should be same as a_size of the corresponding request" +
"message" + extra)
assume (IfThen(my_d_first_beat, my_resp_opcode_legal),
"If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" +
"request message" + extra)
}
def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = {
val c_first = edge.first(c.bits, c.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (c.valid && !c_first) {
monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra)
monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra)
monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra)
monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra)
monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra)
}
when (c.fire && c_first) {
opcode := c.bits.opcode
param := c.bits.param
size := c.bits.size
source := c.bits.source
address := c.bits.address
}
}
def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = {
val d_first = edge.first(d.bits, d.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val sink = Reg(UInt())
val denied = Reg(Bool())
when (d.valid && !d_first) {
assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra)
assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra)
assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra)
assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra)
assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra)
assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra)
}
when (d.fire && d_first) {
opcode := d.bits.opcode
param := d.bits.param
size := d.bits.size
source := d.bits.source
sink := d.bits.sink
denied := d.bits.denied
}
}
def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = {
legalizeMultibeatA(bundle.a, edge)
legalizeMultibeatD(bundle.d, edge)
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
legalizeMultibeatB(bundle.b, edge)
legalizeMultibeatC(bundle.c, edge)
}
}
//This is left in for almond which doesn't adhere to the tilelink protocol
@deprecated("Use legalizeADSource instead if possible","")
def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = {
val inflight = RegInit(0.U(edge.client.endSourceId.W))
val a_first = edge.first(bundle.a.bits, bundle.a.fire)
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
val a_set = WireInit(0.U(edge.client.endSourceId.W))
when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) {
a_set := UIntToOH(bundle.a.bits.source)
assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra)
}
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
assume((a_set | inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra)
}
if (edge.manager.minLatency > 0) {
assume(a_set =/= d_clr || !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra)
}
inflight := (inflight | a_set) & ~d_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
assert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = {
val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset)
val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything
val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size)
val log_a_size_bus_size = log2Ceil(a_size_bus_size)
def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits
val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error
inflight.suggestName("inflight")
val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
inflight_opcodes.suggestName("inflight_opcodes")
val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
inflight_sizes.suggestName("inflight_sizes")
val a_first = edge.first(bundle.a.bits, bundle.a.fire)
a_first.suggestName("a_first")
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
d_first.suggestName("d_first")
val a_set = WireInit(0.U(edge.client.endSourceId.W))
val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
a_set.suggestName("a_set")
a_set_wo_ready.suggestName("a_set_wo_ready")
val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
a_opcodes_set.suggestName("a_opcodes_set")
val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
a_sizes_set.suggestName("a_sizes_set")
val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W))
a_opcode_lookup.suggestName("a_opcode_lookup")
a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U
val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W))
a_size_lookup.suggestName("a_size_lookup")
a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U
val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant))
val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant))
val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W))
a_opcodes_set_interm.suggestName("a_opcodes_set_interm")
val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W))
a_sizes_set_interm.suggestName("a_sizes_set_interm")
when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) {
a_set_wo_ready := UIntToOH(bundle.a.bits.source)
}
when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) {
a_set := UIntToOH(bundle.a.bits.source)
a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) | 1.U
a_sizes_set_interm := (bundle.a.bits.size << 1.U) | 1.U
a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U)
a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U)
monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra)
}
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
d_clr.suggestName("d_clr")
d_clr_wo_ready.suggestName("d_clr_wo_ready")
val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
d_opcodes_clr.suggestName("d_opcodes_clr")
val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
d_sizes_clr.suggestName("d_sizes_clr")
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr_wo_ready := UIntToOH(bundle.d.bits.source)
}
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U)
d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U)
}
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source)
assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra)
when (same_cycle_resp) {
assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) ||
(bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra)
assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra)
} .otherwise {
assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) ||
(bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra)
assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra)
}
}
when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) {
assume((!bundle.d.ready) || bundle.a.ready, "ready check")
}
if (edge.manager.minLatency > 0) {
assume(a_set_wo_ready =/= d_clr_wo_ready || !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra)
}
inflight := (inflight | a_set) & ~d_clr
inflight_opcodes := (inflight_opcodes | a_opcodes_set) & ~d_opcodes_clr
inflight_sizes := (inflight_sizes | a_sizes_set) & ~d_sizes_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = {
val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset)
val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything
val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size)
val log_c_size_bus_size = log2Ceil(c_size_bus_size)
def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits
val inflight = RegInit(0.U((2 max edge.client.endSourceId).W))
val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
inflight.suggestName("inflight")
inflight_opcodes.suggestName("inflight_opcodes")
inflight_sizes.suggestName("inflight_sizes")
val c_first = edge.first(bundle.c.bits, bundle.c.fire)
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
c_first.suggestName("c_first")
d_first.suggestName("d_first")
val c_set = WireInit(0.U(edge.client.endSourceId.W))
val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
c_set.suggestName("c_set")
c_set_wo_ready.suggestName("c_set_wo_ready")
c_opcodes_set.suggestName("c_opcodes_set")
c_sizes_set.suggestName("c_sizes_set")
val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W))
val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W))
c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U
c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U
c_opcode_lookup.suggestName("c_opcode_lookup")
c_size_lookup.suggestName("c_size_lookup")
val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W))
val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W))
c_opcodes_set_interm.suggestName("c_opcodes_set_interm")
c_sizes_set_interm.suggestName("c_sizes_set_interm")
when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) {
c_set_wo_ready := UIntToOH(bundle.c.bits.source)
}
when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) {
c_set := UIntToOH(bundle.c.bits.source)
c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) | 1.U
c_sizes_set_interm := (bundle.c.bits.size << 1.U) | 1.U
c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U)
c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U)
monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra)
}
val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck || bundle.c.bits.opcode === TLMessages.ProbeAckData
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
d_clr.suggestName("d_clr")
d_clr_wo_ready.suggestName("d_clr_wo_ready")
d_opcodes_clr.suggestName("d_opcodes_clr")
d_sizes_clr.suggestName("d_sizes_clr")
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
d_clr_wo_ready := UIntToOH(bundle.d.bits.source)
}
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U)
d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U)
}
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source)
assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra)
when (same_cycle_resp) {
assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra)
} .otherwise {
assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra)
}
}
when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) {
assume((!bundle.d.ready) || bundle.c.ready, "ready check")
}
if (edge.manager.minLatency > 0) {
when (c_set_wo_ready.orR) {
assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra)
}
}
inflight := (inflight | c_set) & ~d_clr
inflight_opcodes := (inflight_opcodes | c_opcodes_set) & ~d_opcodes_clr
inflight_sizes := (inflight_sizes | c_sizes_set) & ~d_sizes_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.c.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = {
val inflight = RegInit(0.U(edge.manager.endSinkId.W))
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
val e_first = true.B
val d_set = WireInit(0.U(edge.manager.endSinkId.W))
when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) {
d_set := UIntToOH(bundle.d.bits.sink)
assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra)
}
val e_clr = WireInit(0.U(edge.manager.endSinkId.W))
when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) {
e_clr := UIntToOH(bundle.e.bits.sink)
monAssert((d_set | inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra)
}
// edge.client.minLatency applies to BC, not DE
inflight := (inflight | d_set) & ~e_clr
}
def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = {
val sourceBits = log2Ceil(edge.client.endSourceId)
val tooBig = 14 // >16kB worth of flight information gets to be too much
if (sourceBits > tooBig) {
println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked")
} else {
if (args.edge.params(TestplanTestType).simulation) {
if (args.edge.params(TLMonitorStrictMode)) {
legalizeADSource(bundle, edge)
legalizeCDSource(bundle, edge)
} else {
legalizeADSourceOld(bundle, edge)
}
}
if (args.edge.params(TestplanTestType).formal) {
legalizeADSourceFormal(bundle, edge)
}
}
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
// legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize...
val sinkBits = log2Ceil(edge.manager.endSinkId)
if (sinkBits > tooBig) {
println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked")
} else {
legalizeDESink(bundle, edge)
}
}
}
def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = {
legalizeFormat (bundle, edge)
legalizeMultibeat (bundle, edge)
legalizeUnique (bundle, edge)
}
}
File PlusArg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.experimental._
import chisel3.util.HasBlackBoxResource
@deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05")
case class PlusArgInfo(default: BigInt, docstring: String)
/** Case class for PlusArg information
*
* @tparam A scala type of the PlusArg value
* @param default optional default value
* @param docstring text to include in the help
* @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT)
*/
private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String)
/** Typeclass for converting a type to a doctype string
* @tparam A some type
*/
trait Doctypeable[A] {
/** Return the doctype string for some option */
def toDoctype(a: Option[A]): String
}
/** Object containing implementations of the Doctypeable typeclass */
object Doctypes {
/** Converts an Int => "INT" */
implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" }
/** Converts a BigInt => "INT" */
implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" }
/** Converts a String => "STRING" */
implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" }
}
class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map(
"FORMAT" -> StringParam(format),
"DEFAULT" -> IntParam(default),
"WIDTH" -> IntParam(width)
)) with HasBlackBoxResource {
val io = IO(new Bundle {
val out = Output(UInt(width.W))
})
addResource("/vsrc/plusarg_reader.v")
}
/* This wrapper class has no outputs, making it clear it is a simulation-only construct */
class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module {
val io = IO(new Bundle {
val count = Input(UInt(width.W))
})
val max = Module(new plusarg_reader(format, default, docstring, width)).io.out
when (max > 0.U) {
assert (io.count < max, s"Timeout exceeded: $docstring")
}
}
import Doctypes._
object PlusArg
{
/** PlusArg("foo") will return 42.U if the simulation is run with +foo=42
* Do not use this as an initial register value. The value is set in an
* initial block and thus accessing it from another initial is racey.
* Add a docstring to document the arg, which can be dumped in an elaboration
* pass.
*/
def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = {
PlusArgArtefacts.append(name, Some(default), docstring)
Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out
}
/** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert
* to kill the simulation when count exceeds the specified integer argument.
* Default 0 will never assert.
*/
def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = {
PlusArgArtefacts.append(name, Some(default), docstring)
Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count
}
}
object PlusArgArtefacts {
private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty
/* Add a new PlusArg */
@deprecated(
"Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08",
"Rocket Chip 2020.05"
)
def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring)
/** Add a new PlusArg
*
* @tparam A scala type of the PlusArg value
* @param name name for the PlusArg
* @param default optional default value
* @param docstring text to include in the help
*/
def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit =
artefacts = artefacts ++
Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default)))
/* From plus args, generate help text */
private def serializeHelp_cHeader(tab: String = ""): String = artefacts
.map{ case(arg, info) =>
s"""|$tab+$arg=${info.doctype}\\n\\
|$tab${" "*20}${info.docstring}\\n\\
|""".stripMargin ++ info.default.map{ case default =>
s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("")
}.toSeq.mkString("\\n\\\n") ++ "\""
/* From plus args, generate a char array of their names */
private def serializeArray_cHeader(tab: String = ""): String = {
val prettyTab = tab + " " * 44 // Length of 'static const ...'
s"${tab}static const char * verilog_plusargs [] = {\\\n" ++
artefacts
.map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" }
.mkString("")++
s"${prettyTab}0};"
}
/* Generate C code to be included in emulator.cc that helps with
* argument parsing based on available Verilog PlusArgs */
def serialize_cHeader(): String =
s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\
|${serializeHelp_cHeader(" "*7)}
|${serializeArray_cHeader()}
|""".stripMargin
}
File package.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip
import chisel3._
import chisel3.util._
import scala.math.min
import scala.collection.{immutable, mutable}
package object util {
implicit class UnzippableOption[S, T](val x: Option[(S, T)]) {
def unzip = (x.map(_._1), x.map(_._2))
}
implicit class UIntIsOneOf(private val x: UInt) extends AnyVal {
def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR
def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq)
}
implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal {
/** Like Vec.apply(idx), but tolerates indices of mismatched width */
def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0))
}
implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal {
def apply(idx: UInt): T = {
if (x.size <= 1) {
x.head
} else if (!isPow2(x.size)) {
// For non-power-of-2 seqs, reflect elements to simplify decoder
(x ++ x.takeRight(x.size & -x.size)).toSeq(idx)
} else {
// Ignore MSBs of idx
val truncIdx =
if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx
else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0)
x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) }
}
}
def extract(idx: UInt): T = VecInit(x).extract(idx)
def asUInt: UInt = Cat(x.map(_.asUInt).reverse)
def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n)
def rotate(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n)
def rotateRight(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
}
// allow bitwise ops on Seq[Bool] just like UInt
implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal {
def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b }
def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b }
def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b }
def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x
def >> (n: Int): Seq[Bool] = x drop n
def unary_~ : Seq[Bool] = x.map(!_)
def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_)
def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_)
def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_)
private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B)
}
implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal {
def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable))
def getElements: Seq[Element] = x match {
case e: Element => Seq(e)
case a: Aggregate => a.getElements.flatMap(_.getElements)
}
}
/** Any Data subtype that has a Bool member named valid. */
type DataCanBeValid = Data { val valid: Bool }
implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal {
def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable)
}
implicit class StringToAugmentedString(private val x: String) extends AnyVal {
/** converts from camel case to to underscores, also removing all spaces */
def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") {
case (acc, c) if c.isUpper => acc + "_" + c.toLower
case (acc, c) if c == ' ' => acc
case (acc, c) => acc + c
}
/** converts spaces or underscores to hyphens, also lowering case */
def kebab: String = x.toLowerCase map {
case ' ' => '-'
case '_' => '-'
case c => c
}
def named(name: Option[String]): String = {
x + name.map("_named_" + _ ).getOrElse("_with_no_name")
}
def named(name: String): String = named(Some(name))
}
implicit def uintToBitPat(x: UInt): BitPat = BitPat(x)
implicit def wcToUInt(c: WideCounter): UInt = c.value
implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal {
def sextTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x)
}
def padTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(0.U((n - x.getWidth).W), x)
}
// shifts left by n if n >= 0, or right by -n if n < 0
def << (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << n(w-1, 0)
Mux(n(w), shifted >> (1 << w), shifted)
}
// shifts right by n if n >= 0, or left by -n if n < 0
def >> (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << (1 << w) >> n(w-1, 0)
Mux(n(w), shifted, shifted >> (1 << w))
}
// Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts
def extract(hi: Int, lo: Int): UInt = {
require(hi >= lo-1)
if (hi == lo-1) 0.U
else x(hi, lo)
}
// Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts
def extractOption(hi: Int, lo: Int): Option[UInt] = {
require(hi >= lo-1)
if (hi == lo-1) None
else Some(x(hi, lo))
}
// like x & ~y, but first truncate or zero-extend y to x's width
def andNot(y: UInt): UInt = x & ~(y | (x & 0.U))
def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n)
def rotateRight(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r))
}
}
def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n))
def rotateLeft(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r))
}
}
// compute (this + y) % n, given (this < n) and (y < n)
def addWrap(y: UInt, n: Int): UInt = {
val z = x +& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0)
}
// compute (this - y) % n, given (this < n) and (y < n)
def subWrap(y: UInt, n: Int): UInt = {
val z = x -& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0)
}
def grouped(width: Int): Seq[UInt] =
(0 until x.getWidth by width).map(base => x(base + width - 1, base))
def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds
def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x)
// Like >=, but prevents x-prop for ('x >= 0)
def >== (y: UInt): Bool = x >= y || y === 0.U
}
implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal {
def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y)
def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y)
}
implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal {
def toInt: Int = if (x) 1 else 0
// this one's snagged from scalaz
def option[T](z: => T): Option[T] = if (x) Some(z) else None
}
implicit class IntToAugmentedInt(private val x: Int) extends AnyVal {
// exact log2
def log2: Int = {
require(isPow2(x))
log2Ceil(x)
}
}
def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x)
def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x))
def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0)
def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1)
def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None
// Fill 1s from low bits to high bits
def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth)
def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0))
helper(1, x)(width-1, 0)
}
// Fill 1s form high bits to low bits
def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth)
def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x >> s))
helper(1, x)(width-1, 0)
}
def OptimizationBarrier[T <: Data](in: T): T = {
val barrier = Module(new Module {
val io = IO(new Bundle {
val x = Input(chiselTypeOf(in))
val y = Output(chiselTypeOf(in))
})
io.y := io.x
override def desiredName = s"OptimizationBarrier_${in.typeName}"
})
barrier.io.x := in
barrier.io.y
}
/** Similar to Seq.groupBy except this returns a Seq instead of a Map
* Useful for deterministic code generation
*/
def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = {
val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]]
for (x <- xs) {
val key = f(x)
val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A])
l += x
}
map.view.map({ case (k, vs) => k -> vs.toList }).toList
}
def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match {
case 1 => List.fill(n)(in.head)
case x if x == n => in
case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in")
}
// HeterogeneousBag moved to standalond diplomacy
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts)
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag
}
File Parameters.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.diplomacy
import chisel3._
import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor}
import freechips.rocketchip.util.ShiftQueue
/** Options for describing the attributes of memory regions */
object RegionType {
// Define the 'more relaxed than' ordering
val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS)
sealed trait T extends Ordered[T] {
def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this)
}
case object CACHED extends T // an intermediate agent may have cached a copy of the region for you
case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided
case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible
case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached
case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects
case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed
case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively
}
// A non-empty half-open range; [start, end)
case class IdRange(start: Int, end: Int) extends Ordered[IdRange]
{
require (start >= 0, s"Ids cannot be negative, but got: $start.")
require (start <= end, "Id ranges cannot be negative.")
def compare(x: IdRange) = {
val primary = (this.start - x.start).signum
val secondary = (x.end - this.end).signum
if (primary != 0) primary else secondary
}
def overlaps(x: IdRange) = start < x.end && x.start < end
def contains(x: IdRange) = start <= x.start && x.end <= end
def contains(x: Int) = start <= x && x < end
def contains(x: UInt) =
if (size == 0) {
false.B
} else if (size == 1) { // simple comparison
x === start.U
} else {
// find index of largest different bit
val largestDeltaBit = log2Floor(start ^ (end-1))
val smallestCommonBit = largestDeltaBit + 1 // may not exist in x
val uncommonMask = (1 << smallestCommonBit) - 1
val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0)
// the prefix must match exactly (note: may shift ALL bits away)
(x >> smallestCommonBit) === (start >> smallestCommonBit).U &&
// firrtl constant prop range analysis can eliminate these two:
(start & uncommonMask).U <= uncommonBits &&
uncommonBits <= ((end-1) & uncommonMask).U
}
def shift(x: Int) = IdRange(start+x, end+x)
def size = end - start
def isEmpty = end == start
def range = start until end
}
object IdRange
{
def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else {
val ranges = s.sorted
(ranges.tail zip ranges.init) find { case (a, b) => a overlaps b }
}
}
// An potentially empty inclusive range of 2-powers [min, max] (in bytes)
case class TransferSizes(min: Int, max: Int)
{
def this(x: Int) = this(x, x)
require (min <= max, s"Min transfer $min > max transfer $max")
require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)")
require (max == 0 || isPow2(max), s"TransferSizes must be a power of 2, got: $max")
require (min == 0 || isPow2(min), s"TransferSizes must be a power of 2, got: $min")
require (max == 0 || min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)")
def none = min == 0
def contains(x: Int) = isPow2(x) && min <= x && x <= max
def containsLg(x: Int) = contains(1 << x)
def containsLg(x: UInt) =
if (none) false.B
else if (min == max) { log2Ceil(min).U === x }
else { log2Ceil(min).U <= x && x <= log2Ceil(max).U }
def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max)
def intersect(x: TransferSizes) =
if (x.max < min || max < x.min) TransferSizes.none
else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max))
// Not a union, because the result may contain sizes contained by neither term
// NOT TO BE CONFUSED WITH COVERPOINTS
def mincover(x: TransferSizes) = {
if (none) {
x
} else if (x.none) {
this
} else {
TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max))
}
}
override def toString() = "TransferSizes[%d, %d]".format(min, max)
}
object TransferSizes {
def apply(x: Int) = new TransferSizes(x)
val none = new TransferSizes(0)
def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _)
def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _)
implicit def asBool(x: TransferSizes) = !x.none
}
// AddressSets specify the address space managed by the manager
// Base is the base address, and mask are the bits consumed by the manager
// e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff
// e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ...
case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet]
{
// Forbid misaligned base address (and empty sets)
require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}")
require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous
// We do allow negative mask (=> ignore all high bits)
def contains(x: BigInt) = ((x ^ base) & ~mask) == 0
def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S
// turn x into an address contained in this set
def legalize(x: UInt): UInt = base.U | (mask.U & x)
// overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1)
def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0
// contains iff bitwise: x.mask => mask && contains(x.base)
def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0
// The number of bytes to which the manager must be aligned
def alignment = ((mask + 1) & ~mask)
// Is this a contiguous memory range
def contiguous = alignment == mask+1
def finite = mask >= 0
def max = { require (finite, "Max cannot be calculated on infinite mask"); base | mask }
// Widen the match function to ignore all bits in imask
def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask)
// Return an AddressSet that only contains the addresses both sets contain
def intersect(x: AddressSet): Option[AddressSet] = {
if (!overlaps(x)) {
None
} else {
val r_mask = mask & x.mask
val r_base = base | x.base
Some(AddressSet(r_base, r_mask))
}
}
def subtract(x: AddressSet): Seq[AddressSet] = {
intersect(x) match {
case None => Seq(this)
case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit =>
val nmask = (mask & (bit-1)) | remove.mask
val nbase = (remove.base ^ bit) & ~nmask
AddressSet(nbase, nmask)
}
}
}
// AddressSets have one natural Ordering (the containment order, if contiguous)
def compare(x: AddressSet) = {
val primary = (this.base - x.base).signum // smallest address first
val secondary = (x.mask - this.mask).signum // largest mask first
if (primary != 0) primary else secondary
}
// We always want to see things in hex
override def toString() = {
if (mask >= 0) {
"AddressSet(0x%x, 0x%x)".format(base, mask)
} else {
"AddressSet(0x%x, ~0x%x)".format(base, ~mask)
}
}
def toRanges = {
require (finite, "Ranges cannot be calculated on infinite mask")
val size = alignment
val fragments = mask & ~(size-1)
val bits = bitIndexes(fragments)
(BigInt(0) until (BigInt(1) << bits.size)).map { i =>
val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) }
AddressRange(off, size)
}
}
}
object AddressSet
{
val everything = AddressSet(0, -1)
def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = {
if (size == 0) tail.reverse else {
val maxBaseAlignment = base & (-base) // 0 for infinite (LSB)
val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size
val step =
if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment)
maxSizeAlignment else maxBaseAlignment
misaligned(base+step, size-step, AddressSet(base, step-1) +: tail)
}
}
def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = {
// Pair terms up by ignoring 'bit'
seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) =>
if (seq.size == 1) {
seq.head // singleton -> unaffected
} else {
key.copy(mask = key.mask | bit) // pair - widen mask by bit
}
}.toList
}
def unify(seq: Seq[AddressSet]): Seq[AddressSet] = {
val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _)
AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted
}
def enumerateMask(mask: BigInt): Seq[BigInt] = {
def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] =
if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail)
helper(0, Nil)
}
def enumerateBits(mask: BigInt): Seq[BigInt] = {
def helper(x: BigInt): Seq[BigInt] = {
if (x == 0) {
Nil
} else {
val bit = x & (-x)
bit +: helper(x & ~bit)
}
}
helper(mask)
}
}
case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean)
{
require (depth >= 0, "Buffer depth must be >= 0")
def isDefined = depth > 0
def latency = if (isDefined && !flow) 1 else 0
def apply[T <: Data](x: DecoupledIO[T]) =
if (isDefined) Queue(x, depth, flow=flow, pipe=pipe)
else x
def irrevocable[T <: Data](x: ReadyValidIO[T]) =
if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe)
else x
def sq[T <: Data](x: DecoupledIO[T]) =
if (!isDefined) x else {
val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe))
sq.io.enq <> x
sq.io.deq
}
override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "")
}
object BufferParams
{
implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false)
val default = BufferParams(2)
val none = BufferParams(0)
val flow = BufferParams(1, true, false)
val pipe = BufferParams(1, false, true)
}
case class TriStateValue(value: Boolean, set: Boolean)
{
def update(orig: Boolean) = if (set) value else orig
}
object TriStateValue
{
implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true)
def unset = TriStateValue(false, false)
}
trait DirectedBuffers[T] {
def copyIn(x: BufferParams): T
def copyOut(x: BufferParams): T
def copyInOut(x: BufferParams): T
}
trait IdMapEntry {
def name: String
def from: IdRange
def to: IdRange
def isCache: Boolean
def requestFifo: Boolean
def maxTransactionsInFlight: Option[Int]
def pretty(fmt: String) =
if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5
fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "")
} else {
fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "")
}
}
abstract class IdMap[T <: IdMapEntry] {
protected val fmt: String
val mapping: Seq[T]
def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n")
}
File Edges.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.util._
class TLEdge(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdgeParameters(client, manager, params, sourceInfo)
{
def isAligned(address: UInt, lgSize: UInt): Bool = {
if (maxLgSize == 0) true.B else {
val mask = UIntToOH1(lgSize, maxLgSize)
(address & mask) === 0.U
}
}
def mask(address: UInt, lgSize: UInt): UInt =
MaskGen(address, lgSize, manager.beatBytes)
def staticHasData(bundle: TLChannel): Option[Boolean] = {
bundle match {
case _:TLBundleA => {
// Do there exist A messages with Data?
val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial
// Do there exist A messages without Data?
val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint
// Statically optimize the case where hasData is a constant
if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None
}
case _:TLBundleB => {
// Do there exist B messages with Data?
val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial
// Do there exist B messages without Data?
val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint
// Statically optimize the case where hasData is a constant
if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None
}
case _:TLBundleC => {
// Do there eixst C messages with Data?
val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe
// Do there exist C messages without Data?
val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe
if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None
}
case _:TLBundleD => {
// Do there eixst D messages with Data?
val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB
// Do there exist D messages without Data?
val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT
if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None
}
case _:TLBundleE => Some(false)
}
}
def isRequest(x: TLChannel): Bool = {
x match {
case a: TLBundleA => true.B
case b: TLBundleB => true.B
case c: TLBundleC => c.opcode(2) && c.opcode(1)
// opcode === TLMessages.Release ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(2) && !d.opcode(1)
// opcode === TLMessages.Grant ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
}
def isResponse(x: TLChannel): Bool = {
x match {
case a: TLBundleA => false.B
case b: TLBundleB => false.B
case c: TLBundleC => !c.opcode(2) || !c.opcode(1)
// opcode =/= TLMessages.Release &&
// opcode =/= TLMessages.ReleaseData
case d: TLBundleD => true.B // Grant isResponse + isRequest
case e: TLBundleE => true.B
}
}
def hasData(x: TLChannel): Bool = {
val opdata = x match {
case a: TLBundleA => !a.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case b: TLBundleB => !b.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case c: TLBundleC => c.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.ProbeAckData ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
staticHasData(x).map(_.B).getOrElse(opdata)
}
def opcode(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.opcode
case b: TLBundleB => b.opcode
case c: TLBundleC => c.opcode
case d: TLBundleD => d.opcode
}
}
def param(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.param
case b: TLBundleB => b.param
case c: TLBundleC => c.param
case d: TLBundleD => d.param
}
}
def size(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.size
case b: TLBundleB => b.size
case c: TLBundleC => c.size
case d: TLBundleD => d.size
}
}
def data(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.data
case b: TLBundleB => b.data
case c: TLBundleC => c.data
case d: TLBundleD => d.data
}
}
def corrupt(x: TLDataChannel): Bool = {
x match {
case a: TLBundleA => a.corrupt
case b: TLBundleB => b.corrupt
case c: TLBundleC => c.corrupt
case d: TLBundleD => d.corrupt
}
}
def mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.mask
case b: TLBundleB => b.mask
case c: TLBundleC => mask(c.address, c.size)
}
}
def full_mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => mask(a.address, a.size)
case b: TLBundleB => mask(b.address, b.size)
case c: TLBundleC => mask(c.address, c.size)
}
}
def address(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.address
case b: TLBundleB => b.address
case c: TLBundleC => c.address
}
}
def source(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.source
case b: TLBundleB => b.source
case c: TLBundleC => c.source
case d: TLBundleD => d.source
}
}
def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes)
def addr_lo(x: UInt): UInt =
if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0)
def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x))
def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x))
def numBeats(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 1.U
case bundle: TLDataChannel => {
val hasData = this.hasData(bundle)
val size = this.size(bundle)
val cutoff = log2Ceil(manager.beatBytes)
val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U
val decode = UIntToOH(size, maxLgSize+1) >> cutoff
Mux(hasData, decode | small.asUInt, 1.U)
}
}
}
def numBeats1(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 0.U
case bundle: TLDataChannel => {
if (maxLgSize == 0) {
0.U
} else {
val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes)
Mux(hasData(bundle), decode, 0.U)
}
}
}
}
def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val beats1 = numBeats1(bits)
val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W))
val counter1 = counter - 1.U
val first = counter === 0.U
val last = counter === 1.U || beats1 === 0.U
val done = last && fire
val count = (beats1 & ~counter1)
when (fire) {
counter := Mux(first, beats1, counter1)
}
(first, last, done, count)
}
def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1
def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire)
def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid)
def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2
def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire)
def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid)
def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3
def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire)
def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid)
def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3)
}
def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire)
def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid)
def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4)
}
def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire)
def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid)
def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes))
}
def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire)
def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid)
// Does the request need T permissions to be executed?
def needT(a: TLBundleA): Bool = {
val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLPermissions.NtoB -> false.B,
TLPermissions.NtoT -> true.B,
TLPermissions.BtoT -> true.B))
MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array(
TLMessages.PutFullData -> true.B,
TLMessages.PutPartialData -> true.B,
TLMessages.ArithmeticData -> true.B,
TLMessages.LogicalData -> true.B,
TLMessages.Get -> false.B,
TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLHints.PREFETCH_READ -> false.B,
TLHints.PREFETCH_WRITE -> true.B)),
TLMessages.AcquireBlock -> acq_needT,
TLMessages.AcquirePerm -> acq_needT))
}
// This is a very expensive circuit; use only if you really mean it!
def inFlight(x: TLBundle): (UInt, UInt) = {
val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W))
val bce = manager.anySupportAcquireB && client.anySupportProbe
val (a_first, a_last, _) = firstlast(x.a)
val (b_first, b_last, _) = firstlast(x.b)
val (c_first, c_last, _) = firstlast(x.c)
val (d_first, d_last, _) = firstlast(x.d)
val (e_first, e_last, _) = firstlast(x.e)
val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits))
val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits))
val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits))
val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits))
val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits))
val a_inc = x.a.fire && a_first && a_request
val b_inc = x.b.fire && b_first && b_request
val c_inc = x.c.fire && c_first && c_request
val d_inc = x.d.fire && d_first && d_request
val e_inc = x.e.fire && e_first && e_request
val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil))
val a_dec = x.a.fire && a_last && a_response
val b_dec = x.b.fire && b_last && b_response
val c_dec = x.c.fire && c_last && c_response
val d_dec = x.d.fire && d_last && d_response
val e_dec = x.e.fire && e_last && e_response
val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil))
val next_flight = flight + PopCount(inc) - PopCount(dec)
flight := next_flight
(flight, next_flight)
}
def prettySourceMapping(context: String): String = {
s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n"
}
}
class TLEdgeOut(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
// Transfers
def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquireBlock
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquirePerm
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.Release
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ReleaseData
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) =
Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B)
def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAck
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions, data)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAckData
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B)
def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink)
def GrantAck(toSink: UInt): TLBundleE = {
val e = Wire(new TLBundleE(bundle))
e.sink := toSink
e
}
// Accesses
def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsGetFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Get
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutFullFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutFullData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, mask, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutPartialFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutPartialData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = {
require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsArithmeticFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.ArithmeticData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsLogicalFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.LogicalData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = {
require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsHintFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Hint
a.param := param
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data)
def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAckData
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size)
def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.HintAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
}
class TLEdgeIn(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = {
val todo = x.filter(!_.isEmpty)
val heads = todo.map(_.head)
val tails = todo.map(_.tail)
if (todo.isEmpty) Nil else { heads +: myTranspose(tails) }
}
// Transfers
def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = {
require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}")
val legal = client.supportsProbe(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Probe
b.param := capPermissions
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.Grant
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.GrantData
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B)
def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.ReleaseAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
// Accesses
def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = {
require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsGet(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Get
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsPutFull(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutFullData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, mask, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsPutPartial(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutPartialData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsArithmetic(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.ArithmeticData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsLogical(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.LogicalData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = {
require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsHint(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Hint
b.param := param
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size)
def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied)
def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data)
def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAckData
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B)
def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied)
def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B)
def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.HintAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
}
| module TLMonitor_42( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14]
input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input [4:0] io_in_a_bits_source, // @[Monitor.scala:20:14]
input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [15:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input io_in_a_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14]
input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input [4:0] io_in_d_bits_source, // @[Monitor.scala:20:14]
input [3:0] io_in_d_bits_sink, // @[Monitor.scala:20:14]
input io_in_d_bits_denied, // @[Monitor.scala:20:14]
input io_in_d_bits_corrupt // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire [26:0] _GEN = {23'h0, io_in_a_bits_size}; // @[package.scala:243:71]
wire _a_first_T_1 = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35]
reg [7:0] a_first_counter; // @[Edges.scala:229:27]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [2:0] param; // @[Monitor.scala:388:22]
reg [3:0] size; // @[Monitor.scala:389:22]
reg [4:0] source; // @[Monitor.scala:390:22]
reg [31:0] address; // @[Monitor.scala:391:22]
reg [7:0] d_first_counter; // @[Edges.scala:229:27]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [1:0] param_1; // @[Monitor.scala:539:22]
reg [3:0] size_1; // @[Monitor.scala:540:22]
reg [4:0] source_1; // @[Monitor.scala:541:22]
reg [3:0] sink; // @[Monitor.scala:542:22]
reg denied; // @[Monitor.scala:543:22]
reg [31:0] inflight; // @[Monitor.scala:614:27]
reg [127:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [255:0] inflight_sizes; // @[Monitor.scala:618:33]
reg [7:0] a_first_counter_1; // @[Edges.scala:229:27]
wire a_first_1 = a_first_counter_1 == 8'h0; // @[Edges.scala:229:27, :231:25]
reg [7:0] d_first_counter_1; // @[Edges.scala:229:27]
wire d_first_1 = d_first_counter_1 == 8'h0; // @[Edges.scala:229:27, :231:25]
wire [31:0] _GEN_0 = {27'h0, io_in_a_bits_source}; // @[OneHot.scala:58:35]
wire _GEN_1 = _a_first_T_1 & a_first_1; // @[Decoupled.scala:51:35]
wire d_release_ack = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala:673:46]
wire _GEN_2 = io_in_d_bits_opcode != 3'h6; // @[Monitor.scala:673:46, :674:74]
wire [31:0] _GEN_3 = {27'h0, io_in_d_bits_source}; // @[OneHot.scala:58:35]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
reg [31:0] inflight_1; // @[Monitor.scala:726:35]
reg [255:0] inflight_sizes_1; // @[Monitor.scala:728:35]
reg [7:0] d_first_counter_2; // @[Edges.scala:229:27]
wire d_first_2 = d_first_counter_2 == 8'h0; // @[Edges.scala:229:27, :231:25]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27] |
Generate the Verilog code corresponding to the following Chisel files.
File primitives.scala:
/*============================================================================
This Chisel source file is part of a pre-release version of the HardFloat IEEE
Floating-Point Arithmetic Package, by John R. Hauser (with some contributions
from Yunsup Lee and Andrew Waterman, mainly concerning testing).
Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
University of California. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
package hardfloat
import chisel3._
import chisel3.util._
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
object lowMask
{
def apply(in: UInt, topBound: BigInt, bottomBound: BigInt): UInt =
{
require(topBound != bottomBound)
val numInVals = BigInt(1)<<in.getWidth
if (topBound < bottomBound) {
lowMask(~in, numInVals - 1 - topBound, numInVals - 1 - bottomBound)
} else if (numInVals > 64 /* Empirical */) {
// For simulation performance, we should avoid generating
// exteremely wide shifters, so we divide and conquer.
// Empirically, this does not impact synthesis QoR.
val mid = numInVals / 2
val msb = in(in.getWidth - 1)
val lsbs = in(in.getWidth - 2, 0)
if (mid < topBound) {
if (mid <= bottomBound) {
Mux(msb,
lowMask(lsbs, topBound - mid, bottomBound - mid),
0.U
)
} else {
Mux(msb,
lowMask(lsbs, topBound - mid, 0) ## ((BigInt(1)<<(mid - bottomBound).toInt) - 1).U,
lowMask(lsbs, mid, bottomBound)
)
}
} else {
~Mux(msb, 0.U, ~lowMask(lsbs, topBound, bottomBound))
}
} else {
val shift = (BigInt(-1)<<numInVals.toInt).S>>in
Reverse(
shift(
(numInVals - 1 - bottomBound).toInt,
(numInVals - topBound).toInt
)
)
}
}
}
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
object countLeadingZeros
{
def apply(in: UInt): UInt = PriorityEncoder(in.asBools.reverse)
}
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
object orReduceBy2
{
def apply(in: UInt): UInt =
{
val reducedWidth = (in.getWidth + 1)>>1
val reducedVec = Wire(Vec(reducedWidth, Bool()))
for (ix <- 0 until reducedWidth - 1) {
reducedVec(ix) := in(ix * 2 + 1, ix * 2).orR
}
reducedVec(reducedWidth - 1) :=
in(in.getWidth - 1, (reducedWidth - 1) * 2).orR
reducedVec.asUInt
}
}
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
object orReduceBy4
{
def apply(in: UInt): UInt =
{
val reducedWidth = (in.getWidth + 3)>>2
val reducedVec = Wire(Vec(reducedWidth, Bool()))
for (ix <- 0 until reducedWidth - 1) {
reducedVec(ix) := in(ix * 4 + 3, ix * 4).orR
}
reducedVec(reducedWidth - 1) :=
in(in.getWidth - 1, (reducedWidth - 1) * 4).orR
reducedVec.asUInt
}
}
File MulAddRecFN.scala:
/*============================================================================
This Chisel source file is part of a pre-release version of the HardFloat IEEE
Floating-Point Arithmetic Package, by John R. Hauser (with some contributions
from Yunsup Lee and Andrew Waterman, mainly concerning testing).
Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
University of California. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
package hardfloat
import chisel3._
import chisel3.util._
import consts._
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
class MulAddRecFN_interIo(expWidth: Int, sigWidth: Int) extends Bundle
{
//*** ENCODE SOME OF THESE CASES IN FEWER BITS?:
val isSigNaNAny = Bool()
val isNaNAOrB = Bool()
val isInfA = Bool()
val isZeroA = Bool()
val isInfB = Bool()
val isZeroB = Bool()
val signProd = Bool()
val isNaNC = Bool()
val isInfC = Bool()
val isZeroC = Bool()
val sExpSum = SInt((expWidth + 2).W)
val doSubMags = Bool()
val CIsDominant = Bool()
val CDom_CAlignDist = UInt(log2Ceil(sigWidth + 1).W)
val highAlignedSigC = UInt((sigWidth + 2).W)
val bit0AlignedSigC = UInt(1.W)
}
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
class MulAddRecFNToRaw_preMul(expWidth: Int, sigWidth: Int) extends RawModule
{
override def desiredName = s"MulAddRecFNToRaw_preMul_e${expWidth}_s${sigWidth}"
val io = IO(new Bundle {
val op = Input(Bits(2.W))
val a = Input(Bits((expWidth + sigWidth + 1).W))
val b = Input(Bits((expWidth + sigWidth + 1).W))
val c = Input(Bits((expWidth + sigWidth + 1).W))
val mulAddA = Output(UInt(sigWidth.W))
val mulAddB = Output(UInt(sigWidth.W))
val mulAddC = Output(UInt((sigWidth * 2).W))
val toPostMul = Output(new MulAddRecFN_interIo(expWidth, sigWidth))
})
//------------------------------------------------------------------------
//------------------------------------------------------------------------
//*** POSSIBLE TO REDUCE THIS BY 1 OR 2 BITS? (CURRENTLY 2 BITS BETWEEN
//*** UNSHIFTED C AND PRODUCT):
val sigSumWidth = sigWidth * 3 + 3
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val rawA = rawFloatFromRecFN(expWidth, sigWidth, io.a)
val rawB = rawFloatFromRecFN(expWidth, sigWidth, io.b)
val rawC = rawFloatFromRecFN(expWidth, sigWidth, io.c)
val signProd = rawA.sign ^ rawB.sign ^ io.op(1)
//*** REVIEW THE BIAS FOR 'sExpAlignedProd':
val sExpAlignedProd =
rawA.sExp +& rawB.sExp + (-(BigInt(1)<<expWidth) + sigWidth + 3).S
val doSubMags = signProd ^ rawC.sign ^ io.op(0)
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val sNatCAlignDist = sExpAlignedProd - rawC.sExp
val posNatCAlignDist = sNatCAlignDist(expWidth + 1, 0)
val isMinCAlign = rawA.isZero || rawB.isZero || (sNatCAlignDist < 0.S)
val CIsDominant =
! rawC.isZero && (isMinCAlign || (posNatCAlignDist <= sigWidth.U))
val CAlignDist =
Mux(isMinCAlign,
0.U,
Mux(posNatCAlignDist < (sigSumWidth - 1).U,
posNatCAlignDist(log2Ceil(sigSumWidth) - 1, 0),
(sigSumWidth - 1).U
)
)
val mainAlignedSigC =
(Mux(doSubMags, ~rawC.sig, rawC.sig) ## Fill(sigSumWidth - sigWidth + 2, doSubMags)).asSInt>>CAlignDist
val reduced4CExtra =
(orReduceBy4(rawC.sig<<((sigSumWidth - sigWidth - 1) & 3)) &
lowMask(
CAlignDist>>2,
//*** NOT NEEDED?:
// (sigSumWidth + 2)>>2,
(sigSumWidth - 1)>>2,
(sigSumWidth - sigWidth - 1)>>2
)
).orR
val alignedSigC =
Cat(mainAlignedSigC>>3,
Mux(doSubMags,
mainAlignedSigC(2, 0).andR && ! reduced4CExtra,
mainAlignedSigC(2, 0).orR || reduced4CExtra
)
)
//------------------------------------------------------------------------
//------------------------------------------------------------------------
io.mulAddA := rawA.sig
io.mulAddB := rawB.sig
io.mulAddC := alignedSigC(sigWidth * 2, 1)
io.toPostMul.isSigNaNAny :=
isSigNaNRawFloat(rawA) || isSigNaNRawFloat(rawB) ||
isSigNaNRawFloat(rawC)
io.toPostMul.isNaNAOrB := rawA.isNaN || rawB.isNaN
io.toPostMul.isInfA := rawA.isInf
io.toPostMul.isZeroA := rawA.isZero
io.toPostMul.isInfB := rawB.isInf
io.toPostMul.isZeroB := rawB.isZero
io.toPostMul.signProd := signProd
io.toPostMul.isNaNC := rawC.isNaN
io.toPostMul.isInfC := rawC.isInf
io.toPostMul.isZeroC := rawC.isZero
io.toPostMul.sExpSum :=
Mux(CIsDominant, rawC.sExp, sExpAlignedProd - sigWidth.S)
io.toPostMul.doSubMags := doSubMags
io.toPostMul.CIsDominant := CIsDominant
io.toPostMul.CDom_CAlignDist := CAlignDist(log2Ceil(sigWidth + 1) - 1, 0)
io.toPostMul.highAlignedSigC :=
alignedSigC(sigSumWidth - 1, sigWidth * 2 + 1)
io.toPostMul.bit0AlignedSigC := alignedSigC(0)
}
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
class MulAddRecFNToRaw_postMul(expWidth: Int, sigWidth: Int) extends RawModule
{
override def desiredName = s"MulAddRecFNToRaw_postMul_e${expWidth}_s${sigWidth}"
val io = IO(new Bundle {
val fromPreMul = Input(new MulAddRecFN_interIo(expWidth, sigWidth))
val mulAddResult = Input(UInt((sigWidth * 2 + 1).W))
val roundingMode = Input(UInt(3.W))
val invalidExc = Output(Bool())
val rawOut = Output(new RawFloat(expWidth, sigWidth + 2))
})
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val sigSumWidth = sigWidth * 3 + 3
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val roundingMode_min = (io.roundingMode === round_min)
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val opSignC = io.fromPreMul.signProd ^ io.fromPreMul.doSubMags
val sigSum =
Cat(Mux(io.mulAddResult(sigWidth * 2),
io.fromPreMul.highAlignedSigC + 1.U,
io.fromPreMul.highAlignedSigC
),
io.mulAddResult(sigWidth * 2 - 1, 0),
io.fromPreMul.bit0AlignedSigC
)
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val CDom_sign = opSignC
val CDom_sExp = io.fromPreMul.sExpSum - io.fromPreMul.doSubMags.zext
val CDom_absSigSum =
Mux(io.fromPreMul.doSubMags,
~sigSum(sigSumWidth - 1, sigWidth + 1),
0.U(1.W) ##
//*** IF GAP IS REDUCED TO 1 BIT, MUST REDUCE THIS COMPONENT TO 1 BIT TOO:
io.fromPreMul.highAlignedSigC(sigWidth + 1, sigWidth) ##
sigSum(sigSumWidth - 3, sigWidth + 2)
)
val CDom_absSigSumExtra =
Mux(io.fromPreMul.doSubMags,
(~sigSum(sigWidth, 1)).orR,
sigSum(sigWidth + 1, 1).orR
)
val CDom_mainSig =
(CDom_absSigSum<<io.fromPreMul.CDom_CAlignDist)(
sigWidth * 2 + 1, sigWidth - 3)
val CDom_reduced4SigExtra =
(orReduceBy4(CDom_absSigSum(sigWidth - 1, 0)<<(~sigWidth & 3)) &
lowMask(io.fromPreMul.CDom_CAlignDist>>2, 0, sigWidth>>2)).orR
val CDom_sig =
Cat(CDom_mainSig>>3,
CDom_mainSig(2, 0).orR || CDom_reduced4SigExtra ||
CDom_absSigSumExtra
)
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val notCDom_signSigSum = sigSum(sigWidth * 2 + 3)
val notCDom_absSigSum =
Mux(notCDom_signSigSum,
~sigSum(sigWidth * 2 + 2, 0),
sigSum(sigWidth * 2 + 2, 0) + io.fromPreMul.doSubMags
)
val notCDom_reduced2AbsSigSum = orReduceBy2(notCDom_absSigSum)
val notCDom_normDistReduced2 = countLeadingZeros(notCDom_reduced2AbsSigSum)
val notCDom_nearNormDist = notCDom_normDistReduced2<<1
val notCDom_sExp = io.fromPreMul.sExpSum - notCDom_nearNormDist.asUInt.zext
val notCDom_mainSig =
(notCDom_absSigSum<<notCDom_nearNormDist)(
sigWidth * 2 + 3, sigWidth - 1)
val notCDom_reduced4SigExtra =
(orReduceBy2(
notCDom_reduced2AbsSigSum(sigWidth>>1, 0)<<((sigWidth>>1) & 1)) &
lowMask(notCDom_normDistReduced2>>1, 0, (sigWidth + 2)>>2)
).orR
val notCDom_sig =
Cat(notCDom_mainSig>>3,
notCDom_mainSig(2, 0).orR || notCDom_reduced4SigExtra
)
val notCDom_completeCancellation =
(notCDom_sig(sigWidth + 2, sigWidth + 1) === 0.U)
val notCDom_sign =
Mux(notCDom_completeCancellation,
roundingMode_min,
io.fromPreMul.signProd ^ notCDom_signSigSum
)
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val notNaN_isInfProd = io.fromPreMul.isInfA || io.fromPreMul.isInfB
val notNaN_isInfOut = notNaN_isInfProd || io.fromPreMul.isInfC
val notNaN_addZeros =
(io.fromPreMul.isZeroA || io.fromPreMul.isZeroB) &&
io.fromPreMul.isZeroC
io.invalidExc :=
io.fromPreMul.isSigNaNAny ||
(io.fromPreMul.isInfA && io.fromPreMul.isZeroB) ||
(io.fromPreMul.isZeroA && io.fromPreMul.isInfB) ||
(! io.fromPreMul.isNaNAOrB &&
(io.fromPreMul.isInfA || io.fromPreMul.isInfB) &&
io.fromPreMul.isInfC &&
io.fromPreMul.doSubMags)
io.rawOut.isNaN := io.fromPreMul.isNaNAOrB || io.fromPreMul.isNaNC
io.rawOut.isInf := notNaN_isInfOut
//*** IMPROVE?:
io.rawOut.isZero :=
notNaN_addZeros ||
(! io.fromPreMul.CIsDominant && notCDom_completeCancellation)
io.rawOut.sign :=
(notNaN_isInfProd && io.fromPreMul.signProd) ||
(io.fromPreMul.isInfC && opSignC) ||
(notNaN_addZeros && ! roundingMode_min &&
io.fromPreMul.signProd && opSignC) ||
(notNaN_addZeros && roundingMode_min &&
(io.fromPreMul.signProd || opSignC)) ||
(! notNaN_isInfOut && ! notNaN_addZeros &&
Mux(io.fromPreMul.CIsDominant, CDom_sign, notCDom_sign))
io.rawOut.sExp := Mux(io.fromPreMul.CIsDominant, CDom_sExp, notCDom_sExp)
io.rawOut.sig := Mux(io.fromPreMul.CIsDominant, CDom_sig, notCDom_sig)
}
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
class MulAddRecFN(expWidth: Int, sigWidth: Int) extends RawModule
{
override def desiredName = s"MulAddRecFN_e${expWidth}_s${sigWidth}"
val io = IO(new Bundle {
val op = Input(Bits(2.W))
val a = Input(Bits((expWidth + sigWidth + 1).W))
val b = Input(Bits((expWidth + sigWidth + 1).W))
val c = Input(Bits((expWidth + sigWidth + 1).W))
val roundingMode = Input(UInt(3.W))
val detectTininess = Input(UInt(1.W))
val out = Output(Bits((expWidth + sigWidth + 1).W))
val exceptionFlags = Output(Bits(5.W))
})
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val mulAddRecFNToRaw_preMul =
Module(new MulAddRecFNToRaw_preMul(expWidth, sigWidth))
val mulAddRecFNToRaw_postMul =
Module(new MulAddRecFNToRaw_postMul(expWidth, sigWidth))
mulAddRecFNToRaw_preMul.io.op := io.op
mulAddRecFNToRaw_preMul.io.a := io.a
mulAddRecFNToRaw_preMul.io.b := io.b
mulAddRecFNToRaw_preMul.io.c := io.c
val mulAddResult =
(mulAddRecFNToRaw_preMul.io.mulAddA *
mulAddRecFNToRaw_preMul.io.mulAddB) +&
mulAddRecFNToRaw_preMul.io.mulAddC
mulAddRecFNToRaw_postMul.io.fromPreMul :=
mulAddRecFNToRaw_preMul.io.toPostMul
mulAddRecFNToRaw_postMul.io.mulAddResult := mulAddResult
mulAddRecFNToRaw_postMul.io.roundingMode := io.roundingMode
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val roundRawFNToRecFN =
Module(new RoundRawFNToRecFN(expWidth, sigWidth, 0))
roundRawFNToRecFN.io.invalidExc := mulAddRecFNToRaw_postMul.io.invalidExc
roundRawFNToRecFN.io.infiniteExc := false.B
roundRawFNToRecFN.io.in := mulAddRecFNToRaw_postMul.io.rawOut
roundRawFNToRecFN.io.roundingMode := io.roundingMode
roundRawFNToRecFN.io.detectTininess := io.detectTininess
io.out := roundRawFNToRecFN.io.out
io.exceptionFlags := roundRawFNToRecFN.io.exceptionFlags
}
File rawFloatFromRecFN.scala:
/*============================================================================
This Chisel source file is part of a pre-release version of the HardFloat IEEE
Floating-Point Arithmetic Package, by John R. Hauser (with some contributions
from Yunsup Lee and Andrew Waterman, mainly concerning testing).
Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the
University of California. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
package hardfloat
import chisel3._
import chisel3.util._
/*----------------------------------------------------------------------------
| In the result, no more than one of 'isNaN', 'isInf', and 'isZero' will be
| set.
*----------------------------------------------------------------------------*/
object rawFloatFromRecFN
{
def apply(expWidth: Int, sigWidth: Int, in: Bits): RawFloat =
{
val exp = in(expWidth + sigWidth - 1, sigWidth - 1)
val isZero = exp(expWidth, expWidth - 2) === 0.U
val isSpecial = exp(expWidth, expWidth - 1) === 3.U
val out = Wire(new RawFloat(expWidth, sigWidth))
out.isNaN := isSpecial && exp(expWidth - 2)
out.isInf := isSpecial && ! exp(expWidth - 2)
out.isZero := isZero
out.sign := in(expWidth + sigWidth)
out.sExp := exp.zext
out.sig := 0.U(1.W) ## ! isZero ## in(sigWidth - 2, 0)
out
}
}
| module MulAddRecFNToRaw_preMul_e11_s53_1( // @[MulAddRecFN.scala:71:7]
input [1:0] io_op, // @[MulAddRecFN.scala:74:16]
input [64:0] io_a, // @[MulAddRecFN.scala:74:16]
input [64:0] io_b, // @[MulAddRecFN.scala:74:16]
input [64:0] io_c, // @[MulAddRecFN.scala:74:16]
output [52:0] io_mulAddA, // @[MulAddRecFN.scala:74:16]
output [52:0] io_mulAddB, // @[MulAddRecFN.scala:74:16]
output [105:0] io_mulAddC, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_isSigNaNAny, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_isNaNAOrB, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_isInfA, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_isZeroA, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_isInfB, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_isZeroB, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_signProd, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_isNaNC, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_isInfC, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_isZeroC, // @[MulAddRecFN.scala:74:16]
output [12:0] io_toPostMul_sExpSum, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_doSubMags, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_CIsDominant, // @[MulAddRecFN.scala:74:16]
output [5:0] io_toPostMul_CDom_CAlignDist, // @[MulAddRecFN.scala:74:16]
output [54:0] io_toPostMul_highAlignedSigC, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_bit0AlignedSigC // @[MulAddRecFN.scala:74:16]
);
wire [1:0] io_op_0 = io_op; // @[MulAddRecFN.scala:71:7]
wire [64:0] io_a_0 = io_a; // @[MulAddRecFN.scala:71:7]
wire [64:0] io_b_0 = io_b; // @[MulAddRecFN.scala:71:7]
wire [64:0] io_c_0 = io_c; // @[MulAddRecFN.scala:71:7]
wire [7:0] _reduced4CExtra_T_6 = 8'hF; // @[primitives.scala:77:20]
wire [7:0] _reduced4CExtra_T_5 = 8'hF0; // @[primitives.scala:77:20]
wire [7:0] _reduced4CExtra_T_11 = 8'hF0; // @[primitives.scala:77:20]
wire [5:0] _reduced4CExtra_T_14 = 6'hF; // @[primitives.scala:77:20]
wire [7:0] _reduced4CExtra_T_15 = 8'h3C; // @[primitives.scala:77:20]
wire [7:0] _reduced4CExtra_T_16 = 8'h33; // @[primitives.scala:77:20]
wire [7:0] _reduced4CExtra_T_21 = 8'hCC; // @[primitives.scala:77:20]
wire [6:0] _reduced4CExtra_T_24 = 7'h33; // @[primitives.scala:77:20]
wire [7:0] _reduced4CExtra_T_25 = 8'h66; // @[primitives.scala:77:20]
wire [7:0] _reduced4CExtra_T_26 = 8'h55; // @[primitives.scala:77:20]
wire [7:0] _reduced4CExtra_T_31 = 8'hAA; // @[primitives.scala:77:20]
wire [105:0] _io_mulAddC_T; // @[MulAddRecFN.scala:143:30]
wire _io_toPostMul_isSigNaNAny_T_10; // @[MulAddRecFN.scala:146:58]
wire _io_toPostMul_isNaNAOrB_T; // @[MulAddRecFN.scala:148:42]
wire rawA_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire rawA_isZero; // @[rawFloatFromRecFN.scala:55:23]
wire rawB_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire rawB_isZero; // @[rawFloatFromRecFN.scala:55:23]
wire signProd; // @[MulAddRecFN.scala:97:42]
wire rawC_isNaN; // @[rawFloatFromRecFN.scala:55:23]
wire rawC_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire rawC_isZero; // @[rawFloatFromRecFN.scala:55:23]
wire doSubMags; // @[MulAddRecFN.scala:102:42]
wire CIsDominant; // @[MulAddRecFN.scala:110:23]
wire [5:0] _io_toPostMul_CDom_CAlignDist_T; // @[MulAddRecFN.scala:161:47]
wire [54:0] _io_toPostMul_highAlignedSigC_T; // @[MulAddRecFN.scala:163:20]
wire _io_toPostMul_bit0AlignedSigC_T; // @[MulAddRecFN.scala:164:48]
wire io_toPostMul_isSigNaNAny_0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_isNaNAOrB_0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_isInfA_0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_isZeroA_0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_isInfB_0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_isZeroB_0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_signProd_0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_isNaNC_0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_isInfC_0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_isZeroC_0; // @[MulAddRecFN.scala:71:7]
wire [12:0] io_toPostMul_sExpSum_0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_doSubMags_0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_CIsDominant_0; // @[MulAddRecFN.scala:71:7]
wire [5:0] io_toPostMul_CDom_CAlignDist_0; // @[MulAddRecFN.scala:71:7]
wire [54:0] io_toPostMul_highAlignedSigC_0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_bit0AlignedSigC_0; // @[MulAddRecFN.scala:71:7]
wire [52:0] io_mulAddA_0; // @[MulAddRecFN.scala:71:7]
wire [52:0] io_mulAddB_0; // @[MulAddRecFN.scala:71:7]
wire [105:0] io_mulAddC_0; // @[MulAddRecFN.scala:71:7]
wire [11:0] rawA_exp = io_a_0[63:52]; // @[rawFloatFromRecFN.scala:51:21]
wire [2:0] _rawA_isZero_T = rawA_exp[11:9]; // @[rawFloatFromRecFN.scala:51:21, :52:28]
wire rawA_isZero_0 = _rawA_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}]
assign rawA_isZero = rawA_isZero_0; // @[rawFloatFromRecFN.scala:52:53, :55:23]
wire [1:0] _rawA_isSpecial_T = rawA_exp[11:10]; // @[rawFloatFromRecFN.scala:51:21, :53:28]
wire rawA_isSpecial = &_rawA_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}]
wire _rawA_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33]
wire _rawA_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33]
assign io_toPostMul_isInfA_0 = rawA_isInf; // @[rawFloatFromRecFN.scala:55:23]
assign io_toPostMul_isZeroA_0 = rawA_isZero; // @[rawFloatFromRecFN.scala:55:23]
wire _rawA_out_sign_T; // @[rawFloatFromRecFN.scala:59:25]
wire [12:0] _rawA_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27]
wire [53:0] _rawA_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44]
wire rawA_isNaN; // @[rawFloatFromRecFN.scala:55:23]
wire rawA_sign; // @[rawFloatFromRecFN.scala:55:23]
wire [12:0] rawA_sExp; // @[rawFloatFromRecFN.scala:55:23]
wire [53:0] rawA_sig; // @[rawFloatFromRecFN.scala:55:23]
wire _rawA_out_isNaN_T = rawA_exp[9]; // @[rawFloatFromRecFN.scala:51:21, :56:41]
wire _rawA_out_isInf_T = rawA_exp[9]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41]
assign _rawA_out_isNaN_T_1 = rawA_isSpecial & _rawA_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}]
assign rawA_isNaN = _rawA_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33]
wire _rawA_out_isInf_T_1 = ~_rawA_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}]
assign _rawA_out_isInf_T_2 = rawA_isSpecial & _rawA_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}]
assign rawA_isInf = _rawA_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33]
assign _rawA_out_sign_T = io_a_0[64]; // @[rawFloatFromRecFN.scala:59:25]
assign rawA_sign = _rawA_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25]
assign _rawA_out_sExp_T = {1'h0, rawA_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27]
assign rawA_sExp = _rawA_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire _rawA_out_sig_T = ~rawA_isZero_0; // @[rawFloatFromRecFN.scala:52:53, :61:35]
wire [1:0] _rawA_out_sig_T_1 = {1'h0, _rawA_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}]
wire [51:0] _rawA_out_sig_T_2 = io_a_0[51:0]; // @[rawFloatFromRecFN.scala:61:49]
assign _rawA_out_sig_T_3 = {_rawA_out_sig_T_1, _rawA_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}]
assign rawA_sig = _rawA_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44]
wire [11:0] rawB_exp = io_b_0[63:52]; // @[rawFloatFromRecFN.scala:51:21]
wire [2:0] _rawB_isZero_T = rawB_exp[11:9]; // @[rawFloatFromRecFN.scala:51:21, :52:28]
wire rawB_isZero_0 = _rawB_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}]
assign rawB_isZero = rawB_isZero_0; // @[rawFloatFromRecFN.scala:52:53, :55:23]
wire [1:0] _rawB_isSpecial_T = rawB_exp[11:10]; // @[rawFloatFromRecFN.scala:51:21, :53:28]
wire rawB_isSpecial = &_rawB_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}]
wire _rawB_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33]
wire _rawB_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33]
assign io_toPostMul_isInfB_0 = rawB_isInf; // @[rawFloatFromRecFN.scala:55:23]
assign io_toPostMul_isZeroB_0 = rawB_isZero; // @[rawFloatFromRecFN.scala:55:23]
wire _rawB_out_sign_T; // @[rawFloatFromRecFN.scala:59:25]
wire [12:0] _rawB_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27]
wire [53:0] _rawB_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44]
wire rawB_isNaN; // @[rawFloatFromRecFN.scala:55:23]
wire rawB_sign; // @[rawFloatFromRecFN.scala:55:23]
wire [12:0] rawB_sExp; // @[rawFloatFromRecFN.scala:55:23]
wire [53:0] rawB_sig; // @[rawFloatFromRecFN.scala:55:23]
wire _rawB_out_isNaN_T = rawB_exp[9]; // @[rawFloatFromRecFN.scala:51:21, :56:41]
wire _rawB_out_isInf_T = rawB_exp[9]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41]
assign _rawB_out_isNaN_T_1 = rawB_isSpecial & _rawB_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}]
assign rawB_isNaN = _rawB_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33]
wire _rawB_out_isInf_T_1 = ~_rawB_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}]
assign _rawB_out_isInf_T_2 = rawB_isSpecial & _rawB_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}]
assign rawB_isInf = _rawB_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33]
assign _rawB_out_sign_T = io_b_0[64]; // @[rawFloatFromRecFN.scala:59:25]
assign rawB_sign = _rawB_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25]
assign _rawB_out_sExp_T = {1'h0, rawB_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27]
assign rawB_sExp = _rawB_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire _rawB_out_sig_T = ~rawB_isZero_0; // @[rawFloatFromRecFN.scala:52:53, :61:35]
wire [1:0] _rawB_out_sig_T_1 = {1'h0, _rawB_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}]
wire [51:0] _rawB_out_sig_T_2 = io_b_0[51:0]; // @[rawFloatFromRecFN.scala:61:49]
assign _rawB_out_sig_T_3 = {_rawB_out_sig_T_1, _rawB_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}]
assign rawB_sig = _rawB_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44]
wire [11:0] rawC_exp = io_c_0[63:52]; // @[rawFloatFromRecFN.scala:51:21]
wire [2:0] _rawC_isZero_T = rawC_exp[11:9]; // @[rawFloatFromRecFN.scala:51:21, :52:28]
wire rawC_isZero_0 = _rawC_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}]
assign rawC_isZero = rawC_isZero_0; // @[rawFloatFromRecFN.scala:52:53, :55:23]
wire [1:0] _rawC_isSpecial_T = rawC_exp[11:10]; // @[rawFloatFromRecFN.scala:51:21, :53:28]
wire rawC_isSpecial = &_rawC_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}]
wire _rawC_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33]
assign io_toPostMul_isNaNC_0 = rawC_isNaN; // @[rawFloatFromRecFN.scala:55:23]
wire _rawC_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33]
assign io_toPostMul_isInfC_0 = rawC_isInf; // @[rawFloatFromRecFN.scala:55:23]
assign io_toPostMul_isZeroC_0 = rawC_isZero; // @[rawFloatFromRecFN.scala:55:23]
wire _rawC_out_sign_T; // @[rawFloatFromRecFN.scala:59:25]
wire [12:0] _rawC_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27]
wire [53:0] _rawC_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44]
wire rawC_sign; // @[rawFloatFromRecFN.scala:55:23]
wire [12:0] rawC_sExp; // @[rawFloatFromRecFN.scala:55:23]
wire [53:0] rawC_sig; // @[rawFloatFromRecFN.scala:55:23]
wire [53:0] _reduced4CExtra_T = rawC_sig; // @[rawFloatFromRecFN.scala:55:23]
wire _rawC_out_isNaN_T = rawC_exp[9]; // @[rawFloatFromRecFN.scala:51:21, :56:41]
wire _rawC_out_isInf_T = rawC_exp[9]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41]
assign _rawC_out_isNaN_T_1 = rawC_isSpecial & _rawC_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}]
assign rawC_isNaN = _rawC_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33]
wire _rawC_out_isInf_T_1 = ~_rawC_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}]
assign _rawC_out_isInf_T_2 = rawC_isSpecial & _rawC_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}]
assign rawC_isInf = _rawC_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33]
assign _rawC_out_sign_T = io_c_0[64]; // @[rawFloatFromRecFN.scala:59:25]
assign rawC_sign = _rawC_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25]
assign _rawC_out_sExp_T = {1'h0, rawC_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27]
assign rawC_sExp = _rawC_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire _rawC_out_sig_T = ~rawC_isZero_0; // @[rawFloatFromRecFN.scala:52:53, :61:35]
wire [1:0] _rawC_out_sig_T_1 = {1'h0, _rawC_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}]
wire [51:0] _rawC_out_sig_T_2 = io_c_0[51:0]; // @[rawFloatFromRecFN.scala:61:49]
assign _rawC_out_sig_T_3 = {_rawC_out_sig_T_1, _rawC_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}]
assign rawC_sig = _rawC_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44]
wire _signProd_T = rawA_sign ^ rawB_sign; // @[rawFloatFromRecFN.scala:55:23]
wire _signProd_T_1 = io_op_0[1]; // @[MulAddRecFN.scala:71:7, :97:49]
assign signProd = _signProd_T ^ _signProd_T_1; // @[MulAddRecFN.scala:97:{30,42,49}]
assign io_toPostMul_signProd_0 = signProd; // @[MulAddRecFN.scala:71:7, :97:42]
wire [13:0] _sExpAlignedProd_T = {rawA_sExp[12], rawA_sExp} + {rawB_sExp[12], rawB_sExp}; // @[rawFloatFromRecFN.scala:55:23]
wire [14:0] _sExpAlignedProd_T_1 = {_sExpAlignedProd_T[13], _sExpAlignedProd_T} - 15'h7C8; // @[MulAddRecFN.scala:100:{19,32}]
wire [13:0] _sExpAlignedProd_T_2 = _sExpAlignedProd_T_1[13:0]; // @[MulAddRecFN.scala:100:32]
wire [13:0] sExpAlignedProd = _sExpAlignedProd_T_2; // @[MulAddRecFN.scala:100:32]
wire _doSubMags_T = signProd ^ rawC_sign; // @[rawFloatFromRecFN.scala:55:23]
wire _doSubMags_T_1 = io_op_0[0]; // @[MulAddRecFN.scala:71:7, :102:49]
assign doSubMags = _doSubMags_T ^ _doSubMags_T_1; // @[MulAddRecFN.scala:102:{30,42,49}]
assign io_toPostMul_doSubMags_0 = doSubMags; // @[MulAddRecFN.scala:71:7, :102:42]
wire [14:0] _GEN = {sExpAlignedProd[13], sExpAlignedProd}; // @[MulAddRecFN.scala:100:32, :106:42]
wire [14:0] _sNatCAlignDist_T = _GEN - {{2{rawC_sExp[12]}}, rawC_sExp}; // @[rawFloatFromRecFN.scala:55:23]
wire [13:0] _sNatCAlignDist_T_1 = _sNatCAlignDist_T[13:0]; // @[MulAddRecFN.scala:106:42]
wire [13:0] sNatCAlignDist = _sNatCAlignDist_T_1; // @[MulAddRecFN.scala:106:42]
wire [12:0] posNatCAlignDist = sNatCAlignDist[12:0]; // @[MulAddRecFN.scala:106:42, :107:42]
wire _isMinCAlign_T = rawA_isZero | rawB_isZero; // @[rawFloatFromRecFN.scala:55:23]
wire _isMinCAlign_T_1 = $signed(sNatCAlignDist) < 14'sh0; // @[MulAddRecFN.scala:106:42, :108:69, :130:11]
wire isMinCAlign = _isMinCAlign_T | _isMinCAlign_T_1; // @[MulAddRecFN.scala:108:{35,50,69}]
wire _CIsDominant_T = ~rawC_isZero; // @[rawFloatFromRecFN.scala:55:23]
wire _CIsDominant_T_1 = posNatCAlignDist < 13'h36; // @[MulAddRecFN.scala:107:42, :110:60]
wire _CIsDominant_T_2 = isMinCAlign | _CIsDominant_T_1; // @[MulAddRecFN.scala:108:50, :110:{39,60}]
assign CIsDominant = _CIsDominant_T & _CIsDominant_T_2; // @[MulAddRecFN.scala:110:{9,23,39}]
assign io_toPostMul_CIsDominant_0 = CIsDominant; // @[MulAddRecFN.scala:71:7, :110:23]
wire _CAlignDist_T = posNatCAlignDist < 13'hA1; // @[MulAddRecFN.scala:107:42, :114:34]
wire [7:0] _CAlignDist_T_1 = posNatCAlignDist[7:0]; // @[MulAddRecFN.scala:107:42, :115:33]
wire [7:0] _CAlignDist_T_2 = _CAlignDist_T ? _CAlignDist_T_1 : 8'hA1; // @[MulAddRecFN.scala:114:{16,34}, :115:33]
wire [7:0] CAlignDist = isMinCAlign ? 8'h0 : _CAlignDist_T_2; // @[MulAddRecFN.scala:108:50, :112:12, :114:16]
wire [53:0] _mainAlignedSigC_T = ~rawC_sig; // @[rawFloatFromRecFN.scala:55:23]
wire [53:0] _mainAlignedSigC_T_1 = doSubMags ? _mainAlignedSigC_T : rawC_sig; // @[rawFloatFromRecFN.scala:55:23]
wire [110:0] _mainAlignedSigC_T_2 = {111{doSubMags}}; // @[MulAddRecFN.scala:102:42, :120:53]
wire [164:0] _mainAlignedSigC_T_3 = {_mainAlignedSigC_T_1, _mainAlignedSigC_T_2}; // @[MulAddRecFN.scala:120:{13,46,53}]
wire [164:0] _mainAlignedSigC_T_4 = _mainAlignedSigC_T_3; // @[MulAddRecFN.scala:120:{46,94}]
wire [164:0] mainAlignedSigC = $signed($signed(_mainAlignedSigC_T_4) >>> CAlignDist); // @[MulAddRecFN.scala:112:12, :120:{94,100}]
wire _reduced4CExtra_reducedVec_0_T_1; // @[primitives.scala:120:54]
wire _reduced4CExtra_reducedVec_1_T_1; // @[primitives.scala:120:54]
wire _reduced4CExtra_reducedVec_2_T_1; // @[primitives.scala:120:54]
wire _reduced4CExtra_reducedVec_3_T_1; // @[primitives.scala:120:54]
wire _reduced4CExtra_reducedVec_4_T_1; // @[primitives.scala:120:54]
wire _reduced4CExtra_reducedVec_5_T_1; // @[primitives.scala:120:54]
wire _reduced4CExtra_reducedVec_6_T_1; // @[primitives.scala:120:54]
wire _reduced4CExtra_reducedVec_7_T_1; // @[primitives.scala:120:54]
wire _reduced4CExtra_reducedVec_8_T_1; // @[primitives.scala:120:54]
wire _reduced4CExtra_reducedVec_9_T_1; // @[primitives.scala:120:54]
wire _reduced4CExtra_reducedVec_10_T_1; // @[primitives.scala:120:54]
wire _reduced4CExtra_reducedVec_11_T_1; // @[primitives.scala:120:54]
wire _reduced4CExtra_reducedVec_12_T_1; // @[primitives.scala:120:54]
wire _reduced4CExtra_reducedVec_13_T_1; // @[primitives.scala:123:57]
wire reduced4CExtra_reducedVec_0; // @[primitives.scala:118:30]
wire reduced4CExtra_reducedVec_1; // @[primitives.scala:118:30]
wire reduced4CExtra_reducedVec_2; // @[primitives.scala:118:30]
wire reduced4CExtra_reducedVec_3; // @[primitives.scala:118:30]
wire reduced4CExtra_reducedVec_4; // @[primitives.scala:118:30]
wire reduced4CExtra_reducedVec_5; // @[primitives.scala:118:30]
wire reduced4CExtra_reducedVec_6; // @[primitives.scala:118:30]
wire reduced4CExtra_reducedVec_7; // @[primitives.scala:118:30]
wire reduced4CExtra_reducedVec_8; // @[primitives.scala:118:30]
wire reduced4CExtra_reducedVec_9; // @[primitives.scala:118:30]
wire reduced4CExtra_reducedVec_10; // @[primitives.scala:118:30]
wire reduced4CExtra_reducedVec_11; // @[primitives.scala:118:30]
wire reduced4CExtra_reducedVec_12; // @[primitives.scala:118:30]
wire reduced4CExtra_reducedVec_13; // @[primitives.scala:118:30]
wire [3:0] _reduced4CExtra_reducedVec_0_T = _reduced4CExtra_T[3:0]; // @[primitives.scala:120:33]
assign _reduced4CExtra_reducedVec_0_T_1 = |_reduced4CExtra_reducedVec_0_T; // @[primitives.scala:120:{33,54}]
assign reduced4CExtra_reducedVec_0 = _reduced4CExtra_reducedVec_0_T_1; // @[primitives.scala:118:30, :120:54]
wire [3:0] _reduced4CExtra_reducedVec_1_T = _reduced4CExtra_T[7:4]; // @[primitives.scala:120:33]
assign _reduced4CExtra_reducedVec_1_T_1 = |_reduced4CExtra_reducedVec_1_T; // @[primitives.scala:120:{33,54}]
assign reduced4CExtra_reducedVec_1 = _reduced4CExtra_reducedVec_1_T_1; // @[primitives.scala:118:30, :120:54]
wire [3:0] _reduced4CExtra_reducedVec_2_T = _reduced4CExtra_T[11:8]; // @[primitives.scala:120:33]
assign _reduced4CExtra_reducedVec_2_T_1 = |_reduced4CExtra_reducedVec_2_T; // @[primitives.scala:120:{33,54}]
assign reduced4CExtra_reducedVec_2 = _reduced4CExtra_reducedVec_2_T_1; // @[primitives.scala:118:30, :120:54]
wire [3:0] _reduced4CExtra_reducedVec_3_T = _reduced4CExtra_T[15:12]; // @[primitives.scala:120:33]
assign _reduced4CExtra_reducedVec_3_T_1 = |_reduced4CExtra_reducedVec_3_T; // @[primitives.scala:120:{33,54}]
assign reduced4CExtra_reducedVec_3 = _reduced4CExtra_reducedVec_3_T_1; // @[primitives.scala:118:30, :120:54]
wire [3:0] _reduced4CExtra_reducedVec_4_T = _reduced4CExtra_T[19:16]; // @[primitives.scala:120:33]
assign _reduced4CExtra_reducedVec_4_T_1 = |_reduced4CExtra_reducedVec_4_T; // @[primitives.scala:120:{33,54}]
assign reduced4CExtra_reducedVec_4 = _reduced4CExtra_reducedVec_4_T_1; // @[primitives.scala:118:30, :120:54]
wire [3:0] _reduced4CExtra_reducedVec_5_T = _reduced4CExtra_T[23:20]; // @[primitives.scala:120:33]
assign _reduced4CExtra_reducedVec_5_T_1 = |_reduced4CExtra_reducedVec_5_T; // @[primitives.scala:120:{33,54}]
assign reduced4CExtra_reducedVec_5 = _reduced4CExtra_reducedVec_5_T_1; // @[primitives.scala:118:30, :120:54]
wire [3:0] _reduced4CExtra_reducedVec_6_T = _reduced4CExtra_T[27:24]; // @[primitives.scala:120:33]
assign _reduced4CExtra_reducedVec_6_T_1 = |_reduced4CExtra_reducedVec_6_T; // @[primitives.scala:120:{33,54}]
assign reduced4CExtra_reducedVec_6 = _reduced4CExtra_reducedVec_6_T_1; // @[primitives.scala:118:30, :120:54]
wire [3:0] _reduced4CExtra_reducedVec_7_T = _reduced4CExtra_T[31:28]; // @[primitives.scala:120:33]
assign _reduced4CExtra_reducedVec_7_T_1 = |_reduced4CExtra_reducedVec_7_T; // @[primitives.scala:120:{33,54}]
assign reduced4CExtra_reducedVec_7 = _reduced4CExtra_reducedVec_7_T_1; // @[primitives.scala:118:30, :120:54]
wire [3:0] _reduced4CExtra_reducedVec_8_T = _reduced4CExtra_T[35:32]; // @[primitives.scala:120:33]
assign _reduced4CExtra_reducedVec_8_T_1 = |_reduced4CExtra_reducedVec_8_T; // @[primitives.scala:120:{33,54}]
assign reduced4CExtra_reducedVec_8 = _reduced4CExtra_reducedVec_8_T_1; // @[primitives.scala:118:30, :120:54]
wire [3:0] _reduced4CExtra_reducedVec_9_T = _reduced4CExtra_T[39:36]; // @[primitives.scala:120:33]
assign _reduced4CExtra_reducedVec_9_T_1 = |_reduced4CExtra_reducedVec_9_T; // @[primitives.scala:120:{33,54}]
assign reduced4CExtra_reducedVec_9 = _reduced4CExtra_reducedVec_9_T_1; // @[primitives.scala:118:30, :120:54]
wire [3:0] _reduced4CExtra_reducedVec_10_T = _reduced4CExtra_T[43:40]; // @[primitives.scala:120:33]
assign _reduced4CExtra_reducedVec_10_T_1 = |_reduced4CExtra_reducedVec_10_T; // @[primitives.scala:120:{33,54}]
assign reduced4CExtra_reducedVec_10 = _reduced4CExtra_reducedVec_10_T_1; // @[primitives.scala:118:30, :120:54]
wire [3:0] _reduced4CExtra_reducedVec_11_T = _reduced4CExtra_T[47:44]; // @[primitives.scala:120:33]
assign _reduced4CExtra_reducedVec_11_T_1 = |_reduced4CExtra_reducedVec_11_T; // @[primitives.scala:120:{33,54}]
assign reduced4CExtra_reducedVec_11 = _reduced4CExtra_reducedVec_11_T_1; // @[primitives.scala:118:30, :120:54]
wire [3:0] _reduced4CExtra_reducedVec_12_T = _reduced4CExtra_T[51:48]; // @[primitives.scala:120:33]
assign _reduced4CExtra_reducedVec_12_T_1 = |_reduced4CExtra_reducedVec_12_T; // @[primitives.scala:120:{33,54}]
assign reduced4CExtra_reducedVec_12 = _reduced4CExtra_reducedVec_12_T_1; // @[primitives.scala:118:30, :120:54]
wire [1:0] _reduced4CExtra_reducedVec_13_T = _reduced4CExtra_T[53:52]; // @[primitives.scala:123:15]
assign _reduced4CExtra_reducedVec_13_T_1 = |_reduced4CExtra_reducedVec_13_T; // @[primitives.scala:123:{15,57}]
assign reduced4CExtra_reducedVec_13 = _reduced4CExtra_reducedVec_13_T_1; // @[primitives.scala:118:30, :123:57]
wire [1:0] reduced4CExtra_lo_lo_hi = {reduced4CExtra_reducedVec_2, reduced4CExtra_reducedVec_1}; // @[primitives.scala:118:30, :124:20]
wire [2:0] reduced4CExtra_lo_lo = {reduced4CExtra_lo_lo_hi, reduced4CExtra_reducedVec_0}; // @[primitives.scala:118:30, :124:20]
wire [1:0] reduced4CExtra_lo_hi_lo = {reduced4CExtra_reducedVec_4, reduced4CExtra_reducedVec_3}; // @[primitives.scala:118:30, :124:20]
wire [1:0] reduced4CExtra_lo_hi_hi = {reduced4CExtra_reducedVec_6, reduced4CExtra_reducedVec_5}; // @[primitives.scala:118:30, :124:20]
wire [3:0] reduced4CExtra_lo_hi = {reduced4CExtra_lo_hi_hi, reduced4CExtra_lo_hi_lo}; // @[primitives.scala:124:20]
wire [6:0] reduced4CExtra_lo = {reduced4CExtra_lo_hi, reduced4CExtra_lo_lo}; // @[primitives.scala:124:20]
wire [1:0] reduced4CExtra_hi_lo_hi = {reduced4CExtra_reducedVec_9, reduced4CExtra_reducedVec_8}; // @[primitives.scala:118:30, :124:20]
wire [2:0] reduced4CExtra_hi_lo = {reduced4CExtra_hi_lo_hi, reduced4CExtra_reducedVec_7}; // @[primitives.scala:118:30, :124:20]
wire [1:0] reduced4CExtra_hi_hi_lo = {reduced4CExtra_reducedVec_11, reduced4CExtra_reducedVec_10}; // @[primitives.scala:118:30, :124:20]
wire [1:0] reduced4CExtra_hi_hi_hi = {reduced4CExtra_reducedVec_13, reduced4CExtra_reducedVec_12}; // @[primitives.scala:118:30, :124:20]
wire [3:0] reduced4CExtra_hi_hi = {reduced4CExtra_hi_hi_hi, reduced4CExtra_hi_hi_lo}; // @[primitives.scala:124:20]
wire [6:0] reduced4CExtra_hi = {reduced4CExtra_hi_hi, reduced4CExtra_hi_lo}; // @[primitives.scala:124:20]
wire [13:0] _reduced4CExtra_T_1 = {reduced4CExtra_hi, reduced4CExtra_lo}; // @[primitives.scala:124:20]
wire [5:0] _reduced4CExtra_T_2 = CAlignDist[7:2]; // @[MulAddRecFN.scala:112:12, :124:28]
wire [64:0] reduced4CExtra_shift = $signed(65'sh10000000000000000 >>> _reduced4CExtra_T_2); // @[primitives.scala:76:56]
wire [12:0] _reduced4CExtra_T_3 = reduced4CExtra_shift[36:24]; // @[primitives.scala:76:56, :78:22]
wire [7:0] _reduced4CExtra_T_4 = _reduced4CExtra_T_3[7:0]; // @[primitives.scala:77:20, :78:22]
wire [3:0] _reduced4CExtra_T_7 = _reduced4CExtra_T_4[7:4]; // @[primitives.scala:77:20]
wire [7:0] _reduced4CExtra_T_8 = {4'h0, _reduced4CExtra_T_7}; // @[primitives.scala:77:20, :120:54]
wire [3:0] _reduced4CExtra_T_9 = _reduced4CExtra_T_4[3:0]; // @[primitives.scala:77:20]
wire [7:0] _reduced4CExtra_T_10 = {_reduced4CExtra_T_9, 4'h0}; // @[primitives.scala:77:20, :120:54]
wire [7:0] _reduced4CExtra_T_12 = _reduced4CExtra_T_10 & 8'hF0; // @[primitives.scala:77:20]
wire [7:0] _reduced4CExtra_T_13 = _reduced4CExtra_T_8 | _reduced4CExtra_T_12; // @[primitives.scala:77:20]
wire [5:0] _reduced4CExtra_T_17 = _reduced4CExtra_T_13[7:2]; // @[primitives.scala:77:20]
wire [7:0] _reduced4CExtra_T_18 = {2'h0, _reduced4CExtra_T_17 & 6'h33}; // @[primitives.scala:77:20, :123:57]
wire [5:0] _reduced4CExtra_T_19 = _reduced4CExtra_T_13[5:0]; // @[primitives.scala:77:20]
wire [7:0] _reduced4CExtra_T_20 = {_reduced4CExtra_T_19, 2'h0}; // @[primitives.scala:77:20, :123:57]
wire [7:0] _reduced4CExtra_T_22 = _reduced4CExtra_T_20 & 8'hCC; // @[primitives.scala:77:20]
wire [7:0] _reduced4CExtra_T_23 = _reduced4CExtra_T_18 | _reduced4CExtra_T_22; // @[primitives.scala:77:20]
wire [6:0] _reduced4CExtra_T_27 = _reduced4CExtra_T_23[7:1]; // @[primitives.scala:77:20]
wire [7:0] _reduced4CExtra_T_28 = {1'h0, _reduced4CExtra_T_27 & 7'h55}; // @[primitives.scala:77:20]
wire [6:0] _reduced4CExtra_T_29 = _reduced4CExtra_T_23[6:0]; // @[primitives.scala:77:20]
wire [7:0] _reduced4CExtra_T_30 = {_reduced4CExtra_T_29, 1'h0}; // @[primitives.scala:77:20]
wire [7:0] _reduced4CExtra_T_32 = _reduced4CExtra_T_30 & 8'hAA; // @[primitives.scala:77:20]
wire [7:0] _reduced4CExtra_T_33 = _reduced4CExtra_T_28 | _reduced4CExtra_T_32; // @[primitives.scala:77:20]
wire [4:0] _reduced4CExtra_T_34 = _reduced4CExtra_T_3[12:8]; // @[primitives.scala:77:20, :78:22]
wire [3:0] _reduced4CExtra_T_35 = _reduced4CExtra_T_34[3:0]; // @[primitives.scala:77:20]
wire [1:0] _reduced4CExtra_T_36 = _reduced4CExtra_T_35[1:0]; // @[primitives.scala:77:20]
wire _reduced4CExtra_T_37 = _reduced4CExtra_T_36[0]; // @[primitives.scala:77:20]
wire _reduced4CExtra_T_38 = _reduced4CExtra_T_36[1]; // @[primitives.scala:77:20]
wire [1:0] _reduced4CExtra_T_39 = {_reduced4CExtra_T_37, _reduced4CExtra_T_38}; // @[primitives.scala:77:20]
wire [1:0] _reduced4CExtra_T_40 = _reduced4CExtra_T_35[3:2]; // @[primitives.scala:77:20]
wire _reduced4CExtra_T_41 = _reduced4CExtra_T_40[0]; // @[primitives.scala:77:20]
wire _reduced4CExtra_T_42 = _reduced4CExtra_T_40[1]; // @[primitives.scala:77:20]
wire [1:0] _reduced4CExtra_T_43 = {_reduced4CExtra_T_41, _reduced4CExtra_T_42}; // @[primitives.scala:77:20]
wire [3:0] _reduced4CExtra_T_44 = {_reduced4CExtra_T_39, _reduced4CExtra_T_43}; // @[primitives.scala:77:20]
wire _reduced4CExtra_T_45 = _reduced4CExtra_T_34[4]; // @[primitives.scala:77:20]
wire [4:0] _reduced4CExtra_T_46 = {_reduced4CExtra_T_44, _reduced4CExtra_T_45}; // @[primitives.scala:77:20]
wire [12:0] _reduced4CExtra_T_47 = {_reduced4CExtra_T_33, _reduced4CExtra_T_46}; // @[primitives.scala:77:20]
wire [13:0] _reduced4CExtra_T_48 = {1'h0, _reduced4CExtra_T_1[12:0] & _reduced4CExtra_T_47}; // @[primitives.scala:77:20, :124:20]
wire reduced4CExtra = |_reduced4CExtra_T_48; // @[MulAddRecFN.scala:122:68, :130:11]
wire [161:0] _alignedSigC_T = mainAlignedSigC[164:3]; // @[MulAddRecFN.scala:120:100, :132:28]
wire [161:0] alignedSigC_hi = _alignedSigC_T; // @[MulAddRecFN.scala:132:{12,28}]
wire [2:0] _alignedSigC_T_1 = mainAlignedSigC[2:0]; // @[MulAddRecFN.scala:120:100, :134:32]
wire [2:0] _alignedSigC_T_5 = mainAlignedSigC[2:0]; // @[MulAddRecFN.scala:120:100, :134:32, :135:32]
wire _alignedSigC_T_2 = &_alignedSigC_T_1; // @[MulAddRecFN.scala:134:{32,39}]
wire _alignedSigC_T_3 = ~reduced4CExtra; // @[MulAddRecFN.scala:130:11, :134:47]
wire _alignedSigC_T_4 = _alignedSigC_T_2 & _alignedSigC_T_3; // @[MulAddRecFN.scala:134:{39,44,47}]
wire _alignedSigC_T_6 = |_alignedSigC_T_5; // @[MulAddRecFN.scala:135:{32,39}]
wire _alignedSigC_T_7 = _alignedSigC_T_6 | reduced4CExtra; // @[MulAddRecFN.scala:130:11, :135:{39,44}]
wire _alignedSigC_T_8 = doSubMags ? _alignedSigC_T_4 : _alignedSigC_T_7; // @[MulAddRecFN.scala:102:42, :133:16, :134:44, :135:44]
wire [162:0] alignedSigC = {alignedSigC_hi, _alignedSigC_T_8}; // @[MulAddRecFN.scala:132:12, :133:16]
assign io_mulAddA_0 = rawA_sig[52:0]; // @[rawFloatFromRecFN.scala:55:23]
assign io_mulAddB_0 = rawB_sig[52:0]; // @[rawFloatFromRecFN.scala:55:23]
assign _io_mulAddC_T = alignedSigC[106:1]; // @[MulAddRecFN.scala:132:12, :143:30]
assign io_mulAddC_0 = _io_mulAddC_T; // @[MulAddRecFN.scala:71:7, :143:30]
wire _io_toPostMul_isSigNaNAny_T = rawA_sig[51]; // @[rawFloatFromRecFN.scala:55:23]
wire _io_toPostMul_isSigNaNAny_T_1 = ~_io_toPostMul_isSigNaNAny_T; // @[common.scala:82:{49,56}]
wire _io_toPostMul_isSigNaNAny_T_2 = rawA_isNaN & _io_toPostMul_isSigNaNAny_T_1; // @[rawFloatFromRecFN.scala:55:23]
wire _io_toPostMul_isSigNaNAny_T_3 = rawB_sig[51]; // @[rawFloatFromRecFN.scala:55:23]
wire _io_toPostMul_isSigNaNAny_T_4 = ~_io_toPostMul_isSigNaNAny_T_3; // @[common.scala:82:{49,56}]
wire _io_toPostMul_isSigNaNAny_T_5 = rawB_isNaN & _io_toPostMul_isSigNaNAny_T_4; // @[rawFloatFromRecFN.scala:55:23]
wire _io_toPostMul_isSigNaNAny_T_6 = _io_toPostMul_isSigNaNAny_T_2 | _io_toPostMul_isSigNaNAny_T_5; // @[common.scala:82:46]
wire _io_toPostMul_isSigNaNAny_T_7 = rawC_sig[51]; // @[rawFloatFromRecFN.scala:55:23]
wire _io_toPostMul_isSigNaNAny_T_8 = ~_io_toPostMul_isSigNaNAny_T_7; // @[common.scala:82:{49,56}]
wire _io_toPostMul_isSigNaNAny_T_9 = rawC_isNaN & _io_toPostMul_isSigNaNAny_T_8; // @[rawFloatFromRecFN.scala:55:23]
assign _io_toPostMul_isSigNaNAny_T_10 = _io_toPostMul_isSigNaNAny_T_6 | _io_toPostMul_isSigNaNAny_T_9; // @[common.scala:82:46]
assign io_toPostMul_isSigNaNAny_0 = _io_toPostMul_isSigNaNAny_T_10; // @[MulAddRecFN.scala:71:7, :146:58]
assign _io_toPostMul_isNaNAOrB_T = rawA_isNaN | rawB_isNaN; // @[rawFloatFromRecFN.scala:55:23]
assign io_toPostMul_isNaNAOrB_0 = _io_toPostMul_isNaNAOrB_T; // @[MulAddRecFN.scala:71:7, :148:42]
wire [14:0] _io_toPostMul_sExpSum_T = _GEN - 15'h35; // @[MulAddRecFN.scala:106:42, :158:53]
wire [13:0] _io_toPostMul_sExpSum_T_1 = _io_toPostMul_sExpSum_T[13:0]; // @[MulAddRecFN.scala:158:53]
wire [13:0] _io_toPostMul_sExpSum_T_2 = _io_toPostMul_sExpSum_T_1; // @[MulAddRecFN.scala:158:53]
wire [13:0] _io_toPostMul_sExpSum_T_3 = CIsDominant ? {rawC_sExp[12], rawC_sExp} : _io_toPostMul_sExpSum_T_2; // @[rawFloatFromRecFN.scala:55:23]
assign io_toPostMul_sExpSum_0 = _io_toPostMul_sExpSum_T_3[12:0]; // @[MulAddRecFN.scala:71:7, :157:28, :158:12]
assign _io_toPostMul_CDom_CAlignDist_T = CAlignDist[5:0]; // @[MulAddRecFN.scala:112:12, :161:47]
assign io_toPostMul_CDom_CAlignDist_0 = _io_toPostMul_CDom_CAlignDist_T; // @[MulAddRecFN.scala:71:7, :161:47]
assign _io_toPostMul_highAlignedSigC_T = alignedSigC[161:107]; // @[MulAddRecFN.scala:132:12, :163:20]
assign io_toPostMul_highAlignedSigC_0 = _io_toPostMul_highAlignedSigC_T; // @[MulAddRecFN.scala:71:7, :163:20]
assign _io_toPostMul_bit0AlignedSigC_T = alignedSigC[0]; // @[MulAddRecFN.scala:132:12, :164:48]
assign io_toPostMul_bit0AlignedSigC_0 = _io_toPostMul_bit0AlignedSigC_T; // @[MulAddRecFN.scala:71:7, :164:48]
assign io_mulAddA = io_mulAddA_0; // @[MulAddRecFN.scala:71:7]
assign io_mulAddB = io_mulAddB_0; // @[MulAddRecFN.scala:71:7]
assign io_mulAddC = io_mulAddC_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_isSigNaNAny = io_toPostMul_isSigNaNAny_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_isNaNAOrB = io_toPostMul_isNaNAOrB_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_isInfA = io_toPostMul_isInfA_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_isZeroA = io_toPostMul_isZeroA_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_isInfB = io_toPostMul_isInfB_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_isZeroB = io_toPostMul_isZeroB_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_signProd = io_toPostMul_signProd_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_isNaNC = io_toPostMul_isNaNC_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_isInfC = io_toPostMul_isInfC_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_isZeroC = io_toPostMul_isZeroC_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_sExpSum = io_toPostMul_sExpSum_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_doSubMags = io_toPostMul_doSubMags_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_CIsDominant = io_toPostMul_CIsDominant_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_CDom_CAlignDist = io_toPostMul_CDom_CAlignDist_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_highAlignedSigC = io_toPostMul_highAlignedSigC_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_bit0AlignedSigC = io_toPostMul_bit0AlignedSigC_0; // @[MulAddRecFN.scala:71:7]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File package.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip
import chisel3._
import chisel3.util._
import scala.math.min
import scala.collection.{immutable, mutable}
package object util {
implicit class UnzippableOption[S, T](val x: Option[(S, T)]) {
def unzip = (x.map(_._1), x.map(_._2))
}
implicit class UIntIsOneOf(private val x: UInt) extends AnyVal {
def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR
def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq)
}
implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal {
/** Like Vec.apply(idx), but tolerates indices of mismatched width */
def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0))
}
implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal {
def apply(idx: UInt): T = {
if (x.size <= 1) {
x.head
} else if (!isPow2(x.size)) {
// For non-power-of-2 seqs, reflect elements to simplify decoder
(x ++ x.takeRight(x.size & -x.size)).toSeq(idx)
} else {
// Ignore MSBs of idx
val truncIdx =
if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx
else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0)
x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) }
}
}
def extract(idx: UInt): T = VecInit(x).extract(idx)
def asUInt: UInt = Cat(x.map(_.asUInt).reverse)
def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n)
def rotate(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n)
def rotateRight(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
}
// allow bitwise ops on Seq[Bool] just like UInt
implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal {
def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b }
def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b }
def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b }
def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x
def >> (n: Int): Seq[Bool] = x drop n
def unary_~ : Seq[Bool] = x.map(!_)
def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_)
def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_)
def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_)
private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B)
}
implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal {
def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable))
def getElements: Seq[Element] = x match {
case e: Element => Seq(e)
case a: Aggregate => a.getElements.flatMap(_.getElements)
}
}
/** Any Data subtype that has a Bool member named valid. */
type DataCanBeValid = Data { val valid: Bool }
implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal {
def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable)
}
implicit class StringToAugmentedString(private val x: String) extends AnyVal {
/** converts from camel case to to underscores, also removing all spaces */
def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") {
case (acc, c) if c.isUpper => acc + "_" + c.toLower
case (acc, c) if c == ' ' => acc
case (acc, c) => acc + c
}
/** converts spaces or underscores to hyphens, also lowering case */
def kebab: String = x.toLowerCase map {
case ' ' => '-'
case '_' => '-'
case c => c
}
def named(name: Option[String]): String = {
x + name.map("_named_" + _ ).getOrElse("_with_no_name")
}
def named(name: String): String = named(Some(name))
}
implicit def uintToBitPat(x: UInt): BitPat = BitPat(x)
implicit def wcToUInt(c: WideCounter): UInt = c.value
implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal {
def sextTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x)
}
def padTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(0.U((n - x.getWidth).W), x)
}
// shifts left by n if n >= 0, or right by -n if n < 0
def << (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << n(w-1, 0)
Mux(n(w), shifted >> (1 << w), shifted)
}
// shifts right by n if n >= 0, or left by -n if n < 0
def >> (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << (1 << w) >> n(w-1, 0)
Mux(n(w), shifted, shifted >> (1 << w))
}
// Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts
def extract(hi: Int, lo: Int): UInt = {
require(hi >= lo-1)
if (hi == lo-1) 0.U
else x(hi, lo)
}
// Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts
def extractOption(hi: Int, lo: Int): Option[UInt] = {
require(hi >= lo-1)
if (hi == lo-1) None
else Some(x(hi, lo))
}
// like x & ~y, but first truncate or zero-extend y to x's width
def andNot(y: UInt): UInt = x & ~(y | (x & 0.U))
def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n)
def rotateRight(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r))
}
}
def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n))
def rotateLeft(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r))
}
}
// compute (this + y) % n, given (this < n) and (y < n)
def addWrap(y: UInt, n: Int): UInt = {
val z = x +& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0)
}
// compute (this - y) % n, given (this < n) and (y < n)
def subWrap(y: UInt, n: Int): UInt = {
val z = x -& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0)
}
def grouped(width: Int): Seq[UInt] =
(0 until x.getWidth by width).map(base => x(base + width - 1, base))
def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds
def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x)
// Like >=, but prevents x-prop for ('x >= 0)
def >== (y: UInt): Bool = x >= y || y === 0.U
}
implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal {
def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y)
def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y)
}
implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal {
def toInt: Int = if (x) 1 else 0
// this one's snagged from scalaz
def option[T](z: => T): Option[T] = if (x) Some(z) else None
}
implicit class IntToAugmentedInt(private val x: Int) extends AnyVal {
// exact log2
def log2: Int = {
require(isPow2(x))
log2Ceil(x)
}
}
def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x)
def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x))
def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0)
def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1)
def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None
// Fill 1s from low bits to high bits
def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth)
def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0))
helper(1, x)(width-1, 0)
}
// Fill 1s form high bits to low bits
def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth)
def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x >> s))
helper(1, x)(width-1, 0)
}
def OptimizationBarrier[T <: Data](in: T): T = {
val barrier = Module(new Module {
val io = IO(new Bundle {
val x = Input(chiselTypeOf(in))
val y = Output(chiselTypeOf(in))
})
io.y := io.x
override def desiredName = s"OptimizationBarrier_${in.typeName}"
})
barrier.io.x := in
barrier.io.y
}
/** Similar to Seq.groupBy except this returns a Seq instead of a Map
* Useful for deterministic code generation
*/
def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = {
val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]]
for (x <- xs) {
val key = f(x)
val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A])
l += x
}
map.view.map({ case (k, vs) => k -> vs.toList }).toList
}
def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match {
case 1 => List.fill(n)(in.head)
case x if x == n => in
case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in")
}
// HeterogeneousBag moved to standalond diplomacy
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts)
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag
}
| module OptimizationBarrier_TLBEntryData_118( // @[package.scala:267:30]
input clock, // @[package.scala:267:30]
input reset, // @[package.scala:267:30]
input [19:0] io_x_ppn, // @[package.scala:268:18]
input io_x_u, // @[package.scala:268:18]
input io_x_g, // @[package.scala:268:18]
input io_x_ae_ptw, // @[package.scala:268:18]
input io_x_ae_final, // @[package.scala:268:18]
input io_x_ae_stage2, // @[package.scala:268:18]
input io_x_pf, // @[package.scala:268:18]
input io_x_gf, // @[package.scala:268:18]
input io_x_sw, // @[package.scala:268:18]
input io_x_sx, // @[package.scala:268:18]
input io_x_sr, // @[package.scala:268:18]
input io_x_hw, // @[package.scala:268:18]
input io_x_hx, // @[package.scala:268:18]
input io_x_hr, // @[package.scala:268:18]
input io_x_pw, // @[package.scala:268:18]
input io_x_px, // @[package.scala:268:18]
input io_x_pr, // @[package.scala:268:18]
input io_x_ppp, // @[package.scala:268:18]
input io_x_pal, // @[package.scala:268:18]
input io_x_paa, // @[package.scala:268:18]
input io_x_eff, // @[package.scala:268:18]
input io_x_c, // @[package.scala:268:18]
input io_x_fragmented_superpage, // @[package.scala:268:18]
output io_y_u, // @[package.scala:268:18]
output io_y_ae_ptw, // @[package.scala:268:18]
output io_y_ae_final, // @[package.scala:268:18]
output io_y_ae_stage2, // @[package.scala:268:18]
output io_y_pf, // @[package.scala:268:18]
output io_y_gf, // @[package.scala:268:18]
output io_y_sw, // @[package.scala:268:18]
output io_y_sx, // @[package.scala:268:18]
output io_y_sr, // @[package.scala:268:18]
output io_y_hw, // @[package.scala:268:18]
output io_y_hx, // @[package.scala:268:18]
output io_y_hr, // @[package.scala:268:18]
output io_y_pw, // @[package.scala:268:18]
output io_y_px, // @[package.scala:268:18]
output io_y_pr, // @[package.scala:268:18]
output io_y_ppp, // @[package.scala:268:18]
output io_y_pal, // @[package.scala:268:18]
output io_y_paa, // @[package.scala:268:18]
output io_y_eff, // @[package.scala:268:18]
output io_y_c // @[package.scala:268:18]
);
wire [19:0] io_x_ppn_0 = io_x_ppn; // @[package.scala:267:30]
wire io_x_u_0 = io_x_u; // @[package.scala:267:30]
wire io_x_g_0 = io_x_g; // @[package.scala:267:30]
wire io_x_ae_ptw_0 = io_x_ae_ptw; // @[package.scala:267:30]
wire io_x_ae_final_0 = io_x_ae_final; // @[package.scala:267:30]
wire io_x_ae_stage2_0 = io_x_ae_stage2; // @[package.scala:267:30]
wire io_x_pf_0 = io_x_pf; // @[package.scala:267:30]
wire io_x_gf_0 = io_x_gf; // @[package.scala:267:30]
wire io_x_sw_0 = io_x_sw; // @[package.scala:267:30]
wire io_x_sx_0 = io_x_sx; // @[package.scala:267:30]
wire io_x_sr_0 = io_x_sr; // @[package.scala:267:30]
wire io_x_hw_0 = io_x_hw; // @[package.scala:267:30]
wire io_x_hx_0 = io_x_hx; // @[package.scala:267:30]
wire io_x_hr_0 = io_x_hr; // @[package.scala:267:30]
wire io_x_pw_0 = io_x_pw; // @[package.scala:267:30]
wire io_x_px_0 = io_x_px; // @[package.scala:267:30]
wire io_x_pr_0 = io_x_pr; // @[package.scala:267:30]
wire io_x_ppp_0 = io_x_ppp; // @[package.scala:267:30]
wire io_x_pal_0 = io_x_pal; // @[package.scala:267:30]
wire io_x_paa_0 = io_x_paa; // @[package.scala:267:30]
wire io_x_eff_0 = io_x_eff; // @[package.scala:267:30]
wire io_x_c_0 = io_x_c; // @[package.scala:267:30]
wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage; // @[package.scala:267:30]
wire [19:0] io_y_ppn = io_x_ppn_0; // @[package.scala:267:30]
wire io_y_u_0 = io_x_u_0; // @[package.scala:267:30]
wire io_y_g = io_x_g_0; // @[package.scala:267:30]
wire io_y_ae_ptw_0 = io_x_ae_ptw_0; // @[package.scala:267:30]
wire io_y_ae_final_0 = io_x_ae_final_0; // @[package.scala:267:30]
wire io_y_ae_stage2_0 = io_x_ae_stage2_0; // @[package.scala:267:30]
wire io_y_pf_0 = io_x_pf_0; // @[package.scala:267:30]
wire io_y_gf_0 = io_x_gf_0; // @[package.scala:267:30]
wire io_y_sw_0 = io_x_sw_0; // @[package.scala:267:30]
wire io_y_sx_0 = io_x_sx_0; // @[package.scala:267:30]
wire io_y_sr_0 = io_x_sr_0; // @[package.scala:267:30]
wire io_y_hw_0 = io_x_hw_0; // @[package.scala:267:30]
wire io_y_hx_0 = io_x_hx_0; // @[package.scala:267:30]
wire io_y_hr_0 = io_x_hr_0; // @[package.scala:267:30]
wire io_y_pw_0 = io_x_pw_0; // @[package.scala:267:30]
wire io_y_px_0 = io_x_px_0; // @[package.scala:267:30]
wire io_y_pr_0 = io_x_pr_0; // @[package.scala:267:30]
wire io_y_ppp_0 = io_x_ppp_0; // @[package.scala:267:30]
wire io_y_pal_0 = io_x_pal_0; // @[package.scala:267:30]
wire io_y_paa_0 = io_x_paa_0; // @[package.scala:267:30]
wire io_y_eff_0 = io_x_eff_0; // @[package.scala:267:30]
wire io_y_c_0 = io_x_c_0; // @[package.scala:267:30]
wire io_y_fragmented_superpage = io_x_fragmented_superpage_0; // @[package.scala:267:30]
assign io_y_u = io_y_u_0; // @[package.scala:267:30]
assign io_y_ae_ptw = io_y_ae_ptw_0; // @[package.scala:267:30]
assign io_y_ae_final = io_y_ae_final_0; // @[package.scala:267:30]
assign io_y_ae_stage2 = io_y_ae_stage2_0; // @[package.scala:267:30]
assign io_y_pf = io_y_pf_0; // @[package.scala:267:30]
assign io_y_gf = io_y_gf_0; // @[package.scala:267:30]
assign io_y_sw = io_y_sw_0; // @[package.scala:267:30]
assign io_y_sx = io_y_sx_0; // @[package.scala:267:30]
assign io_y_sr = io_y_sr_0; // @[package.scala:267:30]
assign io_y_hw = io_y_hw_0; // @[package.scala:267:30]
assign io_y_hx = io_y_hx_0; // @[package.scala:267:30]
assign io_y_hr = io_y_hr_0; // @[package.scala:267:30]
assign io_y_pw = io_y_pw_0; // @[package.scala:267:30]
assign io_y_px = io_y_px_0; // @[package.scala:267:30]
assign io_y_pr = io_y_pr_0; // @[package.scala:267:30]
assign io_y_ppp = io_y_ppp_0; // @[package.scala:267:30]
assign io_y_pal = io_y_pal_0; // @[package.scala:267:30]
assign io_y_paa = io_y_paa_0; // @[package.scala:267:30]
assign io_y_eff = io_y_eff_0; // @[package.scala:267:30]
assign io_y_c = io_y_c_0; // @[package.scala:267:30]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File package.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip
import chisel3._
import chisel3.util._
import scala.math.min
import scala.collection.{immutable, mutable}
package object util {
implicit class UnzippableOption[S, T](val x: Option[(S, T)]) {
def unzip = (x.map(_._1), x.map(_._2))
}
implicit class UIntIsOneOf(private val x: UInt) extends AnyVal {
def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR
def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq)
}
implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal {
/** Like Vec.apply(idx), but tolerates indices of mismatched width */
def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0))
}
implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal {
def apply(idx: UInt): T = {
if (x.size <= 1) {
x.head
} else if (!isPow2(x.size)) {
// For non-power-of-2 seqs, reflect elements to simplify decoder
(x ++ x.takeRight(x.size & -x.size)).toSeq(idx)
} else {
// Ignore MSBs of idx
val truncIdx =
if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx
else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0)
x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) }
}
}
def extract(idx: UInt): T = VecInit(x).extract(idx)
def asUInt: UInt = Cat(x.map(_.asUInt).reverse)
def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n)
def rotate(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n)
def rotateRight(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
}
// allow bitwise ops on Seq[Bool] just like UInt
implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal {
def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b }
def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b }
def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b }
def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x
def >> (n: Int): Seq[Bool] = x drop n
def unary_~ : Seq[Bool] = x.map(!_)
def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_)
def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_)
def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_)
private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B)
}
implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal {
def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable))
def getElements: Seq[Element] = x match {
case e: Element => Seq(e)
case a: Aggregate => a.getElements.flatMap(_.getElements)
}
}
/** Any Data subtype that has a Bool member named valid. */
type DataCanBeValid = Data { val valid: Bool }
implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal {
def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable)
}
implicit class StringToAugmentedString(private val x: String) extends AnyVal {
/** converts from camel case to to underscores, also removing all spaces */
def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") {
case (acc, c) if c.isUpper => acc + "_" + c.toLower
case (acc, c) if c == ' ' => acc
case (acc, c) => acc + c
}
/** converts spaces or underscores to hyphens, also lowering case */
def kebab: String = x.toLowerCase map {
case ' ' => '-'
case '_' => '-'
case c => c
}
def named(name: Option[String]): String = {
x + name.map("_named_" + _ ).getOrElse("_with_no_name")
}
def named(name: String): String = named(Some(name))
}
implicit def uintToBitPat(x: UInt): BitPat = BitPat(x)
implicit def wcToUInt(c: WideCounter): UInt = c.value
implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal {
def sextTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x)
}
def padTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(0.U((n - x.getWidth).W), x)
}
// shifts left by n if n >= 0, or right by -n if n < 0
def << (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << n(w-1, 0)
Mux(n(w), shifted >> (1 << w), shifted)
}
// shifts right by n if n >= 0, or left by -n if n < 0
def >> (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << (1 << w) >> n(w-1, 0)
Mux(n(w), shifted, shifted >> (1 << w))
}
// Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts
def extract(hi: Int, lo: Int): UInt = {
require(hi >= lo-1)
if (hi == lo-1) 0.U
else x(hi, lo)
}
// Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts
def extractOption(hi: Int, lo: Int): Option[UInt] = {
require(hi >= lo-1)
if (hi == lo-1) None
else Some(x(hi, lo))
}
// like x & ~y, but first truncate or zero-extend y to x's width
def andNot(y: UInt): UInt = x & ~(y | (x & 0.U))
def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n)
def rotateRight(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r))
}
}
def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n))
def rotateLeft(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r))
}
}
// compute (this + y) % n, given (this < n) and (y < n)
def addWrap(y: UInt, n: Int): UInt = {
val z = x +& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0)
}
// compute (this - y) % n, given (this < n) and (y < n)
def subWrap(y: UInt, n: Int): UInt = {
val z = x -& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0)
}
def grouped(width: Int): Seq[UInt] =
(0 until x.getWidth by width).map(base => x(base + width - 1, base))
def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds
def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x)
// Like >=, but prevents x-prop for ('x >= 0)
def >== (y: UInt): Bool = x >= y || y === 0.U
}
implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal {
def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y)
def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y)
}
implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal {
def toInt: Int = if (x) 1 else 0
// this one's snagged from scalaz
def option[T](z: => T): Option[T] = if (x) Some(z) else None
}
implicit class IntToAugmentedInt(private val x: Int) extends AnyVal {
// exact log2
def log2: Int = {
require(isPow2(x))
log2Ceil(x)
}
}
def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x)
def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x))
def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0)
def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1)
def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None
// Fill 1s from low bits to high bits
def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth)
def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0))
helper(1, x)(width-1, 0)
}
// Fill 1s form high bits to low bits
def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth)
def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x >> s))
helper(1, x)(width-1, 0)
}
def OptimizationBarrier[T <: Data](in: T): T = {
val barrier = Module(new Module {
val io = IO(new Bundle {
val x = Input(chiselTypeOf(in))
val y = Output(chiselTypeOf(in))
})
io.y := io.x
override def desiredName = s"OptimizationBarrier_${in.typeName}"
})
barrier.io.x := in
barrier.io.y
}
/** Similar to Seq.groupBy except this returns a Seq instead of a Map
* Useful for deterministic code generation
*/
def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = {
val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]]
for (x <- xs) {
val key = f(x)
val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A])
l += x
}
map.view.map({ case (k, vs) => k -> vs.toList }).toList
}
def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match {
case 1 => List.fill(n)(in.head)
case x if x == n => in
case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in")
}
// HeterogeneousBag moved to standalond diplomacy
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts)
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag
}
File Nodes.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import org.chipsalliance.diplomacy.nodes._
import freechips.rocketchip.util.{AsyncQueueParams,RationalDirection}
case object TLMonitorBuilder extends Field[TLMonitorArgs => TLMonitorBase](args => new TLMonitor(args))
object TLImp extends NodeImp[TLMasterPortParameters, TLSlavePortParameters, TLEdgeOut, TLEdgeIn, TLBundle]
{
def edgeO(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeOut(pd, pu, p, sourceInfo)
def edgeI(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeIn (pd, pu, p, sourceInfo)
def bundleO(eo: TLEdgeOut) = TLBundle(eo.bundle)
def bundleI(ei: TLEdgeIn) = TLBundle(ei.bundle)
def render(ei: TLEdgeIn) = RenderedEdge(colour = "#000000" /* black */, label = (ei.manager.beatBytes * 8).toString)
override def monitor(bundle: TLBundle, edge: TLEdgeIn): Unit = {
val monitor = Module(edge.params(TLMonitorBuilder)(TLMonitorArgs(edge)))
monitor.io.in := bundle
}
override def mixO(pd: TLMasterPortParameters, node: OutwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLMasterPortParameters =
pd.v1copy(clients = pd.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })
override def mixI(pu: TLSlavePortParameters, node: InwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLSlavePortParameters =
pu.v1copy(managers = pu.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })
}
trait TLFormatNode extends FormatNode[TLEdgeIn, TLEdgeOut]
case class TLClientNode(portParams: Seq[TLMasterPortParameters])(implicit valName: ValName) extends SourceNode(TLImp)(portParams) with TLFormatNode
case class TLManagerNode(portParams: Seq[TLSlavePortParameters])(implicit valName: ValName) extends SinkNode(TLImp)(portParams) with TLFormatNode
case class TLAdapterNode(
clientFn: TLMasterPortParameters => TLMasterPortParameters = { s => s },
managerFn: TLSlavePortParameters => TLSlavePortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLImp)(clientFn, managerFn) with TLFormatNode
case class TLJunctionNode(
clientFn: Seq[TLMasterPortParameters] => Seq[TLMasterPortParameters],
managerFn: Seq[TLSlavePortParameters] => Seq[TLSlavePortParameters])(
implicit valName: ValName)
extends JunctionNode(TLImp)(clientFn, managerFn) with TLFormatNode
case class TLIdentityNode()(implicit valName: ValName) extends IdentityNode(TLImp)() with TLFormatNode
object TLNameNode {
def apply(name: ValName) = TLIdentityNode()(name)
def apply(name: Option[String]): TLIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLIdentityNode = apply(Some(name))
}
case class TLEphemeralNode()(implicit valName: ValName) extends EphemeralNode(TLImp)()
object TLTempNode {
def apply(): TLEphemeralNode = TLEphemeralNode()(ValName("temp"))
}
case class TLNexusNode(
clientFn: Seq[TLMasterPortParameters] => TLMasterPortParameters,
managerFn: Seq[TLSlavePortParameters] => TLSlavePortParameters)(
implicit valName: ValName)
extends NexusNode(TLImp)(clientFn, managerFn) with TLFormatNode
abstract class TLCustomNode(implicit valName: ValName)
extends CustomNode(TLImp) with TLFormatNode
// Asynchronous crossings
trait TLAsyncFormatNode extends FormatNode[TLAsyncEdgeParameters, TLAsyncEdgeParameters]
object TLAsyncImp extends SimpleNodeImp[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncEdgeParameters, TLAsyncBundle]
{
def edge(pd: TLAsyncClientPortParameters, pu: TLAsyncManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLAsyncEdgeParameters(pd, pu, p, sourceInfo)
def bundle(e: TLAsyncEdgeParameters) = new TLAsyncBundle(e.bundle)
def render(e: TLAsyncEdgeParameters) = RenderedEdge(colour = "#ff0000" /* red */, label = e.manager.async.depth.toString)
override def mixO(pd: TLAsyncClientPortParameters, node: OutwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncClientPortParameters =
pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }))
override def mixI(pu: TLAsyncManagerPortParameters, node: InwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncManagerPortParameters =
pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }))
}
case class TLAsyncAdapterNode(
clientFn: TLAsyncClientPortParameters => TLAsyncClientPortParameters = { s => s },
managerFn: TLAsyncManagerPortParameters => TLAsyncManagerPortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLAsyncImp)(clientFn, managerFn) with TLAsyncFormatNode
case class TLAsyncIdentityNode()(implicit valName: ValName) extends IdentityNode(TLAsyncImp)() with TLAsyncFormatNode
object TLAsyncNameNode {
def apply(name: ValName) = TLAsyncIdentityNode()(name)
def apply(name: Option[String]): TLAsyncIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLAsyncIdentityNode = apply(Some(name))
}
case class TLAsyncSourceNode(sync: Option[Int])(implicit valName: ValName)
extends MixedAdapterNode(TLImp, TLAsyncImp)(
dFn = { p => TLAsyncClientPortParameters(p) },
uFn = { p => p.base.v1copy(minLatency = p.base.minLatency + sync.getOrElse(p.async.sync)) }) with FormatNode[TLEdgeIn, TLAsyncEdgeParameters] // discard cycles in other clock domain
case class TLAsyncSinkNode(async: AsyncQueueParams)(implicit valName: ValName)
extends MixedAdapterNode(TLAsyncImp, TLImp)(
dFn = { p => p.base.v1copy(minLatency = p.base.minLatency + async.sync) },
uFn = { p => TLAsyncManagerPortParameters(async, p) }) with FormatNode[TLAsyncEdgeParameters, TLEdgeOut]
// Rationally related crossings
trait TLRationalFormatNode extends FormatNode[TLRationalEdgeParameters, TLRationalEdgeParameters]
object TLRationalImp extends SimpleNodeImp[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalEdgeParameters, TLRationalBundle]
{
def edge(pd: TLRationalClientPortParameters, pu: TLRationalManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLRationalEdgeParameters(pd, pu, p, sourceInfo)
def bundle(e: TLRationalEdgeParameters) = new TLRationalBundle(e.bundle)
def render(e: TLRationalEdgeParameters) = RenderedEdge(colour = "#00ff00" /* green */)
override def mixO(pd: TLRationalClientPortParameters, node: OutwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalClientPortParameters =
pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }))
override def mixI(pu: TLRationalManagerPortParameters, node: InwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalManagerPortParameters =
pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }))
}
case class TLRationalAdapterNode(
clientFn: TLRationalClientPortParameters => TLRationalClientPortParameters = { s => s },
managerFn: TLRationalManagerPortParameters => TLRationalManagerPortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLRationalImp)(clientFn, managerFn) with TLRationalFormatNode
case class TLRationalIdentityNode()(implicit valName: ValName) extends IdentityNode(TLRationalImp)() with TLRationalFormatNode
object TLRationalNameNode {
def apply(name: ValName) = TLRationalIdentityNode()(name)
def apply(name: Option[String]): TLRationalIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLRationalIdentityNode = apply(Some(name))
}
case class TLRationalSourceNode()(implicit valName: ValName)
extends MixedAdapterNode(TLImp, TLRationalImp)(
dFn = { p => TLRationalClientPortParameters(p) },
uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLRationalEdgeParameters] // discard cycles from other clock domain
case class TLRationalSinkNode(direction: RationalDirection)(implicit valName: ValName)
extends MixedAdapterNode(TLRationalImp, TLImp)(
dFn = { p => p.base.v1copy(minLatency = 1) },
uFn = { p => TLRationalManagerPortParameters(direction, p) }) with FormatNode[TLRationalEdgeParameters, TLEdgeOut]
// Credited version of TileLink channels
trait TLCreditedFormatNode extends FormatNode[TLCreditedEdgeParameters, TLCreditedEdgeParameters]
object TLCreditedImp extends SimpleNodeImp[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedEdgeParameters, TLCreditedBundle]
{
def edge(pd: TLCreditedClientPortParameters, pu: TLCreditedManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLCreditedEdgeParameters(pd, pu, p, sourceInfo)
def bundle(e: TLCreditedEdgeParameters) = new TLCreditedBundle(e.bundle)
def render(e: TLCreditedEdgeParameters) = RenderedEdge(colour = "#ffff00" /* yellow */, e.delay.toString)
override def mixO(pd: TLCreditedClientPortParameters, node: OutwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedClientPortParameters =
pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }))
override def mixI(pu: TLCreditedManagerPortParameters, node: InwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedManagerPortParameters =
pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }))
}
case class TLCreditedAdapterNode(
clientFn: TLCreditedClientPortParameters => TLCreditedClientPortParameters = { s => s },
managerFn: TLCreditedManagerPortParameters => TLCreditedManagerPortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLCreditedImp)(clientFn, managerFn) with TLCreditedFormatNode
case class TLCreditedIdentityNode()(implicit valName: ValName) extends IdentityNode(TLCreditedImp)() with TLCreditedFormatNode
object TLCreditedNameNode {
def apply(name: ValName) = TLCreditedIdentityNode()(name)
def apply(name: Option[String]): TLCreditedIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLCreditedIdentityNode = apply(Some(name))
}
case class TLCreditedSourceNode(delay: TLCreditedDelay)(implicit valName: ValName)
extends MixedAdapterNode(TLImp, TLCreditedImp)(
dFn = { p => TLCreditedClientPortParameters(delay, p) },
uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLCreditedEdgeParameters] // discard cycles from other clock domain
case class TLCreditedSinkNode(delay: TLCreditedDelay)(implicit valName: ValName)
extends MixedAdapterNode(TLCreditedImp, TLImp)(
dFn = { p => p.base.v1copy(minLatency = 1) },
uFn = { p => TLCreditedManagerPortParameters(delay, p) }) with FormatNode[TLCreditedEdgeParameters, TLEdgeOut]
File WidthWidget.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy.lazymodule._
import freechips.rocketchip.diplomacy.AddressSet
import freechips.rocketchip.util.{Repeater, UIntToOH1}
// innBeatBytes => the new client-facing bus width
class TLWidthWidget(innerBeatBytes: Int)(implicit p: Parameters) extends LazyModule
{
private def noChangeRequired(manager: TLManagerPortParameters) = manager.beatBytes == innerBeatBytes
val node = new TLAdapterNode(
clientFn = { case c => c },
managerFn = { case m => m.v1copy(beatBytes = innerBeatBytes) }){
override def circuitIdentity = edges.out.map(_.manager).forall(noChangeRequired)
}
override lazy val desiredName = s"TLWidthWidget$innerBeatBytes"
lazy val module = new Impl
class Impl extends LazyModuleImp(this) {
def merge[T <: TLDataChannel](edgeIn: TLEdge, in: DecoupledIO[T], edgeOut: TLEdge, out: DecoupledIO[T]) = {
val inBytes = edgeIn.manager.beatBytes
val outBytes = edgeOut.manager.beatBytes
val ratio = outBytes / inBytes
val keepBits = log2Ceil(outBytes)
val dropBits = log2Ceil(inBytes)
val countBits = log2Ceil(ratio)
val size = edgeIn.size(in.bits)
val hasData = edgeIn.hasData(in.bits)
val limit = UIntToOH1(size, keepBits) >> dropBits
val count = RegInit(0.U(countBits.W))
val first = count === 0.U
val last = count === limit || !hasData
val enable = Seq.tabulate(ratio) { i => !((count ^ i.U) & limit).orR }
val corrupt_reg = RegInit(false.B)
val corrupt_in = edgeIn.corrupt(in.bits)
val corrupt_out = corrupt_in || corrupt_reg
when (in.fire) {
count := count + 1.U
corrupt_reg := corrupt_out
when (last) {
count := 0.U
corrupt_reg := false.B
}
}
def helper(idata: UInt): UInt = {
// rdata is X until the first time a multi-beat write occurs.
// Prevent the X from leaking outside by jamming the mux control until
// the first time rdata is written (and hence no longer X).
val rdata_written_once = RegInit(false.B)
val masked_enable = enable.map(_ || !rdata_written_once)
val odata = Seq.fill(ratio) { WireInit(idata) }
val rdata = Reg(Vec(ratio-1, chiselTypeOf(idata)))
val pdata = rdata :+ idata
val mdata = (masked_enable zip (odata zip pdata)) map { case (e, (o, p)) => Mux(e, o, p) }
when (in.fire && !last) {
rdata_written_once := true.B
(rdata zip mdata) foreach { case (r, m) => r := m }
}
Cat(mdata.reverse)
}
in.ready := out.ready || !last
out.valid := in.valid && last
out.bits := in.bits
// Don't put down hardware if we never carry data
edgeOut.data(out.bits) := (if (edgeIn.staticHasData(in.bits) == Some(false)) 0.U else helper(edgeIn.data(in.bits)))
edgeOut.corrupt(out.bits) := corrupt_out
(out.bits, in.bits) match {
case (o: TLBundleA, i: TLBundleA) => o.mask := edgeOut.mask(o.address, o.size) & Mux(hasData, helper(i.mask), ~0.U(outBytes.W))
case (o: TLBundleB, i: TLBundleB) => o.mask := edgeOut.mask(o.address, o.size) & Mux(hasData, helper(i.mask), ~0.U(outBytes.W))
case (o: TLBundleC, i: TLBundleC) => ()
case (o: TLBundleD, i: TLBundleD) => ()
case _ => require(false, "Impossible bundle combination in WidthWidget")
}
}
def split[T <: TLDataChannel](edgeIn: TLEdge, in: DecoupledIO[T], edgeOut: TLEdge, out: DecoupledIO[T], sourceMap: UInt => UInt) = {
val inBytes = edgeIn.manager.beatBytes
val outBytes = edgeOut.manager.beatBytes
val ratio = inBytes / outBytes
val keepBits = log2Ceil(inBytes)
val dropBits = log2Ceil(outBytes)
val countBits = log2Ceil(ratio)
val size = edgeIn.size(in.bits)
val hasData = edgeIn.hasData(in.bits)
val limit = UIntToOH1(size, keepBits) >> dropBits
val count = RegInit(0.U(countBits.W))
val first = count === 0.U
val last = count === limit || !hasData
when (out.fire) {
count := count + 1.U
when (last) { count := 0.U }
}
// For sub-beat transfer, extract which part matters
val sel = in.bits match {
case a: TLBundleA => a.address(keepBits-1, dropBits)
case b: TLBundleB => b.address(keepBits-1, dropBits)
case c: TLBundleC => c.address(keepBits-1, dropBits)
case d: TLBundleD => {
val sel = sourceMap(d.source)
val hold = Mux(first, sel, RegEnable(sel, first)) // a_first is not for whole xfer
hold & ~limit // if more than one a_first/xfer, the address must be aligned anyway
}
}
val index = sel | count
def helper(idata: UInt, width: Int): UInt = {
val mux = VecInit.tabulate(ratio) { i => idata((i+1)*outBytes*width-1, i*outBytes*width) }
mux(index)
}
out.bits := in.bits
out.valid := in.valid
in.ready := out.ready
// Don't put down hardware if we never carry data
edgeOut.data(out.bits) := (if (edgeIn.staticHasData(in.bits) == Some(false)) 0.U else helper(edgeIn.data(in.bits), 8))
(out.bits, in.bits) match {
case (o: TLBundleA, i: TLBundleA) => o.mask := helper(i.mask, 1)
case (o: TLBundleB, i: TLBundleB) => o.mask := helper(i.mask, 1)
case (o: TLBundleC, i: TLBundleC) => () // replicating corrupt to all beats is ok
case (o: TLBundleD, i: TLBundleD) => ()
case _ => require(false, "Impossbile bundle combination in WidthWidget")
}
// Repeat the input if we're not last
!last
}
def splice[T <: TLDataChannel](edgeIn: TLEdge, in: DecoupledIO[T], edgeOut: TLEdge, out: DecoupledIO[T], sourceMap: UInt => UInt) = {
if (edgeIn.manager.beatBytes == edgeOut.manager.beatBytes) {
// nothing to do; pass it through
out.bits := in.bits
out.valid := in.valid
in.ready := out.ready
} else if (edgeIn.manager.beatBytes > edgeOut.manager.beatBytes) {
// split input to output
val repeat = Wire(Bool())
val repeated = Repeater(in, repeat)
val cated = Wire(chiselTypeOf(repeated))
cated <> repeated
edgeIn.data(cated.bits) := Cat(
edgeIn.data(repeated.bits)(edgeIn.manager.beatBytes*8-1, edgeOut.manager.beatBytes*8),
edgeIn.data(in.bits)(edgeOut.manager.beatBytes*8-1, 0))
repeat := split(edgeIn, cated, edgeOut, out, sourceMap)
} else {
// merge input to output
merge(edgeIn, in, edgeOut, out)
}
}
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
// If the master is narrower than the slave, the D channel must be narrowed.
// This is tricky, because the D channel has no address data.
// Thus, you don't know which part of a sub-beat transfer to extract.
// To fix this, we record the relevant address bits for all sources.
// The assumption is that this sort of situation happens only where
// you connect a narrow master to the system bus, so there are few sources.
def sourceMap(source_bits: UInt) = {
val source = if (edgeIn.client.endSourceId == 1) 0.U(0.W) else source_bits
require (edgeOut.manager.beatBytes > edgeIn.manager.beatBytes)
val keepBits = log2Ceil(edgeOut.manager.beatBytes)
val dropBits = log2Ceil(edgeIn.manager.beatBytes)
val sources = Reg(Vec(edgeIn.client.endSourceId, UInt((keepBits-dropBits).W)))
val a_sel = in.a.bits.address(keepBits-1, dropBits)
when (in.a.fire) {
if (edgeIn.client.endSourceId == 1) { // avoid extraction-index-width warning
sources(0) := a_sel
} else {
sources(in.a.bits.source) := a_sel
}
}
// depopulate unused source registers:
edgeIn.client.unusedSources.foreach { id => sources(id) := 0.U }
val bypass = in.a.valid && in.a.bits.source === source
if (edgeIn.manager.minLatency > 0) sources(source)
else Mux(bypass, a_sel, sources(source))
}
splice(edgeIn, in.a, edgeOut, out.a, sourceMap)
splice(edgeOut, out.d, edgeIn, in.d, sourceMap)
if (edgeOut.manager.anySupportAcquireB && edgeIn.client.anySupportProbe) {
splice(edgeOut, out.b, edgeIn, in.b, sourceMap)
splice(edgeIn, in.c, edgeOut, out.c, sourceMap)
out.e.valid := in.e.valid
out.e.bits := in.e.bits
in.e.ready := out.e.ready
} else {
in.b.valid := false.B
in.c.ready := true.B
in.e.ready := true.B
out.b.ready := true.B
out.c.valid := false.B
out.e.valid := false.B
}
}
}
}
object TLWidthWidget
{
def apply(innerBeatBytes: Int)(implicit p: Parameters): TLNode =
{
val widget = LazyModule(new TLWidthWidget(innerBeatBytes))
widget.node
}
def apply(wrapper: TLBusWrapper)(implicit p: Parameters): TLNode = apply(wrapper.beatBytes)
}
// Synthesizable unit tests
import freechips.rocketchip.unittest._
class TLRAMWidthWidget(first: Int, second: Int, txns: Int)(implicit p: Parameters) extends LazyModule {
val fuzz = LazyModule(new TLFuzzer(txns))
val model = LazyModule(new TLRAMModel("WidthWidget"))
val ram = LazyModule(new TLRAM(AddressSet(0x0, 0x3ff)))
(ram.node
:= TLDelayer(0.1)
:= TLFragmenter(4, 256)
:= TLWidthWidget(second)
:= TLWidthWidget(first)
:= TLDelayer(0.1)
:= model.node
:= fuzz.node)
lazy val module = new Impl
class Impl extends LazyModuleImp(this) with UnitTestModule {
io.finished := fuzz.module.io.finished
}
}
class TLRAMWidthWidgetTest(little: Int, big: Int, txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) {
val dut = Module(LazyModule(new TLRAMWidthWidget(little,big,txns)).module)
dut.io.start := DontCare
io.finished := dut.io.finished
}
File LazyModuleImp.scala:
package org.chipsalliance.diplomacy.lazymodule
import chisel3.{withClockAndReset, Module, RawModule, Reset, _}
import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo}
import firrtl.passes.InlineAnnotation
import org.chipsalliance.cde.config.Parameters
import org.chipsalliance.diplomacy.nodes.Dangle
import scala.collection.immutable.SortedMap
/** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]].
*
* This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy.
*/
sealed trait LazyModuleImpLike extends RawModule {
/** [[LazyModule]] that contains this instance. */
val wrapper: LazyModule
/** IOs that will be automatically "punched" for this instance. */
val auto: AutoBundle
/** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */
protected[diplomacy] val dangles: Seq[Dangle]
// [[wrapper.module]] had better not be accessed while LazyModules are still being built!
require(
LazyModule.scope.isEmpty,
s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}"
)
/** Set module name. Defaults to the containing LazyModule's desiredName. */
override def desiredName: String = wrapper.desiredName
suggestName(wrapper.suggestedName)
/** [[Parameters]] for chisel [[Module]]s. */
implicit val p: Parameters = wrapper.p
/** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and
* submodules.
*/
protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = {
// 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]],
// 2. return [[Dangle]]s from each module.
val childDangles = wrapper.children.reverse.flatMap { c =>
implicit val sourceInfo: SourceInfo = c.info
c.cloneProto.map { cp =>
// If the child is a clone, then recursively set cloneProto of its children as well
def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = {
require(bases.size == clones.size)
(bases.zip(clones)).map { case (l, r) =>
require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}")
l.cloneProto = Some(r)
assignCloneProtos(l.children, r.children)
}
}
assignCloneProtos(c.children, cp.children)
// Clone the child module as a record, and get its [[AutoBundle]]
val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName)
val clonedAuto = clone("auto").asInstanceOf[AutoBundle]
// Get the empty [[Dangle]]'s of the cloned child
val rawDangles = c.cloneDangles()
require(rawDangles.size == clonedAuto.elements.size)
// Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s
val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) }
dangles
}.getOrElse {
// For non-clones, instantiate the child module
val mod = try {
Module(c.module)
} catch {
case e: ChiselException => {
println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}")
throw e
}
}
mod.dangles
}
}
// Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]].
// This will result in a sequence of [[Dangle]] from these [[BaseNode]]s.
val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate())
// Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]]
val allDangles = nodeDangles ++ childDangles
// Group [[allDangles]] by their [[source]].
val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*)
// For each [[source]] set of [[Dangle]]s of size 2, ensure that these
// can be connected as a source-sink pair (have opposite flipped value).
// Make the connection and mark them as [[done]].
val done = Set() ++ pairing.values.filter(_.size == 2).map {
case Seq(a, b) =>
require(a.flipped != b.flipped)
// @todo <> in chisel3 makes directionless connection.
if (a.flipped) {
a.data <> b.data
} else {
b.data <> a.data
}
a.source
case _ => None
}
// Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module.
val forward = allDangles.filter(d => !done(d.source))
// Generate [[AutoBundle]] IO from [[forward]].
val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*))
// Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]]
val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) =>
if (d.flipped) {
d.data <> io
} else {
io <> d.data
}
d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name)
}
// Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]].
wrapper.inModuleBody.reverse.foreach {
_()
}
if (wrapper.shouldBeInlined) {
chisel3.experimental.annotate(new ChiselAnnotation {
def toFirrtl = InlineAnnotation(toNamed)
})
}
// Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]].
(auto, dangles)
}
}
/** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike {
/** Instantiate hardware of this `Module`. */
val (auto, dangles) = instantiate()
}
/** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike {
// These wires are the default clock+reset for all LazyModule children.
// It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the
// [[LazyRawModuleImp]] children.
// Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly.
/** drive clock explicitly. */
val childClock: Clock = Wire(Clock())
/** drive reset explicitly. */
val childReset: Reset = Wire(Reset())
// the default is that these are disabled
childClock := false.B.asClock
childReset := chisel3.DontCare
def provideImplicitClockToLazyChildren: Boolean = false
val (auto, dangles) =
if (provideImplicitClockToLazyChildren) {
withClockAndReset(childClock, childReset) { instantiate() }
} else {
instantiate()
}
}
File Repeater.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util.{Decoupled, DecoupledIO}
// A Repeater passes its input to its output, unless repeat is asserted.
// When repeat is asserted, the Repeater copies the input and repeats it next cycle.
class Repeater[T <: Data](gen: T) extends Module
{
override def desiredName = s"Repeater_${gen.typeName}"
val io = IO( new Bundle {
val repeat = Input(Bool())
val full = Output(Bool())
val enq = Flipped(Decoupled(gen.cloneType))
val deq = Decoupled(gen.cloneType)
} )
val full = RegInit(false.B)
val saved = Reg(gen.cloneType)
// When !full, a repeater is pass-through
io.deq.valid := io.enq.valid || full
io.enq.ready := io.deq.ready && !full
io.deq.bits := Mux(full, saved, io.enq.bits)
io.full := full
when (io.enq.fire && io.repeat) { full := true.B; saved := io.enq.bits }
when (io.deq.fire && !io.repeat) { full := false.B }
}
object Repeater
{
def apply[T <: Data](enq: DecoupledIO[T], repeat: Bool): DecoupledIO[T] = {
val repeater = Module(new Repeater(chiselTypeOf(enq.bits)))
repeater.io.repeat := repeat
repeater.io.enq <> enq
repeater.io.deq
}
}
| module TLWidthWidget8_3( // @[WidthWidget.scala:27:9]
input clock, // @[WidthWidget.scala:27:9]
input reset, // @[WidthWidget.scala:27:9]
output auto_anon_in_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_in_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_in_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [9:0] auto_anon_in_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [28:0] auto_anon_in_a_bits_address, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_a_bits_user_amba_prot_bufferable, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_a_bits_user_amba_prot_modifiable, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_a_bits_user_amba_prot_readalloc, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_a_bits_user_amba_prot_writealloc, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_a_bits_user_amba_prot_privileged, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_a_bits_user_amba_prot_secure, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_a_bits_user_amba_prot_fetch, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_anon_in_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_anon_in_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_anon_in_d_bits_param, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_in_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [9:0] auto_anon_in_d_bits_source, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_d_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_d_bits_denied, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_anon_in_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_out_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_out_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [9:0] auto_anon_out_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [28:0] auto_anon_out_a_bits_address, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_a_bits_user_amba_prot_bufferable, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_a_bits_user_amba_prot_modifiable, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_a_bits_user_amba_prot_readalloc, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_a_bits_user_amba_prot_writealloc, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_a_bits_user_amba_prot_privileged, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_a_bits_user_amba_prot_secure, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_a_bits_user_amba_prot_fetch, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_anon_out_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_anon_out_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_anon_out_d_bits_param, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_out_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [9:0] auto_anon_out_d_bits_source, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_d_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_d_bits_denied, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_anon_out_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_d_bits_corrupt // @[LazyModuleImp.scala:107:25]
);
wire _repeated_repeater_io_enq_ready; // @[Repeater.scala:36:26]
wire _repeated_repeater_io_deq_valid; // @[Repeater.scala:36:26]
wire [2:0] _repeated_repeater_io_deq_bits_opcode; // @[Repeater.scala:36:26]
wire [2:0] _repeated_repeater_io_deq_bits_size; // @[Repeater.scala:36:26]
wire [28:0] _repeated_repeater_io_deq_bits_address; // @[Repeater.scala:36:26]
wire [7:0] _repeated_repeater_io_deq_bits_mask; // @[Repeater.scala:36:26]
wire [63:0] _repeated_repeater_io_deq_bits_data; // @[Repeater.scala:36:26]
wire [9:0] _repeat_limit_T = 10'h7 << _repeated_repeater_io_deq_bits_size; // @[package.scala:243:71]
reg repeat_count; // @[WidthWidget.scala:105:26]
wire repeat_last = repeat_count == ~(_repeat_limit_T[2]) | _repeated_repeater_io_deq_bits_opcode[2]; // @[package.scala:243:{46,71,76}]
wire repeat_index = _repeated_repeater_io_deq_bits_address[2] | repeat_count; // @[Repeater.scala:36:26]
wire [9:0] _limit_T = 10'h7 << auto_anon_out_d_bits_size; // @[package.scala:243:71]
reg count; // @[WidthWidget.scala:40:27]
wire last = count == ~(_limit_T[2]) | ~(auto_anon_out_d_bits_opcode[0]); // @[package.scala:243:{46,71,76}]
reg corrupt_reg; // @[WidthWidget.scala:45:32]
wire corrupt_out = auto_anon_out_d_bits_corrupt | corrupt_reg; // @[WidthWidget.scala:45:32, :47:36]
wire anonOut_d_ready = auto_anon_in_d_ready | ~last; // @[WidthWidget.scala:42:36, :76:{29,32}]
wire anonIn_d_valid = auto_anon_out_d_valid & last; // @[WidthWidget.scala:42:36, :77:29]
reg anonIn_d_bits_data_rdata_written_once; // @[WidthWidget.scala:62:41]
wire anonIn_d_bits_data_masked_enable_0 = ~(count & ~(_limit_T[2])) | ~anonIn_d_bits_data_rdata_written_once; // @[package.scala:243:{46,71,76}]
reg [31:0] anonIn_d_bits_data_rdata_0; // @[WidthWidget.scala:66:24]
wire _anonIn_d_bits_data_T = anonOut_d_ready & auto_anon_out_d_valid; // @[Decoupled.scala:51:35]
wire _anonIn_d_bits_data_T_2 = _anonIn_d_bits_data_T & ~last; // @[Decoupled.scala:51:35]
always @(posedge clock) begin // @[WidthWidget.scala:27:9]
if (reset) begin // @[WidthWidget.scala:27:9]
repeat_count <= 1'h0; // @[WidthWidget.scala:27:9, :105:26]
count <= 1'h0; // @[WidthWidget.scala:27:9, :40:27]
corrupt_reg <= 1'h0; // @[WidthWidget.scala:27:9, :45:32]
anonIn_d_bits_data_rdata_written_once <= 1'h0; // @[WidthWidget.scala:27:9, :62:41]
end
else begin // @[WidthWidget.scala:27:9]
if (auto_anon_out_a_ready & _repeated_repeater_io_deq_valid) // @[Decoupled.scala:51:35]
repeat_count <= ~repeat_last & repeat_count - 1'h1; // @[WidthWidget.scala:105:26, :107:35, :110:{15,24}, :111:{21,29}]
if (_anonIn_d_bits_data_T) begin // @[Decoupled.scala:51:35]
count <= ~last & count - 1'h1; // @[WidthWidget.scala:40:27, :42:36, :50:{15,24}, :52:21, :53:17]
corrupt_reg <= ~last & corrupt_out; // @[WidthWidget.scala:42:36, :45:32, :47:36, :50:15, :51:21, :52:21, :53:17, :54:23]
end
anonIn_d_bits_data_rdata_written_once <= _anonIn_d_bits_data_T_2 | anonIn_d_bits_data_rdata_written_once; // @[WidthWidget.scala:62:41, :69:{23,33}, :70:30]
end
if (_anonIn_d_bits_data_T_2 & anonIn_d_bits_data_masked_enable_0) // @[WidthWidget.scala:63:42, :66:24, :68:88, :69:{23,33}, :71:56]
anonIn_d_bits_data_rdata_0 <= auto_anon_out_d_bits_data; // @[WidthWidget.scala:66:24]
always @(posedge) |
Generate the Verilog code corresponding to the following Chisel files.
File LazyModuleImp.scala:
package org.chipsalliance.diplomacy.lazymodule
import chisel3.{withClockAndReset, Module, RawModule, Reset, _}
import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo}
import firrtl.passes.InlineAnnotation
import org.chipsalliance.cde.config.Parameters
import org.chipsalliance.diplomacy.nodes.Dangle
import scala.collection.immutable.SortedMap
/** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]].
*
* This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy.
*/
sealed trait LazyModuleImpLike extends RawModule {
/** [[LazyModule]] that contains this instance. */
val wrapper: LazyModule
/** IOs that will be automatically "punched" for this instance. */
val auto: AutoBundle
/** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */
protected[diplomacy] val dangles: Seq[Dangle]
// [[wrapper.module]] had better not be accessed while LazyModules are still being built!
require(
LazyModule.scope.isEmpty,
s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}"
)
/** Set module name. Defaults to the containing LazyModule's desiredName. */
override def desiredName: String = wrapper.desiredName
suggestName(wrapper.suggestedName)
/** [[Parameters]] for chisel [[Module]]s. */
implicit val p: Parameters = wrapper.p
/** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and
* submodules.
*/
protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = {
// 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]],
// 2. return [[Dangle]]s from each module.
val childDangles = wrapper.children.reverse.flatMap { c =>
implicit val sourceInfo: SourceInfo = c.info
c.cloneProto.map { cp =>
// If the child is a clone, then recursively set cloneProto of its children as well
def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = {
require(bases.size == clones.size)
(bases.zip(clones)).map { case (l, r) =>
require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}")
l.cloneProto = Some(r)
assignCloneProtos(l.children, r.children)
}
}
assignCloneProtos(c.children, cp.children)
// Clone the child module as a record, and get its [[AutoBundle]]
val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName)
val clonedAuto = clone("auto").asInstanceOf[AutoBundle]
// Get the empty [[Dangle]]'s of the cloned child
val rawDangles = c.cloneDangles()
require(rawDangles.size == clonedAuto.elements.size)
// Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s
val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) }
dangles
}.getOrElse {
// For non-clones, instantiate the child module
val mod = try {
Module(c.module)
} catch {
case e: ChiselException => {
println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}")
throw e
}
}
mod.dangles
}
}
// Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]].
// This will result in a sequence of [[Dangle]] from these [[BaseNode]]s.
val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate())
// Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]]
val allDangles = nodeDangles ++ childDangles
// Group [[allDangles]] by their [[source]].
val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*)
// For each [[source]] set of [[Dangle]]s of size 2, ensure that these
// can be connected as a source-sink pair (have opposite flipped value).
// Make the connection and mark them as [[done]].
val done = Set() ++ pairing.values.filter(_.size == 2).map {
case Seq(a, b) =>
require(a.flipped != b.flipped)
// @todo <> in chisel3 makes directionless connection.
if (a.flipped) {
a.data <> b.data
} else {
b.data <> a.data
}
a.source
case _ => None
}
// Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module.
val forward = allDangles.filter(d => !done(d.source))
// Generate [[AutoBundle]] IO from [[forward]].
val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*))
// Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]]
val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) =>
if (d.flipped) {
d.data <> io
} else {
io <> d.data
}
d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name)
}
// Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]].
wrapper.inModuleBody.reverse.foreach {
_()
}
if (wrapper.shouldBeInlined) {
chisel3.experimental.annotate(new ChiselAnnotation {
def toFirrtl = InlineAnnotation(toNamed)
})
}
// Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]].
(auto, dangles)
}
}
/** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike {
/** Instantiate hardware of this `Module`. */
val (auto, dangles) = instantiate()
}
/** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike {
// These wires are the default clock+reset for all LazyModule children.
// It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the
// [[LazyRawModuleImp]] children.
// Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly.
/** drive clock explicitly. */
val childClock: Clock = Wire(Clock())
/** drive reset explicitly. */
val childReset: Reset = Wire(Reset())
// the default is that these are disabled
childClock := false.B.asClock
childReset := chisel3.DontCare
def provideImplicitClockToLazyChildren: Boolean = false
val (auto, dangles) =
if (provideImplicitClockToLazyChildren) {
withClockAndReset(childClock, childReset) { instantiate() }
} else {
instantiate()
}
}
File MixedNode.scala:
package org.chipsalliance.diplomacy.nodes
import chisel3.{Data, DontCare, Wire}
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.{Field, Parameters}
import org.chipsalliance.diplomacy.ValName
import org.chipsalliance.diplomacy.sourceLine
/** One side metadata of a [[Dangle]].
*
* Describes one side of an edge going into or out of a [[BaseNode]].
*
* @param serial
* the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to.
* @param index
* the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to.
*/
case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] {
import scala.math.Ordered.orderingToOrdered
def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that))
}
/** [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]]
* connects.
*
* [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] ,
* [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]].
*
* @param source
* the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within
* that [[BaseNode]].
* @param sink
* sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that
* [[BaseNode]].
* @param flipped
* flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to
* `danglesIn`.
* @param dataOpt
* actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module
*/
case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) {
def data = dataOpt.get
}
/** [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often
* derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually
* implement the protocol.
*/
case class Edges[EI, EO](in: Seq[EI], out: Seq[EO])
/** A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. */
case object MonitorsEnabled extends Field[Boolean](true)
/** When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented.
*
* For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but
* [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink
* nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the
* [[LazyModule]].
*/
case object RenderFlipped extends Field[Boolean](false)
/** The sealed node class in the package, all node are derived from it.
*
* @param inner
* Sink interface implementation.
* @param outer
* Source interface implementation.
* @param valName
* val name of this node.
* @tparam DI
* Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters
* describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected
* [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port
* parameters.
* @tparam UI
* Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing
* the protocol parameters of a sink. For an [[InwardNode]], it is determined itself.
* @tparam EI
* Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers
* specified for a sink according to protocol.
* @tparam BI
* Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface.
* It should extends from [[chisel3.Data]], which represents the real hardware.
* @tparam DO
* Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters
* describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself.
* @tparam UO
* Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing
* the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]].
* Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters.
* @tparam EO
* Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers
* specified for a source according to protocol.
* @tparam BO
* Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source
* interface. It should extends from [[chisel3.Data]], which represents the real hardware.
*
* @note
* Call Graph of [[MixedNode]]
* - line `─`: source is process by a function and generate pass to others
* - Arrow `→`: target of arrow is generated by source
*
* {{{
* (from the other node)
* ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐
* ↓ │
* (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │
* [[InwardNode.accPI]] │ │ │
* │ │ (based on protocol) │
* │ │ [[MixedNode.inner.edgeI]] │
* │ │ ↓ │
* ↓ │ │ │
* (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │
* [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │
* │ │ ↑ │ │ │
* │ │ │ [[OutwardNode.doParams]] │ │
* │ │ │ (from the other node) │ │
* │ │ │ │ │ │
* │ │ │ │ │ │
* │ │ │ └────────┬──────────────┤ │
* │ │ │ │ │ │
* │ │ │ │ (based on protocol) │
* │ │ │ │ [[MixedNode.inner.edgeI]] │
* │ │ │ │ │ │
* │ │ (from the other node) │ ↓ │
* │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │
* │ ↑ ↑ │ │ ↓ │
* │ │ │ │ │ [[MixedNode.in]] │
* │ │ │ │ ↓ ↑ │
* │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │
* ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │
* │ │ │ [[MixedNode.bundleOut]]─┐ │ │
* │ │ │ ↑ ↓ │ │
* │ │ │ │ [[MixedNode.out]] │ │
* │ ↓ ↓ │ ↑ │ │
* │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │
* │ │ (from the other node) ↑ │ │
* │ │ │ │ │ │
* │ │ │ [[MixedNode.outer.edgeO]] │ │
* │ │ │ (based on protocol) │ │
* │ │ │ │ │ │
* │ │ │ ┌────────────────────────────────────────┤ │ │
* │ │ │ │ │ │ │
* │ │ │ │ │ │ │
* │ │ │ │ │ │ │
* (immobilize after elaboration)│ ↓ │ │ │ │
* [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │
* ↑ (inward port from [[OutwardNode]]) │ │ │ │
* │ ┌─────────────────────────────────────────┤ │ │ │
* │ │ │ │ │ │
* │ │ │ │ │ │
* [[OutwardNode.accPO]] │ ↓ │ │ │
* (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │
* │ ↑ │ │
* │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │
* └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘
* }}}
*/
abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data](
val inner: InwardNodeImp[DI, UI, EI, BI],
val outer: OutwardNodeImp[DO, UO, EO, BO]
)(
implicit valName: ValName)
extends BaseNode
with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO]
with InwardNode[DI, UI, BI]
with OutwardNode[DO, UO, BO] {
// Generate a [[NodeHandle]] with inward and outward node are both this node.
val inward = this
val outward = this
/** Debug info of nodes binding. */
def bindingInfo: String = s"""$iBindingInfo
|$oBindingInfo
|""".stripMargin
/** Debug info of ports connecting. */
def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}]
|${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}]
|""".stripMargin
/** Debug info of parameters propagations. */
def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}]
|${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}]
|${diParams.size} downstream inward parameters: [${diParams.mkString(",")}]
|${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}]
|""".stripMargin
/** For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and
* [[MixedNode.iPortMapping]].
*
* Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward
* stars and outward stars.
*
* This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type
* of node.
*
* @param iKnown
* Number of known-size ([[BIND_ONCE]]) input bindings.
* @param oKnown
* Number of known-size ([[BIND_ONCE]]) output bindings.
* @param iStar
* Number of unknown size ([[BIND_STAR]]) input bindings.
* @param oStar
* Number of unknown size ([[BIND_STAR]]) output bindings.
* @return
* A Tuple of the resolved number of input and output connections.
*/
protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int)
/** Function to generate downward-flowing outward params from the downward-flowing input params and the current output
* ports.
*
* @param n
* The size of the output sequence to generate.
* @param p
* Sequence of downward-flowing input parameters of this node.
* @return
* A `n`-sized sequence of downward-flowing output edge parameters.
*/
protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO]
/** Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]].
*
* @param n
* Size of the output sequence.
* @param p
* Upward-flowing output edge parameters.
* @return
* A n-sized sequence of upward-flowing input edge parameters.
*/
protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI]
/** @return
* The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with
* [[BIND_STAR]].
*/
protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR)
/** @return
* The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of
* output bindings bound with [[BIND_STAR]].
*/
protected[diplomacy] lazy val sourceCard: Int =
iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR)
/** @return list of nodes involved in flex bindings with this node. */
protected[diplomacy] lazy val flexes: Seq[BaseNode] =
oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2)
/** Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin
* greedily taking up the remaining connections.
*
* @return
* A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return
* value is not relevant.
*/
protected[diplomacy] lazy val flexOffset: Int = {
/** Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex
* operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a
* connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of
* each node in the current set and decide whether they should be added to the set or not.
*
* @return
* the mapping of [[BaseNode]] indexed by their serial numbers.
*/
def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = {
if (visited.contains(v.serial) || !v.flexibleArityDirection) {
visited
} else {
v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum))
}
}
/** Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node.
*
* @example
* {{{
* a :*=* b :*=* c
* d :*=* b
* e :*=* f
* }}}
*
* `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)`
*/
val flexSet = DFS(this, Map()).values
/** The total number of :*= operators where we're on the left. */
val allSink = flexSet.map(_.sinkCard).sum
/** The total number of :=* operators used when we're on the right. */
val allSource = flexSet.map(_.sourceCard).sum
require(
allSink == 0 || allSource == 0,
s"The nodes ${flexSet.map(_.name)} which are inter-connected by :*=* have ${allSink} :*= operators and ${allSource} :=* operators connected to them, making it impossible to determine cardinality inference direction."
)
allSink - allSource
}
/** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. */
protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = {
if (flexibleArityDirection) flexOffset
else if (n.flexibleArityDirection) n.flexOffset
else 0
}
/** For a node which is connected between two nodes, select the one that will influence the direction of the flex
* resolution.
*/
protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = {
val dir = edgeArityDirection(n)
if (dir < 0) l
else if (dir > 0) r
else 1
}
/** Ensure that the same node is not visited twice in resolving `:*=`, etc operators. */
private var starCycleGuard = false
/** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star"
* connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also
* need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct
* edge parameters and later build up correct bundle connections.
*
* [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding
* operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort
* (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N :*= foo` or `N :*=* foo :*=
* bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo :*=* N`
*/
protected[diplomacy] lazy val (
oPortMapping: Seq[(Int, Int)],
iPortMapping: Seq[(Int, Int)],
oStar: Int,
iStar: Int
) = {
try {
if (starCycleGuard) throw StarCycleException()
starCycleGuard = true
// For a given node N...
// Number of foo :=* N
// + Number of bar :=* foo :*=* N
val oStars = oBindings.count { case (_, n, b, _, _) =>
b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) < 0)
}
// Number of N :*= foo
// + Number of N :*=* foo :*= bar
val iStars = iBindings.count { case (_, n, b, _, _) =>
b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) > 0)
}
// 1 for foo := N
// + bar.iStar for bar :*= foo :*=* N
// + foo.iStar for foo :*= N
// + 0 for foo :=* N
val oKnown = oBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, 0, n.iStar)
case BIND_QUERY => n.iStar
case BIND_STAR => 0
}
}.sum
// 1 for N := foo
// + bar.oStar for N :*=* foo :=* bar
// + foo.oStar for N :=* foo
// + 0 for N :*= foo
val iKnown = iBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, n.oStar, 0)
case BIND_QUERY => n.oStar
case BIND_STAR => 0
}
}.sum
// Resolve star depends on the node subclass to implement the algorithm for this.
val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars)
// Cumulative list of resolved outward binding range starting points
val oSum = oBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar)
case BIND_QUERY => n.iStar
case BIND_STAR => oStar
}
}.scanLeft(0)(_ + _)
// Cumulative list of resolved inward binding range starting points
val iSum = iBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar)
case BIND_QUERY => n.oStar
case BIND_STAR => iStar
}
}.scanLeft(0)(_ + _)
// Create ranges for each binding based on the running sums and return
// those along with resolved values for the star operations.
(oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar)
} catch {
case c: StarCycleException => throw c.copy(loop = context +: c.loop)
}
}
/** Sequence of inward ports.
*
* This should be called after all star bindings are resolved.
*
* Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding.
* `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this
* connection was made in the source code.
*/
protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] =
oBindings.flatMap { case (i, n, _, p, s) =>
// for each binding operator in this node, look at what it connects to
val (start, end) = n.iPortMapping(i)
(start until end).map { j => (j, n, p, s) }
}
/** Sequence of outward ports.
*
* This should be called after all star bindings are resolved.
*
* `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of
* outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection
* was made in the source code.
*/
protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] =
iBindings.flatMap { case (i, n, _, p, s) =>
// query this port index range of this node in the other side of node.
val (start, end) = n.oPortMapping(i)
(start until end).map { j => (j, n, p, s) }
}
// Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree
// Thus, there must exist an Eulerian path and the below algorithms terminate
@scala.annotation.tailrec
private def oTrace(
tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)
): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match {
case (i, n, p, s) => n.iForward(i) match {
case None => (i, n, p, s)
case Some((j, m)) => oTrace((j, m, p, s))
}
}
@scala.annotation.tailrec
private def iTrace(
tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)
): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match {
case (i, n, p, s) => n.oForward(i) match {
case None => (i, n, p, s)
case Some((j, m)) => iTrace((j, m, p, s))
}
}
/** Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved.
*
* Each Port is a tuple of:
* - Numeric index of this binding in the [[InwardNode]] on the other end.
* - [[InwardNode]] on the other end of this binding.
* - A view of [[Parameters]] where the binding occurred.
* - [[SourceInfo]] for source-level error reporting.
*/
lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace)
/** Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved.
*
* Each Port is a tuple of:
* - numeric index of this binding in [[OutwardNode]] on the other end.
* - [[OutwardNode]] on the other end of this binding.
* - a view of [[Parameters]] where the binding occurred.
* - [[SourceInfo]] for source-level error reporting.
*/
lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace)
private var oParamsCycleGuard = false
protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) }
protected[diplomacy] lazy val doParams: Seq[DO] = {
try {
if (oParamsCycleGuard) throw DownwardCycleException()
oParamsCycleGuard = true
val o = mapParamsD(oPorts.size, diParams)
require(
o.size == oPorts.size,
s"""Diplomacy has detected a problem with your graph:
|At the following node, the number of outward ports should equal the number of produced outward parameters.
|$context
|$connectedPortsInfo
|Downstreamed inward parameters: [${diParams.mkString(",")}]
|Produced outward parameters: [${o.mkString(",")}]
|""".stripMargin
)
o.map(outer.mixO(_, this))
} catch {
case c: DownwardCycleException => throw c.copy(loop = context +: c.loop)
}
}
private var iParamsCycleGuard = false
protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) }
protected[diplomacy] lazy val uiParams: Seq[UI] = {
try {
if (iParamsCycleGuard) throw UpwardCycleException()
iParamsCycleGuard = true
val i = mapParamsU(iPorts.size, uoParams)
require(
i.size == iPorts.size,
s"""Diplomacy has detected a problem with your graph:
|At the following node, the number of inward ports should equal the number of produced inward parameters.
|$context
|$connectedPortsInfo
|Upstreamed outward parameters: [${uoParams.mkString(",")}]
|Produced inward parameters: [${i.mkString(",")}]
|""".stripMargin
)
i.map(inner.mixI(_, this))
} catch {
case c: UpwardCycleException => throw c.copy(loop = context +: c.loop)
}
}
/** Outward edge parameters. */
protected[diplomacy] lazy val edgesOut: Seq[EO] =
(oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) }
/** Inward edge parameters. */
protected[diplomacy] lazy val edgesIn: Seq[EI] =
(iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) }
/** A tuple of the input edge parameters and output edge parameters for the edges bound to this node.
*
* If you need to access to the edges of a foreign Node, use this method (in/out create bundles).
*/
lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut)
/** Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. */
protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e =>
val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out")
// TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue,
// In the future, we should add an option to decide whether allowing unconnected in the LazyModule
x := DontCare
x
}
/** Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. */
protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e =>
val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In")
// TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue,
// In the future, we should add an option to decide whether allowing unconnected in the LazyModule
x := DontCare
x
}
private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) =>
Dangle(
source = HalfEdge(serial, i),
sink = HalfEdge(n.serial, j),
flipped = false,
name = wirePrefix + "out",
dataOpt = None
)
}
private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) =>
Dangle(
source = HalfEdge(n.serial, j),
sink = HalfEdge(serial, i),
flipped = true,
name = wirePrefix + "in",
dataOpt = None
)
}
/** Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. */
protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) =>
d.copy(dataOpt = Some(bundleOut(i)))
}
/** Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. */
protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) =>
d.copy(dataOpt = Some(bundleIn(i)))
}
private[diplomacy] var instantiated = false
/** Gather Bundle and edge parameters of outward ports.
*
* Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within
* [[LazyModuleImp]] code or after its instantiation has completed.
*/
def out: Seq[(BO, EO)] = {
require(
instantiated,
s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun"
)
bundleOut.zip(edgesOut)
}
/** Gather Bundle and edge parameters of inward ports.
*
* Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within
* [[LazyModuleImp]] code or after its instantiation has completed.
*/
def in: Seq[(BI, EI)] = {
require(
instantiated,
s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun"
)
bundleIn.zip(edgesIn)
}
/** Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires,
* instantiate monitors on all input ports if appropriate, and return all the dangles of this node.
*/
protected[diplomacy] def instantiate(): Seq[Dangle] = {
instantiated = true
if (!circuitIdentity) {
(iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) }
}
danglesOut ++ danglesIn
}
protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn
/** Connects the outward part of a node with the inward part of this node. */
protected[diplomacy] def bind(
h: OutwardNode[DI, UI, BI],
binding: NodeBinding
)(
implicit p: Parameters,
sourceInfo: SourceInfo
): Unit = {
val x = this // x := y
val y = h
sourceLine(sourceInfo, " at ", "")
val i = x.iPushed
val o = y.oPushed
y.oPush(
i,
x,
binding match {
case BIND_ONCE => BIND_ONCE
case BIND_FLEX => BIND_FLEX
case BIND_STAR => BIND_QUERY
case BIND_QUERY => BIND_STAR
}
)
x.iPush(o, y, binding)
}
/* Metadata for printing the node graph. */
def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) =>
val re = inner.render(e)
(n, re.copy(flipped = re.flipped != p(RenderFlipped)))
}
/** Metadata for printing the node graph */
def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) }
}
File UserYanker.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.amba.axi4
import chisel3._
import chisel3.util.{Queue, QueueIO, UIntToOH}
import org.chipsalliance.cde.config.Parameters
import org.chipsalliance.diplomacy.lazymodule.{LazyModule, LazyModuleImp}
import freechips.rocketchip.util.BundleMap
/** This adapter prunes all user bit fields of the echo type from request messages,
* storing them in queues and echoing them back when matching response messages are received.
*
* It also optionally rate limits the number of transactions that can be in flight simultaneously
* per FIFO domain / A[W|R]ID.
*
* @param capMaxFlight is an optional maximum number of transactions that can be in flight per A[W|R]ID.
*/
class AXI4UserYanker(capMaxFlight: Option[Int] = None)(implicit p: Parameters) extends LazyModule
{
val node = AXI4AdapterNode(
masterFn = { mp => mp.copy(
masters = mp.masters.map { m => m.copy(
maxFlight = (m.maxFlight, capMaxFlight) match {
case (Some(x), Some(y)) => Some(x min y)
case (Some(x), None) => Some(x)
case (None, Some(y)) => Some(y)
case (None, None) => None })},
echoFields = Nil)},
slaveFn = { sp => sp })
lazy val module = new Impl
class Impl extends LazyModuleImp(this) {
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
// Which fields are we stripping?
val echoFields = edgeIn.master.echoFields
val need_bypass = edgeOut.slave.minLatency < 1
edgeOut.master.masters.foreach { m =>
require (m.maxFlight.isDefined, "UserYanker needs a flight cap on each ID")
}
def queue(id: Int) = {
val depth = edgeOut.master.masters.find(_.id.contains(id)).flatMap(_.maxFlight).getOrElse(0)
if (depth == 0) {
Wire(new QueueIO(BundleMap(echoFields), 1)) // unused ID => undefined value
} else {
Module(new Queue(BundleMap(echoFields), depth, flow=need_bypass)).io
}
}
val rqueues = Seq.tabulate(edgeIn.master.endId) { i => queue(i) }
val wqueues = Seq.tabulate(edgeIn.master.endId) { i => queue(i) }
val arid = in.ar.bits.id
val ar_ready = VecInit(rqueues.map(_.enq.ready))(arid)
in .ar.ready := out.ar.ready && ar_ready
out.ar.valid := in .ar.valid && ar_ready
Connectable.waiveUnmatched(out.ar.bits, in.ar.bits) match {
case (lhs, rhs) => lhs :<= rhs
}
val rid = out.r.bits.id
val r_valid = VecInit(rqueues.map(_.deq.valid))(rid)
val r_bits = VecInit(rqueues.map(_.deq.bits))(rid)
assert (!out.r.valid || r_valid) // Q must be ready faster than the response
Connectable.waiveUnmatched(in.r, out.r) match {
case (lhs, rhs) => lhs :<>= rhs
}
in.r.bits.echo :<= r_bits
val arsel = UIntToOH(arid, edgeIn.master.endId).asBools
val rsel = UIntToOH(rid, edgeIn.master.endId).asBools
(rqueues zip (arsel zip rsel)) foreach { case (q, (ar, r)) =>
q.deq.ready := out.r .valid && in .r .ready && r && out.r.bits.last
q.deq.valid := DontCare
q.deq.bits := DontCare
q.enq.valid := in .ar.valid && out.ar.ready && ar
q.enq.ready := DontCare
q.enq.bits :<>= in.ar.bits.echo
q.count := DontCare
}
val awid = in.aw.bits.id
val aw_ready = VecInit(wqueues.map(_.enq.ready))(awid)
in .aw.ready := out.aw.ready && aw_ready
out.aw.valid := in .aw.valid && aw_ready
Connectable.waiveUnmatched(out.aw.bits, in.aw.bits) match {
case (lhs, rhs) => lhs :<>= rhs
}
val bid = out.b.bits.id
val b_valid = VecInit(wqueues.map(_.deq.valid))(bid)
val b_bits = VecInit(wqueues.map(_.deq.bits))(bid)
assert (!out.b.valid || b_valid) // Q must be ready faster than the response
Connectable.waiveUnmatched(in.b, out.b) match {
case (lhs, rhs) => lhs :<>= rhs
}
in.b.bits.echo :<>= b_bits
val awsel = UIntToOH(awid, edgeIn.master.endId).asBools
val bsel = UIntToOH(bid, edgeIn.master.endId).asBools
(wqueues zip (awsel zip bsel)) foreach { case (q, (aw, b)) =>
q.deq.ready := out.b .valid && in .b .ready && b
q.deq.valid := DontCare
q.deq.bits := DontCare
q.enq.valid := in .aw.valid && out.aw.ready && aw
q.enq.ready := DontCare
q.enq.bits :<>= in.aw.bits.echo
q.count := DontCare
}
out.w :<>= in.w
}
}
}
object AXI4UserYanker
{
def apply(capMaxFlight: Option[Int] = None)(implicit p: Parameters): AXI4Node =
{
val axi4yank = LazyModule(new AXI4UserYanker(capMaxFlight))
axi4yank.node
}
}
| module AXI4UserYanker( // @[UserYanker.scala:36:9]
input clock, // @[UserYanker.scala:36:9]
input reset, // @[UserYanker.scala:36:9]
output auto_in_aw_ready, // @[LazyModuleImp.scala:107:25]
input auto_in_aw_valid, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_in_aw_bits_id, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_in_aw_bits_addr, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_in_aw_bits_len, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_aw_bits_size, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_in_aw_bits_burst, // @[LazyModuleImp.scala:107:25]
input auto_in_aw_bits_lock, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_in_aw_bits_cache, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_aw_bits_prot, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_in_aw_bits_qos, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_in_aw_bits_echo_tl_state_size, // @[LazyModuleImp.scala:107:25]
input [5:0] auto_in_aw_bits_echo_tl_state_source, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_in_aw_bits_echo_extra_id, // @[LazyModuleImp.scala:107:25]
output auto_in_w_ready, // @[LazyModuleImp.scala:107:25]
input auto_in_w_valid, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_in_w_bits_data, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_in_w_bits_strb, // @[LazyModuleImp.scala:107:25]
input auto_in_w_bits_last, // @[LazyModuleImp.scala:107:25]
input auto_in_b_ready, // @[LazyModuleImp.scala:107:25]
output auto_in_b_valid, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_in_b_bits_id, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_in_b_bits_resp, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_in_b_bits_echo_tl_state_size, // @[LazyModuleImp.scala:107:25]
output [5:0] auto_in_b_bits_echo_tl_state_source, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_in_b_bits_echo_extra_id, // @[LazyModuleImp.scala:107:25]
output auto_in_ar_ready, // @[LazyModuleImp.scala:107:25]
input auto_in_ar_valid, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_in_ar_bits_id, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_in_ar_bits_addr, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_in_ar_bits_len, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_ar_bits_size, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_in_ar_bits_burst, // @[LazyModuleImp.scala:107:25]
input auto_in_ar_bits_lock, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_in_ar_bits_cache, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_ar_bits_prot, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_in_ar_bits_qos, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_in_ar_bits_echo_tl_state_size, // @[LazyModuleImp.scala:107:25]
input [5:0] auto_in_ar_bits_echo_tl_state_source, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_in_ar_bits_echo_extra_id, // @[LazyModuleImp.scala:107:25]
input auto_in_r_ready, // @[LazyModuleImp.scala:107:25]
output auto_in_r_valid, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_in_r_bits_id, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_in_r_bits_data, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_in_r_bits_resp, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_in_r_bits_echo_tl_state_size, // @[LazyModuleImp.scala:107:25]
output [5:0] auto_in_r_bits_echo_tl_state_source, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_in_r_bits_echo_extra_id, // @[LazyModuleImp.scala:107:25]
output auto_in_r_bits_last, // @[LazyModuleImp.scala:107:25]
input auto_out_aw_ready, // @[LazyModuleImp.scala:107:25]
output auto_out_aw_valid, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_out_aw_bits_id, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_out_aw_bits_addr, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_out_aw_bits_len, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_aw_bits_size, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_out_aw_bits_burst, // @[LazyModuleImp.scala:107:25]
output auto_out_aw_bits_lock, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_out_aw_bits_cache, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_aw_bits_prot, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_out_aw_bits_qos, // @[LazyModuleImp.scala:107:25]
input auto_out_w_ready, // @[LazyModuleImp.scala:107:25]
output auto_out_w_valid, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_out_w_bits_data, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_out_w_bits_strb, // @[LazyModuleImp.scala:107:25]
output auto_out_w_bits_last, // @[LazyModuleImp.scala:107:25]
output auto_out_b_ready, // @[LazyModuleImp.scala:107:25]
input auto_out_b_valid, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_out_b_bits_id, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_out_b_bits_resp, // @[LazyModuleImp.scala:107:25]
input auto_out_ar_ready, // @[LazyModuleImp.scala:107:25]
output auto_out_ar_valid, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_out_ar_bits_id, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_out_ar_bits_addr, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_out_ar_bits_len, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_ar_bits_size, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_out_ar_bits_burst, // @[LazyModuleImp.scala:107:25]
output auto_out_ar_bits_lock, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_out_ar_bits_cache, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_ar_bits_prot, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_out_ar_bits_qos, // @[LazyModuleImp.scala:107:25]
output auto_out_r_ready, // @[LazyModuleImp.scala:107:25]
input auto_out_r_valid, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_out_r_bits_id, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_out_r_bits_data, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_out_r_bits_resp, // @[LazyModuleImp.scala:107:25]
input auto_out_r_bits_last // @[LazyModuleImp.scala:107:25]
);
wire auto_in_aw_valid_0 = auto_in_aw_valid; // @[UserYanker.scala:36:9]
wire [3:0] auto_in_aw_bits_id_0 = auto_in_aw_bits_id; // @[UserYanker.scala:36:9]
wire [31:0] auto_in_aw_bits_addr_0 = auto_in_aw_bits_addr; // @[UserYanker.scala:36:9]
wire [7:0] auto_in_aw_bits_len_0 = auto_in_aw_bits_len; // @[UserYanker.scala:36:9]
wire [2:0] auto_in_aw_bits_size_0 = auto_in_aw_bits_size; // @[UserYanker.scala:36:9]
wire [1:0] auto_in_aw_bits_burst_0 = auto_in_aw_bits_burst; // @[UserYanker.scala:36:9]
wire auto_in_aw_bits_lock_0 = auto_in_aw_bits_lock; // @[UserYanker.scala:36:9]
wire [3:0] auto_in_aw_bits_cache_0 = auto_in_aw_bits_cache; // @[UserYanker.scala:36:9]
wire [2:0] auto_in_aw_bits_prot_0 = auto_in_aw_bits_prot; // @[UserYanker.scala:36:9]
wire [3:0] auto_in_aw_bits_qos_0 = auto_in_aw_bits_qos; // @[UserYanker.scala:36:9]
wire [3:0] auto_in_aw_bits_echo_tl_state_size_0 = auto_in_aw_bits_echo_tl_state_size; // @[UserYanker.scala:36:9]
wire [5:0] auto_in_aw_bits_echo_tl_state_source_0 = auto_in_aw_bits_echo_tl_state_source; // @[UserYanker.scala:36:9]
wire [1:0] auto_in_aw_bits_echo_extra_id_0 = auto_in_aw_bits_echo_extra_id; // @[UserYanker.scala:36:9]
wire auto_in_w_valid_0 = auto_in_w_valid; // @[UserYanker.scala:36:9]
wire [63:0] auto_in_w_bits_data_0 = auto_in_w_bits_data; // @[UserYanker.scala:36:9]
wire [7:0] auto_in_w_bits_strb_0 = auto_in_w_bits_strb; // @[UserYanker.scala:36:9]
wire auto_in_w_bits_last_0 = auto_in_w_bits_last; // @[UserYanker.scala:36:9]
wire auto_in_b_ready_0 = auto_in_b_ready; // @[UserYanker.scala:36:9]
wire auto_in_ar_valid_0 = auto_in_ar_valid; // @[UserYanker.scala:36:9]
wire [3:0] auto_in_ar_bits_id_0 = auto_in_ar_bits_id; // @[UserYanker.scala:36:9]
wire [31:0] auto_in_ar_bits_addr_0 = auto_in_ar_bits_addr; // @[UserYanker.scala:36:9]
wire [7:0] auto_in_ar_bits_len_0 = auto_in_ar_bits_len; // @[UserYanker.scala:36:9]
wire [2:0] auto_in_ar_bits_size_0 = auto_in_ar_bits_size; // @[UserYanker.scala:36:9]
wire [1:0] auto_in_ar_bits_burst_0 = auto_in_ar_bits_burst; // @[UserYanker.scala:36:9]
wire auto_in_ar_bits_lock_0 = auto_in_ar_bits_lock; // @[UserYanker.scala:36:9]
wire [3:0] auto_in_ar_bits_cache_0 = auto_in_ar_bits_cache; // @[UserYanker.scala:36:9]
wire [2:0] auto_in_ar_bits_prot_0 = auto_in_ar_bits_prot; // @[UserYanker.scala:36:9]
wire [3:0] auto_in_ar_bits_qos_0 = auto_in_ar_bits_qos; // @[UserYanker.scala:36:9]
wire [3:0] auto_in_ar_bits_echo_tl_state_size_0 = auto_in_ar_bits_echo_tl_state_size; // @[UserYanker.scala:36:9]
wire [5:0] auto_in_ar_bits_echo_tl_state_source_0 = auto_in_ar_bits_echo_tl_state_source; // @[UserYanker.scala:36:9]
wire [1:0] auto_in_ar_bits_echo_extra_id_0 = auto_in_ar_bits_echo_extra_id; // @[UserYanker.scala:36:9]
wire auto_in_r_ready_0 = auto_in_r_ready; // @[UserYanker.scala:36:9]
wire auto_out_aw_ready_0 = auto_out_aw_ready; // @[UserYanker.scala:36:9]
wire auto_out_w_ready_0 = auto_out_w_ready; // @[UserYanker.scala:36:9]
wire auto_out_b_valid_0 = auto_out_b_valid; // @[UserYanker.scala:36:9]
wire [3:0] auto_out_b_bits_id_0 = auto_out_b_bits_id; // @[UserYanker.scala:36:9]
wire [1:0] auto_out_b_bits_resp_0 = auto_out_b_bits_resp; // @[UserYanker.scala:36:9]
wire auto_out_ar_ready_0 = auto_out_ar_ready; // @[UserYanker.scala:36:9]
wire auto_out_r_valid_0 = auto_out_r_valid; // @[UserYanker.scala:36:9]
wire [3:0] auto_out_r_bits_id_0 = auto_out_r_bits_id; // @[UserYanker.scala:36:9]
wire [63:0] auto_out_r_bits_data_0 = auto_out_r_bits_data; // @[UserYanker.scala:36:9]
wire [1:0] auto_out_r_bits_resp_0 = auto_out_r_bits_resp; // @[UserYanker.scala:36:9]
wire auto_out_r_bits_last_0 = auto_out_r_bits_last; // @[UserYanker.scala:36:9]
wire nodeIn_aw_ready; // @[MixedNode.scala:551:17]
wire nodeIn_aw_valid = auto_in_aw_valid_0; // @[UserYanker.scala:36:9]
wire [3:0] nodeIn_aw_bits_id = auto_in_aw_bits_id_0; // @[UserYanker.scala:36:9]
wire [31:0] nodeIn_aw_bits_addr = auto_in_aw_bits_addr_0; // @[UserYanker.scala:36:9]
wire [7:0] nodeIn_aw_bits_len = auto_in_aw_bits_len_0; // @[UserYanker.scala:36:9]
wire [2:0] nodeIn_aw_bits_size = auto_in_aw_bits_size_0; // @[UserYanker.scala:36:9]
wire [1:0] nodeIn_aw_bits_burst = auto_in_aw_bits_burst_0; // @[UserYanker.scala:36:9]
wire nodeIn_aw_bits_lock = auto_in_aw_bits_lock_0; // @[UserYanker.scala:36:9]
wire [3:0] nodeIn_aw_bits_cache = auto_in_aw_bits_cache_0; // @[UserYanker.scala:36:9]
wire [2:0] nodeIn_aw_bits_prot = auto_in_aw_bits_prot_0; // @[UserYanker.scala:36:9]
wire [3:0] nodeIn_aw_bits_qos = auto_in_aw_bits_qos_0; // @[UserYanker.scala:36:9]
wire [3:0] nodeIn_aw_bits_echo_tl_state_size = auto_in_aw_bits_echo_tl_state_size_0; // @[UserYanker.scala:36:9]
wire [5:0] nodeIn_aw_bits_echo_tl_state_source = auto_in_aw_bits_echo_tl_state_source_0; // @[UserYanker.scala:36:9]
wire [1:0] nodeIn_aw_bits_echo_extra_id = auto_in_aw_bits_echo_extra_id_0; // @[UserYanker.scala:36:9]
wire nodeIn_w_ready; // @[MixedNode.scala:551:17]
wire nodeIn_w_valid = auto_in_w_valid_0; // @[UserYanker.scala:36:9]
wire [63:0] nodeIn_w_bits_data = auto_in_w_bits_data_0; // @[UserYanker.scala:36:9]
wire [7:0] nodeIn_w_bits_strb = auto_in_w_bits_strb_0; // @[UserYanker.scala:36:9]
wire nodeIn_w_bits_last = auto_in_w_bits_last_0; // @[UserYanker.scala:36:9]
wire nodeIn_b_ready = auto_in_b_ready_0; // @[UserYanker.scala:36:9]
wire nodeIn_b_valid; // @[MixedNode.scala:551:17]
wire [3:0] nodeIn_b_bits_id; // @[MixedNode.scala:551:17]
wire [1:0] nodeIn_b_bits_resp; // @[MixedNode.scala:551:17]
wire [3:0] nodeIn_b_bits_echo_tl_state_size; // @[MixedNode.scala:551:17]
wire [5:0] nodeIn_b_bits_echo_tl_state_source; // @[MixedNode.scala:551:17]
wire [1:0] nodeIn_b_bits_echo_extra_id; // @[MixedNode.scala:551:17]
wire nodeIn_ar_ready; // @[MixedNode.scala:551:17]
wire nodeIn_ar_valid = auto_in_ar_valid_0; // @[UserYanker.scala:36:9]
wire [3:0] nodeIn_ar_bits_id = auto_in_ar_bits_id_0; // @[UserYanker.scala:36:9]
wire [31:0] nodeIn_ar_bits_addr = auto_in_ar_bits_addr_0; // @[UserYanker.scala:36:9]
wire [7:0] nodeIn_ar_bits_len = auto_in_ar_bits_len_0; // @[UserYanker.scala:36:9]
wire [2:0] nodeIn_ar_bits_size = auto_in_ar_bits_size_0; // @[UserYanker.scala:36:9]
wire [1:0] nodeIn_ar_bits_burst = auto_in_ar_bits_burst_0; // @[UserYanker.scala:36:9]
wire nodeIn_ar_bits_lock = auto_in_ar_bits_lock_0; // @[UserYanker.scala:36:9]
wire [3:0] nodeIn_ar_bits_cache = auto_in_ar_bits_cache_0; // @[UserYanker.scala:36:9]
wire [2:0] nodeIn_ar_bits_prot = auto_in_ar_bits_prot_0; // @[UserYanker.scala:36:9]
wire [3:0] nodeIn_ar_bits_qos = auto_in_ar_bits_qos_0; // @[UserYanker.scala:36:9]
wire [3:0] nodeIn_ar_bits_echo_tl_state_size = auto_in_ar_bits_echo_tl_state_size_0; // @[UserYanker.scala:36:9]
wire [5:0] nodeIn_ar_bits_echo_tl_state_source = auto_in_ar_bits_echo_tl_state_source_0; // @[UserYanker.scala:36:9]
wire [1:0] nodeIn_ar_bits_echo_extra_id = auto_in_ar_bits_echo_extra_id_0; // @[UserYanker.scala:36:9]
wire nodeIn_r_ready = auto_in_r_ready_0; // @[UserYanker.scala:36:9]
wire nodeIn_r_valid; // @[MixedNode.scala:551:17]
wire [3:0] nodeIn_r_bits_id; // @[MixedNode.scala:551:17]
wire [63:0] nodeIn_r_bits_data; // @[MixedNode.scala:551:17]
wire [1:0] nodeIn_r_bits_resp; // @[MixedNode.scala:551:17]
wire [3:0] nodeIn_r_bits_echo_tl_state_size; // @[MixedNode.scala:551:17]
wire [5:0] nodeIn_r_bits_echo_tl_state_source; // @[MixedNode.scala:551:17]
wire [1:0] nodeIn_r_bits_echo_extra_id; // @[MixedNode.scala:551:17]
wire nodeIn_r_bits_last; // @[MixedNode.scala:551:17]
wire nodeOut_aw_ready = auto_out_aw_ready_0; // @[UserYanker.scala:36:9]
wire nodeOut_aw_valid; // @[MixedNode.scala:542:17]
wire [3:0] nodeOut_aw_bits_id; // @[MixedNode.scala:542:17]
wire [31:0] nodeOut_aw_bits_addr; // @[MixedNode.scala:542:17]
wire [7:0] nodeOut_aw_bits_len; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_aw_bits_size; // @[MixedNode.scala:542:17]
wire [1:0] nodeOut_aw_bits_burst; // @[MixedNode.scala:542:17]
wire nodeOut_aw_bits_lock; // @[MixedNode.scala:542:17]
wire [3:0] nodeOut_aw_bits_cache; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_aw_bits_prot; // @[MixedNode.scala:542:17]
wire [3:0] nodeOut_aw_bits_qos; // @[MixedNode.scala:542:17]
wire nodeOut_w_ready = auto_out_w_ready_0; // @[UserYanker.scala:36:9]
wire nodeOut_w_valid; // @[MixedNode.scala:542:17]
wire [63:0] nodeOut_w_bits_data; // @[MixedNode.scala:542:17]
wire [7:0] nodeOut_w_bits_strb; // @[MixedNode.scala:542:17]
wire nodeOut_w_bits_last; // @[MixedNode.scala:542:17]
wire nodeOut_b_ready; // @[MixedNode.scala:542:17]
wire nodeOut_b_valid = auto_out_b_valid_0; // @[UserYanker.scala:36:9]
wire [3:0] nodeOut_b_bits_id = auto_out_b_bits_id_0; // @[UserYanker.scala:36:9]
wire [1:0] nodeOut_b_bits_resp = auto_out_b_bits_resp_0; // @[UserYanker.scala:36:9]
wire nodeOut_ar_ready = auto_out_ar_ready_0; // @[UserYanker.scala:36:9]
wire nodeOut_ar_valid; // @[MixedNode.scala:542:17]
wire [3:0] nodeOut_ar_bits_id; // @[MixedNode.scala:542:17]
wire [31:0] nodeOut_ar_bits_addr; // @[MixedNode.scala:542:17]
wire [7:0] nodeOut_ar_bits_len; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_ar_bits_size; // @[MixedNode.scala:542:17]
wire [1:0] nodeOut_ar_bits_burst; // @[MixedNode.scala:542:17]
wire nodeOut_ar_bits_lock; // @[MixedNode.scala:542:17]
wire [3:0] nodeOut_ar_bits_cache; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_ar_bits_prot; // @[MixedNode.scala:542:17]
wire [3:0] nodeOut_ar_bits_qos; // @[MixedNode.scala:542:17]
wire nodeOut_r_ready; // @[MixedNode.scala:542:17]
wire nodeOut_r_valid = auto_out_r_valid_0; // @[UserYanker.scala:36:9]
wire [3:0] nodeOut_r_bits_id = auto_out_r_bits_id_0; // @[UserYanker.scala:36:9]
wire [63:0] nodeOut_r_bits_data = auto_out_r_bits_data_0; // @[UserYanker.scala:36:9]
wire [1:0] nodeOut_r_bits_resp = auto_out_r_bits_resp_0; // @[UserYanker.scala:36:9]
wire nodeOut_r_bits_last = auto_out_r_bits_last_0; // @[UserYanker.scala:36:9]
wire auto_in_aw_ready_0; // @[UserYanker.scala:36:9]
wire auto_in_w_ready_0; // @[UserYanker.scala:36:9]
wire [3:0] auto_in_b_bits_echo_tl_state_size_0; // @[UserYanker.scala:36:9]
wire [5:0] auto_in_b_bits_echo_tl_state_source_0; // @[UserYanker.scala:36:9]
wire [1:0] auto_in_b_bits_echo_extra_id_0; // @[UserYanker.scala:36:9]
wire [3:0] auto_in_b_bits_id_0; // @[UserYanker.scala:36:9]
wire [1:0] auto_in_b_bits_resp_0; // @[UserYanker.scala:36:9]
wire auto_in_b_valid_0; // @[UserYanker.scala:36:9]
wire auto_in_ar_ready_0; // @[UserYanker.scala:36:9]
wire [3:0] auto_in_r_bits_echo_tl_state_size_0; // @[UserYanker.scala:36:9]
wire [5:0] auto_in_r_bits_echo_tl_state_source_0; // @[UserYanker.scala:36:9]
wire [1:0] auto_in_r_bits_echo_extra_id_0; // @[UserYanker.scala:36:9]
wire [3:0] auto_in_r_bits_id_0; // @[UserYanker.scala:36:9]
wire [63:0] auto_in_r_bits_data_0; // @[UserYanker.scala:36:9]
wire [1:0] auto_in_r_bits_resp_0; // @[UserYanker.scala:36:9]
wire auto_in_r_bits_last_0; // @[UserYanker.scala:36:9]
wire auto_in_r_valid_0; // @[UserYanker.scala:36:9]
wire [3:0] auto_out_aw_bits_id_0; // @[UserYanker.scala:36:9]
wire [31:0] auto_out_aw_bits_addr_0; // @[UserYanker.scala:36:9]
wire [7:0] auto_out_aw_bits_len_0; // @[UserYanker.scala:36:9]
wire [2:0] auto_out_aw_bits_size_0; // @[UserYanker.scala:36:9]
wire [1:0] auto_out_aw_bits_burst_0; // @[UserYanker.scala:36:9]
wire auto_out_aw_bits_lock_0; // @[UserYanker.scala:36:9]
wire [3:0] auto_out_aw_bits_cache_0; // @[UserYanker.scala:36:9]
wire [2:0] auto_out_aw_bits_prot_0; // @[UserYanker.scala:36:9]
wire [3:0] auto_out_aw_bits_qos_0; // @[UserYanker.scala:36:9]
wire auto_out_aw_valid_0; // @[UserYanker.scala:36:9]
wire [63:0] auto_out_w_bits_data_0; // @[UserYanker.scala:36:9]
wire [7:0] auto_out_w_bits_strb_0; // @[UserYanker.scala:36:9]
wire auto_out_w_bits_last_0; // @[UserYanker.scala:36:9]
wire auto_out_w_valid_0; // @[UserYanker.scala:36:9]
wire auto_out_b_ready_0; // @[UserYanker.scala:36:9]
wire [3:0] auto_out_ar_bits_id_0; // @[UserYanker.scala:36:9]
wire [31:0] auto_out_ar_bits_addr_0; // @[UserYanker.scala:36:9]
wire [7:0] auto_out_ar_bits_len_0; // @[UserYanker.scala:36:9]
wire [2:0] auto_out_ar_bits_size_0; // @[UserYanker.scala:36:9]
wire [1:0] auto_out_ar_bits_burst_0; // @[UserYanker.scala:36:9]
wire auto_out_ar_bits_lock_0; // @[UserYanker.scala:36:9]
wire [3:0] auto_out_ar_bits_cache_0; // @[UserYanker.scala:36:9]
wire [2:0] auto_out_ar_bits_prot_0; // @[UserYanker.scala:36:9]
wire [3:0] auto_out_ar_bits_qos_0; // @[UserYanker.scala:36:9]
wire auto_out_ar_valid_0; // @[UserYanker.scala:36:9]
wire auto_out_r_ready_0; // @[UserYanker.scala:36:9]
wire _nodeIn_aw_ready_T; // @[UserYanker.scala:89:36]
assign auto_in_aw_ready_0 = nodeIn_aw_ready; // @[UserYanker.scala:36:9]
assign nodeOut_aw_bits_id = nodeIn_aw_bits_id; // @[MixedNode.scala:542:17, :551:17]
wire [3:0] awsel_shiftAmount = nodeIn_aw_bits_id; // @[OneHot.scala:64:49]
assign nodeOut_aw_bits_addr = nodeIn_aw_bits_addr; // @[MixedNode.scala:542:17, :551:17]
assign nodeOut_aw_bits_len = nodeIn_aw_bits_len; // @[MixedNode.scala:542:17, :551:17]
assign nodeOut_aw_bits_size = nodeIn_aw_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign nodeOut_aw_bits_burst = nodeIn_aw_bits_burst; // @[MixedNode.scala:542:17, :551:17]
assign nodeOut_aw_bits_lock = nodeIn_aw_bits_lock; // @[MixedNode.scala:542:17, :551:17]
assign nodeOut_aw_bits_cache = nodeIn_aw_bits_cache; // @[MixedNode.scala:542:17, :551:17]
assign nodeOut_aw_bits_prot = nodeIn_aw_bits_prot; // @[MixedNode.scala:542:17, :551:17]
assign nodeOut_aw_bits_qos = nodeIn_aw_bits_qos; // @[MixedNode.scala:542:17, :551:17]
assign auto_in_w_ready_0 = nodeIn_w_ready; // @[UserYanker.scala:36:9]
assign nodeOut_w_valid = nodeIn_w_valid; // @[MixedNode.scala:542:17, :551:17]
assign nodeOut_w_bits_data = nodeIn_w_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign nodeOut_w_bits_strb = nodeIn_w_bits_strb; // @[MixedNode.scala:542:17, :551:17]
assign nodeOut_w_bits_last = nodeIn_w_bits_last; // @[MixedNode.scala:542:17, :551:17]
assign nodeOut_b_ready = nodeIn_b_ready; // @[MixedNode.scala:542:17, :551:17]
assign auto_in_b_valid_0 = nodeIn_b_valid; // @[UserYanker.scala:36:9]
assign auto_in_b_bits_id_0 = nodeIn_b_bits_id; // @[UserYanker.scala:36:9]
assign auto_in_b_bits_resp_0 = nodeIn_b_bits_resp; // @[UserYanker.scala:36:9]
assign auto_in_b_bits_echo_tl_state_size_0 = nodeIn_b_bits_echo_tl_state_size; // @[UserYanker.scala:36:9]
assign auto_in_b_bits_echo_tl_state_source_0 = nodeIn_b_bits_echo_tl_state_source; // @[UserYanker.scala:36:9]
assign auto_in_b_bits_echo_extra_id_0 = nodeIn_b_bits_echo_extra_id; // @[UserYanker.scala:36:9]
wire _nodeIn_ar_ready_T; // @[UserYanker.scala:60:36]
assign auto_in_ar_ready_0 = nodeIn_ar_ready; // @[UserYanker.scala:36:9]
assign nodeOut_ar_bits_id = nodeIn_ar_bits_id; // @[MixedNode.scala:542:17, :551:17]
wire [3:0] arsel_shiftAmount = nodeIn_ar_bits_id; // @[OneHot.scala:64:49]
assign nodeOut_ar_bits_addr = nodeIn_ar_bits_addr; // @[MixedNode.scala:542:17, :551:17]
assign nodeOut_ar_bits_len = nodeIn_ar_bits_len; // @[MixedNode.scala:542:17, :551:17]
assign nodeOut_ar_bits_size = nodeIn_ar_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign nodeOut_ar_bits_burst = nodeIn_ar_bits_burst; // @[MixedNode.scala:542:17, :551:17]
assign nodeOut_ar_bits_lock = nodeIn_ar_bits_lock; // @[MixedNode.scala:542:17, :551:17]
assign nodeOut_ar_bits_cache = nodeIn_ar_bits_cache; // @[MixedNode.scala:542:17, :551:17]
assign nodeOut_ar_bits_prot = nodeIn_ar_bits_prot; // @[MixedNode.scala:542:17, :551:17]
assign nodeOut_ar_bits_qos = nodeIn_ar_bits_qos; // @[MixedNode.scala:542:17, :551:17]
assign nodeOut_r_ready = nodeIn_r_ready; // @[MixedNode.scala:542:17, :551:17]
assign auto_in_r_valid_0 = nodeIn_r_valid; // @[UserYanker.scala:36:9]
assign auto_in_r_bits_id_0 = nodeIn_r_bits_id; // @[UserYanker.scala:36:9]
assign auto_in_r_bits_data_0 = nodeIn_r_bits_data; // @[UserYanker.scala:36:9]
assign auto_in_r_bits_resp_0 = nodeIn_r_bits_resp; // @[UserYanker.scala:36:9]
assign auto_in_r_bits_echo_tl_state_size_0 = nodeIn_r_bits_echo_tl_state_size; // @[UserYanker.scala:36:9]
assign auto_in_r_bits_echo_tl_state_source_0 = nodeIn_r_bits_echo_tl_state_source; // @[UserYanker.scala:36:9]
assign auto_in_r_bits_echo_extra_id_0 = nodeIn_r_bits_echo_extra_id; // @[UserYanker.scala:36:9]
assign auto_in_r_bits_last_0 = nodeIn_r_bits_last; // @[UserYanker.scala:36:9]
wire _nodeOut_aw_valid_T; // @[UserYanker.scala:90:36]
assign auto_out_aw_valid_0 = nodeOut_aw_valid; // @[UserYanker.scala:36:9]
assign auto_out_aw_bits_id_0 = nodeOut_aw_bits_id; // @[UserYanker.scala:36:9]
assign auto_out_aw_bits_addr_0 = nodeOut_aw_bits_addr; // @[UserYanker.scala:36:9]
assign auto_out_aw_bits_len_0 = nodeOut_aw_bits_len; // @[UserYanker.scala:36:9]
assign auto_out_aw_bits_size_0 = nodeOut_aw_bits_size; // @[UserYanker.scala:36:9]
assign auto_out_aw_bits_burst_0 = nodeOut_aw_bits_burst; // @[UserYanker.scala:36:9]
assign auto_out_aw_bits_lock_0 = nodeOut_aw_bits_lock; // @[UserYanker.scala:36:9]
assign auto_out_aw_bits_cache_0 = nodeOut_aw_bits_cache; // @[UserYanker.scala:36:9]
assign auto_out_aw_bits_prot_0 = nodeOut_aw_bits_prot; // @[UserYanker.scala:36:9]
assign auto_out_aw_bits_qos_0 = nodeOut_aw_bits_qos; // @[UserYanker.scala:36:9]
assign nodeIn_w_ready = nodeOut_w_ready; // @[MixedNode.scala:542:17, :551:17]
assign auto_out_w_valid_0 = nodeOut_w_valid; // @[UserYanker.scala:36:9]
assign auto_out_w_bits_data_0 = nodeOut_w_bits_data; // @[UserYanker.scala:36:9]
assign auto_out_w_bits_strb_0 = nodeOut_w_bits_strb; // @[UserYanker.scala:36:9]
assign auto_out_w_bits_last_0 = nodeOut_w_bits_last; // @[UserYanker.scala:36:9]
assign auto_out_b_ready_0 = nodeOut_b_ready; // @[UserYanker.scala:36:9]
assign nodeIn_b_valid = nodeOut_b_valid; // @[MixedNode.scala:542:17, :551:17]
assign nodeIn_b_bits_id = nodeOut_b_bits_id; // @[MixedNode.scala:542:17, :551:17]
wire [3:0] bsel_shiftAmount = nodeOut_b_bits_id; // @[OneHot.scala:64:49]
assign nodeIn_b_bits_resp = nodeOut_b_bits_resp; // @[MixedNode.scala:542:17, :551:17]
wire _nodeOut_ar_valid_T; // @[UserYanker.scala:61:36]
assign auto_out_ar_valid_0 = nodeOut_ar_valid; // @[UserYanker.scala:36:9]
assign auto_out_ar_bits_id_0 = nodeOut_ar_bits_id; // @[UserYanker.scala:36:9]
assign auto_out_ar_bits_addr_0 = nodeOut_ar_bits_addr; // @[UserYanker.scala:36:9]
assign auto_out_ar_bits_len_0 = nodeOut_ar_bits_len; // @[UserYanker.scala:36:9]
assign auto_out_ar_bits_size_0 = nodeOut_ar_bits_size; // @[UserYanker.scala:36:9]
assign auto_out_ar_bits_burst_0 = nodeOut_ar_bits_burst; // @[UserYanker.scala:36:9]
assign auto_out_ar_bits_lock_0 = nodeOut_ar_bits_lock; // @[UserYanker.scala:36:9]
assign auto_out_ar_bits_cache_0 = nodeOut_ar_bits_cache; // @[UserYanker.scala:36:9]
assign auto_out_ar_bits_prot_0 = nodeOut_ar_bits_prot; // @[UserYanker.scala:36:9]
assign auto_out_ar_bits_qos_0 = nodeOut_ar_bits_qos; // @[UserYanker.scala:36:9]
assign auto_out_r_ready_0 = nodeOut_r_ready; // @[UserYanker.scala:36:9]
assign nodeIn_r_valid = nodeOut_r_valid; // @[MixedNode.scala:542:17, :551:17]
assign nodeIn_r_bits_id = nodeOut_r_bits_id; // @[MixedNode.scala:542:17, :551:17]
wire [3:0] rsel_shiftAmount = nodeOut_r_bits_id; // @[OneHot.scala:64:49]
assign nodeIn_r_bits_data = nodeOut_r_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign nodeIn_r_bits_resp = nodeOut_r_bits_resp; // @[MixedNode.scala:542:17, :551:17]
assign nodeIn_r_bits_last = nodeOut_r_bits_last; // @[MixedNode.scala:542:17, :551:17]
wire _ar_ready_WIRE_0; // @[UserYanker.scala:59:29]
wire _ar_ready_WIRE_1; // @[UserYanker.scala:59:29]
wire _ar_ready_WIRE_2; // @[UserYanker.scala:59:29]
wire _ar_ready_WIRE_3; // @[UserYanker.scala:59:29]
wire _ar_ready_WIRE_4; // @[UserYanker.scala:59:29]
wire _ar_ready_WIRE_5; // @[UserYanker.scala:59:29]
wire _ar_ready_WIRE_6; // @[UserYanker.scala:59:29]
wire _ar_ready_WIRE_7; // @[UserYanker.scala:59:29]
wire _ar_ready_WIRE_8; // @[UserYanker.scala:59:29]
wire _ar_ready_WIRE_9; // @[UserYanker.scala:59:29]
wire _ar_ready_WIRE_10; // @[UserYanker.scala:59:29]
wire _ar_ready_WIRE_11; // @[UserYanker.scala:59:29]
wire _ar_ready_WIRE_12; // @[UserYanker.scala:59:29]
wire _ar_ready_WIRE_13; // @[UserYanker.scala:59:29]
wire _ar_ready_WIRE_14; // @[UserYanker.scala:59:29]
wire _ar_ready_WIRE_15; // @[UserYanker.scala:59:29]
wire [15:0] _GEN = {{_ar_ready_WIRE_15}, {_ar_ready_WIRE_14}, {_ar_ready_WIRE_13}, {_ar_ready_WIRE_12}, {_ar_ready_WIRE_11}, {_ar_ready_WIRE_10}, {_ar_ready_WIRE_9}, {_ar_ready_WIRE_8}, {_ar_ready_WIRE_7}, {_ar_ready_WIRE_6}, {_ar_ready_WIRE_5}, {_ar_ready_WIRE_4}, {_ar_ready_WIRE_3}, {_ar_ready_WIRE_2}, {_ar_ready_WIRE_1}, {_ar_ready_WIRE_0}}; // @[UserYanker.scala:59:29, :60:36]
assign _nodeIn_ar_ready_T = nodeOut_ar_ready & _GEN[nodeIn_ar_bits_id]; // @[UserYanker.scala:60:36]
assign nodeIn_ar_ready = _nodeIn_ar_ready_T; // @[UserYanker.scala:60:36]
assign _nodeOut_ar_valid_T = nodeIn_ar_valid & _GEN[nodeIn_ar_bits_id]; // @[UserYanker.scala:60:36, :61:36]
assign nodeOut_ar_valid = _nodeOut_ar_valid_T; // @[UserYanker.scala:61:36]
wire [3:0] _r_bits_WIRE_0_tl_state_size; // @[UserYanker.scala:68:27]
wire [3:0] _r_bits_WIRE_1_tl_state_size; // @[UserYanker.scala:68:27]
wire [3:0] _r_bits_WIRE_2_tl_state_size; // @[UserYanker.scala:68:27]
wire [3:0] _r_bits_WIRE_3_tl_state_size; // @[UserYanker.scala:68:27]
wire [3:0] _r_bits_WIRE_4_tl_state_size; // @[UserYanker.scala:68:27]
wire [3:0] _r_bits_WIRE_5_tl_state_size; // @[UserYanker.scala:68:27]
wire [3:0] _r_bits_WIRE_6_tl_state_size; // @[UserYanker.scala:68:27]
wire [3:0] _r_bits_WIRE_7_tl_state_size; // @[UserYanker.scala:68:27]
wire [3:0] _r_bits_WIRE_8_tl_state_size; // @[UserYanker.scala:68:27]
wire [3:0] _r_bits_WIRE_9_tl_state_size; // @[UserYanker.scala:68:27]
wire [3:0] _r_bits_WIRE_10_tl_state_size; // @[UserYanker.scala:68:27]
wire [3:0] _r_bits_WIRE_11_tl_state_size; // @[UserYanker.scala:68:27]
wire [3:0] _r_bits_WIRE_12_tl_state_size; // @[UserYanker.scala:68:27]
wire [3:0] _r_bits_WIRE_13_tl_state_size; // @[UserYanker.scala:68:27]
wire [3:0] _r_bits_WIRE_14_tl_state_size; // @[UserYanker.scala:68:27]
wire [3:0] _r_bits_WIRE_15_tl_state_size; // @[UserYanker.scala:68:27]
wire [15:0][3:0] _GEN_0 = {{_r_bits_WIRE_15_tl_state_size}, {_r_bits_WIRE_14_tl_state_size}, {_r_bits_WIRE_13_tl_state_size}, {_r_bits_WIRE_12_tl_state_size}, {_r_bits_WIRE_11_tl_state_size}, {_r_bits_WIRE_10_tl_state_size}, {_r_bits_WIRE_9_tl_state_size}, {_r_bits_WIRE_8_tl_state_size}, {_r_bits_WIRE_7_tl_state_size}, {_r_bits_WIRE_6_tl_state_size}, {_r_bits_WIRE_5_tl_state_size}, {_r_bits_WIRE_4_tl_state_size}, {_r_bits_WIRE_3_tl_state_size}, {_r_bits_WIRE_2_tl_state_size}, {_r_bits_WIRE_1_tl_state_size}, {_r_bits_WIRE_0_tl_state_size}}; // @[UserYanker.scala:68:27, :73:22]
assign nodeIn_r_bits_echo_tl_state_size = _GEN_0[nodeOut_r_bits_id]; // @[UserYanker.scala:73:22]
wire [5:0] _r_bits_WIRE_0_tl_state_source; // @[UserYanker.scala:68:27]
wire [5:0] _r_bits_WIRE_1_tl_state_source; // @[UserYanker.scala:68:27]
wire [5:0] _r_bits_WIRE_2_tl_state_source; // @[UserYanker.scala:68:27]
wire [5:0] _r_bits_WIRE_3_tl_state_source; // @[UserYanker.scala:68:27]
wire [5:0] _r_bits_WIRE_4_tl_state_source; // @[UserYanker.scala:68:27]
wire [5:0] _r_bits_WIRE_5_tl_state_source; // @[UserYanker.scala:68:27]
wire [5:0] _r_bits_WIRE_6_tl_state_source; // @[UserYanker.scala:68:27]
wire [5:0] _r_bits_WIRE_7_tl_state_source; // @[UserYanker.scala:68:27]
wire [5:0] _r_bits_WIRE_8_tl_state_source; // @[UserYanker.scala:68:27]
wire [5:0] _r_bits_WIRE_9_tl_state_source; // @[UserYanker.scala:68:27]
wire [5:0] _r_bits_WIRE_10_tl_state_source; // @[UserYanker.scala:68:27]
wire [5:0] _r_bits_WIRE_11_tl_state_source; // @[UserYanker.scala:68:27]
wire [5:0] _r_bits_WIRE_12_tl_state_source; // @[UserYanker.scala:68:27]
wire [5:0] _r_bits_WIRE_13_tl_state_source; // @[UserYanker.scala:68:27]
wire [5:0] _r_bits_WIRE_14_tl_state_source; // @[UserYanker.scala:68:27]
wire [5:0] _r_bits_WIRE_15_tl_state_source; // @[UserYanker.scala:68:27]
wire [15:0][5:0] _GEN_1 = {{_r_bits_WIRE_15_tl_state_source}, {_r_bits_WIRE_14_tl_state_source}, {_r_bits_WIRE_13_tl_state_source}, {_r_bits_WIRE_12_tl_state_source}, {_r_bits_WIRE_11_tl_state_source}, {_r_bits_WIRE_10_tl_state_source}, {_r_bits_WIRE_9_tl_state_source}, {_r_bits_WIRE_8_tl_state_source}, {_r_bits_WIRE_7_tl_state_source}, {_r_bits_WIRE_6_tl_state_source}, {_r_bits_WIRE_5_tl_state_source}, {_r_bits_WIRE_4_tl_state_source}, {_r_bits_WIRE_3_tl_state_source}, {_r_bits_WIRE_2_tl_state_source}, {_r_bits_WIRE_1_tl_state_source}, {_r_bits_WIRE_0_tl_state_source}}; // @[UserYanker.scala:68:27, :73:22]
assign nodeIn_r_bits_echo_tl_state_source = _GEN_1[nodeOut_r_bits_id]; // @[UserYanker.scala:73:22]
wire [1:0] _r_bits_WIRE_0_extra_id; // @[UserYanker.scala:68:27]
wire [1:0] _r_bits_WIRE_1_extra_id; // @[UserYanker.scala:68:27]
wire [1:0] _r_bits_WIRE_2_extra_id; // @[UserYanker.scala:68:27]
wire [1:0] _r_bits_WIRE_3_extra_id; // @[UserYanker.scala:68:27]
wire [1:0] _r_bits_WIRE_4_extra_id; // @[UserYanker.scala:68:27]
wire [1:0] _r_bits_WIRE_5_extra_id; // @[UserYanker.scala:68:27]
wire [1:0] _r_bits_WIRE_6_extra_id; // @[UserYanker.scala:68:27]
wire [1:0] _r_bits_WIRE_7_extra_id; // @[UserYanker.scala:68:27]
wire [1:0] _r_bits_WIRE_8_extra_id; // @[UserYanker.scala:68:27]
wire [1:0] _r_bits_WIRE_9_extra_id; // @[UserYanker.scala:68:27]
wire [1:0] _r_bits_WIRE_10_extra_id; // @[UserYanker.scala:68:27]
wire [1:0] _r_bits_WIRE_11_extra_id; // @[UserYanker.scala:68:27]
wire [1:0] _r_bits_WIRE_12_extra_id; // @[UserYanker.scala:68:27]
wire [1:0] _r_bits_WIRE_13_extra_id; // @[UserYanker.scala:68:27]
wire [1:0] _r_bits_WIRE_14_extra_id; // @[UserYanker.scala:68:27]
wire [1:0] _r_bits_WIRE_15_extra_id; // @[UserYanker.scala:68:27]
wire [15:0][1:0] _GEN_2 = {{_r_bits_WIRE_15_extra_id}, {_r_bits_WIRE_14_extra_id}, {_r_bits_WIRE_13_extra_id}, {_r_bits_WIRE_12_extra_id}, {_r_bits_WIRE_11_extra_id}, {_r_bits_WIRE_10_extra_id}, {_r_bits_WIRE_9_extra_id}, {_r_bits_WIRE_8_extra_id}, {_r_bits_WIRE_7_extra_id}, {_r_bits_WIRE_6_extra_id}, {_r_bits_WIRE_5_extra_id}, {_r_bits_WIRE_4_extra_id}, {_r_bits_WIRE_3_extra_id}, {_r_bits_WIRE_2_extra_id}, {_r_bits_WIRE_1_extra_id}, {_r_bits_WIRE_0_extra_id}}; // @[UserYanker.scala:68:27, :73:22]
assign nodeIn_r_bits_echo_extra_id = _GEN_2[nodeOut_r_bits_id]; // @[UserYanker.scala:73:22]
wire [15:0] _arsel_T = 16'h1 << arsel_shiftAmount; // @[OneHot.scala:64:49, :65:12]
wire [15:0] _arsel_T_1 = _arsel_T; // @[OneHot.scala:65:{12,27}]
wire arsel_0 = _arsel_T_1[0]; // @[OneHot.scala:65:27]
wire arsel_1 = _arsel_T_1[1]; // @[OneHot.scala:65:27]
wire arsel_2 = _arsel_T_1[2]; // @[OneHot.scala:65:27]
wire arsel_3 = _arsel_T_1[3]; // @[OneHot.scala:65:27]
wire arsel_4 = _arsel_T_1[4]; // @[OneHot.scala:65:27]
wire arsel_5 = _arsel_T_1[5]; // @[OneHot.scala:65:27]
wire arsel_6 = _arsel_T_1[6]; // @[OneHot.scala:65:27]
wire arsel_7 = _arsel_T_1[7]; // @[OneHot.scala:65:27]
wire arsel_8 = _arsel_T_1[8]; // @[OneHot.scala:65:27]
wire arsel_9 = _arsel_T_1[9]; // @[OneHot.scala:65:27]
wire arsel_10 = _arsel_T_1[10]; // @[OneHot.scala:65:27]
wire arsel_11 = _arsel_T_1[11]; // @[OneHot.scala:65:27]
wire arsel_12 = _arsel_T_1[12]; // @[OneHot.scala:65:27]
wire arsel_13 = _arsel_T_1[13]; // @[OneHot.scala:65:27]
wire arsel_14 = _arsel_T_1[14]; // @[OneHot.scala:65:27]
wire arsel_15 = _arsel_T_1[15]; // @[OneHot.scala:65:27]
wire [15:0] _rsel_T = 16'h1 << rsel_shiftAmount; // @[OneHot.scala:64:49, :65:12]
wire [15:0] _rsel_T_1 = _rsel_T; // @[OneHot.scala:65:{12,27}]
wire rsel_0 = _rsel_T_1[0]; // @[OneHot.scala:65:27]
wire rsel_1 = _rsel_T_1[1]; // @[OneHot.scala:65:27]
wire rsel_2 = _rsel_T_1[2]; // @[OneHot.scala:65:27]
wire rsel_3 = _rsel_T_1[3]; // @[OneHot.scala:65:27]
wire rsel_4 = _rsel_T_1[4]; // @[OneHot.scala:65:27]
wire rsel_5 = _rsel_T_1[5]; // @[OneHot.scala:65:27]
wire rsel_6 = _rsel_T_1[6]; // @[OneHot.scala:65:27]
wire rsel_7 = _rsel_T_1[7]; // @[OneHot.scala:65:27]
wire rsel_8 = _rsel_T_1[8]; // @[OneHot.scala:65:27]
wire rsel_9 = _rsel_T_1[9]; // @[OneHot.scala:65:27]
wire rsel_10 = _rsel_T_1[10]; // @[OneHot.scala:65:27]
wire rsel_11 = _rsel_T_1[11]; // @[OneHot.scala:65:27]
wire rsel_12 = _rsel_T_1[12]; // @[OneHot.scala:65:27]
wire rsel_13 = _rsel_T_1[13]; // @[OneHot.scala:65:27]
wire rsel_14 = _rsel_T_1[14]; // @[OneHot.scala:65:27]
wire rsel_15 = _rsel_T_1[15]; // @[OneHot.scala:65:27]
wire _T_80 = nodeOut_r_valid & nodeIn_r_ready; // @[UserYanker.scala:78:37]
wire _T_83 = nodeIn_ar_valid & nodeOut_ar_ready; // @[UserYanker.scala:81:37]
wire _aw_ready_WIRE_0; // @[UserYanker.scala:88:29]
wire _aw_ready_WIRE_1; // @[UserYanker.scala:88:29]
wire _aw_ready_WIRE_2; // @[UserYanker.scala:88:29]
wire _aw_ready_WIRE_3; // @[UserYanker.scala:88:29]
wire _aw_ready_WIRE_4; // @[UserYanker.scala:88:29]
wire _aw_ready_WIRE_5; // @[UserYanker.scala:88:29]
wire _aw_ready_WIRE_6; // @[UserYanker.scala:88:29]
wire _aw_ready_WIRE_7; // @[UserYanker.scala:88:29]
wire _aw_ready_WIRE_8; // @[UserYanker.scala:88:29]
wire _aw_ready_WIRE_9; // @[UserYanker.scala:88:29]
wire _aw_ready_WIRE_10; // @[UserYanker.scala:88:29]
wire _aw_ready_WIRE_11; // @[UserYanker.scala:88:29]
wire _aw_ready_WIRE_12; // @[UserYanker.scala:88:29]
wire _aw_ready_WIRE_13; // @[UserYanker.scala:88:29]
wire _aw_ready_WIRE_14; // @[UserYanker.scala:88:29]
wire _aw_ready_WIRE_15; // @[UserYanker.scala:88:29]
wire [15:0] _GEN_3 = {{_aw_ready_WIRE_15}, {_aw_ready_WIRE_14}, {_aw_ready_WIRE_13}, {_aw_ready_WIRE_12}, {_aw_ready_WIRE_11}, {_aw_ready_WIRE_10}, {_aw_ready_WIRE_9}, {_aw_ready_WIRE_8}, {_aw_ready_WIRE_7}, {_aw_ready_WIRE_6}, {_aw_ready_WIRE_5}, {_aw_ready_WIRE_4}, {_aw_ready_WIRE_3}, {_aw_ready_WIRE_2}, {_aw_ready_WIRE_1}, {_aw_ready_WIRE_0}}; // @[UserYanker.scala:88:29, :89:36]
assign _nodeIn_aw_ready_T = nodeOut_aw_ready & _GEN_3[nodeIn_aw_bits_id]; // @[UserYanker.scala:89:36]
assign nodeIn_aw_ready = _nodeIn_aw_ready_T; // @[UserYanker.scala:89:36]
assign _nodeOut_aw_valid_T = nodeIn_aw_valid & _GEN_3[nodeIn_aw_bits_id]; // @[UserYanker.scala:89:36, :90:36]
assign nodeOut_aw_valid = _nodeOut_aw_valid_T; // @[UserYanker.scala:90:36]
wire _r_valid_WIRE_0; // @[UserYanker.scala:67:28]
wire _r_valid_WIRE_1; // @[UserYanker.scala:67:28]
wire _r_valid_WIRE_2; // @[UserYanker.scala:67:28]
wire _r_valid_WIRE_3; // @[UserYanker.scala:67:28]
wire _r_valid_WIRE_4; // @[UserYanker.scala:67:28]
wire _r_valid_WIRE_5; // @[UserYanker.scala:67:28]
wire _r_valid_WIRE_6; // @[UserYanker.scala:67:28]
wire _r_valid_WIRE_7; // @[UserYanker.scala:67:28]
wire _r_valid_WIRE_8; // @[UserYanker.scala:67:28]
wire _r_valid_WIRE_9; // @[UserYanker.scala:67:28]
wire _r_valid_WIRE_10; // @[UserYanker.scala:67:28]
wire _r_valid_WIRE_11; // @[UserYanker.scala:67:28]
wire _r_valid_WIRE_12; // @[UserYanker.scala:67:28]
wire _r_valid_WIRE_13; // @[UserYanker.scala:67:28]
wire _r_valid_WIRE_14; // @[UserYanker.scala:67:28]
wire _r_valid_WIRE_15; // @[UserYanker.scala:67:28]
wire _b_valid_WIRE_0; // @[UserYanker.scala:96:28]
wire _b_valid_WIRE_1; // @[UserYanker.scala:96:28]
wire _b_valid_WIRE_2; // @[UserYanker.scala:96:28]
wire _b_valid_WIRE_3; // @[UserYanker.scala:96:28]
wire _b_valid_WIRE_4; // @[UserYanker.scala:96:28]
wire _b_valid_WIRE_5; // @[UserYanker.scala:96:28]
wire _b_valid_WIRE_6; // @[UserYanker.scala:96:28]
wire _b_valid_WIRE_7; // @[UserYanker.scala:96:28]
wire _b_valid_WIRE_8; // @[UserYanker.scala:96:28]
wire _b_valid_WIRE_9; // @[UserYanker.scala:96:28]
wire _b_valid_WIRE_10; // @[UserYanker.scala:96:28]
wire _b_valid_WIRE_11; // @[UserYanker.scala:96:28]
wire _b_valid_WIRE_12; // @[UserYanker.scala:96:28]
wire _b_valid_WIRE_13; // @[UserYanker.scala:96:28]
wire _b_valid_WIRE_14; // @[UserYanker.scala:96:28]
wire _b_valid_WIRE_15; // @[UserYanker.scala:96:28] |
Generate the Verilog code corresponding to the following Chisel files.
File Misc.scala:
// See LICENSE.Berkeley for license details.
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util._
import chisel3.util.random.LFSR
import org.chipsalliance.cde.config.Parameters
import scala.math._
class ParameterizedBundle(implicit p: Parameters) extends Bundle
trait Clocked extends Bundle {
val clock = Clock()
val reset = Bool()
}
object DecoupledHelper {
def apply(rvs: Bool*) = new DecoupledHelper(rvs)
}
class DecoupledHelper(val rvs: Seq[Bool]) {
def fire(exclude: Bool, includes: Bool*) = {
require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!")
(rvs.filter(_ ne exclude) ++ includes).reduce(_ && _)
}
def fire() = {
rvs.reduce(_ && _)
}
}
object MuxT {
def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2))
def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3))
def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4))
}
/** Creates a cascade of n MuxTs to search for a key value. */
object MuxTLookup {
def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = {
var res = default
for ((k, v) <- mapping.reverse)
res = MuxT(k === key, v, res)
res
}
def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = {
var res = default
for ((k, v) <- mapping.reverse)
res = MuxT(k === key, v, res)
res
}
}
object ValidMux {
def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = {
apply(v1 +: v2.toSeq)
}
def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = {
val out = Wire(Valid(valids.head.bits.cloneType))
out.valid := valids.map(_.valid).reduce(_ || _)
out.bits := MuxCase(valids.head.bits,
valids.map(v => (v.valid -> v.bits)))
out
}
}
object Str
{
def apply(s: String): UInt = {
var i = BigInt(0)
require(s.forall(validChar _))
for (c <- s)
i = (i << 8) | c
i.U((s.length*8).W)
}
def apply(x: Char): UInt = {
require(validChar(x))
x.U(8.W)
}
def apply(x: UInt): UInt = apply(x, 10)
def apply(x: UInt, radix: Int): UInt = {
val rad = radix.U
val w = x.getWidth
require(w > 0)
var q = x
var s = digit(q % rad)
for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {
q = q / rad
s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s)
}
s
}
def apply(x: SInt): UInt = apply(x, 10)
def apply(x: SInt, radix: Int): UInt = {
val neg = x < 0.S
val abs = x.abs.asUInt
if (radix != 10) {
Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix))
} else {
val rad = radix.U
val w = abs.getWidth
require(w > 0)
var q = abs
var s = digit(q % rad)
var needSign = neg
for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {
q = q / rad
val placeSpace = q === 0.U
val space = Mux(needSign, Str('-'), Str(' '))
needSign = needSign && !placeSpace
s = Cat(Mux(placeSpace, space, digit(q % rad)), s)
}
Cat(Mux(needSign, Str('-'), Str(' ')), s)
}
}
private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0)
private def validChar(x: Char) = x == (x & 0xFF)
}
object Split
{
def apply(x: UInt, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n0), x.extract(n0-1,0))
}
def apply(x: UInt, n1: Int, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))
}
def apply(x: UInt, n2: Int, n1: Int, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))
}
}
object Random
{
def apply(mod: Int, random: UInt): UInt = {
if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0)
else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod))
}
def apply(mod: Int): UInt = apply(mod, randomizer)
def oneHot(mod: Int, random: UInt): UInt = {
if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0))
else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt
}
def oneHot(mod: Int): UInt = oneHot(mod, randomizer)
private def randomizer = LFSR(16)
private def partition(value: UInt, slices: Int) =
Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U)
}
object Majority {
def apply(in: Set[Bool]): Bool = {
val n = (in.size >> 1) + 1
val clauses = in.subsets(n).map(_.reduce(_ && _))
clauses.reduce(_ || _)
}
def apply(in: Seq[Bool]): Bool = apply(in.toSet)
def apply(in: UInt): Bool = apply(in.asBools.toSet)
}
object PopCountAtLeast {
private def two(x: UInt): (Bool, Bool) = x.getWidth match {
case 1 => (x.asBool, false.B)
case n =>
val half = x.getWidth / 2
val (leftOne, leftTwo) = two(x(half - 1, 0))
val (rightOne, rightTwo) = two(x(x.getWidth - 1, half))
(leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne))
}
def apply(x: UInt, n: Int): Bool = n match {
case 0 => true.B
case 1 => x.orR
case 2 => two(x)._2
case 3 => PopCount(x) >= n.U
}
}
// This gets used everywhere, so make the smallest circuit possible ...
// Given an address and size, create a mask of beatBytes size
// eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111
// groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01
object MaskGen {
def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = {
require (groupBy >= 1 && beatBytes >= groupBy)
require (isPow2(beatBytes) && isPow2(groupBy))
val lgBytes = log2Ceil(beatBytes)
val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U
def helper(i: Int): Seq[(Bool, Bool)] = {
if (i == 0) {
Seq((lgSize >= lgBytes.asUInt, true.B))
} else {
val sub = helper(i-1)
val size = sizeOH(lgBytes - i)
val bit = addr_lo(lgBytes - i)
val nbit = !bit
Seq.tabulate (1 << i) { j =>
val (sub_acc, sub_eq) = sub(j/2)
val eq = sub_eq && (if (j % 2 == 1) bit else nbit)
val acc = sub_acc || (size && eq)
(acc, eq)
}
}
}
if (groupBy == beatBytes) 1.U else
Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse)
}
}
File package.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip
import chisel3._
import chisel3.util._
import scala.math.min
import scala.collection.{immutable, mutable}
package object util {
implicit class UnzippableOption[S, T](val x: Option[(S, T)]) {
def unzip = (x.map(_._1), x.map(_._2))
}
implicit class UIntIsOneOf(private val x: UInt) extends AnyVal {
def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR
def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq)
}
implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal {
/** Like Vec.apply(idx), but tolerates indices of mismatched width */
def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0))
}
implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal {
def apply(idx: UInt): T = {
if (x.size <= 1) {
x.head
} else if (!isPow2(x.size)) {
// For non-power-of-2 seqs, reflect elements to simplify decoder
(x ++ x.takeRight(x.size & -x.size)).toSeq(idx)
} else {
// Ignore MSBs of idx
val truncIdx =
if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx
else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0)
x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) }
}
}
def extract(idx: UInt): T = VecInit(x).extract(idx)
def asUInt: UInt = Cat(x.map(_.asUInt).reverse)
def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n)
def rotate(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n)
def rotateRight(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
}
// allow bitwise ops on Seq[Bool] just like UInt
implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal {
def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b }
def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b }
def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b }
def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x
def >> (n: Int): Seq[Bool] = x drop n
def unary_~ : Seq[Bool] = x.map(!_)
def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_)
def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_)
def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_)
private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B)
}
implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal {
def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable))
def getElements: Seq[Element] = x match {
case e: Element => Seq(e)
case a: Aggregate => a.getElements.flatMap(_.getElements)
}
}
/** Any Data subtype that has a Bool member named valid. */
type DataCanBeValid = Data { val valid: Bool }
implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal {
def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable)
}
implicit class StringToAugmentedString(private val x: String) extends AnyVal {
/** converts from camel case to to underscores, also removing all spaces */
def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") {
case (acc, c) if c.isUpper => acc + "_" + c.toLower
case (acc, c) if c == ' ' => acc
case (acc, c) => acc + c
}
/** converts spaces or underscores to hyphens, also lowering case */
def kebab: String = x.toLowerCase map {
case ' ' => '-'
case '_' => '-'
case c => c
}
def named(name: Option[String]): String = {
x + name.map("_named_" + _ ).getOrElse("_with_no_name")
}
def named(name: String): String = named(Some(name))
}
implicit def uintToBitPat(x: UInt): BitPat = BitPat(x)
implicit def wcToUInt(c: WideCounter): UInt = c.value
implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal {
def sextTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x)
}
def padTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(0.U((n - x.getWidth).W), x)
}
// shifts left by n if n >= 0, or right by -n if n < 0
def << (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << n(w-1, 0)
Mux(n(w), shifted >> (1 << w), shifted)
}
// shifts right by n if n >= 0, or left by -n if n < 0
def >> (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << (1 << w) >> n(w-1, 0)
Mux(n(w), shifted, shifted >> (1 << w))
}
// Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts
def extract(hi: Int, lo: Int): UInt = {
require(hi >= lo-1)
if (hi == lo-1) 0.U
else x(hi, lo)
}
// Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts
def extractOption(hi: Int, lo: Int): Option[UInt] = {
require(hi >= lo-1)
if (hi == lo-1) None
else Some(x(hi, lo))
}
// like x & ~y, but first truncate or zero-extend y to x's width
def andNot(y: UInt): UInt = x & ~(y | (x & 0.U))
def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n)
def rotateRight(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r))
}
}
def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n))
def rotateLeft(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r))
}
}
// compute (this + y) % n, given (this < n) and (y < n)
def addWrap(y: UInt, n: Int): UInt = {
val z = x +& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0)
}
// compute (this - y) % n, given (this < n) and (y < n)
def subWrap(y: UInt, n: Int): UInt = {
val z = x -& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0)
}
def grouped(width: Int): Seq[UInt] =
(0 until x.getWidth by width).map(base => x(base + width - 1, base))
def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds
def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x)
// Like >=, but prevents x-prop for ('x >= 0)
def >== (y: UInt): Bool = x >= y || y === 0.U
}
implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal {
def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y)
def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y)
}
implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal {
def toInt: Int = if (x) 1 else 0
// this one's snagged from scalaz
def option[T](z: => T): Option[T] = if (x) Some(z) else None
}
implicit class IntToAugmentedInt(private val x: Int) extends AnyVal {
// exact log2
def log2: Int = {
require(isPow2(x))
log2Ceil(x)
}
}
def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x)
def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x))
def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0)
def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1)
def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None
// Fill 1s from low bits to high bits
def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth)
def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0))
helper(1, x)(width-1, 0)
}
// Fill 1s form high bits to low bits
def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth)
def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x >> s))
helper(1, x)(width-1, 0)
}
def OptimizationBarrier[T <: Data](in: T): T = {
val barrier = Module(new Module {
val io = IO(new Bundle {
val x = Input(chiselTypeOf(in))
val y = Output(chiselTypeOf(in))
})
io.y := io.x
override def desiredName = s"OptimizationBarrier_${in.typeName}"
})
barrier.io.x := in
barrier.io.y
}
/** Similar to Seq.groupBy except this returns a Seq instead of a Map
* Useful for deterministic code generation
*/
def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = {
val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]]
for (x <- xs) {
val key = f(x)
val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A])
l += x
}
map.view.map({ case (k, vs) => k -> vs.toList }).toList
}
def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match {
case 1 => List.fill(n)(in.head)
case x if x == n => in
case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in")
}
// HeterogeneousBag moved to standalond diplomacy
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts)
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag
}
File Metadata.scala:
// See LICENSE.SiFive for license details.
// See LICENSE.Berkeley for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import freechips.rocketchip.rocket.constants.MemoryOpConstants
import freechips.rocketchip.util._
object ClientStates {
val width = 2
def Nothing = 0.U(width.W)
def Branch = 1.U(width.W)
def Trunk = 2.U(width.W)
def Dirty = 3.U(width.W)
def hasReadPermission(state: UInt): Bool = state > Nothing
def hasWritePermission(state: UInt): Bool = state > Branch
}
object MemoryOpCategories extends MemoryOpConstants {
def wr = Cat(true.B, true.B) // Op actually writes
def wi = Cat(false.B, true.B) // Future op will write
def rd = Cat(false.B, false.B) // Op only reads
def categorize(cmd: UInt): UInt = {
val cat = Cat(isWrite(cmd), isWriteIntent(cmd))
//assert(cat.isOneOf(wr,wi,rd), "Could not categorize command.")
cat
}
}
/** Stores the client-side coherence information,
* such as permissions on the data and whether the data is dirty.
* Its API can be used to make TileLink messages in response to
* memory operations, cache control oeprations, or Probe messages.
*/
class ClientMetadata extends Bundle {
/** Actual state information stored in this bundle */
val state = UInt(ClientStates.width.W)
/** Metadata equality */
def ===(rhs: UInt): Bool = state === rhs
def ===(rhs: ClientMetadata): Bool = state === rhs.state
def =/=(rhs: ClientMetadata): Bool = !this.===(rhs)
/** Is the block's data present in this cache */
def isValid(dummy: Int = 0): Bool = state > ClientStates.Nothing
/** Determine whether this cmd misses, and the new state (on hit) or param to be sent (on miss) */
private def growStarter(cmd: UInt): (Bool, UInt) = {
import MemoryOpCategories._
import TLPermissions._
import ClientStates._
val c = categorize(cmd)
MuxTLookup(Cat(c, state), (false.B, 0.U), Seq(
//(effect, am now) -> (was a hit, next)
Cat(rd, Dirty) -> (true.B, Dirty),
Cat(rd, Trunk) -> (true.B, Trunk),
Cat(rd, Branch) -> (true.B, Branch),
Cat(wi, Dirty) -> (true.B, Dirty),
Cat(wi, Trunk) -> (true.B, Trunk),
Cat(wr, Dirty) -> (true.B, Dirty),
Cat(wr, Trunk) -> (true.B, Dirty),
//(effect, am now) -> (was a miss, param)
Cat(rd, Nothing) -> (false.B, NtoB),
Cat(wi, Branch) -> (false.B, BtoT),
Cat(wi, Nothing) -> (false.B, NtoT),
Cat(wr, Branch) -> (false.B, BtoT),
Cat(wr, Nothing) -> (false.B, NtoT)))
}
/** Determine what state to go to after miss based on Grant param
* For now, doesn't depend on state (which may have been Probed).
*/
private def growFinisher(cmd: UInt, param: UInt): UInt = {
import MemoryOpCategories._
import TLPermissions._
import ClientStates._
val c = categorize(cmd)
//assert(c === rd || param === toT, "Client was expecting trunk permissions.")
MuxLookup(Cat(c, param), Nothing)(Seq(
//(effect param) -> (next)
Cat(rd, toB) -> Branch,
Cat(rd, toT) -> Trunk,
Cat(wi, toT) -> Trunk,
Cat(wr, toT) -> Dirty))
}
/** Does this cache have permissions on this block sufficient to perform op,
* and what to do next (Acquire message param or updated metadata). */
def onAccess(cmd: UInt): (Bool, UInt, ClientMetadata) = {
val r = growStarter(cmd)
(r._1, r._2, ClientMetadata(r._2))
}
/** Does a secondary miss on the block require another Acquire message */
def onSecondaryAccess(first_cmd: UInt, second_cmd: UInt): (Bool, Bool, UInt, ClientMetadata, UInt) = {
import MemoryOpCategories._
val r1 = growStarter(first_cmd)
val r2 = growStarter(second_cmd)
val needs_second_acq = isWriteIntent(second_cmd) && !isWriteIntent(first_cmd)
val hit_again = r1._1 && r2._1
val dirties = categorize(second_cmd) === wr
val biggest_grow_param = Mux(dirties, r2._2, r1._2)
val dirtiest_state = ClientMetadata(biggest_grow_param)
val dirtiest_cmd = Mux(dirties, second_cmd, first_cmd)
(needs_second_acq, hit_again, biggest_grow_param, dirtiest_state, dirtiest_cmd)
}
/** Metadata change on a returned Grant */
def onGrant(cmd: UInt, param: UInt): ClientMetadata = ClientMetadata(growFinisher(cmd, param))
/** Determine what state to go to based on Probe param */
private def shrinkHelper(param: UInt): (Bool, UInt, UInt) = {
import ClientStates._
import TLPermissions._
MuxTLookup(Cat(param, state), (false.B, 0.U, 0.U), Seq(
//(wanted, am now) -> (hasDirtyData resp, next)
Cat(toT, Dirty) -> (true.B, TtoT, Trunk),
Cat(toT, Trunk) -> (false.B, TtoT, Trunk),
Cat(toT, Branch) -> (false.B, BtoB, Branch),
Cat(toT, Nothing) -> (false.B, NtoN, Nothing),
Cat(toB, Dirty) -> (true.B, TtoB, Branch),
Cat(toB, Trunk) -> (false.B, TtoB, Branch), // Policy: Don't notify on clean downgrade
Cat(toB, Branch) -> (false.B, BtoB, Branch),
Cat(toB, Nothing) -> (false.B, NtoN, Nothing),
Cat(toN, Dirty) -> (true.B, TtoN, Nothing),
Cat(toN, Trunk) -> (false.B, TtoN, Nothing), // Policy: Don't notify on clean downgrade
Cat(toN, Branch) -> (false.B, BtoN, Nothing), // Policy: Don't notify on clean downgrade
Cat(toN, Nothing) -> (false.B, NtoN, Nothing)))
}
/** Translate cache control cmds into Probe param */
private def cmdToPermCap(cmd: UInt): UInt = {
import MemoryOpCategories._
import TLPermissions._
MuxLookup(cmd, toN)(Seq(
M_FLUSH -> toN,
M_PRODUCE -> toB,
M_CLEAN -> toT))
}
def onCacheControl(cmd: UInt): (Bool, UInt, ClientMetadata) = {
val r = shrinkHelper(cmdToPermCap(cmd))
(r._1, r._2, ClientMetadata(r._3))
}
def onProbe(param: UInt): (Bool, UInt, ClientMetadata) = {
val r = shrinkHelper(param)
(r._1, r._2, ClientMetadata(r._3))
}
}
/** Factories for ClientMetadata, including on reset */
object ClientMetadata {
def apply(perm: UInt) = {
val meta = Wire(new ClientMetadata)
meta.state := perm
meta
}
def onReset = ClientMetadata(ClientStates.Nothing)
def maximum = ClientMetadata(ClientStates.Dirty)
}
File Consts.scala:
// See LICENSE.Berkeley for license details.
package freechips.rocketchip.rocket.constants
import chisel3._
import chisel3.util._
import freechips.rocketchip.util._
trait ScalarOpConstants {
val SZ_BR = 3
def BR_X = BitPat("b???")
def BR_EQ = 0.U(3.W)
def BR_NE = 1.U(3.W)
def BR_J = 2.U(3.W)
def BR_N = 3.U(3.W)
def BR_LT = 4.U(3.W)
def BR_GE = 5.U(3.W)
def BR_LTU = 6.U(3.W)
def BR_GEU = 7.U(3.W)
def A1_X = BitPat("b??")
def A1_ZERO = 0.U(2.W)
def A1_RS1 = 1.U(2.W)
def A1_PC = 2.U(2.W)
def A1_RS1SHL = 3.U(2.W)
def IMM_X = BitPat("b???")
def IMM_S = 0.U(3.W)
def IMM_SB = 1.U(3.W)
def IMM_U = 2.U(3.W)
def IMM_UJ = 3.U(3.W)
def IMM_I = 4.U(3.W)
def IMM_Z = 5.U(3.W)
def A2_X = BitPat("b???")
def A2_ZERO = 0.U(3.W)
def A2_SIZE = 1.U(3.W)
def A2_RS2 = 2.U(3.W)
def A2_IMM = 3.U(3.W)
def A2_RS2OH = 4.U(3.W)
def A2_IMMOH = 5.U(3.W)
def X = BitPat("b?")
def N = BitPat("b0")
def Y = BitPat("b1")
val SZ_DW = 1
def DW_X = X
def DW_32 = false.B
def DW_64 = true.B
def DW_XPR = DW_64
}
trait MemoryOpConstants {
val NUM_XA_OPS = 9
val M_SZ = 5
def M_X = BitPat("b?????");
def M_XRD = "b00000".U; // int load
def M_XWR = "b00001".U; // int store
def M_PFR = "b00010".U; // prefetch with intent to read
def M_PFW = "b00011".U; // prefetch with intent to write
def M_XA_SWAP = "b00100".U
def M_FLUSH_ALL = "b00101".U // flush all lines
def M_XLR = "b00110".U
def M_XSC = "b00111".U
def M_XA_ADD = "b01000".U
def M_XA_XOR = "b01001".U
def M_XA_OR = "b01010".U
def M_XA_AND = "b01011".U
def M_XA_MIN = "b01100".U
def M_XA_MAX = "b01101".U
def M_XA_MINU = "b01110".U
def M_XA_MAXU = "b01111".U
def M_FLUSH = "b10000".U // write back dirty data and cede R/W permissions
def M_PWR = "b10001".U // partial (masked) store
def M_PRODUCE = "b10010".U // write back dirty data and cede W permissions
def M_CLEAN = "b10011".U // write back dirty data and retain R/W permissions
def M_SFENCE = "b10100".U // SFENCE.VMA
def M_HFENCEV = "b10101".U // HFENCE.VVMA
def M_HFENCEG = "b10110".U // HFENCE.GVMA
def M_WOK = "b10111".U // check write permissions but don't perform a write
def M_HLVX = "b10000".U // HLVX instruction
def isAMOLogical(cmd: UInt) = cmd.isOneOf(M_XA_SWAP, M_XA_XOR, M_XA_OR, M_XA_AND)
def isAMOArithmetic(cmd: UInt) = cmd.isOneOf(M_XA_ADD, M_XA_MIN, M_XA_MAX, M_XA_MINU, M_XA_MAXU)
def isAMO(cmd: UInt) = isAMOLogical(cmd) || isAMOArithmetic(cmd)
def isPrefetch(cmd: UInt) = cmd === M_PFR || cmd === M_PFW
def isRead(cmd: UInt) = cmd.isOneOf(M_XRD, M_HLVX, M_XLR, M_XSC) || isAMO(cmd)
def isWrite(cmd: UInt) = cmd === M_XWR || cmd === M_PWR || cmd === M_XSC || isAMO(cmd)
def isWriteIntent(cmd: UInt) = isWrite(cmd) || cmd === M_PFW || cmd === M_XLR
}
File Parameters.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.diplomacy
import chisel3._
import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor}
import freechips.rocketchip.util.ShiftQueue
/** Options for describing the attributes of memory regions */
object RegionType {
// Define the 'more relaxed than' ordering
val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS)
sealed trait T extends Ordered[T] {
def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this)
}
case object CACHED extends T // an intermediate agent may have cached a copy of the region for you
case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided
case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible
case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached
case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects
case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed
case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively
}
// A non-empty half-open range; [start, end)
case class IdRange(start: Int, end: Int) extends Ordered[IdRange]
{
require (start >= 0, s"Ids cannot be negative, but got: $start.")
require (start <= end, "Id ranges cannot be negative.")
def compare(x: IdRange) = {
val primary = (this.start - x.start).signum
val secondary = (x.end - this.end).signum
if (primary != 0) primary else secondary
}
def overlaps(x: IdRange) = start < x.end && x.start < end
def contains(x: IdRange) = start <= x.start && x.end <= end
def contains(x: Int) = start <= x && x < end
def contains(x: UInt) =
if (size == 0) {
false.B
} else if (size == 1) { // simple comparison
x === start.U
} else {
// find index of largest different bit
val largestDeltaBit = log2Floor(start ^ (end-1))
val smallestCommonBit = largestDeltaBit + 1 // may not exist in x
val uncommonMask = (1 << smallestCommonBit) - 1
val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0)
// the prefix must match exactly (note: may shift ALL bits away)
(x >> smallestCommonBit) === (start >> smallestCommonBit).U &&
// firrtl constant prop range analysis can eliminate these two:
(start & uncommonMask).U <= uncommonBits &&
uncommonBits <= ((end-1) & uncommonMask).U
}
def shift(x: Int) = IdRange(start+x, end+x)
def size = end - start
def isEmpty = end == start
def range = start until end
}
object IdRange
{
def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else {
val ranges = s.sorted
(ranges.tail zip ranges.init) find { case (a, b) => a overlaps b }
}
}
// An potentially empty inclusive range of 2-powers [min, max] (in bytes)
case class TransferSizes(min: Int, max: Int)
{
def this(x: Int) = this(x, x)
require (min <= max, s"Min transfer $min > max transfer $max")
require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)")
require (max == 0 || isPow2(max), s"TransferSizes must be a power of 2, got: $max")
require (min == 0 || isPow2(min), s"TransferSizes must be a power of 2, got: $min")
require (max == 0 || min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)")
def none = min == 0
def contains(x: Int) = isPow2(x) && min <= x && x <= max
def containsLg(x: Int) = contains(1 << x)
def containsLg(x: UInt) =
if (none) false.B
else if (min == max) { log2Ceil(min).U === x }
else { log2Ceil(min).U <= x && x <= log2Ceil(max).U }
def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max)
def intersect(x: TransferSizes) =
if (x.max < min || max < x.min) TransferSizes.none
else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max))
// Not a union, because the result may contain sizes contained by neither term
// NOT TO BE CONFUSED WITH COVERPOINTS
def mincover(x: TransferSizes) = {
if (none) {
x
} else if (x.none) {
this
} else {
TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max))
}
}
override def toString() = "TransferSizes[%d, %d]".format(min, max)
}
object TransferSizes {
def apply(x: Int) = new TransferSizes(x)
val none = new TransferSizes(0)
def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _)
def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _)
implicit def asBool(x: TransferSizes) = !x.none
}
// AddressSets specify the address space managed by the manager
// Base is the base address, and mask are the bits consumed by the manager
// e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff
// e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ...
case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet]
{
// Forbid misaligned base address (and empty sets)
require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}")
require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous
// We do allow negative mask (=> ignore all high bits)
def contains(x: BigInt) = ((x ^ base) & ~mask) == 0
def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S
// turn x into an address contained in this set
def legalize(x: UInt): UInt = base.U | (mask.U & x)
// overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1)
def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0
// contains iff bitwise: x.mask => mask && contains(x.base)
def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0
// The number of bytes to which the manager must be aligned
def alignment = ((mask + 1) & ~mask)
// Is this a contiguous memory range
def contiguous = alignment == mask+1
def finite = mask >= 0
def max = { require (finite, "Max cannot be calculated on infinite mask"); base | mask }
// Widen the match function to ignore all bits in imask
def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask)
// Return an AddressSet that only contains the addresses both sets contain
def intersect(x: AddressSet): Option[AddressSet] = {
if (!overlaps(x)) {
None
} else {
val r_mask = mask & x.mask
val r_base = base | x.base
Some(AddressSet(r_base, r_mask))
}
}
def subtract(x: AddressSet): Seq[AddressSet] = {
intersect(x) match {
case None => Seq(this)
case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit =>
val nmask = (mask & (bit-1)) | remove.mask
val nbase = (remove.base ^ bit) & ~nmask
AddressSet(nbase, nmask)
}
}
}
// AddressSets have one natural Ordering (the containment order, if contiguous)
def compare(x: AddressSet) = {
val primary = (this.base - x.base).signum // smallest address first
val secondary = (x.mask - this.mask).signum // largest mask first
if (primary != 0) primary else secondary
}
// We always want to see things in hex
override def toString() = {
if (mask >= 0) {
"AddressSet(0x%x, 0x%x)".format(base, mask)
} else {
"AddressSet(0x%x, ~0x%x)".format(base, ~mask)
}
}
def toRanges = {
require (finite, "Ranges cannot be calculated on infinite mask")
val size = alignment
val fragments = mask & ~(size-1)
val bits = bitIndexes(fragments)
(BigInt(0) until (BigInt(1) << bits.size)).map { i =>
val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) }
AddressRange(off, size)
}
}
}
object AddressSet
{
val everything = AddressSet(0, -1)
def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = {
if (size == 0) tail.reverse else {
val maxBaseAlignment = base & (-base) // 0 for infinite (LSB)
val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size
val step =
if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment)
maxSizeAlignment else maxBaseAlignment
misaligned(base+step, size-step, AddressSet(base, step-1) +: tail)
}
}
def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = {
// Pair terms up by ignoring 'bit'
seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) =>
if (seq.size == 1) {
seq.head // singleton -> unaffected
} else {
key.copy(mask = key.mask | bit) // pair - widen mask by bit
}
}.toList
}
def unify(seq: Seq[AddressSet]): Seq[AddressSet] = {
val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _)
AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted
}
def enumerateMask(mask: BigInt): Seq[BigInt] = {
def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] =
if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail)
helper(0, Nil)
}
def enumerateBits(mask: BigInt): Seq[BigInt] = {
def helper(x: BigInt): Seq[BigInt] = {
if (x == 0) {
Nil
} else {
val bit = x & (-x)
bit +: helper(x & ~bit)
}
}
helper(mask)
}
}
case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean)
{
require (depth >= 0, "Buffer depth must be >= 0")
def isDefined = depth > 0
def latency = if (isDefined && !flow) 1 else 0
def apply[T <: Data](x: DecoupledIO[T]) =
if (isDefined) Queue(x, depth, flow=flow, pipe=pipe)
else x
def irrevocable[T <: Data](x: ReadyValidIO[T]) =
if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe)
else x
def sq[T <: Data](x: DecoupledIO[T]) =
if (!isDefined) x else {
val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe))
sq.io.enq <> x
sq.io.deq
}
override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "")
}
object BufferParams
{
implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false)
val default = BufferParams(2)
val none = BufferParams(0)
val flow = BufferParams(1, true, false)
val pipe = BufferParams(1, false, true)
}
case class TriStateValue(value: Boolean, set: Boolean)
{
def update(orig: Boolean) = if (set) value else orig
}
object TriStateValue
{
implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true)
def unset = TriStateValue(false, false)
}
trait DirectedBuffers[T] {
def copyIn(x: BufferParams): T
def copyOut(x: BufferParams): T
def copyInOut(x: BufferParams): T
}
trait IdMapEntry {
def name: String
def from: IdRange
def to: IdRange
def isCache: Boolean
def requestFifo: Boolean
def maxTransactionsInFlight: Option[Int]
def pretty(fmt: String) =
if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5
fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "")
} else {
fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "")
}
}
abstract class IdMap[T <: IdMapEntry] {
protected val fmt: String
val mapping: Seq[T]
def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n")
}
File mshrs.scala:
//******************************************************************************
// Ported from Rocket-Chip
// See LICENSE.Berkeley and LICENSE.SiFive in Rocket-Chip for license details.
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
package boom.v3.lsu
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.tilelink._
import freechips.rocketchip.tile._
import freechips.rocketchip.util._
import freechips.rocketchip.rocket._
import boom.v3.common._
import boom.v3.exu.BrUpdateInfo
import boom.v3.util.{IsKilledByBranch, GetNewBrMask, BranchKillableQueue, IsOlder, UpdateBrMask, AgePriorityEncoder, WrapInc}
class BoomDCacheReqInternal(implicit p: Parameters) extends BoomDCacheReq()(p)
with HasL1HellaCacheParameters
{
// miss info
val tag_match = Bool()
val old_meta = new L1Metadata
val way_en = UInt(nWays.W)
// Used in the MSHRs
val sdq_id = UInt(log2Ceil(cfg.nSDQ).W)
}
class BoomMSHR(implicit edge: TLEdgeOut, p: Parameters) extends BoomModule()(p)
with HasL1HellaCacheParameters
{
val io = IO(new Bundle {
val id = Input(UInt())
val req_pri_val = Input(Bool())
val req_pri_rdy = Output(Bool())
val req_sec_val = Input(Bool())
val req_sec_rdy = Output(Bool())
val clear_prefetch = Input(Bool())
val brupdate = Input(new BrUpdateInfo)
val exception = Input(Bool())
val rob_pnr_idx = Input(UInt(robAddrSz.W))
val rob_head_idx = Input(UInt(robAddrSz.W))
val req = Input(new BoomDCacheReqInternal)
val req_is_probe = Input(Bool())
val idx = Output(Valid(UInt()))
val way = Output(Valid(UInt()))
val tag = Output(Valid(UInt()))
val mem_acquire = Decoupled(new TLBundleA(edge.bundle))
val mem_grant = Flipped(Decoupled(new TLBundleD(edge.bundle)))
val mem_finish = Decoupled(new TLBundleE(edge.bundle))
val prober_state = Input(Valid(UInt(coreMaxAddrBits.W)))
val refill = Decoupled(new L1DataWriteReq)
val meta_write = Decoupled(new L1MetaWriteReq)
val meta_read = Decoupled(new L1MetaReadReq)
val meta_resp = Input(Valid(new L1Metadata))
val wb_req = Decoupled(new WritebackReq(edge.bundle))
// To inform the prefetcher when we are commiting the fetch of this line
val commit_val = Output(Bool())
val commit_addr = Output(UInt(coreMaxAddrBits.W))
val commit_coh = Output(new ClientMetadata)
// Reading from the line buffer
val lb_read = Decoupled(new LineBufferReadReq)
val lb_resp = Input(UInt(encRowBits.W))
val lb_write = Decoupled(new LineBufferWriteReq)
// Replays go through the cache pipeline again
val replay = Decoupled(new BoomDCacheReqInternal)
// Resp go straight out to the core
val resp = Decoupled(new BoomDCacheResp)
// Writeback unit tells us when it is done processing our wb
val wb_resp = Input(Bool())
val probe_rdy = Output(Bool())
})
// TODO: Optimize this. We don't want to mess with cache during speculation
// s_refill_req : Make a request for a new cache line
// s_refill_resp : Store the refill response into our buffer
// s_drain_rpq_loads : Drain out loads from the rpq
// : If miss was misspeculated, go to s_invalid
// s_wb_req : Write back the evicted cache line
// s_wb_resp : Finish writing back the evicted cache line
// s_meta_write_req : Write the metadata for new cache lne
// s_meta_write_resp :
val s_invalid :: s_refill_req :: s_refill_resp :: s_drain_rpq_loads :: s_meta_read :: s_meta_resp_1 :: s_meta_resp_2 :: s_meta_clear :: s_wb_meta_read :: s_wb_req :: s_wb_resp :: s_commit_line :: s_drain_rpq :: s_meta_write_req :: s_mem_finish_1 :: s_mem_finish_2 :: s_prefetched :: s_prefetch :: Nil = Enum(18)
val state = RegInit(s_invalid)
val req = Reg(new BoomDCacheReqInternal)
val req_idx = req.addr(untagBits-1, blockOffBits)
val req_tag = req.addr >> untagBits
val req_block_addr = (req.addr >> blockOffBits) << blockOffBits
val req_needs_wb = RegInit(false.B)
val new_coh = RegInit(ClientMetadata.onReset)
val (_, shrink_param, coh_on_clear) = req.old_meta.coh.onCacheControl(M_FLUSH)
val grow_param = new_coh.onAccess(req.uop.mem_cmd)._2
val coh_on_grant = new_coh.onGrant(req.uop.mem_cmd, io.mem_grant.bits.param)
// We only accept secondary misses if the original request had sufficient permissions
val (cmd_requires_second_acquire, is_hit_again, _, dirtier_coh, dirtier_cmd) =
new_coh.onSecondaryAccess(req.uop.mem_cmd, io.req.uop.mem_cmd)
val (_, _, refill_done, refill_address_inc) = edge.addr_inc(io.mem_grant)
val sec_rdy = (!cmd_requires_second_acquire && !io.req_is_probe &&
!state.isOneOf(s_invalid, s_meta_write_req, s_mem_finish_1, s_mem_finish_2))// Always accept secondary misses
val rpq = Module(new BranchKillableQueue(new BoomDCacheReqInternal, cfg.nRPQ, u => u.uses_ldq, false))
rpq.io.brupdate := io.brupdate
rpq.io.flush := io.exception
assert(!(state === s_invalid && !rpq.io.empty))
rpq.io.enq.valid := ((io.req_pri_val && io.req_pri_rdy) || (io.req_sec_val && io.req_sec_rdy)) && !isPrefetch(io.req.uop.mem_cmd)
rpq.io.enq.bits := io.req
rpq.io.deq.ready := false.B
val grantack = Reg(Valid(new TLBundleE(edge.bundle)))
val refill_ctr = Reg(UInt(log2Ceil(cacheDataBeats).W))
val commit_line = Reg(Bool())
val grant_had_data = Reg(Bool())
val finish_to_prefetch = Reg(Bool())
// Block probes if a tag write we started is still in the pipeline
val meta_hazard = RegInit(0.U(2.W))
when (meta_hazard =/= 0.U) { meta_hazard := meta_hazard + 1.U }
when (io.meta_write.fire) { meta_hazard := 1.U }
io.probe_rdy := (meta_hazard === 0.U && (state.isOneOf(s_invalid, s_refill_req, s_refill_resp, s_drain_rpq_loads) || (state === s_meta_read && grantack.valid)))
io.idx.valid := state =/= s_invalid
io.tag.valid := state =/= s_invalid
io.way.valid := !state.isOneOf(s_invalid, s_prefetch)
io.idx.bits := req_idx
io.tag.bits := req_tag
io.way.bits := req.way_en
io.meta_write.valid := false.B
io.meta_write.bits := DontCare
io.req_pri_rdy := false.B
io.req_sec_rdy := sec_rdy && rpq.io.enq.ready
io.mem_acquire.valid := false.B
io.mem_acquire.bits := DontCare
io.refill.valid := false.B
io.refill.bits := DontCare
io.replay.valid := false.B
io.replay.bits := DontCare
io.wb_req.valid := false.B
io.wb_req.bits := DontCare
io.resp.valid := false.B
io.resp.bits := DontCare
io.commit_val := false.B
io.commit_addr := req.addr
io.commit_coh := coh_on_grant
io.meta_read.valid := false.B
io.meta_read.bits := DontCare
io.mem_finish.valid := false.B
io.mem_finish.bits := DontCare
io.lb_write.valid := false.B
io.lb_write.bits := DontCare
io.lb_read.valid := false.B
io.lb_read.bits := DontCare
io.mem_grant.ready := false.B
when (io.req_sec_val && io.req_sec_rdy) {
req.uop.mem_cmd := dirtier_cmd
when (is_hit_again) {
new_coh := dirtier_coh
}
}
def handle_pri_req(old_state: UInt): UInt = {
val new_state = WireInit(old_state)
grantack.valid := false.B
refill_ctr := 0.U
assert(rpq.io.enq.ready)
req := io.req
val old_coh = io.req.old_meta.coh
req_needs_wb := old_coh.onCacheControl(M_FLUSH)._1 // does the line we are evicting need to be written back
when (io.req.tag_match) {
val (is_hit, _, coh_on_hit) = old_coh.onAccess(io.req.uop.mem_cmd)
when (is_hit) { // set dirty bit
assert(isWrite(io.req.uop.mem_cmd))
new_coh := coh_on_hit
new_state := s_drain_rpq
} .otherwise { // upgrade permissions
new_coh := old_coh
new_state := s_refill_req
}
} .otherwise { // refill and writeback if necessary
new_coh := ClientMetadata.onReset
new_state := s_refill_req
}
new_state
}
when (state === s_invalid) {
io.req_pri_rdy := true.B
grant_had_data := false.B
when (io.req_pri_val && io.req_pri_rdy) {
state := handle_pri_req(state)
}
} .elsewhen (state === s_refill_req) {
io.mem_acquire.valid := true.B
// TODO: Use AcquirePerm if just doing permissions acquire
io.mem_acquire.bits := edge.AcquireBlock(
fromSource = io.id,
toAddress = Cat(req_tag, req_idx) << blockOffBits,
lgSize = lgCacheBlockBytes.U,
growPermissions = grow_param)._2
when (io.mem_acquire.fire) {
state := s_refill_resp
}
} .elsewhen (state === s_refill_resp) {
when (edge.hasData(io.mem_grant.bits)) {
io.mem_grant.ready := io.lb_write.ready
io.lb_write.valid := io.mem_grant.valid
io.lb_write.bits.id := io.id
io.lb_write.bits.offset := refill_address_inc >> rowOffBits
io.lb_write.bits.data := io.mem_grant.bits.data
} .otherwise {
io.mem_grant.ready := true.B
}
when (io.mem_grant.fire) {
grant_had_data := edge.hasData(io.mem_grant.bits)
}
when (refill_done) {
grantack.valid := edge.isRequest(io.mem_grant.bits)
grantack.bits := edge.GrantAck(io.mem_grant.bits)
state := Mux(grant_had_data, s_drain_rpq_loads, s_drain_rpq)
assert(!(!grant_had_data && req_needs_wb))
commit_line := false.B
new_coh := coh_on_grant
}
} .elsewhen (state === s_drain_rpq_loads) {
val drain_load = (isRead(rpq.io.deq.bits.uop.mem_cmd) &&
!isWrite(rpq.io.deq.bits.uop.mem_cmd) &&
(rpq.io.deq.bits.uop.mem_cmd =/= M_XLR)) // LR should go through replay
// drain all loads for now
val rp_addr = Cat(req_tag, req_idx, rpq.io.deq.bits.addr(blockOffBits-1,0))
val word_idx = if (rowWords == 1) 0.U else rp_addr(log2Up(rowWords*coreDataBytes)-1, log2Up(wordBytes))
val data = io.lb_resp
val data_word = data >> Cat(word_idx, 0.U(log2Up(coreDataBits).W))
val loadgen = new LoadGen(rpq.io.deq.bits.uop.mem_size, rpq.io.deq.bits.uop.mem_signed,
Cat(req_tag, req_idx, rpq.io.deq.bits.addr(blockOffBits-1,0)),
data_word, false.B, wordBytes)
rpq.io.deq.ready := io.resp.ready && io.lb_read.ready && drain_load
io.lb_read.valid := rpq.io.deq.valid && drain_load
io.lb_read.bits.id := io.id
io.lb_read.bits.offset := rpq.io.deq.bits.addr >> rowOffBits
io.resp.valid := rpq.io.deq.valid && io.lb_read.fire && drain_load
io.resp.bits.uop := rpq.io.deq.bits.uop
io.resp.bits.data := loadgen.data
io.resp.bits.is_hella := rpq.io.deq.bits.is_hella
when (rpq.io.deq.fire) {
commit_line := true.B
}
.elsewhen (rpq.io.empty && !commit_line)
{
when (!rpq.io.enq.fire) {
state := s_mem_finish_1
finish_to_prefetch := enablePrefetching.B
}
} .elsewhen (rpq.io.empty || (rpq.io.deq.valid && !drain_load)) {
// io.commit_val is for the prefetcher. it tells the prefetcher that this line was correctly acquired
// The prefetcher should consider fetching the next line
io.commit_val := true.B
state := s_meta_read
}
} .elsewhen (state === s_meta_read) {
io.meta_read.valid := !io.prober_state.valid || !grantack.valid || (io.prober_state.bits(untagBits-1,blockOffBits) =/= req_idx)
io.meta_read.bits.idx := req_idx
io.meta_read.bits.tag := req_tag
io.meta_read.bits.way_en := req.way_en
when (io.meta_read.fire) {
state := s_meta_resp_1
}
} .elsewhen (state === s_meta_resp_1) {
state := s_meta_resp_2
} .elsewhen (state === s_meta_resp_2) {
val needs_wb = io.meta_resp.bits.coh.onCacheControl(M_FLUSH)._1
state := Mux(!io.meta_resp.valid, s_meta_read, // Prober could have nack'd this read
Mux(needs_wb, s_meta_clear, s_commit_line))
} .elsewhen (state === s_meta_clear) {
io.meta_write.valid := true.B
io.meta_write.bits.idx := req_idx
io.meta_write.bits.data.coh := coh_on_clear
io.meta_write.bits.data.tag := req_tag
io.meta_write.bits.way_en := req.way_en
when (io.meta_write.fire) {
state := s_wb_req
}
} .elsewhen (state === s_wb_req) {
io.wb_req.valid := true.B
io.wb_req.bits.tag := req.old_meta.tag
io.wb_req.bits.idx := req_idx
io.wb_req.bits.param := shrink_param
io.wb_req.bits.way_en := req.way_en
io.wb_req.bits.source := io.id
io.wb_req.bits.voluntary := true.B
when (io.wb_req.fire) {
state := s_wb_resp
}
} .elsewhen (state === s_wb_resp) {
when (io.wb_resp) {
state := s_commit_line
}
} .elsewhen (state === s_commit_line) {
io.lb_read.valid := true.B
io.lb_read.bits.id := io.id
io.lb_read.bits.offset := refill_ctr
io.refill.valid := io.lb_read.fire
io.refill.bits.addr := req_block_addr | (refill_ctr << rowOffBits)
io.refill.bits.way_en := req.way_en
io.refill.bits.wmask := ~(0.U(rowWords.W))
io.refill.bits.data := io.lb_resp
when (io.refill.fire) {
refill_ctr := refill_ctr + 1.U
when (refill_ctr === (cacheDataBeats - 1).U) {
state := s_drain_rpq
}
}
} .elsewhen (state === s_drain_rpq) {
io.replay <> rpq.io.deq
io.replay.bits.way_en := req.way_en
io.replay.bits.addr := Cat(req_tag, req_idx, rpq.io.deq.bits.addr(blockOffBits-1,0))
when (io.replay.fire && isWrite(rpq.io.deq.bits.uop.mem_cmd)) {
// Set dirty bit
val (is_hit, _, coh_on_hit) = new_coh.onAccess(rpq.io.deq.bits.uop.mem_cmd)
assert(is_hit, "We still don't have permissions for this store")
new_coh := coh_on_hit
}
when (rpq.io.empty && !rpq.io.enq.valid) {
state := s_meta_write_req
}
} .elsewhen (state === s_meta_write_req) {
io.meta_write.valid := true.B
io.meta_write.bits.idx := req_idx
io.meta_write.bits.data.coh := new_coh
io.meta_write.bits.data.tag := req_tag
io.meta_write.bits.way_en := req.way_en
when (io.meta_write.fire) {
state := s_mem_finish_1
finish_to_prefetch := false.B
}
} .elsewhen (state === s_mem_finish_1) {
io.mem_finish.valid := grantack.valid
io.mem_finish.bits := grantack.bits
when (io.mem_finish.fire || !grantack.valid) {
grantack.valid := false.B
state := s_mem_finish_2
}
} .elsewhen (state === s_mem_finish_2) {
state := Mux(finish_to_prefetch, s_prefetch, s_invalid)
} .elsewhen (state === s_prefetch) {
io.req_pri_rdy := true.B
when ((io.req_sec_val && !io.req_sec_rdy) || io.clear_prefetch) {
state := s_invalid
} .elsewhen (io.req_sec_val && io.req_sec_rdy) {
val (is_hit, _, coh_on_hit) = new_coh.onAccess(io.req.uop.mem_cmd)
when (is_hit) { // Proceed with refill
new_coh := coh_on_hit
state := s_meta_read
} .otherwise { // Reacquire this line
new_coh := ClientMetadata.onReset
state := s_refill_req
}
} .elsewhen (io.req_pri_val && io.req_pri_rdy) {
grant_had_data := false.B
state := handle_pri_req(state)
}
}
}
class BoomIOMSHR(id: Int)(implicit edge: TLEdgeOut, p: Parameters) extends BoomModule()(p)
with HasL1HellaCacheParameters
{
val io = IO(new Bundle {
val req = Flipped(Decoupled(new BoomDCacheReq))
val resp = Decoupled(new BoomDCacheResp)
val mem_access = Decoupled(new TLBundleA(edge.bundle))
val mem_ack = Flipped(Valid(new TLBundleD(edge.bundle)))
// We don't need brupdate in here because uncacheable operations are guaranteed non-speculative
})
def beatOffset(addr: UInt) = addr.extract(beatOffBits-1, wordOffBits)
def wordFromBeat(addr: UInt, dat: UInt) = {
val shift = Cat(beatOffset(addr), 0.U((wordOffBits+log2Ceil(wordBytes)).W))
(dat >> shift)(wordBits-1, 0)
}
val req = Reg(new BoomDCacheReq)
val grant_word = Reg(UInt(wordBits.W))
val s_idle :: s_mem_access :: s_mem_ack :: s_resp :: Nil = Enum(4)
val state = RegInit(s_idle)
io.req.ready := state === s_idle
val loadgen = new LoadGen(req.uop.mem_size, req.uop.mem_signed, req.addr, grant_word, false.B, wordBytes)
val a_source = id.U
val a_address = req.addr
val a_size = req.uop.mem_size
val a_data = Fill(beatWords, req.data)
val get = edge.Get(a_source, a_address, a_size)._2
val put = edge.Put(a_source, a_address, a_size, a_data)._2
val atomics = if (edge.manager.anySupportLogical) {
MuxLookup(req.uop.mem_cmd, (0.U).asTypeOf(new TLBundleA(edge.bundle)))(Array(
M_XA_SWAP -> edge.Logical(a_source, a_address, a_size, a_data, TLAtomics.SWAP)._2,
M_XA_XOR -> edge.Logical(a_source, a_address, a_size, a_data, TLAtomics.XOR) ._2,
M_XA_OR -> edge.Logical(a_source, a_address, a_size, a_data, TLAtomics.OR) ._2,
M_XA_AND -> edge.Logical(a_source, a_address, a_size, a_data, TLAtomics.AND) ._2,
M_XA_ADD -> edge.Arithmetic(a_source, a_address, a_size, a_data, TLAtomics.ADD)._2,
M_XA_MIN -> edge.Arithmetic(a_source, a_address, a_size, a_data, TLAtomics.MIN)._2,
M_XA_MAX -> edge.Arithmetic(a_source, a_address, a_size, a_data, TLAtomics.MAX)._2,
M_XA_MINU -> edge.Arithmetic(a_source, a_address, a_size, a_data, TLAtomics.MINU)._2,
M_XA_MAXU -> edge.Arithmetic(a_source, a_address, a_size, a_data, TLAtomics.MAXU)._2))
} else {
// If no managers support atomics, assert fail if processor asks for them
assert(state === s_idle || !isAMO(req.uop.mem_cmd))
(0.U).asTypeOf(new TLBundleA(edge.bundle))
}
assert(state === s_idle || req.uop.mem_cmd =/= M_XSC)
io.mem_access.valid := state === s_mem_access
io.mem_access.bits := Mux(isAMO(req.uop.mem_cmd), atomics, Mux(isRead(req.uop.mem_cmd), get, put))
val send_resp = isRead(req.uop.mem_cmd)
io.resp.valid := (state === s_resp) && send_resp
io.resp.bits.is_hella := req.is_hella
io.resp.bits.uop := req.uop
io.resp.bits.data := loadgen.data
when (io.req.fire) {
req := io.req.bits
state := s_mem_access
}
when (io.mem_access.fire) {
state := s_mem_ack
}
when (state === s_mem_ack && io.mem_ack.valid) {
state := s_resp
when (isRead(req.uop.mem_cmd)) {
grant_word := wordFromBeat(req.addr, io.mem_ack.bits.data)
}
}
when (state === s_resp) {
when (!send_resp || io.resp.fire) {
state := s_idle
}
}
}
class LineBufferReadReq(implicit p: Parameters) extends BoomBundle()(p)
with HasL1HellaCacheParameters
{
val id = UInt(log2Ceil(nLBEntries).W)
val offset = UInt(log2Ceil(cacheDataBeats).W)
def lb_addr = Cat(id, offset)
}
class LineBufferWriteReq(implicit p: Parameters) extends LineBufferReadReq()(p)
{
val data = UInt(encRowBits.W)
}
class LineBufferMetaWriteReq(implicit p: Parameters) extends BoomBundle()(p)
{
val id = UInt(log2Ceil(nLBEntries).W)
val coh = new ClientMetadata
val addr = UInt(coreMaxAddrBits.W)
}
class LineBufferMeta(implicit p: Parameters) extends BoomBundle()(p)
with HasL1HellaCacheParameters
{
val coh = new ClientMetadata
val addr = UInt(coreMaxAddrBits.W)
}
class BoomMSHRFile(implicit edge: TLEdgeOut, p: Parameters) extends BoomModule()(p)
with HasL1HellaCacheParameters
{
val io = IO(new Bundle {
val req = Flipped(Vec(memWidth, Decoupled(new BoomDCacheReqInternal))) // Req from s2 of DCache pipe
val req_is_probe = Input(Vec(memWidth, Bool()))
val resp = Decoupled(new BoomDCacheResp)
val secondary_miss = Output(Vec(memWidth, Bool()))
val block_hit = Output(Vec(memWidth, Bool()))
val brupdate = Input(new BrUpdateInfo)
val exception = Input(Bool())
val rob_pnr_idx = Input(UInt(robAddrSz.W))
val rob_head_idx = Input(UInt(robAddrSz.W))
val mem_acquire = Decoupled(new TLBundleA(edge.bundle))
val mem_grant = Flipped(Decoupled(new TLBundleD(edge.bundle)))
val mem_finish = Decoupled(new TLBundleE(edge.bundle))
val refill = Decoupled(new L1DataWriteReq)
val meta_write = Decoupled(new L1MetaWriteReq)
val meta_read = Decoupled(new L1MetaReadReq)
val meta_resp = Input(Valid(new L1Metadata))
val replay = Decoupled(new BoomDCacheReqInternal)
val prefetch = Decoupled(new BoomDCacheReq)
val wb_req = Decoupled(new WritebackReq(edge.bundle))
val prober_state = Input(Valid(UInt(coreMaxAddrBits.W)))
val clear_all = Input(Bool()) // Clears all uncommitted MSHRs to prepare for fence
val wb_resp = Input(Bool())
val fence_rdy = Output(Bool())
val probe_rdy = Output(Bool())
})
val req_idx = OHToUInt(io.req.map(_.valid))
val req = io.req(req_idx)
val req_is_probe = io.req_is_probe(0)
for (w <- 0 until memWidth)
io.req(w).ready := false.B
val prefetcher: DataPrefetcher = if (enablePrefetching) Module(new NLPrefetcher)
else Module(new NullPrefetcher)
io.prefetch <> prefetcher.io.prefetch
val cacheable = edge.manager.supportsAcquireBFast(req.bits.addr, lgCacheBlockBytes.U)
// --------------------
// The MSHR SDQ
val sdq_val = RegInit(0.U(cfg.nSDQ.W))
val sdq_alloc_id = PriorityEncoder(~sdq_val(cfg.nSDQ-1,0))
val sdq_rdy = !sdq_val.andR
val sdq_enq = req.fire && cacheable && isWrite(req.bits.uop.mem_cmd)
val sdq = Mem(cfg.nSDQ, UInt(coreDataBits.W))
when (sdq_enq) {
sdq(sdq_alloc_id) := req.bits.data
}
// --------------------
// The LineBuffer Data
// Holds refilling lines, prefetched lines
val lb = Mem(nLBEntries * cacheDataBeats, UInt(encRowBits.W))
val lb_read_arb = Module(new Arbiter(new LineBufferReadReq, cfg.nMSHRs))
val lb_write_arb = Module(new Arbiter(new LineBufferWriteReq, cfg.nMSHRs))
lb_read_arb.io.out.ready := false.B
lb_write_arb.io.out.ready := true.B
val lb_read_data = WireInit(0.U(encRowBits.W))
when (lb_write_arb.io.out.fire) {
lb.write(lb_write_arb.io.out.bits.lb_addr, lb_write_arb.io.out.bits.data)
} .otherwise {
lb_read_arb.io.out.ready := true.B
when (lb_read_arb.io.out.fire) {
lb_read_data := lb.read(lb_read_arb.io.out.bits.lb_addr)
}
}
def widthMap[T <: Data](f: Int => T) = VecInit((0 until memWidth).map(f))
val idx_matches = Wire(Vec(memWidth, Vec(cfg.nMSHRs, Bool())))
val tag_matches = Wire(Vec(memWidth, Vec(cfg.nMSHRs, Bool())))
val way_matches = Wire(Vec(memWidth, Vec(cfg.nMSHRs, Bool())))
val tag_match = widthMap(w => Mux1H(idx_matches(w), tag_matches(w)))
val idx_match = widthMap(w => idx_matches(w).reduce(_||_))
val way_match = widthMap(w => Mux1H(idx_matches(w), way_matches(w)))
val wb_tag_list = Wire(Vec(cfg.nMSHRs, UInt(tagBits.W)))
val meta_write_arb = Module(new Arbiter(new L1MetaWriteReq , cfg.nMSHRs))
val meta_read_arb = Module(new Arbiter(new L1MetaReadReq , cfg.nMSHRs))
val wb_req_arb = Module(new Arbiter(new WritebackReq(edge.bundle), cfg.nMSHRs))
val replay_arb = Module(new Arbiter(new BoomDCacheReqInternal , cfg.nMSHRs))
val resp_arb = Module(new Arbiter(new BoomDCacheResp , cfg.nMSHRs + nIOMSHRs))
val refill_arb = Module(new Arbiter(new L1DataWriteReq , cfg.nMSHRs))
val commit_vals = Wire(Vec(cfg.nMSHRs, Bool()))
val commit_addrs = Wire(Vec(cfg.nMSHRs, UInt(coreMaxAddrBits.W)))
val commit_cohs = Wire(Vec(cfg.nMSHRs, new ClientMetadata))
var sec_rdy = false.B
io.fence_rdy := true.B
io.probe_rdy := true.B
io.mem_grant.ready := false.B
val mshr_alloc_idx = Wire(UInt())
val pri_rdy = WireInit(false.B)
val pri_val = req.valid && sdq_rdy && cacheable && !idx_match(req_idx)
val mshrs = (0 until cfg.nMSHRs) map { i =>
val mshr = Module(new BoomMSHR)
mshr.io.id := i.U(log2Ceil(cfg.nMSHRs).W)
for (w <- 0 until memWidth) {
idx_matches(w)(i) := mshr.io.idx.valid && mshr.io.idx.bits === io.req(w).bits.addr(untagBits-1,blockOffBits)
tag_matches(w)(i) := mshr.io.tag.valid && mshr.io.tag.bits === io.req(w).bits.addr >> untagBits
way_matches(w)(i) := mshr.io.way.valid && mshr.io.way.bits === io.req(w).bits.way_en
}
wb_tag_list(i) := mshr.io.wb_req.bits.tag
mshr.io.req_pri_val := (i.U === mshr_alloc_idx) && pri_val
when (i.U === mshr_alloc_idx) {
pri_rdy := mshr.io.req_pri_rdy
}
mshr.io.req_sec_val := req.valid && sdq_rdy && tag_match(req_idx) && idx_matches(req_idx)(i) && cacheable
mshr.io.req := req.bits
mshr.io.req_is_probe := req_is_probe
mshr.io.req.sdq_id := sdq_alloc_id
// Clear because of a FENCE, a request to the same idx as a prefetched line,
// a probe to that prefetched line, all mshrs are in use
mshr.io.clear_prefetch := ((io.clear_all && !req.valid)||
(req.valid && idx_matches(req_idx)(i) && cacheable && !tag_match(req_idx)) ||
(req_is_probe && idx_matches(req_idx)(i)))
mshr.io.brupdate := io.brupdate
mshr.io.exception := io.exception
mshr.io.rob_pnr_idx := io.rob_pnr_idx
mshr.io.rob_head_idx := io.rob_head_idx
mshr.io.prober_state := io.prober_state
mshr.io.wb_resp := io.wb_resp
meta_write_arb.io.in(i) <> mshr.io.meta_write
meta_read_arb.io.in(i) <> mshr.io.meta_read
mshr.io.meta_resp := io.meta_resp
wb_req_arb.io.in(i) <> mshr.io.wb_req
replay_arb.io.in(i) <> mshr.io.replay
refill_arb.io.in(i) <> mshr.io.refill
lb_read_arb.io.in(i) <> mshr.io.lb_read
mshr.io.lb_resp := lb_read_data
lb_write_arb.io.in(i) <> mshr.io.lb_write
commit_vals(i) := mshr.io.commit_val
commit_addrs(i) := mshr.io.commit_addr
commit_cohs(i) := mshr.io.commit_coh
mshr.io.mem_grant.valid := false.B
mshr.io.mem_grant.bits := DontCare
when (io.mem_grant.bits.source === i.U) {
mshr.io.mem_grant <> io.mem_grant
}
sec_rdy = sec_rdy || (mshr.io.req_sec_rdy && mshr.io.req_sec_val)
resp_arb.io.in(i) <> mshr.io.resp
when (!mshr.io.req_pri_rdy) {
io.fence_rdy := false.B
}
for (w <- 0 until memWidth) {
when (!mshr.io.probe_rdy && idx_matches(w)(i) && io.req_is_probe(w)) {
io.probe_rdy := false.B
}
}
mshr
}
// Try to round-robin the MSHRs
val mshr_head = RegInit(0.U(log2Ceil(cfg.nMSHRs).W))
mshr_alloc_idx := RegNext(AgePriorityEncoder(mshrs.map(m=>m.io.req_pri_rdy), mshr_head))
when (pri_rdy && pri_val) { mshr_head := WrapInc(mshr_head, cfg.nMSHRs) }
io.meta_write <> meta_write_arb.io.out
io.meta_read <> meta_read_arb.io.out
io.wb_req <> wb_req_arb.io.out
val mmio_alloc_arb = Module(new Arbiter(Bool(), nIOMSHRs))
var mmio_rdy = false.B
val mmios = (0 until nIOMSHRs) map { i =>
val id = cfg.nMSHRs + 1 + i // +1 for wb unit
val mshr = Module(new BoomIOMSHR(id))
mmio_alloc_arb.io.in(i).valid := mshr.io.req.ready
mmio_alloc_arb.io.in(i).bits := DontCare
mshr.io.req.valid := mmio_alloc_arb.io.in(i).ready
mshr.io.req.bits := req.bits
mmio_rdy = mmio_rdy || mshr.io.req.ready
mshr.io.mem_ack.bits := io.mem_grant.bits
mshr.io.mem_ack.valid := io.mem_grant.valid && io.mem_grant.bits.source === id.U
when (io.mem_grant.bits.source === id.U) {
io.mem_grant.ready := true.B
}
resp_arb.io.in(cfg.nMSHRs + i) <> mshr.io.resp
when (!mshr.io.req.ready) {
io.fence_rdy := false.B
}
mshr
}
mmio_alloc_arb.io.out.ready := req.valid && !cacheable
TLArbiter.lowestFromSeq(edge, io.mem_acquire, mshrs.map(_.io.mem_acquire) ++ mmios.map(_.io.mem_access))
TLArbiter.lowestFromSeq(edge, io.mem_finish, mshrs.map(_.io.mem_finish))
val respq = Module(new BranchKillableQueue(new BoomDCacheResp, 4, u => u.uses_ldq, flow = false))
respq.io.brupdate := io.brupdate
respq.io.flush := io.exception
respq.io.enq <> resp_arb.io.out
io.resp <> respq.io.deq
for (w <- 0 until memWidth) {
io.req(w).ready := (w.U === req_idx) &&
Mux(!cacheable, mmio_rdy, sdq_rdy && Mux(idx_match(w), tag_match(w) && sec_rdy, pri_rdy))
io.secondary_miss(w) := idx_match(w) && way_match(w) && !tag_match(w)
io.block_hit(w) := idx_match(w) && tag_match(w)
}
io.refill <> refill_arb.io.out
val free_sdq = io.replay.fire && isWrite(io.replay.bits.uop.mem_cmd)
io.replay <> replay_arb.io.out
io.replay.bits.data := sdq(replay_arb.io.out.bits.sdq_id)
when (io.replay.valid || sdq_enq) {
sdq_val := sdq_val & ~(UIntToOH(replay_arb.io.out.bits.sdq_id) & Fill(cfg.nSDQ, free_sdq)) |
PriorityEncoderOH(~sdq_val(cfg.nSDQ-1,0)) & Fill(cfg.nSDQ, sdq_enq)
}
prefetcher.io.mshr_avail := RegNext(pri_rdy)
prefetcher.io.req_val := RegNext(commit_vals.reduce(_||_))
prefetcher.io.req_addr := RegNext(Mux1H(commit_vals, commit_addrs))
prefetcher.io.req_coh := RegNext(Mux1H(commit_vals, commit_cohs))
}
File Edges.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.util._
class TLEdge(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdgeParameters(client, manager, params, sourceInfo)
{
def isAligned(address: UInt, lgSize: UInt): Bool = {
if (maxLgSize == 0) true.B else {
val mask = UIntToOH1(lgSize, maxLgSize)
(address & mask) === 0.U
}
}
def mask(address: UInt, lgSize: UInt): UInt =
MaskGen(address, lgSize, manager.beatBytes)
def staticHasData(bundle: TLChannel): Option[Boolean] = {
bundle match {
case _:TLBundleA => {
// Do there exist A messages with Data?
val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial
// Do there exist A messages without Data?
val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint
// Statically optimize the case where hasData is a constant
if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None
}
case _:TLBundleB => {
// Do there exist B messages with Data?
val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial
// Do there exist B messages without Data?
val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint
// Statically optimize the case where hasData is a constant
if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None
}
case _:TLBundleC => {
// Do there eixst C messages with Data?
val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe
// Do there exist C messages without Data?
val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe
if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None
}
case _:TLBundleD => {
// Do there eixst D messages with Data?
val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB
// Do there exist D messages without Data?
val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT
if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None
}
case _:TLBundleE => Some(false)
}
}
def isRequest(x: TLChannel): Bool = {
x match {
case a: TLBundleA => true.B
case b: TLBundleB => true.B
case c: TLBundleC => c.opcode(2) && c.opcode(1)
// opcode === TLMessages.Release ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(2) && !d.opcode(1)
// opcode === TLMessages.Grant ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
}
def isResponse(x: TLChannel): Bool = {
x match {
case a: TLBundleA => false.B
case b: TLBundleB => false.B
case c: TLBundleC => !c.opcode(2) || !c.opcode(1)
// opcode =/= TLMessages.Release &&
// opcode =/= TLMessages.ReleaseData
case d: TLBundleD => true.B // Grant isResponse + isRequest
case e: TLBundleE => true.B
}
}
def hasData(x: TLChannel): Bool = {
val opdata = x match {
case a: TLBundleA => !a.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case b: TLBundleB => !b.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case c: TLBundleC => c.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.ProbeAckData ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
staticHasData(x).map(_.B).getOrElse(opdata)
}
def opcode(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.opcode
case b: TLBundleB => b.opcode
case c: TLBundleC => c.opcode
case d: TLBundleD => d.opcode
}
}
def param(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.param
case b: TLBundleB => b.param
case c: TLBundleC => c.param
case d: TLBundleD => d.param
}
}
def size(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.size
case b: TLBundleB => b.size
case c: TLBundleC => c.size
case d: TLBundleD => d.size
}
}
def data(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.data
case b: TLBundleB => b.data
case c: TLBundleC => c.data
case d: TLBundleD => d.data
}
}
def corrupt(x: TLDataChannel): Bool = {
x match {
case a: TLBundleA => a.corrupt
case b: TLBundleB => b.corrupt
case c: TLBundleC => c.corrupt
case d: TLBundleD => d.corrupt
}
}
def mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.mask
case b: TLBundleB => b.mask
case c: TLBundleC => mask(c.address, c.size)
}
}
def full_mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => mask(a.address, a.size)
case b: TLBundleB => mask(b.address, b.size)
case c: TLBundleC => mask(c.address, c.size)
}
}
def address(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.address
case b: TLBundleB => b.address
case c: TLBundleC => c.address
}
}
def source(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.source
case b: TLBundleB => b.source
case c: TLBundleC => c.source
case d: TLBundleD => d.source
}
}
def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes)
def addr_lo(x: UInt): UInt =
if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0)
def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x))
def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x))
def numBeats(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 1.U
case bundle: TLDataChannel => {
val hasData = this.hasData(bundle)
val size = this.size(bundle)
val cutoff = log2Ceil(manager.beatBytes)
val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U
val decode = UIntToOH(size, maxLgSize+1) >> cutoff
Mux(hasData, decode | small.asUInt, 1.U)
}
}
}
def numBeats1(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 0.U
case bundle: TLDataChannel => {
if (maxLgSize == 0) {
0.U
} else {
val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes)
Mux(hasData(bundle), decode, 0.U)
}
}
}
}
def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val beats1 = numBeats1(bits)
val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W))
val counter1 = counter - 1.U
val first = counter === 0.U
val last = counter === 1.U || beats1 === 0.U
val done = last && fire
val count = (beats1 & ~counter1)
when (fire) {
counter := Mux(first, beats1, counter1)
}
(first, last, done, count)
}
def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1
def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire)
def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid)
def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2
def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire)
def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid)
def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3
def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire)
def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid)
def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3)
}
def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire)
def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid)
def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4)
}
def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire)
def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid)
def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes))
}
def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire)
def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid)
// Does the request need T permissions to be executed?
def needT(a: TLBundleA): Bool = {
val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLPermissions.NtoB -> false.B,
TLPermissions.NtoT -> true.B,
TLPermissions.BtoT -> true.B))
MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array(
TLMessages.PutFullData -> true.B,
TLMessages.PutPartialData -> true.B,
TLMessages.ArithmeticData -> true.B,
TLMessages.LogicalData -> true.B,
TLMessages.Get -> false.B,
TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLHints.PREFETCH_READ -> false.B,
TLHints.PREFETCH_WRITE -> true.B)),
TLMessages.AcquireBlock -> acq_needT,
TLMessages.AcquirePerm -> acq_needT))
}
// This is a very expensive circuit; use only if you really mean it!
def inFlight(x: TLBundle): (UInt, UInt) = {
val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W))
val bce = manager.anySupportAcquireB && client.anySupportProbe
val (a_first, a_last, _) = firstlast(x.a)
val (b_first, b_last, _) = firstlast(x.b)
val (c_first, c_last, _) = firstlast(x.c)
val (d_first, d_last, _) = firstlast(x.d)
val (e_first, e_last, _) = firstlast(x.e)
val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits))
val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits))
val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits))
val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits))
val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits))
val a_inc = x.a.fire && a_first && a_request
val b_inc = x.b.fire && b_first && b_request
val c_inc = x.c.fire && c_first && c_request
val d_inc = x.d.fire && d_first && d_request
val e_inc = x.e.fire && e_first && e_request
val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil))
val a_dec = x.a.fire && a_last && a_response
val b_dec = x.b.fire && b_last && b_response
val c_dec = x.c.fire && c_last && c_response
val d_dec = x.d.fire && d_last && d_response
val e_dec = x.e.fire && e_last && e_response
val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil))
val next_flight = flight + PopCount(inc) - PopCount(dec)
flight := next_flight
(flight, next_flight)
}
def prettySourceMapping(context: String): String = {
s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n"
}
}
class TLEdgeOut(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
// Transfers
def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquireBlock
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquirePerm
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.Release
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ReleaseData
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) =
Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B)
def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAck
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions, data)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAckData
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B)
def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink)
def GrantAck(toSink: UInt): TLBundleE = {
val e = Wire(new TLBundleE(bundle))
e.sink := toSink
e
}
// Accesses
def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsGetFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Get
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutFullFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutFullData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, mask, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutPartialFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutPartialData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = {
require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsArithmeticFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.ArithmeticData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsLogicalFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.LogicalData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = {
require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsHintFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Hint
a.param := param
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data)
def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAckData
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size)
def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.HintAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
}
class TLEdgeIn(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = {
val todo = x.filter(!_.isEmpty)
val heads = todo.map(_.head)
val tails = todo.map(_.tail)
if (todo.isEmpty) Nil else { heads +: myTranspose(tails) }
}
// Transfers
def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = {
require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}")
val legal = client.supportsProbe(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Probe
b.param := capPermissions
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.Grant
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.GrantData
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B)
def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.ReleaseAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
// Accesses
def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = {
require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsGet(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Get
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsPutFull(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutFullData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, mask, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsPutPartial(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutPartialData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsArithmetic(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.ArithmeticData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsLogical(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.LogicalData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = {
require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsHint(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Hint
b.param := param
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size)
def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied)
def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data)
def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAckData
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B)
def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied)
def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B)
def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.HintAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
}
File AMOALU.scala:
// See LICENSE.SiFive for license details.
// See LICENSE.Berkeley for license details.
package freechips.rocketchip.rocket
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.Parameters
class StoreGen(typ: UInt, addr: UInt, dat: UInt, maxSize: Int) {
val size = Wire(UInt(log2Up(log2Up(maxSize)+1).W))
size := typ
val dat_padded = dat.pad(maxSize*8)
def misaligned: Bool =
(addr & ((1.U << size) - 1.U)(log2Up(maxSize)-1,0)).orR
def mask = {
var res = 1.U
for (i <- 0 until log2Up(maxSize)) {
val upper = Mux(addr(i), res, 0.U) | Mux(size >= (i+1).U, ((BigInt(1) << (1 << i))-1).U, 0.U)
val lower = Mux(addr(i), 0.U, res)
res = Cat(upper, lower)
}
res
}
protected def genData(i: Int): UInt =
if (i >= log2Up(maxSize)) dat_padded
else Mux(size === i.U, Fill(1 << (log2Up(maxSize)-i), dat_padded((8 << i)-1,0)), genData(i+1))
def data = genData(0)
def wordData = genData(2)
}
class LoadGen(typ: UInt, signed: Bool, addr: UInt, dat: UInt, zero: Bool, maxSize: Int) {
private val size = new StoreGen(typ, addr, dat, maxSize).size
private def genData(logMinSize: Int): UInt = {
var res = dat
for (i <- log2Up(maxSize)-1 to logMinSize by -1) {
val pos = 8 << i
val shifted = Mux(addr(i), res(2*pos-1,pos), res(pos-1,0))
val doZero = (i == 0).B && zero
val zeroed = Mux(doZero, 0.U, shifted)
res = Cat(Mux(size === i.U || doZero, Fill(8*maxSize-pos, signed && zeroed(pos-1)), res(8*maxSize-1,pos)), zeroed)
}
res
}
def wordData = genData(2)
def data = genData(0)
}
class AMOALU(operandBits: Int)(implicit p: Parameters) extends Module {
val minXLen = 32
val widths = (0 to log2Ceil(operandBits / minXLen)).map(minXLen << _)
val io = IO(new Bundle {
val mask = Input(UInt((operandBits / 8).W))
val cmd = Input(UInt(M_SZ.W))
val lhs = Input(UInt(operandBits.W))
val rhs = Input(UInt(operandBits.W))
val out = Output(UInt(operandBits.W))
val out_unmasked = Output(UInt(operandBits.W))
})
val max = io.cmd === M_XA_MAX || io.cmd === M_XA_MAXU
val min = io.cmd === M_XA_MIN || io.cmd === M_XA_MINU
val add = io.cmd === M_XA_ADD
val logic_and = io.cmd === M_XA_OR || io.cmd === M_XA_AND
val logic_xor = io.cmd === M_XA_XOR || io.cmd === M_XA_OR
val adder_out = {
// partition the carry chain to support sub-xLen addition
val mask = ~(0.U(operandBits.W) +: widths.init.map(w => !io.mask(w/8-1) << (w-1))).reduce(_|_)
(io.lhs & mask) + (io.rhs & mask)
}
val less = {
// break up the comparator so the lower parts will be CSE'd
def isLessUnsigned(x: UInt, y: UInt, n: Int): Bool = {
if (n == minXLen) x(n-1, 0) < y(n-1, 0)
else x(n-1, n/2) < y(n-1, n/2) || x(n-1, n/2) === y(n-1, n/2) && isLessUnsigned(x, y, n/2)
}
def isLess(x: UInt, y: UInt, n: Int): Bool = {
val signed = {
val mask = M_XA_MIN ^ M_XA_MINU
(io.cmd & mask) === (M_XA_MIN & mask)
}
Mux(x(n-1) === y(n-1), isLessUnsigned(x, y, n), Mux(signed, x(n-1), y(n-1)))
}
PriorityMux(widths.reverse.map(w => (io.mask(w/8/2), isLess(io.lhs, io.rhs, w))))
}
val minmax = Mux(Mux(less, min, max), io.lhs, io.rhs)
val logic =
Mux(logic_and, io.lhs & io.rhs, 0.U) |
Mux(logic_xor, io.lhs ^ io.rhs, 0.U)
val out =
Mux(add, adder_out,
Mux(logic_and || logic_xor, logic,
minmax))
val wmask = FillInterleaved(8, io.mask)
io.out := wmask & out | ~wmask & io.lhs
io.out_unmasked := out
}
| module BoomMSHR_10( // @[mshrs.scala:36:7]
input clock, // @[mshrs.scala:36:7]
input reset, // @[mshrs.scala:36:7]
input io_req_pri_val, // @[mshrs.scala:39:14]
output io_req_pri_rdy, // @[mshrs.scala:39:14]
input io_req_sec_val, // @[mshrs.scala:39:14]
output io_req_sec_rdy, // @[mshrs.scala:39:14]
input io_clear_prefetch, // @[mshrs.scala:39:14]
input [5:0] io_rob_pnr_idx, // @[mshrs.scala:39:14]
input [5:0] io_rob_head_idx, // @[mshrs.scala:39:14]
input [6:0] io_req_uop_uopc, // @[mshrs.scala:39:14]
input [31:0] io_req_uop_inst, // @[mshrs.scala:39:14]
input [31:0] io_req_uop_debug_inst, // @[mshrs.scala:39:14]
input io_req_uop_is_rvc, // @[mshrs.scala:39:14]
input [33:0] io_req_uop_debug_pc, // @[mshrs.scala:39:14]
input [2:0] io_req_uop_iq_type, // @[mshrs.scala:39:14]
input [9:0] io_req_uop_fu_code, // @[mshrs.scala:39:14]
input [3:0] io_req_uop_ctrl_br_type, // @[mshrs.scala:39:14]
input [1:0] io_req_uop_ctrl_op1_sel, // @[mshrs.scala:39:14]
input [2:0] io_req_uop_ctrl_op2_sel, // @[mshrs.scala:39:14]
input [2:0] io_req_uop_ctrl_imm_sel, // @[mshrs.scala:39:14]
input [4:0] io_req_uop_ctrl_op_fcn, // @[mshrs.scala:39:14]
input io_req_uop_ctrl_fcn_dw, // @[mshrs.scala:39:14]
input [2:0] io_req_uop_ctrl_csr_cmd, // @[mshrs.scala:39:14]
input io_req_uop_ctrl_is_load, // @[mshrs.scala:39:14]
input io_req_uop_ctrl_is_sta, // @[mshrs.scala:39:14]
input io_req_uop_ctrl_is_std, // @[mshrs.scala:39:14]
input [1:0] io_req_uop_iw_state, // @[mshrs.scala:39:14]
input io_req_uop_iw_p1_poisoned, // @[mshrs.scala:39:14]
input io_req_uop_iw_p2_poisoned, // @[mshrs.scala:39:14]
input io_req_uop_is_br, // @[mshrs.scala:39:14]
input io_req_uop_is_jalr, // @[mshrs.scala:39:14]
input io_req_uop_is_jal, // @[mshrs.scala:39:14]
input io_req_uop_is_sfb, // @[mshrs.scala:39:14]
input [3:0] io_req_uop_br_mask, // @[mshrs.scala:39:14]
input [1:0] io_req_uop_br_tag, // @[mshrs.scala:39:14]
input [3:0] io_req_uop_ftq_idx, // @[mshrs.scala:39:14]
input io_req_uop_edge_inst, // @[mshrs.scala:39:14]
input [5:0] io_req_uop_pc_lob, // @[mshrs.scala:39:14]
input io_req_uop_taken, // @[mshrs.scala:39:14]
input [19:0] io_req_uop_imm_packed, // @[mshrs.scala:39:14]
input [11:0] io_req_uop_csr_addr, // @[mshrs.scala:39:14]
input [5:0] io_req_uop_rob_idx, // @[mshrs.scala:39:14]
input [3:0] io_req_uop_ldq_idx, // @[mshrs.scala:39:14]
input [3:0] io_req_uop_stq_idx, // @[mshrs.scala:39:14]
input [1:0] io_req_uop_rxq_idx, // @[mshrs.scala:39:14]
input [6:0] io_req_uop_pdst, // @[mshrs.scala:39:14]
input [6:0] io_req_uop_prs1, // @[mshrs.scala:39:14]
input [6:0] io_req_uop_prs2, // @[mshrs.scala:39:14]
input [6:0] io_req_uop_prs3, // @[mshrs.scala:39:14]
input [3:0] io_req_uop_ppred, // @[mshrs.scala:39:14]
input io_req_uop_prs1_busy, // @[mshrs.scala:39:14]
input io_req_uop_prs2_busy, // @[mshrs.scala:39:14]
input io_req_uop_prs3_busy, // @[mshrs.scala:39:14]
input io_req_uop_ppred_busy, // @[mshrs.scala:39:14]
input [6:0] io_req_uop_stale_pdst, // @[mshrs.scala:39:14]
input io_req_uop_exception, // @[mshrs.scala:39:14]
input [63:0] io_req_uop_exc_cause, // @[mshrs.scala:39:14]
input io_req_uop_bypassable, // @[mshrs.scala:39:14]
input [4:0] io_req_uop_mem_cmd, // @[mshrs.scala:39:14]
input [1:0] io_req_uop_mem_size, // @[mshrs.scala:39:14]
input io_req_uop_mem_signed, // @[mshrs.scala:39:14]
input io_req_uop_is_fence, // @[mshrs.scala:39:14]
input io_req_uop_is_fencei, // @[mshrs.scala:39:14]
input io_req_uop_is_amo, // @[mshrs.scala:39:14]
input io_req_uop_uses_ldq, // @[mshrs.scala:39:14]
input io_req_uop_uses_stq, // @[mshrs.scala:39:14]
input io_req_uop_is_sys_pc2epc, // @[mshrs.scala:39:14]
input io_req_uop_is_unique, // @[mshrs.scala:39:14]
input io_req_uop_flush_on_commit, // @[mshrs.scala:39:14]
input io_req_uop_ldst_is_rs1, // @[mshrs.scala:39:14]
input [5:0] io_req_uop_ldst, // @[mshrs.scala:39:14]
input [5:0] io_req_uop_lrs1, // @[mshrs.scala:39:14]
input [5:0] io_req_uop_lrs2, // @[mshrs.scala:39:14]
input [5:0] io_req_uop_lrs3, // @[mshrs.scala:39:14]
input io_req_uop_ldst_val, // @[mshrs.scala:39:14]
input [1:0] io_req_uop_dst_rtype, // @[mshrs.scala:39:14]
input [1:0] io_req_uop_lrs1_rtype, // @[mshrs.scala:39:14]
input [1:0] io_req_uop_lrs2_rtype, // @[mshrs.scala:39:14]
input io_req_uop_frs3_en, // @[mshrs.scala:39:14]
input io_req_uop_fp_val, // @[mshrs.scala:39:14]
input io_req_uop_fp_single, // @[mshrs.scala:39:14]
input io_req_uop_xcpt_pf_if, // @[mshrs.scala:39:14]
input io_req_uop_xcpt_ae_if, // @[mshrs.scala:39:14]
input io_req_uop_xcpt_ma_if, // @[mshrs.scala:39:14]
input io_req_uop_bp_debug_if, // @[mshrs.scala:39:14]
input io_req_uop_bp_xcpt_if, // @[mshrs.scala:39:14]
input [1:0] io_req_uop_debug_fsrc, // @[mshrs.scala:39:14]
input [1:0] io_req_uop_debug_tsrc, // @[mshrs.scala:39:14]
input [33:0] io_req_addr, // @[mshrs.scala:39:14]
input [63:0] io_req_data, // @[mshrs.scala:39:14]
input io_req_is_hella, // @[mshrs.scala:39:14]
input io_req_tag_match, // @[mshrs.scala:39:14]
input [1:0] io_req_old_meta_coh_state, // @[mshrs.scala:39:14]
input [21:0] io_req_old_meta_tag, // @[mshrs.scala:39:14]
input [1:0] io_req_way_en, // @[mshrs.scala:39:14]
input [4:0] io_req_sdq_id, // @[mshrs.scala:39:14]
input io_req_is_probe, // @[mshrs.scala:39:14]
output io_idx_valid, // @[mshrs.scala:39:14]
output [3:0] io_idx_bits, // @[mshrs.scala:39:14]
output io_way_valid, // @[mshrs.scala:39:14]
output [1:0] io_way_bits, // @[mshrs.scala:39:14]
output io_tag_valid, // @[mshrs.scala:39:14]
output [23:0] io_tag_bits, // @[mshrs.scala:39:14]
input io_mem_acquire_ready, // @[mshrs.scala:39:14]
output io_mem_acquire_valid, // @[mshrs.scala:39:14]
output [2:0] io_mem_acquire_bits_param, // @[mshrs.scala:39:14]
output [31:0] io_mem_acquire_bits_address, // @[mshrs.scala:39:14]
output io_mem_grant_ready, // @[mshrs.scala:39:14]
input io_mem_grant_valid, // @[mshrs.scala:39:14]
input [2:0] io_mem_grant_bits_opcode, // @[mshrs.scala:39:14]
input [1:0] io_mem_grant_bits_param, // @[mshrs.scala:39:14]
input [3:0] io_mem_grant_bits_size, // @[mshrs.scala:39:14]
input [3:0] io_mem_grant_bits_source, // @[mshrs.scala:39:14]
input [2:0] io_mem_grant_bits_sink, // @[mshrs.scala:39:14]
input io_mem_grant_bits_denied, // @[mshrs.scala:39:14]
input [63:0] io_mem_grant_bits_data, // @[mshrs.scala:39:14]
input io_mem_grant_bits_corrupt, // @[mshrs.scala:39:14]
input io_mem_finish_ready, // @[mshrs.scala:39:14]
output io_mem_finish_valid, // @[mshrs.scala:39:14]
output [2:0] io_mem_finish_bits_sink, // @[mshrs.scala:39:14]
input io_prober_state_valid, // @[mshrs.scala:39:14]
input [33:0] io_prober_state_bits, // @[mshrs.scala:39:14]
input io_refill_ready, // @[mshrs.scala:39:14]
output io_refill_valid, // @[mshrs.scala:39:14]
output [1:0] io_refill_bits_way_en, // @[mshrs.scala:39:14]
output [9:0] io_refill_bits_addr, // @[mshrs.scala:39:14]
output [63:0] io_refill_bits_data, // @[mshrs.scala:39:14]
input io_meta_write_ready, // @[mshrs.scala:39:14]
output io_meta_write_valid, // @[mshrs.scala:39:14]
output [3:0] io_meta_write_bits_idx, // @[mshrs.scala:39:14]
output [1:0] io_meta_write_bits_way_en, // @[mshrs.scala:39:14]
output [1:0] io_meta_write_bits_data_coh_state, // @[mshrs.scala:39:14]
output [21:0] io_meta_write_bits_data_tag, // @[mshrs.scala:39:14]
input io_meta_read_ready, // @[mshrs.scala:39:14]
output io_meta_read_valid, // @[mshrs.scala:39:14]
output [3:0] io_meta_read_bits_idx, // @[mshrs.scala:39:14]
output [1:0] io_meta_read_bits_way_en, // @[mshrs.scala:39:14]
output [21:0] io_meta_read_bits_tag, // @[mshrs.scala:39:14]
input io_meta_resp_valid, // @[mshrs.scala:39:14]
input [1:0] io_meta_resp_bits_coh_state, // @[mshrs.scala:39:14]
input [21:0] io_meta_resp_bits_tag, // @[mshrs.scala:39:14]
input io_wb_req_ready, // @[mshrs.scala:39:14]
output io_wb_req_valid, // @[mshrs.scala:39:14]
output [21:0] io_wb_req_bits_tag, // @[mshrs.scala:39:14]
output [3:0] io_wb_req_bits_idx, // @[mshrs.scala:39:14]
output [2:0] io_wb_req_bits_param, // @[mshrs.scala:39:14]
output [1:0] io_wb_req_bits_way_en, // @[mshrs.scala:39:14]
output io_commit_val, // @[mshrs.scala:39:14]
output [33:0] io_commit_addr, // @[mshrs.scala:39:14]
output [1:0] io_commit_coh_state, // @[mshrs.scala:39:14]
input io_lb_read_ready, // @[mshrs.scala:39:14]
output io_lb_read_valid, // @[mshrs.scala:39:14]
output [2:0] io_lb_read_bits_offset, // @[mshrs.scala:39:14]
input [63:0] io_lb_resp, // @[mshrs.scala:39:14]
input io_lb_write_ready, // @[mshrs.scala:39:14]
output io_lb_write_valid, // @[mshrs.scala:39:14]
output [2:0] io_lb_write_bits_offset, // @[mshrs.scala:39:14]
output [63:0] io_lb_write_bits_data, // @[mshrs.scala:39:14]
input io_replay_ready, // @[mshrs.scala:39:14]
output io_replay_valid, // @[mshrs.scala:39:14]
output [6:0] io_replay_bits_uop_uopc, // @[mshrs.scala:39:14]
output [31:0] io_replay_bits_uop_inst, // @[mshrs.scala:39:14]
output [31:0] io_replay_bits_uop_debug_inst, // @[mshrs.scala:39:14]
output io_replay_bits_uop_is_rvc, // @[mshrs.scala:39:14]
output [33:0] io_replay_bits_uop_debug_pc, // @[mshrs.scala:39:14]
output [2:0] io_replay_bits_uop_iq_type, // @[mshrs.scala:39:14]
output [9:0] io_replay_bits_uop_fu_code, // @[mshrs.scala:39:14]
output [3:0] io_replay_bits_uop_ctrl_br_type, // @[mshrs.scala:39:14]
output [1:0] io_replay_bits_uop_ctrl_op1_sel, // @[mshrs.scala:39:14]
output [2:0] io_replay_bits_uop_ctrl_op2_sel, // @[mshrs.scala:39:14]
output [2:0] io_replay_bits_uop_ctrl_imm_sel, // @[mshrs.scala:39:14]
output [4:0] io_replay_bits_uop_ctrl_op_fcn, // @[mshrs.scala:39:14]
output io_replay_bits_uop_ctrl_fcn_dw, // @[mshrs.scala:39:14]
output [2:0] io_replay_bits_uop_ctrl_csr_cmd, // @[mshrs.scala:39:14]
output io_replay_bits_uop_ctrl_is_load, // @[mshrs.scala:39:14]
output io_replay_bits_uop_ctrl_is_sta, // @[mshrs.scala:39:14]
output io_replay_bits_uop_ctrl_is_std, // @[mshrs.scala:39:14]
output [1:0] io_replay_bits_uop_iw_state, // @[mshrs.scala:39:14]
output io_replay_bits_uop_iw_p1_poisoned, // @[mshrs.scala:39:14]
output io_replay_bits_uop_iw_p2_poisoned, // @[mshrs.scala:39:14]
output io_replay_bits_uop_is_br, // @[mshrs.scala:39:14]
output io_replay_bits_uop_is_jalr, // @[mshrs.scala:39:14]
output io_replay_bits_uop_is_jal, // @[mshrs.scala:39:14]
output io_replay_bits_uop_is_sfb, // @[mshrs.scala:39:14]
output [3:0] io_replay_bits_uop_br_mask, // @[mshrs.scala:39:14]
output [1:0] io_replay_bits_uop_br_tag, // @[mshrs.scala:39:14]
output [3:0] io_replay_bits_uop_ftq_idx, // @[mshrs.scala:39:14]
output io_replay_bits_uop_edge_inst, // @[mshrs.scala:39:14]
output [5:0] io_replay_bits_uop_pc_lob, // @[mshrs.scala:39:14]
output io_replay_bits_uop_taken, // @[mshrs.scala:39:14]
output [19:0] io_replay_bits_uop_imm_packed, // @[mshrs.scala:39:14]
output [11:0] io_replay_bits_uop_csr_addr, // @[mshrs.scala:39:14]
output [5:0] io_replay_bits_uop_rob_idx, // @[mshrs.scala:39:14]
output [3:0] io_replay_bits_uop_ldq_idx, // @[mshrs.scala:39:14]
output [3:0] io_replay_bits_uop_stq_idx, // @[mshrs.scala:39:14]
output [1:0] io_replay_bits_uop_rxq_idx, // @[mshrs.scala:39:14]
output [6:0] io_replay_bits_uop_pdst, // @[mshrs.scala:39:14]
output [6:0] io_replay_bits_uop_prs1, // @[mshrs.scala:39:14]
output [6:0] io_replay_bits_uop_prs2, // @[mshrs.scala:39:14]
output [6:0] io_replay_bits_uop_prs3, // @[mshrs.scala:39:14]
output [3:0] io_replay_bits_uop_ppred, // @[mshrs.scala:39:14]
output io_replay_bits_uop_prs1_busy, // @[mshrs.scala:39:14]
output io_replay_bits_uop_prs2_busy, // @[mshrs.scala:39:14]
output io_replay_bits_uop_prs3_busy, // @[mshrs.scala:39:14]
output io_replay_bits_uop_ppred_busy, // @[mshrs.scala:39:14]
output [6:0] io_replay_bits_uop_stale_pdst, // @[mshrs.scala:39:14]
output io_replay_bits_uop_exception, // @[mshrs.scala:39:14]
output [63:0] io_replay_bits_uop_exc_cause, // @[mshrs.scala:39:14]
output io_replay_bits_uop_bypassable, // @[mshrs.scala:39:14]
output [4:0] io_replay_bits_uop_mem_cmd, // @[mshrs.scala:39:14]
output [1:0] io_replay_bits_uop_mem_size, // @[mshrs.scala:39:14]
output io_replay_bits_uop_mem_signed, // @[mshrs.scala:39:14]
output io_replay_bits_uop_is_fence, // @[mshrs.scala:39:14]
output io_replay_bits_uop_is_fencei, // @[mshrs.scala:39:14]
output io_replay_bits_uop_is_amo, // @[mshrs.scala:39:14]
output io_replay_bits_uop_uses_ldq, // @[mshrs.scala:39:14]
output io_replay_bits_uop_uses_stq, // @[mshrs.scala:39:14]
output io_replay_bits_uop_is_sys_pc2epc, // @[mshrs.scala:39:14]
output io_replay_bits_uop_is_unique, // @[mshrs.scala:39:14]
output io_replay_bits_uop_flush_on_commit, // @[mshrs.scala:39:14]
output io_replay_bits_uop_ldst_is_rs1, // @[mshrs.scala:39:14]
output [5:0] io_replay_bits_uop_ldst, // @[mshrs.scala:39:14]
output [5:0] io_replay_bits_uop_lrs1, // @[mshrs.scala:39:14]
output [5:0] io_replay_bits_uop_lrs2, // @[mshrs.scala:39:14]
output [5:0] io_replay_bits_uop_lrs3, // @[mshrs.scala:39:14]
output io_replay_bits_uop_ldst_val, // @[mshrs.scala:39:14]
output [1:0] io_replay_bits_uop_dst_rtype, // @[mshrs.scala:39:14]
output [1:0] io_replay_bits_uop_lrs1_rtype, // @[mshrs.scala:39:14]
output [1:0] io_replay_bits_uop_lrs2_rtype, // @[mshrs.scala:39:14]
output io_replay_bits_uop_frs3_en, // @[mshrs.scala:39:14]
output io_replay_bits_uop_fp_val, // @[mshrs.scala:39:14]
output io_replay_bits_uop_fp_single, // @[mshrs.scala:39:14]
output io_replay_bits_uop_xcpt_pf_if, // @[mshrs.scala:39:14]
output io_replay_bits_uop_xcpt_ae_if, // @[mshrs.scala:39:14]
output io_replay_bits_uop_xcpt_ma_if, // @[mshrs.scala:39:14]
output io_replay_bits_uop_bp_debug_if, // @[mshrs.scala:39:14]
output io_replay_bits_uop_bp_xcpt_if, // @[mshrs.scala:39:14]
output [1:0] io_replay_bits_uop_debug_fsrc, // @[mshrs.scala:39:14]
output [1:0] io_replay_bits_uop_debug_tsrc, // @[mshrs.scala:39:14]
output [33:0] io_replay_bits_addr, // @[mshrs.scala:39:14]
output [63:0] io_replay_bits_data, // @[mshrs.scala:39:14]
output io_replay_bits_is_hella, // @[mshrs.scala:39:14]
output io_replay_bits_tag_match, // @[mshrs.scala:39:14]
output [1:0] io_replay_bits_old_meta_coh_state, // @[mshrs.scala:39:14]
output [21:0] io_replay_bits_old_meta_tag, // @[mshrs.scala:39:14]
output [1:0] io_replay_bits_way_en, // @[mshrs.scala:39:14]
output [4:0] io_replay_bits_sdq_id, // @[mshrs.scala:39:14]
input io_resp_ready, // @[mshrs.scala:39:14]
output io_resp_valid, // @[mshrs.scala:39:14]
output [6:0] io_resp_bits_uop_uopc, // @[mshrs.scala:39:14]
output [31:0] io_resp_bits_uop_inst, // @[mshrs.scala:39:14]
output [31:0] io_resp_bits_uop_debug_inst, // @[mshrs.scala:39:14]
output io_resp_bits_uop_is_rvc, // @[mshrs.scala:39:14]
output [33:0] io_resp_bits_uop_debug_pc, // @[mshrs.scala:39:14]
output [2:0] io_resp_bits_uop_iq_type, // @[mshrs.scala:39:14]
output [9:0] io_resp_bits_uop_fu_code, // @[mshrs.scala:39:14]
output [3:0] io_resp_bits_uop_ctrl_br_type, // @[mshrs.scala:39:14]
output [1:0] io_resp_bits_uop_ctrl_op1_sel, // @[mshrs.scala:39:14]
output [2:0] io_resp_bits_uop_ctrl_op2_sel, // @[mshrs.scala:39:14]
output [2:0] io_resp_bits_uop_ctrl_imm_sel, // @[mshrs.scala:39:14]
output [4:0] io_resp_bits_uop_ctrl_op_fcn, // @[mshrs.scala:39:14]
output io_resp_bits_uop_ctrl_fcn_dw, // @[mshrs.scala:39:14]
output [2:0] io_resp_bits_uop_ctrl_csr_cmd, // @[mshrs.scala:39:14]
output io_resp_bits_uop_ctrl_is_load, // @[mshrs.scala:39:14]
output io_resp_bits_uop_ctrl_is_sta, // @[mshrs.scala:39:14]
output io_resp_bits_uop_ctrl_is_std, // @[mshrs.scala:39:14]
output [1:0] io_resp_bits_uop_iw_state, // @[mshrs.scala:39:14]
output io_resp_bits_uop_iw_p1_poisoned, // @[mshrs.scala:39:14]
output io_resp_bits_uop_iw_p2_poisoned, // @[mshrs.scala:39:14]
output io_resp_bits_uop_is_br, // @[mshrs.scala:39:14]
output io_resp_bits_uop_is_jalr, // @[mshrs.scala:39:14]
output io_resp_bits_uop_is_jal, // @[mshrs.scala:39:14]
output io_resp_bits_uop_is_sfb, // @[mshrs.scala:39:14]
output [3:0] io_resp_bits_uop_br_mask, // @[mshrs.scala:39:14]
output [1:0] io_resp_bits_uop_br_tag, // @[mshrs.scala:39:14]
output [3:0] io_resp_bits_uop_ftq_idx, // @[mshrs.scala:39:14]
output io_resp_bits_uop_edge_inst, // @[mshrs.scala:39:14]
output [5:0] io_resp_bits_uop_pc_lob, // @[mshrs.scala:39:14]
output io_resp_bits_uop_taken, // @[mshrs.scala:39:14]
output [19:0] io_resp_bits_uop_imm_packed, // @[mshrs.scala:39:14]
output [11:0] io_resp_bits_uop_csr_addr, // @[mshrs.scala:39:14]
output [5:0] io_resp_bits_uop_rob_idx, // @[mshrs.scala:39:14]
output [3:0] io_resp_bits_uop_ldq_idx, // @[mshrs.scala:39:14]
output [3:0] io_resp_bits_uop_stq_idx, // @[mshrs.scala:39:14]
output [1:0] io_resp_bits_uop_rxq_idx, // @[mshrs.scala:39:14]
output [6:0] io_resp_bits_uop_pdst, // @[mshrs.scala:39:14]
output [6:0] io_resp_bits_uop_prs1, // @[mshrs.scala:39:14]
output [6:0] io_resp_bits_uop_prs2, // @[mshrs.scala:39:14]
output [6:0] io_resp_bits_uop_prs3, // @[mshrs.scala:39:14]
output [3:0] io_resp_bits_uop_ppred, // @[mshrs.scala:39:14]
output io_resp_bits_uop_prs1_busy, // @[mshrs.scala:39:14]
output io_resp_bits_uop_prs2_busy, // @[mshrs.scala:39:14]
output io_resp_bits_uop_prs3_busy, // @[mshrs.scala:39:14]
output io_resp_bits_uop_ppred_busy, // @[mshrs.scala:39:14]
output [6:0] io_resp_bits_uop_stale_pdst, // @[mshrs.scala:39:14]
output io_resp_bits_uop_exception, // @[mshrs.scala:39:14]
output [63:0] io_resp_bits_uop_exc_cause, // @[mshrs.scala:39:14]
output io_resp_bits_uop_bypassable, // @[mshrs.scala:39:14]
output [4:0] io_resp_bits_uop_mem_cmd, // @[mshrs.scala:39:14]
output [1:0] io_resp_bits_uop_mem_size, // @[mshrs.scala:39:14]
output io_resp_bits_uop_mem_signed, // @[mshrs.scala:39:14]
output io_resp_bits_uop_is_fence, // @[mshrs.scala:39:14]
output io_resp_bits_uop_is_fencei, // @[mshrs.scala:39:14]
output io_resp_bits_uop_is_amo, // @[mshrs.scala:39:14]
output io_resp_bits_uop_uses_ldq, // @[mshrs.scala:39:14]
output io_resp_bits_uop_uses_stq, // @[mshrs.scala:39:14]
output io_resp_bits_uop_is_sys_pc2epc, // @[mshrs.scala:39:14]
output io_resp_bits_uop_is_unique, // @[mshrs.scala:39:14]
output io_resp_bits_uop_flush_on_commit, // @[mshrs.scala:39:14]
output io_resp_bits_uop_ldst_is_rs1, // @[mshrs.scala:39:14]
output [5:0] io_resp_bits_uop_ldst, // @[mshrs.scala:39:14]
output [5:0] io_resp_bits_uop_lrs1, // @[mshrs.scala:39:14]
output [5:0] io_resp_bits_uop_lrs2, // @[mshrs.scala:39:14]
output [5:0] io_resp_bits_uop_lrs3, // @[mshrs.scala:39:14]
output io_resp_bits_uop_ldst_val, // @[mshrs.scala:39:14]
output [1:0] io_resp_bits_uop_dst_rtype, // @[mshrs.scala:39:14]
output [1:0] io_resp_bits_uop_lrs1_rtype, // @[mshrs.scala:39:14]
output [1:0] io_resp_bits_uop_lrs2_rtype, // @[mshrs.scala:39:14]
output io_resp_bits_uop_frs3_en, // @[mshrs.scala:39:14]
output io_resp_bits_uop_fp_val, // @[mshrs.scala:39:14]
output io_resp_bits_uop_fp_single, // @[mshrs.scala:39:14]
output io_resp_bits_uop_xcpt_pf_if, // @[mshrs.scala:39:14]
output io_resp_bits_uop_xcpt_ae_if, // @[mshrs.scala:39:14]
output io_resp_bits_uop_xcpt_ma_if, // @[mshrs.scala:39:14]
output io_resp_bits_uop_bp_debug_if, // @[mshrs.scala:39:14]
output io_resp_bits_uop_bp_xcpt_if, // @[mshrs.scala:39:14]
output [1:0] io_resp_bits_uop_debug_fsrc, // @[mshrs.scala:39:14]
output [1:0] io_resp_bits_uop_debug_tsrc, // @[mshrs.scala:39:14]
output [63:0] io_resp_bits_data, // @[mshrs.scala:39:14]
output io_resp_bits_is_hella, // @[mshrs.scala:39:14]
input io_wb_resp, // @[mshrs.scala:39:14]
output io_probe_rdy // @[mshrs.scala:39:14]
);
wire rpq_io_deq_ready; // @[mshrs.scala:135:20, :215:30, :222:40, :233:41, :256:45]
wire _rpq_io_enq_ready; // @[mshrs.scala:128:19]
wire _rpq_io_deq_valid; // @[mshrs.scala:128:19]
wire [6:0] _rpq_io_deq_bits_uop_uopc; // @[mshrs.scala:128:19]
wire [31:0] _rpq_io_deq_bits_uop_inst; // @[mshrs.scala:128:19]
wire [31:0] _rpq_io_deq_bits_uop_debug_inst; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_is_rvc; // @[mshrs.scala:128:19]
wire [33:0] _rpq_io_deq_bits_uop_debug_pc; // @[mshrs.scala:128:19]
wire [2:0] _rpq_io_deq_bits_uop_iq_type; // @[mshrs.scala:128:19]
wire [9:0] _rpq_io_deq_bits_uop_fu_code; // @[mshrs.scala:128:19]
wire [3:0] _rpq_io_deq_bits_uop_ctrl_br_type; // @[mshrs.scala:128:19]
wire [1:0] _rpq_io_deq_bits_uop_ctrl_op1_sel; // @[mshrs.scala:128:19]
wire [2:0] _rpq_io_deq_bits_uop_ctrl_op2_sel; // @[mshrs.scala:128:19]
wire [2:0] _rpq_io_deq_bits_uop_ctrl_imm_sel; // @[mshrs.scala:128:19]
wire [4:0] _rpq_io_deq_bits_uop_ctrl_op_fcn; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_ctrl_fcn_dw; // @[mshrs.scala:128:19]
wire [2:0] _rpq_io_deq_bits_uop_ctrl_csr_cmd; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_ctrl_is_load; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_ctrl_is_sta; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_ctrl_is_std; // @[mshrs.scala:128:19]
wire [1:0] _rpq_io_deq_bits_uop_iw_state; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_iw_p1_poisoned; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_iw_p2_poisoned; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_is_br; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_is_jalr; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_is_jal; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_is_sfb; // @[mshrs.scala:128:19]
wire [3:0] _rpq_io_deq_bits_uop_br_mask; // @[mshrs.scala:128:19]
wire [1:0] _rpq_io_deq_bits_uop_br_tag; // @[mshrs.scala:128:19]
wire [3:0] _rpq_io_deq_bits_uop_ftq_idx; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_edge_inst; // @[mshrs.scala:128:19]
wire [5:0] _rpq_io_deq_bits_uop_pc_lob; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_taken; // @[mshrs.scala:128:19]
wire [19:0] _rpq_io_deq_bits_uop_imm_packed; // @[mshrs.scala:128:19]
wire [11:0] _rpq_io_deq_bits_uop_csr_addr; // @[mshrs.scala:128:19]
wire [5:0] _rpq_io_deq_bits_uop_rob_idx; // @[mshrs.scala:128:19]
wire [3:0] _rpq_io_deq_bits_uop_ldq_idx; // @[mshrs.scala:128:19]
wire [3:0] _rpq_io_deq_bits_uop_stq_idx; // @[mshrs.scala:128:19]
wire [1:0] _rpq_io_deq_bits_uop_rxq_idx; // @[mshrs.scala:128:19]
wire [6:0] _rpq_io_deq_bits_uop_pdst; // @[mshrs.scala:128:19]
wire [6:0] _rpq_io_deq_bits_uop_prs1; // @[mshrs.scala:128:19]
wire [6:0] _rpq_io_deq_bits_uop_prs2; // @[mshrs.scala:128:19]
wire [6:0] _rpq_io_deq_bits_uop_prs3; // @[mshrs.scala:128:19]
wire [3:0] _rpq_io_deq_bits_uop_ppred; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_prs1_busy; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_prs2_busy; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_prs3_busy; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_ppred_busy; // @[mshrs.scala:128:19]
wire [6:0] _rpq_io_deq_bits_uop_stale_pdst; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_exception; // @[mshrs.scala:128:19]
wire [63:0] _rpq_io_deq_bits_uop_exc_cause; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_bypassable; // @[mshrs.scala:128:19]
wire [4:0] _rpq_io_deq_bits_uop_mem_cmd; // @[mshrs.scala:128:19]
wire [1:0] _rpq_io_deq_bits_uop_mem_size; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_mem_signed; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_is_fence; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_is_fencei; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_is_amo; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_uses_ldq; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_uses_stq; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_is_sys_pc2epc; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_is_unique; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_flush_on_commit; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_ldst_is_rs1; // @[mshrs.scala:128:19]
wire [5:0] _rpq_io_deq_bits_uop_ldst; // @[mshrs.scala:128:19]
wire [5:0] _rpq_io_deq_bits_uop_lrs1; // @[mshrs.scala:128:19]
wire [5:0] _rpq_io_deq_bits_uop_lrs2; // @[mshrs.scala:128:19]
wire [5:0] _rpq_io_deq_bits_uop_lrs3; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_ldst_val; // @[mshrs.scala:128:19]
wire [1:0] _rpq_io_deq_bits_uop_dst_rtype; // @[mshrs.scala:128:19]
wire [1:0] _rpq_io_deq_bits_uop_lrs1_rtype; // @[mshrs.scala:128:19]
wire [1:0] _rpq_io_deq_bits_uop_lrs2_rtype; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_frs3_en; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_fp_val; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_fp_single; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_xcpt_pf_if; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_xcpt_ae_if; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_xcpt_ma_if; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_bp_debug_if; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_bp_xcpt_if; // @[mshrs.scala:128:19]
wire [1:0] _rpq_io_deq_bits_uop_debug_fsrc; // @[mshrs.scala:128:19]
wire [1:0] _rpq_io_deq_bits_uop_debug_tsrc; // @[mshrs.scala:128:19]
wire [33:0] _rpq_io_deq_bits_addr; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_is_hella; // @[mshrs.scala:128:19]
wire _rpq_io_empty; // @[mshrs.scala:128:19]
wire io_req_pri_val_0 = io_req_pri_val; // @[mshrs.scala:36:7]
wire io_req_sec_val_0 = io_req_sec_val; // @[mshrs.scala:36:7]
wire io_clear_prefetch_0 = io_clear_prefetch; // @[mshrs.scala:36:7]
wire [5:0] io_rob_pnr_idx_0 = io_rob_pnr_idx; // @[mshrs.scala:36:7]
wire [5:0] io_rob_head_idx_0 = io_rob_head_idx; // @[mshrs.scala:36:7]
wire [6:0] io_req_uop_uopc_0 = io_req_uop_uopc; // @[mshrs.scala:36:7]
wire [31:0] io_req_uop_inst_0 = io_req_uop_inst; // @[mshrs.scala:36:7]
wire [31:0] io_req_uop_debug_inst_0 = io_req_uop_debug_inst; // @[mshrs.scala:36:7]
wire io_req_uop_is_rvc_0 = io_req_uop_is_rvc; // @[mshrs.scala:36:7]
wire [33:0] io_req_uop_debug_pc_0 = io_req_uop_debug_pc; // @[mshrs.scala:36:7]
wire [2:0] io_req_uop_iq_type_0 = io_req_uop_iq_type; // @[mshrs.scala:36:7]
wire [9:0] io_req_uop_fu_code_0 = io_req_uop_fu_code; // @[mshrs.scala:36:7]
wire [3:0] io_req_uop_ctrl_br_type_0 = io_req_uop_ctrl_br_type; // @[mshrs.scala:36:7]
wire [1:0] io_req_uop_ctrl_op1_sel_0 = io_req_uop_ctrl_op1_sel; // @[mshrs.scala:36:7]
wire [2:0] io_req_uop_ctrl_op2_sel_0 = io_req_uop_ctrl_op2_sel; // @[mshrs.scala:36:7]
wire [2:0] io_req_uop_ctrl_imm_sel_0 = io_req_uop_ctrl_imm_sel; // @[mshrs.scala:36:7]
wire [4:0] io_req_uop_ctrl_op_fcn_0 = io_req_uop_ctrl_op_fcn; // @[mshrs.scala:36:7]
wire io_req_uop_ctrl_fcn_dw_0 = io_req_uop_ctrl_fcn_dw; // @[mshrs.scala:36:7]
wire [2:0] io_req_uop_ctrl_csr_cmd_0 = io_req_uop_ctrl_csr_cmd; // @[mshrs.scala:36:7]
wire io_req_uop_ctrl_is_load_0 = io_req_uop_ctrl_is_load; // @[mshrs.scala:36:7]
wire io_req_uop_ctrl_is_sta_0 = io_req_uop_ctrl_is_sta; // @[mshrs.scala:36:7]
wire io_req_uop_ctrl_is_std_0 = io_req_uop_ctrl_is_std; // @[mshrs.scala:36:7]
wire [1:0] io_req_uop_iw_state_0 = io_req_uop_iw_state; // @[mshrs.scala:36:7]
wire io_req_uop_iw_p1_poisoned_0 = io_req_uop_iw_p1_poisoned; // @[mshrs.scala:36:7]
wire io_req_uop_iw_p2_poisoned_0 = io_req_uop_iw_p2_poisoned; // @[mshrs.scala:36:7]
wire io_req_uop_is_br_0 = io_req_uop_is_br; // @[mshrs.scala:36:7]
wire io_req_uop_is_jalr_0 = io_req_uop_is_jalr; // @[mshrs.scala:36:7]
wire io_req_uop_is_jal_0 = io_req_uop_is_jal; // @[mshrs.scala:36:7]
wire io_req_uop_is_sfb_0 = io_req_uop_is_sfb; // @[mshrs.scala:36:7]
wire [3:0] io_req_uop_br_mask_0 = io_req_uop_br_mask; // @[mshrs.scala:36:7]
wire [1:0] io_req_uop_br_tag_0 = io_req_uop_br_tag; // @[mshrs.scala:36:7]
wire [3:0] io_req_uop_ftq_idx_0 = io_req_uop_ftq_idx; // @[mshrs.scala:36:7]
wire io_req_uop_edge_inst_0 = io_req_uop_edge_inst; // @[mshrs.scala:36:7]
wire [5:0] io_req_uop_pc_lob_0 = io_req_uop_pc_lob; // @[mshrs.scala:36:7]
wire io_req_uop_taken_0 = io_req_uop_taken; // @[mshrs.scala:36:7]
wire [19:0] io_req_uop_imm_packed_0 = io_req_uop_imm_packed; // @[mshrs.scala:36:7]
wire [11:0] io_req_uop_csr_addr_0 = io_req_uop_csr_addr; // @[mshrs.scala:36:7]
wire [5:0] io_req_uop_rob_idx_0 = io_req_uop_rob_idx; // @[mshrs.scala:36:7]
wire [3:0] io_req_uop_ldq_idx_0 = io_req_uop_ldq_idx; // @[mshrs.scala:36:7]
wire [3:0] io_req_uop_stq_idx_0 = io_req_uop_stq_idx; // @[mshrs.scala:36:7]
wire [1:0] io_req_uop_rxq_idx_0 = io_req_uop_rxq_idx; // @[mshrs.scala:36:7]
wire [6:0] io_req_uop_pdst_0 = io_req_uop_pdst; // @[mshrs.scala:36:7]
wire [6:0] io_req_uop_prs1_0 = io_req_uop_prs1; // @[mshrs.scala:36:7]
wire [6:0] io_req_uop_prs2_0 = io_req_uop_prs2; // @[mshrs.scala:36:7]
wire [6:0] io_req_uop_prs3_0 = io_req_uop_prs3; // @[mshrs.scala:36:7]
wire [3:0] io_req_uop_ppred_0 = io_req_uop_ppred; // @[mshrs.scala:36:7]
wire io_req_uop_prs1_busy_0 = io_req_uop_prs1_busy; // @[mshrs.scala:36:7]
wire io_req_uop_prs2_busy_0 = io_req_uop_prs2_busy; // @[mshrs.scala:36:7]
wire io_req_uop_prs3_busy_0 = io_req_uop_prs3_busy; // @[mshrs.scala:36:7]
wire io_req_uop_ppred_busy_0 = io_req_uop_ppred_busy; // @[mshrs.scala:36:7]
wire [6:0] io_req_uop_stale_pdst_0 = io_req_uop_stale_pdst; // @[mshrs.scala:36:7]
wire io_req_uop_exception_0 = io_req_uop_exception; // @[mshrs.scala:36:7]
wire [63:0] io_req_uop_exc_cause_0 = io_req_uop_exc_cause; // @[mshrs.scala:36:7]
wire io_req_uop_bypassable_0 = io_req_uop_bypassable; // @[mshrs.scala:36:7]
wire [4:0] io_req_uop_mem_cmd_0 = io_req_uop_mem_cmd; // @[mshrs.scala:36:7]
wire [1:0] io_req_uop_mem_size_0 = io_req_uop_mem_size; // @[mshrs.scala:36:7]
wire io_req_uop_mem_signed_0 = io_req_uop_mem_signed; // @[mshrs.scala:36:7]
wire io_req_uop_is_fence_0 = io_req_uop_is_fence; // @[mshrs.scala:36:7]
wire io_req_uop_is_fencei_0 = io_req_uop_is_fencei; // @[mshrs.scala:36:7]
wire io_req_uop_is_amo_0 = io_req_uop_is_amo; // @[mshrs.scala:36:7]
wire io_req_uop_uses_ldq_0 = io_req_uop_uses_ldq; // @[mshrs.scala:36:7]
wire io_req_uop_uses_stq_0 = io_req_uop_uses_stq; // @[mshrs.scala:36:7]
wire io_req_uop_is_sys_pc2epc_0 = io_req_uop_is_sys_pc2epc; // @[mshrs.scala:36:7]
wire io_req_uop_is_unique_0 = io_req_uop_is_unique; // @[mshrs.scala:36:7]
wire io_req_uop_flush_on_commit_0 = io_req_uop_flush_on_commit; // @[mshrs.scala:36:7]
wire io_req_uop_ldst_is_rs1_0 = io_req_uop_ldst_is_rs1; // @[mshrs.scala:36:7]
wire [5:0] io_req_uop_ldst_0 = io_req_uop_ldst; // @[mshrs.scala:36:7]
wire [5:0] io_req_uop_lrs1_0 = io_req_uop_lrs1; // @[mshrs.scala:36:7]
wire [5:0] io_req_uop_lrs2_0 = io_req_uop_lrs2; // @[mshrs.scala:36:7]
wire [5:0] io_req_uop_lrs3_0 = io_req_uop_lrs3; // @[mshrs.scala:36:7]
wire io_req_uop_ldst_val_0 = io_req_uop_ldst_val; // @[mshrs.scala:36:7]
wire [1:0] io_req_uop_dst_rtype_0 = io_req_uop_dst_rtype; // @[mshrs.scala:36:7]
wire [1:0] io_req_uop_lrs1_rtype_0 = io_req_uop_lrs1_rtype; // @[mshrs.scala:36:7]
wire [1:0] io_req_uop_lrs2_rtype_0 = io_req_uop_lrs2_rtype; // @[mshrs.scala:36:7]
wire io_req_uop_frs3_en_0 = io_req_uop_frs3_en; // @[mshrs.scala:36:7]
wire io_req_uop_fp_val_0 = io_req_uop_fp_val; // @[mshrs.scala:36:7]
wire io_req_uop_fp_single_0 = io_req_uop_fp_single; // @[mshrs.scala:36:7]
wire io_req_uop_xcpt_pf_if_0 = io_req_uop_xcpt_pf_if; // @[mshrs.scala:36:7]
wire io_req_uop_xcpt_ae_if_0 = io_req_uop_xcpt_ae_if; // @[mshrs.scala:36:7]
wire io_req_uop_xcpt_ma_if_0 = io_req_uop_xcpt_ma_if; // @[mshrs.scala:36:7]
wire io_req_uop_bp_debug_if_0 = io_req_uop_bp_debug_if; // @[mshrs.scala:36:7]
wire io_req_uop_bp_xcpt_if_0 = io_req_uop_bp_xcpt_if; // @[mshrs.scala:36:7]
wire [1:0] io_req_uop_debug_fsrc_0 = io_req_uop_debug_fsrc; // @[mshrs.scala:36:7]
wire [1:0] io_req_uop_debug_tsrc_0 = io_req_uop_debug_tsrc; // @[mshrs.scala:36:7]
wire [33:0] io_req_addr_0 = io_req_addr; // @[mshrs.scala:36:7]
wire [63:0] io_req_data_0 = io_req_data; // @[mshrs.scala:36:7]
wire io_req_is_hella_0 = io_req_is_hella; // @[mshrs.scala:36:7]
wire io_req_tag_match_0 = io_req_tag_match; // @[mshrs.scala:36:7]
wire [1:0] io_req_old_meta_coh_state_0 = io_req_old_meta_coh_state; // @[mshrs.scala:36:7]
wire [21:0] io_req_old_meta_tag_0 = io_req_old_meta_tag; // @[mshrs.scala:36:7]
wire [1:0] io_req_way_en_0 = io_req_way_en; // @[mshrs.scala:36:7]
wire [4:0] io_req_sdq_id_0 = io_req_sdq_id; // @[mshrs.scala:36:7]
wire io_req_is_probe_0 = io_req_is_probe; // @[mshrs.scala:36:7]
wire io_mem_acquire_ready_0 = io_mem_acquire_ready; // @[mshrs.scala:36:7]
wire io_mem_grant_valid_0 = io_mem_grant_valid; // @[mshrs.scala:36:7]
wire [2:0] io_mem_grant_bits_opcode_0 = io_mem_grant_bits_opcode; // @[mshrs.scala:36:7]
wire [1:0] io_mem_grant_bits_param_0 = io_mem_grant_bits_param; // @[mshrs.scala:36:7]
wire [3:0] io_mem_grant_bits_size_0 = io_mem_grant_bits_size; // @[mshrs.scala:36:7]
wire [3:0] io_mem_grant_bits_source_0 = io_mem_grant_bits_source; // @[mshrs.scala:36:7]
wire [2:0] io_mem_grant_bits_sink_0 = io_mem_grant_bits_sink; // @[mshrs.scala:36:7]
wire io_mem_grant_bits_denied_0 = io_mem_grant_bits_denied; // @[mshrs.scala:36:7]
wire [63:0] io_mem_grant_bits_data_0 = io_mem_grant_bits_data; // @[mshrs.scala:36:7]
wire io_mem_grant_bits_corrupt_0 = io_mem_grant_bits_corrupt; // @[mshrs.scala:36:7]
wire io_mem_finish_ready_0 = io_mem_finish_ready; // @[mshrs.scala:36:7]
wire io_prober_state_valid_0 = io_prober_state_valid; // @[mshrs.scala:36:7]
wire [33:0] io_prober_state_bits_0 = io_prober_state_bits; // @[mshrs.scala:36:7]
wire io_refill_ready_0 = io_refill_ready; // @[mshrs.scala:36:7]
wire io_meta_write_ready_0 = io_meta_write_ready; // @[mshrs.scala:36:7]
wire io_meta_read_ready_0 = io_meta_read_ready; // @[mshrs.scala:36:7]
wire io_meta_resp_valid_0 = io_meta_resp_valid; // @[mshrs.scala:36:7]
wire [1:0] io_meta_resp_bits_coh_state_0 = io_meta_resp_bits_coh_state; // @[mshrs.scala:36:7]
wire [21:0] io_meta_resp_bits_tag_0 = io_meta_resp_bits_tag; // @[mshrs.scala:36:7]
wire io_wb_req_ready_0 = io_wb_req_ready; // @[mshrs.scala:36:7]
wire io_lb_read_ready_0 = io_lb_read_ready; // @[mshrs.scala:36:7]
wire [63:0] io_lb_resp_0 = io_lb_resp; // @[mshrs.scala:36:7]
wire io_lb_write_ready_0 = io_lb_write_ready; // @[mshrs.scala:36:7]
wire io_replay_ready_0 = io_replay_ready; // @[mshrs.scala:36:7]
wire io_resp_ready_0 = io_resp_ready; // @[mshrs.scala:36:7]
wire io_wb_resp_0 = io_wb_resp; // @[mshrs.scala:36:7]
wire _state_T = reset; // @[mshrs.scala:194:11]
wire _state_T_26 = reset; // @[mshrs.scala:201:15]
wire _state_T_34 = reset; // @[mshrs.scala:194:11]
wire _state_T_60 = reset; // @[mshrs.scala:201:15]
wire [2:0] io_id = 3'h2; // @[mshrs.scala:36:7]
wire [2:0] io_lb_read_bits_id = 3'h2; // @[mshrs.scala:36:7]
wire [2:0] io_lb_write_bits_id = 3'h2; // @[mshrs.scala:36:7]
wire [3:0] io_brupdate_b1_resolve_mask = 4'h0; // @[mshrs.scala:36:7]
wire [3:0] io_brupdate_b1_mispredict_mask = 4'h0; // @[mshrs.scala:36:7]
wire [3:0] io_brupdate_b2_uop_ctrl_br_type = 4'h0; // @[mshrs.scala:36:7]
wire [3:0] io_brupdate_b2_uop_br_mask = 4'h0; // @[mshrs.scala:36:7]
wire [3:0] io_brupdate_b2_uop_ftq_idx = 4'h0; // @[mshrs.scala:36:7]
wire [3:0] io_brupdate_b2_uop_ldq_idx = 4'h0; // @[mshrs.scala:36:7]
wire [3:0] io_brupdate_b2_uop_stq_idx = 4'h0; // @[mshrs.scala:36:7]
wire [3:0] io_brupdate_b2_uop_ppred = 4'h0; // @[mshrs.scala:36:7]
wire [3:0] _r_T_10 = 4'h0; // @[Metadata.scala:125:10]
wire [3:0] _grow_param_r_T_16 = 4'h0; // @[Metadata.scala:68:10]
wire [3:0] _coh_on_grant_T_4 = 4'h0; // @[Metadata.scala:87:10]
wire [3:0] _r1_T_16 = 4'h0; // @[Metadata.scala:68:10]
wire [3:0] _r2_T_16 = 4'h0; // @[Metadata.scala:68:10]
wire [3:0] _state_req_needs_wb_r_T_10 = 4'h0; // @[Metadata.scala:125:10]
wire [3:0] _state_r_T_16 = 4'h0; // @[Metadata.scala:68:10]
wire [3:0] _needs_wb_r_T_10 = 4'h0; // @[Metadata.scala:125:10]
wire [3:0] _r_T_80 = 4'h0; // @[Metadata.scala:68:10]
wire [3:0] _r_T_139 = 4'h0; // @[Metadata.scala:68:10]
wire [3:0] _state_req_needs_wb_r_T_74 = 4'h0; // @[Metadata.scala:125:10]
wire [3:0] _state_r_T_75 = 4'h0; // @[Metadata.scala:68:10]
wire [6:0] io_brupdate_b2_uop_uopc = 7'h0; // @[mshrs.scala:36:7]
wire [6:0] io_brupdate_b2_uop_pdst = 7'h0; // @[mshrs.scala:36:7]
wire [6:0] io_brupdate_b2_uop_prs1 = 7'h0; // @[mshrs.scala:36:7]
wire [6:0] io_brupdate_b2_uop_prs2 = 7'h0; // @[mshrs.scala:36:7]
wire [6:0] io_brupdate_b2_uop_prs3 = 7'h0; // @[mshrs.scala:36:7]
wire [6:0] io_brupdate_b2_uop_stale_pdst = 7'h0; // @[mshrs.scala:36:7]
wire [6:0] _data_word_T = 7'h0; // @[mshrs.scala:264:32]
wire [31:0] io_brupdate_b2_uop_inst = 32'h0; // @[mshrs.scala:36:7]
wire [31:0] io_brupdate_b2_uop_debug_inst = 32'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_is_rvc = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_ctrl_fcn_dw = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_ctrl_is_load = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_ctrl_is_sta = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_ctrl_is_std = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_iw_p1_poisoned = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_iw_p2_poisoned = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_is_br = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_is_jalr = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_is_jal = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_is_sfb = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_edge_inst = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_taken = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_prs1_busy = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_prs2_busy = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_prs3_busy = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_ppred_busy = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_exception = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_bypassable = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_mem_signed = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_is_fence = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_is_fencei = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_is_amo = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_uses_ldq = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_uses_stq = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_is_sys_pc2epc = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_is_unique = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_flush_on_commit = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_ldst_is_rs1 = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_ldst_val = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_frs3_en = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_fp_val = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_fp_single = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_xcpt_pf_if = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_xcpt_ae_if = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_xcpt_ma_if = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_bp_debug_if = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_bp_xcpt_if = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_valid = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_mispredict = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_taken = 1'h0; // @[mshrs.scala:36:7]
wire io_exception = 1'h0; // @[mshrs.scala:36:7]
wire io_mem_acquire_bits_corrupt = 1'h0; // @[mshrs.scala:36:7]
wire _r_T_2 = 1'h0; // @[Metadata.scala:140:24]
wire _r_T_4 = 1'h0; // @[Metadata.scala:140:24]
wire _r_T_20 = 1'h0; // @[Misc.scala:38:9]
wire _r_T_24 = 1'h0; // @[Misc.scala:38:9]
wire _r_T_28 = 1'h0; // @[Misc.scala:38:9]
wire _grow_param_r_T_26 = 1'h0; // @[Misc.scala:35:9]
wire _grow_param_r_T_29 = 1'h0; // @[Misc.scala:35:9]
wire _grow_param_r_T_32 = 1'h0; // @[Misc.scala:35:9]
wire _grow_param_r_T_35 = 1'h0; // @[Misc.scala:35:9]
wire _grow_param_r_T_38 = 1'h0; // @[Misc.scala:35:9]
wire _r1_T_26 = 1'h0; // @[Misc.scala:35:9]
wire _r1_T_29 = 1'h0; // @[Misc.scala:35:9]
wire _r1_T_32 = 1'h0; // @[Misc.scala:35:9]
wire _r1_T_35 = 1'h0; // @[Misc.scala:35:9]
wire _r1_T_38 = 1'h0; // @[Misc.scala:35:9]
wire _r2_T_26 = 1'h0; // @[Misc.scala:35:9]
wire _r2_T_29 = 1'h0; // @[Misc.scala:35:9]
wire _r2_T_32 = 1'h0; // @[Misc.scala:35:9]
wire _r2_T_35 = 1'h0; // @[Misc.scala:35:9]
wire _r2_T_38 = 1'h0; // @[Misc.scala:35:9]
wire _state_req_needs_wb_r_T_2 = 1'h0; // @[Metadata.scala:140:24]
wire _state_req_needs_wb_r_T_4 = 1'h0; // @[Metadata.scala:140:24]
wire _state_req_needs_wb_r_T_20 = 1'h0; // @[Misc.scala:38:9]
wire _state_req_needs_wb_r_T_24 = 1'h0; // @[Misc.scala:38:9]
wire _state_req_needs_wb_r_T_28 = 1'h0; // @[Misc.scala:38:9]
wire _state_r_T_26 = 1'h0; // @[Misc.scala:35:9]
wire _state_r_T_29 = 1'h0; // @[Misc.scala:35:9]
wire _state_r_T_32 = 1'h0; // @[Misc.scala:35:9]
wire _state_r_T_35 = 1'h0; // @[Misc.scala:35:9]
wire _state_r_T_38 = 1'h0; // @[Misc.scala:35:9]
wire _io_mem_acquire_bits_legal_T = 1'h0; // @[Parameters.scala:684:29]
wire _io_mem_acquire_bits_legal_T_6 = 1'h0; // @[Parameters.scala:684:54]
wire _io_mem_acquire_bits_legal_T_15 = 1'h0; // @[Parameters.scala:686:26]
wire io_mem_acquire_bits_a_corrupt = 1'h0; // @[Edges.scala:346:17]
wire io_mem_acquire_bits_a_mask_sub_size = 1'h0; // @[Misc.scala:209:26]
wire _io_mem_acquire_bits_a_mask_sub_acc_T = 1'h0; // @[Misc.scala:215:38]
wire _io_mem_acquire_bits_a_mask_sub_acc_T_1 = 1'h0; // @[Misc.scala:215:38]
wire _io_mem_acquire_bits_a_mask_sub_acc_T_2 = 1'h0; // @[Misc.scala:215:38]
wire _io_mem_acquire_bits_a_mask_sub_acc_T_3 = 1'h0; // @[Misc.scala:215:38]
wire io_resp_bits_data_doZero = 1'h0; // @[AMOALU.scala:43:31]
wire io_resp_bits_data_doZero_1 = 1'h0; // @[AMOALU.scala:43:31]
wire io_resp_bits_data_doZero_2 = 1'h0; // @[AMOALU.scala:43:31]
wire _needs_wb_r_T_2 = 1'h0; // @[Metadata.scala:140:24]
wire _needs_wb_r_T_4 = 1'h0; // @[Metadata.scala:140:24]
wire _needs_wb_r_T_20 = 1'h0; // @[Misc.scala:38:9]
wire _needs_wb_r_T_24 = 1'h0; // @[Misc.scala:38:9]
wire _needs_wb_r_T_28 = 1'h0; // @[Misc.scala:38:9]
wire _r_T_90 = 1'h0; // @[Misc.scala:35:9]
wire _r_T_93 = 1'h0; // @[Misc.scala:35:9]
wire _r_T_96 = 1'h0; // @[Misc.scala:35:9]
wire _r_T_99 = 1'h0; // @[Misc.scala:35:9]
wire _r_T_102 = 1'h0; // @[Misc.scala:35:9]
wire _r_T_149 = 1'h0; // @[Misc.scala:35:9]
wire _r_T_152 = 1'h0; // @[Misc.scala:35:9]
wire _r_T_155 = 1'h0; // @[Misc.scala:35:9]
wire _r_T_158 = 1'h0; // @[Misc.scala:35:9]
wire _r_T_161 = 1'h0; // @[Misc.scala:35:9]
wire _state_req_needs_wb_r_T_66 = 1'h0; // @[Metadata.scala:140:24]
wire _state_req_needs_wb_r_T_68 = 1'h0; // @[Metadata.scala:140:24]
wire _state_req_needs_wb_r_T_84 = 1'h0; // @[Misc.scala:38:9]
wire _state_req_needs_wb_r_T_88 = 1'h0; // @[Misc.scala:38:9]
wire _state_req_needs_wb_r_T_92 = 1'h0; // @[Misc.scala:38:9]
wire _state_r_T_85 = 1'h0; // @[Misc.scala:35:9]
wire _state_r_T_88 = 1'h0; // @[Misc.scala:35:9]
wire _state_r_T_91 = 1'h0; // @[Misc.scala:35:9]
wire _state_r_T_94 = 1'h0; // @[Misc.scala:35:9]
wire _state_r_T_97 = 1'h0; // @[Misc.scala:35:9]
wire [33:0] io_brupdate_b2_uop_debug_pc = 34'h0; // @[mshrs.scala:36:7]
wire [33:0] io_brupdate_b2_jalr_target = 34'h0; // @[mshrs.scala:36:7]
wire [2:0] io_brupdate_b2_uop_iq_type = 3'h0; // @[mshrs.scala:36:7]
wire [2:0] io_brupdate_b2_uop_ctrl_op2_sel = 3'h0; // @[mshrs.scala:36:7]
wire [2:0] io_brupdate_b2_uop_ctrl_imm_sel = 3'h0; // @[mshrs.scala:36:7]
wire [2:0] io_brupdate_b2_uop_ctrl_csr_cmd = 3'h0; // @[mshrs.scala:36:7]
wire [2:0] io_brupdate_b2_cfi_type = 3'h0; // @[mshrs.scala:36:7]
wire [9:0] io_brupdate_b2_uop_fu_code = 10'h0; // @[mshrs.scala:36:7]
wire [1:0] io_brupdate_b2_uop_ctrl_op1_sel = 2'h0; // @[mshrs.scala:36:7]
wire [1:0] io_brupdate_b2_uop_iw_state = 2'h0; // @[mshrs.scala:36:7]
wire [1:0] io_brupdate_b2_uop_br_tag = 2'h0; // @[mshrs.scala:36:7]
wire [1:0] io_brupdate_b2_uop_rxq_idx = 2'h0; // @[mshrs.scala:36:7]
wire [1:0] io_brupdate_b2_uop_mem_size = 2'h0; // @[mshrs.scala:36:7]
wire [1:0] io_brupdate_b2_uop_dst_rtype = 2'h0; // @[mshrs.scala:36:7]
wire [1:0] io_brupdate_b2_uop_lrs1_rtype = 2'h0; // @[mshrs.scala:36:7]
wire [1:0] io_brupdate_b2_uop_lrs2_rtype = 2'h0; // @[mshrs.scala:36:7]
wire [1:0] io_brupdate_b2_uop_debug_fsrc = 2'h0; // @[mshrs.scala:36:7]
wire [1:0] io_brupdate_b2_uop_debug_tsrc = 2'h0; // @[mshrs.scala:36:7]
wire [1:0] io_brupdate_b2_pc_sel = 2'h0; // @[mshrs.scala:36:7]
wire [1:0] io_brupdate_b2_target_offset = 2'h0; // @[mshrs.scala:36:7]
wire [1:0] new_coh_meta_state = 2'h0; // @[Metadata.scala:160:20]
wire [1:0] _r_T_22 = 2'h0; // @[Misc.scala:38:63]
wire [1:0] _r_T_26 = 2'h0; // @[Misc.scala:38:63]
wire [1:0] _r_T_30 = 2'h0; // @[Misc.scala:38:63]
wire [1:0] _r_T_34 = 2'h0; // @[Misc.scala:38:63]
wire [1:0] _r_T_38 = 2'h0; // @[Misc.scala:38:63]
wire [1:0] _grow_param_r_T_1 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _grow_param_r_T_3 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _grow_param_r_T_5 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _grow_param_r_T_15 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _coh_on_grant_T_1 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _coh_on_grant_T_3 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _r1_T_1 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _r1_T_3 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _r1_T_5 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _r1_T_15 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _r2_T_1 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _r2_T_3 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _r2_T_5 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _r2_T_15 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _state_req_needs_wb_r_T_22 = 2'h0; // @[Misc.scala:38:63]
wire [1:0] _state_req_needs_wb_r_T_26 = 2'h0; // @[Misc.scala:38:63]
wire [1:0] _state_req_needs_wb_r_T_30 = 2'h0; // @[Misc.scala:38:63]
wire [1:0] _state_req_needs_wb_r_T_34 = 2'h0; // @[Misc.scala:38:63]
wire [1:0] _state_req_needs_wb_r_T_38 = 2'h0; // @[Misc.scala:38:63]
wire [1:0] _state_r_T_1 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _state_r_T_3 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _state_r_T_5 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _state_r_T_15 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] state_new_coh_meta_state = 2'h0; // @[Metadata.scala:160:20]
wire [1:0] _needs_wb_r_T_22 = 2'h0; // @[Misc.scala:38:63]
wire [1:0] _needs_wb_r_T_26 = 2'h0; // @[Misc.scala:38:63]
wire [1:0] _needs_wb_r_T_30 = 2'h0; // @[Misc.scala:38:63]
wire [1:0] _needs_wb_r_T_34 = 2'h0; // @[Misc.scala:38:63]
wire [1:0] _needs_wb_r_T_38 = 2'h0; // @[Misc.scala:38:63]
wire [1:0] _r_T_65 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _r_T_67 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _r_T_69 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _r_T_79 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _r_T_124 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _r_T_126 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _r_T_128 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _r_T_138 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] new_coh_meta_1_state = 2'h0; // @[Metadata.scala:160:20]
wire [1:0] _state_req_needs_wb_r_T_86 = 2'h0; // @[Misc.scala:38:63]
wire [1:0] _state_req_needs_wb_r_T_90 = 2'h0; // @[Misc.scala:38:63]
wire [1:0] _state_req_needs_wb_r_T_94 = 2'h0; // @[Misc.scala:38:63]
wire [1:0] _state_req_needs_wb_r_T_98 = 2'h0; // @[Misc.scala:38:63]
wire [1:0] _state_req_needs_wb_r_T_102 = 2'h0; // @[Misc.scala:38:63]
wire [1:0] _state_r_T_60 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _state_r_T_62 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _state_r_T_64 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _state_r_T_74 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] state_new_coh_meta_1_state = 2'h0; // @[Metadata.scala:160:20]
wire [4:0] io_brupdate_b2_uop_ctrl_op_fcn = 5'h0; // @[mshrs.scala:36:7]
wire [4:0] io_brupdate_b2_uop_mem_cmd = 5'h0; // @[mshrs.scala:36:7]
wire [5:0] io_brupdate_b2_uop_pc_lob = 6'h0; // @[mshrs.scala:36:7]
wire [5:0] io_brupdate_b2_uop_rob_idx = 6'h0; // @[mshrs.scala:36:7]
wire [5:0] io_brupdate_b2_uop_ldst = 6'h0; // @[mshrs.scala:36:7]
wire [5:0] io_brupdate_b2_uop_lrs1 = 6'h0; // @[mshrs.scala:36:7]
wire [5:0] io_brupdate_b2_uop_lrs2 = 6'h0; // @[mshrs.scala:36:7]
wire [5:0] io_brupdate_b2_uop_lrs3 = 6'h0; // @[mshrs.scala:36:7]
wire [19:0] io_brupdate_b2_uop_imm_packed = 20'h0; // @[mshrs.scala:36:7]
wire [11:0] io_brupdate_b2_uop_csr_addr = 12'h0; // @[mshrs.scala:36:7]
wire [63:0] io_brupdate_b2_uop_exc_cause = 64'h0; // @[mshrs.scala:36:7]
wire [63:0] io_mem_acquire_bits_data = 64'h0; // @[mshrs.scala:36:7]
wire [63:0] io_mem_acquire_bits_a_data = 64'h0; // @[Edges.scala:346:17]
wire [2:0] io_mem_acquire_bits_opcode = 3'h6; // @[mshrs.scala:36:7]
wire [2:0] io_mem_acquire_bits_a_opcode = 3'h6; // @[Edges.scala:346:17]
wire [2:0] _io_mem_acquire_bits_a_mask_sizeOH_T = 3'h6; // @[Misc.scala:202:34]
wire [3:0] io_mem_acquire_bits_size = 4'h6; // @[mshrs.scala:36:7]
wire [3:0] _r_T_12 = 4'h6; // @[Metadata.scala:127:10]
wire [3:0] _grow_param_r_T_10 = 4'h6; // @[Metadata.scala:64:10]
wire [3:0] _r1_T_10 = 4'h6; // @[Metadata.scala:64:10]
wire [3:0] _r2_T_10 = 4'h6; // @[Metadata.scala:64:10]
wire [3:0] _state_req_needs_wb_r_T_12 = 4'h6; // @[Metadata.scala:127:10]
wire [3:0] _state_r_T_10 = 4'h6; // @[Metadata.scala:64:10]
wire [3:0] io_mem_acquire_bits_a_size = 4'h6; // @[Edges.scala:346:17]
wire [3:0] _needs_wb_r_T_12 = 4'h6; // @[Metadata.scala:127:10]
wire [3:0] _r_T_74 = 4'h6; // @[Metadata.scala:64:10]
wire [3:0] _r_T_133 = 4'h6; // @[Metadata.scala:64:10]
wire [3:0] _state_req_needs_wb_r_T_76 = 4'h6; // @[Metadata.scala:127:10]
wire [3:0] _state_r_T_69 = 4'h6; // @[Metadata.scala:64:10]
wire [3:0] io_mem_acquire_bits_source = 4'h2; // @[mshrs.scala:36:7]
wire [3:0] io_wb_req_bits_source = 4'h2; // @[mshrs.scala:36:7]
wire [3:0] _r_T_8 = 4'h2; // @[Metadata.scala:123:10]
wire [3:0] _grow_param_r_T_4 = 4'h2; // @[Metadata.scala:61:10]
wire [3:0] _r1_T_4 = 4'h2; // @[Metadata.scala:61:10]
wire [3:0] _r2_T_4 = 4'h2; // @[Metadata.scala:61:10]
wire [3:0] _state_req_needs_wb_r_T_8 = 4'h2; // @[Metadata.scala:123:10]
wire [3:0] _state_r_T_4 = 4'h2; // @[Metadata.scala:61:10]
wire [3:0] io_mem_acquire_bits_a_source = 4'h2; // @[Edges.scala:346:17]
wire [3:0] _needs_wb_r_T_8 = 4'h2; // @[Metadata.scala:123:10]
wire [3:0] _r_T_68 = 4'h2; // @[Metadata.scala:61:10]
wire [3:0] _r_T_127 = 4'h2; // @[Metadata.scala:61:10]
wire [3:0] _state_req_needs_wb_r_T_72 = 4'h2; // @[Metadata.scala:123:10]
wire [3:0] _state_r_T_63 = 4'h2; // @[Metadata.scala:61:10]
wire [7:0] io_mem_acquire_bits_mask = 8'hFF; // @[mshrs.scala:36:7]
wire [7:0] io_mem_acquire_bits_a_mask = 8'hFF; // @[Edges.scala:346:17]
wire [7:0] _io_mem_acquire_bits_a_mask_T = 8'hFF; // @[Misc.scala:222:10]
wire io_refill_bits_wmask = 1'h1; // @[mshrs.scala:36:7]
wire io_wb_req_bits_voluntary = 1'h1; // @[mshrs.scala:36:7]
wire _r_T = 1'h1; // @[Metadata.scala:140:24]
wire _state_req_needs_wb_r_T = 1'h1; // @[Metadata.scala:140:24]
wire _io_mem_acquire_bits_legal_T_7 = 1'h1; // @[Parameters.scala:91:44]
wire _io_mem_acquire_bits_legal_T_8 = 1'h1; // @[Parameters.scala:684:29]
wire io_mem_acquire_bits_a_mask_sub_sub_sub_0_1 = 1'h1; // @[Misc.scala:206:21]
wire io_mem_acquire_bits_a_mask_sub_sub_size = 1'h1; // @[Misc.scala:209:26]
wire io_mem_acquire_bits_a_mask_sub_sub_0_1 = 1'h1; // @[Misc.scala:215:29]
wire io_mem_acquire_bits_a_mask_sub_sub_1_1 = 1'h1; // @[Misc.scala:215:29]
wire io_mem_acquire_bits_a_mask_sub_0_1 = 1'h1; // @[Misc.scala:215:29]
wire io_mem_acquire_bits_a_mask_sub_1_1 = 1'h1; // @[Misc.scala:215:29]
wire io_mem_acquire_bits_a_mask_sub_2_1 = 1'h1; // @[Misc.scala:215:29]
wire io_mem_acquire_bits_a_mask_sub_3_1 = 1'h1; // @[Misc.scala:215:29]
wire io_mem_acquire_bits_a_mask_size = 1'h1; // @[Misc.scala:209:26]
wire io_mem_acquire_bits_a_mask_acc = 1'h1; // @[Misc.scala:215:29]
wire io_mem_acquire_bits_a_mask_acc_1 = 1'h1; // @[Misc.scala:215:29]
wire io_mem_acquire_bits_a_mask_acc_2 = 1'h1; // @[Misc.scala:215:29]
wire io_mem_acquire_bits_a_mask_acc_3 = 1'h1; // @[Misc.scala:215:29]
wire io_mem_acquire_bits_a_mask_acc_4 = 1'h1; // @[Misc.scala:215:29]
wire io_mem_acquire_bits_a_mask_acc_5 = 1'h1; // @[Misc.scala:215:29]
wire io_mem_acquire_bits_a_mask_acc_6 = 1'h1; // @[Misc.scala:215:29]
wire io_mem_acquire_bits_a_mask_acc_7 = 1'h1; // @[Misc.scala:215:29]
wire _needs_wb_r_T = 1'h1; // @[Metadata.scala:140:24]
wire _io_refill_bits_wmask_T = 1'h1; // @[mshrs.scala:342:30]
wire _state_req_needs_wb_r_T_64 = 1'h1; // @[Metadata.scala:140:24]
wire [21:0] io_meta_write_bits_tag = 22'h0; // @[mshrs.scala:36:7]
wire [3:0] _grow_param_r_T_24 = 4'hC; // @[Metadata.scala:72:10]
wire [3:0] _coh_on_grant_T_8 = 4'hC; // @[Metadata.scala:89:10]
wire [3:0] _r1_T_24 = 4'hC; // @[Metadata.scala:72:10]
wire [3:0] _r2_T_24 = 4'hC; // @[Metadata.scala:72:10]
wire [3:0] _state_r_T_24 = 4'hC; // @[Metadata.scala:72:10]
wire [3:0] _r_T_88 = 4'hC; // @[Metadata.scala:72:10]
wire [3:0] _r_T_147 = 4'hC; // @[Metadata.scala:72:10]
wire [3:0] _state_r_T_83 = 4'hC; // @[Metadata.scala:72:10]
wire [1:0] _grow_param_r_T_11 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _grow_param_r_T_13 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _grow_param_r_T_21 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _grow_param_r_T_23 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _coh_on_grant_T_7 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _r1_T_11 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _r1_T_13 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _r1_T_21 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _r1_T_23 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _r2_T_11 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _r2_T_13 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _r2_T_21 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _r2_T_23 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _dirties_T = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _state_r_T_11 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _state_r_T_13 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _state_r_T_21 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _state_r_T_23 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] io_mem_acquire_bits_a_mask_lo_lo = 2'h3; // @[Misc.scala:222:10]
wire [1:0] io_mem_acquire_bits_a_mask_lo_hi = 2'h3; // @[Misc.scala:222:10]
wire [1:0] io_mem_acquire_bits_a_mask_hi_lo = 2'h3; // @[Misc.scala:222:10]
wire [1:0] io_mem_acquire_bits_a_mask_hi_hi = 2'h3; // @[Misc.scala:222:10]
wire [1:0] _r_T_75 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _r_T_77 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _r_T_85 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _r_T_87 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _r_T_134 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _r_T_136 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _r_T_144 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _r_T_146 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _state_r_T_70 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _state_r_T_72 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _state_r_T_80 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _state_r_T_82 = 2'h3; // @[Metadata.scala:24:15]
wire [3:0] _grow_param_r_T_22 = 4'hD; // @[Metadata.scala:71:10]
wire [3:0] _r1_T_22 = 4'hD; // @[Metadata.scala:71:10]
wire [3:0] _r2_T_22 = 4'hD; // @[Metadata.scala:71:10]
wire [3:0] _state_r_T_22 = 4'hD; // @[Metadata.scala:71:10]
wire [3:0] _r_T_86 = 4'hD; // @[Metadata.scala:71:10]
wire [3:0] _r_T_145 = 4'hD; // @[Metadata.scala:71:10]
wire [3:0] _state_r_T_81 = 4'hD; // @[Metadata.scala:71:10]
wire [3:0] _r_T_14 = 4'h4; // @[Metadata.scala:129:10]
wire [3:0] _grow_param_r_T_20 = 4'h4; // @[Metadata.scala:70:10]
wire [3:0] _coh_on_grant_T_6 = 4'h4; // @[Metadata.scala:88:10]
wire [3:0] _r1_T_20 = 4'h4; // @[Metadata.scala:70:10]
wire [3:0] _r2_T_20 = 4'h4; // @[Metadata.scala:70:10]
wire [3:0] _state_req_needs_wb_r_T_14 = 4'h4; // @[Metadata.scala:129:10]
wire [3:0] _state_r_T_20 = 4'h4; // @[Metadata.scala:70:10]
wire [3:0] _io_mem_acquire_bits_a_mask_sizeOH_T_1 = 4'h4; // @[OneHot.scala:65:12]
wire [3:0] _needs_wb_r_T_14 = 4'h4; // @[Metadata.scala:129:10]
wire [3:0] _r_T_84 = 4'h4; // @[Metadata.scala:70:10]
wire [3:0] _r_T_143 = 4'h4; // @[Metadata.scala:70:10]
wire [3:0] _state_req_needs_wb_r_T_78 = 4'h4; // @[Metadata.scala:129:10]
wire [3:0] _state_r_T_79 = 4'h4; // @[Metadata.scala:70:10]
wire [3:0] _r_T_13 = 4'h5; // @[Metadata.scala:128:10]
wire [3:0] _grow_param_r_T_18 = 4'h5; // @[Metadata.scala:69:10]
wire [3:0] _r1_T_18 = 4'h5; // @[Metadata.scala:69:10]
wire [3:0] _r2_T_18 = 4'h5; // @[Metadata.scala:69:10]
wire [3:0] _state_req_needs_wb_r_T_13 = 4'h5; // @[Metadata.scala:128:10]
wire [3:0] _state_r_T_18 = 4'h5; // @[Metadata.scala:69:10]
wire [3:0] _needs_wb_r_T_13 = 4'h5; // @[Metadata.scala:128:10]
wire [3:0] _r_T_82 = 4'h5; // @[Metadata.scala:69:10]
wire [3:0] _r_T_141 = 4'h5; // @[Metadata.scala:69:10]
wire [3:0] _state_req_needs_wb_r_T_77 = 4'h5; // @[Metadata.scala:128:10]
wire [3:0] _state_r_T_77 = 4'h5; // @[Metadata.scala:69:10]
wire [3:0] _grow_param_r_T_14 = 4'hE; // @[Metadata.scala:66:10]
wire [3:0] _r1_T_14 = 4'hE; // @[Metadata.scala:66:10]
wire [3:0] _r2_T_14 = 4'hE; // @[Metadata.scala:66:10]
wire [3:0] _state_r_T_14 = 4'hE; // @[Metadata.scala:66:10]
wire [3:0] _r_T_78 = 4'hE; // @[Metadata.scala:66:10]
wire [3:0] _r_T_137 = 4'hE; // @[Metadata.scala:66:10]
wire [3:0] _state_r_T_73 = 4'hE; // @[Metadata.scala:66:10]
wire [3:0] _grow_param_r_T_12 = 4'hF; // @[Metadata.scala:65:10]
wire [3:0] _r1_T_12 = 4'hF; // @[Metadata.scala:65:10]
wire [3:0] _r2_T_12 = 4'hF; // @[Metadata.scala:65:10]
wire [3:0] _state_r_T_12 = 4'hF; // @[Metadata.scala:65:10]
wire [3:0] io_mem_acquire_bits_a_mask_lo = 4'hF; // @[Misc.scala:222:10]
wire [3:0] io_mem_acquire_bits_a_mask_hi = 4'hF; // @[Misc.scala:222:10]
wire [3:0] _r_T_76 = 4'hF; // @[Metadata.scala:65:10]
wire [3:0] _r_T_135 = 4'hF; // @[Metadata.scala:65:10]
wire [3:0] _state_r_T_71 = 4'hF; // @[Metadata.scala:65:10]
wire [3:0] _r_T_11 = 4'h7; // @[Metadata.scala:126:10]
wire [3:0] _grow_param_r_T_8 = 4'h7; // @[Metadata.scala:63:10]
wire [3:0] _r1_T_8 = 4'h7; // @[Metadata.scala:63:10]
wire [3:0] _r2_T_8 = 4'h7; // @[Metadata.scala:63:10]
wire [3:0] _state_req_needs_wb_r_T_11 = 4'h7; // @[Metadata.scala:126:10]
wire [3:0] _state_r_T_8 = 4'h7; // @[Metadata.scala:63:10]
wire [3:0] _needs_wb_r_T_11 = 4'h7; // @[Metadata.scala:126:10]
wire [3:0] _r_T_72 = 4'h7; // @[Metadata.scala:63:10]
wire [3:0] _r_T_131 = 4'h7; // @[Metadata.scala:63:10]
wire [3:0] _state_req_needs_wb_r_T_75 = 4'h7; // @[Metadata.scala:126:10]
wire [3:0] _state_r_T_67 = 4'h7; // @[Metadata.scala:63:10]
wire [3:0] _r_T_9 = 4'h1; // @[Metadata.scala:124:10]
wire [3:0] _grow_param_r_T_6 = 4'h1; // @[Metadata.scala:62:10]
wire [3:0] _coh_on_grant_T_2 = 4'h1; // @[Metadata.scala:86:10]
wire [3:0] _r1_T_6 = 4'h1; // @[Metadata.scala:62:10]
wire [3:0] _r2_T_6 = 4'h1; // @[Metadata.scala:62:10]
wire [3:0] _state_req_needs_wb_r_T_9 = 4'h1; // @[Metadata.scala:124:10]
wire [3:0] _state_r_T_6 = 4'h1; // @[Metadata.scala:62:10]
wire [3:0] _needs_wb_r_T_9 = 4'h1; // @[Metadata.scala:124:10]
wire [3:0] _r_T_70 = 4'h1; // @[Metadata.scala:62:10]
wire [3:0] _r_T_129 = 4'h1; // @[Metadata.scala:62:10]
wire [3:0] _state_req_needs_wb_r_T_73 = 4'h1; // @[Metadata.scala:124:10]
wire [3:0] _state_r_T_65 = 4'h1; // @[Metadata.scala:62:10]
wire [3:0] _r_T_7 = 4'h3; // @[Metadata.scala:122:10]
wire [3:0] _grow_param_r_T_2 = 4'h3; // @[Metadata.scala:60:10]
wire [3:0] _r1_T_2 = 4'h3; // @[Metadata.scala:60:10]
wire [3:0] _r2_T_2 = 4'h3; // @[Metadata.scala:60:10]
wire [3:0] _state_req_needs_wb_r_T_7 = 4'h3; // @[Metadata.scala:122:10]
wire [3:0] _state_r_T_2 = 4'h3; // @[Metadata.scala:60:10]
wire [3:0] _needs_wb_r_T_7 = 4'h3; // @[Metadata.scala:122:10]
wire [3:0] _r_T_66 = 4'h3; // @[Metadata.scala:60:10]
wire [3:0] _r_T_125 = 4'h3; // @[Metadata.scala:60:10]
wire [3:0] _state_req_needs_wb_r_T_71 = 4'h3; // @[Metadata.scala:122:10]
wire [3:0] _state_r_T_61 = 4'h3; // @[Metadata.scala:60:10]
wire [3:0] _r_T_18 = 4'h8; // @[Metadata.scala:133:10]
wire [3:0] _state_req_needs_wb_r_T_18 = 4'h8; // @[Metadata.scala:133:10]
wire [3:0] _needs_wb_r_T_18 = 4'h8; // @[Metadata.scala:133:10]
wire [3:0] _state_req_needs_wb_r_T_82 = 4'h8; // @[Metadata.scala:133:10]
wire [3:0] _r_T_17 = 4'h9; // @[Metadata.scala:132:10]
wire [3:0] _state_req_needs_wb_r_T_17 = 4'h9; // @[Metadata.scala:132:10]
wire [3:0] _needs_wb_r_T_17 = 4'h9; // @[Metadata.scala:132:10]
wire [3:0] _state_req_needs_wb_r_T_81 = 4'h9; // @[Metadata.scala:132:10]
wire [3:0] _r_T_16 = 4'hA; // @[Metadata.scala:131:10]
wire [3:0] _state_req_needs_wb_r_T_16 = 4'hA; // @[Metadata.scala:131:10]
wire [3:0] _needs_wb_r_T_16 = 4'hA; // @[Metadata.scala:131:10]
wire [3:0] _state_req_needs_wb_r_T_80 = 4'hA; // @[Metadata.scala:131:10]
wire [3:0] _r_T_15 = 4'hB; // @[Metadata.scala:130:10]
wire [3:0] _state_req_needs_wb_r_T_15 = 4'hB; // @[Metadata.scala:130:10]
wire [3:0] _needs_wb_r_T_15 = 4'hB; // @[Metadata.scala:130:10]
wire [3:0] _state_req_needs_wb_r_T_79 = 4'hB; // @[Metadata.scala:130:10]
wire [1:0] _r_T_1 = 2'h2; // @[Metadata.scala:140:24]
wire [1:0] _r_T_3 = 2'h2; // @[Metadata.scala:140:24]
wire [1:0] _r_T_5 = 2'h2; // @[Metadata.scala:140:24]
wire [1:0] _state_req_needs_wb_r_T_1 = 2'h2; // @[Metadata.scala:140:24]
wire [1:0] _state_req_needs_wb_r_T_3 = 2'h2; // @[Metadata.scala:140:24]
wire [1:0] _state_req_needs_wb_r_T_5 = 2'h2; // @[Metadata.scala:140:24]
wire [1:0] io_mem_acquire_bits_a_mask_sizeOH_shiftAmount = 2'h2; // @[OneHot.scala:64:49]
wire [1:0] _needs_wb_r_T_1 = 2'h2; // @[Metadata.scala:140:24]
wire [1:0] _needs_wb_r_T_3 = 2'h2; // @[Metadata.scala:140:24]
wire [1:0] _needs_wb_r_T_5 = 2'h2; // @[Metadata.scala:140:24]
wire [1:0] _state_req_needs_wb_r_T_65 = 2'h2; // @[Metadata.scala:140:24]
wire [1:0] _state_req_needs_wb_r_T_67 = 2'h2; // @[Metadata.scala:140:24]
wire [1:0] _state_req_needs_wb_r_T_69 = 2'h2; // @[Metadata.scala:140:24]
wire [2:0] io_mem_acquire_bits_a_mask_sizeOH = 3'h5; // @[Misc.scala:202:81]
wire [2:0] _io_mem_acquire_bits_a_mask_sizeOH_T_2 = 3'h4; // @[OneHot.scala:65:27]
wire [1:0] _grow_param_r_T_7 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _grow_param_r_T_9 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _grow_param_r_T_17 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _grow_param_r_T_19 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _coh_on_grant_T_5 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _r1_T_7 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _r1_T_9 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _r1_T_17 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _r1_T_19 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _r2_T_7 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _r2_T_9 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _r2_T_17 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _r2_T_19 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _state_r_T_7 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _state_r_T_9 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _state_r_T_17 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _state_r_T_19 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _r_T_71 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _r_T_73 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _r_T_81 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _r_T_83 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _r_T_130 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _r_T_132 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _r_T_140 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _r_T_142 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _state_r_T_66 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _state_r_T_68 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _state_r_T_76 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _state_r_T_78 = 2'h1; // @[Metadata.scala:25:15]
wire _io_req_sec_rdy_T; // @[mshrs.scala:159:37]
wire _io_idx_valid_T; // @[mshrs.scala:149:25]
wire [3:0] req_idx; // @[mshrs.scala:110:25]
wire _io_way_valid_T_3; // @[mshrs.scala:151:19]
wire _io_tag_valid_T; // @[mshrs.scala:150:25]
wire [23:0] req_tag; // @[mshrs.scala:111:26]
wire [2:0] io_mem_acquire_bits_a_param; // @[Edges.scala:346:17]
wire [31:0] io_mem_acquire_bits_a_address; // @[Edges.scala:346:17]
wire [2:0] grantack_bits_e_sink = io_mem_grant_bits_sink_0; // @[Edges.scala:451:17]
wire [63:0] io_lb_write_bits_data_0 = io_mem_grant_bits_data_0; // @[mshrs.scala:36:7]
wire [2:0] shrink_param; // @[Misc.scala:38:36]
wire [1:0] coh_on_grant_state; // @[Metadata.scala:160:20]
wire [63:0] io_refill_bits_data_0 = io_lb_resp_0; // @[mshrs.scala:36:7]
wire [63:0] data_word = io_lb_resp_0; // @[mshrs.scala:36:7, :264:26]
wire [33:0] _io_replay_bits_addr_T_1; // @[mshrs.scala:353:31]
wire [63:0] _io_resp_bits_data_T_23; // @[AMOALU.scala:45:16]
wire _io_probe_rdy_T_11; // @[mshrs.scala:148:42]
wire io_idx_valid_0; // @[mshrs.scala:36:7]
wire [3:0] io_idx_bits_0; // @[mshrs.scala:36:7]
wire io_way_valid_0; // @[mshrs.scala:36:7]
wire [1:0] io_way_bits_0; // @[mshrs.scala:36:7]
wire io_tag_valid_0; // @[mshrs.scala:36:7]
wire [23:0] io_tag_bits_0; // @[mshrs.scala:36:7]
wire [2:0] io_mem_acquire_bits_param_0; // @[mshrs.scala:36:7]
wire [31:0] io_mem_acquire_bits_address_0; // @[mshrs.scala:36:7]
wire io_mem_acquire_valid_0; // @[mshrs.scala:36:7]
wire io_mem_grant_ready_0; // @[mshrs.scala:36:7]
wire [2:0] io_mem_finish_bits_sink_0; // @[mshrs.scala:36:7]
wire io_mem_finish_valid_0; // @[mshrs.scala:36:7]
wire [1:0] io_refill_bits_way_en_0; // @[mshrs.scala:36:7]
wire [9:0] io_refill_bits_addr_0; // @[mshrs.scala:36:7]
wire io_refill_valid_0; // @[mshrs.scala:36:7]
wire [1:0] io_meta_write_bits_data_coh_state_0; // @[mshrs.scala:36:7]
wire [21:0] io_meta_write_bits_data_tag_0; // @[mshrs.scala:36:7]
wire [3:0] io_meta_write_bits_idx_0; // @[mshrs.scala:36:7]
wire [1:0] io_meta_write_bits_way_en_0; // @[mshrs.scala:36:7]
wire io_meta_write_valid_0; // @[mshrs.scala:36:7]
wire [3:0] io_meta_read_bits_idx_0; // @[mshrs.scala:36:7]
wire [1:0] io_meta_read_bits_way_en_0; // @[mshrs.scala:36:7]
wire [21:0] io_meta_read_bits_tag_0; // @[mshrs.scala:36:7]
wire io_meta_read_valid_0; // @[mshrs.scala:36:7]
wire [21:0] io_wb_req_bits_tag_0; // @[mshrs.scala:36:7]
wire [3:0] io_wb_req_bits_idx_0; // @[mshrs.scala:36:7]
wire [2:0] io_wb_req_bits_param_0; // @[mshrs.scala:36:7]
wire [1:0] io_wb_req_bits_way_en_0; // @[mshrs.scala:36:7]
wire io_wb_req_valid_0; // @[mshrs.scala:36:7]
wire [1:0] io_commit_coh_state_0; // @[mshrs.scala:36:7]
wire [2:0] io_lb_read_bits_offset_0; // @[mshrs.scala:36:7]
wire io_lb_read_valid_0; // @[mshrs.scala:36:7]
wire [2:0] io_lb_write_bits_offset_0; // @[mshrs.scala:36:7]
wire io_lb_write_valid_0; // @[mshrs.scala:36:7]
wire [3:0] io_replay_bits_uop_ctrl_br_type_0; // @[mshrs.scala:36:7]
wire [1:0] io_replay_bits_uop_ctrl_op1_sel_0; // @[mshrs.scala:36:7]
wire [2:0] io_replay_bits_uop_ctrl_op2_sel_0; // @[mshrs.scala:36:7]
wire [2:0] io_replay_bits_uop_ctrl_imm_sel_0; // @[mshrs.scala:36:7]
wire [4:0] io_replay_bits_uop_ctrl_op_fcn_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_ctrl_fcn_dw_0; // @[mshrs.scala:36:7]
wire [2:0] io_replay_bits_uop_ctrl_csr_cmd_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_ctrl_is_load_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_ctrl_is_sta_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_ctrl_is_std_0; // @[mshrs.scala:36:7]
wire [6:0] io_replay_bits_uop_uopc_0; // @[mshrs.scala:36:7]
wire [31:0] io_replay_bits_uop_inst_0; // @[mshrs.scala:36:7]
wire [31:0] io_replay_bits_uop_debug_inst_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_is_rvc_0; // @[mshrs.scala:36:7]
wire [33:0] io_replay_bits_uop_debug_pc_0; // @[mshrs.scala:36:7]
wire [2:0] io_replay_bits_uop_iq_type_0; // @[mshrs.scala:36:7]
wire [9:0] io_replay_bits_uop_fu_code_0; // @[mshrs.scala:36:7]
wire [1:0] io_replay_bits_uop_iw_state_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_iw_p1_poisoned_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_iw_p2_poisoned_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_is_br_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_is_jalr_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_is_jal_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_is_sfb_0; // @[mshrs.scala:36:7]
wire [3:0] io_replay_bits_uop_br_mask_0; // @[mshrs.scala:36:7]
wire [1:0] io_replay_bits_uop_br_tag_0; // @[mshrs.scala:36:7]
wire [3:0] io_replay_bits_uop_ftq_idx_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_edge_inst_0; // @[mshrs.scala:36:7]
wire [5:0] io_replay_bits_uop_pc_lob_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_taken_0; // @[mshrs.scala:36:7]
wire [19:0] io_replay_bits_uop_imm_packed_0; // @[mshrs.scala:36:7]
wire [11:0] io_replay_bits_uop_csr_addr_0; // @[mshrs.scala:36:7]
wire [5:0] io_replay_bits_uop_rob_idx_0; // @[mshrs.scala:36:7]
wire [3:0] io_replay_bits_uop_ldq_idx_0; // @[mshrs.scala:36:7]
wire [3:0] io_replay_bits_uop_stq_idx_0; // @[mshrs.scala:36:7]
wire [1:0] io_replay_bits_uop_rxq_idx_0; // @[mshrs.scala:36:7]
wire [6:0] io_replay_bits_uop_pdst_0; // @[mshrs.scala:36:7]
wire [6:0] io_replay_bits_uop_prs1_0; // @[mshrs.scala:36:7]
wire [6:0] io_replay_bits_uop_prs2_0; // @[mshrs.scala:36:7]
wire [6:0] io_replay_bits_uop_prs3_0; // @[mshrs.scala:36:7]
wire [3:0] io_replay_bits_uop_ppred_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_prs1_busy_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_prs2_busy_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_prs3_busy_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_ppred_busy_0; // @[mshrs.scala:36:7]
wire [6:0] io_replay_bits_uop_stale_pdst_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_exception_0; // @[mshrs.scala:36:7]
wire [63:0] io_replay_bits_uop_exc_cause_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_bypassable_0; // @[mshrs.scala:36:7]
wire [4:0] io_replay_bits_uop_mem_cmd_0; // @[mshrs.scala:36:7]
wire [1:0] io_replay_bits_uop_mem_size_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_mem_signed_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_is_fence_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_is_fencei_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_is_amo_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_uses_ldq_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_uses_stq_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_is_sys_pc2epc_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_is_unique_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_flush_on_commit_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_ldst_is_rs1_0; // @[mshrs.scala:36:7]
wire [5:0] io_replay_bits_uop_ldst_0; // @[mshrs.scala:36:7]
wire [5:0] io_replay_bits_uop_lrs1_0; // @[mshrs.scala:36:7]
wire [5:0] io_replay_bits_uop_lrs2_0; // @[mshrs.scala:36:7]
wire [5:0] io_replay_bits_uop_lrs3_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_ldst_val_0; // @[mshrs.scala:36:7]
wire [1:0] io_replay_bits_uop_dst_rtype_0; // @[mshrs.scala:36:7]
wire [1:0] io_replay_bits_uop_lrs1_rtype_0; // @[mshrs.scala:36:7]
wire [1:0] io_replay_bits_uop_lrs2_rtype_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_frs3_en_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_fp_val_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_fp_single_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_xcpt_pf_if_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_xcpt_ae_if_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_xcpt_ma_if_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_bp_debug_if_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_bp_xcpt_if_0; // @[mshrs.scala:36:7]
wire [1:0] io_replay_bits_uop_debug_fsrc_0; // @[mshrs.scala:36:7]
wire [1:0] io_replay_bits_uop_debug_tsrc_0; // @[mshrs.scala:36:7]
wire [1:0] io_replay_bits_old_meta_coh_state_0; // @[mshrs.scala:36:7]
wire [21:0] io_replay_bits_old_meta_tag_0; // @[mshrs.scala:36:7]
wire [33:0] io_replay_bits_addr_0; // @[mshrs.scala:36:7]
wire [63:0] io_replay_bits_data_0; // @[mshrs.scala:36:7]
wire io_replay_bits_is_hella_0; // @[mshrs.scala:36:7]
wire io_replay_bits_tag_match_0; // @[mshrs.scala:36:7]
wire [1:0] io_replay_bits_way_en_0; // @[mshrs.scala:36:7]
wire [4:0] io_replay_bits_sdq_id_0; // @[mshrs.scala:36:7]
wire io_replay_valid_0; // @[mshrs.scala:36:7]
wire [3:0] io_resp_bits_uop_ctrl_br_type_0; // @[mshrs.scala:36:7]
wire [1:0] io_resp_bits_uop_ctrl_op1_sel_0; // @[mshrs.scala:36:7]
wire [2:0] io_resp_bits_uop_ctrl_op2_sel_0; // @[mshrs.scala:36:7]
wire [2:0] io_resp_bits_uop_ctrl_imm_sel_0; // @[mshrs.scala:36:7]
wire [4:0] io_resp_bits_uop_ctrl_op_fcn_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_ctrl_fcn_dw_0; // @[mshrs.scala:36:7]
wire [2:0] io_resp_bits_uop_ctrl_csr_cmd_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_ctrl_is_load_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_ctrl_is_sta_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_ctrl_is_std_0; // @[mshrs.scala:36:7]
wire [6:0] io_resp_bits_uop_uopc_0; // @[mshrs.scala:36:7]
wire [31:0] io_resp_bits_uop_inst_0; // @[mshrs.scala:36:7]
wire [31:0] io_resp_bits_uop_debug_inst_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_is_rvc_0; // @[mshrs.scala:36:7]
wire [33:0] io_resp_bits_uop_debug_pc_0; // @[mshrs.scala:36:7]
wire [2:0] io_resp_bits_uop_iq_type_0; // @[mshrs.scala:36:7]
wire [9:0] io_resp_bits_uop_fu_code_0; // @[mshrs.scala:36:7]
wire [1:0] io_resp_bits_uop_iw_state_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_iw_p1_poisoned_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_iw_p2_poisoned_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_is_br_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_is_jalr_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_is_jal_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_is_sfb_0; // @[mshrs.scala:36:7]
wire [3:0] io_resp_bits_uop_br_mask_0; // @[mshrs.scala:36:7]
wire [1:0] io_resp_bits_uop_br_tag_0; // @[mshrs.scala:36:7]
wire [3:0] io_resp_bits_uop_ftq_idx_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_edge_inst_0; // @[mshrs.scala:36:7]
wire [5:0] io_resp_bits_uop_pc_lob_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_taken_0; // @[mshrs.scala:36:7]
wire [19:0] io_resp_bits_uop_imm_packed_0; // @[mshrs.scala:36:7]
wire [11:0] io_resp_bits_uop_csr_addr_0; // @[mshrs.scala:36:7]
wire [5:0] io_resp_bits_uop_rob_idx_0; // @[mshrs.scala:36:7]
wire [3:0] io_resp_bits_uop_ldq_idx_0; // @[mshrs.scala:36:7]
wire [3:0] io_resp_bits_uop_stq_idx_0; // @[mshrs.scala:36:7]
wire [1:0] io_resp_bits_uop_rxq_idx_0; // @[mshrs.scala:36:7]
wire [6:0] io_resp_bits_uop_pdst_0; // @[mshrs.scala:36:7]
wire [6:0] io_resp_bits_uop_prs1_0; // @[mshrs.scala:36:7]
wire [6:0] io_resp_bits_uop_prs2_0; // @[mshrs.scala:36:7]
wire [6:0] io_resp_bits_uop_prs3_0; // @[mshrs.scala:36:7]
wire [3:0] io_resp_bits_uop_ppred_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_prs1_busy_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_prs2_busy_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_prs3_busy_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_ppred_busy_0; // @[mshrs.scala:36:7]
wire [6:0] io_resp_bits_uop_stale_pdst_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_exception_0; // @[mshrs.scala:36:7]
wire [63:0] io_resp_bits_uop_exc_cause_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_bypassable_0; // @[mshrs.scala:36:7]
wire [4:0] io_resp_bits_uop_mem_cmd_0; // @[mshrs.scala:36:7]
wire [1:0] io_resp_bits_uop_mem_size_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_mem_signed_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_is_fence_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_is_fencei_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_is_amo_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_uses_ldq_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_uses_stq_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_is_sys_pc2epc_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_is_unique_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_flush_on_commit_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_ldst_is_rs1_0; // @[mshrs.scala:36:7]
wire [5:0] io_resp_bits_uop_ldst_0; // @[mshrs.scala:36:7]
wire [5:0] io_resp_bits_uop_lrs1_0; // @[mshrs.scala:36:7]
wire [5:0] io_resp_bits_uop_lrs2_0; // @[mshrs.scala:36:7]
wire [5:0] io_resp_bits_uop_lrs3_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_ldst_val_0; // @[mshrs.scala:36:7]
wire [1:0] io_resp_bits_uop_dst_rtype_0; // @[mshrs.scala:36:7]
wire [1:0] io_resp_bits_uop_lrs1_rtype_0; // @[mshrs.scala:36:7]
wire [1:0] io_resp_bits_uop_lrs2_rtype_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_frs3_en_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_fp_val_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_fp_single_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_xcpt_pf_if_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_xcpt_ae_if_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_xcpt_ma_if_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_bp_debug_if_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_bp_xcpt_if_0; // @[mshrs.scala:36:7]
wire [1:0] io_resp_bits_uop_debug_fsrc_0; // @[mshrs.scala:36:7]
wire [1:0] io_resp_bits_uop_debug_tsrc_0; // @[mshrs.scala:36:7]
wire [63:0] io_resp_bits_data_0; // @[mshrs.scala:36:7]
wire io_resp_bits_is_hella_0; // @[mshrs.scala:36:7]
wire io_resp_valid_0; // @[mshrs.scala:36:7]
wire io_req_pri_rdy_0; // @[mshrs.scala:36:7]
wire io_req_sec_rdy_0; // @[mshrs.scala:36:7]
wire io_commit_val_0; // @[mshrs.scala:36:7]
wire [33:0] io_commit_addr_0; // @[mshrs.scala:36:7]
wire io_probe_rdy_0; // @[mshrs.scala:36:7]
reg [4:0] state; // @[mshrs.scala:107:22]
reg [6:0] req_uop_uopc; // @[mshrs.scala:109:20]
reg [31:0] req_uop_inst; // @[mshrs.scala:109:20]
reg [31:0] req_uop_debug_inst; // @[mshrs.scala:109:20]
reg req_uop_is_rvc; // @[mshrs.scala:109:20]
reg [33:0] req_uop_debug_pc; // @[mshrs.scala:109:20]
reg [2:0] req_uop_iq_type; // @[mshrs.scala:109:20]
reg [9:0] req_uop_fu_code; // @[mshrs.scala:109:20]
reg [3:0] req_uop_ctrl_br_type; // @[mshrs.scala:109:20]
reg [1:0] req_uop_ctrl_op1_sel; // @[mshrs.scala:109:20]
reg [2:0] req_uop_ctrl_op2_sel; // @[mshrs.scala:109:20]
reg [2:0] req_uop_ctrl_imm_sel; // @[mshrs.scala:109:20]
reg [4:0] req_uop_ctrl_op_fcn; // @[mshrs.scala:109:20]
reg req_uop_ctrl_fcn_dw; // @[mshrs.scala:109:20]
reg [2:0] req_uop_ctrl_csr_cmd; // @[mshrs.scala:109:20]
reg req_uop_ctrl_is_load; // @[mshrs.scala:109:20]
reg req_uop_ctrl_is_sta; // @[mshrs.scala:109:20]
reg req_uop_ctrl_is_std; // @[mshrs.scala:109:20]
reg [1:0] req_uop_iw_state; // @[mshrs.scala:109:20]
reg req_uop_iw_p1_poisoned; // @[mshrs.scala:109:20]
reg req_uop_iw_p2_poisoned; // @[mshrs.scala:109:20]
reg req_uop_is_br; // @[mshrs.scala:109:20]
reg req_uop_is_jalr; // @[mshrs.scala:109:20]
reg req_uop_is_jal; // @[mshrs.scala:109:20]
reg req_uop_is_sfb; // @[mshrs.scala:109:20]
reg [3:0] req_uop_br_mask; // @[mshrs.scala:109:20]
reg [1:0] req_uop_br_tag; // @[mshrs.scala:109:20]
reg [3:0] req_uop_ftq_idx; // @[mshrs.scala:109:20]
reg req_uop_edge_inst; // @[mshrs.scala:109:20]
reg [5:0] req_uop_pc_lob; // @[mshrs.scala:109:20]
reg req_uop_taken; // @[mshrs.scala:109:20]
reg [19:0] req_uop_imm_packed; // @[mshrs.scala:109:20]
reg [11:0] req_uop_csr_addr; // @[mshrs.scala:109:20]
reg [5:0] req_uop_rob_idx; // @[mshrs.scala:109:20]
reg [3:0] req_uop_ldq_idx; // @[mshrs.scala:109:20]
reg [3:0] req_uop_stq_idx; // @[mshrs.scala:109:20]
reg [1:0] req_uop_rxq_idx; // @[mshrs.scala:109:20]
reg [6:0] req_uop_pdst; // @[mshrs.scala:109:20]
reg [6:0] req_uop_prs1; // @[mshrs.scala:109:20]
reg [6:0] req_uop_prs2; // @[mshrs.scala:109:20]
reg [6:0] req_uop_prs3; // @[mshrs.scala:109:20]
reg [3:0] req_uop_ppred; // @[mshrs.scala:109:20]
reg req_uop_prs1_busy; // @[mshrs.scala:109:20]
reg req_uop_prs2_busy; // @[mshrs.scala:109:20]
reg req_uop_prs3_busy; // @[mshrs.scala:109:20]
reg req_uop_ppred_busy; // @[mshrs.scala:109:20]
reg [6:0] req_uop_stale_pdst; // @[mshrs.scala:109:20]
reg req_uop_exception; // @[mshrs.scala:109:20]
reg [63:0] req_uop_exc_cause; // @[mshrs.scala:109:20]
reg req_uop_bypassable; // @[mshrs.scala:109:20]
reg [4:0] req_uop_mem_cmd; // @[mshrs.scala:109:20]
reg [1:0] req_uop_mem_size; // @[mshrs.scala:109:20]
reg req_uop_mem_signed; // @[mshrs.scala:109:20]
reg req_uop_is_fence; // @[mshrs.scala:109:20]
reg req_uop_is_fencei; // @[mshrs.scala:109:20]
reg req_uop_is_amo; // @[mshrs.scala:109:20]
reg req_uop_uses_ldq; // @[mshrs.scala:109:20]
reg req_uop_uses_stq; // @[mshrs.scala:109:20]
reg req_uop_is_sys_pc2epc; // @[mshrs.scala:109:20]
reg req_uop_is_unique; // @[mshrs.scala:109:20]
reg req_uop_flush_on_commit; // @[mshrs.scala:109:20]
reg req_uop_ldst_is_rs1; // @[mshrs.scala:109:20]
reg [5:0] req_uop_ldst; // @[mshrs.scala:109:20]
reg [5:0] req_uop_lrs1; // @[mshrs.scala:109:20]
reg [5:0] req_uop_lrs2; // @[mshrs.scala:109:20]
reg [5:0] req_uop_lrs3; // @[mshrs.scala:109:20]
reg req_uop_ldst_val; // @[mshrs.scala:109:20]
reg [1:0] req_uop_dst_rtype; // @[mshrs.scala:109:20]
reg [1:0] req_uop_lrs1_rtype; // @[mshrs.scala:109:20]
reg [1:0] req_uop_lrs2_rtype; // @[mshrs.scala:109:20]
reg req_uop_frs3_en; // @[mshrs.scala:109:20]
reg req_uop_fp_val; // @[mshrs.scala:109:20]
reg req_uop_fp_single; // @[mshrs.scala:109:20]
reg req_uop_xcpt_pf_if; // @[mshrs.scala:109:20]
reg req_uop_xcpt_ae_if; // @[mshrs.scala:109:20]
reg req_uop_xcpt_ma_if; // @[mshrs.scala:109:20]
reg req_uop_bp_debug_if; // @[mshrs.scala:109:20]
reg req_uop_bp_xcpt_if; // @[mshrs.scala:109:20]
reg [1:0] req_uop_debug_fsrc; // @[mshrs.scala:109:20]
reg [1:0] req_uop_debug_tsrc; // @[mshrs.scala:109:20]
reg [33:0] req_addr; // @[mshrs.scala:109:20]
assign io_commit_addr_0 = req_addr; // @[mshrs.scala:36:7, :109:20]
reg [63:0] req_data; // @[mshrs.scala:109:20]
reg req_is_hella; // @[mshrs.scala:109:20]
reg req_tag_match; // @[mshrs.scala:109:20]
reg [1:0] req_old_meta_coh_state; // @[mshrs.scala:109:20]
reg [21:0] req_old_meta_tag; // @[mshrs.scala:109:20]
assign io_wb_req_bits_tag_0 = req_old_meta_tag; // @[mshrs.scala:36:7, :109:20]
reg [1:0] req_way_en; // @[mshrs.scala:109:20]
assign io_way_bits_0 = req_way_en; // @[mshrs.scala:36:7, :109:20]
assign io_refill_bits_way_en_0 = req_way_en; // @[mshrs.scala:36:7, :109:20]
assign io_meta_write_bits_way_en_0 = req_way_en; // @[mshrs.scala:36:7, :109:20]
assign io_meta_read_bits_way_en_0 = req_way_en; // @[mshrs.scala:36:7, :109:20]
assign io_wb_req_bits_way_en_0 = req_way_en; // @[mshrs.scala:36:7, :109:20]
assign io_replay_bits_way_en_0 = req_way_en; // @[mshrs.scala:36:7, :109:20]
reg [4:0] req_sdq_id; // @[mshrs.scala:109:20]
assign req_idx = req_addr[9:6]; // @[mshrs.scala:109:20, :110:25]
assign io_idx_bits_0 = req_idx; // @[mshrs.scala:36:7, :110:25]
assign io_meta_write_bits_idx_0 = req_idx; // @[mshrs.scala:36:7, :110:25]
assign io_meta_read_bits_idx_0 = req_idx; // @[mshrs.scala:36:7, :110:25]
assign io_wb_req_bits_idx_0 = req_idx; // @[mshrs.scala:36:7, :110:25]
assign req_tag = req_addr[33:10]; // @[mshrs.scala:109:20, :111:26]
assign io_tag_bits_0 = req_tag; // @[mshrs.scala:36:7, :111:26]
wire [27:0] _req_block_addr_T = req_addr[33:6]; // @[mshrs.scala:109:20, :112:34]
wire [33:0] req_block_addr = {_req_block_addr_T, 6'h0}; // @[mshrs.scala:112:{34,51}]
reg req_needs_wb; // @[mshrs.scala:113:29]
reg [1:0] new_coh_state; // @[mshrs.scala:115:24]
wire [3:0] _r_T_6 = {2'h2, req_old_meta_coh_state}; // @[Metadata.scala:120:19]
wire _r_T_19 = _r_T_6 == 4'h8; // @[Misc.scala:56:20]
wire [2:0] _r_T_21 = _r_T_19 ? 3'h5 : 3'h0; // @[Misc.scala:38:36, :56:20]
wire _r_T_23 = _r_T_6 == 4'h9; // @[Misc.scala:56:20]
wire [2:0] _r_T_25 = _r_T_23 ? 3'h2 : _r_T_21; // @[Misc.scala:38:36, :56:20]
wire _r_T_27 = _r_T_6 == 4'hA; // @[Misc.scala:56:20]
wire [2:0] _r_T_29 = _r_T_27 ? 3'h1 : _r_T_25; // @[Misc.scala:38:36, :56:20]
wire _r_T_31 = _r_T_6 == 4'hB; // @[Misc.scala:56:20]
wire _r_T_32 = _r_T_31; // @[Misc.scala:38:9, :56:20]
wire [2:0] _r_T_33 = _r_T_31 ? 3'h1 : _r_T_29; // @[Misc.scala:38:36, :56:20]
wire _r_T_35 = _r_T_6 == 4'h4; // @[Misc.scala:56:20]
wire _r_T_36 = ~_r_T_35 & _r_T_32; // @[Misc.scala:38:9, :56:20]
wire [2:0] _r_T_37 = _r_T_35 ? 3'h5 : _r_T_33; // @[Misc.scala:38:36, :56:20]
wire _r_T_39 = _r_T_6 == 4'h5; // @[Misc.scala:56:20]
wire _r_T_40 = ~_r_T_39 & _r_T_36; // @[Misc.scala:38:9, :56:20]
wire [2:0] _r_T_41 = _r_T_39 ? 3'h4 : _r_T_37; // @[Misc.scala:38:36, :56:20]
wire [1:0] _r_T_42 = {1'h0, _r_T_39}; // @[Misc.scala:38:63, :56:20]
wire _r_T_43 = _r_T_6 == 4'h6; // @[Misc.scala:56:20]
wire _r_T_44 = ~_r_T_43 & _r_T_40; // @[Misc.scala:38:9, :56:20]
wire [2:0] _r_T_45 = _r_T_43 ? 3'h0 : _r_T_41; // @[Misc.scala:38:36, :56:20]
wire [1:0] _r_T_46 = _r_T_43 ? 2'h1 : _r_T_42; // @[Misc.scala:38:63, :56:20]
wire _r_T_47 = _r_T_6 == 4'h7; // @[Misc.scala:56:20]
wire _r_T_48 = _r_T_47 | _r_T_44; // @[Misc.scala:38:9, :56:20]
wire [2:0] _r_T_49 = _r_T_47 ? 3'h0 : _r_T_45; // @[Misc.scala:38:36, :56:20]
wire [1:0] _r_T_50 = _r_T_47 ? 2'h1 : _r_T_46; // @[Misc.scala:38:63, :56:20]
wire _r_T_51 = _r_T_6 == 4'h0; // @[Misc.scala:56:20]
wire _r_T_52 = ~_r_T_51 & _r_T_48; // @[Misc.scala:38:9, :56:20]
wire [2:0] _r_T_53 = _r_T_51 ? 3'h5 : _r_T_49; // @[Misc.scala:38:36, :56:20]
wire [1:0] _r_T_54 = _r_T_51 ? 2'h0 : _r_T_50; // @[Misc.scala:38:63, :56:20]
wire _r_T_55 = _r_T_6 == 4'h1; // @[Misc.scala:56:20]
wire _r_T_56 = ~_r_T_55 & _r_T_52; // @[Misc.scala:38:9, :56:20]
wire [2:0] _r_T_57 = _r_T_55 ? 3'h4 : _r_T_53; // @[Misc.scala:38:36, :56:20]
wire [1:0] _r_T_58 = _r_T_55 ? 2'h1 : _r_T_54; // @[Misc.scala:38:63, :56:20]
wire _r_T_59 = _r_T_6 == 4'h2; // @[Misc.scala:56:20]
wire _r_T_60 = ~_r_T_59 & _r_T_56; // @[Misc.scala:38:9, :56:20]
wire [2:0] _r_T_61 = _r_T_59 ? 3'h3 : _r_T_57; // @[Misc.scala:38:36, :56:20]
wire [1:0] _r_T_62 = _r_T_59 ? 2'h2 : _r_T_58; // @[Misc.scala:38:63, :56:20]
wire _r_T_63 = _r_T_6 == 4'h3; // @[Misc.scala:56:20]
wire r_1 = _r_T_63 | _r_T_60; // @[Misc.scala:38:9, :56:20]
assign shrink_param = _r_T_63 ? 3'h3 : _r_T_61; // @[Misc.scala:38:36, :56:20]
assign io_wb_req_bits_param_0 = shrink_param; // @[Misc.scala:38:36]
wire [1:0] r_3 = _r_T_63 ? 2'h2 : _r_T_62; // @[Misc.scala:38:63, :56:20]
wire [1:0] coh_on_clear_state = r_3; // @[Misc.scala:38:63]
wire _GEN = req_uop_mem_cmd == 5'h1; // @[Consts.scala:90:32]
wire _grow_param_r_c_cat_T; // @[Consts.scala:90:32]
assign _grow_param_r_c_cat_T = _GEN; // @[Consts.scala:90:32]
wire _grow_param_r_c_cat_T_23; // @[Consts.scala:90:32]
assign _grow_param_r_c_cat_T_23 = _GEN; // @[Consts.scala:90:32]
wire _coh_on_grant_c_cat_T; // @[Consts.scala:90:32]
assign _coh_on_grant_c_cat_T = _GEN; // @[Consts.scala:90:32]
wire _coh_on_grant_c_cat_T_23; // @[Consts.scala:90:32]
assign _coh_on_grant_c_cat_T_23 = _GEN; // @[Consts.scala:90:32]
wire _r1_c_cat_T; // @[Consts.scala:90:32]
assign _r1_c_cat_T = _GEN; // @[Consts.scala:90:32]
wire _r1_c_cat_T_23; // @[Consts.scala:90:32]
assign _r1_c_cat_T_23 = _GEN; // @[Consts.scala:90:32]
wire _needs_second_acq_T_27; // @[Consts.scala:90:32]
assign _needs_second_acq_T_27 = _GEN; // @[Consts.scala:90:32]
wire _GEN_0 = req_uop_mem_cmd == 5'h11; // @[Consts.scala:90:49]
wire _grow_param_r_c_cat_T_1; // @[Consts.scala:90:49]
assign _grow_param_r_c_cat_T_1 = _GEN_0; // @[Consts.scala:90:49]
wire _grow_param_r_c_cat_T_24; // @[Consts.scala:90:49]
assign _grow_param_r_c_cat_T_24 = _GEN_0; // @[Consts.scala:90:49]
wire _coh_on_grant_c_cat_T_1; // @[Consts.scala:90:49]
assign _coh_on_grant_c_cat_T_1 = _GEN_0; // @[Consts.scala:90:49]
wire _coh_on_grant_c_cat_T_24; // @[Consts.scala:90:49]
assign _coh_on_grant_c_cat_T_24 = _GEN_0; // @[Consts.scala:90:49]
wire _r1_c_cat_T_1; // @[Consts.scala:90:49]
assign _r1_c_cat_T_1 = _GEN_0; // @[Consts.scala:90:49]
wire _r1_c_cat_T_24; // @[Consts.scala:90:49]
assign _r1_c_cat_T_24 = _GEN_0; // @[Consts.scala:90:49]
wire _needs_second_acq_T_28; // @[Consts.scala:90:49]
assign _needs_second_acq_T_28 = _GEN_0; // @[Consts.scala:90:49]
wire _grow_param_r_c_cat_T_2 = _grow_param_r_c_cat_T | _grow_param_r_c_cat_T_1; // @[Consts.scala:90:{32,42,49}]
wire _GEN_1 = req_uop_mem_cmd == 5'h7; // @[Consts.scala:90:66]
wire _grow_param_r_c_cat_T_3; // @[Consts.scala:90:66]
assign _grow_param_r_c_cat_T_3 = _GEN_1; // @[Consts.scala:90:66]
wire _grow_param_r_c_cat_T_26; // @[Consts.scala:90:66]
assign _grow_param_r_c_cat_T_26 = _GEN_1; // @[Consts.scala:90:66]
wire _coh_on_grant_c_cat_T_3; // @[Consts.scala:90:66]
assign _coh_on_grant_c_cat_T_3 = _GEN_1; // @[Consts.scala:90:66]
wire _coh_on_grant_c_cat_T_26; // @[Consts.scala:90:66]
assign _coh_on_grant_c_cat_T_26 = _GEN_1; // @[Consts.scala:90:66]
wire _r1_c_cat_T_3; // @[Consts.scala:90:66]
assign _r1_c_cat_T_3 = _GEN_1; // @[Consts.scala:90:66]
wire _r1_c_cat_T_26; // @[Consts.scala:90:66]
assign _r1_c_cat_T_26 = _GEN_1; // @[Consts.scala:90:66]
wire _needs_second_acq_T_30; // @[Consts.scala:90:66]
assign _needs_second_acq_T_30 = _GEN_1; // @[Consts.scala:90:66]
wire _grow_param_r_c_cat_T_4 = _grow_param_r_c_cat_T_2 | _grow_param_r_c_cat_T_3; // @[Consts.scala:90:{42,59,66}]
wire _GEN_2 = req_uop_mem_cmd == 5'h4; // @[package.scala:16:47]
wire _grow_param_r_c_cat_T_5; // @[package.scala:16:47]
assign _grow_param_r_c_cat_T_5 = _GEN_2; // @[package.scala:16:47]
wire _grow_param_r_c_cat_T_28; // @[package.scala:16:47]
assign _grow_param_r_c_cat_T_28 = _GEN_2; // @[package.scala:16:47]
wire _coh_on_grant_c_cat_T_5; // @[package.scala:16:47]
assign _coh_on_grant_c_cat_T_5 = _GEN_2; // @[package.scala:16:47]
wire _coh_on_grant_c_cat_T_28; // @[package.scala:16:47]
assign _coh_on_grant_c_cat_T_28 = _GEN_2; // @[package.scala:16:47]
wire _r1_c_cat_T_5; // @[package.scala:16:47]
assign _r1_c_cat_T_5 = _GEN_2; // @[package.scala:16:47]
wire _r1_c_cat_T_28; // @[package.scala:16:47]
assign _r1_c_cat_T_28 = _GEN_2; // @[package.scala:16:47]
wire _needs_second_acq_T_32; // @[package.scala:16:47]
assign _needs_second_acq_T_32 = _GEN_2; // @[package.scala:16:47]
wire _GEN_3 = req_uop_mem_cmd == 5'h9; // @[package.scala:16:47]
wire _grow_param_r_c_cat_T_6; // @[package.scala:16:47]
assign _grow_param_r_c_cat_T_6 = _GEN_3; // @[package.scala:16:47]
wire _grow_param_r_c_cat_T_29; // @[package.scala:16:47]
assign _grow_param_r_c_cat_T_29 = _GEN_3; // @[package.scala:16:47]
wire _coh_on_grant_c_cat_T_6; // @[package.scala:16:47]
assign _coh_on_grant_c_cat_T_6 = _GEN_3; // @[package.scala:16:47]
wire _coh_on_grant_c_cat_T_29; // @[package.scala:16:47]
assign _coh_on_grant_c_cat_T_29 = _GEN_3; // @[package.scala:16:47]
wire _r1_c_cat_T_6; // @[package.scala:16:47]
assign _r1_c_cat_T_6 = _GEN_3; // @[package.scala:16:47]
wire _r1_c_cat_T_29; // @[package.scala:16:47]
assign _r1_c_cat_T_29 = _GEN_3; // @[package.scala:16:47]
wire _needs_second_acq_T_33; // @[package.scala:16:47]
assign _needs_second_acq_T_33 = _GEN_3; // @[package.scala:16:47]
wire _GEN_4 = req_uop_mem_cmd == 5'hA; // @[package.scala:16:47]
wire _grow_param_r_c_cat_T_7; // @[package.scala:16:47]
assign _grow_param_r_c_cat_T_7 = _GEN_4; // @[package.scala:16:47]
wire _grow_param_r_c_cat_T_30; // @[package.scala:16:47]
assign _grow_param_r_c_cat_T_30 = _GEN_4; // @[package.scala:16:47]
wire _coh_on_grant_c_cat_T_7; // @[package.scala:16:47]
assign _coh_on_grant_c_cat_T_7 = _GEN_4; // @[package.scala:16:47]
wire _coh_on_grant_c_cat_T_30; // @[package.scala:16:47]
assign _coh_on_grant_c_cat_T_30 = _GEN_4; // @[package.scala:16:47]
wire _r1_c_cat_T_7; // @[package.scala:16:47]
assign _r1_c_cat_T_7 = _GEN_4; // @[package.scala:16:47]
wire _r1_c_cat_T_30; // @[package.scala:16:47]
assign _r1_c_cat_T_30 = _GEN_4; // @[package.scala:16:47]
wire _needs_second_acq_T_34; // @[package.scala:16:47]
assign _needs_second_acq_T_34 = _GEN_4; // @[package.scala:16:47]
wire _GEN_5 = req_uop_mem_cmd == 5'hB; // @[package.scala:16:47]
wire _grow_param_r_c_cat_T_8; // @[package.scala:16:47]
assign _grow_param_r_c_cat_T_8 = _GEN_5; // @[package.scala:16:47]
wire _grow_param_r_c_cat_T_31; // @[package.scala:16:47]
assign _grow_param_r_c_cat_T_31 = _GEN_5; // @[package.scala:16:47]
wire _coh_on_grant_c_cat_T_8; // @[package.scala:16:47]
assign _coh_on_grant_c_cat_T_8 = _GEN_5; // @[package.scala:16:47]
wire _coh_on_grant_c_cat_T_31; // @[package.scala:16:47]
assign _coh_on_grant_c_cat_T_31 = _GEN_5; // @[package.scala:16:47]
wire _r1_c_cat_T_8; // @[package.scala:16:47]
assign _r1_c_cat_T_8 = _GEN_5; // @[package.scala:16:47]
wire _r1_c_cat_T_31; // @[package.scala:16:47]
assign _r1_c_cat_T_31 = _GEN_5; // @[package.scala:16:47]
wire _needs_second_acq_T_35; // @[package.scala:16:47]
assign _needs_second_acq_T_35 = _GEN_5; // @[package.scala:16:47]
wire _grow_param_r_c_cat_T_9 = _grow_param_r_c_cat_T_5 | _grow_param_r_c_cat_T_6; // @[package.scala:16:47, :81:59]
wire _grow_param_r_c_cat_T_10 = _grow_param_r_c_cat_T_9 | _grow_param_r_c_cat_T_7; // @[package.scala:16:47, :81:59]
wire _grow_param_r_c_cat_T_11 = _grow_param_r_c_cat_T_10 | _grow_param_r_c_cat_T_8; // @[package.scala:16:47, :81:59]
wire _GEN_6 = req_uop_mem_cmd == 5'h8; // @[package.scala:16:47]
wire _grow_param_r_c_cat_T_12; // @[package.scala:16:47]
assign _grow_param_r_c_cat_T_12 = _GEN_6; // @[package.scala:16:47]
wire _grow_param_r_c_cat_T_35; // @[package.scala:16:47]
assign _grow_param_r_c_cat_T_35 = _GEN_6; // @[package.scala:16:47]
wire _coh_on_grant_c_cat_T_12; // @[package.scala:16:47]
assign _coh_on_grant_c_cat_T_12 = _GEN_6; // @[package.scala:16:47]
wire _coh_on_grant_c_cat_T_35; // @[package.scala:16:47]
assign _coh_on_grant_c_cat_T_35 = _GEN_6; // @[package.scala:16:47]
wire _r1_c_cat_T_12; // @[package.scala:16:47]
assign _r1_c_cat_T_12 = _GEN_6; // @[package.scala:16:47]
wire _r1_c_cat_T_35; // @[package.scala:16:47]
assign _r1_c_cat_T_35 = _GEN_6; // @[package.scala:16:47]
wire _needs_second_acq_T_39; // @[package.scala:16:47]
assign _needs_second_acq_T_39 = _GEN_6; // @[package.scala:16:47]
wire _GEN_7 = req_uop_mem_cmd == 5'hC; // @[package.scala:16:47]
wire _grow_param_r_c_cat_T_13; // @[package.scala:16:47]
assign _grow_param_r_c_cat_T_13 = _GEN_7; // @[package.scala:16:47]
wire _grow_param_r_c_cat_T_36; // @[package.scala:16:47]
assign _grow_param_r_c_cat_T_36 = _GEN_7; // @[package.scala:16:47]
wire _coh_on_grant_c_cat_T_13; // @[package.scala:16:47]
assign _coh_on_grant_c_cat_T_13 = _GEN_7; // @[package.scala:16:47]
wire _coh_on_grant_c_cat_T_36; // @[package.scala:16:47]
assign _coh_on_grant_c_cat_T_36 = _GEN_7; // @[package.scala:16:47]
wire _r1_c_cat_T_13; // @[package.scala:16:47]
assign _r1_c_cat_T_13 = _GEN_7; // @[package.scala:16:47]
wire _r1_c_cat_T_36; // @[package.scala:16:47]
assign _r1_c_cat_T_36 = _GEN_7; // @[package.scala:16:47]
wire _needs_second_acq_T_40; // @[package.scala:16:47]
assign _needs_second_acq_T_40 = _GEN_7; // @[package.scala:16:47]
wire _GEN_8 = req_uop_mem_cmd == 5'hD; // @[package.scala:16:47]
wire _grow_param_r_c_cat_T_14; // @[package.scala:16:47]
assign _grow_param_r_c_cat_T_14 = _GEN_8; // @[package.scala:16:47]
wire _grow_param_r_c_cat_T_37; // @[package.scala:16:47]
assign _grow_param_r_c_cat_T_37 = _GEN_8; // @[package.scala:16:47]
wire _coh_on_grant_c_cat_T_14; // @[package.scala:16:47]
assign _coh_on_grant_c_cat_T_14 = _GEN_8; // @[package.scala:16:47]
wire _coh_on_grant_c_cat_T_37; // @[package.scala:16:47]
assign _coh_on_grant_c_cat_T_37 = _GEN_8; // @[package.scala:16:47]
wire _r1_c_cat_T_14; // @[package.scala:16:47]
assign _r1_c_cat_T_14 = _GEN_8; // @[package.scala:16:47]
wire _r1_c_cat_T_37; // @[package.scala:16:47]
assign _r1_c_cat_T_37 = _GEN_8; // @[package.scala:16:47]
wire _needs_second_acq_T_41; // @[package.scala:16:47]
assign _needs_second_acq_T_41 = _GEN_8; // @[package.scala:16:47]
wire _GEN_9 = req_uop_mem_cmd == 5'hE; // @[package.scala:16:47]
wire _grow_param_r_c_cat_T_15; // @[package.scala:16:47]
assign _grow_param_r_c_cat_T_15 = _GEN_9; // @[package.scala:16:47]
wire _grow_param_r_c_cat_T_38; // @[package.scala:16:47]
assign _grow_param_r_c_cat_T_38 = _GEN_9; // @[package.scala:16:47]
wire _coh_on_grant_c_cat_T_15; // @[package.scala:16:47]
assign _coh_on_grant_c_cat_T_15 = _GEN_9; // @[package.scala:16:47]
wire _coh_on_grant_c_cat_T_38; // @[package.scala:16:47]
assign _coh_on_grant_c_cat_T_38 = _GEN_9; // @[package.scala:16:47]
wire _r1_c_cat_T_15; // @[package.scala:16:47]
assign _r1_c_cat_T_15 = _GEN_9; // @[package.scala:16:47]
wire _r1_c_cat_T_38; // @[package.scala:16:47]
assign _r1_c_cat_T_38 = _GEN_9; // @[package.scala:16:47]
wire _needs_second_acq_T_42; // @[package.scala:16:47]
assign _needs_second_acq_T_42 = _GEN_9; // @[package.scala:16:47]
wire _GEN_10 = req_uop_mem_cmd == 5'hF; // @[package.scala:16:47]
wire _grow_param_r_c_cat_T_16; // @[package.scala:16:47]
assign _grow_param_r_c_cat_T_16 = _GEN_10; // @[package.scala:16:47]
wire _grow_param_r_c_cat_T_39; // @[package.scala:16:47]
assign _grow_param_r_c_cat_T_39 = _GEN_10; // @[package.scala:16:47]
wire _coh_on_grant_c_cat_T_16; // @[package.scala:16:47]
assign _coh_on_grant_c_cat_T_16 = _GEN_10; // @[package.scala:16:47]
wire _coh_on_grant_c_cat_T_39; // @[package.scala:16:47]
assign _coh_on_grant_c_cat_T_39 = _GEN_10; // @[package.scala:16:47]
wire _r1_c_cat_T_16; // @[package.scala:16:47]
assign _r1_c_cat_T_16 = _GEN_10; // @[package.scala:16:47]
wire _r1_c_cat_T_39; // @[package.scala:16:47]
assign _r1_c_cat_T_39 = _GEN_10; // @[package.scala:16:47]
wire _needs_second_acq_T_43; // @[package.scala:16:47]
assign _needs_second_acq_T_43 = _GEN_10; // @[package.scala:16:47]
wire _grow_param_r_c_cat_T_17 = _grow_param_r_c_cat_T_12 | _grow_param_r_c_cat_T_13; // @[package.scala:16:47, :81:59]
wire _grow_param_r_c_cat_T_18 = _grow_param_r_c_cat_T_17 | _grow_param_r_c_cat_T_14; // @[package.scala:16:47, :81:59]
wire _grow_param_r_c_cat_T_19 = _grow_param_r_c_cat_T_18 | _grow_param_r_c_cat_T_15; // @[package.scala:16:47, :81:59]
wire _grow_param_r_c_cat_T_20 = _grow_param_r_c_cat_T_19 | _grow_param_r_c_cat_T_16; // @[package.scala:16:47, :81:59]
wire _grow_param_r_c_cat_T_21 = _grow_param_r_c_cat_T_11 | _grow_param_r_c_cat_T_20; // @[package.scala:81:59]
wire _grow_param_r_c_cat_T_22 = _grow_param_r_c_cat_T_4 | _grow_param_r_c_cat_T_21; // @[Consts.scala:87:44, :90:{59,76}]
wire _grow_param_r_c_cat_T_25 = _grow_param_r_c_cat_T_23 | _grow_param_r_c_cat_T_24; // @[Consts.scala:90:{32,42,49}]
wire _grow_param_r_c_cat_T_27 = _grow_param_r_c_cat_T_25 | _grow_param_r_c_cat_T_26; // @[Consts.scala:90:{42,59,66}]
wire _grow_param_r_c_cat_T_32 = _grow_param_r_c_cat_T_28 | _grow_param_r_c_cat_T_29; // @[package.scala:16:47, :81:59]
wire _grow_param_r_c_cat_T_33 = _grow_param_r_c_cat_T_32 | _grow_param_r_c_cat_T_30; // @[package.scala:16:47, :81:59]
wire _grow_param_r_c_cat_T_34 = _grow_param_r_c_cat_T_33 | _grow_param_r_c_cat_T_31; // @[package.scala:16:47, :81:59]
wire _grow_param_r_c_cat_T_40 = _grow_param_r_c_cat_T_35 | _grow_param_r_c_cat_T_36; // @[package.scala:16:47, :81:59]
wire _grow_param_r_c_cat_T_41 = _grow_param_r_c_cat_T_40 | _grow_param_r_c_cat_T_37; // @[package.scala:16:47, :81:59]
wire _grow_param_r_c_cat_T_42 = _grow_param_r_c_cat_T_41 | _grow_param_r_c_cat_T_38; // @[package.scala:16:47, :81:59]
wire _grow_param_r_c_cat_T_43 = _grow_param_r_c_cat_T_42 | _grow_param_r_c_cat_T_39; // @[package.scala:16:47, :81:59]
wire _grow_param_r_c_cat_T_44 = _grow_param_r_c_cat_T_34 | _grow_param_r_c_cat_T_43; // @[package.scala:81:59]
wire _grow_param_r_c_cat_T_45 = _grow_param_r_c_cat_T_27 | _grow_param_r_c_cat_T_44; // @[Consts.scala:87:44, :90:{59,76}]
wire _GEN_11 = req_uop_mem_cmd == 5'h3; // @[Consts.scala:91:54]
wire _grow_param_r_c_cat_T_46; // @[Consts.scala:91:54]
assign _grow_param_r_c_cat_T_46 = _GEN_11; // @[Consts.scala:91:54]
wire _coh_on_grant_c_cat_T_46; // @[Consts.scala:91:54]
assign _coh_on_grant_c_cat_T_46 = _GEN_11; // @[Consts.scala:91:54]
wire _r1_c_cat_T_46; // @[Consts.scala:91:54]
assign _r1_c_cat_T_46 = _GEN_11; // @[Consts.scala:91:54]
wire _needs_second_acq_T_50; // @[Consts.scala:91:54]
assign _needs_second_acq_T_50 = _GEN_11; // @[Consts.scala:91:54]
wire _grow_param_r_c_cat_T_47 = _grow_param_r_c_cat_T_45 | _grow_param_r_c_cat_T_46; // @[Consts.scala:90:76, :91:{47,54}]
wire _GEN_12 = req_uop_mem_cmd == 5'h6; // @[Consts.scala:91:71]
wire _grow_param_r_c_cat_T_48; // @[Consts.scala:91:71]
assign _grow_param_r_c_cat_T_48 = _GEN_12; // @[Consts.scala:91:71]
wire _coh_on_grant_c_cat_T_48; // @[Consts.scala:91:71]
assign _coh_on_grant_c_cat_T_48 = _GEN_12; // @[Consts.scala:91:71]
wire _r1_c_cat_T_48; // @[Consts.scala:91:71]
assign _r1_c_cat_T_48 = _GEN_12; // @[Consts.scala:91:71]
wire _needs_second_acq_T_52; // @[Consts.scala:91:71]
assign _needs_second_acq_T_52 = _GEN_12; // @[Consts.scala:91:71]
wire _grow_param_r_c_cat_T_49 = _grow_param_r_c_cat_T_47 | _grow_param_r_c_cat_T_48; // @[Consts.scala:91:{47,64,71}]
wire [1:0] grow_param_r_c = {_grow_param_r_c_cat_T_22, _grow_param_r_c_cat_T_49}; // @[Metadata.scala:29:18]
wire [3:0] _grow_param_r_T = {grow_param_r_c, new_coh_state}; // @[Metadata.scala:29:18, :58:19]
wire _grow_param_r_T_25 = _grow_param_r_T == 4'hC; // @[Misc.scala:49:20]
wire [1:0] _grow_param_r_T_27 = {1'h0, _grow_param_r_T_25}; // @[Misc.scala:35:36, :49:20]
wire _grow_param_r_T_28 = _grow_param_r_T == 4'hD; // @[Misc.scala:49:20]
wire [1:0] _grow_param_r_T_30 = _grow_param_r_T_28 ? 2'h2 : _grow_param_r_T_27; // @[Misc.scala:35:36, :49:20]
wire _grow_param_r_T_31 = _grow_param_r_T == 4'h4; // @[Misc.scala:49:20]
wire [1:0] _grow_param_r_T_33 = _grow_param_r_T_31 ? 2'h1 : _grow_param_r_T_30; // @[Misc.scala:35:36, :49:20]
wire _grow_param_r_T_34 = _grow_param_r_T == 4'h5; // @[Misc.scala:49:20]
wire [1:0] _grow_param_r_T_36 = _grow_param_r_T_34 ? 2'h2 : _grow_param_r_T_33; // @[Misc.scala:35:36, :49:20]
wire _grow_param_r_T_37 = _grow_param_r_T == 4'h0; // @[Misc.scala:49:20]
wire [1:0] _grow_param_r_T_39 = _grow_param_r_T_37 ? 2'h0 : _grow_param_r_T_36; // @[Misc.scala:35:36, :49:20]
wire _grow_param_r_T_40 = _grow_param_r_T == 4'hE; // @[Misc.scala:49:20]
wire _grow_param_r_T_41 = _grow_param_r_T_40; // @[Misc.scala:35:9, :49:20]
wire [1:0] _grow_param_r_T_42 = _grow_param_r_T_40 ? 2'h3 : _grow_param_r_T_39; // @[Misc.scala:35:36, :49:20]
wire _grow_param_r_T_43 = &_grow_param_r_T; // @[Misc.scala:49:20]
wire _grow_param_r_T_44 = _grow_param_r_T_43 | _grow_param_r_T_41; // @[Misc.scala:35:9, :49:20]
wire [1:0] _grow_param_r_T_45 = _grow_param_r_T_43 ? 2'h3 : _grow_param_r_T_42; // @[Misc.scala:35:36, :49:20]
wire _grow_param_r_T_46 = _grow_param_r_T == 4'h6; // @[Misc.scala:49:20]
wire _grow_param_r_T_47 = _grow_param_r_T_46 | _grow_param_r_T_44; // @[Misc.scala:35:9, :49:20]
wire [1:0] _grow_param_r_T_48 = _grow_param_r_T_46 ? 2'h2 : _grow_param_r_T_45; // @[Misc.scala:35:36, :49:20]
wire _grow_param_r_T_49 = _grow_param_r_T == 4'h7; // @[Misc.scala:49:20]
wire _grow_param_r_T_50 = _grow_param_r_T_49 | _grow_param_r_T_47; // @[Misc.scala:35:9, :49:20]
wire [1:0] _grow_param_r_T_51 = _grow_param_r_T_49 ? 2'h3 : _grow_param_r_T_48; // @[Misc.scala:35:36, :49:20]
wire _grow_param_r_T_52 = _grow_param_r_T == 4'h1; // @[Misc.scala:49:20]
wire _grow_param_r_T_53 = _grow_param_r_T_52 | _grow_param_r_T_50; // @[Misc.scala:35:9, :49:20]
wire [1:0] _grow_param_r_T_54 = _grow_param_r_T_52 ? 2'h1 : _grow_param_r_T_51; // @[Misc.scala:35:36, :49:20]
wire _grow_param_r_T_55 = _grow_param_r_T == 4'h2; // @[Misc.scala:49:20]
wire _grow_param_r_T_56 = _grow_param_r_T_55 | _grow_param_r_T_53; // @[Misc.scala:35:9, :49:20]
wire [1:0] _grow_param_r_T_57 = _grow_param_r_T_55 ? 2'h2 : _grow_param_r_T_54; // @[Misc.scala:35:36, :49:20]
wire _grow_param_r_T_58 = _grow_param_r_T == 4'h3; // @[Misc.scala:49:20]
wire grow_param_r_1 = _grow_param_r_T_58 | _grow_param_r_T_56; // @[Misc.scala:35:9, :49:20]
wire [1:0] grow_param = _grow_param_r_T_58 ? 2'h3 : _grow_param_r_T_57; // @[Misc.scala:35:36, :49:20]
wire [1:0] grow_param_meta_state = grow_param; // @[Misc.scala:35:36]
wire _coh_on_grant_c_cat_T_2 = _coh_on_grant_c_cat_T | _coh_on_grant_c_cat_T_1; // @[Consts.scala:90:{32,42,49}]
wire _coh_on_grant_c_cat_T_4 = _coh_on_grant_c_cat_T_2 | _coh_on_grant_c_cat_T_3; // @[Consts.scala:90:{42,59,66}]
wire _coh_on_grant_c_cat_T_9 = _coh_on_grant_c_cat_T_5 | _coh_on_grant_c_cat_T_6; // @[package.scala:16:47, :81:59]
wire _coh_on_grant_c_cat_T_10 = _coh_on_grant_c_cat_T_9 | _coh_on_grant_c_cat_T_7; // @[package.scala:16:47, :81:59]
wire _coh_on_grant_c_cat_T_11 = _coh_on_grant_c_cat_T_10 | _coh_on_grant_c_cat_T_8; // @[package.scala:16:47, :81:59]
wire _coh_on_grant_c_cat_T_17 = _coh_on_grant_c_cat_T_12 | _coh_on_grant_c_cat_T_13; // @[package.scala:16:47, :81:59]
wire _coh_on_grant_c_cat_T_18 = _coh_on_grant_c_cat_T_17 | _coh_on_grant_c_cat_T_14; // @[package.scala:16:47, :81:59]
wire _coh_on_grant_c_cat_T_19 = _coh_on_grant_c_cat_T_18 | _coh_on_grant_c_cat_T_15; // @[package.scala:16:47, :81:59]
wire _coh_on_grant_c_cat_T_20 = _coh_on_grant_c_cat_T_19 | _coh_on_grant_c_cat_T_16; // @[package.scala:16:47, :81:59]
wire _coh_on_grant_c_cat_T_21 = _coh_on_grant_c_cat_T_11 | _coh_on_grant_c_cat_T_20; // @[package.scala:81:59]
wire _coh_on_grant_c_cat_T_22 = _coh_on_grant_c_cat_T_4 | _coh_on_grant_c_cat_T_21; // @[Consts.scala:87:44, :90:{59,76}]
wire _coh_on_grant_c_cat_T_25 = _coh_on_grant_c_cat_T_23 | _coh_on_grant_c_cat_T_24; // @[Consts.scala:90:{32,42,49}]
wire _coh_on_grant_c_cat_T_27 = _coh_on_grant_c_cat_T_25 | _coh_on_grant_c_cat_T_26; // @[Consts.scala:90:{42,59,66}]
wire _coh_on_grant_c_cat_T_32 = _coh_on_grant_c_cat_T_28 | _coh_on_grant_c_cat_T_29; // @[package.scala:16:47, :81:59]
wire _coh_on_grant_c_cat_T_33 = _coh_on_grant_c_cat_T_32 | _coh_on_grant_c_cat_T_30; // @[package.scala:16:47, :81:59]
wire _coh_on_grant_c_cat_T_34 = _coh_on_grant_c_cat_T_33 | _coh_on_grant_c_cat_T_31; // @[package.scala:16:47, :81:59]
wire _coh_on_grant_c_cat_T_40 = _coh_on_grant_c_cat_T_35 | _coh_on_grant_c_cat_T_36; // @[package.scala:16:47, :81:59]
wire _coh_on_grant_c_cat_T_41 = _coh_on_grant_c_cat_T_40 | _coh_on_grant_c_cat_T_37; // @[package.scala:16:47, :81:59]
wire _coh_on_grant_c_cat_T_42 = _coh_on_grant_c_cat_T_41 | _coh_on_grant_c_cat_T_38; // @[package.scala:16:47, :81:59]
wire _coh_on_grant_c_cat_T_43 = _coh_on_grant_c_cat_T_42 | _coh_on_grant_c_cat_T_39; // @[package.scala:16:47, :81:59]
wire _coh_on_grant_c_cat_T_44 = _coh_on_grant_c_cat_T_34 | _coh_on_grant_c_cat_T_43; // @[package.scala:81:59]
wire _coh_on_grant_c_cat_T_45 = _coh_on_grant_c_cat_T_27 | _coh_on_grant_c_cat_T_44; // @[Consts.scala:87:44, :90:{59,76}]
wire _coh_on_grant_c_cat_T_47 = _coh_on_grant_c_cat_T_45 | _coh_on_grant_c_cat_T_46; // @[Consts.scala:90:76, :91:{47,54}]
wire _coh_on_grant_c_cat_T_49 = _coh_on_grant_c_cat_T_47 | _coh_on_grant_c_cat_T_48; // @[Consts.scala:91:{47,64,71}]
wire [1:0] coh_on_grant_c = {_coh_on_grant_c_cat_T_22, _coh_on_grant_c_cat_T_49}; // @[Metadata.scala:29:18]
wire [3:0] _coh_on_grant_T = {coh_on_grant_c, io_mem_grant_bits_param_0}; // @[Metadata.scala:29:18, :84:18]
wire _coh_on_grant_T_9 = _coh_on_grant_T == 4'h1; // @[Metadata.scala:84:{18,38}]
wire [1:0] _coh_on_grant_T_10 = {1'h0, _coh_on_grant_T_9}; // @[Metadata.scala:84:38]
wire _coh_on_grant_T_11 = _coh_on_grant_T == 4'h0; // @[Metadata.scala:84:{18,38}]
wire [1:0] _coh_on_grant_T_12 = _coh_on_grant_T_11 ? 2'h2 : _coh_on_grant_T_10; // @[Metadata.scala:84:38]
wire _coh_on_grant_T_13 = _coh_on_grant_T == 4'h4; // @[Metadata.scala:84:{18,38}]
wire [1:0] _coh_on_grant_T_14 = _coh_on_grant_T_13 ? 2'h2 : _coh_on_grant_T_12; // @[Metadata.scala:84:38]
wire _coh_on_grant_T_15 = _coh_on_grant_T == 4'hC; // @[Metadata.scala:84:{18,38}]
wire [1:0] _coh_on_grant_T_16 = _coh_on_grant_T_15 ? 2'h3 : _coh_on_grant_T_14; // @[Metadata.scala:84:38]
assign coh_on_grant_state = _coh_on_grant_T_16; // @[Metadata.scala:84:38, :160:20]
assign io_commit_coh_state_0 = coh_on_grant_state; // @[Metadata.scala:160:20]
wire _r1_c_cat_T_2 = _r1_c_cat_T | _r1_c_cat_T_1; // @[Consts.scala:90:{32,42,49}]
wire _r1_c_cat_T_4 = _r1_c_cat_T_2 | _r1_c_cat_T_3; // @[Consts.scala:90:{42,59,66}]
wire _r1_c_cat_T_9 = _r1_c_cat_T_5 | _r1_c_cat_T_6; // @[package.scala:16:47, :81:59]
wire _r1_c_cat_T_10 = _r1_c_cat_T_9 | _r1_c_cat_T_7; // @[package.scala:16:47, :81:59]
wire _r1_c_cat_T_11 = _r1_c_cat_T_10 | _r1_c_cat_T_8; // @[package.scala:16:47, :81:59]
wire _r1_c_cat_T_17 = _r1_c_cat_T_12 | _r1_c_cat_T_13; // @[package.scala:16:47, :81:59]
wire _r1_c_cat_T_18 = _r1_c_cat_T_17 | _r1_c_cat_T_14; // @[package.scala:16:47, :81:59]
wire _r1_c_cat_T_19 = _r1_c_cat_T_18 | _r1_c_cat_T_15; // @[package.scala:16:47, :81:59]
wire _r1_c_cat_T_20 = _r1_c_cat_T_19 | _r1_c_cat_T_16; // @[package.scala:16:47, :81:59]
wire _r1_c_cat_T_21 = _r1_c_cat_T_11 | _r1_c_cat_T_20; // @[package.scala:81:59]
wire _r1_c_cat_T_22 = _r1_c_cat_T_4 | _r1_c_cat_T_21; // @[Consts.scala:87:44, :90:{59,76}]
wire _r1_c_cat_T_25 = _r1_c_cat_T_23 | _r1_c_cat_T_24; // @[Consts.scala:90:{32,42,49}]
wire _r1_c_cat_T_27 = _r1_c_cat_T_25 | _r1_c_cat_T_26; // @[Consts.scala:90:{42,59,66}]
wire _r1_c_cat_T_32 = _r1_c_cat_T_28 | _r1_c_cat_T_29; // @[package.scala:16:47, :81:59]
wire _r1_c_cat_T_33 = _r1_c_cat_T_32 | _r1_c_cat_T_30; // @[package.scala:16:47, :81:59]
wire _r1_c_cat_T_34 = _r1_c_cat_T_33 | _r1_c_cat_T_31; // @[package.scala:16:47, :81:59]
wire _r1_c_cat_T_40 = _r1_c_cat_T_35 | _r1_c_cat_T_36; // @[package.scala:16:47, :81:59]
wire _r1_c_cat_T_41 = _r1_c_cat_T_40 | _r1_c_cat_T_37; // @[package.scala:16:47, :81:59]
wire _r1_c_cat_T_42 = _r1_c_cat_T_41 | _r1_c_cat_T_38; // @[package.scala:16:47, :81:59]
wire _r1_c_cat_T_43 = _r1_c_cat_T_42 | _r1_c_cat_T_39; // @[package.scala:16:47, :81:59]
wire _r1_c_cat_T_44 = _r1_c_cat_T_34 | _r1_c_cat_T_43; // @[package.scala:81:59]
wire _r1_c_cat_T_45 = _r1_c_cat_T_27 | _r1_c_cat_T_44; // @[Consts.scala:87:44, :90:{59,76}]
wire _r1_c_cat_T_47 = _r1_c_cat_T_45 | _r1_c_cat_T_46; // @[Consts.scala:90:76, :91:{47,54}]
wire _r1_c_cat_T_49 = _r1_c_cat_T_47 | _r1_c_cat_T_48; // @[Consts.scala:91:{47,64,71}]
wire [1:0] r1_c = {_r1_c_cat_T_22, _r1_c_cat_T_49}; // @[Metadata.scala:29:18]
wire [3:0] _r1_T = {r1_c, new_coh_state}; // @[Metadata.scala:29:18, :58:19]
wire _r1_T_25 = _r1_T == 4'hC; // @[Misc.scala:49:20]
wire [1:0] _r1_T_27 = {1'h0, _r1_T_25}; // @[Misc.scala:35:36, :49:20]
wire _r1_T_28 = _r1_T == 4'hD; // @[Misc.scala:49:20]
wire [1:0] _r1_T_30 = _r1_T_28 ? 2'h2 : _r1_T_27; // @[Misc.scala:35:36, :49:20]
wire _r1_T_31 = _r1_T == 4'h4; // @[Misc.scala:49:20]
wire [1:0] _r1_T_33 = _r1_T_31 ? 2'h1 : _r1_T_30; // @[Misc.scala:35:36, :49:20]
wire _r1_T_34 = _r1_T == 4'h5; // @[Misc.scala:49:20]
wire [1:0] _r1_T_36 = _r1_T_34 ? 2'h2 : _r1_T_33; // @[Misc.scala:35:36, :49:20]
wire _r1_T_37 = _r1_T == 4'h0; // @[Misc.scala:49:20]
wire [1:0] _r1_T_39 = _r1_T_37 ? 2'h0 : _r1_T_36; // @[Misc.scala:35:36, :49:20]
wire _r1_T_40 = _r1_T == 4'hE; // @[Misc.scala:49:20]
wire _r1_T_41 = _r1_T_40; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r1_T_42 = _r1_T_40 ? 2'h3 : _r1_T_39; // @[Misc.scala:35:36, :49:20]
wire _r1_T_43 = &_r1_T; // @[Misc.scala:49:20]
wire _r1_T_44 = _r1_T_43 | _r1_T_41; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r1_T_45 = _r1_T_43 ? 2'h3 : _r1_T_42; // @[Misc.scala:35:36, :49:20]
wire _r1_T_46 = _r1_T == 4'h6; // @[Misc.scala:49:20]
wire _r1_T_47 = _r1_T_46 | _r1_T_44; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r1_T_48 = _r1_T_46 ? 2'h2 : _r1_T_45; // @[Misc.scala:35:36, :49:20]
wire _r1_T_49 = _r1_T == 4'h7; // @[Misc.scala:49:20]
wire _r1_T_50 = _r1_T_49 | _r1_T_47; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r1_T_51 = _r1_T_49 ? 2'h3 : _r1_T_48; // @[Misc.scala:35:36, :49:20]
wire _r1_T_52 = _r1_T == 4'h1; // @[Misc.scala:49:20]
wire _r1_T_53 = _r1_T_52 | _r1_T_50; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r1_T_54 = _r1_T_52 ? 2'h1 : _r1_T_51; // @[Misc.scala:35:36, :49:20]
wire _r1_T_55 = _r1_T == 4'h2; // @[Misc.scala:49:20]
wire _r1_T_56 = _r1_T_55 | _r1_T_53; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r1_T_57 = _r1_T_55 ? 2'h2 : _r1_T_54; // @[Misc.scala:35:36, :49:20]
wire _r1_T_58 = _r1_T == 4'h3; // @[Misc.scala:49:20]
wire r1_1 = _r1_T_58 | _r1_T_56; // @[Misc.scala:35:9, :49:20]
wire [1:0] r1_2 = _r1_T_58 ? 2'h3 : _r1_T_57; // @[Misc.scala:35:36, :49:20]
wire _GEN_13 = io_req_uop_mem_cmd_0 == 5'h1; // @[Consts.scala:90:32]
wire _r2_c_cat_T; // @[Consts.scala:90:32]
assign _r2_c_cat_T = _GEN_13; // @[Consts.scala:90:32]
wire _r2_c_cat_T_23; // @[Consts.scala:90:32]
assign _r2_c_cat_T_23 = _GEN_13; // @[Consts.scala:90:32]
wire _needs_second_acq_T; // @[Consts.scala:90:32]
assign _needs_second_acq_T = _GEN_13; // @[Consts.scala:90:32]
wire _dirties_cat_T; // @[Consts.scala:90:32]
assign _dirties_cat_T = _GEN_13; // @[Consts.scala:90:32]
wire _dirties_cat_T_23; // @[Consts.scala:90:32]
assign _dirties_cat_T_23 = _GEN_13; // @[Consts.scala:90:32]
wire _state_r_c_cat_T; // @[Consts.scala:90:32]
assign _state_r_c_cat_T = _GEN_13; // @[Consts.scala:90:32]
wire _state_r_c_cat_T_23; // @[Consts.scala:90:32]
assign _state_r_c_cat_T_23 = _GEN_13; // @[Consts.scala:90:32]
wire _state_T_3; // @[Consts.scala:90:32]
assign _state_T_3 = _GEN_13; // @[Consts.scala:90:32]
wire _r_c_cat_T_50; // @[Consts.scala:90:32]
assign _r_c_cat_T_50 = _GEN_13; // @[Consts.scala:90:32]
wire _r_c_cat_T_73; // @[Consts.scala:90:32]
assign _r_c_cat_T_73 = _GEN_13; // @[Consts.scala:90:32]
wire _state_r_c_cat_T_50; // @[Consts.scala:90:32]
assign _state_r_c_cat_T_50 = _GEN_13; // @[Consts.scala:90:32]
wire _state_r_c_cat_T_73; // @[Consts.scala:90:32]
assign _state_r_c_cat_T_73 = _GEN_13; // @[Consts.scala:90:32]
wire _state_T_37; // @[Consts.scala:90:32]
assign _state_T_37 = _GEN_13; // @[Consts.scala:90:32]
wire _GEN_14 = io_req_uop_mem_cmd_0 == 5'h11; // @[Consts.scala:90:49]
wire _r2_c_cat_T_1; // @[Consts.scala:90:49]
assign _r2_c_cat_T_1 = _GEN_14; // @[Consts.scala:90:49]
wire _r2_c_cat_T_24; // @[Consts.scala:90:49]
assign _r2_c_cat_T_24 = _GEN_14; // @[Consts.scala:90:49]
wire _needs_second_acq_T_1; // @[Consts.scala:90:49]
assign _needs_second_acq_T_1 = _GEN_14; // @[Consts.scala:90:49]
wire _dirties_cat_T_1; // @[Consts.scala:90:49]
assign _dirties_cat_T_1 = _GEN_14; // @[Consts.scala:90:49]
wire _dirties_cat_T_24; // @[Consts.scala:90:49]
assign _dirties_cat_T_24 = _GEN_14; // @[Consts.scala:90:49]
wire _state_r_c_cat_T_1; // @[Consts.scala:90:49]
assign _state_r_c_cat_T_1 = _GEN_14; // @[Consts.scala:90:49]
wire _state_r_c_cat_T_24; // @[Consts.scala:90:49]
assign _state_r_c_cat_T_24 = _GEN_14; // @[Consts.scala:90:49]
wire _state_T_4; // @[Consts.scala:90:49]
assign _state_T_4 = _GEN_14; // @[Consts.scala:90:49]
wire _r_c_cat_T_51; // @[Consts.scala:90:49]
assign _r_c_cat_T_51 = _GEN_14; // @[Consts.scala:90:49]
wire _r_c_cat_T_74; // @[Consts.scala:90:49]
assign _r_c_cat_T_74 = _GEN_14; // @[Consts.scala:90:49]
wire _state_r_c_cat_T_51; // @[Consts.scala:90:49]
assign _state_r_c_cat_T_51 = _GEN_14; // @[Consts.scala:90:49]
wire _state_r_c_cat_T_74; // @[Consts.scala:90:49]
assign _state_r_c_cat_T_74 = _GEN_14; // @[Consts.scala:90:49]
wire _state_T_38; // @[Consts.scala:90:49]
assign _state_T_38 = _GEN_14; // @[Consts.scala:90:49]
wire _r2_c_cat_T_2 = _r2_c_cat_T | _r2_c_cat_T_1; // @[Consts.scala:90:{32,42,49}]
wire _GEN_15 = io_req_uop_mem_cmd_0 == 5'h7; // @[Consts.scala:90:66]
wire _r2_c_cat_T_3; // @[Consts.scala:90:66]
assign _r2_c_cat_T_3 = _GEN_15; // @[Consts.scala:90:66]
wire _r2_c_cat_T_26; // @[Consts.scala:90:66]
assign _r2_c_cat_T_26 = _GEN_15; // @[Consts.scala:90:66]
wire _needs_second_acq_T_3; // @[Consts.scala:90:66]
assign _needs_second_acq_T_3 = _GEN_15; // @[Consts.scala:90:66]
wire _dirties_cat_T_3; // @[Consts.scala:90:66]
assign _dirties_cat_T_3 = _GEN_15; // @[Consts.scala:90:66]
wire _dirties_cat_T_26; // @[Consts.scala:90:66]
assign _dirties_cat_T_26 = _GEN_15; // @[Consts.scala:90:66]
wire _state_r_c_cat_T_3; // @[Consts.scala:90:66]
assign _state_r_c_cat_T_3 = _GEN_15; // @[Consts.scala:90:66]
wire _state_r_c_cat_T_26; // @[Consts.scala:90:66]
assign _state_r_c_cat_T_26 = _GEN_15; // @[Consts.scala:90:66]
wire _state_T_6; // @[Consts.scala:90:66]
assign _state_T_6 = _GEN_15; // @[Consts.scala:90:66]
wire _r_c_cat_T_53; // @[Consts.scala:90:66]
assign _r_c_cat_T_53 = _GEN_15; // @[Consts.scala:90:66]
wire _r_c_cat_T_76; // @[Consts.scala:90:66]
assign _r_c_cat_T_76 = _GEN_15; // @[Consts.scala:90:66]
wire _state_r_c_cat_T_53; // @[Consts.scala:90:66]
assign _state_r_c_cat_T_53 = _GEN_15; // @[Consts.scala:90:66]
wire _state_r_c_cat_T_76; // @[Consts.scala:90:66]
assign _state_r_c_cat_T_76 = _GEN_15; // @[Consts.scala:90:66]
wire _state_T_40; // @[Consts.scala:90:66]
assign _state_T_40 = _GEN_15; // @[Consts.scala:90:66]
wire _r2_c_cat_T_4 = _r2_c_cat_T_2 | _r2_c_cat_T_3; // @[Consts.scala:90:{42,59,66}]
wire _GEN_16 = io_req_uop_mem_cmd_0 == 5'h4; // @[package.scala:16:47]
wire _r2_c_cat_T_5; // @[package.scala:16:47]
assign _r2_c_cat_T_5 = _GEN_16; // @[package.scala:16:47]
wire _r2_c_cat_T_28; // @[package.scala:16:47]
assign _r2_c_cat_T_28 = _GEN_16; // @[package.scala:16:47]
wire _needs_second_acq_T_5; // @[package.scala:16:47]
assign _needs_second_acq_T_5 = _GEN_16; // @[package.scala:16:47]
wire _dirties_cat_T_5; // @[package.scala:16:47]
assign _dirties_cat_T_5 = _GEN_16; // @[package.scala:16:47]
wire _dirties_cat_T_28; // @[package.scala:16:47]
assign _dirties_cat_T_28 = _GEN_16; // @[package.scala:16:47]
wire _state_r_c_cat_T_5; // @[package.scala:16:47]
assign _state_r_c_cat_T_5 = _GEN_16; // @[package.scala:16:47]
wire _state_r_c_cat_T_28; // @[package.scala:16:47]
assign _state_r_c_cat_T_28 = _GEN_16; // @[package.scala:16:47]
wire _state_T_8; // @[package.scala:16:47]
assign _state_T_8 = _GEN_16; // @[package.scala:16:47]
wire _r_c_cat_T_55; // @[package.scala:16:47]
assign _r_c_cat_T_55 = _GEN_16; // @[package.scala:16:47]
wire _r_c_cat_T_78; // @[package.scala:16:47]
assign _r_c_cat_T_78 = _GEN_16; // @[package.scala:16:47]
wire _state_r_c_cat_T_55; // @[package.scala:16:47]
assign _state_r_c_cat_T_55 = _GEN_16; // @[package.scala:16:47]
wire _state_r_c_cat_T_78; // @[package.scala:16:47]
assign _state_r_c_cat_T_78 = _GEN_16; // @[package.scala:16:47]
wire _state_T_42; // @[package.scala:16:47]
assign _state_T_42 = _GEN_16; // @[package.scala:16:47]
wire _GEN_17 = io_req_uop_mem_cmd_0 == 5'h9; // @[package.scala:16:47]
wire _r2_c_cat_T_6; // @[package.scala:16:47]
assign _r2_c_cat_T_6 = _GEN_17; // @[package.scala:16:47]
wire _r2_c_cat_T_29; // @[package.scala:16:47]
assign _r2_c_cat_T_29 = _GEN_17; // @[package.scala:16:47]
wire _needs_second_acq_T_6; // @[package.scala:16:47]
assign _needs_second_acq_T_6 = _GEN_17; // @[package.scala:16:47]
wire _dirties_cat_T_6; // @[package.scala:16:47]
assign _dirties_cat_T_6 = _GEN_17; // @[package.scala:16:47]
wire _dirties_cat_T_29; // @[package.scala:16:47]
assign _dirties_cat_T_29 = _GEN_17; // @[package.scala:16:47]
wire _state_r_c_cat_T_6; // @[package.scala:16:47]
assign _state_r_c_cat_T_6 = _GEN_17; // @[package.scala:16:47]
wire _state_r_c_cat_T_29; // @[package.scala:16:47]
assign _state_r_c_cat_T_29 = _GEN_17; // @[package.scala:16:47]
wire _state_T_9; // @[package.scala:16:47]
assign _state_T_9 = _GEN_17; // @[package.scala:16:47]
wire _r_c_cat_T_56; // @[package.scala:16:47]
assign _r_c_cat_T_56 = _GEN_17; // @[package.scala:16:47]
wire _r_c_cat_T_79; // @[package.scala:16:47]
assign _r_c_cat_T_79 = _GEN_17; // @[package.scala:16:47]
wire _state_r_c_cat_T_56; // @[package.scala:16:47]
assign _state_r_c_cat_T_56 = _GEN_17; // @[package.scala:16:47]
wire _state_r_c_cat_T_79; // @[package.scala:16:47]
assign _state_r_c_cat_T_79 = _GEN_17; // @[package.scala:16:47]
wire _state_T_43; // @[package.scala:16:47]
assign _state_T_43 = _GEN_17; // @[package.scala:16:47]
wire _GEN_18 = io_req_uop_mem_cmd_0 == 5'hA; // @[package.scala:16:47]
wire _r2_c_cat_T_7; // @[package.scala:16:47]
assign _r2_c_cat_T_7 = _GEN_18; // @[package.scala:16:47]
wire _r2_c_cat_T_30; // @[package.scala:16:47]
assign _r2_c_cat_T_30 = _GEN_18; // @[package.scala:16:47]
wire _needs_second_acq_T_7; // @[package.scala:16:47]
assign _needs_second_acq_T_7 = _GEN_18; // @[package.scala:16:47]
wire _dirties_cat_T_7; // @[package.scala:16:47]
assign _dirties_cat_T_7 = _GEN_18; // @[package.scala:16:47]
wire _dirties_cat_T_30; // @[package.scala:16:47]
assign _dirties_cat_T_30 = _GEN_18; // @[package.scala:16:47]
wire _state_r_c_cat_T_7; // @[package.scala:16:47]
assign _state_r_c_cat_T_7 = _GEN_18; // @[package.scala:16:47]
wire _state_r_c_cat_T_30; // @[package.scala:16:47]
assign _state_r_c_cat_T_30 = _GEN_18; // @[package.scala:16:47]
wire _state_T_10; // @[package.scala:16:47]
assign _state_T_10 = _GEN_18; // @[package.scala:16:47]
wire _r_c_cat_T_57; // @[package.scala:16:47]
assign _r_c_cat_T_57 = _GEN_18; // @[package.scala:16:47]
wire _r_c_cat_T_80; // @[package.scala:16:47]
assign _r_c_cat_T_80 = _GEN_18; // @[package.scala:16:47]
wire _state_r_c_cat_T_57; // @[package.scala:16:47]
assign _state_r_c_cat_T_57 = _GEN_18; // @[package.scala:16:47]
wire _state_r_c_cat_T_80; // @[package.scala:16:47]
assign _state_r_c_cat_T_80 = _GEN_18; // @[package.scala:16:47]
wire _state_T_44; // @[package.scala:16:47]
assign _state_T_44 = _GEN_18; // @[package.scala:16:47]
wire _GEN_19 = io_req_uop_mem_cmd_0 == 5'hB; // @[package.scala:16:47]
wire _r2_c_cat_T_8; // @[package.scala:16:47]
assign _r2_c_cat_T_8 = _GEN_19; // @[package.scala:16:47]
wire _r2_c_cat_T_31; // @[package.scala:16:47]
assign _r2_c_cat_T_31 = _GEN_19; // @[package.scala:16:47]
wire _needs_second_acq_T_8; // @[package.scala:16:47]
assign _needs_second_acq_T_8 = _GEN_19; // @[package.scala:16:47]
wire _dirties_cat_T_8; // @[package.scala:16:47]
assign _dirties_cat_T_8 = _GEN_19; // @[package.scala:16:47]
wire _dirties_cat_T_31; // @[package.scala:16:47]
assign _dirties_cat_T_31 = _GEN_19; // @[package.scala:16:47]
wire _state_r_c_cat_T_8; // @[package.scala:16:47]
assign _state_r_c_cat_T_8 = _GEN_19; // @[package.scala:16:47]
wire _state_r_c_cat_T_31; // @[package.scala:16:47]
assign _state_r_c_cat_T_31 = _GEN_19; // @[package.scala:16:47]
wire _state_T_11; // @[package.scala:16:47]
assign _state_T_11 = _GEN_19; // @[package.scala:16:47]
wire _r_c_cat_T_58; // @[package.scala:16:47]
assign _r_c_cat_T_58 = _GEN_19; // @[package.scala:16:47]
wire _r_c_cat_T_81; // @[package.scala:16:47]
assign _r_c_cat_T_81 = _GEN_19; // @[package.scala:16:47]
wire _state_r_c_cat_T_58; // @[package.scala:16:47]
assign _state_r_c_cat_T_58 = _GEN_19; // @[package.scala:16:47]
wire _state_r_c_cat_T_81; // @[package.scala:16:47]
assign _state_r_c_cat_T_81 = _GEN_19; // @[package.scala:16:47]
wire _state_T_45; // @[package.scala:16:47]
assign _state_T_45 = _GEN_19; // @[package.scala:16:47]
wire _r2_c_cat_T_9 = _r2_c_cat_T_5 | _r2_c_cat_T_6; // @[package.scala:16:47, :81:59]
wire _r2_c_cat_T_10 = _r2_c_cat_T_9 | _r2_c_cat_T_7; // @[package.scala:16:47, :81:59]
wire _r2_c_cat_T_11 = _r2_c_cat_T_10 | _r2_c_cat_T_8; // @[package.scala:16:47, :81:59]
wire _GEN_20 = io_req_uop_mem_cmd_0 == 5'h8; // @[package.scala:16:47]
wire _r2_c_cat_T_12; // @[package.scala:16:47]
assign _r2_c_cat_T_12 = _GEN_20; // @[package.scala:16:47]
wire _r2_c_cat_T_35; // @[package.scala:16:47]
assign _r2_c_cat_T_35 = _GEN_20; // @[package.scala:16:47]
wire _needs_second_acq_T_12; // @[package.scala:16:47]
assign _needs_second_acq_T_12 = _GEN_20; // @[package.scala:16:47]
wire _dirties_cat_T_12; // @[package.scala:16:47]
assign _dirties_cat_T_12 = _GEN_20; // @[package.scala:16:47]
wire _dirties_cat_T_35; // @[package.scala:16:47]
assign _dirties_cat_T_35 = _GEN_20; // @[package.scala:16:47]
wire _state_r_c_cat_T_12; // @[package.scala:16:47]
assign _state_r_c_cat_T_12 = _GEN_20; // @[package.scala:16:47]
wire _state_r_c_cat_T_35; // @[package.scala:16:47]
assign _state_r_c_cat_T_35 = _GEN_20; // @[package.scala:16:47]
wire _state_T_15; // @[package.scala:16:47]
assign _state_T_15 = _GEN_20; // @[package.scala:16:47]
wire _r_c_cat_T_62; // @[package.scala:16:47]
assign _r_c_cat_T_62 = _GEN_20; // @[package.scala:16:47]
wire _r_c_cat_T_85; // @[package.scala:16:47]
assign _r_c_cat_T_85 = _GEN_20; // @[package.scala:16:47]
wire _state_r_c_cat_T_62; // @[package.scala:16:47]
assign _state_r_c_cat_T_62 = _GEN_20; // @[package.scala:16:47]
wire _state_r_c_cat_T_85; // @[package.scala:16:47]
assign _state_r_c_cat_T_85 = _GEN_20; // @[package.scala:16:47]
wire _state_T_49; // @[package.scala:16:47]
assign _state_T_49 = _GEN_20; // @[package.scala:16:47]
wire _GEN_21 = io_req_uop_mem_cmd_0 == 5'hC; // @[package.scala:16:47]
wire _r2_c_cat_T_13; // @[package.scala:16:47]
assign _r2_c_cat_T_13 = _GEN_21; // @[package.scala:16:47]
wire _r2_c_cat_T_36; // @[package.scala:16:47]
assign _r2_c_cat_T_36 = _GEN_21; // @[package.scala:16:47]
wire _needs_second_acq_T_13; // @[package.scala:16:47]
assign _needs_second_acq_T_13 = _GEN_21; // @[package.scala:16:47]
wire _dirties_cat_T_13; // @[package.scala:16:47]
assign _dirties_cat_T_13 = _GEN_21; // @[package.scala:16:47]
wire _dirties_cat_T_36; // @[package.scala:16:47]
assign _dirties_cat_T_36 = _GEN_21; // @[package.scala:16:47]
wire _state_r_c_cat_T_13; // @[package.scala:16:47]
assign _state_r_c_cat_T_13 = _GEN_21; // @[package.scala:16:47]
wire _state_r_c_cat_T_36; // @[package.scala:16:47]
assign _state_r_c_cat_T_36 = _GEN_21; // @[package.scala:16:47]
wire _state_T_16; // @[package.scala:16:47]
assign _state_T_16 = _GEN_21; // @[package.scala:16:47]
wire _r_c_cat_T_63; // @[package.scala:16:47]
assign _r_c_cat_T_63 = _GEN_21; // @[package.scala:16:47]
wire _r_c_cat_T_86; // @[package.scala:16:47]
assign _r_c_cat_T_86 = _GEN_21; // @[package.scala:16:47]
wire _state_r_c_cat_T_63; // @[package.scala:16:47]
assign _state_r_c_cat_T_63 = _GEN_21; // @[package.scala:16:47]
wire _state_r_c_cat_T_86; // @[package.scala:16:47]
assign _state_r_c_cat_T_86 = _GEN_21; // @[package.scala:16:47]
wire _state_T_50; // @[package.scala:16:47]
assign _state_T_50 = _GEN_21; // @[package.scala:16:47]
wire _GEN_22 = io_req_uop_mem_cmd_0 == 5'hD; // @[package.scala:16:47]
wire _r2_c_cat_T_14; // @[package.scala:16:47]
assign _r2_c_cat_T_14 = _GEN_22; // @[package.scala:16:47]
wire _r2_c_cat_T_37; // @[package.scala:16:47]
assign _r2_c_cat_T_37 = _GEN_22; // @[package.scala:16:47]
wire _needs_second_acq_T_14; // @[package.scala:16:47]
assign _needs_second_acq_T_14 = _GEN_22; // @[package.scala:16:47]
wire _dirties_cat_T_14; // @[package.scala:16:47]
assign _dirties_cat_T_14 = _GEN_22; // @[package.scala:16:47]
wire _dirties_cat_T_37; // @[package.scala:16:47]
assign _dirties_cat_T_37 = _GEN_22; // @[package.scala:16:47]
wire _state_r_c_cat_T_14; // @[package.scala:16:47]
assign _state_r_c_cat_T_14 = _GEN_22; // @[package.scala:16:47]
wire _state_r_c_cat_T_37; // @[package.scala:16:47]
assign _state_r_c_cat_T_37 = _GEN_22; // @[package.scala:16:47]
wire _state_T_17; // @[package.scala:16:47]
assign _state_T_17 = _GEN_22; // @[package.scala:16:47]
wire _r_c_cat_T_64; // @[package.scala:16:47]
assign _r_c_cat_T_64 = _GEN_22; // @[package.scala:16:47]
wire _r_c_cat_T_87; // @[package.scala:16:47]
assign _r_c_cat_T_87 = _GEN_22; // @[package.scala:16:47]
wire _state_r_c_cat_T_64; // @[package.scala:16:47]
assign _state_r_c_cat_T_64 = _GEN_22; // @[package.scala:16:47]
wire _state_r_c_cat_T_87; // @[package.scala:16:47]
assign _state_r_c_cat_T_87 = _GEN_22; // @[package.scala:16:47]
wire _state_T_51; // @[package.scala:16:47]
assign _state_T_51 = _GEN_22; // @[package.scala:16:47]
wire _GEN_23 = io_req_uop_mem_cmd_0 == 5'hE; // @[package.scala:16:47]
wire _r2_c_cat_T_15; // @[package.scala:16:47]
assign _r2_c_cat_T_15 = _GEN_23; // @[package.scala:16:47]
wire _r2_c_cat_T_38; // @[package.scala:16:47]
assign _r2_c_cat_T_38 = _GEN_23; // @[package.scala:16:47]
wire _needs_second_acq_T_15; // @[package.scala:16:47]
assign _needs_second_acq_T_15 = _GEN_23; // @[package.scala:16:47]
wire _dirties_cat_T_15; // @[package.scala:16:47]
assign _dirties_cat_T_15 = _GEN_23; // @[package.scala:16:47]
wire _dirties_cat_T_38; // @[package.scala:16:47]
assign _dirties_cat_T_38 = _GEN_23; // @[package.scala:16:47]
wire _state_r_c_cat_T_15; // @[package.scala:16:47]
assign _state_r_c_cat_T_15 = _GEN_23; // @[package.scala:16:47]
wire _state_r_c_cat_T_38; // @[package.scala:16:47]
assign _state_r_c_cat_T_38 = _GEN_23; // @[package.scala:16:47]
wire _state_T_18; // @[package.scala:16:47]
assign _state_T_18 = _GEN_23; // @[package.scala:16:47]
wire _r_c_cat_T_65; // @[package.scala:16:47]
assign _r_c_cat_T_65 = _GEN_23; // @[package.scala:16:47]
wire _r_c_cat_T_88; // @[package.scala:16:47]
assign _r_c_cat_T_88 = _GEN_23; // @[package.scala:16:47]
wire _state_r_c_cat_T_65; // @[package.scala:16:47]
assign _state_r_c_cat_T_65 = _GEN_23; // @[package.scala:16:47]
wire _state_r_c_cat_T_88; // @[package.scala:16:47]
assign _state_r_c_cat_T_88 = _GEN_23; // @[package.scala:16:47]
wire _state_T_52; // @[package.scala:16:47]
assign _state_T_52 = _GEN_23; // @[package.scala:16:47]
wire _GEN_24 = io_req_uop_mem_cmd_0 == 5'hF; // @[package.scala:16:47]
wire _r2_c_cat_T_16; // @[package.scala:16:47]
assign _r2_c_cat_T_16 = _GEN_24; // @[package.scala:16:47]
wire _r2_c_cat_T_39; // @[package.scala:16:47]
assign _r2_c_cat_T_39 = _GEN_24; // @[package.scala:16:47]
wire _needs_second_acq_T_16; // @[package.scala:16:47]
assign _needs_second_acq_T_16 = _GEN_24; // @[package.scala:16:47]
wire _dirties_cat_T_16; // @[package.scala:16:47]
assign _dirties_cat_T_16 = _GEN_24; // @[package.scala:16:47]
wire _dirties_cat_T_39; // @[package.scala:16:47]
assign _dirties_cat_T_39 = _GEN_24; // @[package.scala:16:47]
wire _state_r_c_cat_T_16; // @[package.scala:16:47]
assign _state_r_c_cat_T_16 = _GEN_24; // @[package.scala:16:47]
wire _state_r_c_cat_T_39; // @[package.scala:16:47]
assign _state_r_c_cat_T_39 = _GEN_24; // @[package.scala:16:47]
wire _state_T_19; // @[package.scala:16:47]
assign _state_T_19 = _GEN_24; // @[package.scala:16:47]
wire _r_c_cat_T_66; // @[package.scala:16:47]
assign _r_c_cat_T_66 = _GEN_24; // @[package.scala:16:47]
wire _r_c_cat_T_89; // @[package.scala:16:47]
assign _r_c_cat_T_89 = _GEN_24; // @[package.scala:16:47]
wire _state_r_c_cat_T_66; // @[package.scala:16:47]
assign _state_r_c_cat_T_66 = _GEN_24; // @[package.scala:16:47]
wire _state_r_c_cat_T_89; // @[package.scala:16:47]
assign _state_r_c_cat_T_89 = _GEN_24; // @[package.scala:16:47]
wire _state_T_53; // @[package.scala:16:47]
assign _state_T_53 = _GEN_24; // @[package.scala:16:47]
wire _r2_c_cat_T_17 = _r2_c_cat_T_12 | _r2_c_cat_T_13; // @[package.scala:16:47, :81:59]
wire _r2_c_cat_T_18 = _r2_c_cat_T_17 | _r2_c_cat_T_14; // @[package.scala:16:47, :81:59]
wire _r2_c_cat_T_19 = _r2_c_cat_T_18 | _r2_c_cat_T_15; // @[package.scala:16:47, :81:59]
wire _r2_c_cat_T_20 = _r2_c_cat_T_19 | _r2_c_cat_T_16; // @[package.scala:16:47, :81:59]
wire _r2_c_cat_T_21 = _r2_c_cat_T_11 | _r2_c_cat_T_20; // @[package.scala:81:59]
wire _r2_c_cat_T_22 = _r2_c_cat_T_4 | _r2_c_cat_T_21; // @[Consts.scala:87:44, :90:{59,76}]
wire _r2_c_cat_T_25 = _r2_c_cat_T_23 | _r2_c_cat_T_24; // @[Consts.scala:90:{32,42,49}]
wire _r2_c_cat_T_27 = _r2_c_cat_T_25 | _r2_c_cat_T_26; // @[Consts.scala:90:{42,59,66}]
wire _r2_c_cat_T_32 = _r2_c_cat_T_28 | _r2_c_cat_T_29; // @[package.scala:16:47, :81:59]
wire _r2_c_cat_T_33 = _r2_c_cat_T_32 | _r2_c_cat_T_30; // @[package.scala:16:47, :81:59]
wire _r2_c_cat_T_34 = _r2_c_cat_T_33 | _r2_c_cat_T_31; // @[package.scala:16:47, :81:59]
wire _r2_c_cat_T_40 = _r2_c_cat_T_35 | _r2_c_cat_T_36; // @[package.scala:16:47, :81:59]
wire _r2_c_cat_T_41 = _r2_c_cat_T_40 | _r2_c_cat_T_37; // @[package.scala:16:47, :81:59]
wire _r2_c_cat_T_42 = _r2_c_cat_T_41 | _r2_c_cat_T_38; // @[package.scala:16:47, :81:59]
wire _r2_c_cat_T_43 = _r2_c_cat_T_42 | _r2_c_cat_T_39; // @[package.scala:16:47, :81:59]
wire _r2_c_cat_T_44 = _r2_c_cat_T_34 | _r2_c_cat_T_43; // @[package.scala:81:59]
wire _r2_c_cat_T_45 = _r2_c_cat_T_27 | _r2_c_cat_T_44; // @[Consts.scala:87:44, :90:{59,76}]
wire _GEN_25 = io_req_uop_mem_cmd_0 == 5'h3; // @[Consts.scala:91:54]
wire _r2_c_cat_T_46; // @[Consts.scala:91:54]
assign _r2_c_cat_T_46 = _GEN_25; // @[Consts.scala:91:54]
wire _needs_second_acq_T_23; // @[Consts.scala:91:54]
assign _needs_second_acq_T_23 = _GEN_25; // @[Consts.scala:91:54]
wire _dirties_cat_T_46; // @[Consts.scala:91:54]
assign _dirties_cat_T_46 = _GEN_25; // @[Consts.scala:91:54]
wire _rpq_io_enq_valid_T_4; // @[Consts.scala:88:52]
assign _rpq_io_enq_valid_T_4 = _GEN_25; // @[Consts.scala:88:52, :91:54]
wire _state_r_c_cat_T_46; // @[Consts.scala:91:54]
assign _state_r_c_cat_T_46 = _GEN_25; // @[Consts.scala:91:54]
wire _r_c_cat_T_96; // @[Consts.scala:91:54]
assign _r_c_cat_T_96 = _GEN_25; // @[Consts.scala:91:54]
wire _state_r_c_cat_T_96; // @[Consts.scala:91:54]
assign _state_r_c_cat_T_96 = _GEN_25; // @[Consts.scala:91:54]
wire _r2_c_cat_T_47 = _r2_c_cat_T_45 | _r2_c_cat_T_46; // @[Consts.scala:90:76, :91:{47,54}]
wire _GEN_26 = io_req_uop_mem_cmd_0 == 5'h6; // @[Consts.scala:91:71]
wire _r2_c_cat_T_48; // @[Consts.scala:91:71]
assign _r2_c_cat_T_48 = _GEN_26; // @[Consts.scala:91:71]
wire _needs_second_acq_T_25; // @[Consts.scala:91:71]
assign _needs_second_acq_T_25 = _GEN_26; // @[Consts.scala:91:71]
wire _dirties_cat_T_48; // @[Consts.scala:91:71]
assign _dirties_cat_T_48 = _GEN_26; // @[Consts.scala:91:71]
wire _state_r_c_cat_T_48; // @[Consts.scala:91:71]
assign _state_r_c_cat_T_48 = _GEN_26; // @[Consts.scala:91:71]
wire _r_c_cat_T_98; // @[Consts.scala:91:71]
assign _r_c_cat_T_98 = _GEN_26; // @[Consts.scala:91:71]
wire _state_r_c_cat_T_98; // @[Consts.scala:91:71]
assign _state_r_c_cat_T_98 = _GEN_26; // @[Consts.scala:91:71]
wire _r2_c_cat_T_49 = _r2_c_cat_T_47 | _r2_c_cat_T_48; // @[Consts.scala:91:{47,64,71}]
wire [1:0] r2_c = {_r2_c_cat_T_22, _r2_c_cat_T_49}; // @[Metadata.scala:29:18]
wire [3:0] _r2_T = {r2_c, new_coh_state}; // @[Metadata.scala:29:18, :58:19]
wire _r2_T_25 = _r2_T == 4'hC; // @[Misc.scala:49:20]
wire [1:0] _r2_T_27 = {1'h0, _r2_T_25}; // @[Misc.scala:35:36, :49:20]
wire _r2_T_28 = _r2_T == 4'hD; // @[Misc.scala:49:20]
wire [1:0] _r2_T_30 = _r2_T_28 ? 2'h2 : _r2_T_27; // @[Misc.scala:35:36, :49:20]
wire _r2_T_31 = _r2_T == 4'h4; // @[Misc.scala:49:20]
wire [1:0] _r2_T_33 = _r2_T_31 ? 2'h1 : _r2_T_30; // @[Misc.scala:35:36, :49:20]
wire _r2_T_34 = _r2_T == 4'h5; // @[Misc.scala:49:20]
wire [1:0] _r2_T_36 = _r2_T_34 ? 2'h2 : _r2_T_33; // @[Misc.scala:35:36, :49:20]
wire _r2_T_37 = _r2_T == 4'h0; // @[Misc.scala:49:20]
wire [1:0] _r2_T_39 = _r2_T_37 ? 2'h0 : _r2_T_36; // @[Misc.scala:35:36, :49:20]
wire _r2_T_40 = _r2_T == 4'hE; // @[Misc.scala:49:20]
wire _r2_T_41 = _r2_T_40; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r2_T_42 = _r2_T_40 ? 2'h3 : _r2_T_39; // @[Misc.scala:35:36, :49:20]
wire _r2_T_43 = &_r2_T; // @[Misc.scala:49:20]
wire _r2_T_44 = _r2_T_43 | _r2_T_41; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r2_T_45 = _r2_T_43 ? 2'h3 : _r2_T_42; // @[Misc.scala:35:36, :49:20]
wire _r2_T_46 = _r2_T == 4'h6; // @[Misc.scala:49:20]
wire _r2_T_47 = _r2_T_46 | _r2_T_44; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r2_T_48 = _r2_T_46 ? 2'h2 : _r2_T_45; // @[Misc.scala:35:36, :49:20]
wire _r2_T_49 = _r2_T == 4'h7; // @[Misc.scala:49:20]
wire _r2_T_50 = _r2_T_49 | _r2_T_47; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r2_T_51 = _r2_T_49 ? 2'h3 : _r2_T_48; // @[Misc.scala:35:36, :49:20]
wire _r2_T_52 = _r2_T == 4'h1; // @[Misc.scala:49:20]
wire _r2_T_53 = _r2_T_52 | _r2_T_50; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r2_T_54 = _r2_T_52 ? 2'h1 : _r2_T_51; // @[Misc.scala:35:36, :49:20]
wire _r2_T_55 = _r2_T == 4'h2; // @[Misc.scala:49:20]
wire _r2_T_56 = _r2_T_55 | _r2_T_53; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r2_T_57 = _r2_T_55 ? 2'h2 : _r2_T_54; // @[Misc.scala:35:36, :49:20]
wire _r2_T_58 = _r2_T == 4'h3; // @[Misc.scala:49:20]
wire r2_1 = _r2_T_58 | _r2_T_56; // @[Misc.scala:35:9, :49:20]
wire [1:0] r2_2 = _r2_T_58 ? 2'h3 : _r2_T_57; // @[Misc.scala:35:36, :49:20]
wire _needs_second_acq_T_2 = _needs_second_acq_T | _needs_second_acq_T_1; // @[Consts.scala:90:{32,42,49}]
wire _needs_second_acq_T_4 = _needs_second_acq_T_2 | _needs_second_acq_T_3; // @[Consts.scala:90:{42,59,66}]
wire _needs_second_acq_T_9 = _needs_second_acq_T_5 | _needs_second_acq_T_6; // @[package.scala:16:47, :81:59]
wire _needs_second_acq_T_10 = _needs_second_acq_T_9 | _needs_second_acq_T_7; // @[package.scala:16:47, :81:59]
wire _needs_second_acq_T_11 = _needs_second_acq_T_10 | _needs_second_acq_T_8; // @[package.scala:16:47, :81:59]
wire _needs_second_acq_T_17 = _needs_second_acq_T_12 | _needs_second_acq_T_13; // @[package.scala:16:47, :81:59]
wire _needs_second_acq_T_18 = _needs_second_acq_T_17 | _needs_second_acq_T_14; // @[package.scala:16:47, :81:59]
wire _needs_second_acq_T_19 = _needs_second_acq_T_18 | _needs_second_acq_T_15; // @[package.scala:16:47, :81:59]
wire _needs_second_acq_T_20 = _needs_second_acq_T_19 | _needs_second_acq_T_16; // @[package.scala:16:47, :81:59]
wire _needs_second_acq_T_21 = _needs_second_acq_T_11 | _needs_second_acq_T_20; // @[package.scala:81:59]
wire _needs_second_acq_T_22 = _needs_second_acq_T_4 | _needs_second_acq_T_21; // @[Consts.scala:87:44, :90:{59,76}]
wire _needs_second_acq_T_24 = _needs_second_acq_T_22 | _needs_second_acq_T_23; // @[Consts.scala:90:76, :91:{47,54}]
wire _needs_second_acq_T_26 = _needs_second_acq_T_24 | _needs_second_acq_T_25; // @[Consts.scala:91:{47,64,71}]
wire _needs_second_acq_T_29 = _needs_second_acq_T_27 | _needs_second_acq_T_28; // @[Consts.scala:90:{32,42,49}]
wire _needs_second_acq_T_31 = _needs_second_acq_T_29 | _needs_second_acq_T_30; // @[Consts.scala:90:{42,59,66}]
wire _needs_second_acq_T_36 = _needs_second_acq_T_32 | _needs_second_acq_T_33; // @[package.scala:16:47, :81:59]
wire _needs_second_acq_T_37 = _needs_second_acq_T_36 | _needs_second_acq_T_34; // @[package.scala:16:47, :81:59]
wire _needs_second_acq_T_38 = _needs_second_acq_T_37 | _needs_second_acq_T_35; // @[package.scala:16:47, :81:59]
wire _needs_second_acq_T_44 = _needs_second_acq_T_39 | _needs_second_acq_T_40; // @[package.scala:16:47, :81:59]
wire _needs_second_acq_T_45 = _needs_second_acq_T_44 | _needs_second_acq_T_41; // @[package.scala:16:47, :81:59]
wire _needs_second_acq_T_46 = _needs_second_acq_T_45 | _needs_second_acq_T_42; // @[package.scala:16:47, :81:59]
wire _needs_second_acq_T_47 = _needs_second_acq_T_46 | _needs_second_acq_T_43; // @[package.scala:16:47, :81:59]
wire _needs_second_acq_T_48 = _needs_second_acq_T_38 | _needs_second_acq_T_47; // @[package.scala:81:59]
wire _needs_second_acq_T_49 = _needs_second_acq_T_31 | _needs_second_acq_T_48; // @[Consts.scala:87:44, :90:{59,76}]
wire _needs_second_acq_T_51 = _needs_second_acq_T_49 | _needs_second_acq_T_50; // @[Consts.scala:90:76, :91:{47,54}]
wire _needs_second_acq_T_53 = _needs_second_acq_T_51 | _needs_second_acq_T_52; // @[Consts.scala:91:{47,64,71}]
wire _needs_second_acq_T_54 = ~_needs_second_acq_T_53; // @[Metadata.scala:104:57]
wire cmd_requires_second_acquire = _needs_second_acq_T_26 & _needs_second_acq_T_54; // @[Metadata.scala:104:{54,57}]
wire is_hit_again = r1_1 & r2_1; // @[Misc.scala:35:9]
wire _dirties_cat_T_2 = _dirties_cat_T | _dirties_cat_T_1; // @[Consts.scala:90:{32,42,49}]
wire _dirties_cat_T_4 = _dirties_cat_T_2 | _dirties_cat_T_3; // @[Consts.scala:90:{42,59,66}]
wire _dirties_cat_T_9 = _dirties_cat_T_5 | _dirties_cat_T_6; // @[package.scala:16:47, :81:59]
wire _dirties_cat_T_10 = _dirties_cat_T_9 | _dirties_cat_T_7; // @[package.scala:16:47, :81:59]
wire _dirties_cat_T_11 = _dirties_cat_T_10 | _dirties_cat_T_8; // @[package.scala:16:47, :81:59]
wire _dirties_cat_T_17 = _dirties_cat_T_12 | _dirties_cat_T_13; // @[package.scala:16:47, :81:59]
wire _dirties_cat_T_18 = _dirties_cat_T_17 | _dirties_cat_T_14; // @[package.scala:16:47, :81:59]
wire _dirties_cat_T_19 = _dirties_cat_T_18 | _dirties_cat_T_15; // @[package.scala:16:47, :81:59]
wire _dirties_cat_T_20 = _dirties_cat_T_19 | _dirties_cat_T_16; // @[package.scala:16:47, :81:59]
wire _dirties_cat_T_21 = _dirties_cat_T_11 | _dirties_cat_T_20; // @[package.scala:81:59]
wire _dirties_cat_T_22 = _dirties_cat_T_4 | _dirties_cat_T_21; // @[Consts.scala:87:44, :90:{59,76}]
wire _dirties_cat_T_25 = _dirties_cat_T_23 | _dirties_cat_T_24; // @[Consts.scala:90:{32,42,49}]
wire _dirties_cat_T_27 = _dirties_cat_T_25 | _dirties_cat_T_26; // @[Consts.scala:90:{42,59,66}]
wire _dirties_cat_T_32 = _dirties_cat_T_28 | _dirties_cat_T_29; // @[package.scala:16:47, :81:59]
wire _dirties_cat_T_33 = _dirties_cat_T_32 | _dirties_cat_T_30; // @[package.scala:16:47, :81:59]
wire _dirties_cat_T_34 = _dirties_cat_T_33 | _dirties_cat_T_31; // @[package.scala:16:47, :81:59]
wire _dirties_cat_T_40 = _dirties_cat_T_35 | _dirties_cat_T_36; // @[package.scala:16:47, :81:59]
wire _dirties_cat_T_41 = _dirties_cat_T_40 | _dirties_cat_T_37; // @[package.scala:16:47, :81:59]
wire _dirties_cat_T_42 = _dirties_cat_T_41 | _dirties_cat_T_38; // @[package.scala:16:47, :81:59]
wire _dirties_cat_T_43 = _dirties_cat_T_42 | _dirties_cat_T_39; // @[package.scala:16:47, :81:59]
wire _dirties_cat_T_44 = _dirties_cat_T_34 | _dirties_cat_T_43; // @[package.scala:81:59]
wire _dirties_cat_T_45 = _dirties_cat_T_27 | _dirties_cat_T_44; // @[Consts.scala:87:44, :90:{59,76}]
wire _dirties_cat_T_47 = _dirties_cat_T_45 | _dirties_cat_T_46; // @[Consts.scala:90:76, :91:{47,54}]
wire _dirties_cat_T_49 = _dirties_cat_T_47 | _dirties_cat_T_48; // @[Consts.scala:91:{47,64,71}]
wire [1:0] dirties_cat = {_dirties_cat_T_22, _dirties_cat_T_49}; // @[Metadata.scala:29:18]
wire dirties = &dirties_cat; // @[Metadata.scala:29:18, :106:42]
wire [1:0] biggest_grow_param = dirties ? r2_2 : r1_2; // @[Misc.scala:35:36]
wire [1:0] dirtier_coh_state = biggest_grow_param; // @[Metadata.scala:107:33, :160:20]
wire [4:0] dirtier_cmd = dirties ? io_req_uop_mem_cmd_0 : req_uop_mem_cmd; // @[Metadata.scala:106:42, :109:27]
wire _T_16 = io_mem_grant_ready_0 & io_mem_grant_valid_0; // @[Decoupled.scala:51:35]
wire [26:0] _r_beats1_decode_T = 27'hFFF << io_mem_grant_bits_size_0; // @[package.scala:243:71]
wire [11:0] _r_beats1_decode_T_1 = _r_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _r_beats1_decode_T_2 = ~_r_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [8:0] r_beats1_decode = _r_beats1_decode_T_2[11:3]; // @[package.scala:243:46]
wire r_beats1_opdata = io_mem_grant_bits_opcode_0[0]; // @[Edges.scala:106:36]
wire opdata = io_mem_grant_bits_opcode_0[0]; // @[Edges.scala:106:36]
wire grant_had_data_opdata = io_mem_grant_bits_opcode_0[0]; // @[Edges.scala:106:36]
wire [8:0] r_beats1 = r_beats1_opdata ? r_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [8:0] r_counter; // @[Edges.scala:229:27]
wire [9:0] _r_counter1_T = {1'h0, r_counter} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] r_counter1 = _r_counter1_T[8:0]; // @[Edges.scala:230:28]
wire r_1_1 = r_counter == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _r_last_T = r_counter == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _r_last_T_1 = r_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire r_2 = _r_last_T | _r_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire refill_done = r_2 & _T_16; // @[Decoupled.scala:51:35]
wire [8:0] _r_count_T = ~r_counter1; // @[Edges.scala:230:28, :234:27]
wire [8:0] r_4 = r_beats1 & _r_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _r_counter_T = r_1_1 ? r_beats1 : r_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [11:0] refill_address_inc = {r_4, 3'h0}; // @[Edges.scala:234:25, :269:29]
wire _sec_rdy_T = ~cmd_requires_second_acquire; // @[Metadata.scala:104:54]
wire _sec_rdy_T_1 = ~io_req_is_probe_0; // @[mshrs.scala:36:7, :125:50]
wire _sec_rdy_T_2 = _sec_rdy_T & _sec_rdy_T_1; // @[mshrs.scala:125:{18,47,50}]
wire _sec_rdy_T_3 = ~(|state); // @[package.scala:16:47]
wire _sec_rdy_T_4 = state == 5'hD; // @[package.scala:16:47]
wire _sec_rdy_T_5 = state == 5'hE; // @[package.scala:16:47]
wire _sec_rdy_T_6 = state == 5'hF; // @[package.scala:16:47]
wire _sec_rdy_T_7 = _sec_rdy_T_3 | _sec_rdy_T_4; // @[package.scala:16:47, :81:59]
wire _sec_rdy_T_8 = _sec_rdy_T_7 | _sec_rdy_T_5; // @[package.scala:16:47, :81:59]
wire _sec_rdy_T_9 = _sec_rdy_T_8 | _sec_rdy_T_6; // @[package.scala:16:47, :81:59]
wire _sec_rdy_T_10 = ~_sec_rdy_T_9; // @[package.scala:81:59]
wire sec_rdy = _sec_rdy_T_2 & _sec_rdy_T_10; // @[mshrs.scala:125:{47,67}, :126:18]
wire _rpq_io_enq_valid_T = io_req_pri_val_0 & io_req_pri_rdy_0; // @[mshrs.scala:36:7, :133:40]
wire _rpq_io_enq_valid_T_1 = io_req_sec_val_0 & io_req_sec_rdy_0; // @[mshrs.scala:36:7, :133:78]
wire _rpq_io_enq_valid_T_2 = _rpq_io_enq_valid_T | _rpq_io_enq_valid_T_1; // @[mshrs.scala:133:{40,59,78}]
wire _rpq_io_enq_valid_T_3 = io_req_uop_mem_cmd_0 == 5'h2; // @[Consts.scala:88:35]
wire _rpq_io_enq_valid_T_5 = _rpq_io_enq_valid_T_3 | _rpq_io_enq_valid_T_4; // @[Consts.scala:88:{35,45,52}]
wire _rpq_io_enq_valid_T_6 = ~_rpq_io_enq_valid_T_5; // @[Consts.scala:88:45]
wire _rpq_io_enq_valid_T_7 = _rpq_io_enq_valid_T_2 & _rpq_io_enq_valid_T_6; // @[mshrs.scala:133:{59,98,101}]
reg grantack_valid; // @[mshrs.scala:138:21]
reg [2:0] grantack_bits_sink; // @[mshrs.scala:138:21]
assign io_mem_finish_bits_sink_0 = grantack_bits_sink; // @[mshrs.scala:36:7, :138:21]
reg [2:0] refill_ctr; // @[mshrs.scala:139:24]
reg commit_line; // @[mshrs.scala:140:24]
reg grant_had_data; // @[mshrs.scala:141:27]
reg finish_to_prefetch; // @[mshrs.scala:142:31]
reg [1:0] meta_hazard; // @[mshrs.scala:145:28]
wire [2:0] _meta_hazard_T = {1'h0, meta_hazard} + 3'h1; // @[mshrs.scala:145:28, :146:59]
wire [1:0] _meta_hazard_T_1 = _meta_hazard_T[1:0]; // @[mshrs.scala:146:59]
wire _io_probe_rdy_T = meta_hazard == 2'h0; // @[mshrs.scala:145:28, :148:34]
wire _io_probe_rdy_T_1 = ~(|state); // @[package.scala:16:47]
wire _io_probe_rdy_T_2 = state == 5'h1; // @[package.scala:16:47]
wire _io_probe_rdy_T_3 = state == 5'h2; // @[package.scala:16:47]
wire _io_probe_rdy_T_4 = state == 5'h3; // @[package.scala:16:47]
wire _io_probe_rdy_T_5 = _io_probe_rdy_T_1 | _io_probe_rdy_T_2; // @[package.scala:16:47, :81:59]
wire _io_probe_rdy_T_6 = _io_probe_rdy_T_5 | _io_probe_rdy_T_3; // @[package.scala:16:47, :81:59]
wire _io_probe_rdy_T_7 = _io_probe_rdy_T_6 | _io_probe_rdy_T_4; // @[package.scala:16:47, :81:59]
wire _io_probe_rdy_T_8 = state == 5'h4; // @[mshrs.scala:107:22, :148:129]
wire _io_probe_rdy_T_9 = _io_probe_rdy_T_8 & grantack_valid; // @[mshrs.scala:138:21, :148:{129,145}]
wire _io_probe_rdy_T_10 = _io_probe_rdy_T_7 | _io_probe_rdy_T_9; // @[package.scala:81:59]
assign _io_probe_rdy_T_11 = _io_probe_rdy_T & _io_probe_rdy_T_10; // @[mshrs.scala:148:{34,42,119}]
assign io_probe_rdy_0 = _io_probe_rdy_T_11; // @[mshrs.scala:36:7, :148:42]
assign _io_idx_valid_T = |state; // @[package.scala:16:47]
assign io_idx_valid_0 = _io_idx_valid_T; // @[mshrs.scala:36:7, :149:25]
assign _io_tag_valid_T = |state; // @[package.scala:16:47]
assign io_tag_valid_0 = _io_tag_valid_T; // @[mshrs.scala:36:7, :150:25]
wire _io_way_valid_T = ~(|state); // @[package.scala:16:47]
wire _io_way_valid_T_1 = state == 5'h11; // @[package.scala:16:47]
wire _io_way_valid_T_2 = _io_way_valid_T | _io_way_valid_T_1; // @[package.scala:16:47, :81:59]
assign _io_way_valid_T_3 = ~_io_way_valid_T_2; // @[package.scala:81:59]
assign io_way_valid_0 = _io_way_valid_T_3; // @[mshrs.scala:36:7, :151:19]
assign _io_req_sec_rdy_T = sec_rdy & _rpq_io_enq_ready; // @[mshrs.scala:125:67, :128:19, :159:37]
assign io_req_sec_rdy_0 = _io_req_sec_rdy_T; // @[mshrs.scala:36:7, :159:37]
wire [4:0] state_new_state; // @[mshrs.scala:191:29]
wire _state_T_1 = ~_state_T; // @[mshrs.scala:194:11]
wire _state_T_2 = ~_rpq_io_enq_ready; // @[mshrs.scala:128:19, :194:11]
wire [3:0] _GEN_27 = {2'h2, io_req_old_meta_coh_state_0}; // @[Metadata.scala:120:19]
wire [3:0] _state_req_needs_wb_r_T_6; // @[Metadata.scala:120:19]
assign _state_req_needs_wb_r_T_6 = _GEN_27; // @[Metadata.scala:120:19]
wire [3:0] _state_req_needs_wb_r_T_70; // @[Metadata.scala:120:19]
assign _state_req_needs_wb_r_T_70 = _GEN_27; // @[Metadata.scala:120:19]
wire _state_req_needs_wb_r_T_19 = _state_req_needs_wb_r_T_6 == 4'h8; // @[Misc.scala:56:20]
wire [2:0] _state_req_needs_wb_r_T_21 = _state_req_needs_wb_r_T_19 ? 3'h5 : 3'h0; // @[Misc.scala:38:36, :56:20]
wire _state_req_needs_wb_r_T_23 = _state_req_needs_wb_r_T_6 == 4'h9; // @[Misc.scala:56:20]
wire [2:0] _state_req_needs_wb_r_T_25 = _state_req_needs_wb_r_T_23 ? 3'h2 : _state_req_needs_wb_r_T_21; // @[Misc.scala:38:36, :56:20]
wire _state_req_needs_wb_r_T_27 = _state_req_needs_wb_r_T_6 == 4'hA; // @[Misc.scala:56:20]
wire [2:0] _state_req_needs_wb_r_T_29 = _state_req_needs_wb_r_T_27 ? 3'h1 : _state_req_needs_wb_r_T_25; // @[Misc.scala:38:36, :56:20]
wire _state_req_needs_wb_r_T_31 = _state_req_needs_wb_r_T_6 == 4'hB; // @[Misc.scala:56:20]
wire _state_req_needs_wb_r_T_32 = _state_req_needs_wb_r_T_31; // @[Misc.scala:38:9, :56:20]
wire [2:0] _state_req_needs_wb_r_T_33 = _state_req_needs_wb_r_T_31 ? 3'h1 : _state_req_needs_wb_r_T_29; // @[Misc.scala:38:36, :56:20]
wire _state_req_needs_wb_r_T_35 = _state_req_needs_wb_r_T_6 == 4'h4; // @[Misc.scala:56:20]
wire _state_req_needs_wb_r_T_36 = ~_state_req_needs_wb_r_T_35 & _state_req_needs_wb_r_T_32; // @[Misc.scala:38:9, :56:20]
wire [2:0] _state_req_needs_wb_r_T_37 = _state_req_needs_wb_r_T_35 ? 3'h5 : _state_req_needs_wb_r_T_33; // @[Misc.scala:38:36, :56:20]
wire _state_req_needs_wb_r_T_39 = _state_req_needs_wb_r_T_6 == 4'h5; // @[Misc.scala:56:20]
wire _state_req_needs_wb_r_T_40 = ~_state_req_needs_wb_r_T_39 & _state_req_needs_wb_r_T_36; // @[Misc.scala:38:9, :56:20]
wire [2:0] _state_req_needs_wb_r_T_41 = _state_req_needs_wb_r_T_39 ? 3'h4 : _state_req_needs_wb_r_T_37; // @[Misc.scala:38:36, :56:20]
wire [1:0] _state_req_needs_wb_r_T_42 = {1'h0, _state_req_needs_wb_r_T_39}; // @[Misc.scala:38:63, :56:20]
wire _state_req_needs_wb_r_T_43 = _state_req_needs_wb_r_T_6 == 4'h6; // @[Misc.scala:56:20]
wire _state_req_needs_wb_r_T_44 = ~_state_req_needs_wb_r_T_43 & _state_req_needs_wb_r_T_40; // @[Misc.scala:38:9, :56:20]
wire [2:0] _state_req_needs_wb_r_T_45 = _state_req_needs_wb_r_T_43 ? 3'h0 : _state_req_needs_wb_r_T_41; // @[Misc.scala:38:36, :56:20]
wire [1:0] _state_req_needs_wb_r_T_46 = _state_req_needs_wb_r_T_43 ? 2'h1 : _state_req_needs_wb_r_T_42; // @[Misc.scala:38:63, :56:20]
wire _state_req_needs_wb_r_T_47 = _state_req_needs_wb_r_T_6 == 4'h7; // @[Misc.scala:56:20]
wire _state_req_needs_wb_r_T_48 = _state_req_needs_wb_r_T_47 | _state_req_needs_wb_r_T_44; // @[Misc.scala:38:9, :56:20]
wire [2:0] _state_req_needs_wb_r_T_49 = _state_req_needs_wb_r_T_47 ? 3'h0 : _state_req_needs_wb_r_T_45; // @[Misc.scala:38:36, :56:20]
wire [1:0] _state_req_needs_wb_r_T_50 = _state_req_needs_wb_r_T_47 ? 2'h1 : _state_req_needs_wb_r_T_46; // @[Misc.scala:38:63, :56:20]
wire _state_req_needs_wb_r_T_51 = _state_req_needs_wb_r_T_6 == 4'h0; // @[Misc.scala:56:20]
wire _state_req_needs_wb_r_T_52 = ~_state_req_needs_wb_r_T_51 & _state_req_needs_wb_r_T_48; // @[Misc.scala:38:9, :56:20]
wire [2:0] _state_req_needs_wb_r_T_53 = _state_req_needs_wb_r_T_51 ? 3'h5 : _state_req_needs_wb_r_T_49; // @[Misc.scala:38:36, :56:20]
wire [1:0] _state_req_needs_wb_r_T_54 = _state_req_needs_wb_r_T_51 ? 2'h0 : _state_req_needs_wb_r_T_50; // @[Misc.scala:38:63, :56:20]
wire _state_req_needs_wb_r_T_55 = _state_req_needs_wb_r_T_6 == 4'h1; // @[Misc.scala:56:20]
wire _state_req_needs_wb_r_T_56 = ~_state_req_needs_wb_r_T_55 & _state_req_needs_wb_r_T_52; // @[Misc.scala:38:9, :56:20]
wire [2:0] _state_req_needs_wb_r_T_57 = _state_req_needs_wb_r_T_55 ? 3'h4 : _state_req_needs_wb_r_T_53; // @[Misc.scala:38:36, :56:20]
wire [1:0] _state_req_needs_wb_r_T_58 = _state_req_needs_wb_r_T_55 ? 2'h1 : _state_req_needs_wb_r_T_54; // @[Misc.scala:38:63, :56:20]
wire _state_req_needs_wb_r_T_59 = _state_req_needs_wb_r_T_6 == 4'h2; // @[Misc.scala:56:20]
wire _state_req_needs_wb_r_T_60 = ~_state_req_needs_wb_r_T_59 & _state_req_needs_wb_r_T_56; // @[Misc.scala:38:9, :56:20]
wire [2:0] _state_req_needs_wb_r_T_61 = _state_req_needs_wb_r_T_59 ? 3'h3 : _state_req_needs_wb_r_T_57; // @[Misc.scala:38:36, :56:20]
wire [1:0] _state_req_needs_wb_r_T_62 = _state_req_needs_wb_r_T_59 ? 2'h2 : _state_req_needs_wb_r_T_58; // @[Misc.scala:38:63, :56:20]
wire _state_req_needs_wb_r_T_63 = _state_req_needs_wb_r_T_6 == 4'h3; // @[Misc.scala:56:20]
wire state_req_needs_wb_r_1 = _state_req_needs_wb_r_T_63 | _state_req_needs_wb_r_T_60; // @[Misc.scala:38:9, :56:20]
wire [2:0] state_req_needs_wb_r_2 = _state_req_needs_wb_r_T_63 ? 3'h3 : _state_req_needs_wb_r_T_61; // @[Misc.scala:38:36, :56:20]
wire [1:0] state_req_needs_wb_r_3 = _state_req_needs_wb_r_T_63 ? 2'h2 : _state_req_needs_wb_r_T_62; // @[Misc.scala:38:63, :56:20]
wire [1:0] state_req_needs_wb_meta_state = state_req_needs_wb_r_3; // @[Misc.scala:38:63]
wire _state_r_c_cat_T_2 = _state_r_c_cat_T | _state_r_c_cat_T_1; // @[Consts.scala:90:{32,42,49}]
wire _state_r_c_cat_T_4 = _state_r_c_cat_T_2 | _state_r_c_cat_T_3; // @[Consts.scala:90:{42,59,66}]
wire _state_r_c_cat_T_9 = _state_r_c_cat_T_5 | _state_r_c_cat_T_6; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_10 = _state_r_c_cat_T_9 | _state_r_c_cat_T_7; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_11 = _state_r_c_cat_T_10 | _state_r_c_cat_T_8; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_17 = _state_r_c_cat_T_12 | _state_r_c_cat_T_13; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_18 = _state_r_c_cat_T_17 | _state_r_c_cat_T_14; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_19 = _state_r_c_cat_T_18 | _state_r_c_cat_T_15; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_20 = _state_r_c_cat_T_19 | _state_r_c_cat_T_16; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_21 = _state_r_c_cat_T_11 | _state_r_c_cat_T_20; // @[package.scala:81:59]
wire _state_r_c_cat_T_22 = _state_r_c_cat_T_4 | _state_r_c_cat_T_21; // @[Consts.scala:87:44, :90:{59,76}]
wire _state_r_c_cat_T_25 = _state_r_c_cat_T_23 | _state_r_c_cat_T_24; // @[Consts.scala:90:{32,42,49}]
wire _state_r_c_cat_T_27 = _state_r_c_cat_T_25 | _state_r_c_cat_T_26; // @[Consts.scala:90:{42,59,66}]
wire _state_r_c_cat_T_32 = _state_r_c_cat_T_28 | _state_r_c_cat_T_29; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_33 = _state_r_c_cat_T_32 | _state_r_c_cat_T_30; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_34 = _state_r_c_cat_T_33 | _state_r_c_cat_T_31; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_40 = _state_r_c_cat_T_35 | _state_r_c_cat_T_36; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_41 = _state_r_c_cat_T_40 | _state_r_c_cat_T_37; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_42 = _state_r_c_cat_T_41 | _state_r_c_cat_T_38; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_43 = _state_r_c_cat_T_42 | _state_r_c_cat_T_39; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_44 = _state_r_c_cat_T_34 | _state_r_c_cat_T_43; // @[package.scala:81:59]
wire _state_r_c_cat_T_45 = _state_r_c_cat_T_27 | _state_r_c_cat_T_44; // @[Consts.scala:87:44, :90:{59,76}]
wire _state_r_c_cat_T_47 = _state_r_c_cat_T_45 | _state_r_c_cat_T_46; // @[Consts.scala:90:76, :91:{47,54}]
wire _state_r_c_cat_T_49 = _state_r_c_cat_T_47 | _state_r_c_cat_T_48; // @[Consts.scala:91:{47,64,71}]
wire [1:0] state_r_c = {_state_r_c_cat_T_22, _state_r_c_cat_T_49}; // @[Metadata.scala:29:18]
wire [3:0] _state_r_T = {state_r_c, io_req_old_meta_coh_state_0}; // @[Metadata.scala:29:18, :58:19]
wire _state_r_T_25 = _state_r_T == 4'hC; // @[Misc.scala:49:20]
wire [1:0] _state_r_T_27 = {1'h0, _state_r_T_25}; // @[Misc.scala:35:36, :49:20]
wire _state_r_T_28 = _state_r_T == 4'hD; // @[Misc.scala:49:20]
wire [1:0] _state_r_T_30 = _state_r_T_28 ? 2'h2 : _state_r_T_27; // @[Misc.scala:35:36, :49:20]
wire _state_r_T_31 = _state_r_T == 4'h4; // @[Misc.scala:49:20]
wire [1:0] _state_r_T_33 = _state_r_T_31 ? 2'h1 : _state_r_T_30; // @[Misc.scala:35:36, :49:20]
wire _state_r_T_34 = _state_r_T == 4'h5; // @[Misc.scala:49:20]
wire [1:0] _state_r_T_36 = _state_r_T_34 ? 2'h2 : _state_r_T_33; // @[Misc.scala:35:36, :49:20]
wire _state_r_T_37 = _state_r_T == 4'h0; // @[Misc.scala:49:20]
wire [1:0] _state_r_T_39 = _state_r_T_37 ? 2'h0 : _state_r_T_36; // @[Misc.scala:35:36, :49:20]
wire _state_r_T_40 = _state_r_T == 4'hE; // @[Misc.scala:49:20]
wire _state_r_T_41 = _state_r_T_40; // @[Misc.scala:35:9, :49:20]
wire [1:0] _state_r_T_42 = _state_r_T_40 ? 2'h3 : _state_r_T_39; // @[Misc.scala:35:36, :49:20]
wire _state_r_T_43 = &_state_r_T; // @[Misc.scala:49:20]
wire _state_r_T_44 = _state_r_T_43 | _state_r_T_41; // @[Misc.scala:35:9, :49:20]
wire [1:0] _state_r_T_45 = _state_r_T_43 ? 2'h3 : _state_r_T_42; // @[Misc.scala:35:36, :49:20]
wire _state_r_T_46 = _state_r_T == 4'h6; // @[Misc.scala:49:20]
wire _state_r_T_47 = _state_r_T_46 | _state_r_T_44; // @[Misc.scala:35:9, :49:20]
wire [1:0] _state_r_T_48 = _state_r_T_46 ? 2'h2 : _state_r_T_45; // @[Misc.scala:35:36, :49:20]
wire _state_r_T_49 = _state_r_T == 4'h7; // @[Misc.scala:49:20]
wire _state_r_T_50 = _state_r_T_49 | _state_r_T_47; // @[Misc.scala:35:9, :49:20]
wire [1:0] _state_r_T_51 = _state_r_T_49 ? 2'h3 : _state_r_T_48; // @[Misc.scala:35:36, :49:20]
wire _state_r_T_52 = _state_r_T == 4'h1; // @[Misc.scala:49:20]
wire _state_r_T_53 = _state_r_T_52 | _state_r_T_50; // @[Misc.scala:35:9, :49:20]
wire [1:0] _state_r_T_54 = _state_r_T_52 ? 2'h1 : _state_r_T_51; // @[Misc.scala:35:36, :49:20]
wire _state_r_T_55 = _state_r_T == 4'h2; // @[Misc.scala:49:20]
wire _state_r_T_56 = _state_r_T_55 | _state_r_T_53; // @[Misc.scala:35:9, :49:20]
wire [1:0] _state_r_T_57 = _state_r_T_55 ? 2'h2 : _state_r_T_54; // @[Misc.scala:35:36, :49:20]
wire _state_r_T_58 = _state_r_T == 4'h3; // @[Misc.scala:49:20]
wire state_is_hit = _state_r_T_58 | _state_r_T_56; // @[Misc.scala:35:9, :49:20]
wire [1:0] state_r_2 = _state_r_T_58 ? 2'h3 : _state_r_T_57; // @[Misc.scala:35:36, :49:20]
wire [1:0] state_coh_on_hit_state = state_r_2; // @[Misc.scala:35:36]
wire _state_T_5 = _state_T_3 | _state_T_4; // @[Consts.scala:90:{32,42,49}]
wire _state_T_7 = _state_T_5 | _state_T_6; // @[Consts.scala:90:{42,59,66}]
wire _state_T_12 = _state_T_8 | _state_T_9; // @[package.scala:16:47, :81:59]
wire _state_T_13 = _state_T_12 | _state_T_10; // @[package.scala:16:47, :81:59]
wire _state_T_14 = _state_T_13 | _state_T_11; // @[package.scala:16:47, :81:59]
wire _state_T_20 = _state_T_15 | _state_T_16; // @[package.scala:16:47, :81:59]
wire _state_T_21 = _state_T_20 | _state_T_17; // @[package.scala:16:47, :81:59]
wire _state_T_22 = _state_T_21 | _state_T_18; // @[package.scala:16:47, :81:59]
wire _state_T_23 = _state_T_22 | _state_T_19; // @[package.scala:16:47, :81:59]
wire _state_T_24 = _state_T_14 | _state_T_23; // @[package.scala:81:59]
wire _state_T_25 = _state_T_7 | _state_T_24; // @[Consts.scala:87:44, :90:{59,76}]
wire _state_T_27 = ~_state_T_26; // @[mshrs.scala:201:15]
wire _state_T_28 = ~_state_T_25; // @[Consts.scala:90:76]
assign state_new_state = io_req_tag_match_0 & state_is_hit ? 5'hC : 5'h1; // @[Misc.scala:35:9]
assign io_mem_acquire_valid_0 = (|state) & _io_probe_rdy_T_2; // @[package.scala:16:47]
wire [27:0] _GEN_28 = {req_tag, req_idx}; // @[mshrs.scala:110:25, :111:26, :227:28]
wire [27:0] _io_mem_acquire_bits_T; // @[mshrs.scala:227:28]
assign _io_mem_acquire_bits_T = _GEN_28; // @[mshrs.scala:227:28]
wire [27:0] rp_addr_hi; // @[mshrs.scala:261:22]
assign rp_addr_hi = _GEN_28; // @[mshrs.scala:227:28, :261:22]
wire [27:0] hi; // @[mshrs.scala:266:10]
assign hi = _GEN_28; // @[mshrs.scala:227:28, :266:10]
wire [27:0] io_replay_bits_addr_hi; // @[mshrs.scala:353:31]
assign io_replay_bits_addr_hi = _GEN_28; // @[mshrs.scala:227:28, :353:31]
wire [33:0] _io_mem_acquire_bits_T_1 = {_io_mem_acquire_bits_T, 6'h0}; // @[mshrs.scala:227:{28,47}]
wire [33:0] _io_mem_acquire_bits_legal_T_1 = _io_mem_acquire_bits_T_1; // @[Parameters.scala:137:31]
wire [34:0] _io_mem_acquire_bits_legal_T_2 = {1'h0, _io_mem_acquire_bits_legal_T_1}; // @[Parameters.scala:137:{31,41}]
wire [34:0] _io_mem_acquire_bits_legal_T_3 = _io_mem_acquire_bits_legal_T_2 & 35'h80000000; // @[Parameters.scala:137:{41,46}]
wire [34:0] _io_mem_acquire_bits_legal_T_4 = _io_mem_acquire_bits_legal_T_3; // @[Parameters.scala:137:46]
wire _io_mem_acquire_bits_legal_T_5 = _io_mem_acquire_bits_legal_T_4 == 35'h0; // @[Parameters.scala:137:{46,59}]
assign io_mem_acquire_bits_a_address = _io_mem_acquire_bits_T_1[31:0]; // @[Edges.scala:346:17]
wire [33:0] _io_mem_acquire_bits_legal_T_9 = {_io_mem_acquire_bits_T_1[33:32], io_mem_acquire_bits_a_address ^ 32'h80000000}; // @[Edges.scala:346:17]
wire [34:0] _io_mem_acquire_bits_legal_T_10 = {1'h0, _io_mem_acquire_bits_legal_T_9}; // @[Parameters.scala:137:{31,41}]
wire [34:0] _io_mem_acquire_bits_legal_T_11 = _io_mem_acquire_bits_legal_T_10 & 35'h80000000; // @[Parameters.scala:137:{41,46}]
wire [34:0] _io_mem_acquire_bits_legal_T_12 = _io_mem_acquire_bits_legal_T_11; // @[Parameters.scala:137:46]
wire _io_mem_acquire_bits_legal_T_13 = _io_mem_acquire_bits_legal_T_12 == 35'h0; // @[Parameters.scala:137:{46,59}]
wire _io_mem_acquire_bits_legal_T_14 = _io_mem_acquire_bits_legal_T_13; // @[Parameters.scala:684:54]
wire io_mem_acquire_bits_legal = _io_mem_acquire_bits_legal_T_14; // @[Parameters.scala:684:54, :686:26]
assign io_mem_acquire_bits_param_0 = io_mem_acquire_bits_a_param; // @[Edges.scala:346:17]
assign io_mem_acquire_bits_address_0 = io_mem_acquire_bits_a_address; // @[Edges.scala:346:17]
assign io_mem_acquire_bits_a_param = {1'h0, grow_param}; // @[Misc.scala:35:36]
wire io_mem_acquire_bits_a_mask_sub_sub_bit = _io_mem_acquire_bits_T_1[2]; // @[Misc.scala:210:26]
wire io_mem_acquire_bits_a_mask_sub_sub_1_2 = io_mem_acquire_bits_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire io_mem_acquire_bits_a_mask_sub_sub_nbit = ~io_mem_acquire_bits_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20]
wire io_mem_acquire_bits_a_mask_sub_sub_0_2 = io_mem_acquire_bits_a_mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _io_mem_acquire_bits_a_mask_sub_sub_acc_T = io_mem_acquire_bits_a_mask_sub_sub_0_2; // @[Misc.scala:214:27, :215:38]
wire _io_mem_acquire_bits_a_mask_sub_sub_acc_T_1 = io_mem_acquire_bits_a_mask_sub_sub_1_2; // @[Misc.scala:214:27, :215:38]
wire io_mem_acquire_bits_a_mask_sub_bit = _io_mem_acquire_bits_T_1[1]; // @[Misc.scala:210:26]
wire io_mem_acquire_bits_a_mask_sub_nbit = ~io_mem_acquire_bits_a_mask_sub_bit; // @[Misc.scala:210:26, :211:20]
wire io_mem_acquire_bits_a_mask_sub_0_2 = io_mem_acquire_bits_a_mask_sub_sub_0_2 & io_mem_acquire_bits_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire io_mem_acquire_bits_a_mask_sub_1_2 = io_mem_acquire_bits_a_mask_sub_sub_0_2 & io_mem_acquire_bits_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire io_mem_acquire_bits_a_mask_sub_2_2 = io_mem_acquire_bits_a_mask_sub_sub_1_2 & io_mem_acquire_bits_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire io_mem_acquire_bits_a_mask_sub_3_2 = io_mem_acquire_bits_a_mask_sub_sub_1_2 & io_mem_acquire_bits_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire io_mem_acquire_bits_a_mask_bit = _io_mem_acquire_bits_T_1[0]; // @[Misc.scala:210:26]
wire io_mem_acquire_bits_a_mask_nbit = ~io_mem_acquire_bits_a_mask_bit; // @[Misc.scala:210:26, :211:20]
wire io_mem_acquire_bits_a_mask_eq = io_mem_acquire_bits_a_mask_sub_0_2 & io_mem_acquire_bits_a_mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _io_mem_acquire_bits_a_mask_acc_T = io_mem_acquire_bits_a_mask_eq; // @[Misc.scala:214:27, :215:38]
wire io_mem_acquire_bits_a_mask_eq_1 = io_mem_acquire_bits_a_mask_sub_0_2 & io_mem_acquire_bits_a_mask_bit; // @[Misc.scala:210:26, :214:27]
wire _io_mem_acquire_bits_a_mask_acc_T_1 = io_mem_acquire_bits_a_mask_eq_1; // @[Misc.scala:214:27, :215:38]
wire io_mem_acquire_bits_a_mask_eq_2 = io_mem_acquire_bits_a_mask_sub_1_2 & io_mem_acquire_bits_a_mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _io_mem_acquire_bits_a_mask_acc_T_2 = io_mem_acquire_bits_a_mask_eq_2; // @[Misc.scala:214:27, :215:38]
wire io_mem_acquire_bits_a_mask_eq_3 = io_mem_acquire_bits_a_mask_sub_1_2 & io_mem_acquire_bits_a_mask_bit; // @[Misc.scala:210:26, :214:27]
wire _io_mem_acquire_bits_a_mask_acc_T_3 = io_mem_acquire_bits_a_mask_eq_3; // @[Misc.scala:214:27, :215:38]
wire io_mem_acquire_bits_a_mask_eq_4 = io_mem_acquire_bits_a_mask_sub_2_2 & io_mem_acquire_bits_a_mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _io_mem_acquire_bits_a_mask_acc_T_4 = io_mem_acquire_bits_a_mask_eq_4; // @[Misc.scala:214:27, :215:38]
wire io_mem_acquire_bits_a_mask_eq_5 = io_mem_acquire_bits_a_mask_sub_2_2 & io_mem_acquire_bits_a_mask_bit; // @[Misc.scala:210:26, :214:27]
wire _io_mem_acquire_bits_a_mask_acc_T_5 = io_mem_acquire_bits_a_mask_eq_5; // @[Misc.scala:214:27, :215:38]
wire io_mem_acquire_bits_a_mask_eq_6 = io_mem_acquire_bits_a_mask_sub_3_2 & io_mem_acquire_bits_a_mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _io_mem_acquire_bits_a_mask_acc_T_6 = io_mem_acquire_bits_a_mask_eq_6; // @[Misc.scala:214:27, :215:38]
wire io_mem_acquire_bits_a_mask_eq_7 = io_mem_acquire_bits_a_mask_sub_3_2 & io_mem_acquire_bits_a_mask_bit; // @[Misc.scala:210:26, :214:27]
wire _io_mem_acquire_bits_a_mask_acc_T_7 = io_mem_acquire_bits_a_mask_eq_7; // @[Misc.scala:214:27, :215:38]
wire _GEN_29 = ~(|state) | _io_probe_rdy_T_2; // @[package.scala:16:47]
assign io_lb_write_valid_0 = ~_GEN_29 & _io_probe_rdy_T_3 & opdata & io_mem_grant_valid_0; // @[package.scala:16:47]
wire [8:0] _io_lb_write_bits_offset_T = refill_address_inc[11:3]; // @[Edges.scala:269:29]
assign io_lb_write_bits_offset_0 = _io_lb_write_bits_offset_T[2:0]; // @[mshrs.scala:36:7, :238:{31,53}]
assign io_mem_grant_ready_0 = ~_GEN_29 & _io_probe_rdy_T_3 & (~opdata | io_lb_write_ready_0); // @[package.scala:16:47]
wire _grantack_valid_T = io_mem_grant_bits_opcode_0[2]; // @[Edges.scala:71:36]
wire _grantack_valid_T_1 = io_mem_grant_bits_opcode_0[1]; // @[Edges.scala:71:52]
wire _grantack_valid_T_2 = ~_grantack_valid_T_1; // @[Edges.scala:71:{43,52}]
wire _grantack_valid_T_3 = _grantack_valid_T & _grantack_valid_T_2; // @[Edges.scala:71:{36,40,43}]
wire [4:0] _state_T_29 = grant_had_data ? 5'h3 : 5'hC; // @[mshrs.scala:141:27, :250:19]
wire _drain_load_T = _rpq_io_deq_bits_uop_mem_cmd == 5'h0; // @[package.scala:16:47]
wire _drain_load_T_1 = _rpq_io_deq_bits_uop_mem_cmd == 5'h10; // @[package.scala:16:47]
wire _GEN_30 = _rpq_io_deq_bits_uop_mem_cmd == 5'h6; // @[package.scala:16:47]
wire _drain_load_T_2; // @[package.scala:16:47]
assign _drain_load_T_2 = _GEN_30; // @[package.scala:16:47]
wire _r_c_cat_T_48; // @[Consts.scala:91:71]
assign _r_c_cat_T_48 = _GEN_30; // @[package.scala:16:47]
wire _GEN_31 = _rpq_io_deq_bits_uop_mem_cmd == 5'h7; // @[package.scala:16:47]
wire _drain_load_T_3; // @[package.scala:16:47]
assign _drain_load_T_3 = _GEN_31; // @[package.scala:16:47]
wire _drain_load_T_28; // @[Consts.scala:90:66]
assign _drain_load_T_28 = _GEN_31; // @[package.scala:16:47]
wire _drain_load_T_4 = _drain_load_T | _drain_load_T_1; // @[package.scala:16:47, :81:59]
wire _drain_load_T_5 = _drain_load_T_4 | _drain_load_T_2; // @[package.scala:16:47, :81:59]
wire _drain_load_T_6 = _drain_load_T_5 | _drain_load_T_3; // @[package.scala:16:47, :81:59]
wire _GEN_32 = _rpq_io_deq_bits_uop_mem_cmd == 5'h4; // @[package.scala:16:47]
wire _drain_load_T_7; // @[package.scala:16:47]
assign _drain_load_T_7 = _GEN_32; // @[package.scala:16:47]
wire _drain_load_T_30; // @[package.scala:16:47]
assign _drain_load_T_30 = _GEN_32; // @[package.scala:16:47]
wire _GEN_33 = _rpq_io_deq_bits_uop_mem_cmd == 5'h9; // @[package.scala:16:47]
wire _drain_load_T_8; // @[package.scala:16:47]
assign _drain_load_T_8 = _GEN_33; // @[package.scala:16:47]
wire _drain_load_T_31; // @[package.scala:16:47]
assign _drain_load_T_31 = _GEN_33; // @[package.scala:16:47]
wire _GEN_34 = _rpq_io_deq_bits_uop_mem_cmd == 5'hA; // @[package.scala:16:47]
wire _drain_load_T_9; // @[package.scala:16:47]
assign _drain_load_T_9 = _GEN_34; // @[package.scala:16:47]
wire _drain_load_T_32; // @[package.scala:16:47]
assign _drain_load_T_32 = _GEN_34; // @[package.scala:16:47]
wire _GEN_35 = _rpq_io_deq_bits_uop_mem_cmd == 5'hB; // @[package.scala:16:47]
wire _drain_load_T_10; // @[package.scala:16:47]
assign _drain_load_T_10 = _GEN_35; // @[package.scala:16:47]
wire _drain_load_T_33; // @[package.scala:16:47]
assign _drain_load_T_33 = _GEN_35; // @[package.scala:16:47]
wire _drain_load_T_11 = _drain_load_T_7 | _drain_load_T_8; // @[package.scala:16:47, :81:59]
wire _drain_load_T_12 = _drain_load_T_11 | _drain_load_T_9; // @[package.scala:16:47, :81:59]
wire _drain_load_T_13 = _drain_load_T_12 | _drain_load_T_10; // @[package.scala:16:47, :81:59]
wire _GEN_36 = _rpq_io_deq_bits_uop_mem_cmd == 5'h8; // @[package.scala:16:47]
wire _drain_load_T_14; // @[package.scala:16:47]
assign _drain_load_T_14 = _GEN_36; // @[package.scala:16:47]
wire _drain_load_T_37; // @[package.scala:16:47]
assign _drain_load_T_37 = _GEN_36; // @[package.scala:16:47]
wire _GEN_37 = _rpq_io_deq_bits_uop_mem_cmd == 5'hC; // @[package.scala:16:47]
wire _drain_load_T_15; // @[package.scala:16:47]
assign _drain_load_T_15 = _GEN_37; // @[package.scala:16:47]
wire _drain_load_T_38; // @[package.scala:16:47]
assign _drain_load_T_38 = _GEN_37; // @[package.scala:16:47]
wire _GEN_38 = _rpq_io_deq_bits_uop_mem_cmd == 5'hD; // @[package.scala:16:47]
wire _drain_load_T_16; // @[package.scala:16:47]
assign _drain_load_T_16 = _GEN_38; // @[package.scala:16:47]
wire _drain_load_T_39; // @[package.scala:16:47]
assign _drain_load_T_39 = _GEN_38; // @[package.scala:16:47]
wire _GEN_39 = _rpq_io_deq_bits_uop_mem_cmd == 5'hE; // @[package.scala:16:47]
wire _drain_load_T_17; // @[package.scala:16:47]
assign _drain_load_T_17 = _GEN_39; // @[package.scala:16:47]
wire _drain_load_T_40; // @[package.scala:16:47]
assign _drain_load_T_40 = _GEN_39; // @[package.scala:16:47]
wire _GEN_40 = _rpq_io_deq_bits_uop_mem_cmd == 5'hF; // @[package.scala:16:47]
wire _drain_load_T_18; // @[package.scala:16:47]
assign _drain_load_T_18 = _GEN_40; // @[package.scala:16:47]
wire _drain_load_T_41; // @[package.scala:16:47]
assign _drain_load_T_41 = _GEN_40; // @[package.scala:16:47]
wire _drain_load_T_19 = _drain_load_T_14 | _drain_load_T_15; // @[package.scala:16:47, :81:59]
wire _drain_load_T_20 = _drain_load_T_19 | _drain_load_T_16; // @[package.scala:16:47, :81:59]
wire _drain_load_T_21 = _drain_load_T_20 | _drain_load_T_17; // @[package.scala:16:47, :81:59]
wire _drain_load_T_22 = _drain_load_T_21 | _drain_load_T_18; // @[package.scala:16:47, :81:59]
wire _drain_load_T_23 = _drain_load_T_13 | _drain_load_T_22; // @[package.scala:81:59]
wire _drain_load_T_24 = _drain_load_T_6 | _drain_load_T_23; // @[package.scala:81:59]
wire _drain_load_T_25 = _rpq_io_deq_bits_uop_mem_cmd == 5'h1; // @[Consts.scala:90:32]
wire _drain_load_T_26 = _rpq_io_deq_bits_uop_mem_cmd == 5'h11; // @[Consts.scala:90:49]
wire _drain_load_T_27 = _drain_load_T_25 | _drain_load_T_26; // @[Consts.scala:90:{32,42,49}]
wire _drain_load_T_29 = _drain_load_T_27 | _drain_load_T_28; // @[Consts.scala:90:{42,59,66}]
wire _drain_load_T_34 = _drain_load_T_30 | _drain_load_T_31; // @[package.scala:16:47, :81:59]
wire _drain_load_T_35 = _drain_load_T_34 | _drain_load_T_32; // @[package.scala:16:47, :81:59]
wire _drain_load_T_36 = _drain_load_T_35 | _drain_load_T_33; // @[package.scala:16:47, :81:59]
wire _drain_load_T_42 = _drain_load_T_37 | _drain_load_T_38; // @[package.scala:16:47, :81:59]
wire _drain_load_T_43 = _drain_load_T_42 | _drain_load_T_39; // @[package.scala:16:47, :81:59]
wire _drain_load_T_44 = _drain_load_T_43 | _drain_load_T_40; // @[package.scala:16:47, :81:59]
wire _drain_load_T_45 = _drain_load_T_44 | _drain_load_T_41; // @[package.scala:16:47, :81:59]
wire _drain_load_T_46 = _drain_load_T_36 | _drain_load_T_45; // @[package.scala:81:59]
wire _drain_load_T_47 = _drain_load_T_29 | _drain_load_T_46; // @[Consts.scala:87:44, :90:{59,76}]
wire _drain_load_T_48 = ~_drain_load_T_47; // @[Consts.scala:90:76]
wire _drain_load_T_49 = _drain_load_T_24 & _drain_load_T_48; // @[Consts.scala:89:68]
wire _drain_load_T_50 = _rpq_io_deq_bits_uop_mem_cmd != 5'h6; // @[mshrs.scala:128:19, :259:51]
wire drain_load = _drain_load_T_49 & _drain_load_T_50; // @[mshrs.scala:257:59, :258:60, :259:51]
wire [5:0] _rp_addr_T = _rpq_io_deq_bits_addr[5:0]; // @[mshrs.scala:128:19, :261:61]
wire [33:0] rp_addr = {rp_addr_hi, _rp_addr_T}; // @[mshrs.scala:261:{22,61}]
wire [1:0] size; // @[AMOALU.scala:11:18]
wire _rpq_io_deq_ready_T = io_resp_ready_0 & io_lb_read_ready_0; // @[mshrs.scala:36:7, :270:45]
wire _rpq_io_deq_ready_T_1 = _rpq_io_deq_ready_T & drain_load; // @[mshrs.scala:258:60, :270:{45,65}]
wire _io_lb_read_valid_T = _rpq_io_deq_valid & drain_load; // @[mshrs.scala:128:19, :258:60, :271:48]
wire [30:0] _io_lb_read_bits_offset_T = _rpq_io_deq_bits_addr[33:3]; // @[mshrs.scala:128:19, :273:52]
wire _GEN_41 = io_lb_read_ready_0 & io_lb_read_valid_0; // @[Decoupled.scala:51:35]
wire _io_resp_valid_T; // @[Decoupled.scala:51:35]
assign _io_resp_valid_T = _GEN_41; // @[Decoupled.scala:51:35]
wire _io_refill_valid_T; // @[Decoupled.scala:51:35]
assign _io_refill_valid_T = _GEN_41; // @[Decoupled.scala:51:35]
wire _io_resp_valid_T_1 = _rpq_io_deq_valid & _io_resp_valid_T; // @[Decoupled.scala:51:35]
wire _io_resp_valid_T_2 = _io_resp_valid_T_1 & drain_load; // @[mshrs.scala:258:60, :275:{43,62}]
wire _GEN_42 = ~(|state) | _io_probe_rdy_T_2 | _io_probe_rdy_T_3; // @[package.scala:16:47]
assign io_resp_valid_0 = ~_GEN_42 & _io_probe_rdy_T_4 & _io_resp_valid_T_2; // @[package.scala:16:47]
wire _io_resp_bits_data_shifted_T = _rpq_io_deq_bits_addr[2]; // @[AMOALU.scala:42:29]
wire [31:0] _io_resp_bits_data_shifted_T_1 = data_word[63:32]; // @[AMOALU.scala:42:37]
wire [31:0] _io_resp_bits_data_T_5 = data_word[63:32]; // @[AMOALU.scala:42:37, :45:94]
wire [31:0] _io_resp_bits_data_shifted_T_2 = data_word[31:0]; // @[AMOALU.scala:42:55]
wire [31:0] io_resp_bits_data_shifted = _io_resp_bits_data_shifted_T ? _io_resp_bits_data_shifted_T_1 : _io_resp_bits_data_shifted_T_2; // @[AMOALU.scala:42:{24,29,37,55}]
wire [31:0] io_resp_bits_data_zeroed = io_resp_bits_data_shifted; // @[AMOALU.scala:42:24, :44:23]
wire _io_resp_bits_data_T = size == 2'h2; // @[AMOALU.scala:11:18, :45:26]
wire _io_resp_bits_data_T_1 = _io_resp_bits_data_T; // @[AMOALU.scala:45:{26,34}]
wire _io_resp_bits_data_T_2 = io_resp_bits_data_zeroed[31]; // @[AMOALU.scala:44:23, :45:81]
wire _io_resp_bits_data_T_3 = _rpq_io_deq_bits_uop_mem_signed & _io_resp_bits_data_T_2; // @[AMOALU.scala:45:{72,81}]
wire [31:0] _io_resp_bits_data_T_4 = {32{_io_resp_bits_data_T_3}}; // @[AMOALU.scala:45:{49,72}]
wire [31:0] _io_resp_bits_data_T_6 = _io_resp_bits_data_T_1 ? _io_resp_bits_data_T_4 : _io_resp_bits_data_T_5; // @[AMOALU.scala:45:{20,34,49,94}]
wire [63:0] _io_resp_bits_data_T_7 = {_io_resp_bits_data_T_6, io_resp_bits_data_zeroed}; // @[AMOALU.scala:44:23, :45:{16,20}]
wire _io_resp_bits_data_shifted_T_3 = _rpq_io_deq_bits_addr[1]; // @[AMOALU.scala:42:29]
wire [15:0] _io_resp_bits_data_shifted_T_4 = _io_resp_bits_data_T_7[31:16]; // @[AMOALU.scala:42:37, :45:16]
wire [15:0] _io_resp_bits_data_shifted_T_5 = _io_resp_bits_data_T_7[15:0]; // @[AMOALU.scala:42:55, :45:16]
wire [15:0] io_resp_bits_data_shifted_1 = _io_resp_bits_data_shifted_T_3 ? _io_resp_bits_data_shifted_T_4 : _io_resp_bits_data_shifted_T_5; // @[AMOALU.scala:42:{24,29,37,55}]
wire [15:0] io_resp_bits_data_zeroed_1 = io_resp_bits_data_shifted_1; // @[AMOALU.scala:42:24, :44:23]
wire _io_resp_bits_data_T_8 = size == 2'h1; // @[AMOALU.scala:11:18, :45:26]
wire _io_resp_bits_data_T_9 = _io_resp_bits_data_T_8; // @[AMOALU.scala:45:{26,34}]
wire _io_resp_bits_data_T_10 = io_resp_bits_data_zeroed_1[15]; // @[AMOALU.scala:44:23, :45:81]
wire _io_resp_bits_data_T_11 = _rpq_io_deq_bits_uop_mem_signed & _io_resp_bits_data_T_10; // @[AMOALU.scala:45:{72,81}]
wire [47:0] _io_resp_bits_data_T_12 = {48{_io_resp_bits_data_T_11}}; // @[AMOALU.scala:45:{49,72}]
wire [47:0] _io_resp_bits_data_T_13 = _io_resp_bits_data_T_7[63:16]; // @[AMOALU.scala:45:{16,94}]
wire [47:0] _io_resp_bits_data_T_14 = _io_resp_bits_data_T_9 ? _io_resp_bits_data_T_12 : _io_resp_bits_data_T_13; // @[AMOALU.scala:45:{20,34,49,94}]
wire [63:0] _io_resp_bits_data_T_15 = {_io_resp_bits_data_T_14, io_resp_bits_data_zeroed_1}; // @[AMOALU.scala:44:23, :45:{16,20}]
wire _io_resp_bits_data_shifted_T_6 = _rpq_io_deq_bits_addr[0]; // @[AMOALU.scala:42:29]
wire [7:0] _io_resp_bits_data_shifted_T_7 = _io_resp_bits_data_T_15[15:8]; // @[AMOALU.scala:42:37, :45:16]
wire [7:0] _io_resp_bits_data_shifted_T_8 = _io_resp_bits_data_T_15[7:0]; // @[AMOALU.scala:42:55, :45:16]
wire [7:0] io_resp_bits_data_shifted_2 = _io_resp_bits_data_shifted_T_6 ? _io_resp_bits_data_shifted_T_7 : _io_resp_bits_data_shifted_T_8; // @[AMOALU.scala:42:{24,29,37,55}]
wire [7:0] io_resp_bits_data_zeroed_2 = io_resp_bits_data_shifted_2; // @[AMOALU.scala:42:24, :44:23]
wire _io_resp_bits_data_T_16 = size == 2'h0; // @[AMOALU.scala:11:18, :45:26]
wire _io_resp_bits_data_T_17 = _io_resp_bits_data_T_16; // @[AMOALU.scala:45:{26,34}]
wire _io_resp_bits_data_T_18 = io_resp_bits_data_zeroed_2[7]; // @[AMOALU.scala:44:23, :45:81]
wire _io_resp_bits_data_T_19 = _rpq_io_deq_bits_uop_mem_signed & _io_resp_bits_data_T_18; // @[AMOALU.scala:45:{72,81}]
wire [55:0] _io_resp_bits_data_T_20 = {56{_io_resp_bits_data_T_19}}; // @[AMOALU.scala:45:{49,72}]
wire [55:0] _io_resp_bits_data_T_21 = _io_resp_bits_data_T_15[63:8]; // @[AMOALU.scala:45:{16,94}]
wire [55:0] _io_resp_bits_data_T_22 = _io_resp_bits_data_T_17 ? _io_resp_bits_data_T_20 : _io_resp_bits_data_T_21; // @[AMOALU.scala:45:{20,34,49,94}]
assign _io_resp_bits_data_T_23 = {_io_resp_bits_data_T_22, io_resp_bits_data_zeroed_2}; // @[AMOALU.scala:44:23, :45:{16,20}]
assign io_resp_bits_data_0 = _io_resp_bits_data_T_23; // @[AMOALU.scala:45:16]
wire _T_26 = rpq_io_deq_ready & _rpq_io_deq_valid; // @[Decoupled.scala:51:35]
wire _T_28 = _rpq_io_empty & ~commit_line; // @[mshrs.scala:128:19, :140:24, :282:{31,34}]
wire _T_33 = _rpq_io_empty | _rpq_io_deq_valid & ~drain_load; // @[mshrs.scala:128:19, :258:60, :288:{31,52,55}]
assign io_commit_val_0 = ~_GEN_42 & _io_probe_rdy_T_4 & ~(_T_26 | _T_28) & _T_33; // @[Decoupled.scala:51:35]
wire _io_meta_read_valid_T = ~io_prober_state_valid_0; // @[mshrs.scala:36:7, :295:27]
wire _io_meta_read_valid_T_1 = ~grantack_valid; // @[mshrs.scala:138:21, :295:53]
wire _io_meta_read_valid_T_2 = _io_meta_read_valid_T | _io_meta_read_valid_T_1; // @[mshrs.scala:295:{27,50,53}]
wire [3:0] _io_meta_read_valid_T_3 = io_prober_state_bits_0[9:6]; // @[mshrs.scala:36:7, :295:93]
wire _io_meta_read_valid_T_4 = _io_meta_read_valid_T_3 != req_idx; // @[mshrs.scala:110:25, :295:{93,120}]
wire _io_meta_read_valid_T_5 = _io_meta_read_valid_T_2 | _io_meta_read_valid_T_4; // @[mshrs.scala:295:{50,69,120}]
assign io_meta_read_valid_0 = ~(~(|state) | _io_probe_rdy_T_2 | _io_probe_rdy_T_3 | _io_probe_rdy_T_4) & _io_probe_rdy_T_8 & _io_meta_read_valid_T_5; // @[package.scala:16:47]
assign io_meta_write_bits_data_tag_0 = req_tag[21:0]; // @[mshrs.scala:36:7, :111:26, :297:27]
assign io_meta_read_bits_tag_0 = req_tag[21:0]; // @[mshrs.scala:36:7, :111:26, :297:27]
wire _T_36 = state == 5'h5; // @[mshrs.scala:107:22, :302:22]
wire _T_37 = state == 5'h6; // @[mshrs.scala:107:22, :304:22]
wire [3:0] _needs_wb_r_T_6 = {2'h2, io_meta_resp_bits_coh_state_0}; // @[Metadata.scala:120:19]
wire _needs_wb_r_T_19 = _needs_wb_r_T_6 == 4'h8; // @[Misc.scala:56:20]
wire [2:0] _needs_wb_r_T_21 = _needs_wb_r_T_19 ? 3'h5 : 3'h0; // @[Misc.scala:38:36, :56:20]
wire _needs_wb_r_T_23 = _needs_wb_r_T_6 == 4'h9; // @[Misc.scala:56:20]
wire [2:0] _needs_wb_r_T_25 = _needs_wb_r_T_23 ? 3'h2 : _needs_wb_r_T_21; // @[Misc.scala:38:36, :56:20]
wire _needs_wb_r_T_27 = _needs_wb_r_T_6 == 4'hA; // @[Misc.scala:56:20]
wire [2:0] _needs_wb_r_T_29 = _needs_wb_r_T_27 ? 3'h1 : _needs_wb_r_T_25; // @[Misc.scala:38:36, :56:20]
wire _needs_wb_r_T_31 = _needs_wb_r_T_6 == 4'hB; // @[Misc.scala:56:20]
wire _needs_wb_r_T_32 = _needs_wb_r_T_31; // @[Misc.scala:38:9, :56:20]
wire [2:0] _needs_wb_r_T_33 = _needs_wb_r_T_31 ? 3'h1 : _needs_wb_r_T_29; // @[Misc.scala:38:36, :56:20]
wire _needs_wb_r_T_35 = _needs_wb_r_T_6 == 4'h4; // @[Misc.scala:56:20]
wire _needs_wb_r_T_36 = ~_needs_wb_r_T_35 & _needs_wb_r_T_32; // @[Misc.scala:38:9, :56:20]
wire [2:0] _needs_wb_r_T_37 = _needs_wb_r_T_35 ? 3'h5 : _needs_wb_r_T_33; // @[Misc.scala:38:36, :56:20]
wire _needs_wb_r_T_39 = _needs_wb_r_T_6 == 4'h5; // @[Misc.scala:56:20]
wire _needs_wb_r_T_40 = ~_needs_wb_r_T_39 & _needs_wb_r_T_36; // @[Misc.scala:38:9, :56:20]
wire [2:0] _needs_wb_r_T_41 = _needs_wb_r_T_39 ? 3'h4 : _needs_wb_r_T_37; // @[Misc.scala:38:36, :56:20]
wire [1:0] _needs_wb_r_T_42 = {1'h0, _needs_wb_r_T_39}; // @[Misc.scala:38:63, :56:20]
wire _needs_wb_r_T_43 = _needs_wb_r_T_6 == 4'h6; // @[Misc.scala:56:20]
wire _needs_wb_r_T_44 = ~_needs_wb_r_T_43 & _needs_wb_r_T_40; // @[Misc.scala:38:9, :56:20]
wire [2:0] _needs_wb_r_T_45 = _needs_wb_r_T_43 ? 3'h0 : _needs_wb_r_T_41; // @[Misc.scala:38:36, :56:20]
wire [1:0] _needs_wb_r_T_46 = _needs_wb_r_T_43 ? 2'h1 : _needs_wb_r_T_42; // @[Misc.scala:38:63, :56:20]
wire _needs_wb_r_T_47 = _needs_wb_r_T_6 == 4'h7; // @[Misc.scala:56:20]
wire _needs_wb_r_T_48 = _needs_wb_r_T_47 | _needs_wb_r_T_44; // @[Misc.scala:38:9, :56:20]
wire [2:0] _needs_wb_r_T_49 = _needs_wb_r_T_47 ? 3'h0 : _needs_wb_r_T_45; // @[Misc.scala:38:36, :56:20]
wire [1:0] _needs_wb_r_T_50 = _needs_wb_r_T_47 ? 2'h1 : _needs_wb_r_T_46; // @[Misc.scala:38:63, :56:20]
wire _needs_wb_r_T_51 = _needs_wb_r_T_6 == 4'h0; // @[Misc.scala:56:20]
wire _needs_wb_r_T_52 = ~_needs_wb_r_T_51 & _needs_wb_r_T_48; // @[Misc.scala:38:9, :56:20]
wire [2:0] _needs_wb_r_T_53 = _needs_wb_r_T_51 ? 3'h5 : _needs_wb_r_T_49; // @[Misc.scala:38:36, :56:20]
wire [1:0] _needs_wb_r_T_54 = _needs_wb_r_T_51 ? 2'h0 : _needs_wb_r_T_50; // @[Misc.scala:38:63, :56:20]
wire _needs_wb_r_T_55 = _needs_wb_r_T_6 == 4'h1; // @[Misc.scala:56:20]
wire _needs_wb_r_T_56 = ~_needs_wb_r_T_55 & _needs_wb_r_T_52; // @[Misc.scala:38:9, :56:20]
wire [2:0] _needs_wb_r_T_57 = _needs_wb_r_T_55 ? 3'h4 : _needs_wb_r_T_53; // @[Misc.scala:38:36, :56:20]
wire [1:0] _needs_wb_r_T_58 = _needs_wb_r_T_55 ? 2'h1 : _needs_wb_r_T_54; // @[Misc.scala:38:63, :56:20]
wire _needs_wb_r_T_59 = _needs_wb_r_T_6 == 4'h2; // @[Misc.scala:56:20]
wire _needs_wb_r_T_60 = ~_needs_wb_r_T_59 & _needs_wb_r_T_56; // @[Misc.scala:38:9, :56:20]
wire [2:0] _needs_wb_r_T_61 = _needs_wb_r_T_59 ? 3'h3 : _needs_wb_r_T_57; // @[Misc.scala:38:36, :56:20]
wire [1:0] _needs_wb_r_T_62 = _needs_wb_r_T_59 ? 2'h2 : _needs_wb_r_T_58; // @[Misc.scala:38:63, :56:20]
wire _needs_wb_r_T_63 = _needs_wb_r_T_6 == 4'h3; // @[Misc.scala:56:20]
wire needs_wb = _needs_wb_r_T_63 | _needs_wb_r_T_60; // @[Misc.scala:38:9, :56:20]
wire [2:0] needs_wb_r_2 = _needs_wb_r_T_63 ? 3'h3 : _needs_wb_r_T_61; // @[Misc.scala:38:36, :56:20]
wire [1:0] needs_wb_r_3 = _needs_wb_r_T_63 ? 2'h2 : _needs_wb_r_T_62; // @[Misc.scala:38:63, :56:20]
wire [1:0] needs_wb_meta_state = needs_wb_r_3; // @[Misc.scala:38:63]
wire _state_T_30 = ~io_meta_resp_valid_0; // @[mshrs.scala:36:7, :306:18]
wire [4:0] _state_T_31 = needs_wb ? 5'h7 : 5'hB; // @[Misc.scala:38:9]
wire [4:0] _state_T_32 = _state_T_30 ? 5'h4 : _state_T_31; // @[mshrs.scala:306:{17,18}, :307:17]
wire _T_38 = state == 5'h7; // @[mshrs.scala:107:22, :308:22]
wire _T_40 = state == 5'h9; // @[mshrs.scala:107:22, :318:22]
assign io_wb_req_valid_0 = ~(~(|state) | _io_probe_rdy_T_2 | _io_probe_rdy_T_3 | _io_probe_rdy_T_4 | _io_probe_rdy_T_8 | _T_36 | _T_37 | _T_38) & _T_40; // @[package.scala:16:47]
wire _T_42 = state == 5'hA; // @[mshrs.scala:107:22, :330:22]
wire _T_43 = state == 5'hB; // @[mshrs.scala:107:22, :334:22]
wire _GEN_43 = _io_probe_rdy_T_8 | _T_36 | _T_37 | _T_38 | _T_40 | _T_42; // @[mshrs.scala:148:129, :179:26, :294:39, :302:{22,41}, :304:{22,41}, :308:{22,40}, :318:{22,36}, :330:{22,37}, :334:41]
assign io_lb_read_valid_0 = ~_GEN_42 & (_io_probe_rdy_T_4 ? _io_lb_read_valid_T : ~_GEN_43 & _T_43); // @[package.scala:16:47]
assign io_lb_read_bits_offset_0 = _io_probe_rdy_T_4 ? _io_lb_read_bits_offset_T[2:0] : refill_ctr; // @[package.scala:16:47]
wire _GEN_44 = _io_probe_rdy_T_2 | _io_probe_rdy_T_3 | _io_probe_rdy_T_4 | _GEN_43; // @[package.scala:16:47]
assign io_refill_valid_0 = ~(~(|state) | _GEN_44) & _T_43 & _io_refill_valid_T; // @[Decoupled.scala:51:35]
wire [5:0] _io_refill_bits_addr_T = {refill_ctr, 3'h0}; // @[mshrs.scala:139:24, :340:59]
wire [33:0] _io_refill_bits_addr_T_1 = {req_block_addr[33:6], req_block_addr[5:0] | _io_refill_bits_addr_T}; // @[mshrs.scala:112:51, :340:{45,59}]
assign io_refill_bits_addr_0 = _io_refill_bits_addr_T_1[9:0]; // @[mshrs.scala:36:7, :340:{27,45}]
wire [3:0] _refill_ctr_T = {1'h0, refill_ctr} + 4'h1; // @[mshrs.scala:139:24, :345:32]
wire [2:0] _refill_ctr_T_1 = _refill_ctr_T[2:0]; // @[mshrs.scala:345:32]
wire _T_46 = state == 5'hC; // @[mshrs.scala:107:22, :350:22]
wire _GEN_45 = _io_probe_rdy_T_8 | _T_36 | _T_37 | _T_38 | _T_40 | _T_42 | _T_43; // @[mshrs.scala:148:129, :164:26, :294:39, :302:{22,41}, :304:{22,41}, :308:{22,40}, :318:{22,36}, :330:{22,37}, :334:{22,41}, :350:39]
wire _GEN_46 = _io_probe_rdy_T_4 | _GEN_45; // @[package.scala:16:47]
assign io_replay_valid_0 = ~(~(|state) | _io_probe_rdy_T_2 | _io_probe_rdy_T_3 | _GEN_46) & _T_46 & _rpq_io_deq_valid; // @[package.scala:16:47]
assign rpq_io_deq_ready = ~_GEN_42 & (_io_probe_rdy_T_4 ? _rpq_io_deq_ready_T_1 : ~_GEN_45 & _T_46 & io_replay_ready_0); // @[package.scala:16:47]
wire [5:0] _io_replay_bits_addr_T = _rpq_io_deq_bits_addr[5:0]; // @[mshrs.scala:128:19, :353:70]
assign _io_replay_bits_addr_T_1 = {io_replay_bits_addr_hi, _io_replay_bits_addr_T}; // @[mshrs.scala:353:{31,70}]
assign io_replay_bits_addr_0 = _io_replay_bits_addr_T_1; // @[mshrs.scala:36:7, :353:31]
wire _T_48 = _rpq_io_deq_bits_uop_mem_cmd == 5'h1; // @[Consts.scala:90:32]
wire _r_c_cat_T; // @[Consts.scala:90:32]
assign _r_c_cat_T = _T_48; // @[Consts.scala:90:32]
wire _r_c_cat_T_23; // @[Consts.scala:90:32]
assign _r_c_cat_T_23 = _T_48; // @[Consts.scala:90:32]
wire _T_49 = _rpq_io_deq_bits_uop_mem_cmd == 5'h11; // @[Consts.scala:90:49]
wire _r_c_cat_T_1; // @[Consts.scala:90:49]
assign _r_c_cat_T_1 = _T_49; // @[Consts.scala:90:49]
wire _r_c_cat_T_24; // @[Consts.scala:90:49]
assign _r_c_cat_T_24 = _T_49; // @[Consts.scala:90:49]
wire _T_51 = _rpq_io_deq_bits_uop_mem_cmd == 5'h7; // @[Consts.scala:90:66]
wire _r_c_cat_T_3; // @[Consts.scala:90:66]
assign _r_c_cat_T_3 = _T_51; // @[Consts.scala:90:66]
wire _r_c_cat_T_26; // @[Consts.scala:90:66]
assign _r_c_cat_T_26 = _T_51; // @[Consts.scala:90:66]
wire _T_53 = _rpq_io_deq_bits_uop_mem_cmd == 5'h4; // @[package.scala:16:47]
wire _r_c_cat_T_5; // @[package.scala:16:47]
assign _r_c_cat_T_5 = _T_53; // @[package.scala:16:47]
wire _r_c_cat_T_28; // @[package.scala:16:47]
assign _r_c_cat_T_28 = _T_53; // @[package.scala:16:47]
wire _T_54 = _rpq_io_deq_bits_uop_mem_cmd == 5'h9; // @[package.scala:16:47]
wire _r_c_cat_T_6; // @[package.scala:16:47]
assign _r_c_cat_T_6 = _T_54; // @[package.scala:16:47]
wire _r_c_cat_T_29; // @[package.scala:16:47]
assign _r_c_cat_T_29 = _T_54; // @[package.scala:16:47]
wire _T_55 = _rpq_io_deq_bits_uop_mem_cmd == 5'hA; // @[package.scala:16:47]
wire _r_c_cat_T_7; // @[package.scala:16:47]
assign _r_c_cat_T_7 = _T_55; // @[package.scala:16:47]
wire _r_c_cat_T_30; // @[package.scala:16:47]
assign _r_c_cat_T_30 = _T_55; // @[package.scala:16:47]
wire _T_56 = _rpq_io_deq_bits_uop_mem_cmd == 5'hB; // @[package.scala:16:47]
wire _r_c_cat_T_8; // @[package.scala:16:47]
assign _r_c_cat_T_8 = _T_56; // @[package.scala:16:47]
wire _r_c_cat_T_31; // @[package.scala:16:47]
assign _r_c_cat_T_31 = _T_56; // @[package.scala:16:47]
wire _T_60 = _rpq_io_deq_bits_uop_mem_cmd == 5'h8; // @[package.scala:16:47]
wire _r_c_cat_T_12; // @[package.scala:16:47]
assign _r_c_cat_T_12 = _T_60; // @[package.scala:16:47]
wire _r_c_cat_T_35; // @[package.scala:16:47]
assign _r_c_cat_T_35 = _T_60; // @[package.scala:16:47]
wire _T_61 = _rpq_io_deq_bits_uop_mem_cmd == 5'hC; // @[package.scala:16:47]
wire _r_c_cat_T_13; // @[package.scala:16:47]
assign _r_c_cat_T_13 = _T_61; // @[package.scala:16:47]
wire _r_c_cat_T_36; // @[package.scala:16:47]
assign _r_c_cat_T_36 = _T_61; // @[package.scala:16:47]
wire _T_62 = _rpq_io_deq_bits_uop_mem_cmd == 5'hD; // @[package.scala:16:47]
wire _r_c_cat_T_14; // @[package.scala:16:47]
assign _r_c_cat_T_14 = _T_62; // @[package.scala:16:47]
wire _r_c_cat_T_37; // @[package.scala:16:47]
assign _r_c_cat_T_37 = _T_62; // @[package.scala:16:47]
wire _T_63 = _rpq_io_deq_bits_uop_mem_cmd == 5'hE; // @[package.scala:16:47]
wire _r_c_cat_T_15; // @[package.scala:16:47]
assign _r_c_cat_T_15 = _T_63; // @[package.scala:16:47]
wire _r_c_cat_T_38; // @[package.scala:16:47]
assign _r_c_cat_T_38 = _T_63; // @[package.scala:16:47]
wire _T_64 = _rpq_io_deq_bits_uop_mem_cmd == 5'hF; // @[package.scala:16:47]
wire _r_c_cat_T_16; // @[package.scala:16:47]
assign _r_c_cat_T_16 = _T_64; // @[package.scala:16:47]
wire _r_c_cat_T_39; // @[package.scala:16:47]
assign _r_c_cat_T_39 = _T_64; // @[package.scala:16:47]
wire _T_71 = io_replay_ready_0 & io_replay_valid_0 & (_T_48 | _T_49 | _T_51 | _T_53 | _T_54 | _T_55 | _T_56 | _T_60 | _T_61 | _T_62 | _T_63 | _T_64); // @[Decoupled.scala:51:35]
wire _r_c_cat_T_2 = _r_c_cat_T | _r_c_cat_T_1; // @[Consts.scala:90:{32,42,49}]
wire _r_c_cat_T_4 = _r_c_cat_T_2 | _r_c_cat_T_3; // @[Consts.scala:90:{42,59,66}]
wire _r_c_cat_T_9 = _r_c_cat_T_5 | _r_c_cat_T_6; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_10 = _r_c_cat_T_9 | _r_c_cat_T_7; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_11 = _r_c_cat_T_10 | _r_c_cat_T_8; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_17 = _r_c_cat_T_12 | _r_c_cat_T_13; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_18 = _r_c_cat_T_17 | _r_c_cat_T_14; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_19 = _r_c_cat_T_18 | _r_c_cat_T_15; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_20 = _r_c_cat_T_19 | _r_c_cat_T_16; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_21 = _r_c_cat_T_11 | _r_c_cat_T_20; // @[package.scala:81:59]
wire _r_c_cat_T_22 = _r_c_cat_T_4 | _r_c_cat_T_21; // @[Consts.scala:87:44, :90:{59,76}]
wire _r_c_cat_T_25 = _r_c_cat_T_23 | _r_c_cat_T_24; // @[Consts.scala:90:{32,42,49}]
wire _r_c_cat_T_27 = _r_c_cat_T_25 | _r_c_cat_T_26; // @[Consts.scala:90:{42,59,66}]
wire _r_c_cat_T_32 = _r_c_cat_T_28 | _r_c_cat_T_29; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_33 = _r_c_cat_T_32 | _r_c_cat_T_30; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_34 = _r_c_cat_T_33 | _r_c_cat_T_31; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_40 = _r_c_cat_T_35 | _r_c_cat_T_36; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_41 = _r_c_cat_T_40 | _r_c_cat_T_37; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_42 = _r_c_cat_T_41 | _r_c_cat_T_38; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_43 = _r_c_cat_T_42 | _r_c_cat_T_39; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_44 = _r_c_cat_T_34 | _r_c_cat_T_43; // @[package.scala:81:59]
wire _r_c_cat_T_45 = _r_c_cat_T_27 | _r_c_cat_T_44; // @[Consts.scala:87:44, :90:{59,76}]
wire _r_c_cat_T_46 = _rpq_io_deq_bits_uop_mem_cmd == 5'h3; // @[Consts.scala:91:54]
wire _r_c_cat_T_47 = _r_c_cat_T_45 | _r_c_cat_T_46; // @[Consts.scala:90:76, :91:{47,54}]
wire _r_c_cat_T_49 = _r_c_cat_T_47 | _r_c_cat_T_48; // @[Consts.scala:91:{47,64,71}]
wire [1:0] r_c = {_r_c_cat_T_22, _r_c_cat_T_49}; // @[Metadata.scala:29:18]
wire [3:0] _r_T_64 = {r_c, new_coh_state}; // @[Metadata.scala:29:18, :58:19]
wire _r_T_89 = _r_T_64 == 4'hC; // @[Misc.scala:49:20]
wire [1:0] _r_T_91 = {1'h0, _r_T_89}; // @[Misc.scala:35:36, :49:20]
wire _r_T_92 = _r_T_64 == 4'hD; // @[Misc.scala:49:20]
wire [1:0] _r_T_94 = _r_T_92 ? 2'h2 : _r_T_91; // @[Misc.scala:35:36, :49:20]
wire _r_T_95 = _r_T_64 == 4'h4; // @[Misc.scala:49:20]
wire [1:0] _r_T_97 = _r_T_95 ? 2'h1 : _r_T_94; // @[Misc.scala:35:36, :49:20]
wire _r_T_98 = _r_T_64 == 4'h5; // @[Misc.scala:49:20]
wire [1:0] _r_T_100 = _r_T_98 ? 2'h2 : _r_T_97; // @[Misc.scala:35:36, :49:20]
wire _r_T_101 = _r_T_64 == 4'h0; // @[Misc.scala:49:20]
wire [1:0] _r_T_103 = _r_T_101 ? 2'h0 : _r_T_100; // @[Misc.scala:35:36, :49:20]
wire _r_T_104 = _r_T_64 == 4'hE; // @[Misc.scala:49:20]
wire _r_T_105 = _r_T_104; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r_T_106 = _r_T_104 ? 2'h3 : _r_T_103; // @[Misc.scala:35:36, :49:20]
wire _r_T_107 = &_r_T_64; // @[Misc.scala:49:20]
wire _r_T_108 = _r_T_107 | _r_T_105; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r_T_109 = _r_T_107 ? 2'h3 : _r_T_106; // @[Misc.scala:35:36, :49:20]
wire _r_T_110 = _r_T_64 == 4'h6; // @[Misc.scala:49:20]
wire _r_T_111 = _r_T_110 | _r_T_108; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r_T_112 = _r_T_110 ? 2'h2 : _r_T_109; // @[Misc.scala:35:36, :49:20]
wire _r_T_113 = _r_T_64 == 4'h7; // @[Misc.scala:49:20]
wire _r_T_114 = _r_T_113 | _r_T_111; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r_T_115 = _r_T_113 ? 2'h3 : _r_T_112; // @[Misc.scala:35:36, :49:20]
wire _r_T_116 = _r_T_64 == 4'h1; // @[Misc.scala:49:20]
wire _r_T_117 = _r_T_116 | _r_T_114; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r_T_118 = _r_T_116 ? 2'h1 : _r_T_115; // @[Misc.scala:35:36, :49:20]
wire _r_T_119 = _r_T_64 == 4'h2; // @[Misc.scala:49:20]
wire _r_T_120 = _r_T_119 | _r_T_117; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r_T_121 = _r_T_119 ? 2'h2 : _r_T_118; // @[Misc.scala:35:36, :49:20]
wire _r_T_122 = _r_T_64 == 4'h3; // @[Misc.scala:49:20]
wire is_hit = _r_T_122 | _r_T_120; // @[Misc.scala:35:9, :49:20]
wire [1:0] r_2_1 = _r_T_122 ? 2'h3 : _r_T_121; // @[Misc.scala:35:36, :49:20]
wire [1:0] coh_on_hit_state = r_2_1; // @[Misc.scala:35:36]
wire _GEN_47 = _T_40 | _T_42 | _T_43 | _T_46; // @[mshrs.scala:156:26, :318:{22,36}, :330:{22,37}, :334:{22,41}, :350:{22,39}, :363:44]
assign io_meta_write_valid_0 = ~(~(|state) | _io_probe_rdy_T_2 | _io_probe_rdy_T_3 | _io_probe_rdy_T_4 | _io_probe_rdy_T_8 | _T_36 | _T_37) & (_T_38 | ~_GEN_47 & _sec_rdy_T_4); // @[package.scala:16:47]
assign io_meta_write_bits_data_coh_state_0 = _T_38 ? coh_on_clear_state : new_coh_state; // @[Metadata.scala:160:20]
wire _GEN_48 = _io_probe_rdy_T_4 | _io_probe_rdy_T_8 | _T_36 | _T_37 | _T_38 | _T_40 | _T_42 | _T_43 | _T_46 | _sec_rdy_T_4; // @[package.scala:16:47]
assign io_mem_finish_valid_0 = ~(~(|state) | _io_probe_rdy_T_2 | _io_probe_rdy_T_3 | _GEN_48) & _sec_rdy_T_5 & grantack_valid; // @[package.scala:16:47]
wire [4:0] _state_T_33 = finish_to_prefetch ? 5'h11 : 5'h0; // @[mshrs.scala:142:31, :381:17]
wire _GEN_49 = _sec_rdy_T_4 | _sec_rdy_T_5 | _sec_rdy_T_6; // @[package.scala:16:47]
wire _GEN_50 = _T_46 | _GEN_49; // @[mshrs.scala:158:26, :350:{22,39}, :363:44, :373:42, :380:42, :382:38]
wire _GEN_51 = _io_probe_rdy_T_4 | _io_probe_rdy_T_8 | _T_36 | _T_37 | _T_38 | _T_40 | _T_42 | _T_43 | _GEN_50; // @[package.scala:16:47]
wire _GEN_52 = _io_probe_rdy_T_2 | _io_probe_rdy_T_3 | _GEN_51; // @[package.scala:16:47]
assign io_req_pri_rdy_0 = ~(|state) | ~_GEN_52 & _io_way_valid_T_1; // @[package.scala:16:47]
wire _T_87 = io_req_sec_val_0 & ~io_req_sec_rdy_0 | io_clear_prefetch_0; // @[mshrs.scala:36:7, :384:{27,30,47}]
wire _r_c_cat_T_52 = _r_c_cat_T_50 | _r_c_cat_T_51; // @[Consts.scala:90:{32,42,49}]
wire _r_c_cat_T_54 = _r_c_cat_T_52 | _r_c_cat_T_53; // @[Consts.scala:90:{42,59,66}]
wire _r_c_cat_T_59 = _r_c_cat_T_55 | _r_c_cat_T_56; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_60 = _r_c_cat_T_59 | _r_c_cat_T_57; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_61 = _r_c_cat_T_60 | _r_c_cat_T_58; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_67 = _r_c_cat_T_62 | _r_c_cat_T_63; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_68 = _r_c_cat_T_67 | _r_c_cat_T_64; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_69 = _r_c_cat_T_68 | _r_c_cat_T_65; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_70 = _r_c_cat_T_69 | _r_c_cat_T_66; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_71 = _r_c_cat_T_61 | _r_c_cat_T_70; // @[package.scala:81:59]
wire _r_c_cat_T_72 = _r_c_cat_T_54 | _r_c_cat_T_71; // @[Consts.scala:87:44, :90:{59,76}]
wire _r_c_cat_T_75 = _r_c_cat_T_73 | _r_c_cat_T_74; // @[Consts.scala:90:{32,42,49}]
wire _r_c_cat_T_77 = _r_c_cat_T_75 | _r_c_cat_T_76; // @[Consts.scala:90:{42,59,66}]
wire _r_c_cat_T_82 = _r_c_cat_T_78 | _r_c_cat_T_79; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_83 = _r_c_cat_T_82 | _r_c_cat_T_80; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_84 = _r_c_cat_T_83 | _r_c_cat_T_81; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_90 = _r_c_cat_T_85 | _r_c_cat_T_86; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_91 = _r_c_cat_T_90 | _r_c_cat_T_87; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_92 = _r_c_cat_T_91 | _r_c_cat_T_88; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_93 = _r_c_cat_T_92 | _r_c_cat_T_89; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_94 = _r_c_cat_T_84 | _r_c_cat_T_93; // @[package.scala:81:59]
wire _r_c_cat_T_95 = _r_c_cat_T_77 | _r_c_cat_T_94; // @[Consts.scala:87:44, :90:{59,76}]
wire _r_c_cat_T_97 = _r_c_cat_T_95 | _r_c_cat_T_96; // @[Consts.scala:90:76, :91:{47,54}]
wire _r_c_cat_T_99 = _r_c_cat_T_97 | _r_c_cat_T_98; // @[Consts.scala:91:{47,64,71}]
wire [1:0] r_c_1 = {_r_c_cat_T_72, _r_c_cat_T_99}; // @[Metadata.scala:29:18]
wire [3:0] _r_T_123 = {r_c_1, new_coh_state}; // @[Metadata.scala:29:18, :58:19]
wire _r_T_148 = _r_T_123 == 4'hC; // @[Misc.scala:49:20]
wire [1:0] _r_T_150 = {1'h0, _r_T_148}; // @[Misc.scala:35:36, :49:20]
wire _r_T_151 = _r_T_123 == 4'hD; // @[Misc.scala:49:20]
wire [1:0] _r_T_153 = _r_T_151 ? 2'h2 : _r_T_150; // @[Misc.scala:35:36, :49:20]
wire _r_T_154 = _r_T_123 == 4'h4; // @[Misc.scala:49:20]
wire [1:0] _r_T_156 = _r_T_154 ? 2'h1 : _r_T_153; // @[Misc.scala:35:36, :49:20]
wire _r_T_157 = _r_T_123 == 4'h5; // @[Misc.scala:49:20]
wire [1:0] _r_T_159 = _r_T_157 ? 2'h2 : _r_T_156; // @[Misc.scala:35:36, :49:20]
wire _r_T_160 = _r_T_123 == 4'h0; // @[Misc.scala:49:20]
wire [1:0] _r_T_162 = _r_T_160 ? 2'h0 : _r_T_159; // @[Misc.scala:35:36, :49:20]
wire _r_T_163 = _r_T_123 == 4'hE; // @[Misc.scala:49:20]
wire _r_T_164 = _r_T_163; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r_T_165 = _r_T_163 ? 2'h3 : _r_T_162; // @[Misc.scala:35:36, :49:20]
wire _r_T_166 = &_r_T_123; // @[Misc.scala:49:20]
wire _r_T_167 = _r_T_166 | _r_T_164; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r_T_168 = _r_T_166 ? 2'h3 : _r_T_165; // @[Misc.scala:35:36, :49:20]
wire _r_T_169 = _r_T_123 == 4'h6; // @[Misc.scala:49:20]
wire _r_T_170 = _r_T_169 | _r_T_167; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r_T_171 = _r_T_169 ? 2'h2 : _r_T_168; // @[Misc.scala:35:36, :49:20]
wire _r_T_172 = _r_T_123 == 4'h7; // @[Misc.scala:49:20]
wire _r_T_173 = _r_T_172 | _r_T_170; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r_T_174 = _r_T_172 ? 2'h3 : _r_T_171; // @[Misc.scala:35:36, :49:20]
wire _r_T_175 = _r_T_123 == 4'h1; // @[Misc.scala:49:20]
wire _r_T_176 = _r_T_175 | _r_T_173; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r_T_177 = _r_T_175 ? 2'h1 : _r_T_174; // @[Misc.scala:35:36, :49:20]
wire _r_T_178 = _r_T_123 == 4'h2; // @[Misc.scala:49:20]
wire _r_T_179 = _r_T_178 | _r_T_176; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r_T_180 = _r_T_178 ? 2'h2 : _r_T_177; // @[Misc.scala:35:36, :49:20]
wire _r_T_181 = _r_T_123 == 4'h3; // @[Misc.scala:49:20]
wire is_hit_1 = _r_T_181 | _r_T_179; // @[Misc.scala:35:9, :49:20]
wire [1:0] r_2_2 = _r_T_181 ? 2'h3 : _r_T_180; // @[Misc.scala:35:36, :49:20]
wire [1:0] coh_on_hit_1_state = r_2_2; // @[Misc.scala:35:36]
wire [4:0] state_new_state_1; // @[mshrs.scala:191:29]
wire _state_T_35 = ~_state_T_34; // @[mshrs.scala:194:11]
wire _state_T_36 = ~_rpq_io_enq_ready; // @[mshrs.scala:128:19, :194:11]
wire _state_req_needs_wb_r_T_83 = _state_req_needs_wb_r_T_70 == 4'h8; // @[Misc.scala:56:20]
wire [2:0] _state_req_needs_wb_r_T_85 = _state_req_needs_wb_r_T_83 ? 3'h5 : 3'h0; // @[Misc.scala:38:36, :56:20]
wire _state_req_needs_wb_r_T_87 = _state_req_needs_wb_r_T_70 == 4'h9; // @[Misc.scala:56:20]
wire [2:0] _state_req_needs_wb_r_T_89 = _state_req_needs_wb_r_T_87 ? 3'h2 : _state_req_needs_wb_r_T_85; // @[Misc.scala:38:36, :56:20]
wire _state_req_needs_wb_r_T_91 = _state_req_needs_wb_r_T_70 == 4'hA; // @[Misc.scala:56:20]
wire [2:0] _state_req_needs_wb_r_T_93 = _state_req_needs_wb_r_T_91 ? 3'h1 : _state_req_needs_wb_r_T_89; // @[Misc.scala:38:36, :56:20]
wire _state_req_needs_wb_r_T_95 = _state_req_needs_wb_r_T_70 == 4'hB; // @[Misc.scala:56:20]
wire _state_req_needs_wb_r_T_96 = _state_req_needs_wb_r_T_95; // @[Misc.scala:38:9, :56:20]
wire [2:0] _state_req_needs_wb_r_T_97 = _state_req_needs_wb_r_T_95 ? 3'h1 : _state_req_needs_wb_r_T_93; // @[Misc.scala:38:36, :56:20]
wire _state_req_needs_wb_r_T_99 = _state_req_needs_wb_r_T_70 == 4'h4; // @[Misc.scala:56:20]
wire _state_req_needs_wb_r_T_100 = ~_state_req_needs_wb_r_T_99 & _state_req_needs_wb_r_T_96; // @[Misc.scala:38:9, :56:20]
wire [2:0] _state_req_needs_wb_r_T_101 = _state_req_needs_wb_r_T_99 ? 3'h5 : _state_req_needs_wb_r_T_97; // @[Misc.scala:38:36, :56:20]
wire _state_req_needs_wb_r_T_103 = _state_req_needs_wb_r_T_70 == 4'h5; // @[Misc.scala:56:20]
wire _state_req_needs_wb_r_T_104 = ~_state_req_needs_wb_r_T_103 & _state_req_needs_wb_r_T_100; // @[Misc.scala:38:9, :56:20]
wire [2:0] _state_req_needs_wb_r_T_105 = _state_req_needs_wb_r_T_103 ? 3'h4 : _state_req_needs_wb_r_T_101; // @[Misc.scala:38:36, :56:20]
wire [1:0] _state_req_needs_wb_r_T_106 = {1'h0, _state_req_needs_wb_r_T_103}; // @[Misc.scala:38:63, :56:20]
wire _state_req_needs_wb_r_T_107 = _state_req_needs_wb_r_T_70 == 4'h6; // @[Misc.scala:56:20]
wire _state_req_needs_wb_r_T_108 = ~_state_req_needs_wb_r_T_107 & _state_req_needs_wb_r_T_104; // @[Misc.scala:38:9, :56:20]
wire [2:0] _state_req_needs_wb_r_T_109 = _state_req_needs_wb_r_T_107 ? 3'h0 : _state_req_needs_wb_r_T_105; // @[Misc.scala:38:36, :56:20]
wire [1:0] _state_req_needs_wb_r_T_110 = _state_req_needs_wb_r_T_107 ? 2'h1 : _state_req_needs_wb_r_T_106; // @[Misc.scala:38:63, :56:20]
wire _state_req_needs_wb_r_T_111 = _state_req_needs_wb_r_T_70 == 4'h7; // @[Misc.scala:56:20]
wire _state_req_needs_wb_r_T_112 = _state_req_needs_wb_r_T_111 | _state_req_needs_wb_r_T_108; // @[Misc.scala:38:9, :56:20]
wire [2:0] _state_req_needs_wb_r_T_113 = _state_req_needs_wb_r_T_111 ? 3'h0 : _state_req_needs_wb_r_T_109; // @[Misc.scala:38:36, :56:20]
wire [1:0] _state_req_needs_wb_r_T_114 = _state_req_needs_wb_r_T_111 ? 2'h1 : _state_req_needs_wb_r_T_110; // @[Misc.scala:38:63, :56:20]
wire _state_req_needs_wb_r_T_115 = _state_req_needs_wb_r_T_70 == 4'h0; // @[Misc.scala:56:20]
wire _state_req_needs_wb_r_T_116 = ~_state_req_needs_wb_r_T_115 & _state_req_needs_wb_r_T_112; // @[Misc.scala:38:9, :56:20]
wire [2:0] _state_req_needs_wb_r_T_117 = _state_req_needs_wb_r_T_115 ? 3'h5 : _state_req_needs_wb_r_T_113; // @[Misc.scala:38:36, :56:20]
wire [1:0] _state_req_needs_wb_r_T_118 = _state_req_needs_wb_r_T_115 ? 2'h0 : _state_req_needs_wb_r_T_114; // @[Misc.scala:38:63, :56:20]
wire _state_req_needs_wb_r_T_119 = _state_req_needs_wb_r_T_70 == 4'h1; // @[Misc.scala:56:20]
wire _state_req_needs_wb_r_T_120 = ~_state_req_needs_wb_r_T_119 & _state_req_needs_wb_r_T_116; // @[Misc.scala:38:9, :56:20]
wire [2:0] _state_req_needs_wb_r_T_121 = _state_req_needs_wb_r_T_119 ? 3'h4 : _state_req_needs_wb_r_T_117; // @[Misc.scala:38:36, :56:20]
wire [1:0] _state_req_needs_wb_r_T_122 = _state_req_needs_wb_r_T_119 ? 2'h1 : _state_req_needs_wb_r_T_118; // @[Misc.scala:38:63, :56:20]
wire _state_req_needs_wb_r_T_123 = _state_req_needs_wb_r_T_70 == 4'h2; // @[Misc.scala:56:20]
wire _state_req_needs_wb_r_T_124 = ~_state_req_needs_wb_r_T_123 & _state_req_needs_wb_r_T_120; // @[Misc.scala:38:9, :56:20]
wire [2:0] _state_req_needs_wb_r_T_125 = _state_req_needs_wb_r_T_123 ? 3'h3 : _state_req_needs_wb_r_T_121; // @[Misc.scala:38:36, :56:20]
wire [1:0] _state_req_needs_wb_r_T_126 = _state_req_needs_wb_r_T_123 ? 2'h2 : _state_req_needs_wb_r_T_122; // @[Misc.scala:38:63, :56:20]
wire _state_req_needs_wb_r_T_127 = _state_req_needs_wb_r_T_70 == 4'h3; // @[Misc.scala:56:20]
wire state_req_needs_wb_r_1_1 = _state_req_needs_wb_r_T_127 | _state_req_needs_wb_r_T_124; // @[Misc.scala:38:9, :56:20]
wire [2:0] state_req_needs_wb_r_2_1 = _state_req_needs_wb_r_T_127 ? 3'h3 : _state_req_needs_wb_r_T_125; // @[Misc.scala:38:36, :56:20]
wire [1:0] state_req_needs_wb_r_3_1 = _state_req_needs_wb_r_T_127 ? 2'h2 : _state_req_needs_wb_r_T_126; // @[Misc.scala:38:63, :56:20]
wire [1:0] state_req_needs_wb_meta_1_state = state_req_needs_wb_r_3_1; // @[Misc.scala:38:63]
wire _state_r_c_cat_T_52 = _state_r_c_cat_T_50 | _state_r_c_cat_T_51; // @[Consts.scala:90:{32,42,49}]
wire _state_r_c_cat_T_54 = _state_r_c_cat_T_52 | _state_r_c_cat_T_53; // @[Consts.scala:90:{42,59,66}]
wire _state_r_c_cat_T_59 = _state_r_c_cat_T_55 | _state_r_c_cat_T_56; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_60 = _state_r_c_cat_T_59 | _state_r_c_cat_T_57; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_61 = _state_r_c_cat_T_60 | _state_r_c_cat_T_58; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_67 = _state_r_c_cat_T_62 | _state_r_c_cat_T_63; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_68 = _state_r_c_cat_T_67 | _state_r_c_cat_T_64; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_69 = _state_r_c_cat_T_68 | _state_r_c_cat_T_65; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_70 = _state_r_c_cat_T_69 | _state_r_c_cat_T_66; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_71 = _state_r_c_cat_T_61 | _state_r_c_cat_T_70; // @[package.scala:81:59]
wire _state_r_c_cat_T_72 = _state_r_c_cat_T_54 | _state_r_c_cat_T_71; // @[Consts.scala:87:44, :90:{59,76}]
wire _state_r_c_cat_T_75 = _state_r_c_cat_T_73 | _state_r_c_cat_T_74; // @[Consts.scala:90:{32,42,49}]
wire _state_r_c_cat_T_77 = _state_r_c_cat_T_75 | _state_r_c_cat_T_76; // @[Consts.scala:90:{42,59,66}]
wire _state_r_c_cat_T_82 = _state_r_c_cat_T_78 | _state_r_c_cat_T_79; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_83 = _state_r_c_cat_T_82 | _state_r_c_cat_T_80; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_84 = _state_r_c_cat_T_83 | _state_r_c_cat_T_81; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_90 = _state_r_c_cat_T_85 | _state_r_c_cat_T_86; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_91 = _state_r_c_cat_T_90 | _state_r_c_cat_T_87; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_92 = _state_r_c_cat_T_91 | _state_r_c_cat_T_88; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_93 = _state_r_c_cat_T_92 | _state_r_c_cat_T_89; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_94 = _state_r_c_cat_T_84 | _state_r_c_cat_T_93; // @[package.scala:81:59]
wire _state_r_c_cat_T_95 = _state_r_c_cat_T_77 | _state_r_c_cat_T_94; // @[Consts.scala:87:44, :90:{59,76}]
wire _state_r_c_cat_T_97 = _state_r_c_cat_T_95 | _state_r_c_cat_T_96; // @[Consts.scala:90:76, :91:{47,54}]
wire _state_r_c_cat_T_99 = _state_r_c_cat_T_97 | _state_r_c_cat_T_98; // @[Consts.scala:91:{47,64,71}]
wire [1:0] state_r_c_1 = {_state_r_c_cat_T_72, _state_r_c_cat_T_99}; // @[Metadata.scala:29:18]
wire [3:0] _state_r_T_59 = {state_r_c_1, io_req_old_meta_coh_state_0}; // @[Metadata.scala:29:18, :58:19]
wire _state_r_T_84 = _state_r_T_59 == 4'hC; // @[Misc.scala:49:20]
wire [1:0] _state_r_T_86 = {1'h0, _state_r_T_84}; // @[Misc.scala:35:36, :49:20]
wire _state_r_T_87 = _state_r_T_59 == 4'hD; // @[Misc.scala:49:20]
wire [1:0] _state_r_T_89 = _state_r_T_87 ? 2'h2 : _state_r_T_86; // @[Misc.scala:35:36, :49:20]
wire _state_r_T_90 = _state_r_T_59 == 4'h4; // @[Misc.scala:49:20]
wire [1:0] _state_r_T_92 = _state_r_T_90 ? 2'h1 : _state_r_T_89; // @[Misc.scala:35:36, :49:20]
wire _state_r_T_93 = _state_r_T_59 == 4'h5; // @[Misc.scala:49:20]
wire [1:0] _state_r_T_95 = _state_r_T_93 ? 2'h2 : _state_r_T_92; // @[Misc.scala:35:36, :49:20]
wire _state_r_T_96 = _state_r_T_59 == 4'h0; // @[Misc.scala:49:20]
wire [1:0] _state_r_T_98 = _state_r_T_96 ? 2'h0 : _state_r_T_95; // @[Misc.scala:35:36, :49:20]
wire _state_r_T_99 = _state_r_T_59 == 4'hE; // @[Misc.scala:49:20]
wire _state_r_T_100 = _state_r_T_99; // @[Misc.scala:35:9, :49:20]
wire [1:0] _state_r_T_101 = _state_r_T_99 ? 2'h3 : _state_r_T_98; // @[Misc.scala:35:36, :49:20]
wire _state_r_T_102 = &_state_r_T_59; // @[Misc.scala:49:20]
wire _state_r_T_103 = _state_r_T_102 | _state_r_T_100; // @[Misc.scala:35:9, :49:20]
wire [1:0] _state_r_T_104 = _state_r_T_102 ? 2'h3 : _state_r_T_101; // @[Misc.scala:35:36, :49:20]
wire _state_r_T_105 = _state_r_T_59 == 4'h6; // @[Misc.scala:49:20]
wire _state_r_T_106 = _state_r_T_105 | _state_r_T_103; // @[Misc.scala:35:9, :49:20]
wire [1:0] _state_r_T_107 = _state_r_T_105 ? 2'h2 : _state_r_T_104; // @[Misc.scala:35:36, :49:20]
wire _state_r_T_108 = _state_r_T_59 == 4'h7; // @[Misc.scala:49:20]
wire _state_r_T_109 = _state_r_T_108 | _state_r_T_106; // @[Misc.scala:35:9, :49:20]
wire [1:0] _state_r_T_110 = _state_r_T_108 ? 2'h3 : _state_r_T_107; // @[Misc.scala:35:36, :49:20]
wire _state_r_T_111 = _state_r_T_59 == 4'h1; // @[Misc.scala:49:20]
wire _state_r_T_112 = _state_r_T_111 | _state_r_T_109; // @[Misc.scala:35:9, :49:20]
wire [1:0] _state_r_T_113 = _state_r_T_111 ? 2'h1 : _state_r_T_110; // @[Misc.scala:35:36, :49:20]
wire _state_r_T_114 = _state_r_T_59 == 4'h2; // @[Misc.scala:49:20]
wire _state_r_T_115 = _state_r_T_114 | _state_r_T_112; // @[Misc.scala:35:9, :49:20]
wire [1:0] _state_r_T_116 = _state_r_T_114 ? 2'h2 : _state_r_T_113; // @[Misc.scala:35:36, :49:20]
wire _state_r_T_117 = _state_r_T_59 == 4'h3; // @[Misc.scala:49:20]
wire state_is_hit_1 = _state_r_T_117 | _state_r_T_115; // @[Misc.scala:35:9, :49:20]
wire [1:0] state_r_2_1 = _state_r_T_117 ? 2'h3 : _state_r_T_116; // @[Misc.scala:35:36, :49:20]
wire [1:0] state_coh_on_hit_1_state = state_r_2_1; // @[Misc.scala:35:36]
wire _state_T_39 = _state_T_37 | _state_T_38; // @[Consts.scala:90:{32,42,49}]
wire _state_T_41 = _state_T_39 | _state_T_40; // @[Consts.scala:90:{42,59,66}]
wire _state_T_46 = _state_T_42 | _state_T_43; // @[package.scala:16:47, :81:59]
wire _state_T_47 = _state_T_46 | _state_T_44; // @[package.scala:16:47, :81:59]
wire _state_T_48 = _state_T_47 | _state_T_45; // @[package.scala:16:47, :81:59]
wire _state_T_54 = _state_T_49 | _state_T_50; // @[package.scala:16:47, :81:59]
wire _state_T_55 = _state_T_54 | _state_T_51; // @[package.scala:16:47, :81:59]
wire _state_T_56 = _state_T_55 | _state_T_52; // @[package.scala:16:47, :81:59]
wire _state_T_57 = _state_T_56 | _state_T_53; // @[package.scala:16:47, :81:59]
wire _state_T_58 = _state_T_48 | _state_T_57; // @[package.scala:81:59]
wire _state_T_59 = _state_T_41 | _state_T_58; // @[Consts.scala:87:44, :90:{59,76}]
wire _state_T_61 = ~_state_T_60; // @[mshrs.scala:201:15]
wire _state_T_62 = ~_state_T_59; // @[Consts.scala:90:76] |
Generate the Verilog code corresponding to the following Chisel files.
File Monitor.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceLine
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import freechips.rocketchip.diplomacy.EnableMonitors
import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode}
import freechips.rocketchip.util.PlusArg
case class TLMonitorArgs(edge: TLEdge)
abstract class TLMonitorBase(args: TLMonitorArgs) extends Module
{
val io = IO(new Bundle {
val in = Input(new TLBundle(args.edge.bundle))
})
def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit
legalize(io.in, args.edge, reset)
}
object TLMonitor {
def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = {
if (enable) {
EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) }
} else { node }
}
}
class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args)
{
require (args.edge.params(TLMonitorStrictMode) || (! args.edge.params(TestplanTestType).formal))
val cover_prop_class = PropertyClass.Default
//Like assert but can flip to being an assumption for formal verification
def monAssert(cond: Bool, message: String): Unit =
if (monitorDir == MonitorDirection.Monitor) {
assert(cond, message)
} else {
Property(monitorDir, cond, message, PropertyClass.Default)
}
def assume(cond: Bool, message: String): Unit =
if (monitorDir == MonitorDirection.Monitor) {
assert(cond, message)
} else {
Property(monitorDir.flip, cond, message, PropertyClass.Default)
}
def extra = {
args.edge.sourceInfo match {
case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)"
case _ => ""
}
}
def visible(address: UInt, source: UInt, edge: TLEdge) =
edge.client.clients.map { c =>
!c.sourceId.contains(source) ||
c.visibility.map(_.contains(address)).reduce(_ || _)
}.reduce(_ && _)
def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = {
//switch this flag to turn on diplomacy in error messages
def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n"
monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra)
// Reuse these subexpressions to save some firrtl lines
val source_ok = edge.client.contains(bundle.source)
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val mask = edge.full_mask(bundle)
monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility")
//The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B
//TODO: check for acquireT?
when (bundle.opcode === TLMessages.AcquireBlock) {
monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra)
monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra)
monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra)
monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra)
}
when (bundle.opcode === TLMessages.AcquirePerm) {
monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra)
monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra)
monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra)
monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra)
monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra)
}
when (bundle.opcode === TLMessages.Get) {
monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra)
monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra)
monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra)
}
when (bundle.opcode === TLMessages.PutFullData) {
monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra)
monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.PutPartialData) {
monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra)
monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.ArithmeticData) {
monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra)
monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.LogicalData) {
monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra)
monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.Hint) {
monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra)
monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra)
}
}
def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = {
monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra)
monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility")
// Reuse these subexpressions to save some firrtl lines
val address_ok = edge.manager.containsSafe(edge.address(bundle))
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val mask = edge.full_mask(bundle)
val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source
when (bundle.opcode === TLMessages.Probe) {
assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra)
assume (address_ok, "'B' channel Probe carries unmanaged address" + extra)
assume (legal_source, "'B' channel Probe carries source that is not first source" + extra)
assume (is_aligned, "'B' channel Probe address not aligned to size" + extra)
assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra)
assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra)
assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra)
}
when (bundle.opcode === TLMessages.Get) {
monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra)
monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra)
}
when (bundle.opcode === TLMessages.PutFullData) {
monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra)
monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.PutPartialData) {
monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra)
monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.ArithmeticData) {
monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra)
monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra)
monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.LogicalData) {
monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra)
monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra)
monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.Hint) {
monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra)
monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra)
monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra)
}
}
def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = {
monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra)
val source_ok = edge.client.contains(bundle.source)
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val address_ok = edge.manager.containsSafe(edge.address(bundle))
monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility")
when (bundle.opcode === TLMessages.ProbeAck) {
monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra)
monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra)
}
when (bundle.opcode === TLMessages.ProbeAckData) {
monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra)
}
when (bundle.opcode === TLMessages.Release) {
monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra)
monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra)
monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra)
}
when (bundle.opcode === TLMessages.ReleaseData) {
monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra)
monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra)
}
when (bundle.opcode === TLMessages.AccessAck) {
monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra)
monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra)
}
when (bundle.opcode === TLMessages.AccessAckData) {
monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra)
}
when (bundle.opcode === TLMessages.HintAck) {
monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra)
monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra)
}
}
def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = {
assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra)
val source_ok = edge.client.contains(bundle.source)
val sink_ok = bundle.sink < edge.manager.endSinkId.U
val deny_put_ok = edge.manager.mayDenyPut.B
val deny_get_ok = edge.manager.mayDenyGet.B
when (bundle.opcode === TLMessages.ReleaseAck) {
assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra)
assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra)
assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra)
}
when (bundle.opcode === TLMessages.Grant) {
assume (source_ok, "'D' channel Grant carries invalid source ID" + extra)
assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra)
assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra)
assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra)
assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel Grant is denied" + extra)
}
when (bundle.opcode === TLMessages.GrantData) {
assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra)
assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra)
assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra)
assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra)
assume (!bundle.denied || bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra)
assume (deny_get_ok || !bundle.denied, "'D' channel GrantData is denied" + extra)
}
when (bundle.opcode === TLMessages.AccessAck) {
assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel AccessAck is denied" + extra)
}
when (bundle.opcode === TLMessages.AccessAckData) {
assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra)
assume (!bundle.denied || bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra)
assume (deny_get_ok || !bundle.denied, "'D' channel AccessAckData is denied" + extra)
}
when (bundle.opcode === TLMessages.HintAck) {
assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel HintAck is denied" + extra)
}
}
def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = {
val sink_ok = bundle.sink < edge.manager.endSinkId.U
monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra)
}
def legalizeFormat(bundle: TLBundle, edge: TLEdge) = {
when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) }
when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) }
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) }
when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) }
when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) }
} else {
monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra)
monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra)
monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra)
}
}
def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = {
val a_first = edge.first(a.bits, a.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (a.valid && !a_first) {
monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra)
monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra)
monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra)
monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra)
monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra)
}
when (a.fire && a_first) {
opcode := a.bits.opcode
param := a.bits.param
size := a.bits.size
source := a.bits.source
address := a.bits.address
}
}
def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = {
val b_first = edge.first(b.bits, b.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (b.valid && !b_first) {
monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra)
monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra)
monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra)
monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra)
monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra)
}
when (b.fire && b_first) {
opcode := b.bits.opcode
param := b.bits.param
size := b.bits.size
source := b.bits.source
address := b.bits.address
}
}
def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = {
// Symbolic variable
val sym_source = Wire(UInt(edge.client.endSourceId.W))
// TODO: Connect sym_source to a fixed value for simulation and to a
// free wire in formal
sym_source := 0.U
// Type casting Int to UInt
val maxSourceId = Wire(UInt(edge.client.endSourceId.W))
maxSourceId := edge.client.endSourceId.U
// Delayed verison of sym_source
val sym_source_d = Reg(UInt(edge.client.endSourceId.W))
sym_source_d := sym_source
// These will be constraints for FV setup
Property(
MonitorDirection.Monitor,
(sym_source === sym_source_d),
"sym_source should remain stable",
PropertyClass.Default)
Property(
MonitorDirection.Monitor,
(sym_source <= maxSourceId),
"sym_source should take legal value",
PropertyClass.Default)
val my_resp_pend = RegInit(false.B)
val my_opcode = Reg(UInt())
val my_size = Reg(UInt())
val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire)
val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire)
val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source)
val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source)
val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat)
val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend)
when (my_set_resp_pend) {
my_resp_pend := true.B
} .elsewhen (my_clr_resp_pend) {
my_resp_pend := false.B
}
when (my_a_first_beat) {
my_opcode := bundle.a.bits.opcode
my_size := bundle.a.bits.size
}
val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size)
val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode)
val my_resp_opcode_legal = Wire(Bool())
when ((my_resp_opcode === TLMessages.Get) || (my_resp_opcode === TLMessages.ArithmeticData) ||
(my_resp_opcode === TLMessages.LogicalData)) {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData)
} .elsewhen ((my_resp_opcode === TLMessages.PutFullData) || (my_resp_opcode === TLMessages.PutPartialData)) {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck)
} .otherwise {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck)
}
monAssert (IfThen(my_resp_pend, !my_a_first_beat),
"Request message should not be sent with a source ID, for which a response message" +
"is already pending (not received until current cycle) for a prior request message" +
"with the same source ID" + extra)
assume (IfThen(my_clr_resp_pend, (my_set_resp_pend || my_resp_pend)),
"Response message should be accepted with a source ID only if a request message with the" +
"same source ID has been accepted or is being accepted in the current cycle" + extra)
assume (IfThen(my_d_first_beat, (my_a_first_beat || my_resp_pend)),
"Response message should be sent with a source ID only if a request message with the" +
"same source ID has been accepted or is being sent in the current cycle" + extra)
assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)),
"If d_valid is 1, then d_size should be same as a_size of the corresponding request" +
"message" + extra)
assume (IfThen(my_d_first_beat, my_resp_opcode_legal),
"If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" +
"request message" + extra)
}
def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = {
val c_first = edge.first(c.bits, c.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (c.valid && !c_first) {
monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra)
monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra)
monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra)
monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra)
monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra)
}
when (c.fire && c_first) {
opcode := c.bits.opcode
param := c.bits.param
size := c.bits.size
source := c.bits.source
address := c.bits.address
}
}
def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = {
val d_first = edge.first(d.bits, d.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val sink = Reg(UInt())
val denied = Reg(Bool())
when (d.valid && !d_first) {
assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra)
assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra)
assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra)
assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra)
assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra)
assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra)
}
when (d.fire && d_first) {
opcode := d.bits.opcode
param := d.bits.param
size := d.bits.size
source := d.bits.source
sink := d.bits.sink
denied := d.bits.denied
}
}
def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = {
legalizeMultibeatA(bundle.a, edge)
legalizeMultibeatD(bundle.d, edge)
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
legalizeMultibeatB(bundle.b, edge)
legalizeMultibeatC(bundle.c, edge)
}
}
//This is left in for almond which doesn't adhere to the tilelink protocol
@deprecated("Use legalizeADSource instead if possible","")
def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = {
val inflight = RegInit(0.U(edge.client.endSourceId.W))
val a_first = edge.first(bundle.a.bits, bundle.a.fire)
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
val a_set = WireInit(0.U(edge.client.endSourceId.W))
when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) {
a_set := UIntToOH(bundle.a.bits.source)
assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra)
}
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
assume((a_set | inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra)
}
if (edge.manager.minLatency > 0) {
assume(a_set =/= d_clr || !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra)
}
inflight := (inflight | a_set) & ~d_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
assert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = {
val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset)
val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything
val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size)
val log_a_size_bus_size = log2Ceil(a_size_bus_size)
def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits
val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error
inflight.suggestName("inflight")
val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
inflight_opcodes.suggestName("inflight_opcodes")
val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
inflight_sizes.suggestName("inflight_sizes")
val a_first = edge.first(bundle.a.bits, bundle.a.fire)
a_first.suggestName("a_first")
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
d_first.suggestName("d_first")
val a_set = WireInit(0.U(edge.client.endSourceId.W))
val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
a_set.suggestName("a_set")
a_set_wo_ready.suggestName("a_set_wo_ready")
val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
a_opcodes_set.suggestName("a_opcodes_set")
val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
a_sizes_set.suggestName("a_sizes_set")
val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W))
a_opcode_lookup.suggestName("a_opcode_lookup")
a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U
val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W))
a_size_lookup.suggestName("a_size_lookup")
a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U
val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant))
val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant))
val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W))
a_opcodes_set_interm.suggestName("a_opcodes_set_interm")
val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W))
a_sizes_set_interm.suggestName("a_sizes_set_interm")
when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) {
a_set_wo_ready := UIntToOH(bundle.a.bits.source)
}
when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) {
a_set := UIntToOH(bundle.a.bits.source)
a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) | 1.U
a_sizes_set_interm := (bundle.a.bits.size << 1.U) | 1.U
a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U)
a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U)
monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra)
}
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
d_clr.suggestName("d_clr")
d_clr_wo_ready.suggestName("d_clr_wo_ready")
val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
d_opcodes_clr.suggestName("d_opcodes_clr")
val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
d_sizes_clr.suggestName("d_sizes_clr")
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr_wo_ready := UIntToOH(bundle.d.bits.source)
}
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U)
d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U)
}
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source)
assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra)
when (same_cycle_resp) {
assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) ||
(bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra)
assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra)
} .otherwise {
assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) ||
(bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra)
assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra)
}
}
when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) {
assume((!bundle.d.ready) || bundle.a.ready, "ready check")
}
if (edge.manager.minLatency > 0) {
assume(a_set_wo_ready =/= d_clr_wo_ready || !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra)
}
inflight := (inflight | a_set) & ~d_clr
inflight_opcodes := (inflight_opcodes | a_opcodes_set) & ~d_opcodes_clr
inflight_sizes := (inflight_sizes | a_sizes_set) & ~d_sizes_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = {
val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset)
val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything
val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size)
val log_c_size_bus_size = log2Ceil(c_size_bus_size)
def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits
val inflight = RegInit(0.U((2 max edge.client.endSourceId).W))
val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
inflight.suggestName("inflight")
inflight_opcodes.suggestName("inflight_opcodes")
inflight_sizes.suggestName("inflight_sizes")
val c_first = edge.first(bundle.c.bits, bundle.c.fire)
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
c_first.suggestName("c_first")
d_first.suggestName("d_first")
val c_set = WireInit(0.U(edge.client.endSourceId.W))
val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
c_set.suggestName("c_set")
c_set_wo_ready.suggestName("c_set_wo_ready")
c_opcodes_set.suggestName("c_opcodes_set")
c_sizes_set.suggestName("c_sizes_set")
val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W))
val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W))
c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U
c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U
c_opcode_lookup.suggestName("c_opcode_lookup")
c_size_lookup.suggestName("c_size_lookup")
val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W))
val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W))
c_opcodes_set_interm.suggestName("c_opcodes_set_interm")
c_sizes_set_interm.suggestName("c_sizes_set_interm")
when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) {
c_set_wo_ready := UIntToOH(bundle.c.bits.source)
}
when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) {
c_set := UIntToOH(bundle.c.bits.source)
c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) | 1.U
c_sizes_set_interm := (bundle.c.bits.size << 1.U) | 1.U
c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U)
c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U)
monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra)
}
val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck || bundle.c.bits.opcode === TLMessages.ProbeAckData
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
d_clr.suggestName("d_clr")
d_clr_wo_ready.suggestName("d_clr_wo_ready")
d_opcodes_clr.suggestName("d_opcodes_clr")
d_sizes_clr.suggestName("d_sizes_clr")
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
d_clr_wo_ready := UIntToOH(bundle.d.bits.source)
}
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U)
d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U)
}
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source)
assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra)
when (same_cycle_resp) {
assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra)
} .otherwise {
assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra)
}
}
when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) {
assume((!bundle.d.ready) || bundle.c.ready, "ready check")
}
if (edge.manager.minLatency > 0) {
when (c_set_wo_ready.orR) {
assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra)
}
}
inflight := (inflight | c_set) & ~d_clr
inflight_opcodes := (inflight_opcodes | c_opcodes_set) & ~d_opcodes_clr
inflight_sizes := (inflight_sizes | c_sizes_set) & ~d_sizes_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.c.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = {
val inflight = RegInit(0.U(edge.manager.endSinkId.W))
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
val e_first = true.B
val d_set = WireInit(0.U(edge.manager.endSinkId.W))
when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) {
d_set := UIntToOH(bundle.d.bits.sink)
assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra)
}
val e_clr = WireInit(0.U(edge.manager.endSinkId.W))
when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) {
e_clr := UIntToOH(bundle.e.bits.sink)
monAssert((d_set | inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra)
}
// edge.client.minLatency applies to BC, not DE
inflight := (inflight | d_set) & ~e_clr
}
def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = {
val sourceBits = log2Ceil(edge.client.endSourceId)
val tooBig = 14 // >16kB worth of flight information gets to be too much
if (sourceBits > tooBig) {
println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked")
} else {
if (args.edge.params(TestplanTestType).simulation) {
if (args.edge.params(TLMonitorStrictMode)) {
legalizeADSource(bundle, edge)
legalizeCDSource(bundle, edge)
} else {
legalizeADSourceOld(bundle, edge)
}
}
if (args.edge.params(TestplanTestType).formal) {
legalizeADSourceFormal(bundle, edge)
}
}
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
// legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize...
val sinkBits = log2Ceil(edge.manager.endSinkId)
if (sinkBits > tooBig) {
println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked")
} else {
legalizeDESink(bundle, edge)
}
}
}
def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = {
legalizeFormat (bundle, edge)
legalizeMultibeat (bundle, edge)
legalizeUnique (bundle, edge)
}
}
File Misc.scala:
// See LICENSE.Berkeley for license details.
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util._
import chisel3.util.random.LFSR
import org.chipsalliance.cde.config.Parameters
import scala.math._
class ParameterizedBundle(implicit p: Parameters) extends Bundle
trait Clocked extends Bundle {
val clock = Clock()
val reset = Bool()
}
object DecoupledHelper {
def apply(rvs: Bool*) = new DecoupledHelper(rvs)
}
class DecoupledHelper(val rvs: Seq[Bool]) {
def fire(exclude: Bool, includes: Bool*) = {
require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!")
(rvs.filter(_ ne exclude) ++ includes).reduce(_ && _)
}
def fire() = {
rvs.reduce(_ && _)
}
}
object MuxT {
def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2))
def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3))
def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4))
}
/** Creates a cascade of n MuxTs to search for a key value. */
object MuxTLookup {
def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = {
var res = default
for ((k, v) <- mapping.reverse)
res = MuxT(k === key, v, res)
res
}
def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = {
var res = default
for ((k, v) <- mapping.reverse)
res = MuxT(k === key, v, res)
res
}
}
object ValidMux {
def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = {
apply(v1 +: v2.toSeq)
}
def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = {
val out = Wire(Valid(valids.head.bits.cloneType))
out.valid := valids.map(_.valid).reduce(_ || _)
out.bits := MuxCase(valids.head.bits,
valids.map(v => (v.valid -> v.bits)))
out
}
}
object Str
{
def apply(s: String): UInt = {
var i = BigInt(0)
require(s.forall(validChar _))
for (c <- s)
i = (i << 8) | c
i.U((s.length*8).W)
}
def apply(x: Char): UInt = {
require(validChar(x))
x.U(8.W)
}
def apply(x: UInt): UInt = apply(x, 10)
def apply(x: UInt, radix: Int): UInt = {
val rad = radix.U
val w = x.getWidth
require(w > 0)
var q = x
var s = digit(q % rad)
for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {
q = q / rad
s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s)
}
s
}
def apply(x: SInt): UInt = apply(x, 10)
def apply(x: SInt, radix: Int): UInt = {
val neg = x < 0.S
val abs = x.abs.asUInt
if (radix != 10) {
Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix))
} else {
val rad = radix.U
val w = abs.getWidth
require(w > 0)
var q = abs
var s = digit(q % rad)
var needSign = neg
for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {
q = q / rad
val placeSpace = q === 0.U
val space = Mux(needSign, Str('-'), Str(' '))
needSign = needSign && !placeSpace
s = Cat(Mux(placeSpace, space, digit(q % rad)), s)
}
Cat(Mux(needSign, Str('-'), Str(' ')), s)
}
}
private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0)
private def validChar(x: Char) = x == (x & 0xFF)
}
object Split
{
def apply(x: UInt, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n0), x.extract(n0-1,0))
}
def apply(x: UInt, n1: Int, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))
}
def apply(x: UInt, n2: Int, n1: Int, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))
}
}
object Random
{
def apply(mod: Int, random: UInt): UInt = {
if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0)
else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod))
}
def apply(mod: Int): UInt = apply(mod, randomizer)
def oneHot(mod: Int, random: UInt): UInt = {
if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0))
else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt
}
def oneHot(mod: Int): UInt = oneHot(mod, randomizer)
private def randomizer = LFSR(16)
private def partition(value: UInt, slices: Int) =
Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U)
}
object Majority {
def apply(in: Set[Bool]): Bool = {
val n = (in.size >> 1) + 1
val clauses = in.subsets(n).map(_.reduce(_ && _))
clauses.reduce(_ || _)
}
def apply(in: Seq[Bool]): Bool = apply(in.toSet)
def apply(in: UInt): Bool = apply(in.asBools.toSet)
}
object PopCountAtLeast {
private def two(x: UInt): (Bool, Bool) = x.getWidth match {
case 1 => (x.asBool, false.B)
case n =>
val half = x.getWidth / 2
val (leftOne, leftTwo) = two(x(half - 1, 0))
val (rightOne, rightTwo) = two(x(x.getWidth - 1, half))
(leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne))
}
def apply(x: UInt, n: Int): Bool = n match {
case 0 => true.B
case 1 => x.orR
case 2 => two(x)._2
case 3 => PopCount(x) >= n.U
}
}
// This gets used everywhere, so make the smallest circuit possible ...
// Given an address and size, create a mask of beatBytes size
// eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111
// groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01
object MaskGen {
def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = {
require (groupBy >= 1 && beatBytes >= groupBy)
require (isPow2(beatBytes) && isPow2(groupBy))
val lgBytes = log2Ceil(beatBytes)
val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U
def helper(i: Int): Seq[(Bool, Bool)] = {
if (i == 0) {
Seq((lgSize >= lgBytes.asUInt, true.B))
} else {
val sub = helper(i-1)
val size = sizeOH(lgBytes - i)
val bit = addr_lo(lgBytes - i)
val nbit = !bit
Seq.tabulate (1 << i) { j =>
val (sub_acc, sub_eq) = sub(j/2)
val eq = sub_eq && (if (j % 2 == 1) bit else nbit)
val acc = sub_acc || (size && eq)
(acc, eq)
}
}
}
if (groupBy == beatBytes) 1.U else
Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse)
}
}
File PlusArg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.experimental._
import chisel3.util.HasBlackBoxResource
@deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05")
case class PlusArgInfo(default: BigInt, docstring: String)
/** Case class for PlusArg information
*
* @tparam A scala type of the PlusArg value
* @param default optional default value
* @param docstring text to include in the help
* @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT)
*/
private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String)
/** Typeclass for converting a type to a doctype string
* @tparam A some type
*/
trait Doctypeable[A] {
/** Return the doctype string for some option */
def toDoctype(a: Option[A]): String
}
/** Object containing implementations of the Doctypeable typeclass */
object Doctypes {
/** Converts an Int => "INT" */
implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" }
/** Converts a BigInt => "INT" */
implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" }
/** Converts a String => "STRING" */
implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" }
}
class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map(
"FORMAT" -> StringParam(format),
"DEFAULT" -> IntParam(default),
"WIDTH" -> IntParam(width)
)) with HasBlackBoxResource {
val io = IO(new Bundle {
val out = Output(UInt(width.W))
})
addResource("/vsrc/plusarg_reader.v")
}
/* This wrapper class has no outputs, making it clear it is a simulation-only construct */
class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module {
val io = IO(new Bundle {
val count = Input(UInt(width.W))
})
val max = Module(new plusarg_reader(format, default, docstring, width)).io.out
when (max > 0.U) {
assert (io.count < max, s"Timeout exceeded: $docstring")
}
}
import Doctypes._
object PlusArg
{
/** PlusArg("foo") will return 42.U if the simulation is run with +foo=42
* Do not use this as an initial register value. The value is set in an
* initial block and thus accessing it from another initial is racey.
* Add a docstring to document the arg, which can be dumped in an elaboration
* pass.
*/
def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = {
PlusArgArtefacts.append(name, Some(default), docstring)
Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out
}
/** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert
* to kill the simulation when count exceeds the specified integer argument.
* Default 0 will never assert.
*/
def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = {
PlusArgArtefacts.append(name, Some(default), docstring)
Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count
}
}
object PlusArgArtefacts {
private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty
/* Add a new PlusArg */
@deprecated(
"Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08",
"Rocket Chip 2020.05"
)
def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring)
/** Add a new PlusArg
*
* @tparam A scala type of the PlusArg value
* @param name name for the PlusArg
* @param default optional default value
* @param docstring text to include in the help
*/
def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit =
artefacts = artefacts ++
Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default)))
/* From plus args, generate help text */
private def serializeHelp_cHeader(tab: String = ""): String = artefacts
.map{ case(arg, info) =>
s"""|$tab+$arg=${info.doctype}\\n\\
|$tab${" "*20}${info.docstring}\\n\\
|""".stripMargin ++ info.default.map{ case default =>
s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("")
}.toSeq.mkString("\\n\\\n") ++ "\""
/* From plus args, generate a char array of their names */
private def serializeArray_cHeader(tab: String = ""): String = {
val prettyTab = tab + " " * 44 // Length of 'static const ...'
s"${tab}static const char * verilog_plusargs [] = {\\\n" ++
artefacts
.map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" }
.mkString("")++
s"${prettyTab}0};"
}
/* Generate C code to be included in emulator.cc that helps with
* argument parsing based on available Verilog PlusArgs */
def serialize_cHeader(): String =
s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\
|${serializeHelp_cHeader(" "*7)}
|${serializeArray_cHeader()}
|""".stripMargin
}
File package.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip
import chisel3._
import chisel3.util._
import scala.math.min
import scala.collection.{immutable, mutable}
package object util {
implicit class UnzippableOption[S, T](val x: Option[(S, T)]) {
def unzip = (x.map(_._1), x.map(_._2))
}
implicit class UIntIsOneOf(private val x: UInt) extends AnyVal {
def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR
def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq)
}
implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal {
/** Like Vec.apply(idx), but tolerates indices of mismatched width */
def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0))
}
implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal {
def apply(idx: UInt): T = {
if (x.size <= 1) {
x.head
} else if (!isPow2(x.size)) {
// For non-power-of-2 seqs, reflect elements to simplify decoder
(x ++ x.takeRight(x.size & -x.size)).toSeq(idx)
} else {
// Ignore MSBs of idx
val truncIdx =
if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx
else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0)
x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) }
}
}
def extract(idx: UInt): T = VecInit(x).extract(idx)
def asUInt: UInt = Cat(x.map(_.asUInt).reverse)
def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n)
def rotate(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n)
def rotateRight(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
}
// allow bitwise ops on Seq[Bool] just like UInt
implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal {
def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b }
def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b }
def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b }
def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x
def >> (n: Int): Seq[Bool] = x drop n
def unary_~ : Seq[Bool] = x.map(!_)
def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_)
def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_)
def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_)
private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B)
}
implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal {
def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable))
def getElements: Seq[Element] = x match {
case e: Element => Seq(e)
case a: Aggregate => a.getElements.flatMap(_.getElements)
}
}
/** Any Data subtype that has a Bool member named valid. */
type DataCanBeValid = Data { val valid: Bool }
implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal {
def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable)
}
implicit class StringToAugmentedString(private val x: String) extends AnyVal {
/** converts from camel case to to underscores, also removing all spaces */
def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") {
case (acc, c) if c.isUpper => acc + "_" + c.toLower
case (acc, c) if c == ' ' => acc
case (acc, c) => acc + c
}
/** converts spaces or underscores to hyphens, also lowering case */
def kebab: String = x.toLowerCase map {
case ' ' => '-'
case '_' => '-'
case c => c
}
def named(name: Option[String]): String = {
x + name.map("_named_" + _ ).getOrElse("_with_no_name")
}
def named(name: String): String = named(Some(name))
}
implicit def uintToBitPat(x: UInt): BitPat = BitPat(x)
implicit def wcToUInt(c: WideCounter): UInt = c.value
implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal {
def sextTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x)
}
def padTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(0.U((n - x.getWidth).W), x)
}
// shifts left by n if n >= 0, or right by -n if n < 0
def << (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << n(w-1, 0)
Mux(n(w), shifted >> (1 << w), shifted)
}
// shifts right by n if n >= 0, or left by -n if n < 0
def >> (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << (1 << w) >> n(w-1, 0)
Mux(n(w), shifted, shifted >> (1 << w))
}
// Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts
def extract(hi: Int, lo: Int): UInt = {
require(hi >= lo-1)
if (hi == lo-1) 0.U
else x(hi, lo)
}
// Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts
def extractOption(hi: Int, lo: Int): Option[UInt] = {
require(hi >= lo-1)
if (hi == lo-1) None
else Some(x(hi, lo))
}
// like x & ~y, but first truncate or zero-extend y to x's width
def andNot(y: UInt): UInt = x & ~(y | (x & 0.U))
def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n)
def rotateRight(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r))
}
}
def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n))
def rotateLeft(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r))
}
}
// compute (this + y) % n, given (this < n) and (y < n)
def addWrap(y: UInt, n: Int): UInt = {
val z = x +& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0)
}
// compute (this - y) % n, given (this < n) and (y < n)
def subWrap(y: UInt, n: Int): UInt = {
val z = x -& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0)
}
def grouped(width: Int): Seq[UInt] =
(0 until x.getWidth by width).map(base => x(base + width - 1, base))
def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds
def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x)
// Like >=, but prevents x-prop for ('x >= 0)
def >== (y: UInt): Bool = x >= y || y === 0.U
}
implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal {
def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y)
def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y)
}
implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal {
def toInt: Int = if (x) 1 else 0
// this one's snagged from scalaz
def option[T](z: => T): Option[T] = if (x) Some(z) else None
}
implicit class IntToAugmentedInt(private val x: Int) extends AnyVal {
// exact log2
def log2: Int = {
require(isPow2(x))
log2Ceil(x)
}
}
def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x)
def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x))
def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0)
def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1)
def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None
// Fill 1s from low bits to high bits
def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth)
def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0))
helper(1, x)(width-1, 0)
}
// Fill 1s form high bits to low bits
def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth)
def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x >> s))
helper(1, x)(width-1, 0)
}
def OptimizationBarrier[T <: Data](in: T): T = {
val barrier = Module(new Module {
val io = IO(new Bundle {
val x = Input(chiselTypeOf(in))
val y = Output(chiselTypeOf(in))
})
io.y := io.x
override def desiredName = s"OptimizationBarrier_${in.typeName}"
})
barrier.io.x := in
barrier.io.y
}
/** Similar to Seq.groupBy except this returns a Seq instead of a Map
* Useful for deterministic code generation
*/
def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = {
val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]]
for (x <- xs) {
val key = f(x)
val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A])
l += x
}
map.view.map({ case (k, vs) => k -> vs.toList }).toList
}
def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match {
case 1 => List.fill(n)(in.head)
case x if x == n => in
case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in")
}
// HeterogeneousBag moved to standalond diplomacy
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts)
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag
}
File Bundles.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import freechips.rocketchip.util._
import scala.collection.immutable.ListMap
import chisel3.util.Decoupled
import chisel3.util.DecoupledIO
import chisel3.reflect.DataMirror
abstract class TLBundleBase(val params: TLBundleParameters) extends Bundle
// common combos in lazy policy:
// Put + Acquire
// Release + AccessAck
object TLMessages
{
// A B C D E
def PutFullData = 0.U // . . => AccessAck
def PutPartialData = 1.U // . . => AccessAck
def ArithmeticData = 2.U // . . => AccessAckData
def LogicalData = 3.U // . . => AccessAckData
def Get = 4.U // . . => AccessAckData
def Hint = 5.U // . . => HintAck
def AcquireBlock = 6.U // . => Grant[Data]
def AcquirePerm = 7.U // . => Grant[Data]
def Probe = 6.U // . => ProbeAck[Data]
def AccessAck = 0.U // . .
def AccessAckData = 1.U // . .
def HintAck = 2.U // . .
def ProbeAck = 4.U // .
def ProbeAckData = 5.U // .
def Release = 6.U // . => ReleaseAck
def ReleaseData = 7.U // . => ReleaseAck
def Grant = 4.U // . => GrantAck
def GrantData = 5.U // . => GrantAck
def ReleaseAck = 6.U // .
def GrantAck = 0.U // .
def isA(x: UInt) = x <= AcquirePerm
def isB(x: UInt) = x <= Probe
def isC(x: UInt) = x <= ReleaseData
def isD(x: UInt) = x <= ReleaseAck
def adResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant, Grant)
def bcResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, ProbeAck, ProbeAck)
def a = Seq( ("PutFullData",TLPermissions.PermMsgReserved),
("PutPartialData",TLPermissions.PermMsgReserved),
("ArithmeticData",TLAtomics.ArithMsg),
("LogicalData",TLAtomics.LogicMsg),
("Get",TLPermissions.PermMsgReserved),
("Hint",TLHints.HintsMsg),
("AcquireBlock",TLPermissions.PermMsgGrow),
("AcquirePerm",TLPermissions.PermMsgGrow))
def b = Seq( ("PutFullData",TLPermissions.PermMsgReserved),
("PutPartialData",TLPermissions.PermMsgReserved),
("ArithmeticData",TLAtomics.ArithMsg),
("LogicalData",TLAtomics.LogicMsg),
("Get",TLPermissions.PermMsgReserved),
("Hint",TLHints.HintsMsg),
("Probe",TLPermissions.PermMsgCap))
def c = Seq( ("AccessAck",TLPermissions.PermMsgReserved),
("AccessAckData",TLPermissions.PermMsgReserved),
("HintAck",TLPermissions.PermMsgReserved),
("Invalid Opcode",TLPermissions.PermMsgReserved),
("ProbeAck",TLPermissions.PermMsgReport),
("ProbeAckData",TLPermissions.PermMsgReport),
("Release",TLPermissions.PermMsgReport),
("ReleaseData",TLPermissions.PermMsgReport))
def d = Seq( ("AccessAck",TLPermissions.PermMsgReserved),
("AccessAckData",TLPermissions.PermMsgReserved),
("HintAck",TLPermissions.PermMsgReserved),
("Invalid Opcode",TLPermissions.PermMsgReserved),
("Grant",TLPermissions.PermMsgCap),
("GrantData",TLPermissions.PermMsgCap),
("ReleaseAck",TLPermissions.PermMsgReserved))
}
/**
* The three primary TileLink permissions are:
* (T)runk: the agent is (or is on inwards path to) the global point of serialization.
* (B)ranch: the agent is on an outwards path to
* (N)one:
* These permissions are permuted by transfer operations in various ways.
* Operations can cap permissions, request for them to be grown or shrunk,
* or for a report on their current status.
*/
object TLPermissions
{
val aWidth = 2
val bdWidth = 2
val cWidth = 3
// Cap types (Grant = new permissions, Probe = permisions <= target)
def toT = 0.U(bdWidth.W)
def toB = 1.U(bdWidth.W)
def toN = 2.U(bdWidth.W)
def isCap(x: UInt) = x <= toN
// Grow types (Acquire = permissions >= target)
def NtoB = 0.U(aWidth.W)
def NtoT = 1.U(aWidth.W)
def BtoT = 2.U(aWidth.W)
def isGrow(x: UInt) = x <= BtoT
// Shrink types (ProbeAck, Release)
def TtoB = 0.U(cWidth.W)
def TtoN = 1.U(cWidth.W)
def BtoN = 2.U(cWidth.W)
def isShrink(x: UInt) = x <= BtoN
// Report types (ProbeAck, Release)
def TtoT = 3.U(cWidth.W)
def BtoB = 4.U(cWidth.W)
def NtoN = 5.U(cWidth.W)
def isReport(x: UInt) = x <= NtoN
def PermMsgGrow:Seq[String] = Seq("Grow NtoB", "Grow NtoT", "Grow BtoT")
def PermMsgCap:Seq[String] = Seq("Cap toT", "Cap toB", "Cap toN")
def PermMsgReport:Seq[String] = Seq("Shrink TtoB", "Shrink TtoN", "Shrink BtoN", "Report TotT", "Report BtoB", "Report NtoN")
def PermMsgReserved:Seq[String] = Seq("Reserved")
}
object TLAtomics
{
val width = 3
// Arithmetic types
def MIN = 0.U(width.W)
def MAX = 1.U(width.W)
def MINU = 2.U(width.W)
def MAXU = 3.U(width.W)
def ADD = 4.U(width.W)
def isArithmetic(x: UInt) = x <= ADD
// Logical types
def XOR = 0.U(width.W)
def OR = 1.U(width.W)
def AND = 2.U(width.W)
def SWAP = 3.U(width.W)
def isLogical(x: UInt) = x <= SWAP
def ArithMsg:Seq[String] = Seq("MIN", "MAX", "MINU", "MAXU", "ADD")
def LogicMsg:Seq[String] = Seq("XOR", "OR", "AND", "SWAP")
}
object TLHints
{
val width = 1
def PREFETCH_READ = 0.U(width.W)
def PREFETCH_WRITE = 1.U(width.W)
def isHints(x: UInt) = x <= PREFETCH_WRITE
def HintsMsg:Seq[String] = Seq("PrefetchRead", "PrefetchWrite")
}
sealed trait TLChannel extends TLBundleBase {
val channelName: String
}
sealed trait TLDataChannel extends TLChannel
sealed trait TLAddrChannel extends TLDataChannel
final class TLBundleA(params: TLBundleParameters)
extends TLBundleBase(params) with TLAddrChannel
{
override def typeName = s"TLBundleA_${params.shortName}"
val channelName = "'A' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(List(TLAtomics.width, TLPermissions.aWidth, TLHints.width).max.W) // amo_opcode || grow perms || hint
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // from
val address = UInt(params.addressBits.W) // to
val user = BundleMap(params.requestFields)
val echo = BundleMap(params.echoFields)
// variable fields during multibeat:
val mask = UInt((params.dataBits/8).W)
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleB(params: TLBundleParameters)
extends TLBundleBase(params) with TLAddrChannel
{
override def typeName = s"TLBundleB_${params.shortName}"
val channelName = "'B' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(TLPermissions.bdWidth.W) // cap perms
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // to
val address = UInt(params.addressBits.W) // from
// variable fields during multibeat:
val mask = UInt((params.dataBits/8).W)
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleC(params: TLBundleParameters)
extends TLBundleBase(params) with TLAddrChannel
{
override def typeName = s"TLBundleC_${params.shortName}"
val channelName = "'C' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(TLPermissions.cWidth.W) // shrink or report perms
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // from
val address = UInt(params.addressBits.W) // to
val user = BundleMap(params.requestFields)
val echo = BundleMap(params.echoFields)
// variable fields during multibeat:
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleD(params: TLBundleParameters)
extends TLBundleBase(params) with TLDataChannel
{
override def typeName = s"TLBundleD_${params.shortName}"
val channelName = "'D' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(TLPermissions.bdWidth.W) // cap perms
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // to
val sink = UInt(params.sinkBits.W) // from
val denied = Bool() // implies corrupt iff *Data
val user = BundleMap(params.responseFields)
val echo = BundleMap(params.echoFields)
// variable fields during multibeat:
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleE(params: TLBundleParameters)
extends TLBundleBase(params) with TLChannel
{
override def typeName = s"TLBundleE_${params.shortName}"
val channelName = "'E' channel"
val sink = UInt(params.sinkBits.W) // to
}
class TLBundle(val params: TLBundleParameters) extends Record
{
// Emulate a Bundle with elements abcde or ad depending on params.hasBCE
private val optA = Some (Decoupled(new TLBundleA(params)))
private val optB = params.hasBCE.option(Flipped(Decoupled(new TLBundleB(params))))
private val optC = params.hasBCE.option(Decoupled(new TLBundleC(params)))
private val optD = Some (Flipped(Decoupled(new TLBundleD(params))))
private val optE = params.hasBCE.option(Decoupled(new TLBundleE(params)))
def a: DecoupledIO[TLBundleA] = optA.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleA(params)))))
def b: DecoupledIO[TLBundleB] = optB.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleB(params)))))
def c: DecoupledIO[TLBundleC] = optC.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleC(params)))))
def d: DecoupledIO[TLBundleD] = optD.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleD(params)))))
def e: DecoupledIO[TLBundleE] = optE.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleE(params)))))
val elements =
if (params.hasBCE) ListMap("e" -> e, "d" -> d, "c" -> c, "b" -> b, "a" -> a)
else ListMap("d" -> d, "a" -> a)
def tieoff(): Unit = {
DataMirror.specifiedDirectionOf(a.ready) match {
case SpecifiedDirection.Input =>
a.ready := false.B
c.ready := false.B
e.ready := false.B
b.valid := false.B
d.valid := false.B
case SpecifiedDirection.Output =>
a.valid := false.B
c.valid := false.B
e.valid := false.B
b.ready := false.B
d.ready := false.B
case _ =>
}
}
}
object TLBundle
{
def apply(params: TLBundleParameters) = new TLBundle(params)
}
class TLAsyncBundleBase(val params: TLAsyncBundleParameters) extends Bundle
class TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params)
{
val a = new AsyncBundle(new TLBundleA(params.base), params.async)
val b = Flipped(new AsyncBundle(new TLBundleB(params.base), params.async))
val c = new AsyncBundle(new TLBundleC(params.base), params.async)
val d = Flipped(new AsyncBundle(new TLBundleD(params.base), params.async))
val e = new AsyncBundle(new TLBundleE(params.base), params.async)
}
class TLRationalBundle(params: TLBundleParameters) extends TLBundleBase(params)
{
val a = RationalIO(new TLBundleA(params))
val b = Flipped(RationalIO(new TLBundleB(params)))
val c = RationalIO(new TLBundleC(params))
val d = Flipped(RationalIO(new TLBundleD(params)))
val e = RationalIO(new TLBundleE(params))
}
class TLCreditedBundle(params: TLBundleParameters) extends TLBundleBase(params)
{
val a = CreditedIO(new TLBundleA(params))
val b = Flipped(CreditedIO(new TLBundleB(params)))
val c = CreditedIO(new TLBundleC(params))
val d = Flipped(CreditedIO(new TLBundleD(params)))
val e = CreditedIO(new TLBundleE(params))
}
File Parameters.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.diplomacy
import chisel3._
import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor}
import freechips.rocketchip.util.ShiftQueue
/** Options for describing the attributes of memory regions */
object RegionType {
// Define the 'more relaxed than' ordering
val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS)
sealed trait T extends Ordered[T] {
def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this)
}
case object CACHED extends T // an intermediate agent may have cached a copy of the region for you
case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided
case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible
case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached
case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects
case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed
case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively
}
// A non-empty half-open range; [start, end)
case class IdRange(start: Int, end: Int) extends Ordered[IdRange]
{
require (start >= 0, s"Ids cannot be negative, but got: $start.")
require (start <= end, "Id ranges cannot be negative.")
def compare(x: IdRange) = {
val primary = (this.start - x.start).signum
val secondary = (x.end - this.end).signum
if (primary != 0) primary else secondary
}
def overlaps(x: IdRange) = start < x.end && x.start < end
def contains(x: IdRange) = start <= x.start && x.end <= end
def contains(x: Int) = start <= x && x < end
def contains(x: UInt) =
if (size == 0) {
false.B
} else if (size == 1) { // simple comparison
x === start.U
} else {
// find index of largest different bit
val largestDeltaBit = log2Floor(start ^ (end-1))
val smallestCommonBit = largestDeltaBit + 1 // may not exist in x
val uncommonMask = (1 << smallestCommonBit) - 1
val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0)
// the prefix must match exactly (note: may shift ALL bits away)
(x >> smallestCommonBit) === (start >> smallestCommonBit).U &&
// firrtl constant prop range analysis can eliminate these two:
(start & uncommonMask).U <= uncommonBits &&
uncommonBits <= ((end-1) & uncommonMask).U
}
def shift(x: Int) = IdRange(start+x, end+x)
def size = end - start
def isEmpty = end == start
def range = start until end
}
object IdRange
{
def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else {
val ranges = s.sorted
(ranges.tail zip ranges.init) find { case (a, b) => a overlaps b }
}
}
// An potentially empty inclusive range of 2-powers [min, max] (in bytes)
case class TransferSizes(min: Int, max: Int)
{
def this(x: Int) = this(x, x)
require (min <= max, s"Min transfer $min > max transfer $max")
require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)")
require (max == 0 || isPow2(max), s"TransferSizes must be a power of 2, got: $max")
require (min == 0 || isPow2(min), s"TransferSizes must be a power of 2, got: $min")
require (max == 0 || min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)")
def none = min == 0
def contains(x: Int) = isPow2(x) && min <= x && x <= max
def containsLg(x: Int) = contains(1 << x)
def containsLg(x: UInt) =
if (none) false.B
else if (min == max) { log2Ceil(min).U === x }
else { log2Ceil(min).U <= x && x <= log2Ceil(max).U }
def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max)
def intersect(x: TransferSizes) =
if (x.max < min || max < x.min) TransferSizes.none
else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max))
// Not a union, because the result may contain sizes contained by neither term
// NOT TO BE CONFUSED WITH COVERPOINTS
def mincover(x: TransferSizes) = {
if (none) {
x
} else if (x.none) {
this
} else {
TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max))
}
}
override def toString() = "TransferSizes[%d, %d]".format(min, max)
}
object TransferSizes {
def apply(x: Int) = new TransferSizes(x)
val none = new TransferSizes(0)
def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _)
def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _)
implicit def asBool(x: TransferSizes) = !x.none
}
// AddressSets specify the address space managed by the manager
// Base is the base address, and mask are the bits consumed by the manager
// e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff
// e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ...
case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet]
{
// Forbid misaligned base address (and empty sets)
require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}")
require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous
// We do allow negative mask (=> ignore all high bits)
def contains(x: BigInt) = ((x ^ base) & ~mask) == 0
def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S
// turn x into an address contained in this set
def legalize(x: UInt): UInt = base.U | (mask.U & x)
// overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1)
def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0
// contains iff bitwise: x.mask => mask && contains(x.base)
def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0
// The number of bytes to which the manager must be aligned
def alignment = ((mask + 1) & ~mask)
// Is this a contiguous memory range
def contiguous = alignment == mask+1
def finite = mask >= 0
def max = { require (finite, "Max cannot be calculated on infinite mask"); base | mask }
// Widen the match function to ignore all bits in imask
def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask)
// Return an AddressSet that only contains the addresses both sets contain
def intersect(x: AddressSet): Option[AddressSet] = {
if (!overlaps(x)) {
None
} else {
val r_mask = mask & x.mask
val r_base = base | x.base
Some(AddressSet(r_base, r_mask))
}
}
def subtract(x: AddressSet): Seq[AddressSet] = {
intersect(x) match {
case None => Seq(this)
case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit =>
val nmask = (mask & (bit-1)) | remove.mask
val nbase = (remove.base ^ bit) & ~nmask
AddressSet(nbase, nmask)
}
}
}
// AddressSets have one natural Ordering (the containment order, if contiguous)
def compare(x: AddressSet) = {
val primary = (this.base - x.base).signum // smallest address first
val secondary = (x.mask - this.mask).signum // largest mask first
if (primary != 0) primary else secondary
}
// We always want to see things in hex
override def toString() = {
if (mask >= 0) {
"AddressSet(0x%x, 0x%x)".format(base, mask)
} else {
"AddressSet(0x%x, ~0x%x)".format(base, ~mask)
}
}
def toRanges = {
require (finite, "Ranges cannot be calculated on infinite mask")
val size = alignment
val fragments = mask & ~(size-1)
val bits = bitIndexes(fragments)
(BigInt(0) until (BigInt(1) << bits.size)).map { i =>
val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) }
AddressRange(off, size)
}
}
}
object AddressSet
{
val everything = AddressSet(0, -1)
def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = {
if (size == 0) tail.reverse else {
val maxBaseAlignment = base & (-base) // 0 for infinite (LSB)
val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size
val step =
if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment)
maxSizeAlignment else maxBaseAlignment
misaligned(base+step, size-step, AddressSet(base, step-1) +: tail)
}
}
def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = {
// Pair terms up by ignoring 'bit'
seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) =>
if (seq.size == 1) {
seq.head // singleton -> unaffected
} else {
key.copy(mask = key.mask | bit) // pair - widen mask by bit
}
}.toList
}
def unify(seq: Seq[AddressSet]): Seq[AddressSet] = {
val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _)
AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted
}
def enumerateMask(mask: BigInt): Seq[BigInt] = {
def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] =
if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail)
helper(0, Nil)
}
def enumerateBits(mask: BigInt): Seq[BigInt] = {
def helper(x: BigInt): Seq[BigInt] = {
if (x == 0) {
Nil
} else {
val bit = x & (-x)
bit +: helper(x & ~bit)
}
}
helper(mask)
}
}
case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean)
{
require (depth >= 0, "Buffer depth must be >= 0")
def isDefined = depth > 0
def latency = if (isDefined && !flow) 1 else 0
def apply[T <: Data](x: DecoupledIO[T]) =
if (isDefined) Queue(x, depth, flow=flow, pipe=pipe)
else x
def irrevocable[T <: Data](x: ReadyValidIO[T]) =
if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe)
else x
def sq[T <: Data](x: DecoupledIO[T]) =
if (!isDefined) x else {
val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe))
sq.io.enq <> x
sq.io.deq
}
override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "")
}
object BufferParams
{
implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false)
val default = BufferParams(2)
val none = BufferParams(0)
val flow = BufferParams(1, true, false)
val pipe = BufferParams(1, false, true)
}
case class TriStateValue(value: Boolean, set: Boolean)
{
def update(orig: Boolean) = if (set) value else orig
}
object TriStateValue
{
implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true)
def unset = TriStateValue(false, false)
}
trait DirectedBuffers[T] {
def copyIn(x: BufferParams): T
def copyOut(x: BufferParams): T
def copyInOut(x: BufferParams): T
}
trait IdMapEntry {
def name: String
def from: IdRange
def to: IdRange
def isCache: Boolean
def requestFifo: Boolean
def maxTransactionsInFlight: Option[Int]
def pretty(fmt: String) =
if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5
fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "")
} else {
fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "")
}
}
abstract class IdMap[T <: IdMapEntry] {
protected val fmt: String
val mapping: Seq[T]
def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n")
}
File Edges.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.util._
class TLEdge(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdgeParameters(client, manager, params, sourceInfo)
{
def isAligned(address: UInt, lgSize: UInt): Bool = {
if (maxLgSize == 0) true.B else {
val mask = UIntToOH1(lgSize, maxLgSize)
(address & mask) === 0.U
}
}
def mask(address: UInt, lgSize: UInt): UInt =
MaskGen(address, lgSize, manager.beatBytes)
def staticHasData(bundle: TLChannel): Option[Boolean] = {
bundle match {
case _:TLBundleA => {
// Do there exist A messages with Data?
val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial
// Do there exist A messages without Data?
val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint
// Statically optimize the case where hasData is a constant
if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None
}
case _:TLBundleB => {
// Do there exist B messages with Data?
val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial
// Do there exist B messages without Data?
val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint
// Statically optimize the case where hasData is a constant
if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None
}
case _:TLBundleC => {
// Do there eixst C messages with Data?
val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe
// Do there exist C messages without Data?
val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe
if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None
}
case _:TLBundleD => {
// Do there eixst D messages with Data?
val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB
// Do there exist D messages without Data?
val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT
if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None
}
case _:TLBundleE => Some(false)
}
}
def isRequest(x: TLChannel): Bool = {
x match {
case a: TLBundleA => true.B
case b: TLBundleB => true.B
case c: TLBundleC => c.opcode(2) && c.opcode(1)
// opcode === TLMessages.Release ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(2) && !d.opcode(1)
// opcode === TLMessages.Grant ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
}
def isResponse(x: TLChannel): Bool = {
x match {
case a: TLBundleA => false.B
case b: TLBundleB => false.B
case c: TLBundleC => !c.opcode(2) || !c.opcode(1)
// opcode =/= TLMessages.Release &&
// opcode =/= TLMessages.ReleaseData
case d: TLBundleD => true.B // Grant isResponse + isRequest
case e: TLBundleE => true.B
}
}
def hasData(x: TLChannel): Bool = {
val opdata = x match {
case a: TLBundleA => !a.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case b: TLBundleB => !b.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case c: TLBundleC => c.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.ProbeAckData ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
staticHasData(x).map(_.B).getOrElse(opdata)
}
def opcode(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.opcode
case b: TLBundleB => b.opcode
case c: TLBundleC => c.opcode
case d: TLBundleD => d.opcode
}
}
def param(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.param
case b: TLBundleB => b.param
case c: TLBundleC => c.param
case d: TLBundleD => d.param
}
}
def size(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.size
case b: TLBundleB => b.size
case c: TLBundleC => c.size
case d: TLBundleD => d.size
}
}
def data(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.data
case b: TLBundleB => b.data
case c: TLBundleC => c.data
case d: TLBundleD => d.data
}
}
def corrupt(x: TLDataChannel): Bool = {
x match {
case a: TLBundleA => a.corrupt
case b: TLBundleB => b.corrupt
case c: TLBundleC => c.corrupt
case d: TLBundleD => d.corrupt
}
}
def mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.mask
case b: TLBundleB => b.mask
case c: TLBundleC => mask(c.address, c.size)
}
}
def full_mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => mask(a.address, a.size)
case b: TLBundleB => mask(b.address, b.size)
case c: TLBundleC => mask(c.address, c.size)
}
}
def address(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.address
case b: TLBundleB => b.address
case c: TLBundleC => c.address
}
}
def source(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.source
case b: TLBundleB => b.source
case c: TLBundleC => c.source
case d: TLBundleD => d.source
}
}
def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes)
def addr_lo(x: UInt): UInt =
if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0)
def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x))
def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x))
def numBeats(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 1.U
case bundle: TLDataChannel => {
val hasData = this.hasData(bundle)
val size = this.size(bundle)
val cutoff = log2Ceil(manager.beatBytes)
val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U
val decode = UIntToOH(size, maxLgSize+1) >> cutoff
Mux(hasData, decode | small.asUInt, 1.U)
}
}
}
def numBeats1(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 0.U
case bundle: TLDataChannel => {
if (maxLgSize == 0) {
0.U
} else {
val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes)
Mux(hasData(bundle), decode, 0.U)
}
}
}
}
def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val beats1 = numBeats1(bits)
val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W))
val counter1 = counter - 1.U
val first = counter === 0.U
val last = counter === 1.U || beats1 === 0.U
val done = last && fire
val count = (beats1 & ~counter1)
when (fire) {
counter := Mux(first, beats1, counter1)
}
(first, last, done, count)
}
def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1
def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire)
def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid)
def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2
def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire)
def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid)
def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3
def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire)
def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid)
def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3)
}
def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire)
def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid)
def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4)
}
def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire)
def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid)
def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes))
}
def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire)
def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid)
// Does the request need T permissions to be executed?
def needT(a: TLBundleA): Bool = {
val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLPermissions.NtoB -> false.B,
TLPermissions.NtoT -> true.B,
TLPermissions.BtoT -> true.B))
MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array(
TLMessages.PutFullData -> true.B,
TLMessages.PutPartialData -> true.B,
TLMessages.ArithmeticData -> true.B,
TLMessages.LogicalData -> true.B,
TLMessages.Get -> false.B,
TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLHints.PREFETCH_READ -> false.B,
TLHints.PREFETCH_WRITE -> true.B)),
TLMessages.AcquireBlock -> acq_needT,
TLMessages.AcquirePerm -> acq_needT))
}
// This is a very expensive circuit; use only if you really mean it!
def inFlight(x: TLBundle): (UInt, UInt) = {
val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W))
val bce = manager.anySupportAcquireB && client.anySupportProbe
val (a_first, a_last, _) = firstlast(x.a)
val (b_first, b_last, _) = firstlast(x.b)
val (c_first, c_last, _) = firstlast(x.c)
val (d_first, d_last, _) = firstlast(x.d)
val (e_first, e_last, _) = firstlast(x.e)
val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits))
val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits))
val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits))
val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits))
val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits))
val a_inc = x.a.fire && a_first && a_request
val b_inc = x.b.fire && b_first && b_request
val c_inc = x.c.fire && c_first && c_request
val d_inc = x.d.fire && d_first && d_request
val e_inc = x.e.fire && e_first && e_request
val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil))
val a_dec = x.a.fire && a_last && a_response
val b_dec = x.b.fire && b_last && b_response
val c_dec = x.c.fire && c_last && c_response
val d_dec = x.d.fire && d_last && d_response
val e_dec = x.e.fire && e_last && e_response
val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil))
val next_flight = flight + PopCount(inc) - PopCount(dec)
flight := next_flight
(flight, next_flight)
}
def prettySourceMapping(context: String): String = {
s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n"
}
}
class TLEdgeOut(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
// Transfers
def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquireBlock
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquirePerm
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.Release
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ReleaseData
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) =
Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B)
def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAck
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions, data)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAckData
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B)
def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink)
def GrantAck(toSink: UInt): TLBundleE = {
val e = Wire(new TLBundleE(bundle))
e.sink := toSink
e
}
// Accesses
def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsGetFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Get
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutFullFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutFullData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, mask, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutPartialFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutPartialData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = {
require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsArithmeticFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.ArithmeticData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsLogicalFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.LogicalData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = {
require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsHintFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Hint
a.param := param
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data)
def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAckData
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size)
def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.HintAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
}
class TLEdgeIn(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = {
val todo = x.filter(!_.isEmpty)
val heads = todo.map(_.head)
val tails = todo.map(_.tail)
if (todo.isEmpty) Nil else { heads +: myTranspose(tails) }
}
// Transfers
def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = {
require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}")
val legal = client.supportsProbe(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Probe
b.param := capPermissions
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.Grant
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.GrantData
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B)
def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.ReleaseAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
// Accesses
def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = {
require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsGet(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Get
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsPutFull(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutFullData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, mask, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsPutPartial(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutPartialData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsArithmetic(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.ArithmeticData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsLogical(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.LogicalData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = {
require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsHint(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Hint
b.param := param
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size)
def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied)
def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data)
def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAckData
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B)
def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied)
def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B)
def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.HintAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
}
| module TLMonitor_2( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14]
input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input [5:0] io_in_a_bits_source, // @[Monitor.scala:20:14]
input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input io_in_a_bits_user_amba_prot_bufferable, // @[Monitor.scala:20:14]
input io_in_a_bits_user_amba_prot_modifiable, // @[Monitor.scala:20:14]
input io_in_a_bits_user_amba_prot_readalloc, // @[Monitor.scala:20:14]
input io_in_a_bits_user_amba_prot_writealloc, // @[Monitor.scala:20:14]
input io_in_a_bits_user_amba_prot_privileged, // @[Monitor.scala:20:14]
input io_in_a_bits_user_amba_prot_secure, // @[Monitor.scala:20:14]
input io_in_a_bits_user_amba_prot_fetch, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14]
input io_in_a_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14]
input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input [5:0] io_in_d_bits_source, // @[Monitor.scala:20:14]
input io_in_d_bits_sink, // @[Monitor.scala:20:14]
input io_in_d_bits_denied, // @[Monitor.scala:20:14]
input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14]
input io_in_d_bits_corrupt // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7]
wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7]
wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7]
wire [5:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7]
wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7]
wire io_in_a_bits_user_amba_prot_bufferable_0 = io_in_a_bits_user_amba_prot_bufferable; // @[Monitor.scala:36:7]
wire io_in_a_bits_user_amba_prot_modifiable_0 = io_in_a_bits_user_amba_prot_modifiable; // @[Monitor.scala:36:7]
wire io_in_a_bits_user_amba_prot_readalloc_0 = io_in_a_bits_user_amba_prot_readalloc; // @[Monitor.scala:36:7]
wire io_in_a_bits_user_amba_prot_writealloc_0 = io_in_a_bits_user_amba_prot_writealloc; // @[Monitor.scala:36:7]
wire io_in_a_bits_user_amba_prot_privileged_0 = io_in_a_bits_user_amba_prot_privileged; // @[Monitor.scala:36:7]
wire io_in_a_bits_user_amba_prot_secure_0 = io_in_a_bits_user_amba_prot_secure; // @[Monitor.scala:36:7]
wire io_in_a_bits_user_amba_prot_fetch_0 = io_in_a_bits_user_amba_prot_fetch; // @[Monitor.scala:36:7]
wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7]
wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7]
wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7]
wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7]
wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7]
wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7]
wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7]
wire [5:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7]
wire io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7]
wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7]
wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7]
wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7]
wire sink_ok = 1'h0; // @[Monitor.scala:309:31]
wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_bits_user_amba_prot_bufferable = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_bits_user_amba_prot_modifiable = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_bits_user_amba_prot_readalloc = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_bits_user_amba_prot_writealloc = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_bits_user_amba_prot_privileged = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_bits_user_amba_prot_secure = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_bits_user_amba_prot_fetch = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_bits_user_amba_prot_bufferable = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_bits_user_amba_prot_modifiable = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_bits_user_amba_prot_readalloc = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_bits_user_amba_prot_writealloc = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_bits_user_amba_prot_privileged = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_bits_user_amba_prot_secure = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_bits_user_amba_prot_fetch = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_bits_user_amba_prot_bufferable = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_bits_user_amba_prot_modifiable = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_bits_user_amba_prot_readalloc = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_bits_user_amba_prot_writealloc = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_bits_user_amba_prot_privileged = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_bits_user_amba_prot_secure = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_bits_user_amba_prot_fetch = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_bits_user_amba_prot_bufferable = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_bits_user_amba_prot_modifiable = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_bits_user_amba_prot_readalloc = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_bits_user_amba_prot_writealloc = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_bits_user_amba_prot_privileged = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_bits_user_amba_prot_secure = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_bits_user_amba_prot_fetch = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35]
wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36]
wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25]
wire c_first_done = 1'h0; // @[Edges.scala:233:22]
wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_bits_user_amba_prot_bufferable = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_bits_user_amba_prot_modifiable = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_bits_user_amba_prot_readalloc = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_bits_user_amba_prot_writealloc = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_bits_user_amba_prot_privileged = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_bits_user_amba_prot_secure = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_bits_user_amba_prot_fetch = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_bits_user_amba_prot_bufferable = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_bits_user_amba_prot_modifiable = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_bits_user_amba_prot_readalloc = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_bits_user_amba_prot_writealloc = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_bits_user_amba_prot_privileged = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_bits_user_amba_prot_secure = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_bits_user_amba_prot_fetch = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_bits_user_amba_prot_bufferable = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_bits_user_amba_prot_modifiable = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_bits_user_amba_prot_readalloc = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_bits_user_amba_prot_writealloc = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_bits_user_amba_prot_privileged = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_bits_user_amba_prot_secure = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_bits_user_amba_prot_fetch = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_bits_user_amba_prot_bufferable = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_bits_user_amba_prot_modifiable = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_bits_user_amba_prot_readalloc = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_bits_user_amba_prot_writealloc = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_bits_user_amba_prot_privileged = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_bits_user_amba_prot_secure = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_bits_user_amba_prot_fetch = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_bits_user_amba_prot_bufferable = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_bits_user_amba_prot_modifiable = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_bits_user_amba_prot_readalloc = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_bits_user_amba_prot_writealloc = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_bits_user_amba_prot_privileged = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_bits_user_amba_prot_secure = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_bits_user_amba_prot_fetch = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_bits_user_amba_prot_bufferable = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_bits_user_amba_prot_modifiable = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_bits_user_amba_prot_readalloc = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_bits_user_amba_prot_writealloc = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_bits_user_amba_prot_privileged = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_bits_user_amba_prot_secure = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_bits_user_amba_prot_fetch = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_bits_user_amba_prot_bufferable = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_bits_user_amba_prot_modifiable = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_bits_user_amba_prot_readalloc = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_bits_user_amba_prot_writealloc = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_bits_user_amba_prot_privileged = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_bits_user_amba_prot_secure = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_bits_user_amba_prot_fetch = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_bits_user_amba_prot_bufferable = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_bits_user_amba_prot_modifiable = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_bits_user_amba_prot_readalloc = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_bits_user_amba_prot_writealloc = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_bits_user_amba_prot_privileged = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_bits_user_amba_prot_secure = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_bits_user_amba_prot_fetch = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_bits_user_amba_prot_bufferable = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_bits_user_amba_prot_modifiable = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_bits_user_amba_prot_readalloc = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_bits_user_amba_prot_writealloc = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_bits_user_amba_prot_privileged = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_bits_user_amba_prot_secure = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_bits_user_amba_prot_fetch = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_bits_user_amba_prot_bufferable = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_bits_user_amba_prot_modifiable = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_bits_user_amba_prot_readalloc = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_bits_user_amba_prot_writealloc = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_bits_user_amba_prot_privileged = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_bits_user_amba_prot_secure = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_bits_user_amba_prot_fetch = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_bits_user_amba_prot_bufferable = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_bits_user_amba_prot_modifiable = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_bits_user_amba_prot_readalloc = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_bits_user_amba_prot_writealloc = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_bits_user_amba_prot_privileged = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_bits_user_amba_prot_secure = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_bits_user_amba_prot_fetch = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_bits_user_amba_prot_bufferable = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_bits_user_amba_prot_modifiable = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_bits_user_amba_prot_readalloc = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_bits_user_amba_prot_writealloc = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_bits_user_amba_prot_privileged = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_bits_user_amba_prot_secure = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_bits_user_amba_prot_fetch = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_bits_user_amba_prot_bufferable = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_bits_user_amba_prot_modifiable = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_bits_user_amba_prot_readalloc = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_bits_user_amba_prot_writealloc = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_bits_user_amba_prot_privileged = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_bits_user_amba_prot_secure = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_bits_user_amba_prot_fetch = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_bits_user_amba_prot_bufferable = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_bits_user_amba_prot_modifiable = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_bits_user_amba_prot_readalloc = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_bits_user_amba_prot_writealloc = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_bits_user_amba_prot_privileged = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_bits_user_amba_prot_secure = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_bits_user_amba_prot_fetch = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47]
wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_bits_user_amba_prot_bufferable = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_bits_user_amba_prot_modifiable = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_bits_user_amba_prot_readalloc = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_bits_user_amba_prot_writealloc = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_bits_user_amba_prot_privileged = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_bits_user_amba_prot_secure = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_bits_user_amba_prot_fetch = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_bits_user_amba_prot_bufferable = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_bits_user_amba_prot_modifiable = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_bits_user_amba_prot_readalloc = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_bits_user_amba_prot_writealloc = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_bits_user_amba_prot_privileged = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_bits_user_amba_prot_secure = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_bits_user_amba_prot_fetch = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95]
wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71]
wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_bits_user_amba_prot_bufferable = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_bits_user_amba_prot_modifiable = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_bits_user_amba_prot_readalloc = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_bits_user_amba_prot_writealloc = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_bits_user_amba_prot_privileged = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_bits_user_amba_prot_secure = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_bits_user_amba_prot_fetch = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_bits_user_amba_prot_bufferable = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_bits_user_amba_prot_modifiable = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_bits_user_amba_prot_readalloc = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_bits_user_amba_prot_writealloc = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_bits_user_amba_prot_privileged = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_bits_user_amba_prot_secure = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_bits_user_amba_prot_fetch = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44]
wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_bits_user_amba_prot_bufferable = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_bits_user_amba_prot_modifiable = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_bits_user_amba_prot_readalloc = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_bits_user_amba_prot_writealloc = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_bits_user_amba_prot_privileged = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_bits_user_amba_prot_secure = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_bits_user_amba_prot_fetch = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_bits_user_amba_prot_bufferable = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_bits_user_amba_prot_modifiable = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_bits_user_amba_prot_readalloc = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_bits_user_amba_prot_writealloc = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_bits_user_amba_prot_privileged = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_bits_user_amba_prot_secure = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_bits_user_amba_prot_fetch = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36]
wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51]
wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40]
wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55]
wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_bits_user_amba_prot_bufferable = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_bits_user_amba_prot_modifiable = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_bits_user_amba_prot_readalloc = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_bits_user_amba_prot_writealloc = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_bits_user_amba_prot_privileged = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_bits_user_amba_prot_secure = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_bits_user_amba_prot_fetch = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_bits_user_amba_prot_bufferable = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_bits_user_amba_prot_modifiable = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_bits_user_amba_prot_readalloc = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_bits_user_amba_prot_writealloc = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_bits_user_amba_prot_privileged = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_bits_user_amba_prot_secure = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_bits_user_amba_prot_fetch = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88]
wire [8:0] c_first_beats1_decode = 9'h0; // @[Edges.scala:220:59]
wire [8:0] c_first_beats1 = 9'h0; // @[Edges.scala:221:14]
wire [8:0] _c_first_count_T = 9'h0; // @[Edges.scala:234:27]
wire [8:0] c_first_count = 9'h0; // @[Edges.scala:234:25]
wire [8:0] _c_first_counter_T = 9'h0; // @[Edges.scala:236:21]
wire [8:0] _c_opcodes_set_T = 9'h0; // @[Monitor.scala:767:79]
wire [8:0] _c_sizes_set_T = 9'h0; // @[Monitor.scala:768:77]
wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_17 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_21 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_23 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_27 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_29 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_33 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_35 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_45 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_47 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_51 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_53 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_57 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_59 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_63 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_65 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_69 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_71 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_75 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_77 = 1'h1; // @[Parameters.scala:57:20]
wire c_first = 1'h1; // @[Edges.scala:231:25]
wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire c_first_last = 1'h1; // @[Edges.scala:232:33]
wire [8:0] c_first_counter1 = 9'h1FF; // @[Edges.scala:230:28]
wire [9:0] _c_first_counter1_T = 10'h3FF; // @[Edges.scala:230:28]
wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_first_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_first_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_first_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_first_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_set_wo_ready_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_set_wo_ready_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_opcodes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_opcodes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_sizes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_sizes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_opcodes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_opcodes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_sizes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_sizes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_probe_ack_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_probe_ack_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_probe_ack_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_probe_ack_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _same_cycle_resp_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _same_cycle_resp_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _same_cycle_resp_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _same_cycle_resp_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _same_cycle_resp_WIRE_4_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _same_cycle_resp_WIRE_5_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [5:0] _c_first_WIRE_bits_source = 6'h0; // @[Bundles.scala:265:74]
wire [5:0] _c_first_WIRE_1_bits_source = 6'h0; // @[Bundles.scala:265:61]
wire [5:0] _c_first_WIRE_2_bits_source = 6'h0; // @[Bundles.scala:265:74]
wire [5:0] _c_first_WIRE_3_bits_source = 6'h0; // @[Bundles.scala:265:61]
wire [5:0] _c_set_wo_ready_WIRE_bits_source = 6'h0; // @[Bundles.scala:265:74]
wire [5:0] _c_set_wo_ready_WIRE_1_bits_source = 6'h0; // @[Bundles.scala:265:61]
wire [5:0] _c_set_WIRE_bits_source = 6'h0; // @[Bundles.scala:265:74]
wire [5:0] _c_set_WIRE_1_bits_source = 6'h0; // @[Bundles.scala:265:61]
wire [5:0] _c_opcodes_set_interm_WIRE_bits_source = 6'h0; // @[Bundles.scala:265:74]
wire [5:0] _c_opcodes_set_interm_WIRE_1_bits_source = 6'h0; // @[Bundles.scala:265:61]
wire [5:0] _c_sizes_set_interm_WIRE_bits_source = 6'h0; // @[Bundles.scala:265:74]
wire [5:0] _c_sizes_set_interm_WIRE_1_bits_source = 6'h0; // @[Bundles.scala:265:61]
wire [5:0] _c_opcodes_set_WIRE_bits_source = 6'h0; // @[Bundles.scala:265:74]
wire [5:0] _c_opcodes_set_WIRE_1_bits_source = 6'h0; // @[Bundles.scala:265:61]
wire [5:0] _c_sizes_set_WIRE_bits_source = 6'h0; // @[Bundles.scala:265:74]
wire [5:0] _c_sizes_set_WIRE_1_bits_source = 6'h0; // @[Bundles.scala:265:61]
wire [5:0] _c_probe_ack_WIRE_bits_source = 6'h0; // @[Bundles.scala:265:74]
wire [5:0] _c_probe_ack_WIRE_1_bits_source = 6'h0; // @[Bundles.scala:265:61]
wire [5:0] _c_probe_ack_WIRE_2_bits_source = 6'h0; // @[Bundles.scala:265:74]
wire [5:0] _c_probe_ack_WIRE_3_bits_source = 6'h0; // @[Bundles.scala:265:61]
wire [5:0] _same_cycle_resp_WIRE_bits_source = 6'h0; // @[Bundles.scala:265:74]
wire [5:0] _same_cycle_resp_WIRE_1_bits_source = 6'h0; // @[Bundles.scala:265:61]
wire [5:0] _same_cycle_resp_WIRE_2_bits_source = 6'h0; // @[Bundles.scala:265:74]
wire [5:0] _same_cycle_resp_WIRE_3_bits_source = 6'h0; // @[Bundles.scala:265:61]
wire [5:0] _same_cycle_resp_WIRE_4_bits_source = 6'h0; // @[Bundles.scala:265:74]
wire [5:0] _same_cycle_resp_WIRE_5_bits_source = 6'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_first_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_first_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_first_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_first_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40]
wire [3:0] _c_set_wo_ready_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_set_wo_ready_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53]
wire [3:0] _c_sizes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_sizes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_opcodes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_sizes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_sizes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_probe_ack_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_probe_ack_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_probe_ack_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_probe_ack_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_4_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_5_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57]
wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57]
wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57]
wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57]
wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57]
wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57]
wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57]
wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57]
wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51]
wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51]
wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51]
wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51]
wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [515:0] _c_sizes_set_T_1 = 516'h0; // @[Monitor.scala:768:52]
wire [514:0] _c_opcodes_set_T_1 = 515'h0; // @[Monitor.scala:767:54]
wire [4:0] _c_sizes_set_interm_T_1 = 5'h1; // @[Monitor.scala:766:59]
wire [4:0] c_sizes_set_interm = 5'h0; // @[Monitor.scala:755:40]
wire [4:0] _c_sizes_set_interm_T = 5'h0; // @[Monitor.scala:766:51]
wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61]
wire [63:0] _c_set_wo_ready_T = 64'h1; // @[OneHot.scala:58:35]
wire [63:0] _c_set_T = 64'h1; // @[OneHot.scala:58:35]
wire [263:0] c_sizes_set = 264'h0; // @[Monitor.scala:741:34]
wire [131:0] c_opcodes_set = 132'h0; // @[Monitor.scala:740:34]
wire [32:0] c_set = 33'h0; // @[Monitor.scala:738:34]
wire [32:0] c_set_wo_ready = 33'h0; // @[Monitor.scala:739:34]
wire [11:0] _c_first_beats1_decode_T_2 = 12'h0; // @[package.scala:243:46]
wire [11:0] _c_first_beats1_decode_T_1 = 12'hFFF; // @[package.scala:243:76]
wire [26:0] _c_first_beats1_decode_T = 27'hFFF; // @[package.scala:243:71]
wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42]
wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42]
wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42]
wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123]
wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48]
wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123]
wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48]
wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117]
wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48]
wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119]
wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48]
wire [3:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34]
wire [5:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _source_ok_uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _source_ok_uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_36 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_37 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_38 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_39 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_40 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_41 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_42 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_43 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_44 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_45 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_46 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_47 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_48 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_49 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_50 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_51 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_52 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_53 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _source_ok_uncommonBits_T_6 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _source_ok_uncommonBits_T_7 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _source_ok_uncommonBits_T_8 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _source_ok_uncommonBits_T_9 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _source_ok_uncommonBits_T_10 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _source_ok_uncommonBits_T_11 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire _source_ok_T = io_in_a_bits_source_0 == 6'h20; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31]
wire [2:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] _source_ok_T_1 = io_in_a_bits_source_0[5:3]; // @[Monitor.scala:36:7]
wire [2:0] _source_ok_T_7 = io_in_a_bits_source_0[5:3]; // @[Monitor.scala:36:7]
wire _source_ok_T_2 = _source_ok_T_1 == 3'h2; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_4 = _source_ok_T_2; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_6 = _source_ok_T_4; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31]
wire [2:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[2:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_8 = _source_ok_T_7 == 3'h3; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_10 = _source_ok_T_8; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_12 = _source_ok_T_10; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_2 = _source_ok_T_12; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] _source_ok_T_13 = io_in_a_bits_source_0[5:2]; // @[Monitor.scala:36:7]
wire [3:0] _source_ok_T_19 = io_in_a_bits_source_0[5:2]; // @[Monitor.scala:36:7]
wire [3:0] _source_ok_T_25 = io_in_a_bits_source_0[5:2]; // @[Monitor.scala:36:7]
wire [3:0] _source_ok_T_31 = io_in_a_bits_source_0[5:2]; // @[Monitor.scala:36:7]
wire _source_ok_T_14 = _source_ok_T_13 == 4'h0; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_16 = _source_ok_T_14; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_18 = _source_ok_T_16; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_3 = _source_ok_T_18; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_20 = _source_ok_T_19 == 4'h1; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_22 = _source_ok_T_20; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_24 = _source_ok_T_22; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_4 = _source_ok_T_24; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_26 = _source_ok_T_25 == 4'h2; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_28 = _source_ok_T_26; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_30 = _source_ok_T_28; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_5 = _source_ok_T_30; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_32 = _source_ok_T_31 == 4'h3; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_34 = _source_ok_T_32; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_36 = _source_ok_T_34; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_6 = _source_ok_T_36; // @[Parameters.scala:1138:31]
wire _source_ok_T_37 = _source_ok_WIRE_0 | _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_38 = _source_ok_T_37 | _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_39 = _source_ok_T_38 | _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_40 = _source_ok_T_39 | _source_ok_WIRE_4; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_41 = _source_ok_T_40 | _source_ok_WIRE_5; // @[Parameters.scala:1138:31, :1139:46]
wire source_ok = _source_ok_T_41 | _source_ok_WIRE_6; // @[Parameters.scala:1138:31, :1139:46]
wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71]
wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71]
assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71]
wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71]
assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71]
wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71]
wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}]
wire [31:0] _is_aligned_T = {20'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46]
wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}]
wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12]
wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}]
wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27]
wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 4'h2; // @[Misc.scala:206:21]
wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26]
wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}]
wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}]
wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26]
wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26]
wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26]
wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20]
wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}]
wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}]
wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}]
wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}]
wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10]
wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10]
wire [2:0] uncommonBits = _uncommonBits_T[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_1 = _uncommonBits_T_1[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_4 = _uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_5 = _uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_6 = _uncommonBits_T_6[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_7 = _uncommonBits_T_7[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_9 = _uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_10 = _uncommonBits_T_10[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_11 = _uncommonBits_T_11[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_12 = _uncommonBits_T_12[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_13 = _uncommonBits_T_13[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_14 = _uncommonBits_T_14[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_16 = _uncommonBits_T_16[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_17 = _uncommonBits_T_17[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_18 = _uncommonBits_T_18[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_19 = _uncommonBits_T_19[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_20 = _uncommonBits_T_20[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_21 = _uncommonBits_T_21[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_22 = _uncommonBits_T_22[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_23 = _uncommonBits_T_23[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_24 = _uncommonBits_T_24[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_25 = _uncommonBits_T_25[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_26 = _uncommonBits_T_26[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_27 = _uncommonBits_T_27[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_28 = _uncommonBits_T_28[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_29 = _uncommonBits_T_29[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_30 = _uncommonBits_T_30[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_31 = _uncommonBits_T_31[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_32 = _uncommonBits_T_32[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_33 = _uncommonBits_T_33[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_34 = _uncommonBits_T_34[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_35 = _uncommonBits_T_35[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_36 = _uncommonBits_T_36[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_37 = _uncommonBits_T_37[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_38 = _uncommonBits_T_38[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_39 = _uncommonBits_T_39[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_40 = _uncommonBits_T_40[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_41 = _uncommonBits_T_41[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_42 = _uncommonBits_T_42[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_43 = _uncommonBits_T_43[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_44 = _uncommonBits_T_44[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_45 = _uncommonBits_T_45[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_46 = _uncommonBits_T_46[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_47 = _uncommonBits_T_47[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_48 = _uncommonBits_T_48[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_49 = _uncommonBits_T_49[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_50 = _uncommonBits_T_50[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_51 = _uncommonBits_T_51[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_52 = _uncommonBits_T_52[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_53 = _uncommonBits_T_53[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_42 = io_in_d_bits_source_0 == 6'h20; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_0 = _source_ok_T_42; // @[Parameters.scala:1138:31]
wire [2:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] _source_ok_T_43 = io_in_d_bits_source_0[5:3]; // @[Monitor.scala:36:7]
wire [2:0] _source_ok_T_49 = io_in_d_bits_source_0[5:3]; // @[Monitor.scala:36:7]
wire _source_ok_T_44 = _source_ok_T_43 == 3'h2; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_46 = _source_ok_T_44; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_48 = _source_ok_T_46; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_1 = _source_ok_T_48; // @[Parameters.scala:1138:31]
wire [2:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[2:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_50 = _source_ok_T_49 == 3'h3; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_52 = _source_ok_T_50; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_54 = _source_ok_T_52; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_2 = _source_ok_T_54; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_8 = _source_ok_uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] _source_ok_T_55 = io_in_d_bits_source_0[5:2]; // @[Monitor.scala:36:7]
wire [3:0] _source_ok_T_61 = io_in_d_bits_source_0[5:2]; // @[Monitor.scala:36:7]
wire [3:0] _source_ok_T_67 = io_in_d_bits_source_0[5:2]; // @[Monitor.scala:36:7]
wire [3:0] _source_ok_T_73 = io_in_d_bits_source_0[5:2]; // @[Monitor.scala:36:7]
wire _source_ok_T_56 = _source_ok_T_55 == 4'h0; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_58 = _source_ok_T_56; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_60 = _source_ok_T_58; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_3 = _source_ok_T_60; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_9 = _source_ok_uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_62 = _source_ok_T_61 == 4'h1; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_64 = _source_ok_T_62; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_66 = _source_ok_T_64; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_4 = _source_ok_T_66; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_10 = _source_ok_uncommonBits_T_10[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_68 = _source_ok_T_67 == 4'h2; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_70 = _source_ok_T_68; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_72 = _source_ok_T_70; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_5 = _source_ok_T_72; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_11 = _source_ok_uncommonBits_T_11[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_74 = _source_ok_T_73 == 4'h3; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_76 = _source_ok_T_74; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_78 = _source_ok_T_76; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_6 = _source_ok_T_78; // @[Parameters.scala:1138:31]
wire _source_ok_T_79 = _source_ok_WIRE_1_0 | _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_80 = _source_ok_T_79 | _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_81 = _source_ok_T_80 | _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_82 = _source_ok_T_81 | _source_ok_WIRE_1_4; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_83 = _source_ok_T_82 | _source_ok_WIRE_1_5; // @[Parameters.scala:1138:31, :1139:46]
wire source_ok_1 = _source_ok_T_83 | _source_ok_WIRE_1_6; // @[Parameters.scala:1138:31, :1139:46]
wire _T_1571 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35]
wire _a_first_T; // @[Decoupled.scala:51:35]
assign _a_first_T = _T_1571; // @[Decoupled.scala:51:35]
wire _a_first_T_1; // @[Decoupled.scala:51:35]
assign _a_first_T_1 = _T_1571; // @[Decoupled.scala:51:35]
wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [8:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46]
wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}]
wire [8:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [8:0] a_first_counter; // @[Edges.scala:229:27]
wire [9:0] _a_first_counter1_T = {1'h0, a_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] a_first_counter1 = _a_first_counter1_T[8:0]; // @[Edges.scala:230:28]
wire a_first = a_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T = a_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_1 = a_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35]
wire [8:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [8:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [2:0] param; // @[Monitor.scala:388:22]
reg [3:0] size; // @[Monitor.scala:389:22]
reg [5:0] source; // @[Monitor.scala:390:22]
reg [31:0] address; // @[Monitor.scala:391:22]
wire _T_1644 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35]
wire _d_first_T; // @[Decoupled.scala:51:35]
assign _d_first_T = _T_1644; // @[Decoupled.scala:51:35]
wire _d_first_T_1; // @[Decoupled.scala:51:35]
assign _d_first_T_1 = _T_1644; // @[Decoupled.scala:51:35]
wire _d_first_T_2; // @[Decoupled.scala:51:35]
assign _d_first_T_2 = _T_1644; // @[Decoupled.scala:51:35]
wire [26:0] _GEN_0 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71]
assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71]
wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [8:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46]
wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire [8:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [8:0] d_first_counter; // @[Edges.scala:229:27]
wire [9:0] _d_first_counter1_T = {1'h0, d_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] d_first_counter1 = _d_first_counter1_T[8:0]; // @[Edges.scala:230:28]
wire d_first = d_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T = d_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_1 = d_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35]
wire [8:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [8:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [1:0] param_1; // @[Monitor.scala:539:22]
reg [3:0] size_1; // @[Monitor.scala:540:22]
reg [5:0] source_1; // @[Monitor.scala:541:22]
reg sink; // @[Monitor.scala:542:22]
reg denied; // @[Monitor.scala:543:22]
reg [32:0] inflight; // @[Monitor.scala:614:27]
reg [131:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [263:0] inflight_sizes; // @[Monitor.scala:618:33]
wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [8:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46]
wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}]
wire [8:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [8:0] a_first_counter_1; // @[Edges.scala:229:27]
wire [9:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] a_first_counter1_1 = _a_first_counter1_T_1[8:0]; // @[Edges.scala:230:28]
wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T_2 = a_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_3 = a_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35]
wire [8:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [8:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [8:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46]
wire [8:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [8:0] d_first_counter_1; // @[Edges.scala:229:27]
wire [9:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] d_first_counter1_1 = _d_first_counter1_T_1[8:0]; // @[Edges.scala:230:28]
wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_2 = d_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_3 = d_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35]
wire [8:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [8:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [32:0] a_set; // @[Monitor.scala:626:34]
wire [32:0] a_set_wo_ready; // @[Monitor.scala:627:34]
wire [131:0] a_opcodes_set; // @[Monitor.scala:630:33]
wire [263:0] a_sizes_set; // @[Monitor.scala:632:31]
wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35]
wire [8:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69]
wire [8:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69]
assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69]
wire [8:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101]
assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101]
wire [8:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69]
assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69]
wire [8:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101]
assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101]
wire [131:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}]
wire [131:0] _a_opcode_lookup_T_6 = {128'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}]
wire [131:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[131:1]}; // @[Monitor.scala:637:{97,152}]
assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}]
wire [7:0] a_size_lookup; // @[Monitor.scala:639:33]
wire [8:0] _GEN_2 = {io_in_d_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :641:65]
wire [8:0] _a_size_lookup_T; // @[Monitor.scala:641:65]
assign _a_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65]
wire [8:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99]
assign _d_sizes_clr_T_4 = _GEN_2; // @[Monitor.scala:641:65, :681:99]
wire [8:0] _c_size_lookup_T; // @[Monitor.scala:750:67]
assign _c_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65, :750:67]
wire [8:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99]
assign _d_sizes_clr_T_10 = _GEN_2; // @[Monitor.scala:641:65, :791:99]
wire [263:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}]
wire [263:0] _a_size_lookup_T_6 = {256'h0, _a_size_lookup_T_1[7:0]}; // @[Monitor.scala:641:{40,91}]
wire [263:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[263:1]}; // @[Monitor.scala:641:{91,144}]
assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}]
wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40]
wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38]
wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44]
wire [63:0] _GEN_3 = 64'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35]
wire [63:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35]
assign _a_set_wo_ready_T = _GEN_3; // @[OneHot.scala:58:35]
wire [63:0] _a_set_T; // @[OneHot.scala:58:35]
assign _a_set_T = _GEN_3; // @[OneHot.scala:58:35]
assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[32:0] : 33'h0; // @[OneHot.scala:58:35]
wire _T_1497 = _T_1571 & a_first_1; // @[Decoupled.scala:51:35]
assign a_set = _T_1497 ? _a_set_T[32:0] : 33'h0; // @[OneHot.scala:58:35]
wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53]
wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}]
assign a_opcodes_set_interm = _T_1497 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}]
wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51]
wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}]
assign a_sizes_set_interm = _T_1497 ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}]
wire [8:0] _a_opcodes_set_T = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79]
wire [514:0] _a_opcodes_set_T_1 = {511'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}]
assign a_opcodes_set = _T_1497 ? _a_opcodes_set_T_1[131:0] : 132'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}]
wire [8:0] _a_sizes_set_T = {io_in_a_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :660:77]
wire [515:0] _a_sizes_set_T_1 = {511'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}]
assign a_sizes_set = _T_1497 ? _a_sizes_set_T_1[263:0] : 264'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}]
wire [32:0] d_clr; // @[Monitor.scala:664:34]
wire [32:0] d_clr_wo_ready; // @[Monitor.scala:665:34]
wire [131:0] d_opcodes_clr; // @[Monitor.scala:668:33]
wire [263:0] d_sizes_clr; // @[Monitor.scala:670:31]
wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46]
wire d_release_ack; // @[Monitor.scala:673:46]
assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46]
wire d_release_ack_1; // @[Monitor.scala:783:46]
assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46]
wire _T_1543 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26]
wire [63:0] _GEN_5 = 64'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35]
wire [63:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35]
wire [63:0] _d_clr_T; // @[OneHot.scala:58:35]
assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35]
wire [63:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35]
wire [63:0] _d_clr_T_1; // @[OneHot.scala:58:35]
assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35]
assign d_clr_wo_ready = _T_1543 & ~d_release_ack ? _d_clr_wo_ready_T[32:0] : 33'h0; // @[OneHot.scala:58:35]
wire _T_1512 = _T_1644 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35]
assign d_clr = _T_1512 ? _d_clr_T[32:0] : 33'h0; // @[OneHot.scala:58:35]
wire [526:0] _d_opcodes_clr_T_5 = 527'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}]
assign d_opcodes_clr = _T_1512 ? _d_opcodes_clr_T_5[131:0] : 132'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}]
wire [526:0] _d_sizes_clr_T_5 = 527'hFF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}]
assign d_sizes_clr = _T_1512 ? _d_sizes_clr_T_5[263:0] : 264'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}]
wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}]
wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113]
wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}]
wire [32:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27]
wire [32:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38]
wire [32:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}]
wire [131:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43]
wire [131:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62]
wire [131:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}]
wire [263:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39]
wire [263:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56]
wire [263:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26]
wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26]
reg [32:0] inflight_1; // @[Monitor.scala:726:35]
wire [32:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35]
reg [131:0] inflight_opcodes_1; // @[Monitor.scala:727:35]
wire [131:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43]
reg [263:0] inflight_sizes_1; // @[Monitor.scala:728:35]
wire [263:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41]
wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}]
wire [8:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:3]; // @[package.scala:243:46]
wire [8:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [8:0] d_first_counter_2; // @[Edges.scala:229:27]
wire [9:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] d_first_counter1_2 = _d_first_counter1_T_2[8:0]; // @[Edges.scala:230:28]
wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_4 = d_first_counter_2 == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_5 = d_first_beats1_2 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35]
wire [8:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27]
wire [8:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35]
wire [7:0] c_size_lookup; // @[Monitor.scala:748:35]
wire [131:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}]
wire [131:0] _c_opcode_lookup_T_6 = {128'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}]
wire [131:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[131:1]}; // @[Monitor.scala:749:{97,152}]
assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}]
wire [263:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}]
wire [263:0] _c_size_lookup_T_6 = {256'h0, _c_size_lookup_T_1[7:0]}; // @[Monitor.scala:750:{42,93}]
wire [263:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[263:1]}; // @[Monitor.scala:750:{93,146}]
assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}]
wire [32:0] d_clr_1; // @[Monitor.scala:774:34]
wire [32:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34]
wire [131:0] d_opcodes_clr_1; // @[Monitor.scala:776:34]
wire [263:0] d_sizes_clr_1; // @[Monitor.scala:777:34]
wire _T_1615 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26]
assign d_clr_wo_ready_1 = _T_1615 & d_release_ack_1 ? _d_clr_wo_ready_T_1[32:0] : 33'h0; // @[OneHot.scala:58:35]
wire _T_1597 = _T_1644 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35]
assign d_clr_1 = _T_1597 ? _d_clr_T_1[32:0] : 33'h0; // @[OneHot.scala:58:35]
wire [526:0] _d_opcodes_clr_T_11 = 527'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}]
assign d_opcodes_clr_1 = _T_1597 ? _d_opcodes_clr_T_11[131:0] : 132'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}]
wire [526:0] _d_sizes_clr_T_11 = 527'hFF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}]
assign d_sizes_clr_1 = _T_1597 ? _d_sizes_clr_T_11[263:0] : 264'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}]
wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 6'h0; // @[Monitor.scala:36:7, :795:113]
wire [32:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46]
wire [32:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}]
wire [131:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62]
wire [131:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}]
wire [263:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58]
wire [263:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27] |
Generate the Verilog code corresponding to the following Chisel files.
File PE.scala:
// See README.md for license details.
package gemmini
import chisel3._
import chisel3.util._
class PEControl[T <: Data : Arithmetic](accType: T) extends Bundle {
val dataflow = UInt(1.W) // TODO make this an Enum
val propagate = UInt(1.W) // Which register should be propagated (and which should be accumulated)?
val shift = UInt(log2Up(accType.getWidth).W) // TODO this isn't correct for Floats
}
class MacUnit[T <: Data](inputType: T, cType: T, dType: T) (implicit ev: Arithmetic[T]) extends Module {
import ev._
val io = IO(new Bundle {
val in_a = Input(inputType)
val in_b = Input(inputType)
val in_c = Input(cType)
val out_d = Output(dType)
})
io.out_d := io.in_c.mac(io.in_a, io.in_b)
}
// TODO update documentation
/**
* A PE implementing a MAC operation. Configured as fully combinational when integrated into a Mesh.
* @param width Data width of operands
*/
class PE[T <: Data](inputType: T, outputType: T, accType: T, df: Dataflow.Value, max_simultaneous_matmuls: Int)
(implicit ev: Arithmetic[T]) extends Module { // Debugging variables
import ev._
val io = IO(new Bundle {
val in_a = Input(inputType)
val in_b = Input(outputType)
val in_d = Input(outputType)
val out_a = Output(inputType)
val out_b = Output(outputType)
val out_c = Output(outputType)
val in_control = Input(new PEControl(accType))
val out_control = Output(new PEControl(accType))
val in_id = Input(UInt(log2Up(max_simultaneous_matmuls).W))
val out_id = Output(UInt(log2Up(max_simultaneous_matmuls).W))
val in_last = Input(Bool())
val out_last = Output(Bool())
val in_valid = Input(Bool())
val out_valid = Output(Bool())
val bad_dataflow = Output(Bool())
})
val cType = if (df == Dataflow.WS) inputType else accType
// When creating PEs that support multiple dataflows, the
// elaboration/synthesis tools often fail to consolidate and de-duplicate
// MAC units. To force mac circuitry to be re-used, we create a "mac_unit"
// module here which just performs a single MAC operation
val mac_unit = Module(new MacUnit(inputType,
if (df == Dataflow.WS) outputType else accType, outputType))
val a = io.in_a
val b = io.in_b
val d = io.in_d
val c1 = Reg(cType)
val c2 = Reg(cType)
val dataflow = io.in_control.dataflow
val prop = io.in_control.propagate
val shift = io.in_control.shift
val id = io.in_id
val last = io.in_last
val valid = io.in_valid
io.out_a := a
io.out_control.dataflow := dataflow
io.out_control.propagate := prop
io.out_control.shift := shift
io.out_id := id
io.out_last := last
io.out_valid := valid
mac_unit.io.in_a := a
val last_s = RegEnable(prop, valid)
val flip = last_s =/= prop
val shift_offset = Mux(flip, shift, 0.U)
// Which dataflow are we using?
val OUTPUT_STATIONARY = Dataflow.OS.id.U(1.W)
val WEIGHT_STATIONARY = Dataflow.WS.id.U(1.W)
// Is c1 being computed on, or propagated forward (in the output-stationary dataflow)?
val COMPUTE = 0.U(1.W)
val PROPAGATE = 1.U(1.W)
io.bad_dataflow := false.B
when ((df == Dataflow.OS).B || ((df == Dataflow.BOTH).B && dataflow === OUTPUT_STATIONARY)) {
when(prop === PROPAGATE) {
io.out_c := (c1 >> shift_offset).clippedToWidthOf(outputType)
io.out_b := b
mac_unit.io.in_b := b.asTypeOf(inputType)
mac_unit.io.in_c := c2
c2 := mac_unit.io.out_d
c1 := d.withWidthOf(cType)
}.otherwise {
io.out_c := (c2 >> shift_offset).clippedToWidthOf(outputType)
io.out_b := b
mac_unit.io.in_b := b.asTypeOf(inputType)
mac_unit.io.in_c := c1
c1 := mac_unit.io.out_d
c2 := d.withWidthOf(cType)
}
}.elsewhen ((df == Dataflow.WS).B || ((df == Dataflow.BOTH).B && dataflow === WEIGHT_STATIONARY)) {
when(prop === PROPAGATE) {
io.out_c := c1
mac_unit.io.in_b := c2.asTypeOf(inputType)
mac_unit.io.in_c := b
io.out_b := mac_unit.io.out_d
c1 := d
}.otherwise {
io.out_c := c2
mac_unit.io.in_b := c1.asTypeOf(inputType)
mac_unit.io.in_c := b
io.out_b := mac_unit.io.out_d
c2 := d
}
}.otherwise {
io.bad_dataflow := true.B
//assert(false.B, "unknown dataflow")
io.out_c := DontCare
io.out_b := DontCare
mac_unit.io.in_b := b.asTypeOf(inputType)
mac_unit.io.in_c := c2
}
when (!valid) {
c1 := c1
c2 := c2
mac_unit.io.in_b := DontCare
mac_unit.io.in_c := DontCare
}
}
File Arithmetic.scala:
// A simple type class for Chisel datatypes that can add and multiply. To add your own type, simply create your own:
// implicit MyTypeArithmetic extends Arithmetic[MyType] { ... }
package gemmini
import chisel3._
import chisel3.util._
import hardfloat._
// Bundles that represent the raw bits of custom datatypes
case class Float(expWidth: Int, sigWidth: Int) extends Bundle {
val bits = UInt((expWidth + sigWidth).W)
val bias: Int = (1 << (expWidth-1)) - 1
}
case class DummySInt(w: Int) extends Bundle {
val bits = UInt(w.W)
def dontCare: DummySInt = {
val o = Wire(new DummySInt(w))
o.bits := 0.U
o
}
}
// The Arithmetic typeclass which implements various arithmetic operations on custom datatypes
abstract class Arithmetic[T <: Data] {
implicit def cast(t: T): ArithmeticOps[T]
}
abstract class ArithmeticOps[T <: Data](self: T) {
def *(t: T): T
def mac(m1: T, m2: T): T // Returns (m1 * m2 + self)
def +(t: T): T
def -(t: T): T
def >>(u: UInt): T // This is a rounding shift! Rounds away from 0
def >(t: T): Bool
def identity: T
def withWidthOf(t: T): T
def clippedToWidthOf(t: T): T // Like "withWidthOf", except that it saturates
def relu: T
def zero: T
def minimum: T
// Optional parameters, which only need to be defined if you want to enable various optimizations for transformers
def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[T])] = None
def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[T])] = None
def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = None
def mult_with_reciprocal[U <: Data](reciprocal: U) = self
}
object Arithmetic {
implicit object UIntArithmetic extends Arithmetic[UInt] {
override implicit def cast(self: UInt) = new ArithmeticOps(self) {
override def *(t: UInt) = self * t
override def mac(m1: UInt, m2: UInt) = m1 * m2 + self
override def +(t: UInt) = self + t
override def -(t: UInt) = self - t
override def >>(u: UInt) = {
// The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm
// TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here?
val point_five = Mux(u === 0.U, 0.U, self(u - 1.U))
val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U
val ones_digit = self(u)
val r = point_five & (zeros | ones_digit)
(self >> u).asUInt + r
}
override def >(t: UInt): Bool = self > t
override def withWidthOf(t: UInt) = self.asTypeOf(t)
override def clippedToWidthOf(t: UInt) = {
val sat = ((1 << (t.getWidth-1))-1).U
Mux(self > sat, sat, self)(t.getWidth-1, 0)
}
override def relu: UInt = self
override def zero: UInt = 0.U
override def identity: UInt = 1.U
override def minimum: UInt = 0.U
}
}
implicit object SIntArithmetic extends Arithmetic[SInt] {
override implicit def cast(self: SInt) = new ArithmeticOps(self) {
override def *(t: SInt) = self * t
override def mac(m1: SInt, m2: SInt) = m1 * m2 + self
override def +(t: SInt) = self + t
override def -(t: SInt) = self - t
override def >>(u: UInt) = {
// The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm
// TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here?
val point_five = Mux(u === 0.U, 0.U, self(u - 1.U))
val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U
val ones_digit = self(u)
val r = (point_five & (zeros | ones_digit)).asBool
(self >> u).asSInt + Mux(r, 1.S, 0.S)
}
override def >(t: SInt): Bool = self > t
override def withWidthOf(t: SInt) = {
if (self.getWidth >= t.getWidth)
self(t.getWidth-1, 0).asSInt
else {
val sign_bits = t.getWidth - self.getWidth
val sign = self(self.getWidth-1)
Cat(Cat(Seq.fill(sign_bits)(sign)), self).asTypeOf(t)
}
}
override def clippedToWidthOf(t: SInt): SInt = {
val maxsat = ((1 << (t.getWidth-1))-1).S
val minsat = (-(1 << (t.getWidth-1))).S
MuxCase(self, Seq((self > maxsat) -> maxsat, (self < minsat) -> minsat))(t.getWidth-1, 0).asSInt
}
override def relu: SInt = Mux(self >= 0.S, self, 0.S)
override def zero: SInt = 0.S
override def identity: SInt = 1.S
override def minimum: SInt = (-(1 << (self.getWidth-1))).S
override def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = {
// TODO this uses a floating point divider, but we should use an integer divider instead
val input = Wire(Decoupled(denom_t.cloneType))
val output = Wire(Decoupled(self.cloneType))
// We translate our integer to floating-point form so that we can use the hardfloat divider
val expWidth = log2Up(self.getWidth) + 1
val sigWidth = self.getWidth
def sin_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def uin_to_float(x: UInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := false.B
in_to_rec_fn.io.in := x
in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def float_to_in(x: UInt) = {
val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth))
rec_fn_to_in.io.signedOut := true.B
rec_fn_to_in.io.in := x
rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
rec_fn_to_in.io.out.asSInt
}
val self_rec = sin_to_float(self)
val denom_rec = uin_to_float(input.bits)
// Instantiate the hardloat divider
val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options))
input.ready := divider.io.inReady
divider.io.inValid := input.valid
divider.io.sqrtOp := false.B
divider.io.a := self_rec
divider.io.b := denom_rec
divider.io.roundingMode := consts.round_minMag
divider.io.detectTininess := consts.tininess_afterRounding
output.valid := divider.io.outValid_div
output.bits := float_to_in(divider.io.out)
assert(!output.valid || output.ready)
Some((input, output))
}
override def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = {
// TODO this uses a floating point divider, but we should use an integer divider instead
val input = Wire(Decoupled(UInt(0.W)))
val output = Wire(Decoupled(self.cloneType))
input.bits := DontCare
// We translate our integer to floating-point form so that we can use the hardfloat divider
val expWidth = log2Up(self.getWidth) + 1
val sigWidth = self.getWidth
def in_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def float_to_in(x: UInt) = {
val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth))
rec_fn_to_in.io.signedOut := true.B
rec_fn_to_in.io.in := x
rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
rec_fn_to_in.io.out.asSInt
}
val self_rec = in_to_float(self)
// Instantiate the hardloat sqrt
val sqrter = Module(new DivSqrtRecFN_small(expWidth, sigWidth, 0))
input.ready := sqrter.io.inReady
sqrter.io.inValid := input.valid
sqrter.io.sqrtOp := true.B
sqrter.io.a := self_rec
sqrter.io.b := DontCare
sqrter.io.roundingMode := consts.round_minMag
sqrter.io.detectTininess := consts.tininess_afterRounding
output.valid := sqrter.io.outValid_sqrt
output.bits := float_to_in(sqrter.io.out)
assert(!output.valid || output.ready)
Some((input, output))
}
override def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = u match {
case Float(expWidth, sigWidth) =>
val input = Wire(Decoupled(UInt(0.W)))
val output = Wire(Decoupled(u.cloneType))
input.bits := DontCare
// We translate our integer to floating-point form so that we can use the hardfloat divider
def in_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
val self_rec = in_to_float(self)
val one_rec = in_to_float(1.S)
// Instantiate the hardloat divider
val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options))
input.ready := divider.io.inReady
divider.io.inValid := input.valid
divider.io.sqrtOp := false.B
divider.io.a := one_rec
divider.io.b := self_rec
divider.io.roundingMode := consts.round_near_even
divider.io.detectTininess := consts.tininess_afterRounding
output.valid := divider.io.outValid_div
output.bits := fNFromRecFN(expWidth, sigWidth, divider.io.out).asTypeOf(u)
assert(!output.valid || output.ready)
Some((input, output))
case _ => None
}
override def mult_with_reciprocal[U <: Data](reciprocal: U): SInt = reciprocal match {
case recip @ Float(expWidth, sigWidth) =>
def in_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def float_to_in(x: UInt) = {
val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth))
rec_fn_to_in.io.signedOut := true.B
rec_fn_to_in.io.in := x
rec_fn_to_in.io.roundingMode := consts.round_minMag
rec_fn_to_in.io.out.asSInt
}
val self_rec = in_to_float(self)
val reciprocal_rec = recFNFromFN(expWidth, sigWidth, recip.bits)
// Instantiate the hardloat divider
val muladder = Module(new MulRecFN(expWidth, sigWidth))
muladder.io.roundingMode := consts.round_near_even
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := self_rec
muladder.io.b := reciprocal_rec
float_to_in(muladder.io.out)
case _ => self
}
}
}
implicit object FloatArithmetic extends Arithmetic[Float] {
// TODO Floating point arithmetic currently switches between recoded and standard formats for every operation. However, it should stay in the recoded format as it travels through the systolic array
override implicit def cast(self: Float): ArithmeticOps[Float] = new ArithmeticOps(self) {
override def *(t: Float): Float = {
val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth))
t_resizer.io.in := t_rec
t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
t_resizer.io.detectTininess := consts.tininess_afterRounding
val t_rec_resized = t_resizer.io.out
val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth))
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := self_rec
muladder.io.b := t_rec_resized
val out = Wire(Float(self.expWidth, self.sigWidth))
out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
out
}
override def mac(m1: Float, m2: Float): Float = {
// Recode all operands
val m1_rec = recFNFromFN(m1.expWidth, m1.sigWidth, m1.bits)
val m2_rec = recFNFromFN(m2.expWidth, m2.sigWidth, m2.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Resize m1 to self's width
val m1_resizer = Module(new RecFNToRecFN(m1.expWidth, m1.sigWidth, self.expWidth, self.sigWidth))
m1_resizer.io.in := m1_rec
m1_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
m1_resizer.io.detectTininess := consts.tininess_afterRounding
val m1_rec_resized = m1_resizer.io.out
// Resize m2 to self's width
val m2_resizer = Module(new RecFNToRecFN(m2.expWidth, m2.sigWidth, self.expWidth, self.sigWidth))
m2_resizer.io.in := m2_rec
m2_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
m2_resizer.io.detectTininess := consts.tininess_afterRounding
val m2_rec_resized = m2_resizer.io.out
// Perform multiply-add
val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth))
muladder.io.op := 0.U
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := m1_rec_resized
muladder.io.b := m2_rec_resized
muladder.io.c := self_rec
// Convert result to standard format // TODO remove these intermediate recodings
val out = Wire(Float(self.expWidth, self.sigWidth))
out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
out
}
override def +(t: Float): Float = {
require(self.getWidth >= t.getWidth) // This just makes it easier to write the resizing code
// Recode all operands
val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Generate 1 as a float
val in_to_rec_fn = Module(new INToRecFN(1, self.expWidth, self.sigWidth))
in_to_rec_fn.io.signedIn := false.B
in_to_rec_fn.io.in := 1.U
in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
val one_rec = in_to_rec_fn.io.out
// Resize t
val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth))
t_resizer.io.in := t_rec
t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
t_resizer.io.detectTininess := consts.tininess_afterRounding
val t_rec_resized = t_resizer.io.out
// Perform addition
val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth))
muladder.io.op := 0.U
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := t_rec_resized
muladder.io.b := one_rec
muladder.io.c := self_rec
val result = Wire(Float(self.expWidth, self.sigWidth))
result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
result
}
override def -(t: Float): Float = {
val t_sgn = t.bits(t.getWidth-1)
val neg_t = Cat(~t_sgn, t.bits(t.getWidth-2,0)).asTypeOf(t)
self + neg_t
}
override def >>(u: UInt): Float = {
// Recode self
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Get 2^(-u) as a recoded float
val shift_exp = Wire(UInt(self.expWidth.W))
shift_exp := self.bias.U - u
val shift_fn = Cat(0.U(1.W), shift_exp, 0.U((self.sigWidth-1).W))
val shift_rec = recFNFromFN(self.expWidth, self.sigWidth, shift_fn)
assert(shift_exp =/= 0.U, "scaling by denormalized numbers is not currently supported")
// Multiply self and 2^(-u)
val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth))
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := self_rec
muladder.io.b := shift_rec
val result = Wire(Float(self.expWidth, self.sigWidth))
result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
result
}
override def >(t: Float): Bool = {
// Recode all operands
val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Resize t to self's width
val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth))
t_resizer.io.in := t_rec
t_resizer.io.roundingMode := consts.round_near_even
t_resizer.io.detectTininess := consts.tininess_afterRounding
val t_rec_resized = t_resizer.io.out
val comparator = Module(new CompareRecFN(self.expWidth, self.sigWidth))
comparator.io.a := self_rec
comparator.io.b := t_rec_resized
comparator.io.signaling := false.B
comparator.io.gt
}
override def withWidthOf(t: Float): Float = {
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth))
resizer.io.in := self_rec
resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
resizer.io.detectTininess := consts.tininess_afterRounding
val result = Wire(Float(t.expWidth, t.sigWidth))
result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out)
result
}
override def clippedToWidthOf(t: Float): Float = {
// TODO check for overflow. Right now, we just assume that overflow doesn't happen
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth))
resizer.io.in := self_rec
resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
resizer.io.detectTininess := consts.tininess_afterRounding
val result = Wire(Float(t.expWidth, t.sigWidth))
result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out)
result
}
override def relu: Float = {
val raw = rawFloatFromFN(self.expWidth, self.sigWidth, self.bits)
val result = Wire(Float(self.expWidth, self.sigWidth))
result.bits := Mux(!raw.isZero && raw.sign, 0.U, self.bits)
result
}
override def zero: Float = 0.U.asTypeOf(self)
override def identity: Float = Cat(0.U(2.W), ~(0.U((self.expWidth-1).W)), 0.U((self.sigWidth-1).W)).asTypeOf(self)
override def minimum: Float = Cat(1.U, ~(0.U(self.expWidth.W)), 0.U((self.sigWidth-1).W)).asTypeOf(self)
}
}
implicit object DummySIntArithmetic extends Arithmetic[DummySInt] {
override implicit def cast(self: DummySInt) = new ArithmeticOps(self) {
override def *(t: DummySInt) = self.dontCare
override def mac(m1: DummySInt, m2: DummySInt) = self.dontCare
override def +(t: DummySInt) = self.dontCare
override def -(t: DummySInt) = self.dontCare
override def >>(t: UInt) = self.dontCare
override def >(t: DummySInt): Bool = false.B
override def identity = self.dontCare
override def withWidthOf(t: DummySInt) = self.dontCare
override def clippedToWidthOf(t: DummySInt) = self.dontCare
override def relu = self.dontCare
override def zero = self.dontCare
override def minimum: DummySInt = self.dontCare
}
}
}
| module PE_291( // @[PE.scala:31:7]
input clock, // @[PE.scala:31:7]
input reset, // @[PE.scala:31:7]
input [7:0] io_in_a, // @[PE.scala:35:14]
input [19:0] io_in_b, // @[PE.scala:35:14]
input [19:0] io_in_d, // @[PE.scala:35:14]
output [7:0] io_out_a, // @[PE.scala:35:14]
output [19:0] io_out_b, // @[PE.scala:35:14]
output [19:0] io_out_c, // @[PE.scala:35:14]
input io_in_control_dataflow, // @[PE.scala:35:14]
input io_in_control_propagate, // @[PE.scala:35:14]
input [4:0] io_in_control_shift, // @[PE.scala:35:14]
output io_out_control_dataflow, // @[PE.scala:35:14]
output io_out_control_propagate, // @[PE.scala:35:14]
output [4:0] io_out_control_shift, // @[PE.scala:35:14]
input [2:0] io_in_id, // @[PE.scala:35:14]
output [2:0] io_out_id, // @[PE.scala:35:14]
input io_in_last, // @[PE.scala:35:14]
output io_out_last, // @[PE.scala:35:14]
input io_in_valid, // @[PE.scala:35:14]
output io_out_valid, // @[PE.scala:35:14]
output io_bad_dataflow // @[PE.scala:35:14]
);
wire [19:0] _mac_unit_io_out_d; // @[PE.scala:64:24]
wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:31:7]
wire [19:0] io_in_b_0 = io_in_b; // @[PE.scala:31:7]
wire [19:0] io_in_d_0 = io_in_d; // @[PE.scala:31:7]
wire io_in_control_dataflow_0 = io_in_control_dataflow; // @[PE.scala:31:7]
wire io_in_control_propagate_0 = io_in_control_propagate; // @[PE.scala:31:7]
wire [4:0] io_in_control_shift_0 = io_in_control_shift; // @[PE.scala:31:7]
wire [2:0] io_in_id_0 = io_in_id; // @[PE.scala:31:7]
wire io_in_last_0 = io_in_last; // @[PE.scala:31:7]
wire io_in_valid_0 = io_in_valid; // @[PE.scala:31:7]
wire io_bad_dataflow_0 = 1'h0; // @[PE.scala:31:7]
wire [7:0] io_out_a_0 = io_in_a_0; // @[PE.scala:31:7]
wire [19:0] _mac_unit_io_in_b_T = io_in_b_0; // @[PE.scala:31:7, :106:37]
wire [19:0] _mac_unit_io_in_b_T_2 = io_in_b_0; // @[PE.scala:31:7, :113:37]
wire [19:0] _mac_unit_io_in_b_T_8 = io_in_b_0; // @[PE.scala:31:7, :137:35]
wire [19:0] c1_lo_1 = io_in_d_0; // @[PE.scala:31:7]
wire [19:0] c2_lo_1 = io_in_d_0; // @[PE.scala:31:7]
wire io_out_control_dataflow_0 = io_in_control_dataflow_0; // @[PE.scala:31:7]
wire io_out_control_propagate_0 = io_in_control_propagate_0; // @[PE.scala:31:7]
wire [4:0] io_out_control_shift_0 = io_in_control_shift_0; // @[PE.scala:31:7]
wire [2:0] io_out_id_0 = io_in_id_0; // @[PE.scala:31:7]
wire io_out_last_0 = io_in_last_0; // @[PE.scala:31:7]
wire io_out_valid_0 = io_in_valid_0; // @[PE.scala:31:7]
wire [19:0] io_out_b_0; // @[PE.scala:31:7]
wire [19:0] io_out_c_0; // @[PE.scala:31:7]
reg [31:0] c1; // @[PE.scala:70:15]
wire [31:0] _io_out_c_zeros_T_1 = c1; // @[PE.scala:70:15]
wire [31:0] _mac_unit_io_in_b_T_6 = c1; // @[PE.scala:70:15, :127:38]
reg [31:0] c2; // @[PE.scala:71:15]
wire [31:0] _io_out_c_zeros_T_10 = c2; // @[PE.scala:71:15]
wire [31:0] _mac_unit_io_in_b_T_4 = c2; // @[PE.scala:71:15, :121:38]
reg last_s; // @[PE.scala:89:25]
wire flip = last_s != io_in_control_propagate_0; // @[PE.scala:31:7, :89:25, :90:21]
wire [4:0] shift_offset = flip ? io_in_control_shift_0 : 5'h0; // @[PE.scala:31:7, :90:21, :91:25]
wire _GEN = shift_offset == 5'h0; // @[PE.scala:91:25]
wire _io_out_c_point_five_T; // @[Arithmetic.scala:101:32]
assign _io_out_c_point_five_T = _GEN; // @[Arithmetic.scala:101:32]
wire _io_out_c_point_five_T_5; // @[Arithmetic.scala:101:32]
assign _io_out_c_point_five_T_5 = _GEN; // @[Arithmetic.scala:101:32]
wire [5:0] _GEN_0 = {1'h0, shift_offset} - 6'h1; // @[PE.scala:91:25]
wire [5:0] _io_out_c_point_five_T_1; // @[Arithmetic.scala:101:53]
assign _io_out_c_point_five_T_1 = _GEN_0; // @[Arithmetic.scala:101:53]
wire [5:0] _io_out_c_zeros_T_2; // @[Arithmetic.scala:102:66]
assign _io_out_c_zeros_T_2 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66]
wire [5:0] _io_out_c_point_five_T_6; // @[Arithmetic.scala:101:53]
assign _io_out_c_point_five_T_6 = _GEN_0; // @[Arithmetic.scala:101:53]
wire [5:0] _io_out_c_zeros_T_11; // @[Arithmetic.scala:102:66]
assign _io_out_c_zeros_T_11 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66]
wire [4:0] _io_out_c_point_five_T_2 = _io_out_c_point_five_T_1[4:0]; // @[Arithmetic.scala:101:53]
wire [31:0] _io_out_c_point_five_T_3 = $signed($signed(c1) >>> _io_out_c_point_five_T_2); // @[PE.scala:70:15]
wire _io_out_c_point_five_T_4 = _io_out_c_point_five_T_3[0]; // @[Arithmetic.scala:101:50]
wire io_out_c_point_five = ~_io_out_c_point_five_T & _io_out_c_point_five_T_4; // @[Arithmetic.scala:101:{29,32,50}]
wire _GEN_1 = shift_offset < 5'h2; // @[PE.scala:91:25]
wire _io_out_c_zeros_T; // @[Arithmetic.scala:102:27]
assign _io_out_c_zeros_T = _GEN_1; // @[Arithmetic.scala:102:27]
wire _io_out_c_zeros_T_9; // @[Arithmetic.scala:102:27]
assign _io_out_c_zeros_T_9 = _GEN_1; // @[Arithmetic.scala:102:27]
wire [4:0] _io_out_c_zeros_T_3 = _io_out_c_zeros_T_2[4:0]; // @[Arithmetic.scala:102:66]
wire [31:0] _io_out_c_zeros_T_4 = 32'h1 << _io_out_c_zeros_T_3; // @[Arithmetic.scala:102:{60,66}]
wire [32:0] _io_out_c_zeros_T_5 = {1'h0, _io_out_c_zeros_T_4} - 33'h1; // @[Arithmetic.scala:102:{60,81}]
wire [31:0] _io_out_c_zeros_T_6 = _io_out_c_zeros_T_5[31:0]; // @[Arithmetic.scala:102:81]
wire [31:0] _io_out_c_zeros_T_7 = _io_out_c_zeros_T_1 & _io_out_c_zeros_T_6; // @[Arithmetic.scala:102:{45,52,81}]
wire [31:0] _io_out_c_zeros_T_8 = _io_out_c_zeros_T ? 32'h0 : _io_out_c_zeros_T_7; // @[Arithmetic.scala:102:{24,27,52}]
wire io_out_c_zeros = |_io_out_c_zeros_T_8; // @[Arithmetic.scala:102:{24,89}]
wire [31:0] _GEN_2 = {27'h0, shift_offset}; // @[PE.scala:91:25]
wire [31:0] _GEN_3 = $signed($signed(c1) >>> _GEN_2); // @[PE.scala:70:15]
wire [31:0] _io_out_c_ones_digit_T; // @[Arithmetic.scala:103:30]
assign _io_out_c_ones_digit_T = _GEN_3; // @[Arithmetic.scala:103:30]
wire [31:0] _io_out_c_T; // @[Arithmetic.scala:107:15]
assign _io_out_c_T = _GEN_3; // @[Arithmetic.scala:103:30, :107:15]
wire io_out_c_ones_digit = _io_out_c_ones_digit_T[0]; // @[Arithmetic.scala:103:30]
wire _io_out_c_r_T = io_out_c_zeros | io_out_c_ones_digit; // @[Arithmetic.scala:102:89, :103:30, :105:38]
wire _io_out_c_r_T_1 = io_out_c_point_five & _io_out_c_r_T; // @[Arithmetic.scala:101:29, :105:{29,38}]
wire io_out_c_r = _io_out_c_r_T_1; // @[Arithmetic.scala:105:{29,53}]
wire [1:0] _io_out_c_T_1 = {1'h0, io_out_c_r}; // @[Arithmetic.scala:105:53, :107:33]
wire [32:0] _io_out_c_T_2 = {_io_out_c_T[31], _io_out_c_T} + {{31{_io_out_c_T_1[1]}}, _io_out_c_T_1}; // @[Arithmetic.scala:107:{15,28,33}]
wire [31:0] _io_out_c_T_3 = _io_out_c_T_2[31:0]; // @[Arithmetic.scala:107:28]
wire [31:0] _io_out_c_T_4 = _io_out_c_T_3; // @[Arithmetic.scala:107:28]
wire _io_out_c_T_5 = $signed(_io_out_c_T_4) > 32'sh7FFFF; // @[Arithmetic.scala:107:28, :125:33]
wire _io_out_c_T_6 = $signed(_io_out_c_T_4) < -32'sh80000; // @[Arithmetic.scala:107:28, :125:60]
wire [31:0] _io_out_c_T_7 = _io_out_c_T_6 ? 32'hFFF80000 : _io_out_c_T_4; // @[Mux.scala:126:16]
wire [31:0] _io_out_c_T_8 = _io_out_c_T_5 ? 32'h7FFFF : _io_out_c_T_7; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_9 = _io_out_c_T_8[19:0]; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_10 = _io_out_c_T_9; // @[Arithmetic.scala:125:{81,99}]
wire [19:0] _mac_unit_io_in_b_T_1 = _mac_unit_io_in_b_T; // @[PE.scala:106:37]
wire [7:0] _mac_unit_io_in_b_WIRE = _mac_unit_io_in_b_T_1[7:0]; // @[PE.scala:106:37]
wire c1_sign = io_in_d_0[19]; // @[PE.scala:31:7]
wire c2_sign = io_in_d_0[19]; // @[PE.scala:31:7]
wire [1:0] _GEN_4 = {2{c1_sign}}; // @[Arithmetic.scala:117:26, :118:18]
wire [1:0] c1_lo_lo_hi; // @[Arithmetic.scala:118:18]
assign c1_lo_lo_hi = _GEN_4; // @[Arithmetic.scala:118:18]
wire [1:0] c1_lo_hi_hi; // @[Arithmetic.scala:118:18]
assign c1_lo_hi_hi = _GEN_4; // @[Arithmetic.scala:118:18]
wire [1:0] c1_hi_lo_hi; // @[Arithmetic.scala:118:18]
assign c1_hi_lo_hi = _GEN_4; // @[Arithmetic.scala:118:18]
wire [1:0] c1_hi_hi_hi; // @[Arithmetic.scala:118:18]
assign c1_hi_hi_hi = _GEN_4; // @[Arithmetic.scala:118:18]
wire [2:0] c1_lo_lo = {c1_lo_lo_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [2:0] c1_lo_hi = {c1_lo_hi_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [5:0] c1_lo = {c1_lo_hi, c1_lo_lo}; // @[Arithmetic.scala:118:18]
wire [2:0] c1_hi_lo = {c1_hi_lo_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [2:0] c1_hi_hi = {c1_hi_hi_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [5:0] c1_hi = {c1_hi_hi, c1_hi_lo}; // @[Arithmetic.scala:118:18]
wire [11:0] _c1_T = {c1_hi, c1_lo}; // @[Arithmetic.scala:118:18]
wire [31:0] _c1_T_1 = {_c1_T, c1_lo_1}; // @[Arithmetic.scala:118:{14,18}]
wire [31:0] _c1_T_2 = _c1_T_1; // @[Arithmetic.scala:118:{14,61}]
wire [31:0] _c1_WIRE = _c1_T_2; // @[Arithmetic.scala:118:61]
wire [4:0] _io_out_c_point_five_T_7 = _io_out_c_point_five_T_6[4:0]; // @[Arithmetic.scala:101:53]
wire [31:0] _io_out_c_point_five_T_8 = $signed($signed(c2) >>> _io_out_c_point_five_T_7); // @[PE.scala:71:15]
wire _io_out_c_point_five_T_9 = _io_out_c_point_five_T_8[0]; // @[Arithmetic.scala:101:50]
wire io_out_c_point_five_1 = ~_io_out_c_point_five_T_5 & _io_out_c_point_five_T_9; // @[Arithmetic.scala:101:{29,32,50}]
wire [4:0] _io_out_c_zeros_T_12 = _io_out_c_zeros_T_11[4:0]; // @[Arithmetic.scala:102:66]
wire [31:0] _io_out_c_zeros_T_13 = 32'h1 << _io_out_c_zeros_T_12; // @[Arithmetic.scala:102:{60,66}]
wire [32:0] _io_out_c_zeros_T_14 = {1'h0, _io_out_c_zeros_T_13} - 33'h1; // @[Arithmetic.scala:102:{60,81}]
wire [31:0] _io_out_c_zeros_T_15 = _io_out_c_zeros_T_14[31:0]; // @[Arithmetic.scala:102:81]
wire [31:0] _io_out_c_zeros_T_16 = _io_out_c_zeros_T_10 & _io_out_c_zeros_T_15; // @[Arithmetic.scala:102:{45,52,81}]
wire [31:0] _io_out_c_zeros_T_17 = _io_out_c_zeros_T_9 ? 32'h0 : _io_out_c_zeros_T_16; // @[Arithmetic.scala:102:{24,27,52}]
wire io_out_c_zeros_1 = |_io_out_c_zeros_T_17; // @[Arithmetic.scala:102:{24,89}]
wire [31:0] _GEN_5 = $signed($signed(c2) >>> _GEN_2); // @[PE.scala:71:15]
wire [31:0] _io_out_c_ones_digit_T_1; // @[Arithmetic.scala:103:30]
assign _io_out_c_ones_digit_T_1 = _GEN_5; // @[Arithmetic.scala:103:30]
wire [31:0] _io_out_c_T_11; // @[Arithmetic.scala:107:15]
assign _io_out_c_T_11 = _GEN_5; // @[Arithmetic.scala:103:30, :107:15]
wire io_out_c_ones_digit_1 = _io_out_c_ones_digit_T_1[0]; // @[Arithmetic.scala:103:30]
wire _io_out_c_r_T_2 = io_out_c_zeros_1 | io_out_c_ones_digit_1; // @[Arithmetic.scala:102:89, :103:30, :105:38]
wire _io_out_c_r_T_3 = io_out_c_point_five_1 & _io_out_c_r_T_2; // @[Arithmetic.scala:101:29, :105:{29,38}]
wire io_out_c_r_1 = _io_out_c_r_T_3; // @[Arithmetic.scala:105:{29,53}]
wire [1:0] _io_out_c_T_12 = {1'h0, io_out_c_r_1}; // @[Arithmetic.scala:105:53, :107:33]
wire [32:0] _io_out_c_T_13 = {_io_out_c_T_11[31], _io_out_c_T_11} + {{31{_io_out_c_T_12[1]}}, _io_out_c_T_12}; // @[Arithmetic.scala:107:{15,28,33}]
wire [31:0] _io_out_c_T_14 = _io_out_c_T_13[31:0]; // @[Arithmetic.scala:107:28]
wire [31:0] _io_out_c_T_15 = _io_out_c_T_14; // @[Arithmetic.scala:107:28]
wire _io_out_c_T_16 = $signed(_io_out_c_T_15) > 32'sh7FFFF; // @[Arithmetic.scala:107:28, :125:33]
wire _io_out_c_T_17 = $signed(_io_out_c_T_15) < -32'sh80000; // @[Arithmetic.scala:107:28, :125:60]
wire [31:0] _io_out_c_T_18 = _io_out_c_T_17 ? 32'hFFF80000 : _io_out_c_T_15; // @[Mux.scala:126:16]
wire [31:0] _io_out_c_T_19 = _io_out_c_T_16 ? 32'h7FFFF : _io_out_c_T_18; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_20 = _io_out_c_T_19[19:0]; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_21 = _io_out_c_T_20; // @[Arithmetic.scala:125:{81,99}]
wire [19:0] _mac_unit_io_in_b_T_3 = _mac_unit_io_in_b_T_2; // @[PE.scala:113:37]
wire [7:0] _mac_unit_io_in_b_WIRE_1 = _mac_unit_io_in_b_T_3[7:0]; // @[PE.scala:113:37]
wire [1:0] _GEN_6 = {2{c2_sign}}; // @[Arithmetic.scala:117:26, :118:18]
wire [1:0] c2_lo_lo_hi; // @[Arithmetic.scala:118:18]
assign c2_lo_lo_hi = _GEN_6; // @[Arithmetic.scala:118:18]
wire [1:0] c2_lo_hi_hi; // @[Arithmetic.scala:118:18]
assign c2_lo_hi_hi = _GEN_6; // @[Arithmetic.scala:118:18]
wire [1:0] c2_hi_lo_hi; // @[Arithmetic.scala:118:18]
assign c2_hi_lo_hi = _GEN_6; // @[Arithmetic.scala:118:18]
wire [1:0] c2_hi_hi_hi; // @[Arithmetic.scala:118:18]
assign c2_hi_hi_hi = _GEN_6; // @[Arithmetic.scala:118:18]
wire [2:0] c2_lo_lo = {c2_lo_lo_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [2:0] c2_lo_hi = {c2_lo_hi_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [5:0] c2_lo = {c2_lo_hi, c2_lo_lo}; // @[Arithmetic.scala:118:18]
wire [2:0] c2_hi_lo = {c2_hi_lo_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [2:0] c2_hi_hi = {c2_hi_hi_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [5:0] c2_hi = {c2_hi_hi, c2_hi_lo}; // @[Arithmetic.scala:118:18]
wire [11:0] _c2_T = {c2_hi, c2_lo}; // @[Arithmetic.scala:118:18]
wire [31:0] _c2_T_1 = {_c2_T, c2_lo_1}; // @[Arithmetic.scala:118:{14,18}]
wire [31:0] _c2_T_2 = _c2_T_1; // @[Arithmetic.scala:118:{14,61}]
wire [31:0] _c2_WIRE = _c2_T_2; // @[Arithmetic.scala:118:61]
wire [31:0] _mac_unit_io_in_b_T_5 = _mac_unit_io_in_b_T_4; // @[PE.scala:121:38]
wire [7:0] _mac_unit_io_in_b_WIRE_2 = _mac_unit_io_in_b_T_5[7:0]; // @[PE.scala:121:38]
wire [31:0] _mac_unit_io_in_b_T_7 = _mac_unit_io_in_b_T_6; // @[PE.scala:127:38]
wire [7:0] _mac_unit_io_in_b_WIRE_3 = _mac_unit_io_in_b_T_7[7:0]; // @[PE.scala:127:38]
assign io_out_c_0 = io_in_control_dataflow_0 ? (io_in_control_propagate_0 ? c1[19:0] : c2[19:0]) : io_in_control_propagate_0 ? _io_out_c_T_10 : _io_out_c_T_21; // @[PE.scala:31:7, :70:15, :71:15, :102:95, :103:30, :104:16, :111:16, :118:101, :119:30, :120:16, :126:16]
assign io_out_b_0 = io_in_control_dataflow_0 ? _mac_unit_io_out_d : io_in_b_0; // @[PE.scala:31:7, :64:24, :102:95, :103:30, :118:101]
wire [19:0] _mac_unit_io_in_b_T_9 = _mac_unit_io_in_b_T_8; // @[PE.scala:137:35]
wire [7:0] _mac_unit_io_in_b_WIRE_4 = _mac_unit_io_in_b_T_9[7:0]; // @[PE.scala:137:35]
wire [31:0] _GEN_7 = {{12{io_in_d_0[19]}}, io_in_d_0}; // @[PE.scala:31:7, :124:10]
wire [31:0] _GEN_8 = {{12{_mac_unit_io_out_d[19]}}, _mac_unit_io_out_d}; // @[PE.scala:64:24, :108:10]
always @(posedge clock) begin // @[PE.scala:31:7]
if (io_in_valid_0) begin // @[PE.scala:31:7]
if (io_in_control_dataflow_0) begin // @[PE.scala:31:7]
if (io_in_control_dataflow_0 & io_in_control_propagate_0) // @[PE.scala:31:7, :70:15, :118:101, :119:30, :124:10]
c1 <= _GEN_7; // @[PE.scala:70:15, :124:10]
if (~io_in_control_dataflow_0 | io_in_control_propagate_0) begin // @[PE.scala:31:7, :71:15, :118:101, :119:30]
end
else // @[PE.scala:71:15, :118:101, :119:30]
c2 <= _GEN_7; // @[PE.scala:71:15, :124:10]
end
else begin // @[PE.scala:31:7]
c1 <= io_in_control_propagate_0 ? _c1_WIRE : _GEN_8; // @[PE.scala:31:7, :70:15, :103:30, :108:10, :109:10, :115:10]
c2 <= io_in_control_propagate_0 ? _GEN_8 : _c2_WIRE; // @[PE.scala:31:7, :71:15, :103:30, :108:10, :116:10]
end
last_s <= io_in_control_propagate_0; // @[PE.scala:31:7, :89:25]
end
always @(posedge)
MacUnit_35 mac_unit ( // @[PE.scala:64:24]
.clock (clock),
.reset (reset),
.io_in_a (io_in_a_0), // @[PE.scala:31:7]
.io_in_b (io_in_control_dataflow_0 ? (io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE_2 : _mac_unit_io_in_b_WIRE_3) : io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE : _mac_unit_io_in_b_WIRE_1), // @[PE.scala:31:7, :102:95, :103:30, :106:{24,37}, :113:{24,37}, :118:101, :119:30, :121:{24,38}, :127:{24,38}]
.io_in_c (io_in_control_dataflow_0 ? {{12{io_in_b_0[19]}}, io_in_b_0} : io_in_control_propagate_0 ? c2 : c1), // @[PE.scala:31:7, :70:15, :71:15, :102:95, :103:30, :107:24, :114:24, :118:101, :122:24]
.io_out_d (_mac_unit_io_out_d)
); // @[PE.scala:64:24]
assign io_out_a = io_out_a_0; // @[PE.scala:31:7]
assign io_out_b = io_out_b_0; // @[PE.scala:31:7]
assign io_out_c = io_out_c_0; // @[PE.scala:31:7]
assign io_out_control_dataflow = io_out_control_dataflow_0; // @[PE.scala:31:7]
assign io_out_control_propagate = io_out_control_propagate_0; // @[PE.scala:31:7]
assign io_out_control_shift = io_out_control_shift_0; // @[PE.scala:31:7]
assign io_out_id = io_out_id_0; // @[PE.scala:31:7]
assign io_out_last = io_out_last_0; // @[PE.scala:31:7]
assign io_out_valid = io_out_valid_0; // @[PE.scala:31:7]
assign io_bad_dataflow = io_bad_dataflow_0; // @[PE.scala:31:7]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File AsyncResetReg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
/** This black-boxes an Async Reset
* (or Set)
* Register.
*
* Because Chisel doesn't support
* parameterized black boxes,
* we unfortunately have to
* instantiate a number of these.
*
* We also have to hard-code the set/
* reset behavior.
*
* Do not confuse an asynchronous
* reset signal with an asynchronously
* reset reg. You should still
* properly synchronize your reset
* deassertion.
*
* @param d Data input
* @param q Data Output
* @param clk Clock Input
* @param rst Reset Input
* @param en Write Enable Input
*
*/
class AsyncResetReg(resetValue: Int = 0) extends RawModule {
val io = IO(new Bundle {
val d = Input(Bool())
val q = Output(Bool())
val en = Input(Bool())
val clk = Input(Clock())
val rst = Input(Reset())
})
val reg = withClockAndReset(io.clk, io.rst.asAsyncReset)(RegInit(resetValue.U(1.W)))
when (io.en) {
reg := io.d
}
io.q := reg
}
class SimpleRegIO(val w: Int) extends Bundle{
val d = Input(UInt(w.W))
val q = Output(UInt(w.W))
val en = Input(Bool())
}
class AsyncResetRegVec(val w: Int, val init: BigInt) extends Module {
override def desiredName = s"AsyncResetRegVec_w${w}_i${init}"
val io = IO(new SimpleRegIO(w))
val reg = withReset(reset.asAsyncReset)(RegInit(init.U(w.W)))
when (io.en) {
reg := io.d
}
io.q := reg
}
object AsyncResetReg {
// Create Single Registers
def apply(d: Bool, clk: Clock, rst: Bool, init: Boolean, name: Option[String]): Bool = {
val reg = Module(new AsyncResetReg(if (init) 1 else 0))
reg.io.d := d
reg.io.clk := clk
reg.io.rst := rst
reg.io.en := true.B
name.foreach(reg.suggestName(_))
reg.io.q
}
def apply(d: Bool, clk: Clock, rst: Bool): Bool = apply(d, clk, rst, false, None)
def apply(d: Bool, clk: Clock, rst: Bool, name: String): Bool = apply(d, clk, rst, false, Some(name))
// Create Vectors of Registers
def apply(updateData: UInt, resetData: BigInt, enable: Bool, name: Option[String] = None): UInt = {
val w = updateData.getWidth max resetData.bitLength
val reg = Module(new AsyncResetRegVec(w, resetData))
name.foreach(reg.suggestName(_))
reg.io.d := updateData
reg.io.en := enable
reg.io.q
}
def apply(updateData: UInt, resetData: BigInt, enable: Bool, name: String): UInt = apply(updateData,
resetData, enable, Some(name))
def apply(updateData: UInt, resetData: BigInt): UInt = apply(updateData, resetData, enable = true.B)
def apply(updateData: UInt, resetData: BigInt, name: String): UInt = apply(updateData, resetData, enable = true.B, Some(name))
def apply(updateData: UInt, enable: Bool): UInt = apply(updateData, resetData=BigInt(0), enable)
def apply(updateData: UInt, enable: Bool, name: String): UInt = apply(updateData, resetData = BigInt(0), enable, Some(name))
def apply(updateData: UInt): UInt = apply(updateData, resetData = BigInt(0), enable = true.B)
def apply(updateData: UInt, name:String): UInt = apply(updateData, resetData = BigInt(0), enable = true.B, Some(name))
}
| module AsyncResetRegVec_w1_i0_9( // @[AsyncResetReg.scala:56:7]
input clock, // @[AsyncResetReg.scala:56:7]
input reset // @[AsyncResetReg.scala:56:7]
);
wire _reg_T = reset; // @[AsyncResetReg.scala:61:29]
wire io_en = 1'h1; // @[AsyncResetReg.scala:56:7, :59:14]
wire io_d = 1'h0; // @[AsyncResetReg.scala:56:7]
wire io_q = 1'h0; // @[AsyncResetReg.scala:56:7]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File LazyModuleImp.scala:
package org.chipsalliance.diplomacy.lazymodule
import chisel3.{withClockAndReset, Module, RawModule, Reset, _}
import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo}
import firrtl.passes.InlineAnnotation
import org.chipsalliance.cde.config.Parameters
import org.chipsalliance.diplomacy.nodes.Dangle
import scala.collection.immutable.SortedMap
/** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]].
*
* This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy.
*/
sealed trait LazyModuleImpLike extends RawModule {
/** [[LazyModule]] that contains this instance. */
val wrapper: LazyModule
/** IOs that will be automatically "punched" for this instance. */
val auto: AutoBundle
/** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */
protected[diplomacy] val dangles: Seq[Dangle]
// [[wrapper.module]] had better not be accessed while LazyModules are still being built!
require(
LazyModule.scope.isEmpty,
s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}"
)
/** Set module name. Defaults to the containing LazyModule's desiredName. */
override def desiredName: String = wrapper.desiredName
suggestName(wrapper.suggestedName)
/** [[Parameters]] for chisel [[Module]]s. */
implicit val p: Parameters = wrapper.p
/** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and
* submodules.
*/
protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = {
// 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]],
// 2. return [[Dangle]]s from each module.
val childDangles = wrapper.children.reverse.flatMap { c =>
implicit val sourceInfo: SourceInfo = c.info
c.cloneProto.map { cp =>
// If the child is a clone, then recursively set cloneProto of its children as well
def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = {
require(bases.size == clones.size)
(bases.zip(clones)).map { case (l, r) =>
require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}")
l.cloneProto = Some(r)
assignCloneProtos(l.children, r.children)
}
}
assignCloneProtos(c.children, cp.children)
// Clone the child module as a record, and get its [[AutoBundle]]
val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName)
val clonedAuto = clone("auto").asInstanceOf[AutoBundle]
// Get the empty [[Dangle]]'s of the cloned child
val rawDangles = c.cloneDangles()
require(rawDangles.size == clonedAuto.elements.size)
// Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s
val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) }
dangles
}.getOrElse {
// For non-clones, instantiate the child module
val mod = try {
Module(c.module)
} catch {
case e: ChiselException => {
println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}")
throw e
}
}
mod.dangles
}
}
// Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]].
// This will result in a sequence of [[Dangle]] from these [[BaseNode]]s.
val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate())
// Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]]
val allDangles = nodeDangles ++ childDangles
// Group [[allDangles]] by their [[source]].
val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*)
// For each [[source]] set of [[Dangle]]s of size 2, ensure that these
// can be connected as a source-sink pair (have opposite flipped value).
// Make the connection and mark them as [[done]].
val done = Set() ++ pairing.values.filter(_.size == 2).map {
case Seq(a, b) =>
require(a.flipped != b.flipped)
// @todo <> in chisel3 makes directionless connection.
if (a.flipped) {
a.data <> b.data
} else {
b.data <> a.data
}
a.source
case _ => None
}
// Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module.
val forward = allDangles.filter(d => !done(d.source))
// Generate [[AutoBundle]] IO from [[forward]].
val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*))
// Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]]
val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) =>
if (d.flipped) {
d.data <> io
} else {
io <> d.data
}
d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name)
}
// Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]].
wrapper.inModuleBody.reverse.foreach {
_()
}
if (wrapper.shouldBeInlined) {
chisel3.experimental.annotate(new ChiselAnnotation {
def toFirrtl = InlineAnnotation(toNamed)
})
}
// Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]].
(auto, dangles)
}
}
/** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike {
/** Instantiate hardware of this `Module`. */
val (auto, dangles) = instantiate()
}
/** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike {
// These wires are the default clock+reset for all LazyModule children.
// It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the
// [[LazyRawModuleImp]] children.
// Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly.
/** drive clock explicitly. */
val childClock: Clock = Wire(Clock())
/** drive reset explicitly. */
val childReset: Reset = Wire(Reset())
// the default is that these are disabled
childClock := false.B.asClock
childReset := chisel3.DontCare
def provideImplicitClockToLazyChildren: Boolean = false
val (auto, dangles) =
if (provideImplicitClockToLazyChildren) {
withClockAndReset(childClock, childReset) { instantiate() }
} else {
instantiate()
}
}
File ClockGroupCombiner.scala:
package chipyard.clocking
import chisel3._
import chisel3.util._
import chisel3.experimental.Analog
import org.chipsalliance.cde.config._
import freechips.rocketchip.subsystem._
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.prci._
import freechips.rocketchip.util._
import freechips.rocketchip.tilelink._
import freechips.rocketchip.devices.tilelink._
import freechips.rocketchip.regmapper._
import freechips.rocketchip.subsystem._
object ClockGroupCombiner {
def apply()(implicit p: Parameters, valName: ValName): ClockGroupAdapterNode = {
LazyModule(new ClockGroupCombiner()).node
}
}
case object ClockGroupCombinerKey extends Field[Seq[(String, ClockSinkParameters => Boolean)]](Nil)
// All clock groups with a name containing any substring in names will be combined into a single clock group
class WithClockGroupsCombinedByName(groups: (String, Seq[String], Seq[String])*) extends Config((site, here, up) => {
case ClockGroupCombinerKey => groups.map { case (grouped_name, matched_names, unmatched_names) =>
(grouped_name, (m: ClockSinkParameters) => matched_names.exists(n => m.name.get.contains(n)) && !unmatched_names.exists(n => m.name.get.contains(n)))
}
})
/** This node combines sets of clock groups according to functions provided in the ClockGroupCombinerKey
* The ClockGroupCombinersKey contains a list of tuples of:
* - The name of the combined group
* - A function on the ClockSinkParameters, returning True if the associated clock group should be grouped by this node
* This node will fail if
* - Multiple grouping functions match a single clock group
* - A grouping function matches zero clock groups
* - A grouping function matches clock groups with different requested frequncies
*/
class ClockGroupCombiner(implicit p: Parameters, v: ValName) extends LazyModule {
val combiners = p(ClockGroupCombinerKey)
val sourceFn: ClockGroupSourceParameters => ClockGroupSourceParameters = { m => m }
val sinkFn: ClockGroupSinkParameters => ClockGroupSinkParameters = { u =>
var i = 0
val (grouped, rest) = combiners.map(_._2).foldLeft((Seq[ClockSinkParameters](), u.members)) { case ((grouped, rest), c) =>
val (g, r) = rest.partition(c(_))
val name = combiners(i)._1
i = i + 1
require(g.size >= 1)
val names = g.map(_.name.getOrElse("unamed"))
val takes = g.map(_.take).flatten
require(takes.distinct.size <= 1,
s"Clock group '$name' has non-homogeneous requested ClockParameters ${names.zip(takes)}")
require(takes.size > 0,
s"Clock group '$name' has no inheritable frequencies")
(grouped ++ Seq(ClockSinkParameters(take = takes.headOption, name = Some(name))), r)
}
ClockGroupSinkParameters(
name = u.name,
members = grouped ++ rest
)
}
val node = ClockGroupAdapterNode(sourceFn, sinkFn)
lazy val module = new LazyRawModuleImp(this) {
(node.out zip node.in).map { case ((o, oe), (i, ie)) =>
{
val inMap = (i.member.data zip ie.sink.members).map { case (id, im) =>
im.name.get -> id
}.toMap
(o.member.data zip oe.sink.members).map { case (od, om) =>
val matches = combiners.filter(c => c._2(om))
require(matches.size <= 1)
if (matches.size == 0) {
od := inMap(om.name.get)
} else {
od := inMap(matches(0)._1)
}
}
}
}
}
}
File MixedNode.scala:
package org.chipsalliance.diplomacy.nodes
import chisel3.{Data, DontCare, Wire}
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.{Field, Parameters}
import org.chipsalliance.diplomacy.ValName
import org.chipsalliance.diplomacy.sourceLine
/** One side metadata of a [[Dangle]].
*
* Describes one side of an edge going into or out of a [[BaseNode]].
*
* @param serial
* the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to.
* @param index
* the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to.
*/
case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] {
import scala.math.Ordered.orderingToOrdered
def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that))
}
/** [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]]
* connects.
*
* [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] ,
* [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]].
*
* @param source
* the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within
* that [[BaseNode]].
* @param sink
* sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that
* [[BaseNode]].
* @param flipped
* flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to
* `danglesIn`.
* @param dataOpt
* actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module
*/
case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) {
def data = dataOpt.get
}
/** [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often
* derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually
* implement the protocol.
*/
case class Edges[EI, EO](in: Seq[EI], out: Seq[EO])
/** A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. */
case object MonitorsEnabled extends Field[Boolean](true)
/** When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented.
*
* For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but
* [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink
* nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the
* [[LazyModule]].
*/
case object RenderFlipped extends Field[Boolean](false)
/** The sealed node class in the package, all node are derived from it.
*
* @param inner
* Sink interface implementation.
* @param outer
* Source interface implementation.
* @param valName
* val name of this node.
* @tparam DI
* Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters
* describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected
* [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port
* parameters.
* @tparam UI
* Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing
* the protocol parameters of a sink. For an [[InwardNode]], it is determined itself.
* @tparam EI
* Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers
* specified for a sink according to protocol.
* @tparam BI
* Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface.
* It should extends from [[chisel3.Data]], which represents the real hardware.
* @tparam DO
* Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters
* describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself.
* @tparam UO
* Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing
* the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]].
* Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters.
* @tparam EO
* Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers
* specified for a source according to protocol.
* @tparam BO
* Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source
* interface. It should extends from [[chisel3.Data]], which represents the real hardware.
*
* @note
* Call Graph of [[MixedNode]]
* - line `─`: source is process by a function and generate pass to others
* - Arrow `→`: target of arrow is generated by source
*
* {{{
* (from the other node)
* ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐
* ↓ │
* (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │
* [[InwardNode.accPI]] │ │ │
* │ │ (based on protocol) │
* │ │ [[MixedNode.inner.edgeI]] │
* │ │ ↓ │
* ↓ │ │ │
* (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │
* [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │
* │ │ ↑ │ │ │
* │ │ │ [[OutwardNode.doParams]] │ │
* │ │ │ (from the other node) │ │
* │ │ │ │ │ │
* │ │ │ │ │ │
* │ │ │ └────────┬──────────────┤ │
* │ │ │ │ │ │
* │ │ │ │ (based on protocol) │
* │ │ │ │ [[MixedNode.inner.edgeI]] │
* │ │ │ │ │ │
* │ │ (from the other node) │ ↓ │
* │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │
* │ ↑ ↑ │ │ ↓ │
* │ │ │ │ │ [[MixedNode.in]] │
* │ │ │ │ ↓ ↑ │
* │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │
* ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │
* │ │ │ [[MixedNode.bundleOut]]─┐ │ │
* │ │ │ ↑ ↓ │ │
* │ │ │ │ [[MixedNode.out]] │ │
* │ ↓ ↓ │ ↑ │ │
* │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │
* │ │ (from the other node) ↑ │ │
* │ │ │ │ │ │
* │ │ │ [[MixedNode.outer.edgeO]] │ │
* │ │ │ (based on protocol) │ │
* │ │ │ │ │ │
* │ │ │ ┌────────────────────────────────────────┤ │ │
* │ │ │ │ │ │ │
* │ │ │ │ │ │ │
* │ │ │ │ │ │ │
* (immobilize after elaboration)│ ↓ │ │ │ │
* [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │
* ↑ (inward port from [[OutwardNode]]) │ │ │ │
* │ ┌─────────────────────────────────────────┤ │ │ │
* │ │ │ │ │ │
* │ │ │ │ │ │
* [[OutwardNode.accPO]] │ ↓ │ │ │
* (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │
* │ ↑ │ │
* │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │
* └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘
* }}}
*/
abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data](
val inner: InwardNodeImp[DI, UI, EI, BI],
val outer: OutwardNodeImp[DO, UO, EO, BO]
)(
implicit valName: ValName)
extends BaseNode
with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO]
with InwardNode[DI, UI, BI]
with OutwardNode[DO, UO, BO] {
// Generate a [[NodeHandle]] with inward and outward node are both this node.
val inward = this
val outward = this
/** Debug info of nodes binding. */
def bindingInfo: String = s"""$iBindingInfo
|$oBindingInfo
|""".stripMargin
/** Debug info of ports connecting. */
def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}]
|${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}]
|""".stripMargin
/** Debug info of parameters propagations. */
def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}]
|${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}]
|${diParams.size} downstream inward parameters: [${diParams.mkString(",")}]
|${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}]
|""".stripMargin
/** For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and
* [[MixedNode.iPortMapping]].
*
* Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward
* stars and outward stars.
*
* This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type
* of node.
*
* @param iKnown
* Number of known-size ([[BIND_ONCE]]) input bindings.
* @param oKnown
* Number of known-size ([[BIND_ONCE]]) output bindings.
* @param iStar
* Number of unknown size ([[BIND_STAR]]) input bindings.
* @param oStar
* Number of unknown size ([[BIND_STAR]]) output bindings.
* @return
* A Tuple of the resolved number of input and output connections.
*/
protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int)
/** Function to generate downward-flowing outward params from the downward-flowing input params and the current output
* ports.
*
* @param n
* The size of the output sequence to generate.
* @param p
* Sequence of downward-flowing input parameters of this node.
* @return
* A `n`-sized sequence of downward-flowing output edge parameters.
*/
protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO]
/** Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]].
*
* @param n
* Size of the output sequence.
* @param p
* Upward-flowing output edge parameters.
* @return
* A n-sized sequence of upward-flowing input edge parameters.
*/
protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI]
/** @return
* The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with
* [[BIND_STAR]].
*/
protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR)
/** @return
* The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of
* output bindings bound with [[BIND_STAR]].
*/
protected[diplomacy] lazy val sourceCard: Int =
iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR)
/** @return list of nodes involved in flex bindings with this node. */
protected[diplomacy] lazy val flexes: Seq[BaseNode] =
oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2)
/** Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin
* greedily taking up the remaining connections.
*
* @return
* A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return
* value is not relevant.
*/
protected[diplomacy] lazy val flexOffset: Int = {
/** Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex
* operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a
* connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of
* each node in the current set and decide whether they should be added to the set or not.
*
* @return
* the mapping of [[BaseNode]] indexed by their serial numbers.
*/
def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = {
if (visited.contains(v.serial) || !v.flexibleArityDirection) {
visited
} else {
v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum))
}
}
/** Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node.
*
* @example
* {{{
* a :*=* b :*=* c
* d :*=* b
* e :*=* f
* }}}
*
* `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)`
*/
val flexSet = DFS(this, Map()).values
/** The total number of :*= operators where we're on the left. */
val allSink = flexSet.map(_.sinkCard).sum
/** The total number of :=* operators used when we're on the right. */
val allSource = flexSet.map(_.sourceCard).sum
require(
allSink == 0 || allSource == 0,
s"The nodes ${flexSet.map(_.name)} which are inter-connected by :*=* have ${allSink} :*= operators and ${allSource} :=* operators connected to them, making it impossible to determine cardinality inference direction."
)
allSink - allSource
}
/** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. */
protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = {
if (flexibleArityDirection) flexOffset
else if (n.flexibleArityDirection) n.flexOffset
else 0
}
/** For a node which is connected between two nodes, select the one that will influence the direction of the flex
* resolution.
*/
protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = {
val dir = edgeArityDirection(n)
if (dir < 0) l
else if (dir > 0) r
else 1
}
/** Ensure that the same node is not visited twice in resolving `:*=`, etc operators. */
private var starCycleGuard = false
/** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star"
* connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also
* need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct
* edge parameters and later build up correct bundle connections.
*
* [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding
* operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort
* (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N :*= foo` or `N :*=* foo :*=
* bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo :*=* N`
*/
protected[diplomacy] lazy val (
oPortMapping: Seq[(Int, Int)],
iPortMapping: Seq[(Int, Int)],
oStar: Int,
iStar: Int
) = {
try {
if (starCycleGuard) throw StarCycleException()
starCycleGuard = true
// For a given node N...
// Number of foo :=* N
// + Number of bar :=* foo :*=* N
val oStars = oBindings.count { case (_, n, b, _, _) =>
b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) < 0)
}
// Number of N :*= foo
// + Number of N :*=* foo :*= bar
val iStars = iBindings.count { case (_, n, b, _, _) =>
b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) > 0)
}
// 1 for foo := N
// + bar.iStar for bar :*= foo :*=* N
// + foo.iStar for foo :*= N
// + 0 for foo :=* N
val oKnown = oBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, 0, n.iStar)
case BIND_QUERY => n.iStar
case BIND_STAR => 0
}
}.sum
// 1 for N := foo
// + bar.oStar for N :*=* foo :=* bar
// + foo.oStar for N :=* foo
// + 0 for N :*= foo
val iKnown = iBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, n.oStar, 0)
case BIND_QUERY => n.oStar
case BIND_STAR => 0
}
}.sum
// Resolve star depends on the node subclass to implement the algorithm for this.
val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars)
// Cumulative list of resolved outward binding range starting points
val oSum = oBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar)
case BIND_QUERY => n.iStar
case BIND_STAR => oStar
}
}.scanLeft(0)(_ + _)
// Cumulative list of resolved inward binding range starting points
val iSum = iBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar)
case BIND_QUERY => n.oStar
case BIND_STAR => iStar
}
}.scanLeft(0)(_ + _)
// Create ranges for each binding based on the running sums and return
// those along with resolved values for the star operations.
(oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar)
} catch {
case c: StarCycleException => throw c.copy(loop = context +: c.loop)
}
}
/** Sequence of inward ports.
*
* This should be called after all star bindings are resolved.
*
* Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding.
* `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this
* connection was made in the source code.
*/
protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] =
oBindings.flatMap { case (i, n, _, p, s) =>
// for each binding operator in this node, look at what it connects to
val (start, end) = n.iPortMapping(i)
(start until end).map { j => (j, n, p, s) }
}
/** Sequence of outward ports.
*
* This should be called after all star bindings are resolved.
*
* `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of
* outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection
* was made in the source code.
*/
protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] =
iBindings.flatMap { case (i, n, _, p, s) =>
// query this port index range of this node in the other side of node.
val (start, end) = n.oPortMapping(i)
(start until end).map { j => (j, n, p, s) }
}
// Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree
// Thus, there must exist an Eulerian path and the below algorithms terminate
@scala.annotation.tailrec
private def oTrace(
tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)
): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match {
case (i, n, p, s) => n.iForward(i) match {
case None => (i, n, p, s)
case Some((j, m)) => oTrace((j, m, p, s))
}
}
@scala.annotation.tailrec
private def iTrace(
tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)
): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match {
case (i, n, p, s) => n.oForward(i) match {
case None => (i, n, p, s)
case Some((j, m)) => iTrace((j, m, p, s))
}
}
/** Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved.
*
* Each Port is a tuple of:
* - Numeric index of this binding in the [[InwardNode]] on the other end.
* - [[InwardNode]] on the other end of this binding.
* - A view of [[Parameters]] where the binding occurred.
* - [[SourceInfo]] for source-level error reporting.
*/
lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace)
/** Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved.
*
* Each Port is a tuple of:
* - numeric index of this binding in [[OutwardNode]] on the other end.
* - [[OutwardNode]] on the other end of this binding.
* - a view of [[Parameters]] where the binding occurred.
* - [[SourceInfo]] for source-level error reporting.
*/
lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace)
private var oParamsCycleGuard = false
protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) }
protected[diplomacy] lazy val doParams: Seq[DO] = {
try {
if (oParamsCycleGuard) throw DownwardCycleException()
oParamsCycleGuard = true
val o = mapParamsD(oPorts.size, diParams)
require(
o.size == oPorts.size,
s"""Diplomacy has detected a problem with your graph:
|At the following node, the number of outward ports should equal the number of produced outward parameters.
|$context
|$connectedPortsInfo
|Downstreamed inward parameters: [${diParams.mkString(",")}]
|Produced outward parameters: [${o.mkString(",")}]
|""".stripMargin
)
o.map(outer.mixO(_, this))
} catch {
case c: DownwardCycleException => throw c.copy(loop = context +: c.loop)
}
}
private var iParamsCycleGuard = false
protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) }
protected[diplomacy] lazy val uiParams: Seq[UI] = {
try {
if (iParamsCycleGuard) throw UpwardCycleException()
iParamsCycleGuard = true
val i = mapParamsU(iPorts.size, uoParams)
require(
i.size == iPorts.size,
s"""Diplomacy has detected a problem with your graph:
|At the following node, the number of inward ports should equal the number of produced inward parameters.
|$context
|$connectedPortsInfo
|Upstreamed outward parameters: [${uoParams.mkString(",")}]
|Produced inward parameters: [${i.mkString(",")}]
|""".stripMargin
)
i.map(inner.mixI(_, this))
} catch {
case c: UpwardCycleException => throw c.copy(loop = context +: c.loop)
}
}
/** Outward edge parameters. */
protected[diplomacy] lazy val edgesOut: Seq[EO] =
(oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) }
/** Inward edge parameters. */
protected[diplomacy] lazy val edgesIn: Seq[EI] =
(iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) }
/** A tuple of the input edge parameters and output edge parameters for the edges bound to this node.
*
* If you need to access to the edges of a foreign Node, use this method (in/out create bundles).
*/
lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut)
/** Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. */
protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e =>
val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out")
// TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue,
// In the future, we should add an option to decide whether allowing unconnected in the LazyModule
x := DontCare
x
}
/** Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. */
protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e =>
val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In")
// TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue,
// In the future, we should add an option to decide whether allowing unconnected in the LazyModule
x := DontCare
x
}
private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) =>
Dangle(
source = HalfEdge(serial, i),
sink = HalfEdge(n.serial, j),
flipped = false,
name = wirePrefix + "out",
dataOpt = None
)
}
private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) =>
Dangle(
source = HalfEdge(n.serial, j),
sink = HalfEdge(serial, i),
flipped = true,
name = wirePrefix + "in",
dataOpt = None
)
}
/** Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. */
protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) =>
d.copy(dataOpt = Some(bundleOut(i)))
}
/** Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. */
protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) =>
d.copy(dataOpt = Some(bundleIn(i)))
}
private[diplomacy] var instantiated = false
/** Gather Bundle and edge parameters of outward ports.
*
* Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within
* [[LazyModuleImp]] code or after its instantiation has completed.
*/
def out: Seq[(BO, EO)] = {
require(
instantiated,
s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun"
)
bundleOut.zip(edgesOut)
}
/** Gather Bundle and edge parameters of inward ports.
*
* Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within
* [[LazyModuleImp]] code or after its instantiation has completed.
*/
def in: Seq[(BI, EI)] = {
require(
instantiated,
s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun"
)
bundleIn.zip(edgesIn)
}
/** Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires,
* instantiate monitors on all input ports if appropriate, and return all the dangles of this node.
*/
protected[diplomacy] def instantiate(): Seq[Dangle] = {
instantiated = true
if (!circuitIdentity) {
(iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) }
}
danglesOut ++ danglesIn
}
protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn
/** Connects the outward part of a node with the inward part of this node. */
protected[diplomacy] def bind(
h: OutwardNode[DI, UI, BI],
binding: NodeBinding
)(
implicit p: Parameters,
sourceInfo: SourceInfo
): Unit = {
val x = this // x := y
val y = h
sourceLine(sourceInfo, " at ", "")
val i = x.iPushed
val o = y.oPushed
y.oPush(
i,
x,
binding match {
case BIND_ONCE => BIND_ONCE
case BIND_FLEX => BIND_FLEX
case BIND_STAR => BIND_QUERY
case BIND_QUERY => BIND_STAR
}
)
x.iPush(o, y, binding)
}
/* Metadata for printing the node graph. */
def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) =>
val re = inner.render(e)
(n, re.copy(flipped = re.flipped != p(RenderFlipped)))
}
/** Metadata for printing the node graph */
def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) }
}
| module ClockGroupCombiner( // @[ClockGroupCombiner.scala:68:25]
input auto_clock_group_combiner_in_member_allClocks_uncore_clock, // @[LazyModuleImp.scala:107:25]
input auto_clock_group_combiner_in_member_allClocks_uncore_reset, // @[LazyModuleImp.scala:107:25]
output auto_clock_group_combiner_out_member_allClocks_clockTapNode_clock_tap_clock, // @[LazyModuleImp.scala:107:25]
output auto_clock_group_combiner_out_member_allClocks_clockTapNode_clock_tap_reset, // @[LazyModuleImp.scala:107:25]
output auto_clock_group_combiner_out_member_allClocks_cbus_0_clock, // @[LazyModuleImp.scala:107:25]
output auto_clock_group_combiner_out_member_allClocks_cbus_0_reset, // @[LazyModuleImp.scala:107:25]
output auto_clock_group_combiner_out_member_allClocks_mbus_0_clock, // @[LazyModuleImp.scala:107:25]
output auto_clock_group_combiner_out_member_allClocks_mbus_0_reset, // @[LazyModuleImp.scala:107:25]
output auto_clock_group_combiner_out_member_allClocks_fbus_0_clock, // @[LazyModuleImp.scala:107:25]
output auto_clock_group_combiner_out_member_allClocks_fbus_0_reset, // @[LazyModuleImp.scala:107:25]
output auto_clock_group_combiner_out_member_allClocks_pbus_0_clock, // @[LazyModuleImp.scala:107:25]
output auto_clock_group_combiner_out_member_allClocks_pbus_0_reset, // @[LazyModuleImp.scala:107:25]
output auto_clock_group_combiner_out_member_allClocks_ccbus1_0_clock, // @[LazyModuleImp.scala:107:25]
output auto_clock_group_combiner_out_member_allClocks_ccbus1_0_reset, // @[LazyModuleImp.scala:107:25]
output auto_clock_group_combiner_out_member_allClocks_csbus1_0_clock, // @[LazyModuleImp.scala:107:25]
output auto_clock_group_combiner_out_member_allClocks_csbus1_0_reset, // @[LazyModuleImp.scala:107:25]
output auto_clock_group_combiner_out_member_allClocks_ccbus0_0_clock, // @[LazyModuleImp.scala:107:25]
output auto_clock_group_combiner_out_member_allClocks_ccbus0_0_reset, // @[LazyModuleImp.scala:107:25]
output auto_clock_group_combiner_out_member_allClocks_csbus0_0_clock, // @[LazyModuleImp.scala:107:25]
output auto_clock_group_combiner_out_member_allClocks_csbus0_0_reset, // @[LazyModuleImp.scala:107:25]
output auto_clock_group_combiner_out_member_allClocks_sbus_1_clock, // @[LazyModuleImp.scala:107:25]
output auto_clock_group_combiner_out_member_allClocks_sbus_1_reset, // @[LazyModuleImp.scala:107:25]
output auto_clock_group_combiner_out_member_allClocks_sbus_0_clock, // @[LazyModuleImp.scala:107:25]
output auto_clock_group_combiner_out_member_allClocks_sbus_0_reset // @[LazyModuleImp.scala:107:25]
);
wire auto_clock_group_combiner_in_member_allClocks_uncore_clock_0 = auto_clock_group_combiner_in_member_allClocks_uncore_clock; // @[ClockGroupCombiner.scala:68:25]
wire auto_clock_group_combiner_in_member_allClocks_uncore_reset_0 = auto_clock_group_combiner_in_member_allClocks_uncore_reset; // @[ClockGroupCombiner.scala:68:25]
wire childClock = 1'h0; // @[LazyModuleImp.scala:155:31]
wire childReset = 1'h0; // @[LazyModuleImp.scala:158:31]
wire _childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25]
wire clockGroupCombinerIn_member_allClocks_uncore_clock = auto_clock_group_combiner_in_member_allClocks_uncore_clock_0; // @[MixedNode.scala:551:17]
wire clockGroupCombinerIn_member_allClocks_uncore_reset = auto_clock_group_combiner_in_member_allClocks_uncore_reset_0; // @[MixedNode.scala:551:17]
wire clockGroupCombinerOut_member_allClocks_clockTapNode_clock_tap_clock; // @[MixedNode.scala:542:17]
wire clockGroupCombinerOut_member_allClocks_clockTapNode_clock_tap_reset; // @[MixedNode.scala:542:17]
wire clockGroupCombinerOut_member_allClocks_cbus_0_clock; // @[MixedNode.scala:542:17]
wire clockGroupCombinerOut_member_allClocks_cbus_0_reset; // @[MixedNode.scala:542:17]
wire clockGroupCombinerOut_member_allClocks_mbus_0_clock; // @[MixedNode.scala:542:17]
wire clockGroupCombinerOut_member_allClocks_mbus_0_reset; // @[MixedNode.scala:542:17]
wire clockGroupCombinerOut_member_allClocks_fbus_0_clock; // @[MixedNode.scala:542:17]
wire clockGroupCombinerOut_member_allClocks_fbus_0_reset; // @[MixedNode.scala:542:17]
wire clockGroupCombinerOut_member_allClocks_pbus_0_clock; // @[MixedNode.scala:542:17]
wire clockGroupCombinerOut_member_allClocks_pbus_0_reset; // @[MixedNode.scala:542:17]
wire clockGroupCombinerOut_member_allClocks_ccbus1_0_clock; // @[MixedNode.scala:542:17]
wire clockGroupCombinerOut_member_allClocks_ccbus1_0_reset; // @[MixedNode.scala:542:17]
wire clockGroupCombinerOut_member_allClocks_csbus1_0_clock; // @[MixedNode.scala:542:17]
wire clockGroupCombinerOut_member_allClocks_csbus1_0_reset; // @[MixedNode.scala:542:17]
wire clockGroupCombinerOut_member_allClocks_ccbus0_0_clock; // @[MixedNode.scala:542:17]
wire clockGroupCombinerOut_member_allClocks_ccbus0_0_reset; // @[MixedNode.scala:542:17]
wire clockGroupCombinerOut_member_allClocks_csbus0_0_clock; // @[MixedNode.scala:542:17]
wire clockGroupCombinerOut_member_allClocks_csbus0_0_reset; // @[MixedNode.scala:542:17]
wire clockGroupCombinerOut_member_allClocks_sbus_1_clock; // @[MixedNode.scala:542:17]
wire clockGroupCombinerOut_member_allClocks_sbus_1_reset; // @[MixedNode.scala:542:17]
wire clockGroupCombinerOut_member_allClocks_sbus_0_clock; // @[MixedNode.scala:542:17]
wire clockGroupCombinerOut_member_allClocks_sbus_0_reset; // @[MixedNode.scala:542:17]
wire auto_clock_group_combiner_out_member_allClocks_clockTapNode_clock_tap_clock_0; // @[ClockGroupCombiner.scala:68:25]
wire auto_clock_group_combiner_out_member_allClocks_clockTapNode_clock_tap_reset_0; // @[ClockGroupCombiner.scala:68:25]
wire auto_clock_group_combiner_out_member_allClocks_cbus_0_clock_0; // @[ClockGroupCombiner.scala:68:25]
wire auto_clock_group_combiner_out_member_allClocks_cbus_0_reset_0; // @[ClockGroupCombiner.scala:68:25]
wire auto_clock_group_combiner_out_member_allClocks_mbus_0_clock_0; // @[ClockGroupCombiner.scala:68:25]
wire auto_clock_group_combiner_out_member_allClocks_mbus_0_reset_0; // @[ClockGroupCombiner.scala:68:25]
wire auto_clock_group_combiner_out_member_allClocks_fbus_0_clock_0; // @[ClockGroupCombiner.scala:68:25]
wire auto_clock_group_combiner_out_member_allClocks_fbus_0_reset_0; // @[ClockGroupCombiner.scala:68:25]
wire auto_clock_group_combiner_out_member_allClocks_pbus_0_clock_0; // @[ClockGroupCombiner.scala:68:25]
wire auto_clock_group_combiner_out_member_allClocks_pbus_0_reset_0; // @[ClockGroupCombiner.scala:68:25]
wire auto_clock_group_combiner_out_member_allClocks_ccbus1_0_clock_0; // @[ClockGroupCombiner.scala:68:25]
wire auto_clock_group_combiner_out_member_allClocks_ccbus1_0_reset_0; // @[ClockGroupCombiner.scala:68:25]
wire auto_clock_group_combiner_out_member_allClocks_csbus1_0_clock_0; // @[ClockGroupCombiner.scala:68:25]
wire auto_clock_group_combiner_out_member_allClocks_csbus1_0_reset_0; // @[ClockGroupCombiner.scala:68:25]
wire auto_clock_group_combiner_out_member_allClocks_ccbus0_0_clock_0; // @[ClockGroupCombiner.scala:68:25]
wire auto_clock_group_combiner_out_member_allClocks_ccbus0_0_reset_0; // @[ClockGroupCombiner.scala:68:25]
wire auto_clock_group_combiner_out_member_allClocks_csbus0_0_clock_0; // @[ClockGroupCombiner.scala:68:25]
wire auto_clock_group_combiner_out_member_allClocks_csbus0_0_reset_0; // @[ClockGroupCombiner.scala:68:25]
wire auto_clock_group_combiner_out_member_allClocks_sbus_1_clock_0; // @[ClockGroupCombiner.scala:68:25]
wire auto_clock_group_combiner_out_member_allClocks_sbus_1_reset_0; // @[ClockGroupCombiner.scala:68:25]
wire auto_clock_group_combiner_out_member_allClocks_sbus_0_clock_0; // @[ClockGroupCombiner.scala:68:25]
wire auto_clock_group_combiner_out_member_allClocks_sbus_0_reset_0; // @[ClockGroupCombiner.scala:68:25]
assign clockGroupCombinerOut_member_allClocks_clockTapNode_clock_tap_clock = clockGroupCombinerIn_member_allClocks_uncore_clock; // @[MixedNode.scala:542:17, :551:17]
assign clockGroupCombinerOut_member_allClocks_cbus_0_clock = clockGroupCombinerIn_member_allClocks_uncore_clock; // @[MixedNode.scala:542:17, :551:17]
assign clockGroupCombinerOut_member_allClocks_mbus_0_clock = clockGroupCombinerIn_member_allClocks_uncore_clock; // @[MixedNode.scala:542:17, :551:17]
assign clockGroupCombinerOut_member_allClocks_fbus_0_clock = clockGroupCombinerIn_member_allClocks_uncore_clock; // @[MixedNode.scala:542:17, :551:17]
assign clockGroupCombinerOut_member_allClocks_pbus_0_clock = clockGroupCombinerIn_member_allClocks_uncore_clock; // @[MixedNode.scala:542:17, :551:17]
assign clockGroupCombinerOut_member_allClocks_ccbus1_0_clock = clockGroupCombinerIn_member_allClocks_uncore_clock; // @[MixedNode.scala:542:17, :551:17]
assign clockGroupCombinerOut_member_allClocks_csbus1_0_clock = clockGroupCombinerIn_member_allClocks_uncore_clock; // @[MixedNode.scala:542:17, :551:17]
assign clockGroupCombinerOut_member_allClocks_ccbus0_0_clock = clockGroupCombinerIn_member_allClocks_uncore_clock; // @[MixedNode.scala:542:17, :551:17]
assign clockGroupCombinerOut_member_allClocks_csbus0_0_clock = clockGroupCombinerIn_member_allClocks_uncore_clock; // @[MixedNode.scala:542:17, :551:17]
assign clockGroupCombinerOut_member_allClocks_sbus_1_clock = clockGroupCombinerIn_member_allClocks_uncore_clock; // @[MixedNode.scala:542:17, :551:17]
assign clockGroupCombinerOut_member_allClocks_sbus_0_clock = clockGroupCombinerIn_member_allClocks_uncore_clock; // @[MixedNode.scala:542:17, :551:17]
assign clockGroupCombinerOut_member_allClocks_clockTapNode_clock_tap_reset = clockGroupCombinerIn_member_allClocks_uncore_reset; // @[MixedNode.scala:542:17, :551:17]
assign clockGroupCombinerOut_member_allClocks_cbus_0_reset = clockGroupCombinerIn_member_allClocks_uncore_reset; // @[MixedNode.scala:542:17, :551:17]
assign clockGroupCombinerOut_member_allClocks_mbus_0_reset = clockGroupCombinerIn_member_allClocks_uncore_reset; // @[MixedNode.scala:542:17, :551:17]
assign clockGroupCombinerOut_member_allClocks_fbus_0_reset = clockGroupCombinerIn_member_allClocks_uncore_reset; // @[MixedNode.scala:542:17, :551:17]
assign clockGroupCombinerOut_member_allClocks_pbus_0_reset = clockGroupCombinerIn_member_allClocks_uncore_reset; // @[MixedNode.scala:542:17, :551:17]
assign clockGroupCombinerOut_member_allClocks_ccbus1_0_reset = clockGroupCombinerIn_member_allClocks_uncore_reset; // @[MixedNode.scala:542:17, :551:17]
assign clockGroupCombinerOut_member_allClocks_csbus1_0_reset = clockGroupCombinerIn_member_allClocks_uncore_reset; // @[MixedNode.scala:542:17, :551:17]
assign clockGroupCombinerOut_member_allClocks_ccbus0_0_reset = clockGroupCombinerIn_member_allClocks_uncore_reset; // @[MixedNode.scala:542:17, :551:17]
assign clockGroupCombinerOut_member_allClocks_csbus0_0_reset = clockGroupCombinerIn_member_allClocks_uncore_reset; // @[MixedNode.scala:542:17, :551:17]
assign clockGroupCombinerOut_member_allClocks_sbus_1_reset = clockGroupCombinerIn_member_allClocks_uncore_reset; // @[MixedNode.scala:542:17, :551:17]
assign clockGroupCombinerOut_member_allClocks_sbus_0_reset = clockGroupCombinerIn_member_allClocks_uncore_reset; // @[MixedNode.scala:542:17, :551:17]
assign auto_clock_group_combiner_out_member_allClocks_clockTapNode_clock_tap_clock_0 = clockGroupCombinerOut_member_allClocks_clockTapNode_clock_tap_clock; // @[MixedNode.scala:542:17]
assign auto_clock_group_combiner_out_member_allClocks_clockTapNode_clock_tap_reset_0 = clockGroupCombinerOut_member_allClocks_clockTapNode_clock_tap_reset; // @[MixedNode.scala:542:17]
assign auto_clock_group_combiner_out_member_allClocks_cbus_0_clock_0 = clockGroupCombinerOut_member_allClocks_cbus_0_clock; // @[MixedNode.scala:542:17]
assign auto_clock_group_combiner_out_member_allClocks_cbus_0_reset_0 = clockGroupCombinerOut_member_allClocks_cbus_0_reset; // @[MixedNode.scala:542:17]
assign auto_clock_group_combiner_out_member_allClocks_mbus_0_clock_0 = clockGroupCombinerOut_member_allClocks_mbus_0_clock; // @[MixedNode.scala:542:17]
assign auto_clock_group_combiner_out_member_allClocks_mbus_0_reset_0 = clockGroupCombinerOut_member_allClocks_mbus_0_reset; // @[MixedNode.scala:542:17]
assign auto_clock_group_combiner_out_member_allClocks_fbus_0_clock_0 = clockGroupCombinerOut_member_allClocks_fbus_0_clock; // @[MixedNode.scala:542:17]
assign auto_clock_group_combiner_out_member_allClocks_fbus_0_reset_0 = clockGroupCombinerOut_member_allClocks_fbus_0_reset; // @[MixedNode.scala:542:17]
assign auto_clock_group_combiner_out_member_allClocks_pbus_0_clock_0 = clockGroupCombinerOut_member_allClocks_pbus_0_clock; // @[MixedNode.scala:542:17]
assign auto_clock_group_combiner_out_member_allClocks_pbus_0_reset_0 = clockGroupCombinerOut_member_allClocks_pbus_0_reset; // @[MixedNode.scala:542:17]
assign auto_clock_group_combiner_out_member_allClocks_ccbus1_0_clock_0 = clockGroupCombinerOut_member_allClocks_ccbus1_0_clock; // @[MixedNode.scala:542:17]
assign auto_clock_group_combiner_out_member_allClocks_ccbus1_0_reset_0 = clockGroupCombinerOut_member_allClocks_ccbus1_0_reset; // @[MixedNode.scala:542:17]
assign auto_clock_group_combiner_out_member_allClocks_csbus1_0_clock_0 = clockGroupCombinerOut_member_allClocks_csbus1_0_clock; // @[MixedNode.scala:542:17]
assign auto_clock_group_combiner_out_member_allClocks_csbus1_0_reset_0 = clockGroupCombinerOut_member_allClocks_csbus1_0_reset; // @[MixedNode.scala:542:17]
assign auto_clock_group_combiner_out_member_allClocks_ccbus0_0_clock_0 = clockGroupCombinerOut_member_allClocks_ccbus0_0_clock; // @[MixedNode.scala:542:17]
assign auto_clock_group_combiner_out_member_allClocks_ccbus0_0_reset_0 = clockGroupCombinerOut_member_allClocks_ccbus0_0_reset; // @[MixedNode.scala:542:17]
assign auto_clock_group_combiner_out_member_allClocks_csbus0_0_clock_0 = clockGroupCombinerOut_member_allClocks_csbus0_0_clock; // @[MixedNode.scala:542:17]
assign auto_clock_group_combiner_out_member_allClocks_csbus0_0_reset_0 = clockGroupCombinerOut_member_allClocks_csbus0_0_reset; // @[MixedNode.scala:542:17]
assign auto_clock_group_combiner_out_member_allClocks_sbus_1_clock_0 = clockGroupCombinerOut_member_allClocks_sbus_1_clock; // @[MixedNode.scala:542:17]
assign auto_clock_group_combiner_out_member_allClocks_sbus_1_reset_0 = clockGroupCombinerOut_member_allClocks_sbus_1_reset; // @[MixedNode.scala:542:17]
assign auto_clock_group_combiner_out_member_allClocks_sbus_0_clock_0 = clockGroupCombinerOut_member_allClocks_sbus_0_clock; // @[MixedNode.scala:542:17]
assign auto_clock_group_combiner_out_member_allClocks_sbus_0_reset_0 = clockGroupCombinerOut_member_allClocks_sbus_0_reset; // @[MixedNode.scala:542:17]
assign auto_clock_group_combiner_out_member_allClocks_clockTapNode_clock_tap_clock = auto_clock_group_combiner_out_member_allClocks_clockTapNode_clock_tap_clock_0; // @[ClockGroupCombiner.scala:68:25]
assign auto_clock_group_combiner_out_member_allClocks_clockTapNode_clock_tap_reset = auto_clock_group_combiner_out_member_allClocks_clockTapNode_clock_tap_reset_0; // @[ClockGroupCombiner.scala:68:25]
assign auto_clock_group_combiner_out_member_allClocks_cbus_0_clock = auto_clock_group_combiner_out_member_allClocks_cbus_0_clock_0; // @[ClockGroupCombiner.scala:68:25]
assign auto_clock_group_combiner_out_member_allClocks_cbus_0_reset = auto_clock_group_combiner_out_member_allClocks_cbus_0_reset_0; // @[ClockGroupCombiner.scala:68:25]
assign auto_clock_group_combiner_out_member_allClocks_mbus_0_clock = auto_clock_group_combiner_out_member_allClocks_mbus_0_clock_0; // @[ClockGroupCombiner.scala:68:25]
assign auto_clock_group_combiner_out_member_allClocks_mbus_0_reset = auto_clock_group_combiner_out_member_allClocks_mbus_0_reset_0; // @[ClockGroupCombiner.scala:68:25]
assign auto_clock_group_combiner_out_member_allClocks_fbus_0_clock = auto_clock_group_combiner_out_member_allClocks_fbus_0_clock_0; // @[ClockGroupCombiner.scala:68:25]
assign auto_clock_group_combiner_out_member_allClocks_fbus_0_reset = auto_clock_group_combiner_out_member_allClocks_fbus_0_reset_0; // @[ClockGroupCombiner.scala:68:25]
assign auto_clock_group_combiner_out_member_allClocks_pbus_0_clock = auto_clock_group_combiner_out_member_allClocks_pbus_0_clock_0; // @[ClockGroupCombiner.scala:68:25]
assign auto_clock_group_combiner_out_member_allClocks_pbus_0_reset = auto_clock_group_combiner_out_member_allClocks_pbus_0_reset_0; // @[ClockGroupCombiner.scala:68:25]
assign auto_clock_group_combiner_out_member_allClocks_ccbus1_0_clock = auto_clock_group_combiner_out_member_allClocks_ccbus1_0_clock_0; // @[ClockGroupCombiner.scala:68:25]
assign auto_clock_group_combiner_out_member_allClocks_ccbus1_0_reset = auto_clock_group_combiner_out_member_allClocks_ccbus1_0_reset_0; // @[ClockGroupCombiner.scala:68:25]
assign auto_clock_group_combiner_out_member_allClocks_csbus1_0_clock = auto_clock_group_combiner_out_member_allClocks_csbus1_0_clock_0; // @[ClockGroupCombiner.scala:68:25]
assign auto_clock_group_combiner_out_member_allClocks_csbus1_0_reset = auto_clock_group_combiner_out_member_allClocks_csbus1_0_reset_0; // @[ClockGroupCombiner.scala:68:25]
assign auto_clock_group_combiner_out_member_allClocks_ccbus0_0_clock = auto_clock_group_combiner_out_member_allClocks_ccbus0_0_clock_0; // @[ClockGroupCombiner.scala:68:25]
assign auto_clock_group_combiner_out_member_allClocks_ccbus0_0_reset = auto_clock_group_combiner_out_member_allClocks_ccbus0_0_reset_0; // @[ClockGroupCombiner.scala:68:25]
assign auto_clock_group_combiner_out_member_allClocks_csbus0_0_clock = auto_clock_group_combiner_out_member_allClocks_csbus0_0_clock_0; // @[ClockGroupCombiner.scala:68:25]
assign auto_clock_group_combiner_out_member_allClocks_csbus0_0_reset = auto_clock_group_combiner_out_member_allClocks_csbus0_0_reset_0; // @[ClockGroupCombiner.scala:68:25]
assign auto_clock_group_combiner_out_member_allClocks_sbus_1_clock = auto_clock_group_combiner_out_member_allClocks_sbus_1_clock_0; // @[ClockGroupCombiner.scala:68:25]
assign auto_clock_group_combiner_out_member_allClocks_sbus_1_reset = auto_clock_group_combiner_out_member_allClocks_sbus_1_reset_0; // @[ClockGroupCombiner.scala:68:25]
assign auto_clock_group_combiner_out_member_allClocks_sbus_0_clock = auto_clock_group_combiner_out_member_allClocks_sbus_0_clock_0; // @[ClockGroupCombiner.scala:68:25]
assign auto_clock_group_combiner_out_member_allClocks_sbus_0_reset = auto_clock_group_combiner_out_member_allClocks_sbus_0_reset_0; // @[ClockGroupCombiner.scala:68:25]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File package.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip
import chisel3._
import chisel3.util._
import scala.math.min
import scala.collection.{immutable, mutable}
package object util {
implicit class UnzippableOption[S, T](val x: Option[(S, T)]) {
def unzip = (x.map(_._1), x.map(_._2))
}
implicit class UIntIsOneOf(private val x: UInt) extends AnyVal {
def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR
def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq)
}
implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal {
/** Like Vec.apply(idx), but tolerates indices of mismatched width */
def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0))
}
implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal {
def apply(idx: UInt): T = {
if (x.size <= 1) {
x.head
} else if (!isPow2(x.size)) {
// For non-power-of-2 seqs, reflect elements to simplify decoder
(x ++ x.takeRight(x.size & -x.size)).toSeq(idx)
} else {
// Ignore MSBs of idx
val truncIdx =
if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx
else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0)
x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) }
}
}
def extract(idx: UInt): T = VecInit(x).extract(idx)
def asUInt: UInt = Cat(x.map(_.asUInt).reverse)
def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n)
def rotate(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n)
def rotateRight(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
}
// allow bitwise ops on Seq[Bool] just like UInt
implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal {
def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b }
def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b }
def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b }
def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x
def >> (n: Int): Seq[Bool] = x drop n
def unary_~ : Seq[Bool] = x.map(!_)
def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_)
def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_)
def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_)
private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B)
}
implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal {
def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable))
def getElements: Seq[Element] = x match {
case e: Element => Seq(e)
case a: Aggregate => a.getElements.flatMap(_.getElements)
}
}
/** Any Data subtype that has a Bool member named valid. */
type DataCanBeValid = Data { val valid: Bool }
implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal {
def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable)
}
implicit class StringToAugmentedString(private val x: String) extends AnyVal {
/** converts from camel case to to underscores, also removing all spaces */
def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") {
case (acc, c) if c.isUpper => acc + "_" + c.toLower
case (acc, c) if c == ' ' => acc
case (acc, c) => acc + c
}
/** converts spaces or underscores to hyphens, also lowering case */
def kebab: String = x.toLowerCase map {
case ' ' => '-'
case '_' => '-'
case c => c
}
def named(name: Option[String]): String = {
x + name.map("_named_" + _ ).getOrElse("_with_no_name")
}
def named(name: String): String = named(Some(name))
}
implicit def uintToBitPat(x: UInt): BitPat = BitPat(x)
implicit def wcToUInt(c: WideCounter): UInt = c.value
implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal {
def sextTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x)
}
def padTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(0.U((n - x.getWidth).W), x)
}
// shifts left by n if n >= 0, or right by -n if n < 0
def << (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << n(w-1, 0)
Mux(n(w), shifted >> (1 << w), shifted)
}
// shifts right by n if n >= 0, or left by -n if n < 0
def >> (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << (1 << w) >> n(w-1, 0)
Mux(n(w), shifted, shifted >> (1 << w))
}
// Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts
def extract(hi: Int, lo: Int): UInt = {
require(hi >= lo-1)
if (hi == lo-1) 0.U
else x(hi, lo)
}
// Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts
def extractOption(hi: Int, lo: Int): Option[UInt] = {
require(hi >= lo-1)
if (hi == lo-1) None
else Some(x(hi, lo))
}
// like x & ~y, but first truncate or zero-extend y to x's width
def andNot(y: UInt): UInt = x & ~(y | (x & 0.U))
def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n)
def rotateRight(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r))
}
}
def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n))
def rotateLeft(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r))
}
}
// compute (this + y) % n, given (this < n) and (y < n)
def addWrap(y: UInt, n: Int): UInt = {
val z = x +& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0)
}
// compute (this - y) % n, given (this < n) and (y < n)
def subWrap(y: UInt, n: Int): UInt = {
val z = x -& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0)
}
def grouped(width: Int): Seq[UInt] =
(0 until x.getWidth by width).map(base => x(base + width - 1, base))
def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds
def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x)
// Like >=, but prevents x-prop for ('x >= 0)
def >== (y: UInt): Bool = x >= y || y === 0.U
}
implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal {
def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y)
def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y)
}
implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal {
def toInt: Int = if (x) 1 else 0
// this one's snagged from scalaz
def option[T](z: => T): Option[T] = if (x) Some(z) else None
}
implicit class IntToAugmentedInt(private val x: Int) extends AnyVal {
// exact log2
def log2: Int = {
require(isPow2(x))
log2Ceil(x)
}
}
def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x)
def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x))
def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0)
def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1)
def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None
// Fill 1s from low bits to high bits
def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth)
def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0))
helper(1, x)(width-1, 0)
}
// Fill 1s form high bits to low bits
def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth)
def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x >> s))
helper(1, x)(width-1, 0)
}
def OptimizationBarrier[T <: Data](in: T): T = {
val barrier = Module(new Module {
val io = IO(new Bundle {
val x = Input(chiselTypeOf(in))
val y = Output(chiselTypeOf(in))
})
io.y := io.x
override def desiredName = s"OptimizationBarrier_${in.typeName}"
})
barrier.io.x := in
barrier.io.y
}
/** Similar to Seq.groupBy except this returns a Seq instead of a Map
* Useful for deterministic code generation
*/
def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = {
val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]]
for (x <- xs) {
val key = f(x)
val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A])
l += x
}
map.view.map({ case (k, vs) => k -> vs.toList }).toList
}
def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match {
case 1 => List.fill(n)(in.head)
case x if x == n => in
case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in")
}
// HeterogeneousBag moved to standalond diplomacy
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts)
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag
}
| module OptimizationBarrier_TLBEntryData_131( // @[package.scala:267:30]
input clock, // @[package.scala:267:30]
input reset, // @[package.scala:267:30]
input [19:0] io_x_ppn, // @[package.scala:268:18]
input io_x_u, // @[package.scala:268:18]
input io_x_g, // @[package.scala:268:18]
input io_x_ae_ptw, // @[package.scala:268:18]
input io_x_ae_final, // @[package.scala:268:18]
input io_x_ae_stage2, // @[package.scala:268:18]
input io_x_pf, // @[package.scala:268:18]
input io_x_gf, // @[package.scala:268:18]
input io_x_sw, // @[package.scala:268:18]
input io_x_sx, // @[package.scala:268:18]
input io_x_sr, // @[package.scala:268:18]
input io_x_hw, // @[package.scala:268:18]
input io_x_hx, // @[package.scala:268:18]
input io_x_hr, // @[package.scala:268:18]
input io_x_pw, // @[package.scala:268:18]
input io_x_px, // @[package.scala:268:18]
input io_x_pr, // @[package.scala:268:18]
input io_x_ppp, // @[package.scala:268:18]
input io_x_pal, // @[package.scala:268:18]
input io_x_paa, // @[package.scala:268:18]
input io_x_eff, // @[package.scala:268:18]
input io_x_c, // @[package.scala:268:18]
input io_x_fragmented_superpage, // @[package.scala:268:18]
output [19:0] io_y_ppn, // @[package.scala:268:18]
output io_y_u, // @[package.scala:268:18]
output io_y_ae_ptw, // @[package.scala:268:18]
output io_y_ae_final, // @[package.scala:268:18]
output io_y_ae_stage2, // @[package.scala:268:18]
output io_y_pf, // @[package.scala:268:18]
output io_y_gf, // @[package.scala:268:18]
output io_y_sw, // @[package.scala:268:18]
output io_y_sx, // @[package.scala:268:18]
output io_y_sr, // @[package.scala:268:18]
output io_y_hw, // @[package.scala:268:18]
output io_y_hx, // @[package.scala:268:18]
output io_y_hr, // @[package.scala:268:18]
output io_y_pw, // @[package.scala:268:18]
output io_y_px, // @[package.scala:268:18]
output io_y_pr, // @[package.scala:268:18]
output io_y_ppp, // @[package.scala:268:18]
output io_y_pal, // @[package.scala:268:18]
output io_y_paa, // @[package.scala:268:18]
output io_y_eff, // @[package.scala:268:18]
output io_y_c // @[package.scala:268:18]
);
wire [19:0] io_x_ppn_0 = io_x_ppn; // @[package.scala:267:30]
wire io_x_u_0 = io_x_u; // @[package.scala:267:30]
wire io_x_g_0 = io_x_g; // @[package.scala:267:30]
wire io_x_ae_ptw_0 = io_x_ae_ptw; // @[package.scala:267:30]
wire io_x_ae_final_0 = io_x_ae_final; // @[package.scala:267:30]
wire io_x_ae_stage2_0 = io_x_ae_stage2; // @[package.scala:267:30]
wire io_x_pf_0 = io_x_pf; // @[package.scala:267:30]
wire io_x_gf_0 = io_x_gf; // @[package.scala:267:30]
wire io_x_sw_0 = io_x_sw; // @[package.scala:267:30]
wire io_x_sx_0 = io_x_sx; // @[package.scala:267:30]
wire io_x_sr_0 = io_x_sr; // @[package.scala:267:30]
wire io_x_hw_0 = io_x_hw; // @[package.scala:267:30]
wire io_x_hx_0 = io_x_hx; // @[package.scala:267:30]
wire io_x_hr_0 = io_x_hr; // @[package.scala:267:30]
wire io_x_pw_0 = io_x_pw; // @[package.scala:267:30]
wire io_x_px_0 = io_x_px; // @[package.scala:267:30]
wire io_x_pr_0 = io_x_pr; // @[package.scala:267:30]
wire io_x_ppp_0 = io_x_ppp; // @[package.scala:267:30]
wire io_x_pal_0 = io_x_pal; // @[package.scala:267:30]
wire io_x_paa_0 = io_x_paa; // @[package.scala:267:30]
wire io_x_eff_0 = io_x_eff; // @[package.scala:267:30]
wire io_x_c_0 = io_x_c; // @[package.scala:267:30]
wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage; // @[package.scala:267:30]
wire [19:0] io_y_ppn_0 = io_x_ppn_0; // @[package.scala:267:30]
wire io_y_u_0 = io_x_u_0; // @[package.scala:267:30]
wire io_y_g = io_x_g_0; // @[package.scala:267:30]
wire io_y_ae_ptw_0 = io_x_ae_ptw_0; // @[package.scala:267:30]
wire io_y_ae_final_0 = io_x_ae_final_0; // @[package.scala:267:30]
wire io_y_ae_stage2_0 = io_x_ae_stage2_0; // @[package.scala:267:30]
wire io_y_pf_0 = io_x_pf_0; // @[package.scala:267:30]
wire io_y_gf_0 = io_x_gf_0; // @[package.scala:267:30]
wire io_y_sw_0 = io_x_sw_0; // @[package.scala:267:30]
wire io_y_sx_0 = io_x_sx_0; // @[package.scala:267:30]
wire io_y_sr_0 = io_x_sr_0; // @[package.scala:267:30]
wire io_y_hw_0 = io_x_hw_0; // @[package.scala:267:30]
wire io_y_hx_0 = io_x_hx_0; // @[package.scala:267:30]
wire io_y_hr_0 = io_x_hr_0; // @[package.scala:267:30]
wire io_y_pw_0 = io_x_pw_0; // @[package.scala:267:30]
wire io_y_px_0 = io_x_px_0; // @[package.scala:267:30]
wire io_y_pr_0 = io_x_pr_0; // @[package.scala:267:30]
wire io_y_ppp_0 = io_x_ppp_0; // @[package.scala:267:30]
wire io_y_pal_0 = io_x_pal_0; // @[package.scala:267:30]
wire io_y_paa_0 = io_x_paa_0; // @[package.scala:267:30]
wire io_y_eff_0 = io_x_eff_0; // @[package.scala:267:30]
wire io_y_c_0 = io_x_c_0; // @[package.scala:267:30]
wire io_y_fragmented_superpage = io_x_fragmented_superpage_0; // @[package.scala:267:30]
assign io_y_ppn = io_y_ppn_0; // @[package.scala:267:30]
assign io_y_u = io_y_u_0; // @[package.scala:267:30]
assign io_y_ae_ptw = io_y_ae_ptw_0; // @[package.scala:267:30]
assign io_y_ae_final = io_y_ae_final_0; // @[package.scala:267:30]
assign io_y_ae_stage2 = io_y_ae_stage2_0; // @[package.scala:267:30]
assign io_y_pf = io_y_pf_0; // @[package.scala:267:30]
assign io_y_gf = io_y_gf_0; // @[package.scala:267:30]
assign io_y_sw = io_y_sw_0; // @[package.scala:267:30]
assign io_y_sx = io_y_sx_0; // @[package.scala:267:30]
assign io_y_sr = io_y_sr_0; // @[package.scala:267:30]
assign io_y_hw = io_y_hw_0; // @[package.scala:267:30]
assign io_y_hx = io_y_hx_0; // @[package.scala:267:30]
assign io_y_hr = io_y_hr_0; // @[package.scala:267:30]
assign io_y_pw = io_y_pw_0; // @[package.scala:267:30]
assign io_y_px = io_y_px_0; // @[package.scala:267:30]
assign io_y_pr = io_y_pr_0; // @[package.scala:267:30]
assign io_y_ppp = io_y_ppp_0; // @[package.scala:267:30]
assign io_y_pal = io_y_pal_0; // @[package.scala:267:30]
assign io_y_paa = io_y_paa_0; // @[package.scala:267:30]
assign io_y_eff = io_y_eff_0; // @[package.scala:267:30]
assign io_y_c = io_y_c_0; // @[package.scala:267:30]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File UnsafeAXI4ToTL.scala:
package ara
import chisel3._
import chisel3.util._
import freechips.rocketchip.amba._
import freechips.rocketchip.amba.axi4._
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.tilelink._
import freechips.rocketchip.util._
class ReorderData(val dataWidth: Int, val respWidth: Int, val userFields: Seq[BundleFieldBase]) extends Bundle {
val data = UInt(dataWidth.W)
val resp = UInt(respWidth.W)
val last = Bool()
val user = BundleMap(userFields)
}
/** Parameters for [[BaseReservableListBuffer]] and all child classes.
*
* @param numEntries Total number of elements that can be stored in the 'data' RAM
* @param numLists Maximum number of linked lists
* @param numBeats Maximum number of beats per entry
*/
case class ReservableListBufferParameters(numEntries: Int, numLists: Int, numBeats: Int) {
// Avoid zero-width wires when we call 'log2Ceil'
val entryBits = if (numEntries == 1) 1 else log2Ceil(numEntries)
val listBits = if (numLists == 1) 1 else log2Ceil(numLists)
val beatBits = if (numBeats == 1) 1 else log2Ceil(numBeats)
}
case class UnsafeAXI4ToTLNode(numTlTxns: Int, wcorrupt: Boolean)(implicit valName: ValName)
extends MixedAdapterNode(AXI4Imp, TLImp)(
dFn = { case mp =>
TLMasterPortParameters.v2(
masters = mp.masters.zipWithIndex.map { case (m, i) =>
// Support 'numTlTxns' read requests and 'numTlTxns' write requests at once.
val numSourceIds = numTlTxns * 2
TLMasterParameters.v2(
name = m.name,
sourceId = IdRange(i * numSourceIds, (i + 1) * numSourceIds),
nodePath = m.nodePath
)
},
echoFields = mp.echoFields,
requestFields = AMBAProtField() +: mp.requestFields,
responseKeys = mp.responseKeys
)
},
uFn = { mp =>
AXI4SlavePortParameters(
slaves = mp.managers.map { m =>
val maxXfer = TransferSizes(1, mp.beatBytes * (1 << AXI4Parameters.lenBits))
AXI4SlaveParameters(
address = m.address,
resources = m.resources,
regionType = m.regionType,
executable = m.executable,
nodePath = m.nodePath,
supportsWrite = m.supportsPutPartial.intersect(maxXfer),
supportsRead = m.supportsGet.intersect(maxXfer),
interleavedId = Some(0) // TL2 never interleaves D beats
)
},
beatBytes = mp.beatBytes,
minLatency = mp.minLatency,
responseFields = mp.responseFields,
requestKeys = (if (wcorrupt) Seq(AMBACorrupt) else Seq()) ++ mp.requestKeys.filter(_ != AMBAProt)
)
}
)
class UnsafeAXI4ToTL(numTlTxns: Int, wcorrupt: Boolean)(implicit p: Parameters) extends LazyModule {
require(numTlTxns >= 1)
require(isPow2(numTlTxns), s"Number of TileLink transactions ($numTlTxns) must be a power of 2")
val node = UnsafeAXI4ToTLNode(numTlTxns, wcorrupt)
lazy val module = new LazyModuleImp(this) {
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
edgeIn.master.masters.foreach { m =>
require(m.aligned, "AXI4ToTL requires aligned requests")
}
val numIds = edgeIn.master.endId
val beatBytes = edgeOut.slave.beatBytes
val maxTransfer = edgeOut.slave.maxTransfer
val maxBeats = maxTransfer / beatBytes
// Look for an Error device to redirect bad requests
val errorDevs = edgeOut.slave.managers.filter(_.nodePath.last.lazyModule.className == "TLError")
require(!errorDevs.isEmpty, "There is no TLError reachable from AXI4ToTL. One must be instantiated.")
val errorDev = errorDevs.maxBy(_.maxTransfer)
val errorDevAddr = errorDev.address.head.base
require(
errorDev.supportsPutPartial.contains(maxTransfer),
s"Error device supports ${errorDev.supportsPutPartial} PutPartial but must support $maxTransfer"
)
require(
errorDev.supportsGet.contains(maxTransfer),
s"Error device supports ${errorDev.supportsGet} Get but must support $maxTransfer"
)
// All of the read-response reordering logic.
val listBufData = new ReorderData(beatBytes * 8, edgeIn.bundle.respBits, out.d.bits.user.fields)
val listBufParams = ReservableListBufferParameters(numTlTxns, numIds, maxBeats)
val listBuffer = if (numTlTxns > 1) {
Module(new ReservableListBuffer(listBufData, listBufParams))
} else {
Module(new PassthroughListBuffer(listBufData, listBufParams))
}
// To differentiate between read and write transaction IDs, we will set the MSB of the TileLink 'source' field to
// 0 for read requests and 1 for write requests.
val isReadSourceBit = 0.U(1.W)
val isWriteSourceBit = 1.U(1.W)
/* Read request logic */
val rOut = Wire(Decoupled(new TLBundleA(edgeOut.bundle)))
val rBytes1 = in.ar.bits.bytes1()
val rSize = OH1ToUInt(rBytes1)
val rOk = edgeOut.slave.supportsGetSafe(in.ar.bits.addr, rSize)
val rId = if (numTlTxns > 1) {
Cat(isReadSourceBit, listBuffer.ioReservedIndex)
} else {
isReadSourceBit
}
val rAddr = Mux(rOk, in.ar.bits.addr, errorDevAddr.U | in.ar.bits.addr(log2Ceil(beatBytes) - 1, 0))
// Indicates if there are still valid TileLink source IDs left to use.
val canIssueR = listBuffer.ioReserve.ready
listBuffer.ioReserve.bits := in.ar.bits.id
listBuffer.ioReserve.valid := in.ar.valid && rOut.ready
in.ar.ready := rOut.ready && canIssueR
rOut.valid := in.ar.valid && canIssueR
rOut.bits :<= edgeOut.Get(rId, rAddr, rSize)._2
rOut.bits.user :<= in.ar.bits.user
rOut.bits.user.lift(AMBAProt).foreach { rProt =>
rProt.privileged := in.ar.bits.prot(0)
rProt.secure := !in.ar.bits.prot(1)
rProt.fetch := in.ar.bits.prot(2)
rProt.bufferable := in.ar.bits.cache(0)
rProt.modifiable := in.ar.bits.cache(1)
rProt.readalloc := in.ar.bits.cache(2)
rProt.writealloc := in.ar.bits.cache(3)
}
/* Write request logic */
// Strip off the MSB, which identifies the transaction as read vs write.
val strippedResponseSourceId = if (numTlTxns > 1) {
out.d.bits.source((out.d.bits.source).getWidth - 2, 0)
} else {
// When there's only 1 TileLink transaction allowed for read/write, then this field is always 0.
0.U(1.W)
}
// Track when a write request burst is in progress.
val writeBurstBusy = RegInit(false.B)
when(in.w.fire) {
writeBurstBusy := !in.w.bits.last
}
val usedWriteIds = RegInit(0.U(numTlTxns.W))
val canIssueW = !usedWriteIds.andR
val usedWriteIdsSet = WireDefault(0.U(numTlTxns.W))
val usedWriteIdsClr = WireDefault(0.U(numTlTxns.W))
usedWriteIds := (usedWriteIds & ~usedWriteIdsClr) | usedWriteIdsSet
// Since write responses can show up in the middle of a write burst, we need to ensure the write burst ID doesn't
// change mid-burst.
val freeWriteIdOHRaw = Wire(UInt(numTlTxns.W))
val freeWriteIdOH = freeWriteIdOHRaw holdUnless !writeBurstBusy
val freeWriteIdIndex = OHToUInt(freeWriteIdOH)
freeWriteIdOHRaw := ~(leftOR(~usedWriteIds) << 1) & ~usedWriteIds
val wOut = Wire(Decoupled(new TLBundleA(edgeOut.bundle)))
val wBytes1 = in.aw.bits.bytes1()
val wSize = OH1ToUInt(wBytes1)
val wOk = edgeOut.slave.supportsPutPartialSafe(in.aw.bits.addr, wSize)
val wId = if (numTlTxns > 1) {
Cat(isWriteSourceBit, freeWriteIdIndex)
} else {
isWriteSourceBit
}
val wAddr = Mux(wOk, in.aw.bits.addr, errorDevAddr.U | in.aw.bits.addr(log2Ceil(beatBytes) - 1, 0))
// Here, we're taking advantage of the Irrevocable behavior of AXI4 (once 'valid' is asserted it must remain
// asserted until the handshake occurs). We will only accept W-channel beats when we have a valid AW beat, but
// the AW-channel beat won't fire until the final W-channel beat fires. So, we have stable address/size/strb
// bits during a W-channel burst.
in.aw.ready := wOut.ready && in.w.valid && in.w.bits.last && canIssueW
in.w.ready := wOut.ready && in.aw.valid && canIssueW
wOut.valid := in.aw.valid && in.w.valid && canIssueW
wOut.bits :<= edgeOut.Put(wId, wAddr, wSize, in.w.bits.data, in.w.bits.strb)._2
in.w.bits.user.lift(AMBACorrupt).foreach { wOut.bits.corrupt := _ }
wOut.bits.user :<= in.aw.bits.user
wOut.bits.user.lift(AMBAProt).foreach { wProt =>
wProt.privileged := in.aw.bits.prot(0)
wProt.secure := !in.aw.bits.prot(1)
wProt.fetch := in.aw.bits.prot(2)
wProt.bufferable := in.aw.bits.cache(0)
wProt.modifiable := in.aw.bits.cache(1)
wProt.readalloc := in.aw.bits.cache(2)
wProt.writealloc := in.aw.bits.cache(3)
}
// Merge the AXI4 read/write requests into the TL-A channel.
TLArbiter(TLArbiter.roundRobin)(out.a, (0.U, rOut), (in.aw.bits.len, wOut))
/* Read/write response logic */
val okB = Wire(Irrevocable(new AXI4BundleB(edgeIn.bundle)))
val okR = Wire(Irrevocable(new AXI4BundleR(edgeIn.bundle)))
val dResp = Mux(out.d.bits.denied || out.d.bits.corrupt, AXI4Parameters.RESP_SLVERR, AXI4Parameters.RESP_OKAY)
val dHasData = edgeOut.hasData(out.d.bits)
val (_dFirst, dLast, _dDone, dCount) = edgeOut.count(out.d)
val dNumBeats1 = edgeOut.numBeats1(out.d.bits)
// Handle cases where writeack arrives before write is done
val writeEarlyAck = (UIntToOH(strippedResponseSourceId) & usedWriteIds) === 0.U
out.d.ready := Mux(dHasData, listBuffer.ioResponse.ready, okB.ready && !writeEarlyAck)
listBuffer.ioDataOut.ready := okR.ready
okR.valid := listBuffer.ioDataOut.valid
okB.valid := out.d.valid && !dHasData && !writeEarlyAck
listBuffer.ioResponse.valid := out.d.valid && dHasData
listBuffer.ioResponse.bits.index := strippedResponseSourceId
listBuffer.ioResponse.bits.data.data := out.d.bits.data
listBuffer.ioResponse.bits.data.resp := dResp
listBuffer.ioResponse.bits.data.last := dLast
listBuffer.ioResponse.bits.data.user :<= out.d.bits.user
listBuffer.ioResponse.bits.count := dCount
listBuffer.ioResponse.bits.numBeats1 := dNumBeats1
okR.bits.id := listBuffer.ioDataOut.bits.listIndex
okR.bits.data := listBuffer.ioDataOut.bits.payload.data
okR.bits.resp := listBuffer.ioDataOut.bits.payload.resp
okR.bits.last := listBuffer.ioDataOut.bits.payload.last
okR.bits.user :<= listBuffer.ioDataOut.bits.payload.user
// Upon the final beat in a write request, record a mapping from TileLink source ID to AXI write ID. Upon a write
// response, mark the write transaction as complete.
val writeIdMap = Mem(numTlTxns, UInt(log2Ceil(numIds).W))
val writeResponseId = writeIdMap.read(strippedResponseSourceId)
when(wOut.fire) {
writeIdMap.write(freeWriteIdIndex, in.aw.bits.id)
}
when(edgeOut.done(wOut)) {
usedWriteIdsSet := freeWriteIdOH
}
when(okB.fire) {
usedWriteIdsClr := UIntToOH(strippedResponseSourceId, numTlTxns)
}
okB.bits.id := writeResponseId
okB.bits.resp := dResp
okB.bits.user :<= out.d.bits.user
// AXI4 needs irrevocable behaviour
in.r <> Queue.irrevocable(okR, 1, flow = true)
in.b <> Queue.irrevocable(okB, 1, flow = true)
// Unused channels
out.b.ready := true.B
out.c.valid := false.B
out.e.valid := false.B
/* Alignment constraints. The AXI4Fragmenter should guarantee all of these constraints. */
def checkRequest[T <: AXI4BundleA](a: IrrevocableIO[T], reqType: String): Unit = {
val lReqType = reqType.toLowerCase
when(a.valid) {
assert(a.bits.len < maxBeats.U, s"$reqType burst length (%d) must be less than $maxBeats", a.bits.len + 1.U)
// Narrow transfers and FIXED bursts must be single-beat bursts.
when(a.bits.len =/= 0.U) {
assert(
a.bits.size === log2Ceil(beatBytes).U,
s"Narrow $lReqType transfers (%d < $beatBytes bytes) can't be multi-beat bursts (%d beats)",
1.U << a.bits.size,
a.bits.len + 1.U
)
assert(
a.bits.burst =/= AXI4Parameters.BURST_FIXED,
s"Fixed $lReqType bursts can't be multi-beat bursts (%d beats)",
a.bits.len + 1.U
)
}
// Furthermore, the transfer size (a.bits.bytes1() + 1.U) must be naturally-aligned to the address (in
// particular, during both WRAP and INCR bursts), but this constraint is already checked by TileLink
// Monitors. Note that this alignment requirement means that WRAP bursts are identical to INCR bursts.
}
}
checkRequest(in.ar, "Read")
checkRequest(in.aw, "Write")
}
}
}
object UnsafeAXI4ToTL {
def apply(numTlTxns: Int = 1, wcorrupt: Boolean = true)(implicit p: Parameters) = {
val axi42tl = LazyModule(new UnsafeAXI4ToTL(numTlTxns, wcorrupt))
axi42tl.node
}
}
/* ReservableListBuffer logic, and associated classes. */
class ResponsePayload[T <: Data](val data: T, val params: ReservableListBufferParameters) extends Bundle {
val index = UInt(params.entryBits.W)
val count = UInt(params.beatBits.W)
val numBeats1 = UInt(params.beatBits.W)
}
class DataOutPayload[T <: Data](val payload: T, val params: ReservableListBufferParameters) extends Bundle {
val listIndex = UInt(params.listBits.W)
}
/** Abstract base class to unify [[ReservableListBuffer]] and [[PassthroughListBuffer]]. */
abstract class BaseReservableListBuffer[T <: Data](gen: T, params: ReservableListBufferParameters)
extends Module {
require(params.numEntries > 0)
require(params.numLists > 0)
val ioReserve = IO(Flipped(Decoupled(UInt(params.listBits.W))))
val ioReservedIndex = IO(Output(UInt(params.entryBits.W)))
val ioResponse = IO(Flipped(Decoupled(new ResponsePayload(gen, params))))
val ioDataOut = IO(Decoupled(new DataOutPayload(gen, params)))
}
/** A modified version of 'ListBuffer' from 'sifive/block-inclusivecache-sifive'. This module forces users to reserve
* linked list entries (through the 'ioReserve' port) before writing data into those linked lists (through the
* 'ioResponse' port). Each response is tagged to indicate which linked list it is written into. The responses for a
* given linked list can come back out-of-order, but they will be read out through the 'ioDataOut' port in-order.
*
* ==Constructor==
* @param gen Chisel type of linked list data element
* @param params Other parameters
*
* ==Module IO==
* @param ioReserve Index of list to reserve a new element in
* @param ioReservedIndex Index of the entry that was reserved in the linked list, valid when 'ioReserve.fire'
* @param ioResponse Payload containing response data and linked-list-entry index
* @param ioDataOut Payload containing data read from response linked list and linked list index
*/
class ReservableListBuffer[T <: Data](gen: T, params: ReservableListBufferParameters)
extends BaseReservableListBuffer(gen, params) {
val valid = RegInit(0.U(params.numLists.W))
val head = Mem(params.numLists, UInt(params.entryBits.W))
val tail = Mem(params.numLists, UInt(params.entryBits.W))
val used = RegInit(0.U(params.numEntries.W))
val next = Mem(params.numEntries, UInt(params.entryBits.W))
val map = Mem(params.numEntries, UInt(params.listBits.W))
val dataMems = Seq.fill(params.numBeats) { SyncReadMem(params.numEntries, gen) }
val dataIsPresent = RegInit(0.U(params.numEntries.W))
val beats = Mem(params.numEntries, UInt(params.beatBits.W))
// The 'data' SRAM should be single-ported (read-or-write), since dual-ported SRAMs are significantly slower.
val dataMemReadEnable = WireDefault(false.B)
val dataMemWriteEnable = WireDefault(false.B)
assert(!(dataMemReadEnable && dataMemWriteEnable))
// 'freeOH' has a single bit set, which is the least-significant bit that is cleared in 'used'. So, it's the
// lowest-index entry in the 'data' RAM which is free.
val freeOH = Wire(UInt(params.numEntries.W))
val freeIndex = OHToUInt(freeOH)
freeOH := ~(leftOR(~used) << 1) & ~used
ioReservedIndex := freeIndex
val validSet = WireDefault(0.U(params.numLists.W))
val validClr = WireDefault(0.U(params.numLists.W))
val usedSet = WireDefault(0.U(params.numEntries.W))
val usedClr = WireDefault(0.U(params.numEntries.W))
val dataIsPresentSet = WireDefault(0.U(params.numEntries.W))
val dataIsPresentClr = WireDefault(0.U(params.numEntries.W))
valid := (valid & ~validClr) | validSet
used := (used & ~usedClr) | usedSet
dataIsPresent := (dataIsPresent & ~dataIsPresentClr) | dataIsPresentSet
/* Reservation logic signals */
val reserveTail = Wire(UInt(params.entryBits.W))
val reserveIsValid = Wire(Bool())
/* Response logic signals */
val responseIndex = Wire(UInt(params.entryBits.W))
val responseListIndex = Wire(UInt(params.listBits.W))
val responseHead = Wire(UInt(params.entryBits.W))
val responseTail = Wire(UInt(params.entryBits.W))
val nextResponseHead = Wire(UInt(params.entryBits.W))
val nextDataIsPresent = Wire(Bool())
val isResponseInOrder = Wire(Bool())
val isEndOfList = Wire(Bool())
val isLastBeat = Wire(Bool())
val isLastResponseBeat = Wire(Bool())
val isLastUnwindBeat = Wire(Bool())
/* Reservation logic */
reserveTail := tail.read(ioReserve.bits)
reserveIsValid := valid(ioReserve.bits)
ioReserve.ready := !used.andR
// When we want to append-to and destroy the same linked list on the same cycle, we need to take special care that we
// actually start a new list, rather than appending to a list that's about to disappear.
val reserveResponseSameList = ioReserve.bits === responseListIndex
val appendToAndDestroyList =
ioReserve.fire && ioDataOut.fire && reserveResponseSameList && isEndOfList && isLastBeat
when(ioReserve.fire) {
validSet := UIntToOH(ioReserve.bits, params.numLists)
usedSet := freeOH
when(reserveIsValid && !appendToAndDestroyList) {
next.write(reserveTail, freeIndex)
}.otherwise {
head.write(ioReserve.bits, freeIndex)
}
tail.write(ioReserve.bits, freeIndex)
map.write(freeIndex, ioReserve.bits)
}
/* Response logic */
// The majority of the response logic (reading from and writing to the various RAMs) is common between the
// response-from-IO case (ioResponse.fire) and the response-from-unwind case (unwindDataIsValid).
// The read from the 'next' RAM should be performed at the address given by 'responseHead'. However, we only use the
// 'nextResponseHead' signal when 'isResponseInOrder' is asserted (both in the response-from-IO and
// response-from-unwind cases), which implies that 'responseHead' equals 'responseIndex'. 'responseHead' comes after
// two back-to-back RAM reads, so indexing into the 'next' RAM with 'responseIndex' is much quicker.
responseHead := head.read(responseListIndex)
responseTail := tail.read(responseListIndex)
nextResponseHead := next.read(responseIndex)
nextDataIsPresent := dataIsPresent(nextResponseHead)
// Note that when 'isEndOfList' is asserted, 'nextResponseHead' (and therefore 'nextDataIsPresent') is invalid, since
// there isn't a next element in the linked list.
isResponseInOrder := responseHead === responseIndex
isEndOfList := responseHead === responseTail
isLastResponseBeat := ioResponse.bits.count === ioResponse.bits.numBeats1
// When a response's last beat is sent to the output channel, mark it as completed. This can happen in two
// situations:
// 1. We receive an in-order response, which travels straight from 'ioResponse' to 'ioDataOut'. The 'data' SRAM
// reservation was never needed.
// 2. An entry is read out of the 'data' SRAM (within the unwind FSM).
when(ioDataOut.fire && isLastBeat) {
// Mark the reservation as no-longer-used.
usedClr := UIntToOH(responseIndex, params.numEntries)
// If the response is in-order, then we're popping an element from this linked list.
when(isEndOfList) {
// Once we pop the last element from a linked list, mark it as no-longer-present.
validClr := UIntToOH(responseListIndex, params.numLists)
}.otherwise {
// Move the linked list's head pointer to the new head pointer.
head.write(responseListIndex, nextResponseHead)
}
}
// If we get an out-of-order response, then stash it in the 'data' SRAM for later unwinding.
when(ioResponse.fire && !isResponseInOrder) {
dataMemWriteEnable := true.B
when(isLastResponseBeat) {
dataIsPresentSet := UIntToOH(ioResponse.bits.index, params.numEntries)
beats.write(ioResponse.bits.index, ioResponse.bits.numBeats1)
}
}
// Use the 'ioResponse.bits.count' index (AKA the beat number) to select which 'data' SRAM to write to.
val responseCountOH = UIntToOH(ioResponse.bits.count, params.numBeats)
(responseCountOH.asBools zip dataMems) foreach { case (select, seqMem) =>
when(select && dataMemWriteEnable) {
seqMem.write(ioResponse.bits.index, ioResponse.bits.data)
}
}
/* Response unwind logic */
// Unwind FSM state definitions
val sIdle :: sUnwinding :: Nil = Enum(2)
val unwindState = RegInit(sIdle)
val busyUnwinding = unwindState === sUnwinding
val startUnwind = Wire(Bool())
val stopUnwind = Wire(Bool())
when(startUnwind) {
unwindState := sUnwinding
}.elsewhen(stopUnwind) {
unwindState := sIdle
}
assert(!(startUnwind && stopUnwind))
// Start the unwind FSM when there is an old out-of-order response stored in the 'data' SRAM that is now about to
// become the next in-order response. As noted previously, when 'isEndOfList' is asserted, 'nextDataIsPresent' is
// invalid.
//
// Note that since an in-order response from 'ioResponse' to 'ioDataOut' starts the unwind FSM, we don't have to
// worry about overwriting the 'data' SRAM's output when we start the unwind FSM.
startUnwind := ioResponse.fire && isResponseInOrder && isLastResponseBeat && !isEndOfList && nextDataIsPresent
// Stop the unwind FSM when the output channel consumes the final beat of an element from the unwind FSM, and one of
// two things happens:
// 1. We're still waiting for the next in-order response for this list (!nextDataIsPresent)
// 2. There are no more outstanding responses in this list (isEndOfList)
//
// Including 'busyUnwinding' ensures this is a single-cycle pulse, and it never fires while in-order transactions are
// passing from 'ioResponse' to 'ioDataOut'.
stopUnwind := busyUnwinding && ioDataOut.fire && isLastUnwindBeat && (!nextDataIsPresent || isEndOfList)
val isUnwindBurstOver = Wire(Bool())
val startNewBurst = startUnwind || (isUnwindBurstOver && dataMemReadEnable)
// Track the number of beats left to unwind for each list entry. At the start of a new burst, we flop the number of
// beats in this burst (minus 1) into 'unwindBeats1', and we reset the 'beatCounter' counter. With each beat, we
// increment 'beatCounter' until it reaches 'unwindBeats1'.
val unwindBeats1 = Reg(UInt(params.beatBits.W))
val nextBeatCounter = Wire(UInt(params.beatBits.W))
val beatCounter = RegNext(nextBeatCounter)
isUnwindBurstOver := beatCounter === unwindBeats1
when(startNewBurst) {
unwindBeats1 := beats.read(nextResponseHead)
nextBeatCounter := 0.U
}.elsewhen(dataMemReadEnable) {
nextBeatCounter := beatCounter + 1.U
}.otherwise {
nextBeatCounter := beatCounter
}
// When unwinding, feed the next linked-list head pointer (read out of the 'next' RAM) back so we can unwind the next
// entry in this linked list. Only update the pointer when we're actually moving to the next 'data' SRAM entry (which
// happens at the start of reading a new stored burst).
val unwindResponseIndex = RegEnable(nextResponseHead, startNewBurst)
responseIndex := Mux(busyUnwinding, unwindResponseIndex, ioResponse.bits.index)
// Hold 'nextResponseHead' static while we're in the middle of unwinding a multi-beat burst entry. We don't want the
// SRAM read address to shift while reading beats from a burst. Note that this is identical to 'nextResponseHead
// holdUnless startNewBurst', but 'unwindResponseIndex' already implements the 'RegEnable' signal in 'holdUnless'.
val unwindReadAddress = Mux(startNewBurst, nextResponseHead, unwindResponseIndex)
// The 'data' SRAM's output is valid if we read from the SRAM on the previous cycle. The SRAM's output stays valid
// until it is consumed by the output channel (and if we don't read from the SRAM again on that same cycle).
val unwindDataIsValid = RegInit(false.B)
when(dataMemReadEnable) {
unwindDataIsValid := true.B
}.elsewhen(ioDataOut.fire) {
unwindDataIsValid := false.B
}
isLastUnwindBeat := isUnwindBurstOver && unwindDataIsValid
// Indicates if this is the last beat for both 'ioResponse'-to-'ioDataOut' and unwind-to-'ioDataOut' beats.
isLastBeat := Mux(busyUnwinding, isLastUnwindBeat, isLastResponseBeat)
// Select which SRAM to read from based on the beat counter.
val dataOutputVec = Wire(Vec(params.numBeats, gen))
val nextBeatCounterOH = UIntToOH(nextBeatCounter, params.numBeats)
(nextBeatCounterOH.asBools zip dataMems).zipWithIndex foreach { case ((select, seqMem), i) =>
dataOutputVec(i) := seqMem.read(unwindReadAddress, select && dataMemReadEnable)
}
// Select the current 'data' SRAM output beat, and save the output in a register in case we're being back-pressured
// by 'ioDataOut'. This implements the functionality of 'readAndHold', but only on the single SRAM we're reading
// from.
val dataOutput = dataOutputVec(beatCounter) holdUnless RegNext(dataMemReadEnable)
// Mark 'data' burst entries as no-longer-present as they get read out of the SRAM.
when(dataMemReadEnable) {
dataIsPresentClr := UIntToOH(unwindReadAddress, params.numEntries)
}
// As noted above, when starting the unwind FSM, we know the 'data' SRAM's output isn't valid, so it's safe to issue
// a read command. Otherwise, only issue an SRAM read when the next 'unwindState' is 'sUnwinding', and if we know
// we're not going to overwrite the SRAM's current output (the SRAM output is already valid, and it's not going to be
// consumed by the output channel).
val dontReadFromDataMem = unwindDataIsValid && !ioDataOut.ready
dataMemReadEnable := startUnwind || (busyUnwinding && !stopUnwind && !dontReadFromDataMem)
// While unwinding, prevent new reservations from overwriting the current 'map' entry that we're using. We need
// 'responseListIndex' to be coherent for the entire unwind process.
val rawResponseListIndex = map.read(responseIndex)
val unwindResponseListIndex = RegEnable(rawResponseListIndex, startNewBurst)
responseListIndex := Mux(busyUnwinding, unwindResponseListIndex, rawResponseListIndex)
// Accept responses either when they can be passed through to the output channel, or if they're out-of-order and are
// just going to be stashed in the 'data' SRAM. Never accept a response payload when we're busy unwinding, since that
// could result in reading from and writing to the 'data' SRAM in the same cycle, and we want that SRAM to be
// single-ported.
ioResponse.ready := (ioDataOut.ready || !isResponseInOrder) && !busyUnwinding
// Either pass an in-order response to the output channel, or data read from the unwind FSM.
ioDataOut.valid := Mux(busyUnwinding, unwindDataIsValid, ioResponse.valid && isResponseInOrder)
ioDataOut.bits.listIndex := responseListIndex
ioDataOut.bits.payload := Mux(busyUnwinding, dataOutput, ioResponse.bits.data)
// It's an error to get a response that isn't associated with a valid linked list.
when(ioResponse.fire || unwindDataIsValid) {
assert(
valid(responseListIndex),
"No linked list exists at index %d, mapped from %d",
responseListIndex,
responseIndex
)
}
when(busyUnwinding && dataMemReadEnable) {
assert(isResponseInOrder, "Unwind FSM must read entries from SRAM in order")
}
}
/** Specialized version of [[ReservableListBuffer]] for the case of numEntries == 1.
*
* Much of the complex logic in [[ReservableListBuffer]] can disappear in this case. For instance, we don't have to
* reorder any responses, or store any linked lists.
*/
class PassthroughListBuffer[T <: Data](gen: T, params: ReservableListBufferParameters)
extends BaseReservableListBuffer(gen, params) {
require(params.numEntries == 1, s"PassthroughListBuffer is only valid when 'numEntries' (${params.numEntries}) is 1")
val used = RegInit(0.U(params.numEntries.W))
val map = Mem(params.numEntries, UInt(params.listBits.W))
val usedSet = WireDefault(0.U(params.numEntries.W))
val usedClr = WireDefault(0.U(params.numEntries.W))
used := (used & ~usedClr) | usedSet
ioReserve.ready := used === 0.U
// Store which list index was reserved, we need to return this value when we get a response.
when(ioReserve.fire) {
usedSet := 1.U
map.write(0.U, ioReserve.bits)
}
// There's only one valid linked list entry, which is at index 0.
ioReservedIndex := 0.U
val isLastResponseBeat = ioResponse.bits.count === ioResponse.bits.numBeats1
// Mark the linked list as empty when we get the last beat in a response.
// Note that 'ioResponse.fire === ioDataOut.fire'.
when(ioResponse.fire && isLastResponseBeat) {
usedClr := 1.U
}
// Always pass the response data straight through, since we never need to reorder the response data.
ioDataOut.bits.listIndex := map.read(0.U)
ioDataOut.bits.payload := ioResponse.bits.data
ioDataOut.valid := ioResponse.valid
ioResponse.ready := ioDataOut.ready
}
| module dataMems_126( // @[UnsafeAXI4ToTL.scala:365:62]
input [4:0] R0_addr,
input R0_en,
input R0_clk,
output [66:0] R0_data,
input [4:0] W0_addr,
input W0_en,
input W0_clk,
input [66:0] W0_data
);
dataMems_0_ext dataMems_0_ext ( // @[UnsafeAXI4ToTL.scala:365:62]
.R0_addr (R0_addr),
.R0_en (R0_en),
.R0_clk (R0_clk),
.R0_data (R0_data),
.W0_addr (W0_addr),
.W0_en (W0_en),
.W0_clk (W0_clk),
.W0_data (W0_data)
); // @[UnsafeAXI4ToTL.scala:365:62]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File PE.scala:
// See README.md for license details.
package gemmini
import chisel3._
import chisel3.util._
class PEControl[T <: Data : Arithmetic](accType: T) extends Bundle {
val dataflow = UInt(1.W) // TODO make this an Enum
val propagate = UInt(1.W) // Which register should be propagated (and which should be accumulated)?
val shift = UInt(log2Up(accType.getWidth).W) // TODO this isn't correct for Floats
}
class MacUnit[T <: Data](inputType: T, cType: T, dType: T) (implicit ev: Arithmetic[T]) extends Module {
import ev._
val io = IO(new Bundle {
val in_a = Input(inputType)
val in_b = Input(inputType)
val in_c = Input(cType)
val out_d = Output(dType)
})
io.out_d := io.in_c.mac(io.in_a, io.in_b)
}
// TODO update documentation
/**
* A PE implementing a MAC operation. Configured as fully combinational when integrated into a Mesh.
* @param width Data width of operands
*/
class PE[T <: Data](inputType: T, outputType: T, accType: T, df: Dataflow.Value, max_simultaneous_matmuls: Int)
(implicit ev: Arithmetic[T]) extends Module { // Debugging variables
import ev._
val io = IO(new Bundle {
val in_a = Input(inputType)
val in_b = Input(outputType)
val in_d = Input(outputType)
val out_a = Output(inputType)
val out_b = Output(outputType)
val out_c = Output(outputType)
val in_control = Input(new PEControl(accType))
val out_control = Output(new PEControl(accType))
val in_id = Input(UInt(log2Up(max_simultaneous_matmuls).W))
val out_id = Output(UInt(log2Up(max_simultaneous_matmuls).W))
val in_last = Input(Bool())
val out_last = Output(Bool())
val in_valid = Input(Bool())
val out_valid = Output(Bool())
val bad_dataflow = Output(Bool())
})
val cType = if (df == Dataflow.WS) inputType else accType
// When creating PEs that support multiple dataflows, the
// elaboration/synthesis tools often fail to consolidate and de-duplicate
// MAC units. To force mac circuitry to be re-used, we create a "mac_unit"
// module here which just performs a single MAC operation
val mac_unit = Module(new MacUnit(inputType,
if (df == Dataflow.WS) outputType else accType, outputType))
val a = io.in_a
val b = io.in_b
val d = io.in_d
val c1 = Reg(cType)
val c2 = Reg(cType)
val dataflow = io.in_control.dataflow
val prop = io.in_control.propagate
val shift = io.in_control.shift
val id = io.in_id
val last = io.in_last
val valid = io.in_valid
io.out_a := a
io.out_control.dataflow := dataflow
io.out_control.propagate := prop
io.out_control.shift := shift
io.out_id := id
io.out_last := last
io.out_valid := valid
mac_unit.io.in_a := a
val last_s = RegEnable(prop, valid)
val flip = last_s =/= prop
val shift_offset = Mux(flip, shift, 0.U)
// Which dataflow are we using?
val OUTPUT_STATIONARY = Dataflow.OS.id.U(1.W)
val WEIGHT_STATIONARY = Dataflow.WS.id.U(1.W)
// Is c1 being computed on, or propagated forward (in the output-stationary dataflow)?
val COMPUTE = 0.U(1.W)
val PROPAGATE = 1.U(1.W)
io.bad_dataflow := false.B
when ((df == Dataflow.OS).B || ((df == Dataflow.BOTH).B && dataflow === OUTPUT_STATIONARY)) {
when(prop === PROPAGATE) {
io.out_c := (c1 >> shift_offset).clippedToWidthOf(outputType)
io.out_b := b
mac_unit.io.in_b := b.asTypeOf(inputType)
mac_unit.io.in_c := c2
c2 := mac_unit.io.out_d
c1 := d.withWidthOf(cType)
}.otherwise {
io.out_c := (c2 >> shift_offset).clippedToWidthOf(outputType)
io.out_b := b
mac_unit.io.in_b := b.asTypeOf(inputType)
mac_unit.io.in_c := c1
c1 := mac_unit.io.out_d
c2 := d.withWidthOf(cType)
}
}.elsewhen ((df == Dataflow.WS).B || ((df == Dataflow.BOTH).B && dataflow === WEIGHT_STATIONARY)) {
when(prop === PROPAGATE) {
io.out_c := c1
mac_unit.io.in_b := c2.asTypeOf(inputType)
mac_unit.io.in_c := b
io.out_b := mac_unit.io.out_d
c1 := d
}.otherwise {
io.out_c := c2
mac_unit.io.in_b := c1.asTypeOf(inputType)
mac_unit.io.in_c := b
io.out_b := mac_unit.io.out_d
c2 := d
}
}.otherwise {
io.bad_dataflow := true.B
//assert(false.B, "unknown dataflow")
io.out_c := DontCare
io.out_b := DontCare
mac_unit.io.in_b := b.asTypeOf(inputType)
mac_unit.io.in_c := c2
}
when (!valid) {
c1 := c1
c2 := c2
mac_unit.io.in_b := DontCare
mac_unit.io.in_c := DontCare
}
}
File Arithmetic.scala:
// A simple type class for Chisel datatypes that can add and multiply. To add your own type, simply create your own:
// implicit MyTypeArithmetic extends Arithmetic[MyType] { ... }
package gemmini
import chisel3._
import chisel3.util._
import hardfloat._
// Bundles that represent the raw bits of custom datatypes
case class Float(expWidth: Int, sigWidth: Int) extends Bundle {
val bits = UInt((expWidth + sigWidth).W)
val bias: Int = (1 << (expWidth-1)) - 1
}
case class DummySInt(w: Int) extends Bundle {
val bits = UInt(w.W)
def dontCare: DummySInt = {
val o = Wire(new DummySInt(w))
o.bits := 0.U
o
}
}
// The Arithmetic typeclass which implements various arithmetic operations on custom datatypes
abstract class Arithmetic[T <: Data] {
implicit def cast(t: T): ArithmeticOps[T]
}
abstract class ArithmeticOps[T <: Data](self: T) {
def *(t: T): T
def mac(m1: T, m2: T): T // Returns (m1 * m2 + self)
def +(t: T): T
def -(t: T): T
def >>(u: UInt): T // This is a rounding shift! Rounds away from 0
def >(t: T): Bool
def identity: T
def withWidthOf(t: T): T
def clippedToWidthOf(t: T): T // Like "withWidthOf", except that it saturates
def relu: T
def zero: T
def minimum: T
// Optional parameters, which only need to be defined if you want to enable various optimizations for transformers
def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[T])] = None
def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[T])] = None
def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = None
def mult_with_reciprocal[U <: Data](reciprocal: U) = self
}
object Arithmetic {
implicit object UIntArithmetic extends Arithmetic[UInt] {
override implicit def cast(self: UInt) = new ArithmeticOps(self) {
override def *(t: UInt) = self * t
override def mac(m1: UInt, m2: UInt) = m1 * m2 + self
override def +(t: UInt) = self + t
override def -(t: UInt) = self - t
override def >>(u: UInt) = {
// The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm
// TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here?
val point_five = Mux(u === 0.U, 0.U, self(u - 1.U))
val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U
val ones_digit = self(u)
val r = point_five & (zeros | ones_digit)
(self >> u).asUInt + r
}
override def >(t: UInt): Bool = self > t
override def withWidthOf(t: UInt) = self.asTypeOf(t)
override def clippedToWidthOf(t: UInt) = {
val sat = ((1 << (t.getWidth-1))-1).U
Mux(self > sat, sat, self)(t.getWidth-1, 0)
}
override def relu: UInt = self
override def zero: UInt = 0.U
override def identity: UInt = 1.U
override def minimum: UInt = 0.U
}
}
implicit object SIntArithmetic extends Arithmetic[SInt] {
override implicit def cast(self: SInt) = new ArithmeticOps(self) {
override def *(t: SInt) = self * t
override def mac(m1: SInt, m2: SInt) = m1 * m2 + self
override def +(t: SInt) = self + t
override def -(t: SInt) = self - t
override def >>(u: UInt) = {
// The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm
// TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here?
val point_five = Mux(u === 0.U, 0.U, self(u - 1.U))
val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U
val ones_digit = self(u)
val r = (point_five & (zeros | ones_digit)).asBool
(self >> u).asSInt + Mux(r, 1.S, 0.S)
}
override def >(t: SInt): Bool = self > t
override def withWidthOf(t: SInt) = {
if (self.getWidth >= t.getWidth)
self(t.getWidth-1, 0).asSInt
else {
val sign_bits = t.getWidth - self.getWidth
val sign = self(self.getWidth-1)
Cat(Cat(Seq.fill(sign_bits)(sign)), self).asTypeOf(t)
}
}
override def clippedToWidthOf(t: SInt): SInt = {
val maxsat = ((1 << (t.getWidth-1))-1).S
val minsat = (-(1 << (t.getWidth-1))).S
MuxCase(self, Seq((self > maxsat) -> maxsat, (self < minsat) -> minsat))(t.getWidth-1, 0).asSInt
}
override def relu: SInt = Mux(self >= 0.S, self, 0.S)
override def zero: SInt = 0.S
override def identity: SInt = 1.S
override def minimum: SInt = (-(1 << (self.getWidth-1))).S
override def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = {
// TODO this uses a floating point divider, but we should use an integer divider instead
val input = Wire(Decoupled(denom_t.cloneType))
val output = Wire(Decoupled(self.cloneType))
// We translate our integer to floating-point form so that we can use the hardfloat divider
val expWidth = log2Up(self.getWidth) + 1
val sigWidth = self.getWidth
def sin_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def uin_to_float(x: UInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := false.B
in_to_rec_fn.io.in := x
in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def float_to_in(x: UInt) = {
val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth))
rec_fn_to_in.io.signedOut := true.B
rec_fn_to_in.io.in := x
rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
rec_fn_to_in.io.out.asSInt
}
val self_rec = sin_to_float(self)
val denom_rec = uin_to_float(input.bits)
// Instantiate the hardloat divider
val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options))
input.ready := divider.io.inReady
divider.io.inValid := input.valid
divider.io.sqrtOp := false.B
divider.io.a := self_rec
divider.io.b := denom_rec
divider.io.roundingMode := consts.round_minMag
divider.io.detectTininess := consts.tininess_afterRounding
output.valid := divider.io.outValid_div
output.bits := float_to_in(divider.io.out)
assert(!output.valid || output.ready)
Some((input, output))
}
override def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = {
// TODO this uses a floating point divider, but we should use an integer divider instead
val input = Wire(Decoupled(UInt(0.W)))
val output = Wire(Decoupled(self.cloneType))
input.bits := DontCare
// We translate our integer to floating-point form so that we can use the hardfloat divider
val expWidth = log2Up(self.getWidth) + 1
val sigWidth = self.getWidth
def in_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def float_to_in(x: UInt) = {
val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth))
rec_fn_to_in.io.signedOut := true.B
rec_fn_to_in.io.in := x
rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
rec_fn_to_in.io.out.asSInt
}
val self_rec = in_to_float(self)
// Instantiate the hardloat sqrt
val sqrter = Module(new DivSqrtRecFN_small(expWidth, sigWidth, 0))
input.ready := sqrter.io.inReady
sqrter.io.inValid := input.valid
sqrter.io.sqrtOp := true.B
sqrter.io.a := self_rec
sqrter.io.b := DontCare
sqrter.io.roundingMode := consts.round_minMag
sqrter.io.detectTininess := consts.tininess_afterRounding
output.valid := sqrter.io.outValid_sqrt
output.bits := float_to_in(sqrter.io.out)
assert(!output.valid || output.ready)
Some((input, output))
}
override def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = u match {
case Float(expWidth, sigWidth) =>
val input = Wire(Decoupled(UInt(0.W)))
val output = Wire(Decoupled(u.cloneType))
input.bits := DontCare
// We translate our integer to floating-point form so that we can use the hardfloat divider
def in_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
val self_rec = in_to_float(self)
val one_rec = in_to_float(1.S)
// Instantiate the hardloat divider
val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options))
input.ready := divider.io.inReady
divider.io.inValid := input.valid
divider.io.sqrtOp := false.B
divider.io.a := one_rec
divider.io.b := self_rec
divider.io.roundingMode := consts.round_near_even
divider.io.detectTininess := consts.tininess_afterRounding
output.valid := divider.io.outValid_div
output.bits := fNFromRecFN(expWidth, sigWidth, divider.io.out).asTypeOf(u)
assert(!output.valid || output.ready)
Some((input, output))
case _ => None
}
override def mult_with_reciprocal[U <: Data](reciprocal: U): SInt = reciprocal match {
case recip @ Float(expWidth, sigWidth) =>
def in_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def float_to_in(x: UInt) = {
val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth))
rec_fn_to_in.io.signedOut := true.B
rec_fn_to_in.io.in := x
rec_fn_to_in.io.roundingMode := consts.round_minMag
rec_fn_to_in.io.out.asSInt
}
val self_rec = in_to_float(self)
val reciprocal_rec = recFNFromFN(expWidth, sigWidth, recip.bits)
// Instantiate the hardloat divider
val muladder = Module(new MulRecFN(expWidth, sigWidth))
muladder.io.roundingMode := consts.round_near_even
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := self_rec
muladder.io.b := reciprocal_rec
float_to_in(muladder.io.out)
case _ => self
}
}
}
implicit object FloatArithmetic extends Arithmetic[Float] {
// TODO Floating point arithmetic currently switches between recoded and standard formats for every operation. However, it should stay in the recoded format as it travels through the systolic array
override implicit def cast(self: Float): ArithmeticOps[Float] = new ArithmeticOps(self) {
override def *(t: Float): Float = {
val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth))
t_resizer.io.in := t_rec
t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
t_resizer.io.detectTininess := consts.tininess_afterRounding
val t_rec_resized = t_resizer.io.out
val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth))
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := self_rec
muladder.io.b := t_rec_resized
val out = Wire(Float(self.expWidth, self.sigWidth))
out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
out
}
override def mac(m1: Float, m2: Float): Float = {
// Recode all operands
val m1_rec = recFNFromFN(m1.expWidth, m1.sigWidth, m1.bits)
val m2_rec = recFNFromFN(m2.expWidth, m2.sigWidth, m2.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Resize m1 to self's width
val m1_resizer = Module(new RecFNToRecFN(m1.expWidth, m1.sigWidth, self.expWidth, self.sigWidth))
m1_resizer.io.in := m1_rec
m1_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
m1_resizer.io.detectTininess := consts.tininess_afterRounding
val m1_rec_resized = m1_resizer.io.out
// Resize m2 to self's width
val m2_resizer = Module(new RecFNToRecFN(m2.expWidth, m2.sigWidth, self.expWidth, self.sigWidth))
m2_resizer.io.in := m2_rec
m2_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
m2_resizer.io.detectTininess := consts.tininess_afterRounding
val m2_rec_resized = m2_resizer.io.out
// Perform multiply-add
val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth))
muladder.io.op := 0.U
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := m1_rec_resized
muladder.io.b := m2_rec_resized
muladder.io.c := self_rec
// Convert result to standard format // TODO remove these intermediate recodings
val out = Wire(Float(self.expWidth, self.sigWidth))
out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
out
}
override def +(t: Float): Float = {
require(self.getWidth >= t.getWidth) // This just makes it easier to write the resizing code
// Recode all operands
val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Generate 1 as a float
val in_to_rec_fn = Module(new INToRecFN(1, self.expWidth, self.sigWidth))
in_to_rec_fn.io.signedIn := false.B
in_to_rec_fn.io.in := 1.U
in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
val one_rec = in_to_rec_fn.io.out
// Resize t
val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth))
t_resizer.io.in := t_rec
t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
t_resizer.io.detectTininess := consts.tininess_afterRounding
val t_rec_resized = t_resizer.io.out
// Perform addition
val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth))
muladder.io.op := 0.U
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := t_rec_resized
muladder.io.b := one_rec
muladder.io.c := self_rec
val result = Wire(Float(self.expWidth, self.sigWidth))
result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
result
}
override def -(t: Float): Float = {
val t_sgn = t.bits(t.getWidth-1)
val neg_t = Cat(~t_sgn, t.bits(t.getWidth-2,0)).asTypeOf(t)
self + neg_t
}
override def >>(u: UInt): Float = {
// Recode self
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Get 2^(-u) as a recoded float
val shift_exp = Wire(UInt(self.expWidth.W))
shift_exp := self.bias.U - u
val shift_fn = Cat(0.U(1.W), shift_exp, 0.U((self.sigWidth-1).W))
val shift_rec = recFNFromFN(self.expWidth, self.sigWidth, shift_fn)
assert(shift_exp =/= 0.U, "scaling by denormalized numbers is not currently supported")
// Multiply self and 2^(-u)
val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth))
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := self_rec
muladder.io.b := shift_rec
val result = Wire(Float(self.expWidth, self.sigWidth))
result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
result
}
override def >(t: Float): Bool = {
// Recode all operands
val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Resize t to self's width
val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth))
t_resizer.io.in := t_rec
t_resizer.io.roundingMode := consts.round_near_even
t_resizer.io.detectTininess := consts.tininess_afterRounding
val t_rec_resized = t_resizer.io.out
val comparator = Module(new CompareRecFN(self.expWidth, self.sigWidth))
comparator.io.a := self_rec
comparator.io.b := t_rec_resized
comparator.io.signaling := false.B
comparator.io.gt
}
override def withWidthOf(t: Float): Float = {
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth))
resizer.io.in := self_rec
resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
resizer.io.detectTininess := consts.tininess_afterRounding
val result = Wire(Float(t.expWidth, t.sigWidth))
result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out)
result
}
override def clippedToWidthOf(t: Float): Float = {
// TODO check for overflow. Right now, we just assume that overflow doesn't happen
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth))
resizer.io.in := self_rec
resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
resizer.io.detectTininess := consts.tininess_afterRounding
val result = Wire(Float(t.expWidth, t.sigWidth))
result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out)
result
}
override def relu: Float = {
val raw = rawFloatFromFN(self.expWidth, self.sigWidth, self.bits)
val result = Wire(Float(self.expWidth, self.sigWidth))
result.bits := Mux(!raw.isZero && raw.sign, 0.U, self.bits)
result
}
override def zero: Float = 0.U.asTypeOf(self)
override def identity: Float = Cat(0.U(2.W), ~(0.U((self.expWidth-1).W)), 0.U((self.sigWidth-1).W)).asTypeOf(self)
override def minimum: Float = Cat(1.U, ~(0.U(self.expWidth.W)), 0.U((self.sigWidth-1).W)).asTypeOf(self)
}
}
implicit object DummySIntArithmetic extends Arithmetic[DummySInt] {
override implicit def cast(self: DummySInt) = new ArithmeticOps(self) {
override def *(t: DummySInt) = self.dontCare
override def mac(m1: DummySInt, m2: DummySInt) = self.dontCare
override def +(t: DummySInt) = self.dontCare
override def -(t: DummySInt) = self.dontCare
override def >>(t: UInt) = self.dontCare
override def >(t: DummySInt): Bool = false.B
override def identity = self.dontCare
override def withWidthOf(t: DummySInt) = self.dontCare
override def clippedToWidthOf(t: DummySInt) = self.dontCare
override def relu = self.dontCare
override def zero = self.dontCare
override def minimum: DummySInt = self.dontCare
}
}
}
| module MacUnit_221( // @[PE.scala:14:7]
input clock, // @[PE.scala:14:7]
input reset, // @[PE.scala:14:7]
input [7:0] io_in_a, // @[PE.scala:16:14]
input [7:0] io_in_b, // @[PE.scala:16:14]
input [31:0] io_in_c, // @[PE.scala:16:14]
output [19:0] io_out_d // @[PE.scala:16:14]
);
wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:14:7]
wire [7:0] io_in_b_0 = io_in_b; // @[PE.scala:14:7]
wire [31:0] io_in_c_0 = io_in_c; // @[PE.scala:14:7]
wire [19:0] io_out_d_0; // @[PE.scala:14:7]
wire [15:0] _io_out_d_T = {{8{io_in_a_0[7]}}, io_in_a_0} * {{8{io_in_b_0[7]}}, io_in_b_0}; // @[PE.scala:14:7]
wire [32:0] _io_out_d_T_1 = {{17{_io_out_d_T[15]}}, _io_out_d_T} + {io_in_c_0[31], io_in_c_0}; // @[PE.scala:14:7]
wire [31:0] _io_out_d_T_2 = _io_out_d_T_1[31:0]; // @[Arithmetic.scala:93:54]
wire [31:0] _io_out_d_T_3 = _io_out_d_T_2; // @[Arithmetic.scala:93:54]
assign io_out_d_0 = _io_out_d_T_3[19:0]; // @[PE.scala:14:7, :23:12]
assign io_out_d = io_out_d_0; // @[PE.scala:14:7]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File util.scala:
//******************************************************************************
// Copyright (c) 2015 - 2019, The Regents of the University of California (Regents).
// All Rights Reserved. See LICENSE and LICENSE.SiFive for license details.
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
// Utility Functions
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
package boom.v3.util
import chisel3._
import chisel3.util._
import freechips.rocketchip.rocket.Instructions._
import freechips.rocketchip.rocket._
import freechips.rocketchip.util.{Str}
import org.chipsalliance.cde.config.{Parameters}
import freechips.rocketchip.tile.{TileKey}
import boom.v3.common.{MicroOp}
import boom.v3.exu.{BrUpdateInfo}
/**
* Object to XOR fold a input register of fullLength into a compressedLength.
*/
object Fold
{
def apply(input: UInt, compressedLength: Int, fullLength: Int): UInt = {
val clen = compressedLength
val hlen = fullLength
if (hlen <= clen) {
input
} else {
var res = 0.U(clen.W)
var remaining = input.asUInt
for (i <- 0 to hlen-1 by clen) {
val len = if (i + clen > hlen ) (hlen - i) else clen
require(len > 0)
res = res(clen-1,0) ^ remaining(len-1,0)
remaining = remaining >> len.U
}
res
}
}
}
/**
* Object to check if MicroOp was killed due to a branch mispredict.
* Uses "Fast" branch masks
*/
object IsKilledByBranch
{
def apply(brupdate: BrUpdateInfo, uop: MicroOp): Bool = {
return maskMatch(brupdate.b1.mispredict_mask, uop.br_mask)
}
def apply(brupdate: BrUpdateInfo, uop_mask: UInt): Bool = {
return maskMatch(brupdate.b1.mispredict_mask, uop_mask)
}
}
/**
* Object to return new MicroOp with a new BR mask given a MicroOp mask
* and old BR mask.
*/
object GetNewUopAndBrMask
{
def apply(uop: MicroOp, brupdate: BrUpdateInfo)
(implicit p: Parameters): MicroOp = {
val newuop = WireInit(uop)
newuop.br_mask := uop.br_mask & ~brupdate.b1.resolve_mask
newuop
}
}
/**
* Object to return a BR mask given a MicroOp mask and old BR mask.
*/
object GetNewBrMask
{
def apply(brupdate: BrUpdateInfo, uop: MicroOp): UInt = {
return uop.br_mask & ~brupdate.b1.resolve_mask
}
def apply(brupdate: BrUpdateInfo, br_mask: UInt): UInt = {
return br_mask & ~brupdate.b1.resolve_mask
}
}
object UpdateBrMask
{
def apply(brupdate: BrUpdateInfo, uop: MicroOp): MicroOp = {
val out = WireInit(uop)
out.br_mask := GetNewBrMask(brupdate, uop)
out
}
def apply[T <: boom.v3.common.HasBoomUOP](brupdate: BrUpdateInfo, bundle: T): T = {
val out = WireInit(bundle)
out.uop.br_mask := GetNewBrMask(brupdate, bundle.uop.br_mask)
out
}
def apply[T <: boom.v3.common.HasBoomUOP](brupdate: BrUpdateInfo, bundle: Valid[T]): Valid[T] = {
val out = WireInit(bundle)
out.bits.uop.br_mask := GetNewBrMask(brupdate, bundle.bits.uop.br_mask)
out.valid := bundle.valid && !IsKilledByBranch(brupdate, bundle.bits.uop.br_mask)
out
}
}
/**
* Object to check if at least 1 bit matches in two masks
*/
object maskMatch
{
def apply(msk1: UInt, msk2: UInt): Bool = (msk1 & msk2) =/= 0.U
}
/**
* Object to clear one bit in a mask given an index
*/
object clearMaskBit
{
def apply(msk: UInt, idx: UInt): UInt = (msk & ~(1.U << idx))(msk.getWidth-1, 0)
}
/**
* Object to shift a register over by one bit and concat a new one
*/
object PerformShiftRegister
{
def apply(reg_val: UInt, new_bit: Bool): UInt = {
reg_val := Cat(reg_val(reg_val.getWidth-1, 0).asUInt, new_bit.asUInt).asUInt
reg_val
}
}
/**
* Object to shift a register over by one bit, wrapping the top bit around to the bottom
* (XOR'ed with a new-bit), and evicting a bit at index HLEN.
* This is used to simulate a longer HLEN-width shift register that is folded
* down to a compressed CLEN.
*/
object PerformCircularShiftRegister
{
def apply(csr: UInt, new_bit: Bool, evict_bit: Bool, hlen: Int, clen: Int): UInt = {
val carry = csr(clen-1)
val newval = Cat(csr, new_bit ^ carry) ^ (evict_bit << (hlen % clen).U)
newval
}
}
/**
* Object to increment an input value, wrapping it if
* necessary.
*/
object WrapAdd
{
// "n" is the number of increments, so we wrap at n-1.
def apply(value: UInt, amt: UInt, n: Int): UInt = {
if (isPow2(n)) {
(value + amt)(log2Ceil(n)-1,0)
} else {
val sum = Cat(0.U(1.W), value) + Cat(0.U(1.W), amt)
Mux(sum >= n.U,
sum - n.U,
sum)
}
}
}
/**
* Object to decrement an input value, wrapping it if
* necessary.
*/
object WrapSub
{
// "n" is the number of increments, so we wrap to n-1.
def apply(value: UInt, amt: Int, n: Int): UInt = {
if (isPow2(n)) {
(value - amt.U)(log2Ceil(n)-1,0)
} else {
val v = Cat(0.U(1.W), value)
val b = Cat(0.U(1.W), amt.U)
Mux(value >= amt.U,
value - amt.U,
n.U - amt.U + value)
}
}
}
/**
* Object to increment an input value, wrapping it if
* necessary.
*/
object WrapInc
{
// "n" is the number of increments, so we wrap at n-1.
def apply(value: UInt, n: Int): UInt = {
if (isPow2(n)) {
(value + 1.U)(log2Ceil(n)-1,0)
} else {
val wrap = (value === (n-1).U)
Mux(wrap, 0.U, value + 1.U)
}
}
}
/**
* Object to decrement an input value, wrapping it if
* necessary.
*/
object WrapDec
{
// "n" is the number of increments, so we wrap at n-1.
def apply(value: UInt, n: Int): UInt = {
if (isPow2(n)) {
(value - 1.U)(log2Ceil(n)-1,0)
} else {
val wrap = (value === 0.U)
Mux(wrap, (n-1).U, value - 1.U)
}
}
}
/**
* Object to mask off lower bits of a PC to align to a "b"
* Byte boundary.
*/
object AlignPCToBoundary
{
def apply(pc: UInt, b: Int): UInt = {
// Invert for scenario where pc longer than b
// (which would clear all bits above size(b)).
~(~pc | (b-1).U)
}
}
/**
* Object to rotate a signal left by one
*/
object RotateL1
{
def apply(signal: UInt): UInt = {
val w = signal.getWidth
val out = Cat(signal(w-2,0), signal(w-1))
return out
}
}
/**
* Object to sext a value to a particular length.
*/
object Sext
{
def apply(x: UInt, length: Int): UInt = {
if (x.getWidth == length) return x
else return Cat(Fill(length-x.getWidth, x(x.getWidth-1)), x)
}
}
/**
* Object to translate from BOOM's special "packed immediate" to a 32b signed immediate
* Asking for U-type gives it shifted up 12 bits.
*/
object ImmGen
{
import boom.v3.common.{LONGEST_IMM_SZ, IS_B, IS_I, IS_J, IS_S, IS_U}
def apply(ip: UInt, isel: UInt): SInt = {
val sign = ip(LONGEST_IMM_SZ-1).asSInt
val i30_20 = Mux(isel === IS_U, ip(18,8).asSInt, sign)
val i19_12 = Mux(isel === IS_U || isel === IS_J, ip(7,0).asSInt, sign)
val i11 = Mux(isel === IS_U, 0.S,
Mux(isel === IS_J || isel === IS_B, ip(8).asSInt, sign))
val i10_5 = Mux(isel === IS_U, 0.S, ip(18,14).asSInt)
val i4_1 = Mux(isel === IS_U, 0.S, ip(13,9).asSInt)
val i0 = Mux(isel === IS_S || isel === IS_I, ip(8).asSInt, 0.S)
return Cat(sign, i30_20, i19_12, i11, i10_5, i4_1, i0).asSInt
}
}
/**
* Object to get the FP rounding mode out of a packed immediate.
*/
object ImmGenRm { def apply(ip: UInt): UInt = { return ip(2,0) } }
/**
* Object to get the FP function fype from a packed immediate.
* Note: only works if !(IS_B or IS_S)
*/
object ImmGenTyp { def apply(ip: UInt): UInt = { return ip(9,8) } }
/**
* Object to see if an instruction is a JALR.
*/
object DebugIsJALR
{
def apply(inst: UInt): Bool = {
// TODO Chisel not sure why this won't compile
// val is_jalr = rocket.DecodeLogic(inst, List(Bool(false)),
// Array(
// JALR -> Bool(true)))
inst(6,0) === "b1100111".U
}
}
/**
* Object to take an instruction and output its branch or jal target. Only used
* for a debug assert (no where else would we jump straight from instruction
* bits to a target).
*/
object DebugGetBJImm
{
def apply(inst: UInt): UInt = {
// TODO Chisel not sure why this won't compile
//val csignals =
//rocket.DecodeLogic(inst,
// List(Bool(false), Bool(false)),
// Array(
// BEQ -> List(Bool(true ), Bool(false)),
// BNE -> List(Bool(true ), Bool(false)),
// BGE -> List(Bool(true ), Bool(false)),
// BGEU -> List(Bool(true ), Bool(false)),
// BLT -> List(Bool(true ), Bool(false)),
// BLTU -> List(Bool(true ), Bool(false))
// ))
//val is_br :: nothing :: Nil = csignals
val is_br = (inst(6,0) === "b1100011".U)
val br_targ = Cat(Fill(12, inst(31)), Fill(8,inst(31)), inst(7), inst(30,25), inst(11,8), 0.U(1.W))
val jal_targ= Cat(Fill(12, inst(31)), inst(19,12), inst(20), inst(30,25), inst(24,21), 0.U(1.W))
Mux(is_br, br_targ, jal_targ)
}
}
/**
* Object to return the lowest bit position after the head.
*/
object AgePriorityEncoder
{
def apply(in: Seq[Bool], head: UInt): UInt = {
val n = in.size
val width = log2Ceil(in.size)
val n_padded = 1 << width
val temp_vec = (0 until n_padded).map(i => if (i < n) in(i) && i.U >= head else false.B) ++ in
val idx = PriorityEncoder(temp_vec)
idx(width-1, 0) //discard msb
}
}
/**
* Object to determine whether queue
* index i0 is older than index i1.
*/
object IsOlder
{
def apply(i0: UInt, i1: UInt, head: UInt) = ((i0 < i1) ^ (i0 < head) ^ (i1 < head))
}
/**
* Set all bits at or below the highest order '1'.
*/
object MaskLower
{
def apply(in: UInt) = {
val n = in.getWidth
(0 until n).map(i => in >> i.U).reduce(_|_)
}
}
/**
* Set all bits at or above the lowest order '1'.
*/
object MaskUpper
{
def apply(in: UInt) = {
val n = in.getWidth
(0 until n).map(i => (in << i.U)(n-1,0)).reduce(_|_)
}
}
/**
* Transpose a matrix of Chisel Vecs.
*/
object Transpose
{
def apply[T <: chisel3.Data](in: Vec[Vec[T]]) = {
val n = in(0).size
VecInit((0 until n).map(i => VecInit(in.map(row => row(i)))))
}
}
/**
* N-wide one-hot priority encoder.
*/
object SelectFirstN
{
def apply(in: UInt, n: Int) = {
val sels = Wire(Vec(n, UInt(in.getWidth.W)))
var mask = in
for (i <- 0 until n) {
sels(i) := PriorityEncoderOH(mask)
mask = mask & ~sels(i)
}
sels
}
}
/**
* Connect the first k of n valid input interfaces to k output interfaces.
*/
class Compactor[T <: chisel3.Data](n: Int, k: Int, gen: T) extends Module
{
require(n >= k)
val io = IO(new Bundle {
val in = Vec(n, Flipped(DecoupledIO(gen)))
val out = Vec(k, DecoupledIO(gen))
})
if (n == k) {
io.out <> io.in
} else {
val counts = io.in.map(_.valid).scanLeft(1.U(k.W)) ((c,e) => Mux(e, (c<<1)(k-1,0), c))
val sels = Transpose(VecInit(counts map (c => VecInit(c.asBools)))) map (col =>
(col zip io.in.map(_.valid)) map {case (c,v) => c && v})
val in_readys = counts map (row => (row.asBools zip io.out.map(_.ready)) map {case (c,r) => c && r} reduce (_||_))
val out_valids = sels map (col => col.reduce(_||_))
val out_data = sels map (s => Mux1H(s, io.in.map(_.bits)))
in_readys zip io.in foreach {case (r,i) => i.ready := r}
out_valids zip out_data zip io.out foreach {case ((v,d),o) => o.valid := v; o.bits := d}
}
}
/**
* Create a queue that can be killed with a branch kill signal.
* Assumption: enq.valid only high if not killed by branch (so don't check IsKilled on io.enq).
*/
class BranchKillableQueue[T <: boom.v3.common.HasBoomUOP](gen: T, entries: Int, flush_fn: boom.v3.common.MicroOp => Bool = u => true.B, flow: Boolean = true)
(implicit p: org.chipsalliance.cde.config.Parameters)
extends boom.v3.common.BoomModule()(p)
with boom.v3.common.HasBoomCoreParameters
{
val io = IO(new Bundle {
val enq = Flipped(Decoupled(gen))
val deq = Decoupled(gen)
val brupdate = Input(new BrUpdateInfo())
val flush = Input(Bool())
val empty = Output(Bool())
val count = Output(UInt(log2Ceil(entries).W))
})
val ram = Mem(entries, gen)
val valids = RegInit(VecInit(Seq.fill(entries) {false.B}))
val uops = Reg(Vec(entries, new MicroOp))
val enq_ptr = Counter(entries)
val deq_ptr = Counter(entries)
val maybe_full = RegInit(false.B)
val ptr_match = enq_ptr.value === deq_ptr.value
io.empty := ptr_match && !maybe_full
val full = ptr_match && maybe_full
val do_enq = WireInit(io.enq.fire)
val do_deq = WireInit((io.deq.ready || !valids(deq_ptr.value)) && !io.empty)
for (i <- 0 until entries) {
val mask = uops(i).br_mask
val uop = uops(i)
valids(i) := valids(i) && !IsKilledByBranch(io.brupdate, mask) && !(io.flush && flush_fn(uop))
when (valids(i)) {
uops(i).br_mask := GetNewBrMask(io.brupdate, mask)
}
}
when (do_enq) {
ram(enq_ptr.value) := io.enq.bits
valids(enq_ptr.value) := true.B //!IsKilledByBranch(io.brupdate, io.enq.bits.uop)
uops(enq_ptr.value) := io.enq.bits.uop
uops(enq_ptr.value).br_mask := GetNewBrMask(io.brupdate, io.enq.bits.uop)
enq_ptr.inc()
}
when (do_deq) {
valids(deq_ptr.value) := false.B
deq_ptr.inc()
}
when (do_enq =/= do_deq) {
maybe_full := do_enq
}
io.enq.ready := !full
val out = Wire(gen)
out := ram(deq_ptr.value)
out.uop := uops(deq_ptr.value)
io.deq.valid := !io.empty && valids(deq_ptr.value) && !IsKilledByBranch(io.brupdate, out.uop) && !(io.flush && flush_fn(out.uop))
io.deq.bits := out
io.deq.bits.uop.br_mask := GetNewBrMask(io.brupdate, out.uop)
// For flow queue behavior.
if (flow) {
when (io.empty) {
io.deq.valid := io.enq.valid //&& !IsKilledByBranch(io.brupdate, io.enq.bits.uop)
io.deq.bits := io.enq.bits
io.deq.bits.uop.br_mask := GetNewBrMask(io.brupdate, io.enq.bits.uop)
do_deq := false.B
when (io.deq.ready) { do_enq := false.B }
}
}
private val ptr_diff = enq_ptr.value - deq_ptr.value
if (isPow2(entries)) {
io.count := Cat(maybe_full && ptr_match, ptr_diff)
}
else {
io.count := Mux(ptr_match,
Mux(maybe_full,
entries.asUInt, 0.U),
Mux(deq_ptr.value > enq_ptr.value,
entries.asUInt + ptr_diff, ptr_diff))
}
}
// ------------------------------------------
// Printf helper functions
// ------------------------------------------
object BoolToChar
{
/**
* Take in a Chisel Bool and convert it into a Str
* based on the Chars given
*
* @param c_bool Chisel Bool
* @param trueChar Scala Char if bool is true
* @param falseChar Scala Char if bool is false
* @return UInt ASCII Char for "trueChar" or "falseChar"
*/
def apply(c_bool: Bool, trueChar: Char, falseChar: Char = '-'): UInt = {
Mux(c_bool, Str(trueChar), Str(falseChar))
}
}
object CfiTypeToChars
{
/**
* Get a Vec of Strs that can be used for printing
*
* @param cfi_type specific cfi type
* @return Vec of Strs (must be indexed to get specific char)
*/
def apply(cfi_type: UInt) = {
val strings = Seq("----", "BR ", "JAL ", "JALR")
val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })
multiVec(cfi_type)
}
}
object BpdTypeToChars
{
/**
* Get a Vec of Strs that can be used for printing
*
* @param bpd_type specific bpd type
* @return Vec of Strs (must be indexed to get specific char)
*/
def apply(bpd_type: UInt) = {
val strings = Seq("BR ", "JUMP", "----", "RET ", "----", "CALL", "----", "----")
val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })
multiVec(bpd_type)
}
}
object RobTypeToChars
{
/**
* Get a Vec of Strs that can be used for printing
*
* @param rob_type specific rob type
* @return Vec of Strs (must be indexed to get specific char)
*/
def apply(rob_type: UInt) = {
val strings = Seq("RST", "NML", "RBK", " WT")
val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })
multiVec(rob_type)
}
}
object XRegToChars
{
/**
* Get a Vec of Strs that can be used for printing
*
* @param xreg specific register number
* @return Vec of Strs (must be indexed to get specific char)
*/
def apply(xreg: UInt) = {
val strings = Seq(" x0", " ra", " sp", " gp",
" tp", " t0", " t1", " t2",
" s0", " s1", " a0", " a1",
" a2", " a3", " a4", " a5",
" a6", " a7", " s2", " s3",
" s4", " s5", " s6", " s7",
" s8", " s9", "s10", "s11",
" t3", " t4", " t5", " t6")
val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })
multiVec(xreg)
}
}
object FPRegToChars
{
/**
* Get a Vec of Strs that can be used for printing
*
* @param fpreg specific register number
* @return Vec of Strs (must be indexed to get specific char)
*/
def apply(fpreg: UInt) = {
val strings = Seq(" ft0", " ft1", " ft2", " ft3",
" ft4", " ft5", " ft6", " ft7",
" fs0", " fs1", " fa0", " fa1",
" fa2", " fa3", " fa4", " fa5",
" fa6", " fa7", " fs2", " fs3",
" fs4", " fs5", " fs6", " fs7",
" fs8", " fs9", "fs10", "fs11",
" ft8", " ft9", "ft10", "ft11")
val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })
multiVec(fpreg)
}
}
object BoomCoreStringPrefix
{
/**
* Add prefix to BOOM strings (currently only adds the hartId)
*
* @param strs list of strings
* @return String combining the list with the prefix per line
*/
def apply(strs: String*)(implicit p: Parameters) = {
val prefix = "[C" + s"${p(TileKey).tileId}" + "] "
strs.map(str => prefix + str + "\n").mkString("")
}
}
File consts.scala:
//******************************************************************************
// Copyright (c) 2011 - 2018, The Regents of the University of California (Regents).
// All Rights Reserved. See LICENSE and LICENSE.SiFive for license details.
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
// RISCV Processor Constants
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
package boom.v3.common.constants
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.util.Str
import freechips.rocketchip.rocket.RVCExpander
/**
* Mixin for issue queue types
*/
trait IQType
{
val IQT_SZ = 3
val IQT_INT = 1.U(IQT_SZ.W)
val IQT_MEM = 2.U(IQT_SZ.W)
val IQT_FP = 4.U(IQT_SZ.W)
val IQT_MFP = 6.U(IQT_SZ.W)
}
/**
* Mixin for scalar operation constants
*/
trait ScalarOpConstants
{
val X = BitPat("b?")
val Y = BitPat("b1")
val N = BitPat("b0")
//************************************
// Extra Constants
// Which branch predictor predicted us
val BSRC_SZ = 2
val BSRC_1 = 0.U(BSRC_SZ.W) // 1-cycle branch pred
val BSRC_2 = 1.U(BSRC_SZ.W) // 2-cycle branch pred
val BSRC_3 = 2.U(BSRC_SZ.W) // 3-cycle branch pred
val BSRC_C = 3.U(BSRC_SZ.W) // core branch resolution
//************************************
// Control Signals
// CFI types
val CFI_SZ = 3
val CFI_X = 0.U(CFI_SZ.W) // Not a CFI instruction
val CFI_BR = 1.U(CFI_SZ.W) // Branch
val CFI_JAL = 2.U(CFI_SZ.W) // JAL
val CFI_JALR = 3.U(CFI_SZ.W) // JALR
// PC Select Signal
val PC_PLUS4 = 0.U(2.W) // PC + 4
val PC_BRJMP = 1.U(2.W) // brjmp_target
val PC_JALR = 2.U(2.W) // jump_reg_target
// Branch Type
val BR_N = 0.U(4.W) // Next
val BR_NE = 1.U(4.W) // Branch on NotEqual
val BR_EQ = 2.U(4.W) // Branch on Equal
val BR_GE = 3.U(4.W) // Branch on Greater/Equal
val BR_GEU = 4.U(4.W) // Branch on Greater/Equal Unsigned
val BR_LT = 5.U(4.W) // Branch on Less Than
val BR_LTU = 6.U(4.W) // Branch on Less Than Unsigned
val BR_J = 7.U(4.W) // Jump
val BR_JR = 8.U(4.W) // Jump Register
// RS1 Operand Select Signal
val OP1_RS1 = 0.U(2.W) // Register Source #1
val OP1_ZERO= 1.U(2.W)
val OP1_PC = 2.U(2.W)
val OP1_X = BitPat("b??")
// RS2 Operand Select Signal
val OP2_RS2 = 0.U(3.W) // Register Source #2
val OP2_IMM = 1.U(3.W) // immediate
val OP2_ZERO= 2.U(3.W) // constant 0
val OP2_NEXT= 3.U(3.W) // constant 2/4 (for PC+2/4)
val OP2_IMMC= 4.U(3.W) // for CSR imm found in RS1
val OP2_X = BitPat("b???")
// Register File Write Enable Signal
val REN_0 = false.B
val REN_1 = true.B
// Is 32b Word or 64b Doubldword?
val SZ_DW = 1
val DW_X = true.B // Bool(xLen==64)
val DW_32 = false.B
val DW_64 = true.B
val DW_XPR = true.B // Bool(xLen==64)
// Memory Enable Signal
val MEN_0 = false.B
val MEN_1 = true.B
val MEN_X = false.B
// Immediate Extend Select
val IS_I = 0.U(3.W) // I-Type (LD,ALU)
val IS_S = 1.U(3.W) // S-Type (ST)
val IS_B = 2.U(3.W) // SB-Type (BR)
val IS_U = 3.U(3.W) // U-Type (LUI/AUIPC)
val IS_J = 4.U(3.W) // UJ-Type (J/JAL)
val IS_X = BitPat("b???")
// Decode Stage Control Signals
val RT_FIX = 0.U(2.W)
val RT_FLT = 1.U(2.W)
val RT_PAS = 3.U(2.W) // pass-through (prs1 := lrs1, etc)
val RT_X = 2.U(2.W) // not-a-register (but shouldn't get a busy-bit, etc.)
// TODO rename RT_NAR
// Micro-op opcodes
// TODO change micro-op opcodes into using enum
val UOPC_SZ = 7
val uopX = BitPat.dontCare(UOPC_SZ)
val uopNOP = 0.U(UOPC_SZ.W)
val uopLD = 1.U(UOPC_SZ.W)
val uopSTA = 2.U(UOPC_SZ.W) // store address generation
val uopSTD = 3.U(UOPC_SZ.W) // store data generation
val uopLUI = 4.U(UOPC_SZ.W)
val uopADDI = 5.U(UOPC_SZ.W)
val uopANDI = 6.U(UOPC_SZ.W)
val uopORI = 7.U(UOPC_SZ.W)
val uopXORI = 8.U(UOPC_SZ.W)
val uopSLTI = 9.U(UOPC_SZ.W)
val uopSLTIU= 10.U(UOPC_SZ.W)
val uopSLLI = 11.U(UOPC_SZ.W)
val uopSRAI = 12.U(UOPC_SZ.W)
val uopSRLI = 13.U(UOPC_SZ.W)
val uopSLL = 14.U(UOPC_SZ.W)
val uopADD = 15.U(UOPC_SZ.W)
val uopSUB = 16.U(UOPC_SZ.W)
val uopSLT = 17.U(UOPC_SZ.W)
val uopSLTU = 18.U(UOPC_SZ.W)
val uopAND = 19.U(UOPC_SZ.W)
val uopOR = 20.U(UOPC_SZ.W)
val uopXOR = 21.U(UOPC_SZ.W)
val uopSRA = 22.U(UOPC_SZ.W)
val uopSRL = 23.U(UOPC_SZ.W)
val uopBEQ = 24.U(UOPC_SZ.W)
val uopBNE = 25.U(UOPC_SZ.W)
val uopBGE = 26.U(UOPC_SZ.W)
val uopBGEU = 27.U(UOPC_SZ.W)
val uopBLT = 28.U(UOPC_SZ.W)
val uopBLTU = 29.U(UOPC_SZ.W)
val uopCSRRW= 30.U(UOPC_SZ.W)
val uopCSRRS= 31.U(UOPC_SZ.W)
val uopCSRRC= 32.U(UOPC_SZ.W)
val uopCSRRWI=33.U(UOPC_SZ.W)
val uopCSRRSI=34.U(UOPC_SZ.W)
val uopCSRRCI=35.U(UOPC_SZ.W)
val uopJ = 36.U(UOPC_SZ.W)
val uopJAL = 37.U(UOPC_SZ.W)
val uopJALR = 38.U(UOPC_SZ.W)
val uopAUIPC= 39.U(UOPC_SZ.W)
//val uopSRET = 40.U(UOPC_SZ.W)
val uopCFLSH= 41.U(UOPC_SZ.W)
val uopFENCE= 42.U(UOPC_SZ.W)
val uopADDIW= 43.U(UOPC_SZ.W)
val uopADDW = 44.U(UOPC_SZ.W)
val uopSUBW = 45.U(UOPC_SZ.W)
val uopSLLIW= 46.U(UOPC_SZ.W)
val uopSLLW = 47.U(UOPC_SZ.W)
val uopSRAIW= 48.U(UOPC_SZ.W)
val uopSRAW = 49.U(UOPC_SZ.W)
val uopSRLIW= 50.U(UOPC_SZ.W)
val uopSRLW = 51.U(UOPC_SZ.W)
val uopMUL = 52.U(UOPC_SZ.W)
val uopMULH = 53.U(UOPC_SZ.W)
val uopMULHU= 54.U(UOPC_SZ.W)
val uopMULHSU=55.U(UOPC_SZ.W)
val uopMULW = 56.U(UOPC_SZ.W)
val uopDIV = 57.U(UOPC_SZ.W)
val uopDIVU = 58.U(UOPC_SZ.W)
val uopREM = 59.U(UOPC_SZ.W)
val uopREMU = 60.U(UOPC_SZ.W)
val uopDIVW = 61.U(UOPC_SZ.W)
val uopDIVUW= 62.U(UOPC_SZ.W)
val uopREMW = 63.U(UOPC_SZ.W)
val uopREMUW= 64.U(UOPC_SZ.W)
val uopFENCEI = 65.U(UOPC_SZ.W)
// = 66.U(UOPC_SZ.W)
val uopAMO_AG = 67.U(UOPC_SZ.W) // AMO-address gen (use normal STD for datagen)
val uopFMV_W_X = 68.U(UOPC_SZ.W)
val uopFMV_D_X = 69.U(UOPC_SZ.W)
val uopFMV_X_W = 70.U(UOPC_SZ.W)
val uopFMV_X_D = 71.U(UOPC_SZ.W)
val uopFSGNJ_S = 72.U(UOPC_SZ.W)
val uopFSGNJ_D = 73.U(UOPC_SZ.W)
val uopFCVT_S_D = 74.U(UOPC_SZ.W)
val uopFCVT_D_S = 75.U(UOPC_SZ.W)
val uopFCVT_S_X = 76.U(UOPC_SZ.W)
val uopFCVT_D_X = 77.U(UOPC_SZ.W)
val uopFCVT_X_S = 78.U(UOPC_SZ.W)
val uopFCVT_X_D = 79.U(UOPC_SZ.W)
val uopCMPR_S = 80.U(UOPC_SZ.W)
val uopCMPR_D = 81.U(UOPC_SZ.W)
val uopFCLASS_S = 82.U(UOPC_SZ.W)
val uopFCLASS_D = 83.U(UOPC_SZ.W)
val uopFMINMAX_S = 84.U(UOPC_SZ.W)
val uopFMINMAX_D = 85.U(UOPC_SZ.W)
// = 86.U(UOPC_SZ.W)
val uopFADD_S = 87.U(UOPC_SZ.W)
val uopFSUB_S = 88.U(UOPC_SZ.W)
val uopFMUL_S = 89.U(UOPC_SZ.W)
val uopFADD_D = 90.U(UOPC_SZ.W)
val uopFSUB_D = 91.U(UOPC_SZ.W)
val uopFMUL_D = 92.U(UOPC_SZ.W)
val uopFMADD_S = 93.U(UOPC_SZ.W)
val uopFMSUB_S = 94.U(UOPC_SZ.W)
val uopFNMADD_S = 95.U(UOPC_SZ.W)
val uopFNMSUB_S = 96.U(UOPC_SZ.W)
val uopFMADD_D = 97.U(UOPC_SZ.W)
val uopFMSUB_D = 98.U(UOPC_SZ.W)
val uopFNMADD_D = 99.U(UOPC_SZ.W)
val uopFNMSUB_D = 100.U(UOPC_SZ.W)
val uopFDIV_S = 101.U(UOPC_SZ.W)
val uopFDIV_D = 102.U(UOPC_SZ.W)
val uopFSQRT_S = 103.U(UOPC_SZ.W)
val uopFSQRT_D = 104.U(UOPC_SZ.W)
val uopWFI = 105.U(UOPC_SZ.W) // pass uop down the CSR pipeline
val uopERET = 106.U(UOPC_SZ.W) // pass uop down the CSR pipeline, also is ERET
val uopSFENCE = 107.U(UOPC_SZ.W)
val uopROCC = 108.U(UOPC_SZ.W)
val uopMOV = 109.U(UOPC_SZ.W) // conditional mov decoded from "add rd, x0, rs2"
// The Bubble Instruction (Machine generated NOP)
// Insert (XOR x0,x0,x0) which is different from software compiler
// generated NOPs which are (ADDI x0, x0, 0).
// Reasoning for this is to let visualizers and stat-trackers differentiate
// between software NOPs and machine-generated Bubbles in the pipeline.
val BUBBLE = (0x4033).U(32.W)
def NullMicroOp()(implicit p: Parameters): boom.v3.common.MicroOp = {
val uop = Wire(new boom.v3.common.MicroOp)
uop := DontCare // Overridden in the following lines
uop.uopc := uopNOP // maybe not required, but helps on asserts that try to catch spurious behavior
uop.bypassable := false.B
uop.fp_val := false.B
uop.uses_stq := false.B
uop.uses_ldq := false.B
uop.pdst := 0.U
uop.dst_rtype := RT_X
val cs = Wire(new boom.v3.common.CtrlSignals())
cs := DontCare // Overridden in the following lines
cs.br_type := BR_N
cs.csr_cmd := freechips.rocketchip.rocket.CSR.N
cs.is_load := false.B
cs.is_sta := false.B
cs.is_std := false.B
uop.ctrl := cs
uop
}
}
/**
* Mixin for RISCV constants
*/
trait RISCVConstants
{
// abstract out instruction decode magic numbers
val RD_MSB = 11
val RD_LSB = 7
val RS1_MSB = 19
val RS1_LSB = 15
val RS2_MSB = 24
val RS2_LSB = 20
val RS3_MSB = 31
val RS3_LSB = 27
val CSR_ADDR_MSB = 31
val CSR_ADDR_LSB = 20
val CSR_ADDR_SZ = 12
// location of the fifth bit in the shamt (for checking for illegal ops for SRAIW,etc.)
val SHAMT_5_BIT = 25
val LONGEST_IMM_SZ = 20
val X0 = 0.U
val RA = 1.U // return address register
// memory consistency model
// The C/C++ atomics MCM requires that two loads to the same address maintain program order.
// The Cortex A9 does NOT enforce load/load ordering (which leads to buggy behavior).
val MCM_ORDER_DEPENDENT_LOADS = true
val jal_opc = (0x6f).U
val jalr_opc = (0x67).U
def GetUop(inst: UInt): UInt = inst(6,0)
def GetRd (inst: UInt): UInt = inst(RD_MSB,RD_LSB)
def GetRs1(inst: UInt): UInt = inst(RS1_MSB,RS1_LSB)
def ExpandRVC(inst: UInt)(implicit p: Parameters): UInt = {
val rvc_exp = Module(new RVCExpander)
rvc_exp.io.in := inst
Mux(rvc_exp.io.rvc, rvc_exp.io.out.bits, inst)
}
// Note: Accepts only EXPANDED rvc instructions
def ComputeBranchTarget(pc: UInt, inst: UInt, xlen: Int)(implicit p: Parameters): UInt = {
val b_imm32 = Cat(Fill(20,inst(31)), inst(7), inst(30,25), inst(11,8), 0.U(1.W))
((pc.asSInt + b_imm32.asSInt).asSInt & (-2).S).asUInt
}
// Note: Accepts only EXPANDED rvc instructions
def ComputeJALTarget(pc: UInt, inst: UInt, xlen: Int)(implicit p: Parameters): UInt = {
val j_imm32 = Cat(Fill(12,inst(31)), inst(19,12), inst(20), inst(30,25), inst(24,21), 0.U(1.W))
((pc.asSInt + j_imm32.asSInt).asSInt & (-2).S).asUInt
}
// Note: Accepts only EXPANDED rvc instructions
def GetCfiType(inst: UInt)(implicit p: Parameters): UInt = {
val bdecode = Module(new boom.v3.exu.BranchDecode)
bdecode.io.inst := inst
bdecode.io.pc := 0.U
bdecode.io.out.cfi_type
}
}
/**
* Mixin for exception cause constants
*/
trait ExcCauseConstants
{
// a memory disambigious misspeculation occurred
val MINI_EXCEPTION_MEM_ORDERING = 16.U
val MINI_EXCEPTION_CSR_REPLAY = 17.U
require (!freechips.rocketchip.rocket.Causes.all.contains(16))
require (!freechips.rocketchip.rocket.Causes.all.contains(17))
}
File issue-slot.scala:
//******************************************************************************
// Copyright (c) 2015 - 2018, The Regents of the University of California (Regents).
// All Rights Reserved. See LICENSE and LICENSE.SiFive for license details.
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
// RISCV Processor Issue Slot Logic
//--------------------------------------------------------------------------
//------------------------------------------------------------------------------
//
// Note: stores (and AMOs) are "broken down" into 2 uops, but stored within a single issue-slot.
// TODO XXX make a separate issueSlot for MemoryIssueSlots, and only they break apart stores.
// TODO Disable ldspec for FP queue.
package boom.v3.exu
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.Parameters
import boom.v3.common._
import boom.v3.util._
import FUConstants._
/**
* IO bundle to interact with Issue slot
*
* @param numWakeupPorts number of wakeup ports for the slot
*/
class IssueSlotIO(val numWakeupPorts: Int)(implicit p: Parameters) extends BoomBundle
{
val valid = Output(Bool())
val will_be_valid = Output(Bool()) // TODO code review, do we need this signal so explicitely?
val request = Output(Bool())
val request_hp = Output(Bool())
val grant = Input(Bool())
val brupdate = Input(new BrUpdateInfo())
val kill = Input(Bool()) // pipeline flush
val clear = Input(Bool()) // entry being moved elsewhere (not mutually exclusive with grant)
val ldspec_miss = Input(Bool()) // Previous cycle's speculative load wakeup was mispredicted.
val wakeup_ports = Flipped(Vec(numWakeupPorts, Valid(new IqWakeup(maxPregSz))))
val pred_wakeup_port = Flipped(Valid(UInt(log2Ceil(ftqSz).W)))
val spec_ld_wakeup = Flipped(Vec(memWidth, Valid(UInt(width=maxPregSz.W))))
val in_uop = Flipped(Valid(new MicroOp())) // if valid, this WILL overwrite an entry!
val out_uop = Output(new MicroOp()) // the updated slot uop; will be shifted upwards in a collasping queue.
val uop = Output(new MicroOp()) // the current Slot's uop. Sent down the pipeline when issued.
val debug = {
val result = new Bundle {
val p1 = Bool()
val p2 = Bool()
val p3 = Bool()
val ppred = Bool()
val state = UInt(width=2.W)
}
Output(result)
}
}
/**
* Single issue slot. Holds a uop within the issue queue
*
* @param numWakeupPorts number of wakeup ports
*/
class IssueSlot(val numWakeupPorts: Int)(implicit p: Parameters)
extends BoomModule
with IssueUnitConstants
{
val io = IO(new IssueSlotIO(numWakeupPorts))
// slot invalid?
// slot is valid, holding 1 uop
// slot is valid, holds 2 uops (like a store)
def is_invalid = state === s_invalid
def is_valid = state =/= s_invalid
val next_state = Wire(UInt()) // the next state of this slot (which might then get moved to a new slot)
val next_uopc = Wire(UInt()) // the next uopc of this slot (which might then get moved to a new slot)
val next_lrs1_rtype = Wire(UInt()) // the next reg type of this slot (which might then get moved to a new slot)
val next_lrs2_rtype = Wire(UInt()) // the next reg type of this slot (which might then get moved to a new slot)
val state = RegInit(s_invalid)
val p1 = RegInit(false.B)
val p2 = RegInit(false.B)
val p3 = RegInit(false.B)
val ppred = RegInit(false.B)
// Poison if woken up by speculative load.
// Poison lasts 1 cycle (as ldMiss will come on the next cycle).
// SO if poisoned is true, set it to false!
val p1_poisoned = RegInit(false.B)
val p2_poisoned = RegInit(false.B)
p1_poisoned := false.B
p2_poisoned := false.B
val next_p1_poisoned = Mux(io.in_uop.valid, io.in_uop.bits.iw_p1_poisoned, p1_poisoned)
val next_p2_poisoned = Mux(io.in_uop.valid, io.in_uop.bits.iw_p2_poisoned, p2_poisoned)
val slot_uop = RegInit(NullMicroOp)
val next_uop = Mux(io.in_uop.valid, io.in_uop.bits, slot_uop)
//-----------------------------------------------------------------------------
// next slot state computation
// compute the next state for THIS entry slot (in a collasping queue, the
// current uop may get moved elsewhere, and a new uop can enter
when (io.kill) {
state := s_invalid
} .elsewhen (io.in_uop.valid) {
state := io.in_uop.bits.iw_state
} .elsewhen (io.clear) {
state := s_invalid
} .otherwise {
state := next_state
}
//-----------------------------------------------------------------------------
// "update" state
// compute the next state for the micro-op in this slot. This micro-op may
// be moved elsewhere, so the "next_state" travels with it.
// defaults
next_state := state
next_uopc := slot_uop.uopc
next_lrs1_rtype := slot_uop.lrs1_rtype
next_lrs2_rtype := slot_uop.lrs2_rtype
when (io.kill) {
next_state := s_invalid
} .elsewhen ((io.grant && (state === s_valid_1)) ||
(io.grant && (state === s_valid_2) && p1 && p2 && ppred)) {
// try to issue this uop.
when (!(io.ldspec_miss && (p1_poisoned || p2_poisoned))) {
next_state := s_invalid
}
} .elsewhen (io.grant && (state === s_valid_2)) {
when (!(io.ldspec_miss && (p1_poisoned || p2_poisoned))) {
next_state := s_valid_1
when (p1) {
slot_uop.uopc := uopSTD
next_uopc := uopSTD
slot_uop.lrs1_rtype := RT_X
next_lrs1_rtype := RT_X
} .otherwise {
slot_uop.lrs2_rtype := RT_X
next_lrs2_rtype := RT_X
}
}
}
when (io.in_uop.valid) {
slot_uop := io.in_uop.bits
assert (is_invalid || io.clear || io.kill, "trying to overwrite a valid issue slot.")
}
// Wakeup Compare Logic
// these signals are the "next_p*" for the current slot's micro-op.
// they are important for shifting the current slot_uop up to an other entry.
val next_p1 = WireInit(p1)
val next_p2 = WireInit(p2)
val next_p3 = WireInit(p3)
val next_ppred = WireInit(ppred)
when (io.in_uop.valid) {
p1 := !(io.in_uop.bits.prs1_busy)
p2 := !(io.in_uop.bits.prs2_busy)
p3 := !(io.in_uop.bits.prs3_busy)
ppred := !(io.in_uop.bits.ppred_busy)
}
when (io.ldspec_miss && next_p1_poisoned) {
assert(next_uop.prs1 =/= 0.U, "Poison bit can't be set for prs1=x0!")
p1 := false.B
}
when (io.ldspec_miss && next_p2_poisoned) {
assert(next_uop.prs2 =/= 0.U, "Poison bit can't be set for prs2=x0!")
p2 := false.B
}
for (i <- 0 until numWakeupPorts) {
when (io.wakeup_ports(i).valid &&
(io.wakeup_ports(i).bits.pdst === next_uop.prs1)) {
p1 := true.B
}
when (io.wakeup_ports(i).valid &&
(io.wakeup_ports(i).bits.pdst === next_uop.prs2)) {
p2 := true.B
}
when (io.wakeup_ports(i).valid &&
(io.wakeup_ports(i).bits.pdst === next_uop.prs3)) {
p3 := true.B
}
}
when (io.pred_wakeup_port.valid && io.pred_wakeup_port.bits === next_uop.ppred) {
ppred := true.B
}
for (w <- 0 until memWidth) {
assert (!(io.spec_ld_wakeup(w).valid && io.spec_ld_wakeup(w).bits === 0.U),
"Loads to x0 should never speculatively wakeup other instructions")
}
// TODO disable if FP IQ.
for (w <- 0 until memWidth) {
when (io.spec_ld_wakeup(w).valid &&
io.spec_ld_wakeup(w).bits === next_uop.prs1 &&
next_uop.lrs1_rtype === RT_FIX) {
p1 := true.B
p1_poisoned := true.B
assert (!next_p1_poisoned)
}
when (io.spec_ld_wakeup(w).valid &&
io.spec_ld_wakeup(w).bits === next_uop.prs2 &&
next_uop.lrs2_rtype === RT_FIX) {
p2 := true.B
p2_poisoned := true.B
assert (!next_p2_poisoned)
}
}
// Handle branch misspeculations
val next_br_mask = GetNewBrMask(io.brupdate, slot_uop)
// was this micro-op killed by a branch? if yes, we can't let it be valid if
// we compact it into an other entry
when (IsKilledByBranch(io.brupdate, slot_uop)) {
next_state := s_invalid
}
when (!io.in_uop.valid) {
slot_uop.br_mask := next_br_mask
}
//-------------------------------------------------------------
// Request Logic
io.request := is_valid && p1 && p2 && p3 && ppred && !io.kill
val high_priority = slot_uop.is_br || slot_uop.is_jal || slot_uop.is_jalr
io.request_hp := io.request && high_priority
when (state === s_valid_1) {
io.request := p1 && p2 && p3 && ppred && !io.kill
} .elsewhen (state === s_valid_2) {
io.request := (p1 || p2) && ppred && !io.kill
} .otherwise {
io.request := false.B
}
//assign outputs
io.valid := is_valid
io.uop := slot_uop
io.uop.iw_p1_poisoned := p1_poisoned
io.uop.iw_p2_poisoned := p2_poisoned
// micro-op will vacate due to grant.
val may_vacate = io.grant && ((state === s_valid_1) || (state === s_valid_2) && p1 && p2 && ppred)
val squash_grant = io.ldspec_miss && (p1_poisoned || p2_poisoned)
io.will_be_valid := is_valid && !(may_vacate && !squash_grant)
io.out_uop := slot_uop
io.out_uop.iw_state := next_state
io.out_uop.uopc := next_uopc
io.out_uop.lrs1_rtype := next_lrs1_rtype
io.out_uop.lrs2_rtype := next_lrs2_rtype
io.out_uop.br_mask := next_br_mask
io.out_uop.prs1_busy := !p1
io.out_uop.prs2_busy := !p2
io.out_uop.prs3_busy := !p3
io.out_uop.ppred_busy := !ppred
io.out_uop.iw_p1_poisoned := p1_poisoned
io.out_uop.iw_p2_poisoned := p2_poisoned
when (state === s_valid_2) {
when (p1 && p2 && ppred) {
; // send out the entire instruction as one uop
} .elsewhen (p1 && ppred) {
io.uop.uopc := slot_uop.uopc
io.uop.lrs2_rtype := RT_X
} .elsewhen (p2 && ppred) {
io.uop.uopc := uopSTD
io.uop.lrs1_rtype := RT_X
}
}
// debug outputs
io.debug.p1 := p1
io.debug.p2 := p2
io.debug.p3 := p3
io.debug.ppred := ppred
io.debug.state := state
}
| module IssueSlot_27( // @[issue-slot.scala:69:7]
input clock, // @[issue-slot.scala:69:7]
input reset, // @[issue-slot.scala:69:7]
output io_valid, // @[issue-slot.scala:73:14]
output io_will_be_valid, // @[issue-slot.scala:73:14]
output io_request, // @[issue-slot.scala:73:14]
output io_request_hp, // @[issue-slot.scala:73:14]
input io_grant, // @[issue-slot.scala:73:14]
input [15:0] io_brupdate_b1_resolve_mask, // @[issue-slot.scala:73:14]
input [15:0] io_brupdate_b1_mispredict_mask, // @[issue-slot.scala:73:14]
input [6:0] io_brupdate_b2_uop_uopc, // @[issue-slot.scala:73:14]
input [31:0] io_brupdate_b2_uop_inst, // @[issue-slot.scala:73:14]
input [31:0] io_brupdate_b2_uop_debug_inst, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_rvc, // @[issue-slot.scala:73:14]
input [39:0] io_brupdate_b2_uop_debug_pc, // @[issue-slot.scala:73:14]
input [2:0] io_brupdate_b2_uop_iq_type, // @[issue-slot.scala:73:14]
input [9:0] io_brupdate_b2_uop_fu_code, // @[issue-slot.scala:73:14]
input [3:0] io_brupdate_b2_uop_ctrl_br_type, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14]
input [2:0] io_brupdate_b2_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14]
input [2:0] io_brupdate_b2_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14]
input [4:0] io_brupdate_b2_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14]
input [2:0] io_brupdate_b2_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_ctrl_is_load, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_ctrl_is_sta, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_ctrl_is_std, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_uop_iw_state, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_iw_p1_poisoned, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_iw_p2_poisoned, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_br, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_jalr, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_jal, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_sfb, // @[issue-slot.scala:73:14]
input [15:0] io_brupdate_b2_uop_br_mask, // @[issue-slot.scala:73:14]
input [3:0] io_brupdate_b2_uop_br_tag, // @[issue-slot.scala:73:14]
input [4:0] io_brupdate_b2_uop_ftq_idx, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_edge_inst, // @[issue-slot.scala:73:14]
input [5:0] io_brupdate_b2_uop_pc_lob, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_taken, // @[issue-slot.scala:73:14]
input [19:0] io_brupdate_b2_uop_imm_packed, // @[issue-slot.scala:73:14]
input [11:0] io_brupdate_b2_uop_csr_addr, // @[issue-slot.scala:73:14]
input [6:0] io_brupdate_b2_uop_rob_idx, // @[issue-slot.scala:73:14]
input [4:0] io_brupdate_b2_uop_ldq_idx, // @[issue-slot.scala:73:14]
input [4:0] io_brupdate_b2_uop_stq_idx, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_uop_rxq_idx, // @[issue-slot.scala:73:14]
input [6:0] io_brupdate_b2_uop_pdst, // @[issue-slot.scala:73:14]
input [6:0] io_brupdate_b2_uop_prs1, // @[issue-slot.scala:73:14]
input [6:0] io_brupdate_b2_uop_prs2, // @[issue-slot.scala:73:14]
input [6:0] io_brupdate_b2_uop_prs3, // @[issue-slot.scala:73:14]
input [4:0] io_brupdate_b2_uop_ppred, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_prs1_busy, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_prs2_busy, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_prs3_busy, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_ppred_busy, // @[issue-slot.scala:73:14]
input [6:0] io_brupdate_b2_uop_stale_pdst, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_exception, // @[issue-slot.scala:73:14]
input [63:0] io_brupdate_b2_uop_exc_cause, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_bypassable, // @[issue-slot.scala:73:14]
input [4:0] io_brupdate_b2_uop_mem_cmd, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_uop_mem_size, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_mem_signed, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_fence, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_fencei, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_amo, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_uses_ldq, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_uses_stq, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_unique, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_flush_on_commit, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_ldst_is_rs1, // @[issue-slot.scala:73:14]
input [5:0] io_brupdate_b2_uop_ldst, // @[issue-slot.scala:73:14]
input [5:0] io_brupdate_b2_uop_lrs1, // @[issue-slot.scala:73:14]
input [5:0] io_brupdate_b2_uop_lrs2, // @[issue-slot.scala:73:14]
input [5:0] io_brupdate_b2_uop_lrs3, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_ldst_val, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_uop_dst_rtype, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_uop_lrs1_rtype, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_uop_lrs2_rtype, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_frs3_en, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_fp_val, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_fp_single, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_xcpt_pf_if, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_xcpt_ae_if, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_xcpt_ma_if, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_bp_debug_if, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_bp_xcpt_if, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_uop_debug_fsrc, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_uop_debug_tsrc, // @[issue-slot.scala:73:14]
input io_brupdate_b2_valid, // @[issue-slot.scala:73:14]
input io_brupdate_b2_mispredict, // @[issue-slot.scala:73:14]
input io_brupdate_b2_taken, // @[issue-slot.scala:73:14]
input [2:0] io_brupdate_b2_cfi_type, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_pc_sel, // @[issue-slot.scala:73:14]
input [39:0] io_brupdate_b2_jalr_target, // @[issue-slot.scala:73:14]
input [20:0] io_brupdate_b2_target_offset, // @[issue-slot.scala:73:14]
input io_kill, // @[issue-slot.scala:73:14]
input io_clear, // @[issue-slot.scala:73:14]
input io_ldspec_miss, // @[issue-slot.scala:73:14]
input io_wakeup_ports_0_valid, // @[issue-slot.scala:73:14]
input [6:0] io_wakeup_ports_0_bits_pdst, // @[issue-slot.scala:73:14]
input io_wakeup_ports_0_bits_poisoned, // @[issue-slot.scala:73:14]
input io_wakeup_ports_1_valid, // @[issue-slot.scala:73:14]
input [6:0] io_wakeup_ports_1_bits_pdst, // @[issue-slot.scala:73:14]
input io_wakeup_ports_1_bits_poisoned, // @[issue-slot.scala:73:14]
input io_wakeup_ports_2_valid, // @[issue-slot.scala:73:14]
input [6:0] io_wakeup_ports_2_bits_pdst, // @[issue-slot.scala:73:14]
input io_wakeup_ports_2_bits_poisoned, // @[issue-slot.scala:73:14]
input io_wakeup_ports_3_valid, // @[issue-slot.scala:73:14]
input [6:0] io_wakeup_ports_3_bits_pdst, // @[issue-slot.scala:73:14]
input io_wakeup_ports_3_bits_poisoned, // @[issue-slot.scala:73:14]
input io_wakeup_ports_4_valid, // @[issue-slot.scala:73:14]
input [6:0] io_wakeup_ports_4_bits_pdst, // @[issue-slot.scala:73:14]
input io_wakeup_ports_4_bits_poisoned, // @[issue-slot.scala:73:14]
input io_wakeup_ports_5_valid, // @[issue-slot.scala:73:14]
input [6:0] io_wakeup_ports_5_bits_pdst, // @[issue-slot.scala:73:14]
input io_wakeup_ports_5_bits_poisoned, // @[issue-slot.scala:73:14]
input io_wakeup_ports_6_valid, // @[issue-slot.scala:73:14]
input [6:0] io_wakeup_ports_6_bits_pdst, // @[issue-slot.scala:73:14]
input io_wakeup_ports_6_bits_poisoned, // @[issue-slot.scala:73:14]
input io_spec_ld_wakeup_0_valid, // @[issue-slot.scala:73:14]
input [6:0] io_spec_ld_wakeup_0_bits, // @[issue-slot.scala:73:14]
input io_in_uop_valid, // @[issue-slot.scala:73:14]
input [6:0] io_in_uop_bits_uopc, // @[issue-slot.scala:73:14]
input [31:0] io_in_uop_bits_inst, // @[issue-slot.scala:73:14]
input [31:0] io_in_uop_bits_debug_inst, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_rvc, // @[issue-slot.scala:73:14]
input [39:0] io_in_uop_bits_debug_pc, // @[issue-slot.scala:73:14]
input [2:0] io_in_uop_bits_iq_type, // @[issue-slot.scala:73:14]
input [9:0] io_in_uop_bits_fu_code, // @[issue-slot.scala:73:14]
input [3:0] io_in_uop_bits_ctrl_br_type, // @[issue-slot.scala:73:14]
input [1:0] io_in_uop_bits_ctrl_op1_sel, // @[issue-slot.scala:73:14]
input [2:0] io_in_uop_bits_ctrl_op2_sel, // @[issue-slot.scala:73:14]
input [2:0] io_in_uop_bits_ctrl_imm_sel, // @[issue-slot.scala:73:14]
input [4:0] io_in_uop_bits_ctrl_op_fcn, // @[issue-slot.scala:73:14]
input io_in_uop_bits_ctrl_fcn_dw, // @[issue-slot.scala:73:14]
input [2:0] io_in_uop_bits_ctrl_csr_cmd, // @[issue-slot.scala:73:14]
input io_in_uop_bits_ctrl_is_load, // @[issue-slot.scala:73:14]
input io_in_uop_bits_ctrl_is_sta, // @[issue-slot.scala:73:14]
input io_in_uop_bits_ctrl_is_std, // @[issue-slot.scala:73:14]
input [1:0] io_in_uop_bits_iw_state, // @[issue-slot.scala:73:14]
input io_in_uop_bits_iw_p1_poisoned, // @[issue-slot.scala:73:14]
input io_in_uop_bits_iw_p2_poisoned, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_br, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_jalr, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_jal, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_sfb, // @[issue-slot.scala:73:14]
input [15:0] io_in_uop_bits_br_mask, // @[issue-slot.scala:73:14]
input [3:0] io_in_uop_bits_br_tag, // @[issue-slot.scala:73:14]
input [4:0] io_in_uop_bits_ftq_idx, // @[issue-slot.scala:73:14]
input io_in_uop_bits_edge_inst, // @[issue-slot.scala:73:14]
input [5:0] io_in_uop_bits_pc_lob, // @[issue-slot.scala:73:14]
input io_in_uop_bits_taken, // @[issue-slot.scala:73:14]
input [19:0] io_in_uop_bits_imm_packed, // @[issue-slot.scala:73:14]
input [11:0] io_in_uop_bits_csr_addr, // @[issue-slot.scala:73:14]
input [6:0] io_in_uop_bits_rob_idx, // @[issue-slot.scala:73:14]
input [4:0] io_in_uop_bits_ldq_idx, // @[issue-slot.scala:73:14]
input [4:0] io_in_uop_bits_stq_idx, // @[issue-slot.scala:73:14]
input [1:0] io_in_uop_bits_rxq_idx, // @[issue-slot.scala:73:14]
input [6:0] io_in_uop_bits_pdst, // @[issue-slot.scala:73:14]
input [6:0] io_in_uop_bits_prs1, // @[issue-slot.scala:73:14]
input [6:0] io_in_uop_bits_prs2, // @[issue-slot.scala:73:14]
input [6:0] io_in_uop_bits_prs3, // @[issue-slot.scala:73:14]
input [4:0] io_in_uop_bits_ppred, // @[issue-slot.scala:73:14]
input io_in_uop_bits_prs1_busy, // @[issue-slot.scala:73:14]
input io_in_uop_bits_prs2_busy, // @[issue-slot.scala:73:14]
input io_in_uop_bits_prs3_busy, // @[issue-slot.scala:73:14]
input io_in_uop_bits_ppred_busy, // @[issue-slot.scala:73:14]
input [6:0] io_in_uop_bits_stale_pdst, // @[issue-slot.scala:73:14]
input io_in_uop_bits_exception, // @[issue-slot.scala:73:14]
input [63:0] io_in_uop_bits_exc_cause, // @[issue-slot.scala:73:14]
input io_in_uop_bits_bypassable, // @[issue-slot.scala:73:14]
input [4:0] io_in_uop_bits_mem_cmd, // @[issue-slot.scala:73:14]
input [1:0] io_in_uop_bits_mem_size, // @[issue-slot.scala:73:14]
input io_in_uop_bits_mem_signed, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_fence, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_fencei, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_amo, // @[issue-slot.scala:73:14]
input io_in_uop_bits_uses_ldq, // @[issue-slot.scala:73:14]
input io_in_uop_bits_uses_stq, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_sys_pc2epc, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_unique, // @[issue-slot.scala:73:14]
input io_in_uop_bits_flush_on_commit, // @[issue-slot.scala:73:14]
input io_in_uop_bits_ldst_is_rs1, // @[issue-slot.scala:73:14]
input [5:0] io_in_uop_bits_ldst, // @[issue-slot.scala:73:14]
input [5:0] io_in_uop_bits_lrs1, // @[issue-slot.scala:73:14]
input [5:0] io_in_uop_bits_lrs2, // @[issue-slot.scala:73:14]
input [5:0] io_in_uop_bits_lrs3, // @[issue-slot.scala:73:14]
input io_in_uop_bits_ldst_val, // @[issue-slot.scala:73:14]
input [1:0] io_in_uop_bits_dst_rtype, // @[issue-slot.scala:73:14]
input [1:0] io_in_uop_bits_lrs1_rtype, // @[issue-slot.scala:73:14]
input [1:0] io_in_uop_bits_lrs2_rtype, // @[issue-slot.scala:73:14]
input io_in_uop_bits_frs3_en, // @[issue-slot.scala:73:14]
input io_in_uop_bits_fp_val, // @[issue-slot.scala:73:14]
input io_in_uop_bits_fp_single, // @[issue-slot.scala:73:14]
input io_in_uop_bits_xcpt_pf_if, // @[issue-slot.scala:73:14]
input io_in_uop_bits_xcpt_ae_if, // @[issue-slot.scala:73:14]
input io_in_uop_bits_xcpt_ma_if, // @[issue-slot.scala:73:14]
input io_in_uop_bits_bp_debug_if, // @[issue-slot.scala:73:14]
input io_in_uop_bits_bp_xcpt_if, // @[issue-slot.scala:73:14]
input [1:0] io_in_uop_bits_debug_fsrc, // @[issue-slot.scala:73:14]
input [1:0] io_in_uop_bits_debug_tsrc, // @[issue-slot.scala:73:14]
output [6:0] io_out_uop_uopc, // @[issue-slot.scala:73:14]
output [31:0] io_out_uop_inst, // @[issue-slot.scala:73:14]
output [31:0] io_out_uop_debug_inst, // @[issue-slot.scala:73:14]
output io_out_uop_is_rvc, // @[issue-slot.scala:73:14]
output [39:0] io_out_uop_debug_pc, // @[issue-slot.scala:73:14]
output [2:0] io_out_uop_iq_type, // @[issue-slot.scala:73:14]
output [9:0] io_out_uop_fu_code, // @[issue-slot.scala:73:14]
output [3:0] io_out_uop_ctrl_br_type, // @[issue-slot.scala:73:14]
output [1:0] io_out_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14]
output [2:0] io_out_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14]
output [2:0] io_out_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14]
output [4:0] io_out_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14]
output io_out_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14]
output [2:0] io_out_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14]
output io_out_uop_ctrl_is_load, // @[issue-slot.scala:73:14]
output io_out_uop_ctrl_is_sta, // @[issue-slot.scala:73:14]
output io_out_uop_ctrl_is_std, // @[issue-slot.scala:73:14]
output [1:0] io_out_uop_iw_state, // @[issue-slot.scala:73:14]
output io_out_uop_iw_p1_poisoned, // @[issue-slot.scala:73:14]
output io_out_uop_iw_p2_poisoned, // @[issue-slot.scala:73:14]
output io_out_uop_is_br, // @[issue-slot.scala:73:14]
output io_out_uop_is_jalr, // @[issue-slot.scala:73:14]
output io_out_uop_is_jal, // @[issue-slot.scala:73:14]
output io_out_uop_is_sfb, // @[issue-slot.scala:73:14]
output [15:0] io_out_uop_br_mask, // @[issue-slot.scala:73:14]
output [3:0] io_out_uop_br_tag, // @[issue-slot.scala:73:14]
output [4:0] io_out_uop_ftq_idx, // @[issue-slot.scala:73:14]
output io_out_uop_edge_inst, // @[issue-slot.scala:73:14]
output [5:0] io_out_uop_pc_lob, // @[issue-slot.scala:73:14]
output io_out_uop_taken, // @[issue-slot.scala:73:14]
output [19:0] io_out_uop_imm_packed, // @[issue-slot.scala:73:14]
output [11:0] io_out_uop_csr_addr, // @[issue-slot.scala:73:14]
output [6:0] io_out_uop_rob_idx, // @[issue-slot.scala:73:14]
output [4:0] io_out_uop_ldq_idx, // @[issue-slot.scala:73:14]
output [4:0] io_out_uop_stq_idx, // @[issue-slot.scala:73:14]
output [1:0] io_out_uop_rxq_idx, // @[issue-slot.scala:73:14]
output [6:0] io_out_uop_pdst, // @[issue-slot.scala:73:14]
output [6:0] io_out_uop_prs1, // @[issue-slot.scala:73:14]
output [6:0] io_out_uop_prs2, // @[issue-slot.scala:73:14]
output [6:0] io_out_uop_prs3, // @[issue-slot.scala:73:14]
output [4:0] io_out_uop_ppred, // @[issue-slot.scala:73:14]
output io_out_uop_prs1_busy, // @[issue-slot.scala:73:14]
output io_out_uop_prs2_busy, // @[issue-slot.scala:73:14]
output io_out_uop_prs3_busy, // @[issue-slot.scala:73:14]
output io_out_uop_ppred_busy, // @[issue-slot.scala:73:14]
output [6:0] io_out_uop_stale_pdst, // @[issue-slot.scala:73:14]
output io_out_uop_exception, // @[issue-slot.scala:73:14]
output [63:0] io_out_uop_exc_cause, // @[issue-slot.scala:73:14]
output io_out_uop_bypassable, // @[issue-slot.scala:73:14]
output [4:0] io_out_uop_mem_cmd, // @[issue-slot.scala:73:14]
output [1:0] io_out_uop_mem_size, // @[issue-slot.scala:73:14]
output io_out_uop_mem_signed, // @[issue-slot.scala:73:14]
output io_out_uop_is_fence, // @[issue-slot.scala:73:14]
output io_out_uop_is_fencei, // @[issue-slot.scala:73:14]
output io_out_uop_is_amo, // @[issue-slot.scala:73:14]
output io_out_uop_uses_ldq, // @[issue-slot.scala:73:14]
output io_out_uop_uses_stq, // @[issue-slot.scala:73:14]
output io_out_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14]
output io_out_uop_is_unique, // @[issue-slot.scala:73:14]
output io_out_uop_flush_on_commit, // @[issue-slot.scala:73:14]
output io_out_uop_ldst_is_rs1, // @[issue-slot.scala:73:14]
output [5:0] io_out_uop_ldst, // @[issue-slot.scala:73:14]
output [5:0] io_out_uop_lrs1, // @[issue-slot.scala:73:14]
output [5:0] io_out_uop_lrs2, // @[issue-slot.scala:73:14]
output [5:0] io_out_uop_lrs3, // @[issue-slot.scala:73:14]
output io_out_uop_ldst_val, // @[issue-slot.scala:73:14]
output [1:0] io_out_uop_dst_rtype, // @[issue-slot.scala:73:14]
output [1:0] io_out_uop_lrs1_rtype, // @[issue-slot.scala:73:14]
output [1:0] io_out_uop_lrs2_rtype, // @[issue-slot.scala:73:14]
output io_out_uop_frs3_en, // @[issue-slot.scala:73:14]
output io_out_uop_fp_val, // @[issue-slot.scala:73:14]
output io_out_uop_fp_single, // @[issue-slot.scala:73:14]
output io_out_uop_xcpt_pf_if, // @[issue-slot.scala:73:14]
output io_out_uop_xcpt_ae_if, // @[issue-slot.scala:73:14]
output io_out_uop_xcpt_ma_if, // @[issue-slot.scala:73:14]
output io_out_uop_bp_debug_if, // @[issue-slot.scala:73:14]
output io_out_uop_bp_xcpt_if, // @[issue-slot.scala:73:14]
output [1:0] io_out_uop_debug_fsrc, // @[issue-slot.scala:73:14]
output [1:0] io_out_uop_debug_tsrc, // @[issue-slot.scala:73:14]
output [6:0] io_uop_uopc, // @[issue-slot.scala:73:14]
output [31:0] io_uop_inst, // @[issue-slot.scala:73:14]
output [31:0] io_uop_debug_inst, // @[issue-slot.scala:73:14]
output io_uop_is_rvc, // @[issue-slot.scala:73:14]
output [39:0] io_uop_debug_pc, // @[issue-slot.scala:73:14]
output [2:0] io_uop_iq_type, // @[issue-slot.scala:73:14]
output [9:0] io_uop_fu_code, // @[issue-slot.scala:73:14]
output [3:0] io_uop_ctrl_br_type, // @[issue-slot.scala:73:14]
output [1:0] io_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14]
output [2:0] io_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14]
output [2:0] io_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14]
output [4:0] io_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14]
output io_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14]
output [2:0] io_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14]
output io_uop_ctrl_is_load, // @[issue-slot.scala:73:14]
output io_uop_ctrl_is_sta, // @[issue-slot.scala:73:14]
output io_uop_ctrl_is_std, // @[issue-slot.scala:73:14]
output [1:0] io_uop_iw_state, // @[issue-slot.scala:73:14]
output io_uop_iw_p1_poisoned, // @[issue-slot.scala:73:14]
output io_uop_iw_p2_poisoned, // @[issue-slot.scala:73:14]
output io_uop_is_br, // @[issue-slot.scala:73:14]
output io_uop_is_jalr, // @[issue-slot.scala:73:14]
output io_uop_is_jal, // @[issue-slot.scala:73:14]
output io_uop_is_sfb, // @[issue-slot.scala:73:14]
output [15:0] io_uop_br_mask, // @[issue-slot.scala:73:14]
output [3:0] io_uop_br_tag, // @[issue-slot.scala:73:14]
output [4:0] io_uop_ftq_idx, // @[issue-slot.scala:73:14]
output io_uop_edge_inst, // @[issue-slot.scala:73:14]
output [5:0] io_uop_pc_lob, // @[issue-slot.scala:73:14]
output io_uop_taken, // @[issue-slot.scala:73:14]
output [19:0] io_uop_imm_packed, // @[issue-slot.scala:73:14]
output [11:0] io_uop_csr_addr, // @[issue-slot.scala:73:14]
output [6:0] io_uop_rob_idx, // @[issue-slot.scala:73:14]
output [4:0] io_uop_ldq_idx, // @[issue-slot.scala:73:14]
output [4:0] io_uop_stq_idx, // @[issue-slot.scala:73:14]
output [1:0] io_uop_rxq_idx, // @[issue-slot.scala:73:14]
output [6:0] io_uop_pdst, // @[issue-slot.scala:73:14]
output [6:0] io_uop_prs1, // @[issue-slot.scala:73:14]
output [6:0] io_uop_prs2, // @[issue-slot.scala:73:14]
output [6:0] io_uop_prs3, // @[issue-slot.scala:73:14]
output [4:0] io_uop_ppred, // @[issue-slot.scala:73:14]
output io_uop_prs1_busy, // @[issue-slot.scala:73:14]
output io_uop_prs2_busy, // @[issue-slot.scala:73:14]
output io_uop_prs3_busy, // @[issue-slot.scala:73:14]
output io_uop_ppred_busy, // @[issue-slot.scala:73:14]
output [6:0] io_uop_stale_pdst, // @[issue-slot.scala:73:14]
output io_uop_exception, // @[issue-slot.scala:73:14]
output [63:0] io_uop_exc_cause, // @[issue-slot.scala:73:14]
output io_uop_bypassable, // @[issue-slot.scala:73:14]
output [4:0] io_uop_mem_cmd, // @[issue-slot.scala:73:14]
output [1:0] io_uop_mem_size, // @[issue-slot.scala:73:14]
output io_uop_mem_signed, // @[issue-slot.scala:73:14]
output io_uop_is_fence, // @[issue-slot.scala:73:14]
output io_uop_is_fencei, // @[issue-slot.scala:73:14]
output io_uop_is_amo, // @[issue-slot.scala:73:14]
output io_uop_uses_ldq, // @[issue-slot.scala:73:14]
output io_uop_uses_stq, // @[issue-slot.scala:73:14]
output io_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14]
output io_uop_is_unique, // @[issue-slot.scala:73:14]
output io_uop_flush_on_commit, // @[issue-slot.scala:73:14]
output io_uop_ldst_is_rs1, // @[issue-slot.scala:73:14]
output [5:0] io_uop_ldst, // @[issue-slot.scala:73:14]
output [5:0] io_uop_lrs1, // @[issue-slot.scala:73:14]
output [5:0] io_uop_lrs2, // @[issue-slot.scala:73:14]
output [5:0] io_uop_lrs3, // @[issue-slot.scala:73:14]
output io_uop_ldst_val, // @[issue-slot.scala:73:14]
output [1:0] io_uop_dst_rtype, // @[issue-slot.scala:73:14]
output [1:0] io_uop_lrs1_rtype, // @[issue-slot.scala:73:14]
output [1:0] io_uop_lrs2_rtype, // @[issue-slot.scala:73:14]
output io_uop_frs3_en, // @[issue-slot.scala:73:14]
output io_uop_fp_val, // @[issue-slot.scala:73:14]
output io_uop_fp_single, // @[issue-slot.scala:73:14]
output io_uop_xcpt_pf_if, // @[issue-slot.scala:73:14]
output io_uop_xcpt_ae_if, // @[issue-slot.scala:73:14]
output io_uop_xcpt_ma_if, // @[issue-slot.scala:73:14]
output io_uop_bp_debug_if, // @[issue-slot.scala:73:14]
output io_uop_bp_xcpt_if, // @[issue-slot.scala:73:14]
output [1:0] io_uop_debug_fsrc, // @[issue-slot.scala:73:14]
output [1:0] io_uop_debug_tsrc, // @[issue-slot.scala:73:14]
output io_debug_p1, // @[issue-slot.scala:73:14]
output io_debug_p2, // @[issue-slot.scala:73:14]
output io_debug_p3, // @[issue-slot.scala:73:14]
output io_debug_ppred, // @[issue-slot.scala:73:14]
output [1:0] io_debug_state // @[issue-slot.scala:73:14]
);
wire io_grant_0 = io_grant; // @[issue-slot.scala:69:7]
wire [15:0] io_brupdate_b1_resolve_mask_0 = io_brupdate_b1_resolve_mask; // @[issue-slot.scala:69:7]
wire [15:0] io_brupdate_b1_mispredict_mask_0 = io_brupdate_b1_mispredict_mask; // @[issue-slot.scala:69:7]
wire [6:0] io_brupdate_b2_uop_uopc_0 = io_brupdate_b2_uop_uopc; // @[issue-slot.scala:69:7]
wire [31:0] io_brupdate_b2_uop_inst_0 = io_brupdate_b2_uop_inst; // @[issue-slot.scala:69:7]
wire [31:0] io_brupdate_b2_uop_debug_inst_0 = io_brupdate_b2_uop_debug_inst; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_rvc_0 = io_brupdate_b2_uop_is_rvc; // @[issue-slot.scala:69:7]
wire [39:0] io_brupdate_b2_uop_debug_pc_0 = io_brupdate_b2_uop_debug_pc; // @[issue-slot.scala:69:7]
wire [2:0] io_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type; // @[issue-slot.scala:69:7]
wire [9:0] io_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code; // @[issue-slot.scala:69:7]
wire [3:0] io_brupdate_b2_uop_ctrl_br_type_0 = io_brupdate_b2_uop_ctrl_br_type; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_uop_ctrl_op1_sel_0 = io_brupdate_b2_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7]
wire [2:0] io_brupdate_b2_uop_ctrl_op2_sel_0 = io_brupdate_b2_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7]
wire [2:0] io_brupdate_b2_uop_ctrl_imm_sel_0 = io_brupdate_b2_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7]
wire [4:0] io_brupdate_b2_uop_ctrl_op_fcn_0 = io_brupdate_b2_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_ctrl_fcn_dw_0 = io_brupdate_b2_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7]
wire [2:0] io_brupdate_b2_uop_ctrl_csr_cmd_0 = io_brupdate_b2_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_ctrl_is_load_0 = io_brupdate_b2_uop_ctrl_is_load; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_ctrl_is_sta_0 = io_brupdate_b2_uop_ctrl_is_sta; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_ctrl_is_std_0 = io_brupdate_b2_uop_ctrl_is_std; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_uop_iw_state_0 = io_brupdate_b2_uop_iw_state; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_iw_p1_poisoned_0 = io_brupdate_b2_uop_iw_p1_poisoned; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_iw_p2_poisoned_0 = io_brupdate_b2_uop_iw_p2_poisoned; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_br_0 = io_brupdate_b2_uop_is_br; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_jalr_0 = io_brupdate_b2_uop_is_jalr; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_jal_0 = io_brupdate_b2_uop_is_jal; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_sfb_0 = io_brupdate_b2_uop_is_sfb; // @[issue-slot.scala:69:7]
wire [15:0] io_brupdate_b2_uop_br_mask_0 = io_brupdate_b2_uop_br_mask; // @[issue-slot.scala:69:7]
wire [3:0] io_brupdate_b2_uop_br_tag_0 = io_brupdate_b2_uop_br_tag; // @[issue-slot.scala:69:7]
wire [4:0] io_brupdate_b2_uop_ftq_idx_0 = io_brupdate_b2_uop_ftq_idx; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_edge_inst_0 = io_brupdate_b2_uop_edge_inst; // @[issue-slot.scala:69:7]
wire [5:0] io_brupdate_b2_uop_pc_lob_0 = io_brupdate_b2_uop_pc_lob; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_taken_0 = io_brupdate_b2_uop_taken; // @[issue-slot.scala:69:7]
wire [19:0] io_brupdate_b2_uop_imm_packed_0 = io_brupdate_b2_uop_imm_packed; // @[issue-slot.scala:69:7]
wire [11:0] io_brupdate_b2_uop_csr_addr_0 = io_brupdate_b2_uop_csr_addr; // @[issue-slot.scala:69:7]
wire [6:0] io_brupdate_b2_uop_rob_idx_0 = io_brupdate_b2_uop_rob_idx; // @[issue-slot.scala:69:7]
wire [4:0] io_brupdate_b2_uop_ldq_idx_0 = io_brupdate_b2_uop_ldq_idx; // @[issue-slot.scala:69:7]
wire [4:0] io_brupdate_b2_uop_stq_idx_0 = io_brupdate_b2_uop_stq_idx; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_uop_rxq_idx_0 = io_brupdate_b2_uop_rxq_idx; // @[issue-slot.scala:69:7]
wire [6:0] io_brupdate_b2_uop_pdst_0 = io_brupdate_b2_uop_pdst; // @[issue-slot.scala:69:7]
wire [6:0] io_brupdate_b2_uop_prs1_0 = io_brupdate_b2_uop_prs1; // @[issue-slot.scala:69:7]
wire [6:0] io_brupdate_b2_uop_prs2_0 = io_brupdate_b2_uop_prs2; // @[issue-slot.scala:69:7]
wire [6:0] io_brupdate_b2_uop_prs3_0 = io_brupdate_b2_uop_prs3; // @[issue-slot.scala:69:7]
wire [4:0] io_brupdate_b2_uop_ppred_0 = io_brupdate_b2_uop_ppred; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_prs1_busy_0 = io_brupdate_b2_uop_prs1_busy; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_prs2_busy_0 = io_brupdate_b2_uop_prs2_busy; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_prs3_busy_0 = io_brupdate_b2_uop_prs3_busy; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_ppred_busy_0 = io_brupdate_b2_uop_ppred_busy; // @[issue-slot.scala:69:7]
wire [6:0] io_brupdate_b2_uop_stale_pdst_0 = io_brupdate_b2_uop_stale_pdst; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_exception_0 = io_brupdate_b2_uop_exception; // @[issue-slot.scala:69:7]
wire [63:0] io_brupdate_b2_uop_exc_cause_0 = io_brupdate_b2_uop_exc_cause; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_bypassable_0 = io_brupdate_b2_uop_bypassable; // @[issue-slot.scala:69:7]
wire [4:0] io_brupdate_b2_uop_mem_cmd_0 = io_brupdate_b2_uop_mem_cmd; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_uop_mem_size_0 = io_brupdate_b2_uop_mem_size; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_mem_signed_0 = io_brupdate_b2_uop_mem_signed; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_fence_0 = io_brupdate_b2_uop_is_fence; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_fencei_0 = io_brupdate_b2_uop_is_fencei; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_amo_0 = io_brupdate_b2_uop_is_amo; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_uses_ldq_0 = io_brupdate_b2_uop_uses_ldq; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_uses_stq_0 = io_brupdate_b2_uop_uses_stq; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_sys_pc2epc_0 = io_brupdate_b2_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_unique_0 = io_brupdate_b2_uop_is_unique; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_flush_on_commit_0 = io_brupdate_b2_uop_flush_on_commit; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_ldst_is_rs1_0 = io_brupdate_b2_uop_ldst_is_rs1; // @[issue-slot.scala:69:7]
wire [5:0] io_brupdate_b2_uop_ldst_0 = io_brupdate_b2_uop_ldst; // @[issue-slot.scala:69:7]
wire [5:0] io_brupdate_b2_uop_lrs1_0 = io_brupdate_b2_uop_lrs1; // @[issue-slot.scala:69:7]
wire [5:0] io_brupdate_b2_uop_lrs2_0 = io_brupdate_b2_uop_lrs2; // @[issue-slot.scala:69:7]
wire [5:0] io_brupdate_b2_uop_lrs3_0 = io_brupdate_b2_uop_lrs3; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_ldst_val_0 = io_brupdate_b2_uop_ldst_val; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_uop_dst_rtype_0 = io_brupdate_b2_uop_dst_rtype; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_uop_lrs1_rtype_0 = io_brupdate_b2_uop_lrs1_rtype; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_uop_lrs2_rtype_0 = io_brupdate_b2_uop_lrs2_rtype; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_frs3_en_0 = io_brupdate_b2_uop_frs3_en; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_fp_val_0 = io_brupdate_b2_uop_fp_val; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_fp_single_0 = io_brupdate_b2_uop_fp_single; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_xcpt_pf_if_0 = io_brupdate_b2_uop_xcpt_pf_if; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_xcpt_ae_if_0 = io_brupdate_b2_uop_xcpt_ae_if; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_xcpt_ma_if_0 = io_brupdate_b2_uop_xcpt_ma_if; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_bp_debug_if_0 = io_brupdate_b2_uop_bp_debug_if; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_bp_xcpt_if_0 = io_brupdate_b2_uop_bp_xcpt_if; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_uop_debug_fsrc_0 = io_brupdate_b2_uop_debug_fsrc; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_uop_debug_tsrc_0 = io_brupdate_b2_uop_debug_tsrc; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_valid_0 = io_brupdate_b2_valid; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_mispredict_0 = io_brupdate_b2_mispredict; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_taken_0 = io_brupdate_b2_taken; // @[issue-slot.scala:69:7]
wire [2:0] io_brupdate_b2_cfi_type_0 = io_brupdate_b2_cfi_type; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_pc_sel_0 = io_brupdate_b2_pc_sel; // @[issue-slot.scala:69:7]
wire [39:0] io_brupdate_b2_jalr_target_0 = io_brupdate_b2_jalr_target; // @[issue-slot.scala:69:7]
wire [20:0] io_brupdate_b2_target_offset_0 = io_brupdate_b2_target_offset; // @[issue-slot.scala:69:7]
wire io_kill_0 = io_kill; // @[issue-slot.scala:69:7]
wire io_clear_0 = io_clear; // @[issue-slot.scala:69:7]
wire io_ldspec_miss_0 = io_ldspec_miss; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_0_valid_0 = io_wakeup_ports_0_valid; // @[issue-slot.scala:69:7]
wire [6:0] io_wakeup_ports_0_bits_pdst_0 = io_wakeup_ports_0_bits_pdst; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_0_bits_poisoned_0 = io_wakeup_ports_0_bits_poisoned; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_1_valid_0 = io_wakeup_ports_1_valid; // @[issue-slot.scala:69:7]
wire [6:0] io_wakeup_ports_1_bits_pdst_0 = io_wakeup_ports_1_bits_pdst; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_1_bits_poisoned_0 = io_wakeup_ports_1_bits_poisoned; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_2_valid_0 = io_wakeup_ports_2_valid; // @[issue-slot.scala:69:7]
wire [6:0] io_wakeup_ports_2_bits_pdst_0 = io_wakeup_ports_2_bits_pdst; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_2_bits_poisoned_0 = io_wakeup_ports_2_bits_poisoned; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_3_valid_0 = io_wakeup_ports_3_valid; // @[issue-slot.scala:69:7]
wire [6:0] io_wakeup_ports_3_bits_pdst_0 = io_wakeup_ports_3_bits_pdst; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_3_bits_poisoned_0 = io_wakeup_ports_3_bits_poisoned; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_4_valid_0 = io_wakeup_ports_4_valid; // @[issue-slot.scala:69:7]
wire [6:0] io_wakeup_ports_4_bits_pdst_0 = io_wakeup_ports_4_bits_pdst; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_4_bits_poisoned_0 = io_wakeup_ports_4_bits_poisoned; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_5_valid_0 = io_wakeup_ports_5_valid; // @[issue-slot.scala:69:7]
wire [6:0] io_wakeup_ports_5_bits_pdst_0 = io_wakeup_ports_5_bits_pdst; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_5_bits_poisoned_0 = io_wakeup_ports_5_bits_poisoned; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_6_valid_0 = io_wakeup_ports_6_valid; // @[issue-slot.scala:69:7]
wire [6:0] io_wakeup_ports_6_bits_pdst_0 = io_wakeup_ports_6_bits_pdst; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_6_bits_poisoned_0 = io_wakeup_ports_6_bits_poisoned; // @[issue-slot.scala:69:7]
wire io_spec_ld_wakeup_0_valid_0 = io_spec_ld_wakeup_0_valid; // @[issue-slot.scala:69:7]
wire [6:0] io_spec_ld_wakeup_0_bits_0 = io_spec_ld_wakeup_0_bits; // @[issue-slot.scala:69:7]
wire io_in_uop_valid_0 = io_in_uop_valid; // @[issue-slot.scala:69:7]
wire [6:0] io_in_uop_bits_uopc_0 = io_in_uop_bits_uopc; // @[issue-slot.scala:69:7]
wire [31:0] io_in_uop_bits_inst_0 = io_in_uop_bits_inst; // @[issue-slot.scala:69:7]
wire [31:0] io_in_uop_bits_debug_inst_0 = io_in_uop_bits_debug_inst; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_rvc_0 = io_in_uop_bits_is_rvc; // @[issue-slot.scala:69:7]
wire [39:0] io_in_uop_bits_debug_pc_0 = io_in_uop_bits_debug_pc; // @[issue-slot.scala:69:7]
wire [2:0] io_in_uop_bits_iq_type_0 = io_in_uop_bits_iq_type; // @[issue-slot.scala:69:7]
wire [9:0] io_in_uop_bits_fu_code_0 = io_in_uop_bits_fu_code; // @[issue-slot.scala:69:7]
wire [3:0] io_in_uop_bits_ctrl_br_type_0 = io_in_uop_bits_ctrl_br_type; // @[issue-slot.scala:69:7]
wire [1:0] io_in_uop_bits_ctrl_op1_sel_0 = io_in_uop_bits_ctrl_op1_sel; // @[issue-slot.scala:69:7]
wire [2:0] io_in_uop_bits_ctrl_op2_sel_0 = io_in_uop_bits_ctrl_op2_sel; // @[issue-slot.scala:69:7]
wire [2:0] io_in_uop_bits_ctrl_imm_sel_0 = io_in_uop_bits_ctrl_imm_sel; // @[issue-slot.scala:69:7]
wire [4:0] io_in_uop_bits_ctrl_op_fcn_0 = io_in_uop_bits_ctrl_op_fcn; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_ctrl_fcn_dw_0 = io_in_uop_bits_ctrl_fcn_dw; // @[issue-slot.scala:69:7]
wire [2:0] io_in_uop_bits_ctrl_csr_cmd_0 = io_in_uop_bits_ctrl_csr_cmd; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_ctrl_is_load_0 = io_in_uop_bits_ctrl_is_load; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_ctrl_is_sta_0 = io_in_uop_bits_ctrl_is_sta; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_ctrl_is_std_0 = io_in_uop_bits_ctrl_is_std; // @[issue-slot.scala:69:7]
wire [1:0] io_in_uop_bits_iw_state_0 = io_in_uop_bits_iw_state; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_iw_p1_poisoned_0 = io_in_uop_bits_iw_p1_poisoned; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_iw_p2_poisoned_0 = io_in_uop_bits_iw_p2_poisoned; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_br_0 = io_in_uop_bits_is_br; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_jalr_0 = io_in_uop_bits_is_jalr; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_jal_0 = io_in_uop_bits_is_jal; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_sfb_0 = io_in_uop_bits_is_sfb; // @[issue-slot.scala:69:7]
wire [15:0] io_in_uop_bits_br_mask_0 = io_in_uop_bits_br_mask; // @[issue-slot.scala:69:7]
wire [3:0] io_in_uop_bits_br_tag_0 = io_in_uop_bits_br_tag; // @[issue-slot.scala:69:7]
wire [4:0] io_in_uop_bits_ftq_idx_0 = io_in_uop_bits_ftq_idx; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_edge_inst_0 = io_in_uop_bits_edge_inst; // @[issue-slot.scala:69:7]
wire [5:0] io_in_uop_bits_pc_lob_0 = io_in_uop_bits_pc_lob; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_taken_0 = io_in_uop_bits_taken; // @[issue-slot.scala:69:7]
wire [19:0] io_in_uop_bits_imm_packed_0 = io_in_uop_bits_imm_packed; // @[issue-slot.scala:69:7]
wire [11:0] io_in_uop_bits_csr_addr_0 = io_in_uop_bits_csr_addr; // @[issue-slot.scala:69:7]
wire [6:0] io_in_uop_bits_rob_idx_0 = io_in_uop_bits_rob_idx; // @[issue-slot.scala:69:7]
wire [4:0] io_in_uop_bits_ldq_idx_0 = io_in_uop_bits_ldq_idx; // @[issue-slot.scala:69:7]
wire [4:0] io_in_uop_bits_stq_idx_0 = io_in_uop_bits_stq_idx; // @[issue-slot.scala:69:7]
wire [1:0] io_in_uop_bits_rxq_idx_0 = io_in_uop_bits_rxq_idx; // @[issue-slot.scala:69:7]
wire [6:0] io_in_uop_bits_pdst_0 = io_in_uop_bits_pdst; // @[issue-slot.scala:69:7]
wire [6:0] io_in_uop_bits_prs1_0 = io_in_uop_bits_prs1; // @[issue-slot.scala:69:7]
wire [6:0] io_in_uop_bits_prs2_0 = io_in_uop_bits_prs2; // @[issue-slot.scala:69:7]
wire [6:0] io_in_uop_bits_prs3_0 = io_in_uop_bits_prs3; // @[issue-slot.scala:69:7]
wire [4:0] io_in_uop_bits_ppred_0 = io_in_uop_bits_ppred; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_prs1_busy_0 = io_in_uop_bits_prs1_busy; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_prs2_busy_0 = io_in_uop_bits_prs2_busy; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_prs3_busy_0 = io_in_uop_bits_prs3_busy; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_ppred_busy_0 = io_in_uop_bits_ppred_busy; // @[issue-slot.scala:69:7]
wire [6:0] io_in_uop_bits_stale_pdst_0 = io_in_uop_bits_stale_pdst; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_exception_0 = io_in_uop_bits_exception; // @[issue-slot.scala:69:7]
wire [63:0] io_in_uop_bits_exc_cause_0 = io_in_uop_bits_exc_cause; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_bypassable_0 = io_in_uop_bits_bypassable; // @[issue-slot.scala:69:7]
wire [4:0] io_in_uop_bits_mem_cmd_0 = io_in_uop_bits_mem_cmd; // @[issue-slot.scala:69:7]
wire [1:0] io_in_uop_bits_mem_size_0 = io_in_uop_bits_mem_size; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_mem_signed_0 = io_in_uop_bits_mem_signed; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_fence_0 = io_in_uop_bits_is_fence; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_fencei_0 = io_in_uop_bits_is_fencei; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_amo_0 = io_in_uop_bits_is_amo; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_uses_ldq_0 = io_in_uop_bits_uses_ldq; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_uses_stq_0 = io_in_uop_bits_uses_stq; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_sys_pc2epc_0 = io_in_uop_bits_is_sys_pc2epc; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_unique_0 = io_in_uop_bits_is_unique; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_flush_on_commit_0 = io_in_uop_bits_flush_on_commit; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_ldst_is_rs1_0 = io_in_uop_bits_ldst_is_rs1; // @[issue-slot.scala:69:7]
wire [5:0] io_in_uop_bits_ldst_0 = io_in_uop_bits_ldst; // @[issue-slot.scala:69:7]
wire [5:0] io_in_uop_bits_lrs1_0 = io_in_uop_bits_lrs1; // @[issue-slot.scala:69:7]
wire [5:0] io_in_uop_bits_lrs2_0 = io_in_uop_bits_lrs2; // @[issue-slot.scala:69:7]
wire [5:0] io_in_uop_bits_lrs3_0 = io_in_uop_bits_lrs3; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_ldst_val_0 = io_in_uop_bits_ldst_val; // @[issue-slot.scala:69:7]
wire [1:0] io_in_uop_bits_dst_rtype_0 = io_in_uop_bits_dst_rtype; // @[issue-slot.scala:69:7]
wire [1:0] io_in_uop_bits_lrs1_rtype_0 = io_in_uop_bits_lrs1_rtype; // @[issue-slot.scala:69:7]
wire [1:0] io_in_uop_bits_lrs2_rtype_0 = io_in_uop_bits_lrs2_rtype; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_frs3_en_0 = io_in_uop_bits_frs3_en; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_fp_val_0 = io_in_uop_bits_fp_val; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_fp_single_0 = io_in_uop_bits_fp_single; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_xcpt_pf_if_0 = io_in_uop_bits_xcpt_pf_if; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_xcpt_ae_if_0 = io_in_uop_bits_xcpt_ae_if; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_xcpt_ma_if_0 = io_in_uop_bits_xcpt_ma_if; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_bp_debug_if_0 = io_in_uop_bits_bp_debug_if; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_bp_xcpt_if_0 = io_in_uop_bits_bp_xcpt_if; // @[issue-slot.scala:69:7]
wire [1:0] io_in_uop_bits_debug_fsrc_0 = io_in_uop_bits_debug_fsrc; // @[issue-slot.scala:69:7]
wire [1:0] io_in_uop_bits_debug_tsrc_0 = io_in_uop_bits_debug_tsrc; // @[issue-slot.scala:69:7]
wire io_pred_wakeup_port_valid = 1'h0; // @[issue-slot.scala:69:7]
wire slot_uop_uop_is_rvc = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_ctrl_fcn_dw = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_ctrl_is_load = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_ctrl_is_sta = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_ctrl_is_std = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_iw_p1_poisoned = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_iw_p2_poisoned = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_is_br = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_is_jalr = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_is_jal = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_is_sfb = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_edge_inst = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_taken = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_prs1_busy = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_prs2_busy = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_prs3_busy = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_ppred_busy = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_exception = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_bypassable = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_mem_signed = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_is_fence = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_is_fencei = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_is_amo = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_uses_ldq = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_uses_stq = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_is_sys_pc2epc = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_is_unique = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_flush_on_commit = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_ldst_is_rs1 = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_ldst_val = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_frs3_en = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_fp_val = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_fp_single = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_xcpt_pf_if = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_xcpt_ae_if = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_xcpt_ma_if = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_bp_debug_if = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_bp_xcpt_if = 1'h0; // @[consts.scala:269:19]
wire slot_uop_cs_fcn_dw = 1'h0; // @[consts.scala:279:18]
wire slot_uop_cs_is_load = 1'h0; // @[consts.scala:279:18]
wire slot_uop_cs_is_sta = 1'h0; // @[consts.scala:279:18]
wire slot_uop_cs_is_std = 1'h0; // @[consts.scala:279:18]
wire [4:0] io_pred_wakeup_port_bits = 5'h0; // @[issue-slot.scala:69:7]
wire [4:0] slot_uop_uop_ctrl_op_fcn = 5'h0; // @[consts.scala:269:19]
wire [4:0] slot_uop_uop_ftq_idx = 5'h0; // @[consts.scala:269:19]
wire [4:0] slot_uop_uop_ldq_idx = 5'h0; // @[consts.scala:269:19]
wire [4:0] slot_uop_uop_stq_idx = 5'h0; // @[consts.scala:269:19]
wire [4:0] slot_uop_uop_ppred = 5'h0; // @[consts.scala:269:19]
wire [4:0] slot_uop_uop_mem_cmd = 5'h0; // @[consts.scala:269:19]
wire [4:0] slot_uop_cs_op_fcn = 5'h0; // @[consts.scala:279:18]
wire [2:0] slot_uop_uop_iq_type = 3'h0; // @[consts.scala:269:19]
wire [2:0] slot_uop_uop_ctrl_op2_sel = 3'h0; // @[consts.scala:269:19]
wire [2:0] slot_uop_uop_ctrl_imm_sel = 3'h0; // @[consts.scala:269:19]
wire [2:0] slot_uop_uop_ctrl_csr_cmd = 3'h0; // @[consts.scala:269:19]
wire [2:0] slot_uop_cs_op2_sel = 3'h0; // @[consts.scala:279:18]
wire [2:0] slot_uop_cs_imm_sel = 3'h0; // @[consts.scala:279:18]
wire [2:0] slot_uop_cs_csr_cmd = 3'h0; // @[consts.scala:279:18]
wire [1:0] slot_uop_uop_ctrl_op1_sel = 2'h0; // @[consts.scala:269:19]
wire [1:0] slot_uop_uop_iw_state = 2'h0; // @[consts.scala:269:19]
wire [1:0] slot_uop_uop_rxq_idx = 2'h0; // @[consts.scala:269:19]
wire [1:0] slot_uop_uop_mem_size = 2'h0; // @[consts.scala:269:19]
wire [1:0] slot_uop_uop_lrs1_rtype = 2'h0; // @[consts.scala:269:19]
wire [1:0] slot_uop_uop_lrs2_rtype = 2'h0; // @[consts.scala:269:19]
wire [1:0] slot_uop_uop_debug_fsrc = 2'h0; // @[consts.scala:269:19]
wire [1:0] slot_uop_uop_debug_tsrc = 2'h0; // @[consts.scala:269:19]
wire [1:0] slot_uop_cs_op1_sel = 2'h0; // @[consts.scala:279:18]
wire [3:0] slot_uop_uop_ctrl_br_type = 4'h0; // @[consts.scala:269:19]
wire [3:0] slot_uop_uop_br_tag = 4'h0; // @[consts.scala:269:19]
wire [3:0] slot_uop_cs_br_type = 4'h0; // @[consts.scala:279:18]
wire [1:0] slot_uop_uop_dst_rtype = 2'h2; // @[consts.scala:269:19]
wire [5:0] slot_uop_uop_pc_lob = 6'h0; // @[consts.scala:269:19]
wire [5:0] slot_uop_uop_ldst = 6'h0; // @[consts.scala:269:19]
wire [5:0] slot_uop_uop_lrs1 = 6'h0; // @[consts.scala:269:19]
wire [5:0] slot_uop_uop_lrs2 = 6'h0; // @[consts.scala:269:19]
wire [5:0] slot_uop_uop_lrs3 = 6'h0; // @[consts.scala:269:19]
wire [63:0] slot_uop_uop_exc_cause = 64'h0; // @[consts.scala:269:19]
wire [6:0] slot_uop_uop_uopc = 7'h0; // @[consts.scala:269:19]
wire [6:0] slot_uop_uop_rob_idx = 7'h0; // @[consts.scala:269:19]
wire [6:0] slot_uop_uop_pdst = 7'h0; // @[consts.scala:269:19]
wire [6:0] slot_uop_uop_prs1 = 7'h0; // @[consts.scala:269:19]
wire [6:0] slot_uop_uop_prs2 = 7'h0; // @[consts.scala:269:19]
wire [6:0] slot_uop_uop_prs3 = 7'h0; // @[consts.scala:269:19]
wire [6:0] slot_uop_uop_stale_pdst = 7'h0; // @[consts.scala:269:19]
wire [11:0] slot_uop_uop_csr_addr = 12'h0; // @[consts.scala:269:19]
wire [19:0] slot_uop_uop_imm_packed = 20'h0; // @[consts.scala:269:19]
wire [15:0] slot_uop_uop_br_mask = 16'h0; // @[consts.scala:269:19]
wire [9:0] slot_uop_uop_fu_code = 10'h0; // @[consts.scala:269:19]
wire [39:0] slot_uop_uop_debug_pc = 40'h0; // @[consts.scala:269:19]
wire [31:0] slot_uop_uop_inst = 32'h0; // @[consts.scala:269:19]
wire [31:0] slot_uop_uop_debug_inst = 32'h0; // @[consts.scala:269:19]
wire _io_valid_T; // @[issue-slot.scala:79:24]
wire _io_will_be_valid_T_4; // @[issue-slot.scala:262:32]
wire _io_request_hp_T; // @[issue-slot.scala:243:31]
wire [6:0] next_uopc; // @[issue-slot.scala:82:29]
wire [1:0] next_state; // @[issue-slot.scala:81:29]
wire [15:0] next_br_mask; // @[util.scala:85:25]
wire _io_out_uop_prs1_busy_T; // @[issue-slot.scala:270:28]
wire _io_out_uop_prs2_busy_T; // @[issue-slot.scala:271:28]
wire _io_out_uop_prs3_busy_T; // @[issue-slot.scala:272:28]
wire _io_out_uop_ppred_busy_T; // @[issue-slot.scala:273:28]
wire [1:0] next_lrs1_rtype; // @[issue-slot.scala:83:29]
wire [1:0] next_lrs2_rtype; // @[issue-slot.scala:84:29]
wire [3:0] io_out_uop_ctrl_br_type_0; // @[issue-slot.scala:69:7]
wire [1:0] io_out_uop_ctrl_op1_sel_0; // @[issue-slot.scala:69:7]
wire [2:0] io_out_uop_ctrl_op2_sel_0; // @[issue-slot.scala:69:7]
wire [2:0] io_out_uop_ctrl_imm_sel_0; // @[issue-slot.scala:69:7]
wire [4:0] io_out_uop_ctrl_op_fcn_0; // @[issue-slot.scala:69:7]
wire io_out_uop_ctrl_fcn_dw_0; // @[issue-slot.scala:69:7]
wire [2:0] io_out_uop_ctrl_csr_cmd_0; // @[issue-slot.scala:69:7]
wire io_out_uop_ctrl_is_load_0; // @[issue-slot.scala:69:7]
wire io_out_uop_ctrl_is_sta_0; // @[issue-slot.scala:69:7]
wire io_out_uop_ctrl_is_std_0; // @[issue-slot.scala:69:7]
wire [6:0] io_out_uop_uopc_0; // @[issue-slot.scala:69:7]
wire [31:0] io_out_uop_inst_0; // @[issue-slot.scala:69:7]
wire [31:0] io_out_uop_debug_inst_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_rvc_0; // @[issue-slot.scala:69:7]
wire [39:0] io_out_uop_debug_pc_0; // @[issue-slot.scala:69:7]
wire [2:0] io_out_uop_iq_type_0; // @[issue-slot.scala:69:7]
wire [9:0] io_out_uop_fu_code_0; // @[issue-slot.scala:69:7]
wire [1:0] io_out_uop_iw_state_0; // @[issue-slot.scala:69:7]
wire io_out_uop_iw_p1_poisoned_0; // @[issue-slot.scala:69:7]
wire io_out_uop_iw_p2_poisoned_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_br_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_jalr_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_jal_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_sfb_0; // @[issue-slot.scala:69:7]
wire [15:0] io_out_uop_br_mask_0; // @[issue-slot.scala:69:7]
wire [3:0] io_out_uop_br_tag_0; // @[issue-slot.scala:69:7]
wire [4:0] io_out_uop_ftq_idx_0; // @[issue-slot.scala:69:7]
wire io_out_uop_edge_inst_0; // @[issue-slot.scala:69:7]
wire [5:0] io_out_uop_pc_lob_0; // @[issue-slot.scala:69:7]
wire io_out_uop_taken_0; // @[issue-slot.scala:69:7]
wire [19:0] io_out_uop_imm_packed_0; // @[issue-slot.scala:69:7]
wire [11:0] io_out_uop_csr_addr_0; // @[issue-slot.scala:69:7]
wire [6:0] io_out_uop_rob_idx_0; // @[issue-slot.scala:69:7]
wire [4:0] io_out_uop_ldq_idx_0; // @[issue-slot.scala:69:7]
wire [4:0] io_out_uop_stq_idx_0; // @[issue-slot.scala:69:7]
wire [1:0] io_out_uop_rxq_idx_0; // @[issue-slot.scala:69:7]
wire [6:0] io_out_uop_pdst_0; // @[issue-slot.scala:69:7]
wire [6:0] io_out_uop_prs1_0; // @[issue-slot.scala:69:7]
wire [6:0] io_out_uop_prs2_0; // @[issue-slot.scala:69:7]
wire [6:0] io_out_uop_prs3_0; // @[issue-slot.scala:69:7]
wire [4:0] io_out_uop_ppred_0; // @[issue-slot.scala:69:7]
wire io_out_uop_prs1_busy_0; // @[issue-slot.scala:69:7]
wire io_out_uop_prs2_busy_0; // @[issue-slot.scala:69:7]
wire io_out_uop_prs3_busy_0; // @[issue-slot.scala:69:7]
wire io_out_uop_ppred_busy_0; // @[issue-slot.scala:69:7]
wire [6:0] io_out_uop_stale_pdst_0; // @[issue-slot.scala:69:7]
wire io_out_uop_exception_0; // @[issue-slot.scala:69:7]
wire [63:0] io_out_uop_exc_cause_0; // @[issue-slot.scala:69:7]
wire io_out_uop_bypassable_0; // @[issue-slot.scala:69:7]
wire [4:0] io_out_uop_mem_cmd_0; // @[issue-slot.scala:69:7]
wire [1:0] io_out_uop_mem_size_0; // @[issue-slot.scala:69:7]
wire io_out_uop_mem_signed_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_fence_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_fencei_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_amo_0; // @[issue-slot.scala:69:7]
wire io_out_uop_uses_ldq_0; // @[issue-slot.scala:69:7]
wire io_out_uop_uses_stq_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_sys_pc2epc_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_unique_0; // @[issue-slot.scala:69:7]
wire io_out_uop_flush_on_commit_0; // @[issue-slot.scala:69:7]
wire io_out_uop_ldst_is_rs1_0; // @[issue-slot.scala:69:7]
wire [5:0] io_out_uop_ldst_0; // @[issue-slot.scala:69:7]
wire [5:0] io_out_uop_lrs1_0; // @[issue-slot.scala:69:7]
wire [5:0] io_out_uop_lrs2_0; // @[issue-slot.scala:69:7]
wire [5:0] io_out_uop_lrs3_0; // @[issue-slot.scala:69:7]
wire io_out_uop_ldst_val_0; // @[issue-slot.scala:69:7]
wire [1:0] io_out_uop_dst_rtype_0; // @[issue-slot.scala:69:7]
wire [1:0] io_out_uop_lrs1_rtype_0; // @[issue-slot.scala:69:7]
wire [1:0] io_out_uop_lrs2_rtype_0; // @[issue-slot.scala:69:7]
wire io_out_uop_frs3_en_0; // @[issue-slot.scala:69:7]
wire io_out_uop_fp_val_0; // @[issue-slot.scala:69:7]
wire io_out_uop_fp_single_0; // @[issue-slot.scala:69:7]
wire io_out_uop_xcpt_pf_if_0; // @[issue-slot.scala:69:7]
wire io_out_uop_xcpt_ae_if_0; // @[issue-slot.scala:69:7]
wire io_out_uop_xcpt_ma_if_0; // @[issue-slot.scala:69:7]
wire io_out_uop_bp_debug_if_0; // @[issue-slot.scala:69:7]
wire io_out_uop_bp_xcpt_if_0; // @[issue-slot.scala:69:7]
wire [1:0] io_out_uop_debug_fsrc_0; // @[issue-slot.scala:69:7]
wire [1:0] io_out_uop_debug_tsrc_0; // @[issue-slot.scala:69:7]
wire [3:0] io_uop_ctrl_br_type_0; // @[issue-slot.scala:69:7]
wire [1:0] io_uop_ctrl_op1_sel_0; // @[issue-slot.scala:69:7]
wire [2:0] io_uop_ctrl_op2_sel_0; // @[issue-slot.scala:69:7]
wire [2:0] io_uop_ctrl_imm_sel_0; // @[issue-slot.scala:69:7]
wire [4:0] io_uop_ctrl_op_fcn_0; // @[issue-slot.scala:69:7]
wire io_uop_ctrl_fcn_dw_0; // @[issue-slot.scala:69:7]
wire [2:0] io_uop_ctrl_csr_cmd_0; // @[issue-slot.scala:69:7]
wire io_uop_ctrl_is_load_0; // @[issue-slot.scala:69:7]
wire io_uop_ctrl_is_sta_0; // @[issue-slot.scala:69:7]
wire io_uop_ctrl_is_std_0; // @[issue-slot.scala:69:7]
wire [6:0] io_uop_uopc_0; // @[issue-slot.scala:69:7]
wire [31:0] io_uop_inst_0; // @[issue-slot.scala:69:7]
wire [31:0] io_uop_debug_inst_0; // @[issue-slot.scala:69:7]
wire io_uop_is_rvc_0; // @[issue-slot.scala:69:7]
wire [39:0] io_uop_debug_pc_0; // @[issue-slot.scala:69:7]
wire [2:0] io_uop_iq_type_0; // @[issue-slot.scala:69:7]
wire [9:0] io_uop_fu_code_0; // @[issue-slot.scala:69:7]
wire [1:0] io_uop_iw_state_0; // @[issue-slot.scala:69:7]
wire io_uop_iw_p1_poisoned_0; // @[issue-slot.scala:69:7]
wire io_uop_iw_p2_poisoned_0; // @[issue-slot.scala:69:7]
wire io_uop_is_br_0; // @[issue-slot.scala:69:7]
wire io_uop_is_jalr_0; // @[issue-slot.scala:69:7]
wire io_uop_is_jal_0; // @[issue-slot.scala:69:7]
wire io_uop_is_sfb_0; // @[issue-slot.scala:69:7]
wire [15:0] io_uop_br_mask_0; // @[issue-slot.scala:69:7]
wire [3:0] io_uop_br_tag_0; // @[issue-slot.scala:69:7]
wire [4:0] io_uop_ftq_idx_0; // @[issue-slot.scala:69:7]
wire io_uop_edge_inst_0; // @[issue-slot.scala:69:7]
wire [5:0] io_uop_pc_lob_0; // @[issue-slot.scala:69:7]
wire io_uop_taken_0; // @[issue-slot.scala:69:7]
wire [19:0] io_uop_imm_packed_0; // @[issue-slot.scala:69:7]
wire [11:0] io_uop_csr_addr_0; // @[issue-slot.scala:69:7]
wire [6:0] io_uop_rob_idx_0; // @[issue-slot.scala:69:7]
wire [4:0] io_uop_ldq_idx_0; // @[issue-slot.scala:69:7]
wire [4:0] io_uop_stq_idx_0; // @[issue-slot.scala:69:7]
wire [1:0] io_uop_rxq_idx_0; // @[issue-slot.scala:69:7]
wire [6:0] io_uop_pdst_0; // @[issue-slot.scala:69:7]
wire [6:0] io_uop_prs1_0; // @[issue-slot.scala:69:7]
wire [6:0] io_uop_prs2_0; // @[issue-slot.scala:69:7]
wire [6:0] io_uop_prs3_0; // @[issue-slot.scala:69:7]
wire [4:0] io_uop_ppred_0; // @[issue-slot.scala:69:7]
wire io_uop_prs1_busy_0; // @[issue-slot.scala:69:7]
wire io_uop_prs2_busy_0; // @[issue-slot.scala:69:7]
wire io_uop_prs3_busy_0; // @[issue-slot.scala:69:7]
wire io_uop_ppred_busy_0; // @[issue-slot.scala:69:7]
wire [6:0] io_uop_stale_pdst_0; // @[issue-slot.scala:69:7]
wire io_uop_exception_0; // @[issue-slot.scala:69:7]
wire [63:0] io_uop_exc_cause_0; // @[issue-slot.scala:69:7]
wire io_uop_bypassable_0; // @[issue-slot.scala:69:7]
wire [4:0] io_uop_mem_cmd_0; // @[issue-slot.scala:69:7]
wire [1:0] io_uop_mem_size_0; // @[issue-slot.scala:69:7]
wire io_uop_mem_signed_0; // @[issue-slot.scala:69:7]
wire io_uop_is_fence_0; // @[issue-slot.scala:69:7]
wire io_uop_is_fencei_0; // @[issue-slot.scala:69:7]
wire io_uop_is_amo_0; // @[issue-slot.scala:69:7]
wire io_uop_uses_ldq_0; // @[issue-slot.scala:69:7]
wire io_uop_uses_stq_0; // @[issue-slot.scala:69:7]
wire io_uop_is_sys_pc2epc_0; // @[issue-slot.scala:69:7]
wire io_uop_is_unique_0; // @[issue-slot.scala:69:7]
wire io_uop_flush_on_commit_0; // @[issue-slot.scala:69:7]
wire io_uop_ldst_is_rs1_0; // @[issue-slot.scala:69:7]
wire [5:0] io_uop_ldst_0; // @[issue-slot.scala:69:7]
wire [5:0] io_uop_lrs1_0; // @[issue-slot.scala:69:7]
wire [5:0] io_uop_lrs2_0; // @[issue-slot.scala:69:7]
wire [5:0] io_uop_lrs3_0; // @[issue-slot.scala:69:7]
wire io_uop_ldst_val_0; // @[issue-slot.scala:69:7]
wire [1:0] io_uop_dst_rtype_0; // @[issue-slot.scala:69:7]
wire [1:0] io_uop_lrs1_rtype_0; // @[issue-slot.scala:69:7]
wire [1:0] io_uop_lrs2_rtype_0; // @[issue-slot.scala:69:7]
wire io_uop_frs3_en_0; // @[issue-slot.scala:69:7]
wire io_uop_fp_val_0; // @[issue-slot.scala:69:7]
wire io_uop_fp_single_0; // @[issue-slot.scala:69:7]
wire io_uop_xcpt_pf_if_0; // @[issue-slot.scala:69:7]
wire io_uop_xcpt_ae_if_0; // @[issue-slot.scala:69:7]
wire io_uop_xcpt_ma_if_0; // @[issue-slot.scala:69:7]
wire io_uop_bp_debug_if_0; // @[issue-slot.scala:69:7]
wire io_uop_bp_xcpt_if_0; // @[issue-slot.scala:69:7]
wire [1:0] io_uop_debug_fsrc_0; // @[issue-slot.scala:69:7]
wire [1:0] io_uop_debug_tsrc_0; // @[issue-slot.scala:69:7]
wire io_debug_p1_0; // @[issue-slot.scala:69:7]
wire io_debug_p2_0; // @[issue-slot.scala:69:7]
wire io_debug_p3_0; // @[issue-slot.scala:69:7]
wire io_debug_ppred_0; // @[issue-slot.scala:69:7]
wire [1:0] io_debug_state_0; // @[issue-slot.scala:69:7]
wire io_valid_0; // @[issue-slot.scala:69:7]
wire io_will_be_valid_0; // @[issue-slot.scala:69:7]
wire io_request_0; // @[issue-slot.scala:69:7]
wire io_request_hp_0; // @[issue-slot.scala:69:7]
assign io_out_uop_iw_state_0 = next_state; // @[issue-slot.scala:69:7, :81:29]
assign io_out_uop_uopc_0 = next_uopc; // @[issue-slot.scala:69:7, :82:29]
assign io_out_uop_lrs1_rtype_0 = next_lrs1_rtype; // @[issue-slot.scala:69:7, :83:29]
assign io_out_uop_lrs2_rtype_0 = next_lrs2_rtype; // @[issue-slot.scala:69:7, :84:29]
reg [1:0] state; // @[issue-slot.scala:86:22]
assign io_debug_state_0 = state; // @[issue-slot.scala:69:7, :86:22]
reg p1; // @[issue-slot.scala:87:22]
assign io_debug_p1_0 = p1; // @[issue-slot.scala:69:7, :87:22]
wire next_p1 = p1; // @[issue-slot.scala:87:22, :163:25]
reg p2; // @[issue-slot.scala:88:22]
assign io_debug_p2_0 = p2; // @[issue-slot.scala:69:7, :88:22]
wire next_p2 = p2; // @[issue-slot.scala:88:22, :164:25]
reg p3; // @[issue-slot.scala:89:22]
assign io_debug_p3_0 = p3; // @[issue-slot.scala:69:7, :89:22]
wire next_p3 = p3; // @[issue-slot.scala:89:22, :165:25]
reg ppred; // @[issue-slot.scala:90:22]
assign io_debug_ppred_0 = ppred; // @[issue-slot.scala:69:7, :90:22]
wire next_ppred = ppred; // @[issue-slot.scala:90:22, :166:28]
reg p1_poisoned; // @[issue-slot.scala:95:28]
assign io_out_uop_iw_p1_poisoned_0 = p1_poisoned; // @[issue-slot.scala:69:7, :95:28]
assign io_uop_iw_p1_poisoned_0 = p1_poisoned; // @[issue-slot.scala:69:7, :95:28]
reg p2_poisoned; // @[issue-slot.scala:96:28]
assign io_out_uop_iw_p2_poisoned_0 = p2_poisoned; // @[issue-slot.scala:69:7, :96:28]
assign io_uop_iw_p2_poisoned_0 = p2_poisoned; // @[issue-slot.scala:69:7, :96:28]
wire next_p1_poisoned = io_in_uop_valid_0 ? io_in_uop_bits_iw_p1_poisoned_0 : p1_poisoned; // @[issue-slot.scala:69:7, :95:28, :99:29]
wire next_p2_poisoned = io_in_uop_valid_0 ? io_in_uop_bits_iw_p2_poisoned_0 : p2_poisoned; // @[issue-slot.scala:69:7, :96:28, :100:29]
reg [6:0] slot_uop_uopc; // @[issue-slot.scala:102:25]
reg [31:0] slot_uop_inst; // @[issue-slot.scala:102:25]
assign io_out_uop_inst_0 = slot_uop_inst; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_inst_0 = slot_uop_inst; // @[issue-slot.scala:69:7, :102:25]
reg [31:0] slot_uop_debug_inst; // @[issue-slot.scala:102:25]
assign io_out_uop_debug_inst_0 = slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_debug_inst_0 = slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_is_rvc; // @[issue-slot.scala:102:25]
assign io_out_uop_is_rvc_0 = slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_rvc_0 = slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25]
reg [39:0] slot_uop_debug_pc; // @[issue-slot.scala:102:25]
assign io_out_uop_debug_pc_0 = slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_debug_pc_0 = slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25]
reg [2:0] slot_uop_iq_type; // @[issue-slot.scala:102:25]
assign io_out_uop_iq_type_0 = slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_iq_type_0 = slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25]
reg [9:0] slot_uop_fu_code; // @[issue-slot.scala:102:25]
assign io_out_uop_fu_code_0 = slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_fu_code_0 = slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25]
reg [3:0] slot_uop_ctrl_br_type; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_br_type_0 = slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_br_type_0 = slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25]
reg [1:0] slot_uop_ctrl_op1_sel; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_op1_sel_0 = slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_op1_sel_0 = slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25]
reg [2:0] slot_uop_ctrl_op2_sel; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_op2_sel_0 = slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_op2_sel_0 = slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25]
reg [2:0] slot_uop_ctrl_imm_sel; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_imm_sel_0 = slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_imm_sel_0 = slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25]
reg [4:0] slot_uop_ctrl_op_fcn; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_op_fcn_0 = slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_op_fcn_0 = slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_fcn_dw_0 = slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_fcn_dw_0 = slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25]
reg [2:0] slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_csr_cmd_0 = slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_csr_cmd_0 = slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_ctrl_is_load; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_is_load_0 = slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_is_load_0 = slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_ctrl_is_sta; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_is_sta_0 = slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_is_sta_0 = slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_ctrl_is_std; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_is_std_0 = slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_is_std_0 = slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25]
reg [1:0] slot_uop_iw_state; // @[issue-slot.scala:102:25]
assign io_uop_iw_state_0 = slot_uop_iw_state; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_iw_p1_poisoned; // @[issue-slot.scala:102:25]
reg slot_uop_iw_p2_poisoned; // @[issue-slot.scala:102:25]
reg slot_uop_is_br; // @[issue-slot.scala:102:25]
assign io_out_uop_is_br_0 = slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_br_0 = slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_is_jalr; // @[issue-slot.scala:102:25]
assign io_out_uop_is_jalr_0 = slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_jalr_0 = slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_is_jal; // @[issue-slot.scala:102:25]
assign io_out_uop_is_jal_0 = slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_jal_0 = slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_is_sfb; // @[issue-slot.scala:102:25]
assign io_out_uop_is_sfb_0 = slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_sfb_0 = slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25]
reg [15:0] slot_uop_br_mask; // @[issue-slot.scala:102:25]
assign io_uop_br_mask_0 = slot_uop_br_mask; // @[issue-slot.scala:69:7, :102:25]
reg [3:0] slot_uop_br_tag; // @[issue-slot.scala:102:25]
assign io_out_uop_br_tag_0 = slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_br_tag_0 = slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25]
reg [4:0] slot_uop_ftq_idx; // @[issue-slot.scala:102:25]
assign io_out_uop_ftq_idx_0 = slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ftq_idx_0 = slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_edge_inst; // @[issue-slot.scala:102:25]
assign io_out_uop_edge_inst_0 = slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_edge_inst_0 = slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25]
reg [5:0] slot_uop_pc_lob; // @[issue-slot.scala:102:25]
assign io_out_uop_pc_lob_0 = slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_pc_lob_0 = slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_taken; // @[issue-slot.scala:102:25]
assign io_out_uop_taken_0 = slot_uop_taken; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_taken_0 = slot_uop_taken; // @[issue-slot.scala:69:7, :102:25]
reg [19:0] slot_uop_imm_packed; // @[issue-slot.scala:102:25]
assign io_out_uop_imm_packed_0 = slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_imm_packed_0 = slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25]
reg [11:0] slot_uop_csr_addr; // @[issue-slot.scala:102:25]
assign io_out_uop_csr_addr_0 = slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_csr_addr_0 = slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25]
reg [6:0] slot_uop_rob_idx; // @[issue-slot.scala:102:25]
assign io_out_uop_rob_idx_0 = slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_rob_idx_0 = slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25]
reg [4:0] slot_uop_ldq_idx; // @[issue-slot.scala:102:25]
assign io_out_uop_ldq_idx_0 = slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ldq_idx_0 = slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25]
reg [4:0] slot_uop_stq_idx; // @[issue-slot.scala:102:25]
assign io_out_uop_stq_idx_0 = slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_stq_idx_0 = slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25]
reg [1:0] slot_uop_rxq_idx; // @[issue-slot.scala:102:25]
assign io_out_uop_rxq_idx_0 = slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_rxq_idx_0 = slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25]
reg [6:0] slot_uop_pdst; // @[issue-slot.scala:102:25]
assign io_out_uop_pdst_0 = slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_pdst_0 = slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25]
reg [6:0] slot_uop_prs1; // @[issue-slot.scala:102:25]
assign io_out_uop_prs1_0 = slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_prs1_0 = slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25]
reg [6:0] slot_uop_prs2; // @[issue-slot.scala:102:25]
assign io_out_uop_prs2_0 = slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_prs2_0 = slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25]
reg [6:0] slot_uop_prs3; // @[issue-slot.scala:102:25]
assign io_out_uop_prs3_0 = slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_prs3_0 = slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25]
reg [4:0] slot_uop_ppred; // @[issue-slot.scala:102:25]
assign io_out_uop_ppred_0 = slot_uop_ppred; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ppred_0 = slot_uop_ppred; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_prs1_busy; // @[issue-slot.scala:102:25]
assign io_uop_prs1_busy_0 = slot_uop_prs1_busy; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_prs2_busy; // @[issue-slot.scala:102:25]
assign io_uop_prs2_busy_0 = slot_uop_prs2_busy; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_prs3_busy; // @[issue-slot.scala:102:25]
assign io_uop_prs3_busy_0 = slot_uop_prs3_busy; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_ppred_busy; // @[issue-slot.scala:102:25]
assign io_uop_ppred_busy_0 = slot_uop_ppred_busy; // @[issue-slot.scala:69:7, :102:25]
reg [6:0] slot_uop_stale_pdst; // @[issue-slot.scala:102:25]
assign io_out_uop_stale_pdst_0 = slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_stale_pdst_0 = slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_exception; // @[issue-slot.scala:102:25]
assign io_out_uop_exception_0 = slot_uop_exception; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_exception_0 = slot_uop_exception; // @[issue-slot.scala:69:7, :102:25]
reg [63:0] slot_uop_exc_cause; // @[issue-slot.scala:102:25]
assign io_out_uop_exc_cause_0 = slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_exc_cause_0 = slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_bypassable; // @[issue-slot.scala:102:25]
assign io_out_uop_bypassable_0 = slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_bypassable_0 = slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25]
reg [4:0] slot_uop_mem_cmd; // @[issue-slot.scala:102:25]
assign io_out_uop_mem_cmd_0 = slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_mem_cmd_0 = slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25]
reg [1:0] slot_uop_mem_size; // @[issue-slot.scala:102:25]
assign io_out_uop_mem_size_0 = slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_mem_size_0 = slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_mem_signed; // @[issue-slot.scala:102:25]
assign io_out_uop_mem_signed_0 = slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_mem_signed_0 = slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_is_fence; // @[issue-slot.scala:102:25]
assign io_out_uop_is_fence_0 = slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_fence_0 = slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_is_fencei; // @[issue-slot.scala:102:25]
assign io_out_uop_is_fencei_0 = slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_fencei_0 = slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_is_amo; // @[issue-slot.scala:102:25]
assign io_out_uop_is_amo_0 = slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_amo_0 = slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_uses_ldq; // @[issue-slot.scala:102:25]
assign io_out_uop_uses_ldq_0 = slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_uses_ldq_0 = slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_uses_stq; // @[issue-slot.scala:102:25]
assign io_out_uop_uses_stq_0 = slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_uses_stq_0 = slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_is_sys_pc2epc; // @[issue-slot.scala:102:25]
assign io_out_uop_is_sys_pc2epc_0 = slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_sys_pc2epc_0 = slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_is_unique; // @[issue-slot.scala:102:25]
assign io_out_uop_is_unique_0 = slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_unique_0 = slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_flush_on_commit; // @[issue-slot.scala:102:25]
assign io_out_uop_flush_on_commit_0 = slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_flush_on_commit_0 = slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_ldst_is_rs1; // @[issue-slot.scala:102:25]
assign io_out_uop_ldst_is_rs1_0 = slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ldst_is_rs1_0 = slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25]
reg [5:0] slot_uop_ldst; // @[issue-slot.scala:102:25]
assign io_out_uop_ldst_0 = slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ldst_0 = slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25]
reg [5:0] slot_uop_lrs1; // @[issue-slot.scala:102:25]
assign io_out_uop_lrs1_0 = slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_lrs1_0 = slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25]
reg [5:0] slot_uop_lrs2; // @[issue-slot.scala:102:25]
assign io_out_uop_lrs2_0 = slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_lrs2_0 = slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25]
reg [5:0] slot_uop_lrs3; // @[issue-slot.scala:102:25]
assign io_out_uop_lrs3_0 = slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_lrs3_0 = slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_ldst_val; // @[issue-slot.scala:102:25]
assign io_out_uop_ldst_val_0 = slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ldst_val_0 = slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25]
reg [1:0] slot_uop_dst_rtype; // @[issue-slot.scala:102:25]
assign io_out_uop_dst_rtype_0 = slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_dst_rtype_0 = slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25]
reg [1:0] slot_uop_lrs1_rtype; // @[issue-slot.scala:102:25]
reg [1:0] slot_uop_lrs2_rtype; // @[issue-slot.scala:102:25]
reg slot_uop_frs3_en; // @[issue-slot.scala:102:25]
assign io_out_uop_frs3_en_0 = slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_frs3_en_0 = slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_fp_val; // @[issue-slot.scala:102:25]
assign io_out_uop_fp_val_0 = slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_fp_val_0 = slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_fp_single; // @[issue-slot.scala:102:25]
assign io_out_uop_fp_single_0 = slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_fp_single_0 = slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_xcpt_pf_if; // @[issue-slot.scala:102:25]
assign io_out_uop_xcpt_pf_if_0 = slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_xcpt_pf_if_0 = slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_xcpt_ae_if; // @[issue-slot.scala:102:25]
assign io_out_uop_xcpt_ae_if_0 = slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_xcpt_ae_if_0 = slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_xcpt_ma_if; // @[issue-slot.scala:102:25]
assign io_out_uop_xcpt_ma_if_0 = slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_xcpt_ma_if_0 = slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_bp_debug_if; // @[issue-slot.scala:102:25]
assign io_out_uop_bp_debug_if_0 = slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_bp_debug_if_0 = slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_bp_xcpt_if; // @[issue-slot.scala:102:25]
assign io_out_uop_bp_xcpt_if_0 = slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_bp_xcpt_if_0 = slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25]
reg [1:0] slot_uop_debug_fsrc; // @[issue-slot.scala:102:25]
assign io_out_uop_debug_fsrc_0 = slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_debug_fsrc_0 = slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25]
reg [1:0] slot_uop_debug_tsrc; // @[issue-slot.scala:102:25]
assign io_out_uop_debug_tsrc_0 = slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_debug_tsrc_0 = slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25]
wire [6:0] next_uop_uopc = io_in_uop_valid_0 ? io_in_uop_bits_uopc_0 : slot_uop_uopc; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [31:0] next_uop_inst = io_in_uop_valid_0 ? io_in_uop_bits_inst_0 : slot_uop_inst; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [31:0] next_uop_debug_inst = io_in_uop_valid_0 ? io_in_uop_bits_debug_inst_0 : slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_rvc = io_in_uop_valid_0 ? io_in_uop_bits_is_rvc_0 : slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [39:0] next_uop_debug_pc = io_in_uop_valid_0 ? io_in_uop_bits_debug_pc_0 : slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [2:0] next_uop_iq_type = io_in_uop_valid_0 ? io_in_uop_bits_iq_type_0 : slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [9:0] next_uop_fu_code = io_in_uop_valid_0 ? io_in_uop_bits_fu_code_0 : slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [3:0] next_uop_ctrl_br_type = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_br_type_0 : slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [1:0] next_uop_ctrl_op1_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op1_sel_0 : slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [2:0] next_uop_ctrl_op2_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op2_sel_0 : slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [2:0] next_uop_ctrl_imm_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_imm_sel_0 : slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [4:0] next_uop_ctrl_op_fcn = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op_fcn_0 : slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_ctrl_fcn_dw = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_fcn_dw_0 : slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [2:0] next_uop_ctrl_csr_cmd = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_csr_cmd_0 : slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_ctrl_is_load = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_load_0 : slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_ctrl_is_sta = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_sta_0 : slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_ctrl_is_std = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_std_0 : slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [1:0] next_uop_iw_state = io_in_uop_valid_0 ? io_in_uop_bits_iw_state_0 : slot_uop_iw_state; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_iw_p1_poisoned = io_in_uop_valid_0 ? io_in_uop_bits_iw_p1_poisoned_0 : slot_uop_iw_p1_poisoned; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_iw_p2_poisoned = io_in_uop_valid_0 ? io_in_uop_bits_iw_p2_poisoned_0 : slot_uop_iw_p2_poisoned; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_br = io_in_uop_valid_0 ? io_in_uop_bits_is_br_0 : slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_jalr = io_in_uop_valid_0 ? io_in_uop_bits_is_jalr_0 : slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_jal = io_in_uop_valid_0 ? io_in_uop_bits_is_jal_0 : slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_sfb = io_in_uop_valid_0 ? io_in_uop_bits_is_sfb_0 : slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [15:0] next_uop_br_mask = io_in_uop_valid_0 ? io_in_uop_bits_br_mask_0 : slot_uop_br_mask; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [3:0] next_uop_br_tag = io_in_uop_valid_0 ? io_in_uop_bits_br_tag_0 : slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [4:0] next_uop_ftq_idx = io_in_uop_valid_0 ? io_in_uop_bits_ftq_idx_0 : slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_edge_inst = io_in_uop_valid_0 ? io_in_uop_bits_edge_inst_0 : slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [5:0] next_uop_pc_lob = io_in_uop_valid_0 ? io_in_uop_bits_pc_lob_0 : slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_taken = io_in_uop_valid_0 ? io_in_uop_bits_taken_0 : slot_uop_taken; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [19:0] next_uop_imm_packed = io_in_uop_valid_0 ? io_in_uop_bits_imm_packed_0 : slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [11:0] next_uop_csr_addr = io_in_uop_valid_0 ? io_in_uop_bits_csr_addr_0 : slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [6:0] next_uop_rob_idx = io_in_uop_valid_0 ? io_in_uop_bits_rob_idx_0 : slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [4:0] next_uop_ldq_idx = io_in_uop_valid_0 ? io_in_uop_bits_ldq_idx_0 : slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [4:0] next_uop_stq_idx = io_in_uop_valid_0 ? io_in_uop_bits_stq_idx_0 : slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [1:0] next_uop_rxq_idx = io_in_uop_valid_0 ? io_in_uop_bits_rxq_idx_0 : slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [6:0] next_uop_pdst = io_in_uop_valid_0 ? io_in_uop_bits_pdst_0 : slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [6:0] next_uop_prs1 = io_in_uop_valid_0 ? io_in_uop_bits_prs1_0 : slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [6:0] next_uop_prs2 = io_in_uop_valid_0 ? io_in_uop_bits_prs2_0 : slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [6:0] next_uop_prs3 = io_in_uop_valid_0 ? io_in_uop_bits_prs3_0 : slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [4:0] next_uop_ppred = io_in_uop_valid_0 ? io_in_uop_bits_ppred_0 : slot_uop_ppred; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_prs1_busy = io_in_uop_valid_0 ? io_in_uop_bits_prs1_busy_0 : slot_uop_prs1_busy; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_prs2_busy = io_in_uop_valid_0 ? io_in_uop_bits_prs2_busy_0 : slot_uop_prs2_busy; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_prs3_busy = io_in_uop_valid_0 ? io_in_uop_bits_prs3_busy_0 : slot_uop_prs3_busy; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_ppred_busy = io_in_uop_valid_0 ? io_in_uop_bits_ppred_busy_0 : slot_uop_ppred_busy; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [6:0] next_uop_stale_pdst = io_in_uop_valid_0 ? io_in_uop_bits_stale_pdst_0 : slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_exception = io_in_uop_valid_0 ? io_in_uop_bits_exception_0 : slot_uop_exception; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [63:0] next_uop_exc_cause = io_in_uop_valid_0 ? io_in_uop_bits_exc_cause_0 : slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_bypassable = io_in_uop_valid_0 ? io_in_uop_bits_bypassable_0 : slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [4:0] next_uop_mem_cmd = io_in_uop_valid_0 ? io_in_uop_bits_mem_cmd_0 : slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [1:0] next_uop_mem_size = io_in_uop_valid_0 ? io_in_uop_bits_mem_size_0 : slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_mem_signed = io_in_uop_valid_0 ? io_in_uop_bits_mem_signed_0 : slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_fence = io_in_uop_valid_0 ? io_in_uop_bits_is_fence_0 : slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_fencei = io_in_uop_valid_0 ? io_in_uop_bits_is_fencei_0 : slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_amo = io_in_uop_valid_0 ? io_in_uop_bits_is_amo_0 : slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_uses_ldq = io_in_uop_valid_0 ? io_in_uop_bits_uses_ldq_0 : slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_uses_stq = io_in_uop_valid_0 ? io_in_uop_bits_uses_stq_0 : slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_sys_pc2epc = io_in_uop_valid_0 ? io_in_uop_bits_is_sys_pc2epc_0 : slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_unique = io_in_uop_valid_0 ? io_in_uop_bits_is_unique_0 : slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_flush_on_commit = io_in_uop_valid_0 ? io_in_uop_bits_flush_on_commit_0 : slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_ldst_is_rs1 = io_in_uop_valid_0 ? io_in_uop_bits_ldst_is_rs1_0 : slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [5:0] next_uop_ldst = io_in_uop_valid_0 ? io_in_uop_bits_ldst_0 : slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [5:0] next_uop_lrs1 = io_in_uop_valid_0 ? io_in_uop_bits_lrs1_0 : slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [5:0] next_uop_lrs2 = io_in_uop_valid_0 ? io_in_uop_bits_lrs2_0 : slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [5:0] next_uop_lrs3 = io_in_uop_valid_0 ? io_in_uop_bits_lrs3_0 : slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_ldst_val = io_in_uop_valid_0 ? io_in_uop_bits_ldst_val_0 : slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [1:0] next_uop_dst_rtype = io_in_uop_valid_0 ? io_in_uop_bits_dst_rtype_0 : slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [1:0] next_uop_lrs1_rtype = io_in_uop_valid_0 ? io_in_uop_bits_lrs1_rtype_0 : slot_uop_lrs1_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [1:0] next_uop_lrs2_rtype = io_in_uop_valid_0 ? io_in_uop_bits_lrs2_rtype_0 : slot_uop_lrs2_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_frs3_en = io_in_uop_valid_0 ? io_in_uop_bits_frs3_en_0 : slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_fp_val = io_in_uop_valid_0 ? io_in_uop_bits_fp_val_0 : slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_fp_single = io_in_uop_valid_0 ? io_in_uop_bits_fp_single_0 : slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_xcpt_pf_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_pf_if_0 : slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_xcpt_ae_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_ae_if_0 : slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_xcpt_ma_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_ma_if_0 : slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_bp_debug_if = io_in_uop_valid_0 ? io_in_uop_bits_bp_debug_if_0 : slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_bp_xcpt_if = io_in_uop_valid_0 ? io_in_uop_bits_bp_xcpt_if_0 : slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [1:0] next_uop_debug_fsrc = io_in_uop_valid_0 ? io_in_uop_bits_debug_fsrc_0 : slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [1:0] next_uop_debug_tsrc = io_in_uop_valid_0 ? io_in_uop_bits_debug_tsrc_0 : slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire _T_11 = state == 2'h2; // @[issue-slot.scala:86:22, :134:25]
wire _T_7 = io_grant_0 & state == 2'h1 | io_grant_0 & _T_11 & p1 & p2 & ppred; // @[issue-slot.scala:69:7, :86:22, :87:22, :88:22, :90:22, :133:{26,36,52}, :134:{15,25,40,46,52}]
wire _T_12 = io_grant_0 & _T_11; // @[issue-slot.scala:69:7, :134:25, :139:25]
wire _T_14 = io_ldspec_miss_0 & (p1_poisoned | p2_poisoned); // @[issue-slot.scala:69:7, :95:28, :96:28, :140:{28,44}]
wire _GEN = _T_12 & ~_T_14; // @[issue-slot.scala:126:14, :139:{25,51}, :140:{11,28,62}, :141:18]
wire _GEN_0 = io_kill_0 | _T_7; // @[issue-slot.scala:69:7, :102:25, :131:18, :133:52, :134:63, :139:51]
wire _GEN_1 = _GEN_0 | ~(_T_12 & ~_T_14 & p1); // @[issue-slot.scala:87:22, :102:25, :131:18, :134:63, :139:{25,51}, :140:{11,28,62}, :142:17, :143:23]
assign next_uopc = _GEN_1 ? slot_uop_uopc : 7'h3; // @[issue-slot.scala:82:29, :102:25, :131:18, :134:63, :139:51]
assign next_lrs1_rtype = _GEN_1 ? slot_uop_lrs1_rtype : 2'h2; // @[issue-slot.scala:83:29, :102:25, :131:18, :134:63, :139:51]
wire _GEN_2 = _GEN_0 | ~_GEN | p1; // @[issue-slot.scala:87:22, :102:25, :126:14, :131:18, :134:63, :139:51, :140:62, :141:18, :142:17]
assign next_lrs2_rtype = _GEN_2 ? slot_uop_lrs2_rtype : 2'h2; // @[issue-slot.scala:84:29, :102:25, :131:18, :134:63, :139:51, :140:62, :142:17]
wire _p1_T = ~io_in_uop_bits_prs1_busy_0; // @[issue-slot.scala:69:7, :169:11]
wire _p2_T = ~io_in_uop_bits_prs2_busy_0; // @[issue-slot.scala:69:7, :170:11]
wire _p3_T = ~io_in_uop_bits_prs3_busy_0; // @[issue-slot.scala:69:7, :171:11]
wire _ppred_T = ~io_in_uop_bits_ppred_busy_0; // @[issue-slot.scala:69:7, :172:14]
wire _T_22 = io_ldspec_miss_0 & next_p1_poisoned; // @[issue-slot.scala:69:7, :99:29, :175:24]
wire _T_27 = io_ldspec_miss_0 & next_p2_poisoned; // @[issue-slot.scala:69:7, :100:29, :179:24]
wire _T_85 = io_spec_ld_wakeup_0_valid_0 & io_spec_ld_wakeup_0_bits_0 == next_uop_prs1 & next_uop_lrs1_rtype == 2'h0; // @[issue-slot.scala:69:7, :103:21, :209:38, :210:{33,51}, :211:27]
wire _T_93 = io_spec_ld_wakeup_0_valid_0 & io_spec_ld_wakeup_0_bits_0 == next_uop_prs2 & next_uop_lrs2_rtype == 2'h0; // @[issue-slot.scala:69:7, :103:21, :216:38, :217:{33,51}, :218:27] |
Generate the Verilog code corresponding to the following Chisel files.
File Crossing.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.interrupts
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy.lazymodule._
import freechips.rocketchip.util.{SynchronizerShiftReg, AsyncResetReg}
@deprecated("IntXing does not ensure interrupt source is glitch free. Use IntSyncSource and IntSyncSink", "rocket-chip 1.2")
class IntXing(sync: Int = 3)(implicit p: Parameters) extends LazyModule
{
val intnode = IntAdapterNode()
lazy val module = new Impl
class Impl extends LazyModuleImp(this) {
(intnode.in zip intnode.out) foreach { case ((in, _), (out, _)) =>
out := SynchronizerShiftReg(in, sync)
}
}
}
object IntSyncCrossingSource
{
def apply(alreadyRegistered: Boolean = false)(implicit p: Parameters) =
{
val intsource = LazyModule(new IntSyncCrossingSource(alreadyRegistered))
intsource.node
}
}
class IntSyncCrossingSource(alreadyRegistered: Boolean = false)(implicit p: Parameters) extends LazyModule
{
val node = IntSyncSourceNode(alreadyRegistered)
lazy val module = if (alreadyRegistered) (new ImplRegistered) else (new Impl)
class Impl extends LazyModuleImp(this) {
def outSize = node.out.headOption.map(_._1.sync.size).getOrElse(0)
override def desiredName = s"IntSyncCrossingSource_n${node.out.size}x${outSize}"
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
out.sync := AsyncResetReg(Cat(in.reverse)).asBools
}
}
class ImplRegistered extends LazyRawModuleImp(this) {
def outSize = node.out.headOption.map(_._1.sync.size).getOrElse(0)
override def desiredName = s"IntSyncCrossingSource_n${node.out.size}x${outSize}_Registered"
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
out.sync := in
}
}
}
object IntSyncCrossingSink
{
@deprecated("IntSyncCrossingSink which used the `sync` parameter to determine crossing type is deprecated. Use IntSyncAsyncCrossingSink, IntSyncRationalCrossingSink, or IntSyncSyncCrossingSink instead for > 1, 1, and 0 sync values respectively", "rocket-chip 1.2")
def apply(sync: Int = 3)(implicit p: Parameters) =
{
val intsink = LazyModule(new IntSyncAsyncCrossingSink(sync))
intsink.node
}
}
class IntSyncAsyncCrossingSink(sync: Int = 3)(implicit p: Parameters) extends LazyModule
{
val node = IntSyncSinkNode(sync)
lazy val module = new Impl
class Impl extends LazyModuleImp(this) {
override def desiredName = s"IntSyncAsyncCrossingSink_n${node.out.size}x${node.out.head._1.size}"
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
out := SynchronizerShiftReg(in.sync, sync)
}
}
}
object IntSyncAsyncCrossingSink
{
def apply(sync: Int = 3)(implicit p: Parameters) =
{
val intsink = LazyModule(new IntSyncAsyncCrossingSink(sync))
intsink.node
}
}
class IntSyncSyncCrossingSink()(implicit p: Parameters) extends LazyModule
{
val node = IntSyncSinkNode(0)
lazy val module = new Impl
class Impl extends LazyRawModuleImp(this) {
def outSize = node.out.headOption.map(_._1.size).getOrElse(0)
override def desiredName = s"IntSyncSyncCrossingSink_n${node.out.size}x${outSize}"
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
out := in.sync
}
}
}
object IntSyncSyncCrossingSink
{
def apply()(implicit p: Parameters) =
{
val intsink = LazyModule(new IntSyncSyncCrossingSink())
intsink.node
}
}
class IntSyncRationalCrossingSink()(implicit p: Parameters) extends LazyModule
{
val node = IntSyncSinkNode(1)
lazy val module = new Impl
class Impl extends LazyModuleImp(this) {
def outSize = node.out.headOption.map(_._1.size).getOrElse(0)
override def desiredName = s"IntSyncRationalCrossingSink_n${node.out.size}x${outSize}"
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
out := RegNext(in.sync)
}
}
}
object IntSyncRationalCrossingSink
{
def apply()(implicit p: Parameters) =
{
val intsink = LazyModule(new IntSyncRationalCrossingSink())
intsink.node
}
}
| module IntSyncCrossingSource_n0x0_1( // @[Crossing.scala:41:9]
input clock, // @[Crossing.scala:41:9]
input reset // @[Crossing.scala:41:9]
);
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File package.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip
import chisel3._
import chisel3.util._
import scala.math.min
import scala.collection.{immutable, mutable}
package object util {
implicit class UnzippableOption[S, T](val x: Option[(S, T)]) {
def unzip = (x.map(_._1), x.map(_._2))
}
implicit class UIntIsOneOf(private val x: UInt) extends AnyVal {
def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR
def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq)
}
implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal {
/** Like Vec.apply(idx), but tolerates indices of mismatched width */
def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0))
}
implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal {
def apply(idx: UInt): T = {
if (x.size <= 1) {
x.head
} else if (!isPow2(x.size)) {
// For non-power-of-2 seqs, reflect elements to simplify decoder
(x ++ x.takeRight(x.size & -x.size)).toSeq(idx)
} else {
// Ignore MSBs of idx
val truncIdx =
if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx
else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0)
x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) }
}
}
def extract(idx: UInt): T = VecInit(x).extract(idx)
def asUInt: UInt = Cat(x.map(_.asUInt).reverse)
def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n)
def rotate(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n)
def rotateRight(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
}
// allow bitwise ops on Seq[Bool] just like UInt
implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal {
def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b }
def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b }
def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b }
def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x
def >> (n: Int): Seq[Bool] = x drop n
def unary_~ : Seq[Bool] = x.map(!_)
def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_)
def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_)
def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_)
private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B)
}
implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal {
def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable))
def getElements: Seq[Element] = x match {
case e: Element => Seq(e)
case a: Aggregate => a.getElements.flatMap(_.getElements)
}
}
/** Any Data subtype that has a Bool member named valid. */
type DataCanBeValid = Data { val valid: Bool }
implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal {
def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable)
}
implicit class StringToAugmentedString(private val x: String) extends AnyVal {
/** converts from camel case to to underscores, also removing all spaces */
def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") {
case (acc, c) if c.isUpper => acc + "_" + c.toLower
case (acc, c) if c == ' ' => acc
case (acc, c) => acc + c
}
/** converts spaces or underscores to hyphens, also lowering case */
def kebab: String = x.toLowerCase map {
case ' ' => '-'
case '_' => '-'
case c => c
}
def named(name: Option[String]): String = {
x + name.map("_named_" + _ ).getOrElse("_with_no_name")
}
def named(name: String): String = named(Some(name))
}
implicit def uintToBitPat(x: UInt): BitPat = BitPat(x)
implicit def wcToUInt(c: WideCounter): UInt = c.value
implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal {
def sextTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x)
}
def padTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(0.U((n - x.getWidth).W), x)
}
// shifts left by n if n >= 0, or right by -n if n < 0
def << (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << n(w-1, 0)
Mux(n(w), shifted >> (1 << w), shifted)
}
// shifts right by n if n >= 0, or left by -n if n < 0
def >> (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << (1 << w) >> n(w-1, 0)
Mux(n(w), shifted, shifted >> (1 << w))
}
// Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts
def extract(hi: Int, lo: Int): UInt = {
require(hi >= lo-1)
if (hi == lo-1) 0.U
else x(hi, lo)
}
// Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts
def extractOption(hi: Int, lo: Int): Option[UInt] = {
require(hi >= lo-1)
if (hi == lo-1) None
else Some(x(hi, lo))
}
// like x & ~y, but first truncate or zero-extend y to x's width
def andNot(y: UInt): UInt = x & ~(y | (x & 0.U))
def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n)
def rotateRight(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r))
}
}
def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n))
def rotateLeft(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r))
}
}
// compute (this + y) % n, given (this < n) and (y < n)
def addWrap(y: UInt, n: Int): UInt = {
val z = x +& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0)
}
// compute (this - y) % n, given (this < n) and (y < n)
def subWrap(y: UInt, n: Int): UInt = {
val z = x -& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0)
}
def grouped(width: Int): Seq[UInt] =
(0 until x.getWidth by width).map(base => x(base + width - 1, base))
def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds
def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x)
// Like >=, but prevents x-prop for ('x >= 0)
def >== (y: UInt): Bool = x >= y || y === 0.U
}
implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal {
def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y)
def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y)
}
implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal {
def toInt: Int = if (x) 1 else 0
// this one's snagged from scalaz
def option[T](z: => T): Option[T] = if (x) Some(z) else None
}
implicit class IntToAugmentedInt(private val x: Int) extends AnyVal {
// exact log2
def log2: Int = {
require(isPow2(x))
log2Ceil(x)
}
}
def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x)
def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x))
def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0)
def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1)
def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None
// Fill 1s from low bits to high bits
def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth)
def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0))
helper(1, x)(width-1, 0)
}
// Fill 1s form high bits to low bits
def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth)
def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x >> s))
helper(1, x)(width-1, 0)
}
def OptimizationBarrier[T <: Data](in: T): T = {
val barrier = Module(new Module {
val io = IO(new Bundle {
val x = Input(chiselTypeOf(in))
val y = Output(chiselTypeOf(in))
})
io.y := io.x
override def desiredName = s"OptimizationBarrier_${in.typeName}"
})
barrier.io.x := in
barrier.io.y
}
/** Similar to Seq.groupBy except this returns a Seq instead of a Map
* Useful for deterministic code generation
*/
def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = {
val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]]
for (x <- xs) {
val key = f(x)
val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A])
l += x
}
map.view.map({ case (k, vs) => k -> vs.toList }).toList
}
def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match {
case 1 => List.fill(n)(in.head)
case x if x == n => in
case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in")
}
// HeterogeneousBag moved to standalond diplomacy
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts)
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag
}
| module OptimizationBarrier_TLBEntryData_200( // @[package.scala:267:30]
input clock, // @[package.scala:267:30]
input reset, // @[package.scala:267:30]
input [19:0] io_x_ppn, // @[package.scala:268:18]
input io_x_u, // @[package.scala:268:18]
input io_x_g, // @[package.scala:268:18]
input io_x_ae_ptw, // @[package.scala:268:18]
input io_x_ae_final, // @[package.scala:268:18]
input io_x_ae_stage2, // @[package.scala:268:18]
input io_x_pf, // @[package.scala:268:18]
input io_x_gf, // @[package.scala:268:18]
input io_x_sw, // @[package.scala:268:18]
input io_x_sx, // @[package.scala:268:18]
input io_x_sr, // @[package.scala:268:18]
input io_x_hw, // @[package.scala:268:18]
input io_x_hx, // @[package.scala:268:18]
input io_x_hr, // @[package.scala:268:18]
input io_x_pw, // @[package.scala:268:18]
input io_x_px, // @[package.scala:268:18]
input io_x_pr, // @[package.scala:268:18]
input io_x_ppp, // @[package.scala:268:18]
input io_x_pal, // @[package.scala:268:18]
input io_x_paa, // @[package.scala:268:18]
input io_x_eff, // @[package.scala:268:18]
input io_x_c, // @[package.scala:268:18]
input io_x_fragmented_superpage, // @[package.scala:268:18]
output [19:0] io_y_ppn, // @[package.scala:268:18]
output io_y_u, // @[package.scala:268:18]
output io_y_ae_ptw, // @[package.scala:268:18]
output io_y_ae_final, // @[package.scala:268:18]
output io_y_ae_stage2, // @[package.scala:268:18]
output io_y_pf, // @[package.scala:268:18]
output io_y_gf, // @[package.scala:268:18]
output io_y_sw, // @[package.scala:268:18]
output io_y_sx, // @[package.scala:268:18]
output io_y_sr, // @[package.scala:268:18]
output io_y_hw, // @[package.scala:268:18]
output io_y_hx, // @[package.scala:268:18]
output io_y_hr, // @[package.scala:268:18]
output io_y_pw, // @[package.scala:268:18]
output io_y_px, // @[package.scala:268:18]
output io_y_pr, // @[package.scala:268:18]
output io_y_ppp, // @[package.scala:268:18]
output io_y_pal, // @[package.scala:268:18]
output io_y_paa, // @[package.scala:268:18]
output io_y_eff, // @[package.scala:268:18]
output io_y_c // @[package.scala:268:18]
);
wire [19:0] io_x_ppn_0 = io_x_ppn; // @[package.scala:267:30]
wire io_x_u_0 = io_x_u; // @[package.scala:267:30]
wire io_x_g_0 = io_x_g; // @[package.scala:267:30]
wire io_x_ae_ptw_0 = io_x_ae_ptw; // @[package.scala:267:30]
wire io_x_ae_final_0 = io_x_ae_final; // @[package.scala:267:30]
wire io_x_ae_stage2_0 = io_x_ae_stage2; // @[package.scala:267:30]
wire io_x_pf_0 = io_x_pf; // @[package.scala:267:30]
wire io_x_gf_0 = io_x_gf; // @[package.scala:267:30]
wire io_x_sw_0 = io_x_sw; // @[package.scala:267:30]
wire io_x_sx_0 = io_x_sx; // @[package.scala:267:30]
wire io_x_sr_0 = io_x_sr; // @[package.scala:267:30]
wire io_x_hw_0 = io_x_hw; // @[package.scala:267:30]
wire io_x_hx_0 = io_x_hx; // @[package.scala:267:30]
wire io_x_hr_0 = io_x_hr; // @[package.scala:267:30]
wire io_x_pw_0 = io_x_pw; // @[package.scala:267:30]
wire io_x_px_0 = io_x_px; // @[package.scala:267:30]
wire io_x_pr_0 = io_x_pr; // @[package.scala:267:30]
wire io_x_ppp_0 = io_x_ppp; // @[package.scala:267:30]
wire io_x_pal_0 = io_x_pal; // @[package.scala:267:30]
wire io_x_paa_0 = io_x_paa; // @[package.scala:267:30]
wire io_x_eff_0 = io_x_eff; // @[package.scala:267:30]
wire io_x_c_0 = io_x_c; // @[package.scala:267:30]
wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage; // @[package.scala:267:30]
wire [19:0] io_y_ppn_0 = io_x_ppn_0; // @[package.scala:267:30]
wire io_y_u_0 = io_x_u_0; // @[package.scala:267:30]
wire io_y_g = io_x_g_0; // @[package.scala:267:30]
wire io_y_ae_ptw_0 = io_x_ae_ptw_0; // @[package.scala:267:30]
wire io_y_ae_final_0 = io_x_ae_final_0; // @[package.scala:267:30]
wire io_y_ae_stage2_0 = io_x_ae_stage2_0; // @[package.scala:267:30]
wire io_y_pf_0 = io_x_pf_0; // @[package.scala:267:30]
wire io_y_gf_0 = io_x_gf_0; // @[package.scala:267:30]
wire io_y_sw_0 = io_x_sw_0; // @[package.scala:267:30]
wire io_y_sx_0 = io_x_sx_0; // @[package.scala:267:30]
wire io_y_sr_0 = io_x_sr_0; // @[package.scala:267:30]
wire io_y_hw_0 = io_x_hw_0; // @[package.scala:267:30]
wire io_y_hx_0 = io_x_hx_0; // @[package.scala:267:30]
wire io_y_hr_0 = io_x_hr_0; // @[package.scala:267:30]
wire io_y_pw_0 = io_x_pw_0; // @[package.scala:267:30]
wire io_y_px_0 = io_x_px_0; // @[package.scala:267:30]
wire io_y_pr_0 = io_x_pr_0; // @[package.scala:267:30]
wire io_y_ppp_0 = io_x_ppp_0; // @[package.scala:267:30]
wire io_y_pal_0 = io_x_pal_0; // @[package.scala:267:30]
wire io_y_paa_0 = io_x_paa_0; // @[package.scala:267:30]
wire io_y_eff_0 = io_x_eff_0; // @[package.scala:267:30]
wire io_y_c_0 = io_x_c_0; // @[package.scala:267:30]
wire io_y_fragmented_superpage = io_x_fragmented_superpage_0; // @[package.scala:267:30]
assign io_y_ppn = io_y_ppn_0; // @[package.scala:267:30]
assign io_y_u = io_y_u_0; // @[package.scala:267:30]
assign io_y_ae_ptw = io_y_ae_ptw_0; // @[package.scala:267:30]
assign io_y_ae_final = io_y_ae_final_0; // @[package.scala:267:30]
assign io_y_ae_stage2 = io_y_ae_stage2_0; // @[package.scala:267:30]
assign io_y_pf = io_y_pf_0; // @[package.scala:267:30]
assign io_y_gf = io_y_gf_0; // @[package.scala:267:30]
assign io_y_sw = io_y_sw_0; // @[package.scala:267:30]
assign io_y_sx = io_y_sx_0; // @[package.scala:267:30]
assign io_y_sr = io_y_sr_0; // @[package.scala:267:30]
assign io_y_hw = io_y_hw_0; // @[package.scala:267:30]
assign io_y_hx = io_y_hx_0; // @[package.scala:267:30]
assign io_y_hr = io_y_hr_0; // @[package.scala:267:30]
assign io_y_pw = io_y_pw_0; // @[package.scala:267:30]
assign io_y_px = io_y_px_0; // @[package.scala:267:30]
assign io_y_pr = io_y_pr_0; // @[package.scala:267:30]
assign io_y_ppp = io_y_ppp_0; // @[package.scala:267:30]
assign io_y_pal = io_y_pal_0; // @[package.scala:267:30]
assign io_y_paa = io_y_paa_0; // @[package.scala:267:30]
assign io_y_eff = io_y_eff_0; // @[package.scala:267:30]
assign io_y_c = io_y_c_0; // @[package.scala:267:30]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File Crossing.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.interrupts
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy.lazymodule._
import freechips.rocketchip.util.{SynchronizerShiftReg, AsyncResetReg}
@deprecated("IntXing does not ensure interrupt source is glitch free. Use IntSyncSource and IntSyncSink", "rocket-chip 1.2")
class IntXing(sync: Int = 3)(implicit p: Parameters) extends LazyModule
{
val intnode = IntAdapterNode()
lazy val module = new Impl
class Impl extends LazyModuleImp(this) {
(intnode.in zip intnode.out) foreach { case ((in, _), (out, _)) =>
out := SynchronizerShiftReg(in, sync)
}
}
}
object IntSyncCrossingSource
{
def apply(alreadyRegistered: Boolean = false)(implicit p: Parameters) =
{
val intsource = LazyModule(new IntSyncCrossingSource(alreadyRegistered))
intsource.node
}
}
class IntSyncCrossingSource(alreadyRegistered: Boolean = false)(implicit p: Parameters) extends LazyModule
{
val node = IntSyncSourceNode(alreadyRegistered)
lazy val module = if (alreadyRegistered) (new ImplRegistered) else (new Impl)
class Impl extends LazyModuleImp(this) {
def outSize = node.out.headOption.map(_._1.sync.size).getOrElse(0)
override def desiredName = s"IntSyncCrossingSource_n${node.out.size}x${outSize}"
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
out.sync := AsyncResetReg(Cat(in.reverse)).asBools
}
}
class ImplRegistered extends LazyRawModuleImp(this) {
def outSize = node.out.headOption.map(_._1.sync.size).getOrElse(0)
override def desiredName = s"IntSyncCrossingSource_n${node.out.size}x${outSize}_Registered"
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
out.sync := in
}
}
}
object IntSyncCrossingSink
{
@deprecated("IntSyncCrossingSink which used the `sync` parameter to determine crossing type is deprecated. Use IntSyncAsyncCrossingSink, IntSyncRationalCrossingSink, or IntSyncSyncCrossingSink instead for > 1, 1, and 0 sync values respectively", "rocket-chip 1.2")
def apply(sync: Int = 3)(implicit p: Parameters) =
{
val intsink = LazyModule(new IntSyncAsyncCrossingSink(sync))
intsink.node
}
}
class IntSyncAsyncCrossingSink(sync: Int = 3)(implicit p: Parameters) extends LazyModule
{
val node = IntSyncSinkNode(sync)
lazy val module = new Impl
class Impl extends LazyModuleImp(this) {
override def desiredName = s"IntSyncAsyncCrossingSink_n${node.out.size}x${node.out.head._1.size}"
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
out := SynchronizerShiftReg(in.sync, sync)
}
}
}
object IntSyncAsyncCrossingSink
{
def apply(sync: Int = 3)(implicit p: Parameters) =
{
val intsink = LazyModule(new IntSyncAsyncCrossingSink(sync))
intsink.node
}
}
class IntSyncSyncCrossingSink()(implicit p: Parameters) extends LazyModule
{
val node = IntSyncSinkNode(0)
lazy val module = new Impl
class Impl extends LazyRawModuleImp(this) {
def outSize = node.out.headOption.map(_._1.size).getOrElse(0)
override def desiredName = s"IntSyncSyncCrossingSink_n${node.out.size}x${outSize}"
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
out := in.sync
}
}
}
object IntSyncSyncCrossingSink
{
def apply()(implicit p: Parameters) =
{
val intsink = LazyModule(new IntSyncSyncCrossingSink())
intsink.node
}
}
class IntSyncRationalCrossingSink()(implicit p: Parameters) extends LazyModule
{
val node = IntSyncSinkNode(1)
lazy val module = new Impl
class Impl extends LazyModuleImp(this) {
def outSize = node.out.headOption.map(_._1.size).getOrElse(0)
override def desiredName = s"IntSyncRationalCrossingSink_n${node.out.size}x${outSize}"
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
out := RegNext(in.sync)
}
}
}
object IntSyncRationalCrossingSink
{
def apply()(implicit p: Parameters) =
{
val intsink = LazyModule(new IntSyncRationalCrossingSink())
intsink.node
}
}
File LazyModuleImp.scala:
package org.chipsalliance.diplomacy.lazymodule
import chisel3.{withClockAndReset, Module, RawModule, Reset, _}
import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo}
import firrtl.passes.InlineAnnotation
import org.chipsalliance.cde.config.Parameters
import org.chipsalliance.diplomacy.nodes.Dangle
import scala.collection.immutable.SortedMap
/** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]].
*
* This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy.
*/
sealed trait LazyModuleImpLike extends RawModule {
/** [[LazyModule]] that contains this instance. */
val wrapper: LazyModule
/** IOs that will be automatically "punched" for this instance. */
val auto: AutoBundle
/** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */
protected[diplomacy] val dangles: Seq[Dangle]
// [[wrapper.module]] had better not be accessed while LazyModules are still being built!
require(
LazyModule.scope.isEmpty,
s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}"
)
/** Set module name. Defaults to the containing LazyModule's desiredName. */
override def desiredName: String = wrapper.desiredName
suggestName(wrapper.suggestedName)
/** [[Parameters]] for chisel [[Module]]s. */
implicit val p: Parameters = wrapper.p
/** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and
* submodules.
*/
protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = {
// 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]],
// 2. return [[Dangle]]s from each module.
val childDangles = wrapper.children.reverse.flatMap { c =>
implicit val sourceInfo: SourceInfo = c.info
c.cloneProto.map { cp =>
// If the child is a clone, then recursively set cloneProto of its children as well
def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = {
require(bases.size == clones.size)
(bases.zip(clones)).map { case (l, r) =>
require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}")
l.cloneProto = Some(r)
assignCloneProtos(l.children, r.children)
}
}
assignCloneProtos(c.children, cp.children)
// Clone the child module as a record, and get its [[AutoBundle]]
val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName)
val clonedAuto = clone("auto").asInstanceOf[AutoBundle]
// Get the empty [[Dangle]]'s of the cloned child
val rawDangles = c.cloneDangles()
require(rawDangles.size == clonedAuto.elements.size)
// Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s
val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) }
dangles
}.getOrElse {
// For non-clones, instantiate the child module
val mod = try {
Module(c.module)
} catch {
case e: ChiselException => {
println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}")
throw e
}
}
mod.dangles
}
}
// Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]].
// This will result in a sequence of [[Dangle]] from these [[BaseNode]]s.
val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate())
// Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]]
val allDangles = nodeDangles ++ childDangles
// Group [[allDangles]] by their [[source]].
val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*)
// For each [[source]] set of [[Dangle]]s of size 2, ensure that these
// can be connected as a source-sink pair (have opposite flipped value).
// Make the connection and mark them as [[done]].
val done = Set() ++ pairing.values.filter(_.size == 2).map {
case Seq(a, b) =>
require(a.flipped != b.flipped)
// @todo <> in chisel3 makes directionless connection.
if (a.flipped) {
a.data <> b.data
} else {
b.data <> a.data
}
a.source
case _ => None
}
// Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module.
val forward = allDangles.filter(d => !done(d.source))
// Generate [[AutoBundle]] IO from [[forward]].
val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*))
// Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]]
val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) =>
if (d.flipped) {
d.data <> io
} else {
io <> d.data
}
d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name)
}
// Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]].
wrapper.inModuleBody.reverse.foreach {
_()
}
if (wrapper.shouldBeInlined) {
chisel3.experimental.annotate(new ChiselAnnotation {
def toFirrtl = InlineAnnotation(toNamed)
})
}
// Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]].
(auto, dangles)
}
}
/** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike {
/** Instantiate hardware of this `Module`. */
val (auto, dangles) = instantiate()
}
/** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike {
// These wires are the default clock+reset for all LazyModule children.
// It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the
// [[LazyRawModuleImp]] children.
// Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly.
/** drive clock explicitly. */
val childClock: Clock = Wire(Clock())
/** drive reset explicitly. */
val childReset: Reset = Wire(Reset())
// the default is that these are disabled
childClock := false.B.asClock
childReset := chisel3.DontCare
def provideImplicitClockToLazyChildren: Boolean = false
val (auto, dangles) =
if (provideImplicitClockToLazyChildren) {
withClockAndReset(childClock, childReset) { instantiate() }
} else {
instantiate()
}
}
File MixedNode.scala:
package org.chipsalliance.diplomacy.nodes
import chisel3.{Data, DontCare, Wire}
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.{Field, Parameters}
import org.chipsalliance.diplomacy.ValName
import org.chipsalliance.diplomacy.sourceLine
/** One side metadata of a [[Dangle]].
*
* Describes one side of an edge going into or out of a [[BaseNode]].
*
* @param serial
* the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to.
* @param index
* the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to.
*/
case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] {
import scala.math.Ordered.orderingToOrdered
def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that))
}
/** [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]]
* connects.
*
* [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] ,
* [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]].
*
* @param source
* the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within
* that [[BaseNode]].
* @param sink
* sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that
* [[BaseNode]].
* @param flipped
* flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to
* `danglesIn`.
* @param dataOpt
* actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module
*/
case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) {
def data = dataOpt.get
}
/** [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often
* derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually
* implement the protocol.
*/
case class Edges[EI, EO](in: Seq[EI], out: Seq[EO])
/** A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. */
case object MonitorsEnabled extends Field[Boolean](true)
/** When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented.
*
* For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but
* [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink
* nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the
* [[LazyModule]].
*/
case object RenderFlipped extends Field[Boolean](false)
/** The sealed node class in the package, all node are derived from it.
*
* @param inner
* Sink interface implementation.
* @param outer
* Source interface implementation.
* @param valName
* val name of this node.
* @tparam DI
* Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters
* describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected
* [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port
* parameters.
* @tparam UI
* Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing
* the protocol parameters of a sink. For an [[InwardNode]], it is determined itself.
* @tparam EI
* Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers
* specified for a sink according to protocol.
* @tparam BI
* Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface.
* It should extends from [[chisel3.Data]], which represents the real hardware.
* @tparam DO
* Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters
* describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself.
* @tparam UO
* Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing
* the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]].
* Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters.
* @tparam EO
* Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers
* specified for a source according to protocol.
* @tparam BO
* Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source
* interface. It should extends from [[chisel3.Data]], which represents the real hardware.
*
* @note
* Call Graph of [[MixedNode]]
* - line `─`: source is process by a function and generate pass to others
* - Arrow `→`: target of arrow is generated by source
*
* {{{
* (from the other node)
* ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐
* ↓ │
* (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │
* [[InwardNode.accPI]] │ │ │
* │ │ (based on protocol) │
* │ │ [[MixedNode.inner.edgeI]] │
* │ │ ↓ │
* ↓ │ │ │
* (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │
* [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │
* │ │ ↑ │ │ │
* │ │ │ [[OutwardNode.doParams]] │ │
* │ │ │ (from the other node) │ │
* │ │ │ │ │ │
* │ │ │ │ │ │
* │ │ │ └────────┬──────────────┤ │
* │ │ │ │ │ │
* │ │ │ │ (based on protocol) │
* │ │ │ │ [[MixedNode.inner.edgeI]] │
* │ │ │ │ │ │
* │ │ (from the other node) │ ↓ │
* │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │
* │ ↑ ↑ │ │ ↓ │
* │ │ │ │ │ [[MixedNode.in]] │
* │ │ │ │ ↓ ↑ │
* │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │
* ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │
* │ │ │ [[MixedNode.bundleOut]]─┐ │ │
* │ │ │ ↑ ↓ │ │
* │ │ │ │ [[MixedNode.out]] │ │
* │ ↓ ↓ │ ↑ │ │
* │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │
* │ │ (from the other node) ↑ │ │
* │ │ │ │ │ │
* │ │ │ [[MixedNode.outer.edgeO]] │ │
* │ │ │ (based on protocol) │ │
* │ │ │ │ │ │
* │ │ │ ┌────────────────────────────────────────┤ │ │
* │ │ │ │ │ │ │
* │ │ │ │ │ │ │
* │ │ │ │ │ │ │
* (immobilize after elaboration)│ ↓ │ │ │ │
* [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │
* ↑ (inward port from [[OutwardNode]]) │ │ │ │
* │ ┌─────────────────────────────────────────┤ │ │ │
* │ │ │ │ │ │
* │ │ │ │ │ │
* [[OutwardNode.accPO]] │ ↓ │ │ │
* (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │
* │ ↑ │ │
* │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │
* └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘
* }}}
*/
abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data](
val inner: InwardNodeImp[DI, UI, EI, BI],
val outer: OutwardNodeImp[DO, UO, EO, BO]
)(
implicit valName: ValName)
extends BaseNode
with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO]
with InwardNode[DI, UI, BI]
with OutwardNode[DO, UO, BO] {
// Generate a [[NodeHandle]] with inward and outward node are both this node.
val inward = this
val outward = this
/** Debug info of nodes binding. */
def bindingInfo: String = s"""$iBindingInfo
|$oBindingInfo
|""".stripMargin
/** Debug info of ports connecting. */
def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}]
|${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}]
|""".stripMargin
/** Debug info of parameters propagations. */
def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}]
|${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}]
|${diParams.size} downstream inward parameters: [${diParams.mkString(",")}]
|${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}]
|""".stripMargin
/** For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and
* [[MixedNode.iPortMapping]].
*
* Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward
* stars and outward stars.
*
* This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type
* of node.
*
* @param iKnown
* Number of known-size ([[BIND_ONCE]]) input bindings.
* @param oKnown
* Number of known-size ([[BIND_ONCE]]) output bindings.
* @param iStar
* Number of unknown size ([[BIND_STAR]]) input bindings.
* @param oStar
* Number of unknown size ([[BIND_STAR]]) output bindings.
* @return
* A Tuple of the resolved number of input and output connections.
*/
protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int)
/** Function to generate downward-flowing outward params from the downward-flowing input params and the current output
* ports.
*
* @param n
* The size of the output sequence to generate.
* @param p
* Sequence of downward-flowing input parameters of this node.
* @return
* A `n`-sized sequence of downward-flowing output edge parameters.
*/
protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO]
/** Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]].
*
* @param n
* Size of the output sequence.
* @param p
* Upward-flowing output edge parameters.
* @return
* A n-sized sequence of upward-flowing input edge parameters.
*/
protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI]
/** @return
* The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with
* [[BIND_STAR]].
*/
protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR)
/** @return
* The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of
* output bindings bound with [[BIND_STAR]].
*/
protected[diplomacy] lazy val sourceCard: Int =
iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR)
/** @return list of nodes involved in flex bindings with this node. */
protected[diplomacy] lazy val flexes: Seq[BaseNode] =
oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2)
/** Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin
* greedily taking up the remaining connections.
*
* @return
* A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return
* value is not relevant.
*/
protected[diplomacy] lazy val flexOffset: Int = {
/** Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex
* operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a
* connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of
* each node in the current set and decide whether they should be added to the set or not.
*
* @return
* the mapping of [[BaseNode]] indexed by their serial numbers.
*/
def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = {
if (visited.contains(v.serial) || !v.flexibleArityDirection) {
visited
} else {
v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum))
}
}
/** Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node.
*
* @example
* {{{
* a :*=* b :*=* c
* d :*=* b
* e :*=* f
* }}}
*
* `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)`
*/
val flexSet = DFS(this, Map()).values
/** The total number of :*= operators where we're on the left. */
val allSink = flexSet.map(_.sinkCard).sum
/** The total number of :=* operators used when we're on the right. */
val allSource = flexSet.map(_.sourceCard).sum
require(
allSink == 0 || allSource == 0,
s"The nodes ${flexSet.map(_.name)} which are inter-connected by :*=* have ${allSink} :*= operators and ${allSource} :=* operators connected to them, making it impossible to determine cardinality inference direction."
)
allSink - allSource
}
/** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. */
protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = {
if (flexibleArityDirection) flexOffset
else if (n.flexibleArityDirection) n.flexOffset
else 0
}
/** For a node which is connected between two nodes, select the one that will influence the direction of the flex
* resolution.
*/
protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = {
val dir = edgeArityDirection(n)
if (dir < 0) l
else if (dir > 0) r
else 1
}
/** Ensure that the same node is not visited twice in resolving `:*=`, etc operators. */
private var starCycleGuard = false
/** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star"
* connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also
* need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct
* edge parameters and later build up correct bundle connections.
*
* [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding
* operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort
* (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N :*= foo` or `N :*=* foo :*=
* bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo :*=* N`
*/
protected[diplomacy] lazy val (
oPortMapping: Seq[(Int, Int)],
iPortMapping: Seq[(Int, Int)],
oStar: Int,
iStar: Int
) = {
try {
if (starCycleGuard) throw StarCycleException()
starCycleGuard = true
// For a given node N...
// Number of foo :=* N
// + Number of bar :=* foo :*=* N
val oStars = oBindings.count { case (_, n, b, _, _) =>
b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) < 0)
}
// Number of N :*= foo
// + Number of N :*=* foo :*= bar
val iStars = iBindings.count { case (_, n, b, _, _) =>
b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) > 0)
}
// 1 for foo := N
// + bar.iStar for bar :*= foo :*=* N
// + foo.iStar for foo :*= N
// + 0 for foo :=* N
val oKnown = oBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, 0, n.iStar)
case BIND_QUERY => n.iStar
case BIND_STAR => 0
}
}.sum
// 1 for N := foo
// + bar.oStar for N :*=* foo :=* bar
// + foo.oStar for N :=* foo
// + 0 for N :*= foo
val iKnown = iBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, n.oStar, 0)
case BIND_QUERY => n.oStar
case BIND_STAR => 0
}
}.sum
// Resolve star depends on the node subclass to implement the algorithm for this.
val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars)
// Cumulative list of resolved outward binding range starting points
val oSum = oBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar)
case BIND_QUERY => n.iStar
case BIND_STAR => oStar
}
}.scanLeft(0)(_ + _)
// Cumulative list of resolved inward binding range starting points
val iSum = iBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar)
case BIND_QUERY => n.oStar
case BIND_STAR => iStar
}
}.scanLeft(0)(_ + _)
// Create ranges for each binding based on the running sums and return
// those along with resolved values for the star operations.
(oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar)
} catch {
case c: StarCycleException => throw c.copy(loop = context +: c.loop)
}
}
/** Sequence of inward ports.
*
* This should be called after all star bindings are resolved.
*
* Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding.
* `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this
* connection was made in the source code.
*/
protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] =
oBindings.flatMap { case (i, n, _, p, s) =>
// for each binding operator in this node, look at what it connects to
val (start, end) = n.iPortMapping(i)
(start until end).map { j => (j, n, p, s) }
}
/** Sequence of outward ports.
*
* This should be called after all star bindings are resolved.
*
* `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of
* outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection
* was made in the source code.
*/
protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] =
iBindings.flatMap { case (i, n, _, p, s) =>
// query this port index range of this node in the other side of node.
val (start, end) = n.oPortMapping(i)
(start until end).map { j => (j, n, p, s) }
}
// Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree
// Thus, there must exist an Eulerian path and the below algorithms terminate
@scala.annotation.tailrec
private def oTrace(
tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)
): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match {
case (i, n, p, s) => n.iForward(i) match {
case None => (i, n, p, s)
case Some((j, m)) => oTrace((j, m, p, s))
}
}
@scala.annotation.tailrec
private def iTrace(
tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)
): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match {
case (i, n, p, s) => n.oForward(i) match {
case None => (i, n, p, s)
case Some((j, m)) => iTrace((j, m, p, s))
}
}
/** Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved.
*
* Each Port is a tuple of:
* - Numeric index of this binding in the [[InwardNode]] on the other end.
* - [[InwardNode]] on the other end of this binding.
* - A view of [[Parameters]] where the binding occurred.
* - [[SourceInfo]] for source-level error reporting.
*/
lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace)
/** Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved.
*
* Each Port is a tuple of:
* - numeric index of this binding in [[OutwardNode]] on the other end.
* - [[OutwardNode]] on the other end of this binding.
* - a view of [[Parameters]] where the binding occurred.
* - [[SourceInfo]] for source-level error reporting.
*/
lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace)
private var oParamsCycleGuard = false
protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) }
protected[diplomacy] lazy val doParams: Seq[DO] = {
try {
if (oParamsCycleGuard) throw DownwardCycleException()
oParamsCycleGuard = true
val o = mapParamsD(oPorts.size, diParams)
require(
o.size == oPorts.size,
s"""Diplomacy has detected a problem with your graph:
|At the following node, the number of outward ports should equal the number of produced outward parameters.
|$context
|$connectedPortsInfo
|Downstreamed inward parameters: [${diParams.mkString(",")}]
|Produced outward parameters: [${o.mkString(",")}]
|""".stripMargin
)
o.map(outer.mixO(_, this))
} catch {
case c: DownwardCycleException => throw c.copy(loop = context +: c.loop)
}
}
private var iParamsCycleGuard = false
protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) }
protected[diplomacy] lazy val uiParams: Seq[UI] = {
try {
if (iParamsCycleGuard) throw UpwardCycleException()
iParamsCycleGuard = true
val i = mapParamsU(iPorts.size, uoParams)
require(
i.size == iPorts.size,
s"""Diplomacy has detected a problem with your graph:
|At the following node, the number of inward ports should equal the number of produced inward parameters.
|$context
|$connectedPortsInfo
|Upstreamed outward parameters: [${uoParams.mkString(",")}]
|Produced inward parameters: [${i.mkString(",")}]
|""".stripMargin
)
i.map(inner.mixI(_, this))
} catch {
case c: UpwardCycleException => throw c.copy(loop = context +: c.loop)
}
}
/** Outward edge parameters. */
protected[diplomacy] lazy val edgesOut: Seq[EO] =
(oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) }
/** Inward edge parameters. */
protected[diplomacy] lazy val edgesIn: Seq[EI] =
(iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) }
/** A tuple of the input edge parameters and output edge parameters for the edges bound to this node.
*
* If you need to access to the edges of a foreign Node, use this method (in/out create bundles).
*/
lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut)
/** Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. */
protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e =>
val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out")
// TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue,
// In the future, we should add an option to decide whether allowing unconnected in the LazyModule
x := DontCare
x
}
/** Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. */
protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e =>
val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In")
// TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue,
// In the future, we should add an option to decide whether allowing unconnected in the LazyModule
x := DontCare
x
}
private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) =>
Dangle(
source = HalfEdge(serial, i),
sink = HalfEdge(n.serial, j),
flipped = false,
name = wirePrefix + "out",
dataOpt = None
)
}
private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) =>
Dangle(
source = HalfEdge(n.serial, j),
sink = HalfEdge(serial, i),
flipped = true,
name = wirePrefix + "in",
dataOpt = None
)
}
/** Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. */
protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) =>
d.copy(dataOpt = Some(bundleOut(i)))
}
/** Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. */
protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) =>
d.copy(dataOpt = Some(bundleIn(i)))
}
private[diplomacy] var instantiated = false
/** Gather Bundle and edge parameters of outward ports.
*
* Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within
* [[LazyModuleImp]] code or after its instantiation has completed.
*/
def out: Seq[(BO, EO)] = {
require(
instantiated,
s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun"
)
bundleOut.zip(edgesOut)
}
/** Gather Bundle and edge parameters of inward ports.
*
* Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within
* [[LazyModuleImp]] code or after its instantiation has completed.
*/
def in: Seq[(BI, EI)] = {
require(
instantiated,
s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun"
)
bundleIn.zip(edgesIn)
}
/** Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires,
* instantiate monitors on all input ports if appropriate, and return all the dangles of this node.
*/
protected[diplomacy] def instantiate(): Seq[Dangle] = {
instantiated = true
if (!circuitIdentity) {
(iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) }
}
danglesOut ++ danglesIn
}
protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn
/** Connects the outward part of a node with the inward part of this node. */
protected[diplomacy] def bind(
h: OutwardNode[DI, UI, BI],
binding: NodeBinding
)(
implicit p: Parameters,
sourceInfo: SourceInfo
): Unit = {
val x = this // x := y
val y = h
sourceLine(sourceInfo, " at ", "")
val i = x.iPushed
val o = y.oPushed
y.oPush(
i,
x,
binding match {
case BIND_ONCE => BIND_ONCE
case BIND_FLEX => BIND_FLEX
case BIND_STAR => BIND_QUERY
case BIND_QUERY => BIND_STAR
}
)
x.iPush(o, y, binding)
}
/* Metadata for printing the node graph. */
def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) =>
val re = inner.render(e)
(n, re.copy(flipped = re.flipped != p(RenderFlipped)))
}
/** Metadata for printing the node graph */
def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) }
}
File AsyncResetReg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
/** This black-boxes an Async Reset
* (or Set)
* Register.
*
* Because Chisel doesn't support
* parameterized black boxes,
* we unfortunately have to
* instantiate a number of these.
*
* We also have to hard-code the set/
* reset behavior.
*
* Do not confuse an asynchronous
* reset signal with an asynchronously
* reset reg. You should still
* properly synchronize your reset
* deassertion.
*
* @param d Data input
* @param q Data Output
* @param clk Clock Input
* @param rst Reset Input
* @param en Write Enable Input
*
*/
class AsyncResetReg(resetValue: Int = 0) extends RawModule {
val io = IO(new Bundle {
val d = Input(Bool())
val q = Output(Bool())
val en = Input(Bool())
val clk = Input(Clock())
val rst = Input(Reset())
})
val reg = withClockAndReset(io.clk, io.rst.asAsyncReset)(RegInit(resetValue.U(1.W)))
when (io.en) {
reg := io.d
}
io.q := reg
}
class SimpleRegIO(val w: Int) extends Bundle{
val d = Input(UInt(w.W))
val q = Output(UInt(w.W))
val en = Input(Bool())
}
class AsyncResetRegVec(val w: Int, val init: BigInt) extends Module {
override def desiredName = s"AsyncResetRegVec_w${w}_i${init}"
val io = IO(new SimpleRegIO(w))
val reg = withReset(reset.asAsyncReset)(RegInit(init.U(w.W)))
when (io.en) {
reg := io.d
}
io.q := reg
}
object AsyncResetReg {
// Create Single Registers
def apply(d: Bool, clk: Clock, rst: Bool, init: Boolean, name: Option[String]): Bool = {
val reg = Module(new AsyncResetReg(if (init) 1 else 0))
reg.io.d := d
reg.io.clk := clk
reg.io.rst := rst
reg.io.en := true.B
name.foreach(reg.suggestName(_))
reg.io.q
}
def apply(d: Bool, clk: Clock, rst: Bool): Bool = apply(d, clk, rst, false, None)
def apply(d: Bool, clk: Clock, rst: Bool, name: String): Bool = apply(d, clk, rst, false, Some(name))
// Create Vectors of Registers
def apply(updateData: UInt, resetData: BigInt, enable: Bool, name: Option[String] = None): UInt = {
val w = updateData.getWidth max resetData.bitLength
val reg = Module(new AsyncResetRegVec(w, resetData))
name.foreach(reg.suggestName(_))
reg.io.d := updateData
reg.io.en := enable
reg.io.q
}
def apply(updateData: UInt, resetData: BigInt, enable: Bool, name: String): UInt = apply(updateData,
resetData, enable, Some(name))
def apply(updateData: UInt, resetData: BigInt): UInt = apply(updateData, resetData, enable = true.B)
def apply(updateData: UInt, resetData: BigInt, name: String): UInt = apply(updateData, resetData, enable = true.B, Some(name))
def apply(updateData: UInt, enable: Bool): UInt = apply(updateData, resetData=BigInt(0), enable)
def apply(updateData: UInt, enable: Bool, name: String): UInt = apply(updateData, resetData = BigInt(0), enable, Some(name))
def apply(updateData: UInt): UInt = apply(updateData, resetData = BigInt(0), enable = true.B)
def apply(updateData: UInt, name:String): UInt = apply(updateData, resetData = BigInt(0), enable = true.B, Some(name))
}
| module IntSyncCrossingSource_n1x1_33( // @[Crossing.scala:41:9]
input clock, // @[Crossing.scala:41:9]
input reset, // @[Crossing.scala:41:9]
input auto_in_0, // @[LazyModuleImp.scala:107:25]
output auto_out_sync_0 // @[LazyModuleImp.scala:107:25]
);
wire auto_in_0_0 = auto_in_0; // @[Crossing.scala:41:9]
wire nodeIn_0 = auto_in_0_0; // @[Crossing.scala:41:9]
wire nodeOut_sync_0; // @[MixedNode.scala:542:17]
wire auto_out_sync_0_0; // @[Crossing.scala:41:9]
assign auto_out_sync_0_0 = nodeOut_sync_0; // @[Crossing.scala:41:9]
AsyncResetRegVec_w1_i0_33 reg_0 ( // @[AsyncResetReg.scala:86:21]
.clock (clock),
.reset (reset),
.io_d (nodeIn_0), // @[MixedNode.scala:551:17]
.io_q (nodeOut_sync_0)
); // @[AsyncResetReg.scala:86:21]
assign auto_out_sync_0 = auto_out_sync_0_0; // @[Crossing.scala:41:9]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File ShiftReg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
// Similar to the Chisel ShiftRegister but allows the user to suggest a
// name to the registers that get instantiated, and
// to provide a reset value.
object ShiftRegInit {
def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T =
(0 until n).foldRight(in) {
case (i, next) => {
val r = RegNext(next, init)
name.foreach { na => r.suggestName(s"${na}_${i}") }
r
}
}
}
/** These wrap behavioral
* shift registers into specific modules to allow for
* backend flows to replace or constrain
* them properly when used for CDC synchronization,
* rather than buffering.
*
* The different types vary in their reset behavior:
* AsyncResetShiftReg -- Asynchronously reset register array
* A W(width) x D(depth) sized array is constructed from D instantiations of a
* W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg,
* but only used for timing applications
*/
abstract class AbstractPipelineReg(w: Int = 1) extends Module {
val io = IO(new Bundle {
val d = Input(UInt(w.W))
val q = Output(UInt(w.W))
}
)
}
object AbstractPipelineReg {
def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = {
val chain = Module(gen)
name.foreach{ chain.suggestName(_) }
chain.io.d := in.asUInt
chain.io.q.asTypeOf(in)
}
}
class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) {
require(depth > 0, "Depth must be greater than 0.")
override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}"
val chain = List.tabulate(depth) { i =>
Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}")
}
chain.last.io.d := io.d
chain.last.io.en := true.B
(chain.init zip chain.tail).foreach { case (sink, source) =>
sink.io.d := source.io.q
sink.io.en := true.B
}
io.q := chain.head.io.q
}
object AsyncResetShiftReg {
def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T =
AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name)
def apply [T <: Data](in: T, depth: Int, name: Option[String]): T =
apply(in, depth, 0, name)
def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T =
apply(in, depth, init.litValue.toInt, name)
def apply [T <: Data](in: T, depth: Int, init: T): T =
apply (in, depth, init.litValue.toInt, None)
}
File SynchronizerReg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util.{RegEnable, Cat}
/** These wrap behavioral
* shift and next registers into specific modules to allow for
* backend flows to replace or constrain
* them properly when used for CDC synchronization,
* rather than buffering.
*
*
* These are built up of *ResetSynchronizerPrimitiveShiftReg,
* intended to be replaced by the integrator's metastable flops chains or replaced
* at this level if they have a multi-bit wide synchronizer primitive.
* The different types vary in their reset behavior:
* NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin
* AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep
* 1-bit-wide shift registers.
* SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg
*
* [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference.
*
* ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross
* Clock Domains.
*/
object SynchronizerResetType extends Enumeration {
val NonSync, Inferred, Sync, Async = Value
}
// Note: this should not be used directly.
// Use the companion object to generate this with the correct reset type mixin.
private class SynchronizerPrimitiveShiftReg(
sync: Int,
init: Boolean,
resetType: SynchronizerResetType.Value)
extends AbstractPipelineReg(1) {
val initInt = if (init) 1 else 0
val initPostfix = resetType match {
case SynchronizerResetType.NonSync => ""
case _ => s"_i${initInt}"
}
override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}"
val chain = List.tabulate(sync) { i =>
val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B)
reg.suggestName(s"sync_$i")
}
chain.last := io.d.asBool
(chain.init zip chain.tail).foreach { case (sink, source) =>
sink := source
}
io.q := chain.head.asUInt
}
private object SynchronizerPrimitiveShiftReg {
def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = {
val gen: () => SynchronizerPrimitiveShiftReg = resetType match {
case SynchronizerResetType.NonSync =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType)
case SynchronizerResetType.Async =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset
case SynchronizerResetType.Sync =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset
case SynchronizerResetType.Inferred =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType)
}
AbstractPipelineReg(gen(), in)
}
}
// Note: This module may end up with a non-AsyncReset type reset.
// But the Primitives within will always have AsyncReset type.
class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int)
extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
withReset(reset.asAsyncReset){
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async)
}
}
io.q := Cat(output.reverse)
}
object AsyncResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
// Note: This module may end up with a non-Bool type reset.
// But the Primitives within will always have Bool reset type.
@deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2")
class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
withReset(reset.asBool){
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync)
}
}
io.q := Cat(output.reverse)
}
object SyncResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred)
}
io.q := Cat(output.reverse)
}
object ResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}"
val output = Seq.tabulate(w) { i =>
SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync)
}
io.q := Cat(output.reverse)
}
object SynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T =
if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, None)
def apply [T <: Data](in: T): T =
apply (in, 3, None)
}
class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module {
override def desiredName = s"ClockCrossingReg_w${w}"
val io = IO(new Bundle{
val d = Input(UInt(w.W))
val q = Output(UInt(w.W))
val en = Input(Bool())
})
val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en)
io.q := cdc_reg
}
object ClockCrossingReg {
def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = {
val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit))
name.foreach{ cdc_reg.suggestName(_) }
cdc_reg.io.d := in.asUInt
cdc_reg.io.en := en
cdc_reg.io.q.asTypeOf(in)
}
}
| module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_116( // @[SynchronizerReg.scala:68:19]
input clock, // @[SynchronizerReg.scala:68:19]
input reset, // @[SynchronizerReg.scala:68:19]
output io_q // @[ShiftReg.scala:36:14]
);
wire io_d = 1'h1; // @[SynchronizerReg.scala:54:22, :68:19]
wire _sync_2_T = 1'h1; // @[SynchronizerReg.scala:54:22, :68:19]
wire io_q_0; // @[SynchronizerReg.scala:68:19]
reg sync_0; // @[SynchronizerReg.scala:51:87]
assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19]
reg sync_1; // @[SynchronizerReg.scala:51:87]
reg sync_2; // @[SynchronizerReg.scala:51:87]
always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19]
if (reset) begin // @[SynchronizerReg.scala:68:19]
sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87]
sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87]
sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87]
end
else begin // @[SynchronizerReg.scala:68:19]
sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87]
sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87]
sync_2 <= 1'h1; // @[SynchronizerReg.scala:51:87, :54:22, :68:19]
end
always @(posedge, posedge) |
Generate the Verilog code corresponding to the following Chisel files.
File fNFromRecFN.scala:
/*============================================================================
This Chisel source file is part of a pre-release version of the HardFloat IEEE
Floating-Point Arithmetic Package, by John R. Hauser (with some contributions
from Yunsup Lee and Andrew Waterman, mainly concerning testing).
Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
University of California. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
package hardfloat
import chisel3._
import chisel3.util._
object fNFromRecFN
{
def apply(expWidth: Int, sigWidth: Int, in: Bits) =
{
val minNormExp = (BigInt(1)<<(expWidth - 1)) + 2
val rawIn = rawFloatFromRecFN(expWidth, sigWidth, in)
val isSubnormal = rawIn.sExp < minNormExp.S
val denormShiftDist = 1.U - rawIn.sExp(log2Up(sigWidth - 1) - 1, 0)
val denormFract = ((rawIn.sig>>1)>>denormShiftDist)(sigWidth - 2, 0)
val expOut =
Mux(isSubnormal,
0.U,
rawIn.sExp(expWidth - 1, 0) -
((BigInt(1)<<(expWidth - 1)) + 1).U
) | Fill(expWidth, rawIn.isNaN || rawIn.isInf)
val fractOut =
Mux(isSubnormal,
denormFract,
Mux(rawIn.isInf, 0.U, rawIn.sig(sigWidth - 2, 0))
)
Cat(rawIn.sign, expOut, fractOut)
}
}
File execution-unit.scala:
//******************************************************************************
// Copyright (c) 2013 - 2018, The Regents of the University of California (Regents).
// All Rights Reserved. See LICENSE and LICENSE.SiFive for license details.
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
// Execution Units
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
//
// The issue window schedules micro-ops onto a specific execution pipeline
// A given execution pipeline may contain multiple functional units; one or more
// read ports, and one or more writeports.
package boom.v3.exu
import scala.collection.mutable.{ArrayBuffer}
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.{Parameters}
import freechips.rocketchip.rocket.{BP}
import freechips.rocketchip.tile
import FUConstants._
import boom.v3.common._
import boom.v3.ifu.{GetPCFromFtqIO}
import boom.v3.util.{ImmGen, IsKilledByBranch, BranchKillableQueue, BoomCoreStringPrefix}
/**
* Response from Execution Unit. Bundles a MicroOp with data
*
* @param dataWidth width of the data coming from the execution unit
*/
class ExeUnitResp(val dataWidth: Int)(implicit p: Parameters) extends BoomBundle
with HasBoomUOP
{
val data = Bits(dataWidth.W)
val predicated = Bool() // Was this predicated off?
val fflags = new ValidIO(new FFlagsResp) // write fflags to ROB // TODO: Do this better
}
/**
* Floating Point flag response
*/
class FFlagsResp(implicit p: Parameters) extends BoomBundle
{
val uop = new MicroOp()
val flags = Bits(tile.FPConstants.FLAGS_SZ.W)
}
/**
* Abstract Top level Execution Unit that wraps lower level functional units to make a
* multi function execution unit.
*
* @param readsIrf does this exe unit need a integer regfile port
* @param writesIrf does this exe unit need a integer regfile port
* @param readsFrf does this exe unit need a integer regfile port
* @param writesFrf does this exe unit need a integer regfile port
* @param writesLlIrf does this exe unit need a integer regfile port
* @param writesLlFrf does this exe unit need a integer regfile port
* @param numBypassStages number of bypass ports for the exe unit
* @param dataWidth width of the data coming out of the exe unit
* @param bypassable is the exe unit able to be bypassed
* @param hasMem does the exe unit have a MemAddrCalcUnit
* @param hasCSR does the exe unit write to the CSRFile
* @param hasBrUnit does the exe unit have a branch unit
* @param hasAlu does the exe unit have a alu
* @param hasFpu does the exe unit have a fpu
* @param hasMul does the exe unit have a multiplier
* @param hasDiv does the exe unit have a divider
* @param hasFdiv does the exe unit have a FP divider
* @param hasIfpu does the exe unit have a int to FP unit
* @param hasFpiu does the exe unit have a FP to int unit
*/
abstract class ExecutionUnit(
val readsIrf : Boolean = false,
val writesIrf : Boolean = false,
val readsFrf : Boolean = false,
val writesFrf : Boolean = false,
val writesLlIrf : Boolean = false,
val writesLlFrf : Boolean = false,
val numBypassStages : Int,
val dataWidth : Int,
val bypassable : Boolean = false, // TODO make override def for code clarity
val alwaysBypassable : Boolean = false,
val hasMem : Boolean = false,
val hasCSR : Boolean = false,
val hasJmpUnit : Boolean = false,
val hasAlu : Boolean = false,
val hasFpu : Boolean = false,
val hasMul : Boolean = false,
val hasDiv : Boolean = false,
val hasFdiv : Boolean = false,
val hasIfpu : Boolean = false,
val hasFpiu : Boolean = false,
val hasRocc : Boolean = false
)(implicit p: Parameters) extends BoomModule
{
val io = IO(new Bundle {
val fu_types = Output(Bits(FUC_SZ.W))
val req = Flipped(new DecoupledIO(new FuncUnitReq(dataWidth)))
val iresp = if (writesIrf) new DecoupledIO(new ExeUnitResp(dataWidth)) else null
val fresp = if (writesFrf) new DecoupledIO(new ExeUnitResp(dataWidth)) else null
val ll_iresp = if (writesLlIrf) new DecoupledIO(new ExeUnitResp(dataWidth)) else null
val ll_fresp = if (writesLlFrf) new DecoupledIO(new ExeUnitResp(dataWidth)) else null
val bypass = Output(Vec(numBypassStages, Valid(new ExeUnitResp(dataWidth))))
val brupdate = Input(new BrUpdateInfo())
// only used by the rocc unit
val rocc = if (hasRocc) new RoCCShimCoreIO else null
// only used by the branch unit
val brinfo = if (hasAlu) Output(new BrResolutionInfo()) else null
val get_ftq_pc = if (hasJmpUnit) Flipped(new GetPCFromFtqIO()) else null
val status = Input(new freechips.rocketchip.rocket.MStatus())
// only used by the fpu unit
val fcsr_rm = if (hasFcsr) Input(Bits(tile.FPConstants.RM_SZ.W)) else null
// only used by the mem unit
val lsu_io = if (hasMem) Flipped(new boom.v3.lsu.LSUExeIO) else null
val bp = if (hasMem) Input(Vec(nBreakpoints, new BP)) else null
val mcontext = if (hasMem) Input(UInt(coreParams.mcontextWidth.W)) else null
val scontext = if (hasMem) Input(UInt(coreParams.scontextWidth.W)) else null
// TODO move this out of ExecutionUnit
val com_exception = if (hasMem || hasRocc) Input(Bool()) else null
})
io.req.ready := false.B
if (writesIrf) {
io.iresp.valid := false.B
io.iresp.bits := DontCare
io.iresp.bits.fflags.valid := false.B
io.iresp.bits.predicated := false.B
assert(io.iresp.ready)
}
if (writesLlIrf) {
io.ll_iresp.valid := false.B
io.ll_iresp.bits := DontCare
io.ll_iresp.bits.fflags.valid := false.B
io.ll_iresp.bits.predicated := false.B
}
if (writesFrf) {
io.fresp.valid := false.B
io.fresp.bits := DontCare
io.fresp.bits.fflags.valid := false.B
io.fresp.bits.predicated := false.B
assert(io.fresp.ready)
}
if (writesLlFrf) {
io.ll_fresp.valid := false.B
io.ll_fresp.bits := DontCare
io.ll_fresp.bits.fflags.valid := false.B
io.ll_fresp.bits.predicated := false.B
}
// TODO add "number of fflag ports", so we can properly account for FPU+Mem combinations
def hasFFlags : Boolean = hasFpu || hasFdiv
require ((hasFpu || hasFdiv) ^ (hasAlu || hasMul || hasMem || hasIfpu),
"[execute] we no longer support mixing FP and Integer functional units in the same exe unit.")
def hasFcsr = hasIfpu || hasFpu || hasFdiv
require (bypassable || !alwaysBypassable,
"[execute] an execution unit must be bypassable if it is always bypassable")
def supportedFuncUnits = {
new SupportedFuncUnits(
alu = hasAlu,
jmp = hasJmpUnit,
mem = hasMem,
muld = hasMul || hasDiv,
fpu = hasFpu,
csr = hasCSR,
fdiv = hasFdiv,
ifpu = hasIfpu)
}
}
/**
* ALU execution unit that can have a branch, alu, mul, div, int to FP,
* and memory unit.
*
* @param hasBrUnit does the exe unit have a branch unit
* @param hasCSR does the exe unit write to the CSRFile
* @param hasAlu does the exe unit have a alu
* @param hasMul does the exe unit have a multiplier
* @param hasDiv does the exe unit have a divider
* @param hasIfpu does the exe unit have a int to FP unit
* @param hasMem does the exe unit have a MemAddrCalcUnit
*/
class ALUExeUnit(
hasJmpUnit : Boolean = false,
hasCSR : Boolean = false,
hasAlu : Boolean = true,
hasMul : Boolean = false,
hasDiv : Boolean = false,
hasIfpu : Boolean = false,
hasMem : Boolean = false,
hasRocc : Boolean = false)
(implicit p: Parameters)
extends ExecutionUnit(
readsIrf = true,
writesIrf = hasAlu || hasMul || hasDiv,
writesLlIrf = hasMem || hasRocc,
writesLlFrf = (hasIfpu || hasMem) && p(tile.TileKey).core.fpu != None,
numBypassStages =
if (hasAlu && hasMul) 3 //TODO XXX p(tile.TileKey).core.imulLatency
else if (hasAlu) 1 else 0,
dataWidth = 64 + 1,
bypassable = hasAlu,
alwaysBypassable = hasAlu && !(hasMem || hasJmpUnit || hasMul || hasDiv || hasCSR || hasIfpu || hasRocc),
hasCSR = hasCSR,
hasJmpUnit = hasJmpUnit,
hasAlu = hasAlu,
hasMul = hasMul,
hasDiv = hasDiv,
hasIfpu = hasIfpu,
hasMem = hasMem,
hasRocc = hasRocc)
with freechips.rocketchip.rocket.constants.MemoryOpConstants
{
require(!(hasRocc && !hasCSR),
"RoCC needs to be shared with CSR unit")
require(!(hasMem && hasRocc),
"We do not support execution unit with both Mem and Rocc writebacks")
require(!(hasMem && hasIfpu),
"TODO. Currently do not support AluMemExeUnit with FP")
val out_str =
BoomCoreStringPrefix("==ExeUnit==") +
(if (hasAlu) BoomCoreStringPrefix(" - ALU") else "") +
(if (hasMul) BoomCoreStringPrefix(" - Mul") else "") +
(if (hasDiv) BoomCoreStringPrefix(" - Div") else "") +
(if (hasIfpu) BoomCoreStringPrefix(" - IFPU") else "") +
(if (hasMem) BoomCoreStringPrefix(" - Mem") else "") +
(if (hasRocc) BoomCoreStringPrefix(" - RoCC") else "")
override def toString: String = out_str.toString
val div_busy = WireInit(false.B)
val ifpu_busy = WireInit(false.B)
// The Functional Units --------------------
// Specifically the functional units with fast writeback to IRF
val iresp_fu_units = ArrayBuffer[FunctionalUnit]()
io.fu_types := Mux(hasAlu.B, FU_ALU, 0.U) |
Mux(hasMul.B, FU_MUL, 0.U) |
Mux(!div_busy && hasDiv.B, FU_DIV, 0.U) |
Mux(hasCSR.B, FU_CSR, 0.U) |
Mux(hasJmpUnit.B, FU_JMP, 0.U) |
Mux(!ifpu_busy && hasIfpu.B, FU_I2F, 0.U) |
Mux(hasMem.B, FU_MEM, 0.U)
// ALU Unit -------------------------------
var alu: ALUUnit = null
if (hasAlu) {
alu = Module(new ALUUnit(isJmpUnit = hasJmpUnit,
numStages = numBypassStages,
dataWidth = xLen))
alu.io.req.valid := (
io.req.valid &&
(io.req.bits.uop.fu_code === FU_ALU ||
io.req.bits.uop.fu_code === FU_JMP ||
(io.req.bits.uop.fu_code === FU_CSR && io.req.bits.uop.uopc =/= uopROCC)))
//ROCC Rocc Commands are taken by the RoCC unit
alu.io.req.bits.uop := io.req.bits.uop
alu.io.req.bits.kill := io.req.bits.kill
alu.io.req.bits.rs1_data := io.req.bits.rs1_data
alu.io.req.bits.rs2_data := io.req.bits.rs2_data
alu.io.req.bits.rs3_data := DontCare
alu.io.req.bits.pred_data := io.req.bits.pred_data
alu.io.resp.ready := DontCare
alu.io.brupdate := io.brupdate
iresp_fu_units += alu
// Bypassing only applies to ALU
io.bypass := alu.io.bypass
// branch unit is embedded inside the ALU
io.brinfo := alu.io.brinfo
if (hasJmpUnit) {
alu.io.get_ftq_pc <> io.get_ftq_pc
}
}
var rocc: RoCCShim = null
if (hasRocc) {
rocc = Module(new RoCCShim)
rocc.io.req.valid := io.req.valid && io.req.bits.uop.uopc === uopROCC
rocc.io.req.bits := DontCare
rocc.io.req.bits.uop := io.req.bits.uop
rocc.io.req.bits.kill := io.req.bits.kill
rocc.io.req.bits.rs1_data := io.req.bits.rs1_data
rocc.io.req.bits.rs2_data := io.req.bits.rs2_data
rocc.io.brupdate := io.brupdate // We should assert on this somewhere
rocc.io.status := io.status
rocc.io.exception := io.com_exception
io.rocc <> rocc.io.core
rocc.io.resp.ready := io.ll_iresp.ready
io.ll_iresp.valid := rocc.io.resp.valid
io.ll_iresp.bits.uop := rocc.io.resp.bits.uop
io.ll_iresp.bits.data := rocc.io.resp.bits.data
}
// Pipelined, IMul Unit ------------------
var imul: PipelinedMulUnit = null
if (hasMul) {
imul = Module(new PipelinedMulUnit(imulLatency, xLen))
imul.io <> DontCare
imul.io.req.valid := io.req.valid && io.req.bits.uop.fu_code_is(FU_MUL)
imul.io.req.bits.uop := io.req.bits.uop
imul.io.req.bits.rs1_data := io.req.bits.rs1_data
imul.io.req.bits.rs2_data := io.req.bits.rs2_data
imul.io.req.bits.kill := io.req.bits.kill
imul.io.brupdate := io.brupdate
iresp_fu_units += imul
}
var ifpu: IntToFPUnit = null
if (hasIfpu) {
ifpu = Module(new IntToFPUnit(latency=intToFpLatency))
ifpu.io.req <> io.req
ifpu.io.req.valid := io.req.valid && io.req.bits.uop.fu_code_is(FU_I2F)
ifpu.io.fcsr_rm := io.fcsr_rm
ifpu.io.brupdate <> io.brupdate
ifpu.io.resp.ready := DontCare
// buffer up results since we share write-port on integer regfile.
val queue = Module(new BranchKillableQueue(new ExeUnitResp(dataWidth),
entries = intToFpLatency + 3)) // TODO being overly conservative
queue.io.enq.valid := ifpu.io.resp.valid
queue.io.enq.bits.uop := ifpu.io.resp.bits.uop
queue.io.enq.bits.data := ifpu.io.resp.bits.data
queue.io.enq.bits.predicated := ifpu.io.resp.bits.predicated
queue.io.enq.bits.fflags := ifpu.io.resp.bits.fflags
queue.io.brupdate := io.brupdate
queue.io.flush := io.req.bits.kill
io.ll_fresp <> queue.io.deq
ifpu_busy := !(queue.io.empty)
assert (queue.io.enq.ready)
}
// Div/Rem Unit -----------------------
var div: DivUnit = null
val div_resp_val = WireInit(false.B)
if (hasDiv) {
div = Module(new DivUnit(xLen))
div.io <> DontCare
div.io.req.valid := io.req.valid && io.req.bits.uop.fu_code_is(FU_DIV) && hasDiv.B
div.io.req.bits.uop := io.req.bits.uop
div.io.req.bits.rs1_data := io.req.bits.rs1_data
div.io.req.bits.rs2_data := io.req.bits.rs2_data
div.io.brupdate := io.brupdate
div.io.req.bits.kill := io.req.bits.kill
// share write port with the pipelined units
div.io.resp.ready := !(iresp_fu_units.map(_.io.resp.valid).reduce(_|_))
div_resp_val := div.io.resp.valid
div_busy := !div.io.req.ready ||
(io.req.valid && io.req.bits.uop.fu_code_is(FU_DIV))
iresp_fu_units += div
}
// Mem Unit --------------------------
if (hasMem) {
require(!hasAlu)
val maddrcalc = Module(new MemAddrCalcUnit)
maddrcalc.io.req <> io.req
maddrcalc.io.req.valid := io.req.valid && io.req.bits.uop.fu_code_is(FU_MEM)
maddrcalc.io.brupdate <> io.brupdate
maddrcalc.io.status := io.status
maddrcalc.io.bp := io.bp
maddrcalc.io.mcontext := io.mcontext
maddrcalc.io.scontext := io.scontext
maddrcalc.io.resp.ready := DontCare
require(numBypassStages == 0)
io.lsu_io.req := maddrcalc.io.resp
io.ll_iresp <> io.lsu_io.iresp
if (usingFPU) {
io.ll_fresp <> io.lsu_io.fresp
}
}
// Outputs (Write Port #0) ---------------
if (writesIrf) {
io.iresp.valid := iresp_fu_units.map(_.io.resp.valid).reduce(_|_)
io.iresp.bits.uop := PriorityMux(iresp_fu_units.map(f =>
(f.io.resp.valid, f.io.resp.bits.uop)).toSeq)
io.iresp.bits.data := PriorityMux(iresp_fu_units.map(f =>
(f.io.resp.valid, f.io.resp.bits.data)).toSeq)
io.iresp.bits.predicated := PriorityMux(iresp_fu_units.map(f =>
(f.io.resp.valid, f.io.resp.bits.predicated)).toSeq)
// pulled out for critical path reasons
// TODO: Does this make sense as part of the iresp bundle?
if (hasAlu) {
io.iresp.bits.uop.csr_addr := ImmGen(alu.io.resp.bits.uop.imm_packed, IS_I).asUInt
io.iresp.bits.uop.ctrl.csr_cmd := alu.io.resp.bits.uop.ctrl.csr_cmd
}
}
assert ((PopCount(iresp_fu_units.map(_.io.resp.valid)) <= 1.U && !div_resp_val) ||
(PopCount(iresp_fu_units.map(_.io.resp.valid)) <= 2.U && (div_resp_val)),
"Multiple functional units are fighting over the write port.")
}
/**
* FPU-only unit, with optional second write-port for ToInt micro-ops.
*
* @param hasFpu does the exe unit have a fpu
* @param hasFdiv does the exe unit have a FP divider
* @param hasFpiu does the exe unit have a FP to int unit
*/
class FPUExeUnit(
hasFpu : Boolean = true,
hasFdiv : Boolean = false,
hasFpiu : Boolean = false
)
(implicit p: Parameters)
extends ExecutionUnit(
readsFrf = true,
writesFrf = true,
writesLlIrf = hasFpiu,
writesIrf = false,
numBypassStages = 0,
dataWidth = p(tile.TileKey).core.fpu.get.fLen + 1,
bypassable = false,
hasFpu = hasFpu,
hasFdiv = hasFdiv,
hasFpiu = hasFpiu) with tile.HasFPUParameters
{
val out_str =
BoomCoreStringPrefix("==ExeUnit==")
(if (hasFpu) BoomCoreStringPrefix("- FPU (Latency: " + dfmaLatency + ")") else "") +
(if (hasFdiv) BoomCoreStringPrefix("- FDiv/FSqrt") else "") +
(if (hasFpiu) BoomCoreStringPrefix("- FPIU (writes to Integer RF)") else "")
val fdiv_busy = WireInit(false.B)
val fpiu_busy = WireInit(false.B)
// The Functional Units --------------------
val fu_units = ArrayBuffer[FunctionalUnit]()
io.fu_types := Mux(hasFpu.B, FU_FPU, 0.U) |
Mux(!fdiv_busy && hasFdiv.B, FU_FDV, 0.U) |
Mux(!fpiu_busy && hasFpiu.B, FU_F2I, 0.U)
// FPU Unit -----------------------
var fpu: FPUUnit = null
val fpu_resp_val = WireInit(false.B)
val fpu_resp_fflags = Wire(new ValidIO(new FFlagsResp()))
fpu_resp_fflags.valid := false.B
if (hasFpu) {
fpu = Module(new FPUUnit())
fpu.io.req.valid := io.req.valid &&
(io.req.bits.uop.fu_code_is(FU_FPU) ||
io.req.bits.uop.fu_code_is(FU_F2I)) // TODO move to using a separate unit
fpu.io.req.bits.uop := io.req.bits.uop
fpu.io.req.bits.rs1_data := io.req.bits.rs1_data
fpu.io.req.bits.rs2_data := io.req.bits.rs2_data
fpu.io.req.bits.rs3_data := io.req.bits.rs3_data
fpu.io.req.bits.pred_data := false.B
fpu.io.req.bits.kill := io.req.bits.kill
fpu.io.fcsr_rm := io.fcsr_rm
fpu.io.brupdate := io.brupdate
fpu.io.resp.ready := DontCare
fpu_resp_val := fpu.io.resp.valid
fpu_resp_fflags := fpu.io.resp.bits.fflags
fu_units += fpu
}
// FDiv/FSqrt Unit -----------------------
var fdivsqrt: FDivSqrtUnit = null
val fdiv_resp_fflags = Wire(new ValidIO(new FFlagsResp()))
fdiv_resp_fflags := DontCare
fdiv_resp_fflags.valid := false.B
if (hasFdiv) {
fdivsqrt = Module(new FDivSqrtUnit())
fdivsqrt.io.req.valid := io.req.valid && io.req.bits.uop.fu_code_is(FU_FDV)
fdivsqrt.io.req.bits.uop := io.req.bits.uop
fdivsqrt.io.req.bits.rs1_data := io.req.bits.rs1_data
fdivsqrt.io.req.bits.rs2_data := io.req.bits.rs2_data
fdivsqrt.io.req.bits.rs3_data := DontCare
fdivsqrt.io.req.bits.pred_data := false.B
fdivsqrt.io.req.bits.kill := io.req.bits.kill
fdivsqrt.io.fcsr_rm := io.fcsr_rm
fdivsqrt.io.brupdate := io.brupdate
// share write port with the pipelined units
fdivsqrt.io.resp.ready := !(fu_units.map(_.io.resp.valid).reduce(_|_)) // TODO PERF will get blocked by fpiu.
fdiv_busy := !fdivsqrt.io.req.ready || (io.req.valid && io.req.bits.uop.fu_code_is(FU_FDV))
fdiv_resp_fflags := fdivsqrt.io.resp.bits.fflags
fu_units += fdivsqrt
}
// Outputs (Write Port #0) ---------------
io.fresp.valid := fu_units.map(_.io.resp.valid).reduce(_|_) &&
!(fpu.io.resp.valid && fpu.io.resp.bits.uop.fu_code_is(FU_F2I))
io.fresp.bits.uop := PriorityMux(fu_units.map(f => (f.io.resp.valid,
f.io.resp.bits.uop)).toSeq)
io.fresp.bits.data:= PriorityMux(fu_units.map(f => (f.io.resp.valid, f.io.resp.bits.data)).toSeq)
io.fresp.bits.fflags := Mux(fpu_resp_val, fpu_resp_fflags, fdiv_resp_fflags)
// Outputs (Write Port #1) -- FpToInt Queuing Unit -----------------------
if (hasFpiu) {
// TODO instantiate our own fpiu; and remove it from fpu.scala.
// buffer up results since we share write-port on integer regfile.
val queue = Module(new BranchKillableQueue(new ExeUnitResp(dataWidth),
entries = dfmaLatency + 3)) // TODO being overly conservative
queue.io.enq.valid := (fpu.io.resp.valid &&
fpu.io.resp.bits.uop.fu_code_is(FU_F2I) &&
fpu.io.resp.bits.uop.uopc =/= uopSTA) // STA means store data gen for floating point
queue.io.enq.bits.uop := fpu.io.resp.bits.uop
queue.io.enq.bits.data := fpu.io.resp.bits.data
queue.io.enq.bits.predicated := fpu.io.resp.bits.predicated
queue.io.enq.bits.fflags := fpu.io.resp.bits.fflags
queue.io.brupdate := io.brupdate
queue.io.flush := io.req.bits.kill
assert (queue.io.enq.ready) // If this backs up, we've miscalculated the size of the queue.
val fp_sdq = Module(new BranchKillableQueue(new ExeUnitResp(dataWidth),
entries = 3)) // Lets us backpressure floating point store data
fp_sdq.io.enq.valid := io.req.valid && io.req.bits.uop.uopc === uopSTA && !IsKilledByBranch(io.brupdate, io.req.bits.uop)
fp_sdq.io.enq.bits.uop := io.req.bits.uop
fp_sdq.io.enq.bits.data := ieee(io.req.bits.rs2_data)
fp_sdq.io.enq.bits.predicated := false.B
fp_sdq.io.enq.bits.fflags := DontCare
fp_sdq.io.brupdate := io.brupdate
fp_sdq.io.flush := io.req.bits.kill
assert(!(fp_sdq.io.enq.valid && !fp_sdq.io.enq.ready))
val resp_arb = Module(new Arbiter(new ExeUnitResp(dataWidth), 2))
resp_arb.io.in(0) <> queue.io.deq
resp_arb.io.in(1) <> fp_sdq.io.deq
io.ll_iresp <> resp_arb.io.out
fpiu_busy := !(queue.io.empty && fp_sdq.io.empty)
}
override def toString: String = out_str.toString
}
File micro-op.scala:
//******************************************************************************
// Copyright (c) 2015 - 2018, The Regents of the University of California (Regents).
// All Rights Reserved. See LICENSE and LICENSE.SiFive for license details.
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
// MicroOp
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
package boom.v3.common
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.Parameters
import boom.v3.exu.FUConstants
/**
* Extension to BoomBundle to add a MicroOp
*/
abstract trait HasBoomUOP extends BoomBundle
{
val uop = new MicroOp()
}
/**
* MicroOp passing through the pipeline
*/
class MicroOp(implicit p: Parameters) extends BoomBundle
with freechips.rocketchip.rocket.constants.MemoryOpConstants
with freechips.rocketchip.rocket.constants.ScalarOpConstants
{
val uopc = UInt(UOPC_SZ.W) // micro-op code
val inst = UInt(32.W)
val debug_inst = UInt(32.W)
val is_rvc = Bool()
val debug_pc = UInt(coreMaxAddrBits.W)
val iq_type = UInt(IQT_SZ.W) // which issue unit do we use?
val fu_code = UInt(FUConstants.FUC_SZ.W) // which functional unit do we use?
val ctrl = new CtrlSignals
// What is the next state of this uop in the issue window? useful
// for the compacting queue.
val iw_state = UInt(2.W)
// Has operand 1 or 2 been waken speculatively by a load?
// Only integer operands are speculaively woken up,
// so we can ignore p3.
val iw_p1_poisoned = Bool()
val iw_p2_poisoned = Bool()
val is_br = Bool() // is this micro-op a (branch) vs a regular PC+4 inst?
val is_jalr = Bool() // is this a jump? (jal or jalr)
val is_jal = Bool() // is this a JAL (doesn't include JR)? used for branch unit
val is_sfb = Bool() // is this a sfb or in the shadow of a sfb
val br_mask = UInt(maxBrCount.W) // which branches are we being speculated under?
val br_tag = UInt(brTagSz.W)
// Index into FTQ to figure out our fetch PC.
val ftq_idx = UInt(log2Ceil(ftqSz).W)
// This inst straddles two fetch packets
val edge_inst = Bool()
// Low-order bits of our own PC. Combine with ftq[ftq_idx] to get PC.
// Aligned to a cache-line size, as that is the greater fetch granularity.
// TODO: Shouldn't this be aligned to fetch-width size?
val pc_lob = UInt(log2Ceil(icBlockBytes).W)
// Was this a branch that was predicted taken?
val taken = Bool()
val imm_packed = UInt(LONGEST_IMM_SZ.W) // densely pack the imm in decode...
// then translate and sign-extend in execute
val csr_addr = UInt(CSR_ADDR_SZ.W) // only used for critical path reasons in Exe
val rob_idx = UInt(robAddrSz.W)
val ldq_idx = UInt(ldqAddrSz.W)
val stq_idx = UInt(stqAddrSz.W)
val rxq_idx = UInt(log2Ceil(numRxqEntries).W)
val pdst = UInt(maxPregSz.W)
val prs1 = UInt(maxPregSz.W)
val prs2 = UInt(maxPregSz.W)
val prs3 = UInt(maxPregSz.W)
val ppred = UInt(log2Ceil(ftqSz).W)
val prs1_busy = Bool()
val prs2_busy = Bool()
val prs3_busy = Bool()
val ppred_busy = Bool()
val stale_pdst = UInt(maxPregSz.W)
val exception = Bool()
val exc_cause = UInt(xLen.W) // TODO compress this down, xlen is insanity
val bypassable = Bool() // can we bypass ALU results? (doesn't include loads, csr, etc...)
val mem_cmd = UInt(M_SZ.W) // sync primitives/cache flushes
val mem_size = UInt(2.W)
val mem_signed = Bool()
val is_fence = Bool()
val is_fencei = Bool()
val is_amo = Bool()
val uses_ldq = Bool()
val uses_stq = Bool()
val is_sys_pc2epc = Bool() // Is a ECall or Breakpoint -- both set EPC to PC.
val is_unique = Bool() // only allow this instruction in the pipeline, wait for STQ to
// drain, clear fetcha fter it (tell ROB to un-ready until empty)
val flush_on_commit = Bool() // some instructions need to flush the pipeline behind them
// Preditation
def is_sfb_br = is_br && is_sfb && enableSFBOpt.B // Does this write a predicate
def is_sfb_shadow = !is_br && is_sfb && enableSFBOpt.B // Is this predicated
val ldst_is_rs1 = Bool() // If this is set and we are predicated off, copy rs1 to dst,
// else copy rs2 to dst
// logical specifiers (only used in Decode->Rename), except rollback (ldst)
val ldst = UInt(lregSz.W)
val lrs1 = UInt(lregSz.W)
val lrs2 = UInt(lregSz.W)
val lrs3 = UInt(lregSz.W)
val ldst_val = Bool() // is there a destination? invalid for stores, rd==x0, etc.
val dst_rtype = UInt(2.W)
val lrs1_rtype = UInt(2.W)
val lrs2_rtype = UInt(2.W)
val frs3_en = Bool()
// floating point information
val fp_val = Bool() // is a floating-point instruction (F- or D-extension)?
// If it's non-ld/st it will write back exception bits to the fcsr.
val fp_single = Bool() // single-precision floating point instruction (F-extension)
// frontend exception information
val xcpt_pf_if = Bool() // I-TLB page fault.
val xcpt_ae_if = Bool() // I$ access exception.
val xcpt_ma_if = Bool() // Misaligned fetch (jal/brjumping to misaligned addr).
val bp_debug_if = Bool() // Breakpoint
val bp_xcpt_if = Bool() // Breakpoint
// What prediction structure provides the prediction FROM this op
val debug_fsrc = UInt(BSRC_SZ.W)
// What prediction structure provides the prediction TO this op
val debug_tsrc = UInt(BSRC_SZ.W)
// Do we allocate a branch tag for this?
// SFB branches don't get a mask, they get a predicate bit
def allocate_brtag = (is_br && !is_sfb) || is_jalr
// Does this register write-back
def rf_wen = dst_rtype =/= RT_X
// Is it possible for this uop to misspeculate, preventing the commit of subsequent uops?
def unsafe = uses_ldq || (uses_stq && !is_fence) || is_br || is_jalr
def fu_code_is(_fu: UInt) = (fu_code & _fu) =/= 0.U
}
/**
* Control signals within a MicroOp
*
* TODO REFACTOR this, as this should no longer be true, as bypass occurs in stage before branch resolution
*/
class CtrlSignals extends Bundle()
{
val br_type = UInt(BR_N.getWidth.W)
val op1_sel = UInt(OP1_X.getWidth.W)
val op2_sel = UInt(OP2_X.getWidth.W)
val imm_sel = UInt(IS_X.getWidth.W)
val op_fcn = UInt(freechips.rocketchip.rocket.ALU.SZ_ALU_FN.W)
val fcn_dw = Bool()
val csr_cmd = UInt(freechips.rocketchip.rocket.CSR.SZ.W)
val is_load = Bool() // will invoke TLB address lookup
val is_sta = Bool() // will invoke TLB address lookup
val is_std = Bool()
}
File rawFloatFromRecFN.scala:
/*============================================================================
This Chisel source file is part of a pre-release version of the HardFloat IEEE
Floating-Point Arithmetic Package, by John R. Hauser (with some contributions
from Yunsup Lee and Andrew Waterman, mainly concerning testing).
Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the
University of California. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
package hardfloat
import chisel3._
import chisel3.util._
/*----------------------------------------------------------------------------
| In the result, no more than one of 'isNaN', 'isInf', and 'isZero' will be
| set.
*----------------------------------------------------------------------------*/
object rawFloatFromRecFN
{
def apply(expWidth: Int, sigWidth: Int, in: Bits): RawFloat =
{
val exp = in(expWidth + sigWidth - 1, sigWidth - 1)
val isZero = exp(expWidth, expWidth - 2) === 0.U
val isSpecial = exp(expWidth, expWidth - 1) === 3.U
val out = Wire(new RawFloat(expWidth, sigWidth))
out.isNaN := isSpecial && exp(expWidth - 2)
out.isInf := isSpecial && ! exp(expWidth - 2)
out.isZero := isZero
out.sign := in(expWidth + sigWidth)
out.sExp := exp.zext
out.sig := 0.U(1.W) ## ! isZero ## in(sigWidth - 2, 0)
out
}
}
| module FPUExeUnit_1( // @[execution-unit.scala:437:7]
input clock, // @[execution-unit.scala:437:7]
input reset, // @[execution-unit.scala:437:7]
output [9:0] io_fu_types, // @[execution-unit.scala:104:14]
input io_req_valid, // @[execution-unit.scala:104:14]
input [6:0] io_req_bits_uop_uopc, // @[execution-unit.scala:104:14]
input [31:0] io_req_bits_uop_inst, // @[execution-unit.scala:104:14]
input [31:0] io_req_bits_uop_debug_inst, // @[execution-unit.scala:104:14]
input io_req_bits_uop_is_rvc, // @[execution-unit.scala:104:14]
input [39:0] io_req_bits_uop_debug_pc, // @[execution-unit.scala:104:14]
input [2:0] io_req_bits_uop_iq_type, // @[execution-unit.scala:104:14]
input [9:0] io_req_bits_uop_fu_code, // @[execution-unit.scala:104:14]
input [3:0] io_req_bits_uop_ctrl_br_type, // @[execution-unit.scala:104:14]
input [1:0] io_req_bits_uop_ctrl_op1_sel, // @[execution-unit.scala:104:14]
input [2:0] io_req_bits_uop_ctrl_op2_sel, // @[execution-unit.scala:104:14]
input [2:0] io_req_bits_uop_ctrl_imm_sel, // @[execution-unit.scala:104:14]
input [4:0] io_req_bits_uop_ctrl_op_fcn, // @[execution-unit.scala:104:14]
input io_req_bits_uop_ctrl_fcn_dw, // @[execution-unit.scala:104:14]
input [2:0] io_req_bits_uop_ctrl_csr_cmd, // @[execution-unit.scala:104:14]
input io_req_bits_uop_ctrl_is_load, // @[execution-unit.scala:104:14]
input io_req_bits_uop_ctrl_is_sta, // @[execution-unit.scala:104:14]
input io_req_bits_uop_ctrl_is_std, // @[execution-unit.scala:104:14]
input [1:0] io_req_bits_uop_iw_state, // @[execution-unit.scala:104:14]
input io_req_bits_uop_iw_p1_poisoned, // @[execution-unit.scala:104:14]
input io_req_bits_uop_iw_p2_poisoned, // @[execution-unit.scala:104:14]
input io_req_bits_uop_is_br, // @[execution-unit.scala:104:14]
input io_req_bits_uop_is_jalr, // @[execution-unit.scala:104:14]
input io_req_bits_uop_is_jal, // @[execution-unit.scala:104:14]
input io_req_bits_uop_is_sfb, // @[execution-unit.scala:104:14]
input [15:0] io_req_bits_uop_br_mask, // @[execution-unit.scala:104:14]
input [3:0] io_req_bits_uop_br_tag, // @[execution-unit.scala:104:14]
input [4:0] io_req_bits_uop_ftq_idx, // @[execution-unit.scala:104:14]
input io_req_bits_uop_edge_inst, // @[execution-unit.scala:104:14]
input [5:0] io_req_bits_uop_pc_lob, // @[execution-unit.scala:104:14]
input io_req_bits_uop_taken, // @[execution-unit.scala:104:14]
input [19:0] io_req_bits_uop_imm_packed, // @[execution-unit.scala:104:14]
input [11:0] io_req_bits_uop_csr_addr, // @[execution-unit.scala:104:14]
input [6:0] io_req_bits_uop_rob_idx, // @[execution-unit.scala:104:14]
input [4:0] io_req_bits_uop_ldq_idx, // @[execution-unit.scala:104:14]
input [4:0] io_req_bits_uop_stq_idx, // @[execution-unit.scala:104:14]
input [1:0] io_req_bits_uop_rxq_idx, // @[execution-unit.scala:104:14]
input [6:0] io_req_bits_uop_pdst, // @[execution-unit.scala:104:14]
input [6:0] io_req_bits_uop_prs1, // @[execution-unit.scala:104:14]
input [6:0] io_req_bits_uop_prs2, // @[execution-unit.scala:104:14]
input [6:0] io_req_bits_uop_prs3, // @[execution-unit.scala:104:14]
input [4:0] io_req_bits_uop_ppred, // @[execution-unit.scala:104:14]
input io_req_bits_uop_prs1_busy, // @[execution-unit.scala:104:14]
input io_req_bits_uop_prs2_busy, // @[execution-unit.scala:104:14]
input io_req_bits_uop_prs3_busy, // @[execution-unit.scala:104:14]
input io_req_bits_uop_ppred_busy, // @[execution-unit.scala:104:14]
input [6:0] io_req_bits_uop_stale_pdst, // @[execution-unit.scala:104:14]
input io_req_bits_uop_exception, // @[execution-unit.scala:104:14]
input [63:0] io_req_bits_uop_exc_cause, // @[execution-unit.scala:104:14]
input io_req_bits_uop_bypassable, // @[execution-unit.scala:104:14]
input [4:0] io_req_bits_uop_mem_cmd, // @[execution-unit.scala:104:14]
input [1:0] io_req_bits_uop_mem_size, // @[execution-unit.scala:104:14]
input io_req_bits_uop_mem_signed, // @[execution-unit.scala:104:14]
input io_req_bits_uop_is_fence, // @[execution-unit.scala:104:14]
input io_req_bits_uop_is_fencei, // @[execution-unit.scala:104:14]
input io_req_bits_uop_is_amo, // @[execution-unit.scala:104:14]
input io_req_bits_uop_uses_ldq, // @[execution-unit.scala:104:14]
input io_req_bits_uop_uses_stq, // @[execution-unit.scala:104:14]
input io_req_bits_uop_is_sys_pc2epc, // @[execution-unit.scala:104:14]
input io_req_bits_uop_is_unique, // @[execution-unit.scala:104:14]
input io_req_bits_uop_flush_on_commit, // @[execution-unit.scala:104:14]
input io_req_bits_uop_ldst_is_rs1, // @[execution-unit.scala:104:14]
input [5:0] io_req_bits_uop_ldst, // @[execution-unit.scala:104:14]
input [5:0] io_req_bits_uop_lrs1, // @[execution-unit.scala:104:14]
input [5:0] io_req_bits_uop_lrs2, // @[execution-unit.scala:104:14]
input [5:0] io_req_bits_uop_lrs3, // @[execution-unit.scala:104:14]
input io_req_bits_uop_ldst_val, // @[execution-unit.scala:104:14]
input [1:0] io_req_bits_uop_dst_rtype, // @[execution-unit.scala:104:14]
input [1:0] io_req_bits_uop_lrs1_rtype, // @[execution-unit.scala:104:14]
input [1:0] io_req_bits_uop_lrs2_rtype, // @[execution-unit.scala:104:14]
input io_req_bits_uop_frs3_en, // @[execution-unit.scala:104:14]
input io_req_bits_uop_fp_val, // @[execution-unit.scala:104:14]
input io_req_bits_uop_fp_single, // @[execution-unit.scala:104:14]
input io_req_bits_uop_xcpt_pf_if, // @[execution-unit.scala:104:14]
input io_req_bits_uop_xcpt_ae_if, // @[execution-unit.scala:104:14]
input io_req_bits_uop_xcpt_ma_if, // @[execution-unit.scala:104:14]
input io_req_bits_uop_bp_debug_if, // @[execution-unit.scala:104:14]
input io_req_bits_uop_bp_xcpt_if, // @[execution-unit.scala:104:14]
input [1:0] io_req_bits_uop_debug_fsrc, // @[execution-unit.scala:104:14]
input [1:0] io_req_bits_uop_debug_tsrc, // @[execution-unit.scala:104:14]
input [64:0] io_req_bits_rs1_data, // @[execution-unit.scala:104:14]
input [64:0] io_req_bits_rs2_data, // @[execution-unit.scala:104:14]
input [64:0] io_req_bits_rs3_data, // @[execution-unit.scala:104:14]
input io_req_bits_kill, // @[execution-unit.scala:104:14]
output io_fresp_valid, // @[execution-unit.scala:104:14]
output [6:0] io_fresp_bits_uop_uopc, // @[execution-unit.scala:104:14]
output [31:0] io_fresp_bits_uop_inst, // @[execution-unit.scala:104:14]
output [31:0] io_fresp_bits_uop_debug_inst, // @[execution-unit.scala:104:14]
output io_fresp_bits_uop_is_rvc, // @[execution-unit.scala:104:14]
output [39:0] io_fresp_bits_uop_debug_pc, // @[execution-unit.scala:104:14]
output [2:0] io_fresp_bits_uop_iq_type, // @[execution-unit.scala:104:14]
output [9:0] io_fresp_bits_uop_fu_code, // @[execution-unit.scala:104:14]
output [3:0] io_fresp_bits_uop_ctrl_br_type, // @[execution-unit.scala:104:14]
output [1:0] io_fresp_bits_uop_ctrl_op1_sel, // @[execution-unit.scala:104:14]
output [2:0] io_fresp_bits_uop_ctrl_op2_sel, // @[execution-unit.scala:104:14]
output [2:0] io_fresp_bits_uop_ctrl_imm_sel, // @[execution-unit.scala:104:14]
output [4:0] io_fresp_bits_uop_ctrl_op_fcn, // @[execution-unit.scala:104:14]
output io_fresp_bits_uop_ctrl_fcn_dw, // @[execution-unit.scala:104:14]
output [2:0] io_fresp_bits_uop_ctrl_csr_cmd, // @[execution-unit.scala:104:14]
output io_fresp_bits_uop_ctrl_is_load, // @[execution-unit.scala:104:14]
output io_fresp_bits_uop_ctrl_is_sta, // @[execution-unit.scala:104:14]
output io_fresp_bits_uop_ctrl_is_std, // @[execution-unit.scala:104:14]
output [1:0] io_fresp_bits_uop_iw_state, // @[execution-unit.scala:104:14]
output io_fresp_bits_uop_iw_p1_poisoned, // @[execution-unit.scala:104:14]
output io_fresp_bits_uop_iw_p2_poisoned, // @[execution-unit.scala:104:14]
output io_fresp_bits_uop_is_br, // @[execution-unit.scala:104:14]
output io_fresp_bits_uop_is_jalr, // @[execution-unit.scala:104:14]
output io_fresp_bits_uop_is_jal, // @[execution-unit.scala:104:14]
output io_fresp_bits_uop_is_sfb, // @[execution-unit.scala:104:14]
output [15:0] io_fresp_bits_uop_br_mask, // @[execution-unit.scala:104:14]
output [3:0] io_fresp_bits_uop_br_tag, // @[execution-unit.scala:104:14]
output [4:0] io_fresp_bits_uop_ftq_idx, // @[execution-unit.scala:104:14]
output io_fresp_bits_uop_edge_inst, // @[execution-unit.scala:104:14]
output [5:0] io_fresp_bits_uop_pc_lob, // @[execution-unit.scala:104:14]
output io_fresp_bits_uop_taken, // @[execution-unit.scala:104:14]
output [19:0] io_fresp_bits_uop_imm_packed, // @[execution-unit.scala:104:14]
output [11:0] io_fresp_bits_uop_csr_addr, // @[execution-unit.scala:104:14]
output [6:0] io_fresp_bits_uop_rob_idx, // @[execution-unit.scala:104:14]
output [4:0] io_fresp_bits_uop_ldq_idx, // @[execution-unit.scala:104:14]
output [4:0] io_fresp_bits_uop_stq_idx, // @[execution-unit.scala:104:14]
output [1:0] io_fresp_bits_uop_rxq_idx, // @[execution-unit.scala:104:14]
output [6:0] io_fresp_bits_uop_pdst, // @[execution-unit.scala:104:14]
output [6:0] io_fresp_bits_uop_prs1, // @[execution-unit.scala:104:14]
output [6:0] io_fresp_bits_uop_prs2, // @[execution-unit.scala:104:14]
output [6:0] io_fresp_bits_uop_prs3, // @[execution-unit.scala:104:14]
output [4:0] io_fresp_bits_uop_ppred, // @[execution-unit.scala:104:14]
output io_fresp_bits_uop_prs1_busy, // @[execution-unit.scala:104:14]
output io_fresp_bits_uop_prs2_busy, // @[execution-unit.scala:104:14]
output io_fresp_bits_uop_prs3_busy, // @[execution-unit.scala:104:14]
output io_fresp_bits_uop_ppred_busy, // @[execution-unit.scala:104:14]
output [6:0] io_fresp_bits_uop_stale_pdst, // @[execution-unit.scala:104:14]
output io_fresp_bits_uop_exception, // @[execution-unit.scala:104:14]
output [63:0] io_fresp_bits_uop_exc_cause, // @[execution-unit.scala:104:14]
output io_fresp_bits_uop_bypassable, // @[execution-unit.scala:104:14]
output [4:0] io_fresp_bits_uop_mem_cmd, // @[execution-unit.scala:104:14]
output [1:0] io_fresp_bits_uop_mem_size, // @[execution-unit.scala:104:14]
output io_fresp_bits_uop_mem_signed, // @[execution-unit.scala:104:14]
output io_fresp_bits_uop_is_fence, // @[execution-unit.scala:104:14]
output io_fresp_bits_uop_is_fencei, // @[execution-unit.scala:104:14]
output io_fresp_bits_uop_is_amo, // @[execution-unit.scala:104:14]
output io_fresp_bits_uop_uses_ldq, // @[execution-unit.scala:104:14]
output io_fresp_bits_uop_uses_stq, // @[execution-unit.scala:104:14]
output io_fresp_bits_uop_is_sys_pc2epc, // @[execution-unit.scala:104:14]
output io_fresp_bits_uop_is_unique, // @[execution-unit.scala:104:14]
output io_fresp_bits_uop_flush_on_commit, // @[execution-unit.scala:104:14]
output io_fresp_bits_uop_ldst_is_rs1, // @[execution-unit.scala:104:14]
output [5:0] io_fresp_bits_uop_ldst, // @[execution-unit.scala:104:14]
output [5:0] io_fresp_bits_uop_lrs1, // @[execution-unit.scala:104:14]
output [5:0] io_fresp_bits_uop_lrs2, // @[execution-unit.scala:104:14]
output [5:0] io_fresp_bits_uop_lrs3, // @[execution-unit.scala:104:14]
output io_fresp_bits_uop_ldst_val, // @[execution-unit.scala:104:14]
output [1:0] io_fresp_bits_uop_dst_rtype, // @[execution-unit.scala:104:14]
output [1:0] io_fresp_bits_uop_lrs1_rtype, // @[execution-unit.scala:104:14]
output [1:0] io_fresp_bits_uop_lrs2_rtype, // @[execution-unit.scala:104:14]
output io_fresp_bits_uop_frs3_en, // @[execution-unit.scala:104:14]
output io_fresp_bits_uop_fp_val, // @[execution-unit.scala:104:14]
output io_fresp_bits_uop_fp_single, // @[execution-unit.scala:104:14]
output io_fresp_bits_uop_xcpt_pf_if, // @[execution-unit.scala:104:14]
output io_fresp_bits_uop_xcpt_ae_if, // @[execution-unit.scala:104:14]
output io_fresp_bits_uop_xcpt_ma_if, // @[execution-unit.scala:104:14]
output io_fresp_bits_uop_bp_debug_if, // @[execution-unit.scala:104:14]
output io_fresp_bits_uop_bp_xcpt_if, // @[execution-unit.scala:104:14]
output [1:0] io_fresp_bits_uop_debug_fsrc, // @[execution-unit.scala:104:14]
output [1:0] io_fresp_bits_uop_debug_tsrc, // @[execution-unit.scala:104:14]
output [64:0] io_fresp_bits_data, // @[execution-unit.scala:104:14]
output io_fresp_bits_fflags_valid, // @[execution-unit.scala:104:14]
output [6:0] io_fresp_bits_fflags_bits_uop_uopc, // @[execution-unit.scala:104:14]
output [31:0] io_fresp_bits_fflags_bits_uop_inst, // @[execution-unit.scala:104:14]
output [31:0] io_fresp_bits_fflags_bits_uop_debug_inst, // @[execution-unit.scala:104:14]
output io_fresp_bits_fflags_bits_uop_is_rvc, // @[execution-unit.scala:104:14]
output [39:0] io_fresp_bits_fflags_bits_uop_debug_pc, // @[execution-unit.scala:104:14]
output [2:0] io_fresp_bits_fflags_bits_uop_iq_type, // @[execution-unit.scala:104:14]
output [9:0] io_fresp_bits_fflags_bits_uop_fu_code, // @[execution-unit.scala:104:14]
output [3:0] io_fresp_bits_fflags_bits_uop_ctrl_br_type, // @[execution-unit.scala:104:14]
output [1:0] io_fresp_bits_fflags_bits_uop_ctrl_op1_sel, // @[execution-unit.scala:104:14]
output [2:0] io_fresp_bits_fflags_bits_uop_ctrl_op2_sel, // @[execution-unit.scala:104:14]
output [2:0] io_fresp_bits_fflags_bits_uop_ctrl_imm_sel, // @[execution-unit.scala:104:14]
output [4:0] io_fresp_bits_fflags_bits_uop_ctrl_op_fcn, // @[execution-unit.scala:104:14]
output io_fresp_bits_fflags_bits_uop_ctrl_fcn_dw, // @[execution-unit.scala:104:14]
output [2:0] io_fresp_bits_fflags_bits_uop_ctrl_csr_cmd, // @[execution-unit.scala:104:14]
output io_fresp_bits_fflags_bits_uop_ctrl_is_load, // @[execution-unit.scala:104:14]
output io_fresp_bits_fflags_bits_uop_ctrl_is_sta, // @[execution-unit.scala:104:14]
output io_fresp_bits_fflags_bits_uop_ctrl_is_std, // @[execution-unit.scala:104:14]
output [1:0] io_fresp_bits_fflags_bits_uop_iw_state, // @[execution-unit.scala:104:14]
output io_fresp_bits_fflags_bits_uop_iw_p1_poisoned, // @[execution-unit.scala:104:14]
output io_fresp_bits_fflags_bits_uop_iw_p2_poisoned, // @[execution-unit.scala:104:14]
output io_fresp_bits_fflags_bits_uop_is_br, // @[execution-unit.scala:104:14]
output io_fresp_bits_fflags_bits_uop_is_jalr, // @[execution-unit.scala:104:14]
output io_fresp_bits_fflags_bits_uop_is_jal, // @[execution-unit.scala:104:14]
output io_fresp_bits_fflags_bits_uop_is_sfb, // @[execution-unit.scala:104:14]
output [15:0] io_fresp_bits_fflags_bits_uop_br_mask, // @[execution-unit.scala:104:14]
output [3:0] io_fresp_bits_fflags_bits_uop_br_tag, // @[execution-unit.scala:104:14]
output [4:0] io_fresp_bits_fflags_bits_uop_ftq_idx, // @[execution-unit.scala:104:14]
output io_fresp_bits_fflags_bits_uop_edge_inst, // @[execution-unit.scala:104:14]
output [5:0] io_fresp_bits_fflags_bits_uop_pc_lob, // @[execution-unit.scala:104:14]
output io_fresp_bits_fflags_bits_uop_taken, // @[execution-unit.scala:104:14]
output [19:0] io_fresp_bits_fflags_bits_uop_imm_packed, // @[execution-unit.scala:104:14]
output [11:0] io_fresp_bits_fflags_bits_uop_csr_addr, // @[execution-unit.scala:104:14]
output [6:0] io_fresp_bits_fflags_bits_uop_rob_idx, // @[execution-unit.scala:104:14]
output [4:0] io_fresp_bits_fflags_bits_uop_ldq_idx, // @[execution-unit.scala:104:14]
output [4:0] io_fresp_bits_fflags_bits_uop_stq_idx, // @[execution-unit.scala:104:14]
output [1:0] io_fresp_bits_fflags_bits_uop_rxq_idx, // @[execution-unit.scala:104:14]
output [6:0] io_fresp_bits_fflags_bits_uop_pdst, // @[execution-unit.scala:104:14]
output [6:0] io_fresp_bits_fflags_bits_uop_prs1, // @[execution-unit.scala:104:14]
output [6:0] io_fresp_bits_fflags_bits_uop_prs2, // @[execution-unit.scala:104:14]
output [6:0] io_fresp_bits_fflags_bits_uop_prs3, // @[execution-unit.scala:104:14]
output [4:0] io_fresp_bits_fflags_bits_uop_ppred, // @[execution-unit.scala:104:14]
output io_fresp_bits_fflags_bits_uop_prs1_busy, // @[execution-unit.scala:104:14]
output io_fresp_bits_fflags_bits_uop_prs2_busy, // @[execution-unit.scala:104:14]
output io_fresp_bits_fflags_bits_uop_prs3_busy, // @[execution-unit.scala:104:14]
output io_fresp_bits_fflags_bits_uop_ppred_busy, // @[execution-unit.scala:104:14]
output [6:0] io_fresp_bits_fflags_bits_uop_stale_pdst, // @[execution-unit.scala:104:14]
output io_fresp_bits_fflags_bits_uop_exception, // @[execution-unit.scala:104:14]
output [63:0] io_fresp_bits_fflags_bits_uop_exc_cause, // @[execution-unit.scala:104:14]
output io_fresp_bits_fflags_bits_uop_bypassable, // @[execution-unit.scala:104:14]
output [4:0] io_fresp_bits_fflags_bits_uop_mem_cmd, // @[execution-unit.scala:104:14]
output [1:0] io_fresp_bits_fflags_bits_uop_mem_size, // @[execution-unit.scala:104:14]
output io_fresp_bits_fflags_bits_uop_mem_signed, // @[execution-unit.scala:104:14]
output io_fresp_bits_fflags_bits_uop_is_fence, // @[execution-unit.scala:104:14]
output io_fresp_bits_fflags_bits_uop_is_fencei, // @[execution-unit.scala:104:14]
output io_fresp_bits_fflags_bits_uop_is_amo, // @[execution-unit.scala:104:14]
output io_fresp_bits_fflags_bits_uop_uses_ldq, // @[execution-unit.scala:104:14]
output io_fresp_bits_fflags_bits_uop_uses_stq, // @[execution-unit.scala:104:14]
output io_fresp_bits_fflags_bits_uop_is_sys_pc2epc, // @[execution-unit.scala:104:14]
output io_fresp_bits_fflags_bits_uop_is_unique, // @[execution-unit.scala:104:14]
output io_fresp_bits_fflags_bits_uop_flush_on_commit, // @[execution-unit.scala:104:14]
output io_fresp_bits_fflags_bits_uop_ldst_is_rs1, // @[execution-unit.scala:104:14]
output [5:0] io_fresp_bits_fflags_bits_uop_ldst, // @[execution-unit.scala:104:14]
output [5:0] io_fresp_bits_fflags_bits_uop_lrs1, // @[execution-unit.scala:104:14]
output [5:0] io_fresp_bits_fflags_bits_uop_lrs2, // @[execution-unit.scala:104:14]
output [5:0] io_fresp_bits_fflags_bits_uop_lrs3, // @[execution-unit.scala:104:14]
output io_fresp_bits_fflags_bits_uop_ldst_val, // @[execution-unit.scala:104:14]
output [1:0] io_fresp_bits_fflags_bits_uop_dst_rtype, // @[execution-unit.scala:104:14]
output [1:0] io_fresp_bits_fflags_bits_uop_lrs1_rtype, // @[execution-unit.scala:104:14]
output [1:0] io_fresp_bits_fflags_bits_uop_lrs2_rtype, // @[execution-unit.scala:104:14]
output io_fresp_bits_fflags_bits_uop_frs3_en, // @[execution-unit.scala:104:14]
output io_fresp_bits_fflags_bits_uop_fp_val, // @[execution-unit.scala:104:14]
output io_fresp_bits_fflags_bits_uop_fp_single, // @[execution-unit.scala:104:14]
output io_fresp_bits_fflags_bits_uop_xcpt_pf_if, // @[execution-unit.scala:104:14]
output io_fresp_bits_fflags_bits_uop_xcpt_ae_if, // @[execution-unit.scala:104:14]
output io_fresp_bits_fflags_bits_uop_xcpt_ma_if, // @[execution-unit.scala:104:14]
output io_fresp_bits_fflags_bits_uop_bp_debug_if, // @[execution-unit.scala:104:14]
output io_fresp_bits_fflags_bits_uop_bp_xcpt_if, // @[execution-unit.scala:104:14]
output [1:0] io_fresp_bits_fflags_bits_uop_debug_fsrc, // @[execution-unit.scala:104:14]
output [1:0] io_fresp_bits_fflags_bits_uop_debug_tsrc, // @[execution-unit.scala:104:14]
output [4:0] io_fresp_bits_fflags_bits_flags, // @[execution-unit.scala:104:14]
input io_ll_iresp_ready, // @[execution-unit.scala:104:14]
output io_ll_iresp_valid, // @[execution-unit.scala:104:14]
output [6:0] io_ll_iresp_bits_uop_uopc, // @[execution-unit.scala:104:14]
output [31:0] io_ll_iresp_bits_uop_inst, // @[execution-unit.scala:104:14]
output [31:0] io_ll_iresp_bits_uop_debug_inst, // @[execution-unit.scala:104:14]
output io_ll_iresp_bits_uop_is_rvc, // @[execution-unit.scala:104:14]
output [39:0] io_ll_iresp_bits_uop_debug_pc, // @[execution-unit.scala:104:14]
output [2:0] io_ll_iresp_bits_uop_iq_type, // @[execution-unit.scala:104:14]
output [9:0] io_ll_iresp_bits_uop_fu_code, // @[execution-unit.scala:104:14]
output [3:0] io_ll_iresp_bits_uop_ctrl_br_type, // @[execution-unit.scala:104:14]
output [1:0] io_ll_iresp_bits_uop_ctrl_op1_sel, // @[execution-unit.scala:104:14]
output [2:0] io_ll_iresp_bits_uop_ctrl_op2_sel, // @[execution-unit.scala:104:14]
output [2:0] io_ll_iresp_bits_uop_ctrl_imm_sel, // @[execution-unit.scala:104:14]
output [4:0] io_ll_iresp_bits_uop_ctrl_op_fcn, // @[execution-unit.scala:104:14]
output io_ll_iresp_bits_uop_ctrl_fcn_dw, // @[execution-unit.scala:104:14]
output [2:0] io_ll_iresp_bits_uop_ctrl_csr_cmd, // @[execution-unit.scala:104:14]
output io_ll_iresp_bits_uop_ctrl_is_load, // @[execution-unit.scala:104:14]
output io_ll_iresp_bits_uop_ctrl_is_sta, // @[execution-unit.scala:104:14]
output io_ll_iresp_bits_uop_ctrl_is_std, // @[execution-unit.scala:104:14]
output [1:0] io_ll_iresp_bits_uop_iw_state, // @[execution-unit.scala:104:14]
output io_ll_iresp_bits_uop_iw_p1_poisoned, // @[execution-unit.scala:104:14]
output io_ll_iresp_bits_uop_iw_p2_poisoned, // @[execution-unit.scala:104:14]
output io_ll_iresp_bits_uop_is_br, // @[execution-unit.scala:104:14]
output io_ll_iresp_bits_uop_is_jalr, // @[execution-unit.scala:104:14]
output io_ll_iresp_bits_uop_is_jal, // @[execution-unit.scala:104:14]
output io_ll_iresp_bits_uop_is_sfb, // @[execution-unit.scala:104:14]
output [15:0] io_ll_iresp_bits_uop_br_mask, // @[execution-unit.scala:104:14]
output [3:0] io_ll_iresp_bits_uop_br_tag, // @[execution-unit.scala:104:14]
output [4:0] io_ll_iresp_bits_uop_ftq_idx, // @[execution-unit.scala:104:14]
output io_ll_iresp_bits_uop_edge_inst, // @[execution-unit.scala:104:14]
output [5:0] io_ll_iresp_bits_uop_pc_lob, // @[execution-unit.scala:104:14]
output io_ll_iresp_bits_uop_taken, // @[execution-unit.scala:104:14]
output [19:0] io_ll_iresp_bits_uop_imm_packed, // @[execution-unit.scala:104:14]
output [11:0] io_ll_iresp_bits_uop_csr_addr, // @[execution-unit.scala:104:14]
output [6:0] io_ll_iresp_bits_uop_rob_idx, // @[execution-unit.scala:104:14]
output [4:0] io_ll_iresp_bits_uop_ldq_idx, // @[execution-unit.scala:104:14]
output [4:0] io_ll_iresp_bits_uop_stq_idx, // @[execution-unit.scala:104:14]
output [1:0] io_ll_iresp_bits_uop_rxq_idx, // @[execution-unit.scala:104:14]
output [6:0] io_ll_iresp_bits_uop_pdst, // @[execution-unit.scala:104:14]
output [6:0] io_ll_iresp_bits_uop_prs1, // @[execution-unit.scala:104:14]
output [6:0] io_ll_iresp_bits_uop_prs2, // @[execution-unit.scala:104:14]
output [6:0] io_ll_iresp_bits_uop_prs3, // @[execution-unit.scala:104:14]
output [4:0] io_ll_iresp_bits_uop_ppred, // @[execution-unit.scala:104:14]
output io_ll_iresp_bits_uop_prs1_busy, // @[execution-unit.scala:104:14]
output io_ll_iresp_bits_uop_prs2_busy, // @[execution-unit.scala:104:14]
output io_ll_iresp_bits_uop_prs3_busy, // @[execution-unit.scala:104:14]
output io_ll_iresp_bits_uop_ppred_busy, // @[execution-unit.scala:104:14]
output [6:0] io_ll_iresp_bits_uop_stale_pdst, // @[execution-unit.scala:104:14]
output io_ll_iresp_bits_uop_exception, // @[execution-unit.scala:104:14]
output [63:0] io_ll_iresp_bits_uop_exc_cause, // @[execution-unit.scala:104:14]
output io_ll_iresp_bits_uop_bypassable, // @[execution-unit.scala:104:14]
output [4:0] io_ll_iresp_bits_uop_mem_cmd, // @[execution-unit.scala:104:14]
output [1:0] io_ll_iresp_bits_uop_mem_size, // @[execution-unit.scala:104:14]
output io_ll_iresp_bits_uop_mem_signed, // @[execution-unit.scala:104:14]
output io_ll_iresp_bits_uop_is_fence, // @[execution-unit.scala:104:14]
output io_ll_iresp_bits_uop_is_fencei, // @[execution-unit.scala:104:14]
output io_ll_iresp_bits_uop_is_amo, // @[execution-unit.scala:104:14]
output io_ll_iresp_bits_uop_uses_ldq, // @[execution-unit.scala:104:14]
output io_ll_iresp_bits_uop_uses_stq, // @[execution-unit.scala:104:14]
output io_ll_iresp_bits_uop_is_sys_pc2epc, // @[execution-unit.scala:104:14]
output io_ll_iresp_bits_uop_is_unique, // @[execution-unit.scala:104:14]
output io_ll_iresp_bits_uop_flush_on_commit, // @[execution-unit.scala:104:14]
output io_ll_iresp_bits_uop_ldst_is_rs1, // @[execution-unit.scala:104:14]
output [5:0] io_ll_iresp_bits_uop_ldst, // @[execution-unit.scala:104:14]
output [5:0] io_ll_iresp_bits_uop_lrs1, // @[execution-unit.scala:104:14]
output [5:0] io_ll_iresp_bits_uop_lrs2, // @[execution-unit.scala:104:14]
output [5:0] io_ll_iresp_bits_uop_lrs3, // @[execution-unit.scala:104:14]
output io_ll_iresp_bits_uop_ldst_val, // @[execution-unit.scala:104:14]
output [1:0] io_ll_iresp_bits_uop_dst_rtype, // @[execution-unit.scala:104:14]
output [1:0] io_ll_iresp_bits_uop_lrs1_rtype, // @[execution-unit.scala:104:14]
output [1:0] io_ll_iresp_bits_uop_lrs2_rtype, // @[execution-unit.scala:104:14]
output io_ll_iresp_bits_uop_frs3_en, // @[execution-unit.scala:104:14]
output io_ll_iresp_bits_uop_fp_val, // @[execution-unit.scala:104:14]
output io_ll_iresp_bits_uop_fp_single, // @[execution-unit.scala:104:14]
output io_ll_iresp_bits_uop_xcpt_pf_if, // @[execution-unit.scala:104:14]
output io_ll_iresp_bits_uop_xcpt_ae_if, // @[execution-unit.scala:104:14]
output io_ll_iresp_bits_uop_xcpt_ma_if, // @[execution-unit.scala:104:14]
output io_ll_iresp_bits_uop_bp_debug_if, // @[execution-unit.scala:104:14]
output io_ll_iresp_bits_uop_bp_xcpt_if, // @[execution-unit.scala:104:14]
output [1:0] io_ll_iresp_bits_uop_debug_fsrc, // @[execution-unit.scala:104:14]
output [1:0] io_ll_iresp_bits_uop_debug_tsrc, // @[execution-unit.scala:104:14]
output [64:0] io_ll_iresp_bits_data, // @[execution-unit.scala:104:14]
output io_ll_iresp_bits_predicated, // @[execution-unit.scala:104:14]
output io_ll_iresp_bits_fflags_valid, // @[execution-unit.scala:104:14]
output [6:0] io_ll_iresp_bits_fflags_bits_uop_uopc, // @[execution-unit.scala:104:14]
output [31:0] io_ll_iresp_bits_fflags_bits_uop_inst, // @[execution-unit.scala:104:14]
output [31:0] io_ll_iresp_bits_fflags_bits_uop_debug_inst, // @[execution-unit.scala:104:14]
output io_ll_iresp_bits_fflags_bits_uop_is_rvc, // @[execution-unit.scala:104:14]
output [39:0] io_ll_iresp_bits_fflags_bits_uop_debug_pc, // @[execution-unit.scala:104:14]
output [2:0] io_ll_iresp_bits_fflags_bits_uop_iq_type, // @[execution-unit.scala:104:14]
output [9:0] io_ll_iresp_bits_fflags_bits_uop_fu_code, // @[execution-unit.scala:104:14]
output [3:0] io_ll_iresp_bits_fflags_bits_uop_ctrl_br_type, // @[execution-unit.scala:104:14]
output [1:0] io_ll_iresp_bits_fflags_bits_uop_ctrl_op1_sel, // @[execution-unit.scala:104:14]
output [2:0] io_ll_iresp_bits_fflags_bits_uop_ctrl_op2_sel, // @[execution-unit.scala:104:14]
output [2:0] io_ll_iresp_bits_fflags_bits_uop_ctrl_imm_sel, // @[execution-unit.scala:104:14]
output [4:0] io_ll_iresp_bits_fflags_bits_uop_ctrl_op_fcn, // @[execution-unit.scala:104:14]
output io_ll_iresp_bits_fflags_bits_uop_ctrl_fcn_dw, // @[execution-unit.scala:104:14]
output [2:0] io_ll_iresp_bits_fflags_bits_uop_ctrl_csr_cmd, // @[execution-unit.scala:104:14]
output io_ll_iresp_bits_fflags_bits_uop_ctrl_is_load, // @[execution-unit.scala:104:14]
output io_ll_iresp_bits_fflags_bits_uop_ctrl_is_sta, // @[execution-unit.scala:104:14]
output io_ll_iresp_bits_fflags_bits_uop_ctrl_is_std, // @[execution-unit.scala:104:14]
output [1:0] io_ll_iresp_bits_fflags_bits_uop_iw_state, // @[execution-unit.scala:104:14]
output io_ll_iresp_bits_fflags_bits_uop_iw_p1_poisoned, // @[execution-unit.scala:104:14]
output io_ll_iresp_bits_fflags_bits_uop_iw_p2_poisoned, // @[execution-unit.scala:104:14]
output io_ll_iresp_bits_fflags_bits_uop_is_br, // @[execution-unit.scala:104:14]
output io_ll_iresp_bits_fflags_bits_uop_is_jalr, // @[execution-unit.scala:104:14]
output io_ll_iresp_bits_fflags_bits_uop_is_jal, // @[execution-unit.scala:104:14]
output io_ll_iresp_bits_fflags_bits_uop_is_sfb, // @[execution-unit.scala:104:14]
output [15:0] io_ll_iresp_bits_fflags_bits_uop_br_mask, // @[execution-unit.scala:104:14]
output [3:0] io_ll_iresp_bits_fflags_bits_uop_br_tag, // @[execution-unit.scala:104:14]
output [4:0] io_ll_iresp_bits_fflags_bits_uop_ftq_idx, // @[execution-unit.scala:104:14]
output io_ll_iresp_bits_fflags_bits_uop_edge_inst, // @[execution-unit.scala:104:14]
output [5:0] io_ll_iresp_bits_fflags_bits_uop_pc_lob, // @[execution-unit.scala:104:14]
output io_ll_iresp_bits_fflags_bits_uop_taken, // @[execution-unit.scala:104:14]
output [19:0] io_ll_iresp_bits_fflags_bits_uop_imm_packed, // @[execution-unit.scala:104:14]
output [11:0] io_ll_iresp_bits_fflags_bits_uop_csr_addr, // @[execution-unit.scala:104:14]
output [6:0] io_ll_iresp_bits_fflags_bits_uop_rob_idx, // @[execution-unit.scala:104:14]
output [4:0] io_ll_iresp_bits_fflags_bits_uop_ldq_idx, // @[execution-unit.scala:104:14]
output [4:0] io_ll_iresp_bits_fflags_bits_uop_stq_idx, // @[execution-unit.scala:104:14]
output [1:0] io_ll_iresp_bits_fflags_bits_uop_rxq_idx, // @[execution-unit.scala:104:14]
output [6:0] io_ll_iresp_bits_fflags_bits_uop_pdst, // @[execution-unit.scala:104:14]
output [6:0] io_ll_iresp_bits_fflags_bits_uop_prs1, // @[execution-unit.scala:104:14]
output [6:0] io_ll_iresp_bits_fflags_bits_uop_prs2, // @[execution-unit.scala:104:14]
output [6:0] io_ll_iresp_bits_fflags_bits_uop_prs3, // @[execution-unit.scala:104:14]
output [4:0] io_ll_iresp_bits_fflags_bits_uop_ppred, // @[execution-unit.scala:104:14]
output io_ll_iresp_bits_fflags_bits_uop_prs1_busy, // @[execution-unit.scala:104:14]
output io_ll_iresp_bits_fflags_bits_uop_prs2_busy, // @[execution-unit.scala:104:14]
output io_ll_iresp_bits_fflags_bits_uop_prs3_busy, // @[execution-unit.scala:104:14]
output io_ll_iresp_bits_fflags_bits_uop_ppred_busy, // @[execution-unit.scala:104:14]
output [6:0] io_ll_iresp_bits_fflags_bits_uop_stale_pdst, // @[execution-unit.scala:104:14]
output io_ll_iresp_bits_fflags_bits_uop_exception, // @[execution-unit.scala:104:14]
output [63:0] io_ll_iresp_bits_fflags_bits_uop_exc_cause, // @[execution-unit.scala:104:14]
output io_ll_iresp_bits_fflags_bits_uop_bypassable, // @[execution-unit.scala:104:14]
output [4:0] io_ll_iresp_bits_fflags_bits_uop_mem_cmd, // @[execution-unit.scala:104:14]
output [1:0] io_ll_iresp_bits_fflags_bits_uop_mem_size, // @[execution-unit.scala:104:14]
output io_ll_iresp_bits_fflags_bits_uop_mem_signed, // @[execution-unit.scala:104:14]
output io_ll_iresp_bits_fflags_bits_uop_is_fence, // @[execution-unit.scala:104:14]
output io_ll_iresp_bits_fflags_bits_uop_is_fencei, // @[execution-unit.scala:104:14]
output io_ll_iresp_bits_fflags_bits_uop_is_amo, // @[execution-unit.scala:104:14]
output io_ll_iresp_bits_fflags_bits_uop_uses_ldq, // @[execution-unit.scala:104:14]
output io_ll_iresp_bits_fflags_bits_uop_uses_stq, // @[execution-unit.scala:104:14]
output io_ll_iresp_bits_fflags_bits_uop_is_sys_pc2epc, // @[execution-unit.scala:104:14]
output io_ll_iresp_bits_fflags_bits_uop_is_unique, // @[execution-unit.scala:104:14]
output io_ll_iresp_bits_fflags_bits_uop_flush_on_commit, // @[execution-unit.scala:104:14]
output io_ll_iresp_bits_fflags_bits_uop_ldst_is_rs1, // @[execution-unit.scala:104:14]
output [5:0] io_ll_iresp_bits_fflags_bits_uop_ldst, // @[execution-unit.scala:104:14]
output [5:0] io_ll_iresp_bits_fflags_bits_uop_lrs1, // @[execution-unit.scala:104:14]
output [5:0] io_ll_iresp_bits_fflags_bits_uop_lrs2, // @[execution-unit.scala:104:14]
output [5:0] io_ll_iresp_bits_fflags_bits_uop_lrs3, // @[execution-unit.scala:104:14]
output io_ll_iresp_bits_fflags_bits_uop_ldst_val, // @[execution-unit.scala:104:14]
output [1:0] io_ll_iresp_bits_fflags_bits_uop_dst_rtype, // @[execution-unit.scala:104:14]
output [1:0] io_ll_iresp_bits_fflags_bits_uop_lrs1_rtype, // @[execution-unit.scala:104:14]
output [1:0] io_ll_iresp_bits_fflags_bits_uop_lrs2_rtype, // @[execution-unit.scala:104:14]
output io_ll_iresp_bits_fflags_bits_uop_frs3_en, // @[execution-unit.scala:104:14]
output io_ll_iresp_bits_fflags_bits_uop_fp_val, // @[execution-unit.scala:104:14]
output io_ll_iresp_bits_fflags_bits_uop_fp_single, // @[execution-unit.scala:104:14]
output io_ll_iresp_bits_fflags_bits_uop_xcpt_pf_if, // @[execution-unit.scala:104:14]
output io_ll_iresp_bits_fflags_bits_uop_xcpt_ae_if, // @[execution-unit.scala:104:14]
output io_ll_iresp_bits_fflags_bits_uop_xcpt_ma_if, // @[execution-unit.scala:104:14]
output io_ll_iresp_bits_fflags_bits_uop_bp_debug_if, // @[execution-unit.scala:104:14]
output io_ll_iresp_bits_fflags_bits_uop_bp_xcpt_if, // @[execution-unit.scala:104:14]
output [1:0] io_ll_iresp_bits_fflags_bits_uop_debug_fsrc, // @[execution-unit.scala:104:14]
output [1:0] io_ll_iresp_bits_fflags_bits_uop_debug_tsrc, // @[execution-unit.scala:104:14]
output [4:0] io_ll_iresp_bits_fflags_bits_flags, // @[execution-unit.scala:104:14]
input [15:0] io_brupdate_b1_resolve_mask, // @[execution-unit.scala:104:14]
input [15:0] io_brupdate_b1_mispredict_mask, // @[execution-unit.scala:104:14]
input [6:0] io_brupdate_b2_uop_uopc, // @[execution-unit.scala:104:14]
input [31:0] io_brupdate_b2_uop_inst, // @[execution-unit.scala:104:14]
input [31:0] io_brupdate_b2_uop_debug_inst, // @[execution-unit.scala:104:14]
input io_brupdate_b2_uop_is_rvc, // @[execution-unit.scala:104:14]
input [39:0] io_brupdate_b2_uop_debug_pc, // @[execution-unit.scala:104:14]
input [2:0] io_brupdate_b2_uop_iq_type, // @[execution-unit.scala:104:14]
input [9:0] io_brupdate_b2_uop_fu_code, // @[execution-unit.scala:104:14]
input [3:0] io_brupdate_b2_uop_ctrl_br_type, // @[execution-unit.scala:104:14]
input [1:0] io_brupdate_b2_uop_ctrl_op1_sel, // @[execution-unit.scala:104:14]
input [2:0] io_brupdate_b2_uop_ctrl_op2_sel, // @[execution-unit.scala:104:14]
input [2:0] io_brupdate_b2_uop_ctrl_imm_sel, // @[execution-unit.scala:104:14]
input [4:0] io_brupdate_b2_uop_ctrl_op_fcn, // @[execution-unit.scala:104:14]
input io_brupdate_b2_uop_ctrl_fcn_dw, // @[execution-unit.scala:104:14]
input [2:0] io_brupdate_b2_uop_ctrl_csr_cmd, // @[execution-unit.scala:104:14]
input io_brupdate_b2_uop_ctrl_is_load, // @[execution-unit.scala:104:14]
input io_brupdate_b2_uop_ctrl_is_sta, // @[execution-unit.scala:104:14]
input io_brupdate_b2_uop_ctrl_is_std, // @[execution-unit.scala:104:14]
input [1:0] io_brupdate_b2_uop_iw_state, // @[execution-unit.scala:104:14]
input io_brupdate_b2_uop_iw_p1_poisoned, // @[execution-unit.scala:104:14]
input io_brupdate_b2_uop_iw_p2_poisoned, // @[execution-unit.scala:104:14]
input io_brupdate_b2_uop_is_br, // @[execution-unit.scala:104:14]
input io_brupdate_b2_uop_is_jalr, // @[execution-unit.scala:104:14]
input io_brupdate_b2_uop_is_jal, // @[execution-unit.scala:104:14]
input io_brupdate_b2_uop_is_sfb, // @[execution-unit.scala:104:14]
input [15:0] io_brupdate_b2_uop_br_mask, // @[execution-unit.scala:104:14]
input [3:0] io_brupdate_b2_uop_br_tag, // @[execution-unit.scala:104:14]
input [4:0] io_brupdate_b2_uop_ftq_idx, // @[execution-unit.scala:104:14]
input io_brupdate_b2_uop_edge_inst, // @[execution-unit.scala:104:14]
input [5:0] io_brupdate_b2_uop_pc_lob, // @[execution-unit.scala:104:14]
input io_brupdate_b2_uop_taken, // @[execution-unit.scala:104:14]
input [19:0] io_brupdate_b2_uop_imm_packed, // @[execution-unit.scala:104:14]
input [11:0] io_brupdate_b2_uop_csr_addr, // @[execution-unit.scala:104:14]
input [6:0] io_brupdate_b2_uop_rob_idx, // @[execution-unit.scala:104:14]
input [4:0] io_brupdate_b2_uop_ldq_idx, // @[execution-unit.scala:104:14]
input [4:0] io_brupdate_b2_uop_stq_idx, // @[execution-unit.scala:104:14]
input [1:0] io_brupdate_b2_uop_rxq_idx, // @[execution-unit.scala:104:14]
input [6:0] io_brupdate_b2_uop_pdst, // @[execution-unit.scala:104:14]
input [6:0] io_brupdate_b2_uop_prs1, // @[execution-unit.scala:104:14]
input [6:0] io_brupdate_b2_uop_prs2, // @[execution-unit.scala:104:14]
input [6:0] io_brupdate_b2_uop_prs3, // @[execution-unit.scala:104:14]
input [4:0] io_brupdate_b2_uop_ppred, // @[execution-unit.scala:104:14]
input io_brupdate_b2_uop_prs1_busy, // @[execution-unit.scala:104:14]
input io_brupdate_b2_uop_prs2_busy, // @[execution-unit.scala:104:14]
input io_brupdate_b2_uop_prs3_busy, // @[execution-unit.scala:104:14]
input io_brupdate_b2_uop_ppred_busy, // @[execution-unit.scala:104:14]
input [6:0] io_brupdate_b2_uop_stale_pdst, // @[execution-unit.scala:104:14]
input io_brupdate_b2_uop_exception, // @[execution-unit.scala:104:14]
input [63:0] io_brupdate_b2_uop_exc_cause, // @[execution-unit.scala:104:14]
input io_brupdate_b2_uop_bypassable, // @[execution-unit.scala:104:14]
input [4:0] io_brupdate_b2_uop_mem_cmd, // @[execution-unit.scala:104:14]
input [1:0] io_brupdate_b2_uop_mem_size, // @[execution-unit.scala:104:14]
input io_brupdate_b2_uop_mem_signed, // @[execution-unit.scala:104:14]
input io_brupdate_b2_uop_is_fence, // @[execution-unit.scala:104:14]
input io_brupdate_b2_uop_is_fencei, // @[execution-unit.scala:104:14]
input io_brupdate_b2_uop_is_amo, // @[execution-unit.scala:104:14]
input io_brupdate_b2_uop_uses_ldq, // @[execution-unit.scala:104:14]
input io_brupdate_b2_uop_uses_stq, // @[execution-unit.scala:104:14]
input io_brupdate_b2_uop_is_sys_pc2epc, // @[execution-unit.scala:104:14]
input io_brupdate_b2_uop_is_unique, // @[execution-unit.scala:104:14]
input io_brupdate_b2_uop_flush_on_commit, // @[execution-unit.scala:104:14]
input io_brupdate_b2_uop_ldst_is_rs1, // @[execution-unit.scala:104:14]
input [5:0] io_brupdate_b2_uop_ldst, // @[execution-unit.scala:104:14]
input [5:0] io_brupdate_b2_uop_lrs1, // @[execution-unit.scala:104:14]
input [5:0] io_brupdate_b2_uop_lrs2, // @[execution-unit.scala:104:14]
input [5:0] io_brupdate_b2_uop_lrs3, // @[execution-unit.scala:104:14]
input io_brupdate_b2_uop_ldst_val, // @[execution-unit.scala:104:14]
input [1:0] io_brupdate_b2_uop_dst_rtype, // @[execution-unit.scala:104:14]
input [1:0] io_brupdate_b2_uop_lrs1_rtype, // @[execution-unit.scala:104:14]
input [1:0] io_brupdate_b2_uop_lrs2_rtype, // @[execution-unit.scala:104:14]
input io_brupdate_b2_uop_frs3_en, // @[execution-unit.scala:104:14]
input io_brupdate_b2_uop_fp_val, // @[execution-unit.scala:104:14]
input io_brupdate_b2_uop_fp_single, // @[execution-unit.scala:104:14]
input io_brupdate_b2_uop_xcpt_pf_if, // @[execution-unit.scala:104:14]
input io_brupdate_b2_uop_xcpt_ae_if, // @[execution-unit.scala:104:14]
input io_brupdate_b2_uop_xcpt_ma_if, // @[execution-unit.scala:104:14]
input io_brupdate_b2_uop_bp_debug_if, // @[execution-unit.scala:104:14]
input io_brupdate_b2_uop_bp_xcpt_if, // @[execution-unit.scala:104:14]
input [1:0] io_brupdate_b2_uop_debug_fsrc, // @[execution-unit.scala:104:14]
input [1:0] io_brupdate_b2_uop_debug_tsrc, // @[execution-unit.scala:104:14]
input io_brupdate_b2_valid, // @[execution-unit.scala:104:14]
input io_brupdate_b2_mispredict, // @[execution-unit.scala:104:14]
input io_brupdate_b2_taken, // @[execution-unit.scala:104:14]
input [2:0] io_brupdate_b2_cfi_type, // @[execution-unit.scala:104:14]
input [1:0] io_brupdate_b2_pc_sel, // @[execution-unit.scala:104:14]
input [39:0] io_brupdate_b2_jalr_target, // @[execution-unit.scala:104:14]
input [20:0] io_brupdate_b2_target_offset, // @[execution-unit.scala:104:14]
input io_status_debug, // @[execution-unit.scala:104:14]
input io_status_cease, // @[execution-unit.scala:104:14]
input io_status_wfi, // @[execution-unit.scala:104:14]
input [1:0] io_status_dprv, // @[execution-unit.scala:104:14]
input io_status_dv, // @[execution-unit.scala:104:14]
input [1:0] io_status_prv, // @[execution-unit.scala:104:14]
input io_status_v, // @[execution-unit.scala:104:14]
input io_status_sd, // @[execution-unit.scala:104:14]
input io_status_mpv, // @[execution-unit.scala:104:14]
input io_status_gva, // @[execution-unit.scala:104:14]
input io_status_tsr, // @[execution-unit.scala:104:14]
input io_status_tw, // @[execution-unit.scala:104:14]
input io_status_tvm, // @[execution-unit.scala:104:14]
input io_status_mxr, // @[execution-unit.scala:104:14]
input io_status_sum, // @[execution-unit.scala:104:14]
input io_status_mprv, // @[execution-unit.scala:104:14]
input [1:0] io_status_fs, // @[execution-unit.scala:104:14]
input [1:0] io_status_mpp, // @[execution-unit.scala:104:14]
input io_status_spp, // @[execution-unit.scala:104:14]
input io_status_mpie, // @[execution-unit.scala:104:14]
input io_status_spie, // @[execution-unit.scala:104:14]
input io_status_mie, // @[execution-unit.scala:104:14]
input io_status_sie, // @[execution-unit.scala:104:14]
input [2:0] io_fcsr_rm // @[execution-unit.scala:104:14]
);
wire _resp_arb_io_in_0_ready; // @[execution-unit.scala:563:26]
wire _resp_arb_io_in_1_ready; // @[execution-unit.scala:563:26]
wire _fp_sdq_io_enq_ready; // @[execution-unit.scala:551:24]
wire _fp_sdq_io_deq_valid; // @[execution-unit.scala:551:24]
wire [6:0] _fp_sdq_io_deq_bits_uop_uopc; // @[execution-unit.scala:551:24]
wire [31:0] _fp_sdq_io_deq_bits_uop_inst; // @[execution-unit.scala:551:24]
wire [31:0] _fp_sdq_io_deq_bits_uop_debug_inst; // @[execution-unit.scala:551:24]
wire _fp_sdq_io_deq_bits_uop_is_rvc; // @[execution-unit.scala:551:24]
wire [39:0] _fp_sdq_io_deq_bits_uop_debug_pc; // @[execution-unit.scala:551:24]
wire [2:0] _fp_sdq_io_deq_bits_uop_iq_type; // @[execution-unit.scala:551:24]
wire [9:0] _fp_sdq_io_deq_bits_uop_fu_code; // @[execution-unit.scala:551:24]
wire [3:0] _fp_sdq_io_deq_bits_uop_ctrl_br_type; // @[execution-unit.scala:551:24]
wire [1:0] _fp_sdq_io_deq_bits_uop_ctrl_op1_sel; // @[execution-unit.scala:551:24]
wire [2:0] _fp_sdq_io_deq_bits_uop_ctrl_op2_sel; // @[execution-unit.scala:551:24]
wire [2:0] _fp_sdq_io_deq_bits_uop_ctrl_imm_sel; // @[execution-unit.scala:551:24]
wire [4:0] _fp_sdq_io_deq_bits_uop_ctrl_op_fcn; // @[execution-unit.scala:551:24]
wire _fp_sdq_io_deq_bits_uop_ctrl_fcn_dw; // @[execution-unit.scala:551:24]
wire [2:0] _fp_sdq_io_deq_bits_uop_ctrl_csr_cmd; // @[execution-unit.scala:551:24]
wire _fp_sdq_io_deq_bits_uop_ctrl_is_load; // @[execution-unit.scala:551:24]
wire _fp_sdq_io_deq_bits_uop_ctrl_is_sta; // @[execution-unit.scala:551:24]
wire _fp_sdq_io_deq_bits_uop_ctrl_is_std; // @[execution-unit.scala:551:24]
wire [1:0] _fp_sdq_io_deq_bits_uop_iw_state; // @[execution-unit.scala:551:24]
wire _fp_sdq_io_deq_bits_uop_iw_p1_poisoned; // @[execution-unit.scala:551:24]
wire _fp_sdq_io_deq_bits_uop_iw_p2_poisoned; // @[execution-unit.scala:551:24]
wire _fp_sdq_io_deq_bits_uop_is_br; // @[execution-unit.scala:551:24]
wire _fp_sdq_io_deq_bits_uop_is_jalr; // @[execution-unit.scala:551:24]
wire _fp_sdq_io_deq_bits_uop_is_jal; // @[execution-unit.scala:551:24]
wire _fp_sdq_io_deq_bits_uop_is_sfb; // @[execution-unit.scala:551:24]
wire [15:0] _fp_sdq_io_deq_bits_uop_br_mask; // @[execution-unit.scala:551:24]
wire [3:0] _fp_sdq_io_deq_bits_uop_br_tag; // @[execution-unit.scala:551:24]
wire [4:0] _fp_sdq_io_deq_bits_uop_ftq_idx; // @[execution-unit.scala:551:24]
wire _fp_sdq_io_deq_bits_uop_edge_inst; // @[execution-unit.scala:551:24]
wire [5:0] _fp_sdq_io_deq_bits_uop_pc_lob; // @[execution-unit.scala:551:24]
wire _fp_sdq_io_deq_bits_uop_taken; // @[execution-unit.scala:551:24]
wire [19:0] _fp_sdq_io_deq_bits_uop_imm_packed; // @[execution-unit.scala:551:24]
wire [11:0] _fp_sdq_io_deq_bits_uop_csr_addr; // @[execution-unit.scala:551:24]
wire [6:0] _fp_sdq_io_deq_bits_uop_rob_idx; // @[execution-unit.scala:551:24]
wire [4:0] _fp_sdq_io_deq_bits_uop_ldq_idx; // @[execution-unit.scala:551:24]
wire [4:0] _fp_sdq_io_deq_bits_uop_stq_idx; // @[execution-unit.scala:551:24]
wire [1:0] _fp_sdq_io_deq_bits_uop_rxq_idx; // @[execution-unit.scala:551:24]
wire [6:0] _fp_sdq_io_deq_bits_uop_pdst; // @[execution-unit.scala:551:24]
wire [6:0] _fp_sdq_io_deq_bits_uop_prs1; // @[execution-unit.scala:551:24]
wire [6:0] _fp_sdq_io_deq_bits_uop_prs2; // @[execution-unit.scala:551:24]
wire [6:0] _fp_sdq_io_deq_bits_uop_prs3; // @[execution-unit.scala:551:24]
wire [4:0] _fp_sdq_io_deq_bits_uop_ppred; // @[execution-unit.scala:551:24]
wire _fp_sdq_io_deq_bits_uop_prs1_busy; // @[execution-unit.scala:551:24]
wire _fp_sdq_io_deq_bits_uop_prs2_busy; // @[execution-unit.scala:551:24]
wire _fp_sdq_io_deq_bits_uop_prs3_busy; // @[execution-unit.scala:551:24]
wire _fp_sdq_io_deq_bits_uop_ppred_busy; // @[execution-unit.scala:551:24]
wire [6:0] _fp_sdq_io_deq_bits_uop_stale_pdst; // @[execution-unit.scala:551:24]
wire _fp_sdq_io_deq_bits_uop_exception; // @[execution-unit.scala:551:24]
wire [63:0] _fp_sdq_io_deq_bits_uop_exc_cause; // @[execution-unit.scala:551:24]
wire _fp_sdq_io_deq_bits_uop_bypassable; // @[execution-unit.scala:551:24]
wire [4:0] _fp_sdq_io_deq_bits_uop_mem_cmd; // @[execution-unit.scala:551:24]
wire [1:0] _fp_sdq_io_deq_bits_uop_mem_size; // @[execution-unit.scala:551:24]
wire _fp_sdq_io_deq_bits_uop_mem_signed; // @[execution-unit.scala:551:24]
wire _fp_sdq_io_deq_bits_uop_is_fence; // @[execution-unit.scala:551:24]
wire _fp_sdq_io_deq_bits_uop_is_fencei; // @[execution-unit.scala:551:24]
wire _fp_sdq_io_deq_bits_uop_is_amo; // @[execution-unit.scala:551:24]
wire _fp_sdq_io_deq_bits_uop_uses_ldq; // @[execution-unit.scala:551:24]
wire _fp_sdq_io_deq_bits_uop_uses_stq; // @[execution-unit.scala:551:24]
wire _fp_sdq_io_deq_bits_uop_is_sys_pc2epc; // @[execution-unit.scala:551:24]
wire _fp_sdq_io_deq_bits_uop_is_unique; // @[execution-unit.scala:551:24]
wire _fp_sdq_io_deq_bits_uop_flush_on_commit; // @[execution-unit.scala:551:24]
wire _fp_sdq_io_deq_bits_uop_ldst_is_rs1; // @[execution-unit.scala:551:24]
wire [5:0] _fp_sdq_io_deq_bits_uop_ldst; // @[execution-unit.scala:551:24]
wire [5:0] _fp_sdq_io_deq_bits_uop_lrs1; // @[execution-unit.scala:551:24]
wire [5:0] _fp_sdq_io_deq_bits_uop_lrs2; // @[execution-unit.scala:551:24]
wire [5:0] _fp_sdq_io_deq_bits_uop_lrs3; // @[execution-unit.scala:551:24]
wire _fp_sdq_io_deq_bits_uop_ldst_val; // @[execution-unit.scala:551:24]
wire [1:0] _fp_sdq_io_deq_bits_uop_dst_rtype; // @[execution-unit.scala:551:24]
wire [1:0] _fp_sdq_io_deq_bits_uop_lrs1_rtype; // @[execution-unit.scala:551:24]
wire [1:0] _fp_sdq_io_deq_bits_uop_lrs2_rtype; // @[execution-unit.scala:551:24]
wire _fp_sdq_io_deq_bits_uop_frs3_en; // @[execution-unit.scala:551:24]
wire _fp_sdq_io_deq_bits_uop_fp_val; // @[execution-unit.scala:551:24]
wire _fp_sdq_io_deq_bits_uop_fp_single; // @[execution-unit.scala:551:24]
wire _fp_sdq_io_deq_bits_uop_xcpt_pf_if; // @[execution-unit.scala:551:24]
wire _fp_sdq_io_deq_bits_uop_xcpt_ae_if; // @[execution-unit.scala:551:24]
wire _fp_sdq_io_deq_bits_uop_xcpt_ma_if; // @[execution-unit.scala:551:24]
wire _fp_sdq_io_deq_bits_uop_bp_debug_if; // @[execution-unit.scala:551:24]
wire _fp_sdq_io_deq_bits_uop_bp_xcpt_if; // @[execution-unit.scala:551:24]
wire [1:0] _fp_sdq_io_deq_bits_uop_debug_fsrc; // @[execution-unit.scala:551:24]
wire [1:0] _fp_sdq_io_deq_bits_uop_debug_tsrc; // @[execution-unit.scala:551:24]
wire [64:0] _fp_sdq_io_deq_bits_data; // @[execution-unit.scala:551:24]
wire _fp_sdq_io_deq_bits_predicated; // @[execution-unit.scala:551:24]
wire _fp_sdq_io_deq_bits_fflags_valid; // @[execution-unit.scala:551:24]
wire [6:0] _fp_sdq_io_deq_bits_fflags_bits_uop_uopc; // @[execution-unit.scala:551:24]
wire [31:0] _fp_sdq_io_deq_bits_fflags_bits_uop_inst; // @[execution-unit.scala:551:24]
wire [31:0] _fp_sdq_io_deq_bits_fflags_bits_uop_debug_inst; // @[execution-unit.scala:551:24]
wire _fp_sdq_io_deq_bits_fflags_bits_uop_is_rvc; // @[execution-unit.scala:551:24]
wire [39:0] _fp_sdq_io_deq_bits_fflags_bits_uop_debug_pc; // @[execution-unit.scala:551:24]
wire [2:0] _fp_sdq_io_deq_bits_fflags_bits_uop_iq_type; // @[execution-unit.scala:551:24]
wire [9:0] _fp_sdq_io_deq_bits_fflags_bits_uop_fu_code; // @[execution-unit.scala:551:24]
wire [3:0] _fp_sdq_io_deq_bits_fflags_bits_uop_ctrl_br_type; // @[execution-unit.scala:551:24]
wire [1:0] _fp_sdq_io_deq_bits_fflags_bits_uop_ctrl_op1_sel; // @[execution-unit.scala:551:24]
wire [2:0] _fp_sdq_io_deq_bits_fflags_bits_uop_ctrl_op2_sel; // @[execution-unit.scala:551:24]
wire [2:0] _fp_sdq_io_deq_bits_fflags_bits_uop_ctrl_imm_sel; // @[execution-unit.scala:551:24]
wire [4:0] _fp_sdq_io_deq_bits_fflags_bits_uop_ctrl_op_fcn; // @[execution-unit.scala:551:24]
wire _fp_sdq_io_deq_bits_fflags_bits_uop_ctrl_fcn_dw; // @[execution-unit.scala:551:24]
wire [2:0] _fp_sdq_io_deq_bits_fflags_bits_uop_ctrl_csr_cmd; // @[execution-unit.scala:551:24]
wire _fp_sdq_io_deq_bits_fflags_bits_uop_ctrl_is_load; // @[execution-unit.scala:551:24]
wire _fp_sdq_io_deq_bits_fflags_bits_uop_ctrl_is_sta; // @[execution-unit.scala:551:24]
wire _fp_sdq_io_deq_bits_fflags_bits_uop_ctrl_is_std; // @[execution-unit.scala:551:24]
wire [1:0] _fp_sdq_io_deq_bits_fflags_bits_uop_iw_state; // @[execution-unit.scala:551:24]
wire _fp_sdq_io_deq_bits_fflags_bits_uop_iw_p1_poisoned; // @[execution-unit.scala:551:24]
wire _fp_sdq_io_deq_bits_fflags_bits_uop_iw_p2_poisoned; // @[execution-unit.scala:551:24]
wire _fp_sdq_io_deq_bits_fflags_bits_uop_is_br; // @[execution-unit.scala:551:24]
wire _fp_sdq_io_deq_bits_fflags_bits_uop_is_jalr; // @[execution-unit.scala:551:24]
wire _fp_sdq_io_deq_bits_fflags_bits_uop_is_jal; // @[execution-unit.scala:551:24]
wire _fp_sdq_io_deq_bits_fflags_bits_uop_is_sfb; // @[execution-unit.scala:551:24]
wire [15:0] _fp_sdq_io_deq_bits_fflags_bits_uop_br_mask; // @[execution-unit.scala:551:24]
wire [3:0] _fp_sdq_io_deq_bits_fflags_bits_uop_br_tag; // @[execution-unit.scala:551:24]
wire [4:0] _fp_sdq_io_deq_bits_fflags_bits_uop_ftq_idx; // @[execution-unit.scala:551:24]
wire _fp_sdq_io_deq_bits_fflags_bits_uop_edge_inst; // @[execution-unit.scala:551:24]
wire [5:0] _fp_sdq_io_deq_bits_fflags_bits_uop_pc_lob; // @[execution-unit.scala:551:24]
wire _fp_sdq_io_deq_bits_fflags_bits_uop_taken; // @[execution-unit.scala:551:24]
wire [19:0] _fp_sdq_io_deq_bits_fflags_bits_uop_imm_packed; // @[execution-unit.scala:551:24]
wire [11:0] _fp_sdq_io_deq_bits_fflags_bits_uop_csr_addr; // @[execution-unit.scala:551:24]
wire [6:0] _fp_sdq_io_deq_bits_fflags_bits_uop_rob_idx; // @[execution-unit.scala:551:24]
wire [4:0] _fp_sdq_io_deq_bits_fflags_bits_uop_ldq_idx; // @[execution-unit.scala:551:24]
wire [4:0] _fp_sdq_io_deq_bits_fflags_bits_uop_stq_idx; // @[execution-unit.scala:551:24]
wire [1:0] _fp_sdq_io_deq_bits_fflags_bits_uop_rxq_idx; // @[execution-unit.scala:551:24]
wire [6:0] _fp_sdq_io_deq_bits_fflags_bits_uop_pdst; // @[execution-unit.scala:551:24]
wire [6:0] _fp_sdq_io_deq_bits_fflags_bits_uop_prs1; // @[execution-unit.scala:551:24]
wire [6:0] _fp_sdq_io_deq_bits_fflags_bits_uop_prs2; // @[execution-unit.scala:551:24]
wire [6:0] _fp_sdq_io_deq_bits_fflags_bits_uop_prs3; // @[execution-unit.scala:551:24]
wire [4:0] _fp_sdq_io_deq_bits_fflags_bits_uop_ppred; // @[execution-unit.scala:551:24]
wire _fp_sdq_io_deq_bits_fflags_bits_uop_prs1_busy; // @[execution-unit.scala:551:24]
wire _fp_sdq_io_deq_bits_fflags_bits_uop_prs2_busy; // @[execution-unit.scala:551:24]
wire _fp_sdq_io_deq_bits_fflags_bits_uop_prs3_busy; // @[execution-unit.scala:551:24]
wire _fp_sdq_io_deq_bits_fflags_bits_uop_ppred_busy; // @[execution-unit.scala:551:24]
wire [6:0] _fp_sdq_io_deq_bits_fflags_bits_uop_stale_pdst; // @[execution-unit.scala:551:24]
wire _fp_sdq_io_deq_bits_fflags_bits_uop_exception; // @[execution-unit.scala:551:24]
wire [63:0] _fp_sdq_io_deq_bits_fflags_bits_uop_exc_cause; // @[execution-unit.scala:551:24]
wire _fp_sdq_io_deq_bits_fflags_bits_uop_bypassable; // @[execution-unit.scala:551:24]
wire [4:0] _fp_sdq_io_deq_bits_fflags_bits_uop_mem_cmd; // @[execution-unit.scala:551:24]
wire [1:0] _fp_sdq_io_deq_bits_fflags_bits_uop_mem_size; // @[execution-unit.scala:551:24]
wire _fp_sdq_io_deq_bits_fflags_bits_uop_mem_signed; // @[execution-unit.scala:551:24]
wire _fp_sdq_io_deq_bits_fflags_bits_uop_is_fence; // @[execution-unit.scala:551:24]
wire _fp_sdq_io_deq_bits_fflags_bits_uop_is_fencei; // @[execution-unit.scala:551:24]
wire _fp_sdq_io_deq_bits_fflags_bits_uop_is_amo; // @[execution-unit.scala:551:24]
wire _fp_sdq_io_deq_bits_fflags_bits_uop_uses_ldq; // @[execution-unit.scala:551:24]
wire _fp_sdq_io_deq_bits_fflags_bits_uop_uses_stq; // @[execution-unit.scala:551:24]
wire _fp_sdq_io_deq_bits_fflags_bits_uop_is_sys_pc2epc; // @[execution-unit.scala:551:24]
wire _fp_sdq_io_deq_bits_fflags_bits_uop_is_unique; // @[execution-unit.scala:551:24]
wire _fp_sdq_io_deq_bits_fflags_bits_uop_flush_on_commit; // @[execution-unit.scala:551:24]
wire _fp_sdq_io_deq_bits_fflags_bits_uop_ldst_is_rs1; // @[execution-unit.scala:551:24]
wire [5:0] _fp_sdq_io_deq_bits_fflags_bits_uop_ldst; // @[execution-unit.scala:551:24]
wire [5:0] _fp_sdq_io_deq_bits_fflags_bits_uop_lrs1; // @[execution-unit.scala:551:24]
wire [5:0] _fp_sdq_io_deq_bits_fflags_bits_uop_lrs2; // @[execution-unit.scala:551:24]
wire [5:0] _fp_sdq_io_deq_bits_fflags_bits_uop_lrs3; // @[execution-unit.scala:551:24]
wire _fp_sdq_io_deq_bits_fflags_bits_uop_ldst_val; // @[execution-unit.scala:551:24]
wire [1:0] _fp_sdq_io_deq_bits_fflags_bits_uop_dst_rtype; // @[execution-unit.scala:551:24]
wire [1:0] _fp_sdq_io_deq_bits_fflags_bits_uop_lrs1_rtype; // @[execution-unit.scala:551:24]
wire [1:0] _fp_sdq_io_deq_bits_fflags_bits_uop_lrs2_rtype; // @[execution-unit.scala:551:24]
wire _fp_sdq_io_deq_bits_fflags_bits_uop_frs3_en; // @[execution-unit.scala:551:24]
wire _fp_sdq_io_deq_bits_fflags_bits_uop_fp_val; // @[execution-unit.scala:551:24]
wire _fp_sdq_io_deq_bits_fflags_bits_uop_fp_single; // @[execution-unit.scala:551:24]
wire _fp_sdq_io_deq_bits_fflags_bits_uop_xcpt_pf_if; // @[execution-unit.scala:551:24]
wire _fp_sdq_io_deq_bits_fflags_bits_uop_xcpt_ae_if; // @[execution-unit.scala:551:24]
wire _fp_sdq_io_deq_bits_fflags_bits_uop_xcpt_ma_if; // @[execution-unit.scala:551:24]
wire _fp_sdq_io_deq_bits_fflags_bits_uop_bp_debug_if; // @[execution-unit.scala:551:24]
wire _fp_sdq_io_deq_bits_fflags_bits_uop_bp_xcpt_if; // @[execution-unit.scala:551:24]
wire [1:0] _fp_sdq_io_deq_bits_fflags_bits_uop_debug_fsrc; // @[execution-unit.scala:551:24]
wire [1:0] _fp_sdq_io_deq_bits_fflags_bits_uop_debug_tsrc; // @[execution-unit.scala:551:24]
wire [4:0] _fp_sdq_io_deq_bits_fflags_bits_flags; // @[execution-unit.scala:551:24]
wire _fp_sdq_io_empty; // @[execution-unit.scala:551:24]
wire _queue_io_enq_ready; // @[execution-unit.scala:537:23]
wire _queue_io_deq_valid; // @[execution-unit.scala:537:23]
wire [6:0] _queue_io_deq_bits_uop_uopc; // @[execution-unit.scala:537:23]
wire [31:0] _queue_io_deq_bits_uop_inst; // @[execution-unit.scala:537:23]
wire [31:0] _queue_io_deq_bits_uop_debug_inst; // @[execution-unit.scala:537:23]
wire _queue_io_deq_bits_uop_is_rvc; // @[execution-unit.scala:537:23]
wire [39:0] _queue_io_deq_bits_uop_debug_pc; // @[execution-unit.scala:537:23]
wire [2:0] _queue_io_deq_bits_uop_iq_type; // @[execution-unit.scala:537:23]
wire [9:0] _queue_io_deq_bits_uop_fu_code; // @[execution-unit.scala:537:23]
wire [3:0] _queue_io_deq_bits_uop_ctrl_br_type; // @[execution-unit.scala:537:23]
wire [1:0] _queue_io_deq_bits_uop_ctrl_op1_sel; // @[execution-unit.scala:537:23]
wire [2:0] _queue_io_deq_bits_uop_ctrl_op2_sel; // @[execution-unit.scala:537:23]
wire [2:0] _queue_io_deq_bits_uop_ctrl_imm_sel; // @[execution-unit.scala:537:23]
wire [4:0] _queue_io_deq_bits_uop_ctrl_op_fcn; // @[execution-unit.scala:537:23]
wire _queue_io_deq_bits_uop_ctrl_fcn_dw; // @[execution-unit.scala:537:23]
wire [2:0] _queue_io_deq_bits_uop_ctrl_csr_cmd; // @[execution-unit.scala:537:23]
wire _queue_io_deq_bits_uop_ctrl_is_load; // @[execution-unit.scala:537:23]
wire _queue_io_deq_bits_uop_ctrl_is_sta; // @[execution-unit.scala:537:23]
wire _queue_io_deq_bits_uop_ctrl_is_std; // @[execution-unit.scala:537:23]
wire [1:0] _queue_io_deq_bits_uop_iw_state; // @[execution-unit.scala:537:23]
wire _queue_io_deq_bits_uop_iw_p1_poisoned; // @[execution-unit.scala:537:23]
wire _queue_io_deq_bits_uop_iw_p2_poisoned; // @[execution-unit.scala:537:23]
wire _queue_io_deq_bits_uop_is_br; // @[execution-unit.scala:537:23]
wire _queue_io_deq_bits_uop_is_jalr; // @[execution-unit.scala:537:23]
wire _queue_io_deq_bits_uop_is_jal; // @[execution-unit.scala:537:23]
wire _queue_io_deq_bits_uop_is_sfb; // @[execution-unit.scala:537:23]
wire [15:0] _queue_io_deq_bits_uop_br_mask; // @[execution-unit.scala:537:23]
wire [3:0] _queue_io_deq_bits_uop_br_tag; // @[execution-unit.scala:537:23]
wire [4:0] _queue_io_deq_bits_uop_ftq_idx; // @[execution-unit.scala:537:23]
wire _queue_io_deq_bits_uop_edge_inst; // @[execution-unit.scala:537:23]
wire [5:0] _queue_io_deq_bits_uop_pc_lob; // @[execution-unit.scala:537:23]
wire _queue_io_deq_bits_uop_taken; // @[execution-unit.scala:537:23]
wire [19:0] _queue_io_deq_bits_uop_imm_packed; // @[execution-unit.scala:537:23]
wire [11:0] _queue_io_deq_bits_uop_csr_addr; // @[execution-unit.scala:537:23]
wire [6:0] _queue_io_deq_bits_uop_rob_idx; // @[execution-unit.scala:537:23]
wire [4:0] _queue_io_deq_bits_uop_ldq_idx; // @[execution-unit.scala:537:23]
wire [4:0] _queue_io_deq_bits_uop_stq_idx; // @[execution-unit.scala:537:23]
wire [1:0] _queue_io_deq_bits_uop_rxq_idx; // @[execution-unit.scala:537:23]
wire [6:0] _queue_io_deq_bits_uop_pdst; // @[execution-unit.scala:537:23]
wire [6:0] _queue_io_deq_bits_uop_prs1; // @[execution-unit.scala:537:23]
wire [6:0] _queue_io_deq_bits_uop_prs2; // @[execution-unit.scala:537:23]
wire [6:0] _queue_io_deq_bits_uop_prs3; // @[execution-unit.scala:537:23]
wire [4:0] _queue_io_deq_bits_uop_ppred; // @[execution-unit.scala:537:23]
wire _queue_io_deq_bits_uop_prs1_busy; // @[execution-unit.scala:537:23]
wire _queue_io_deq_bits_uop_prs2_busy; // @[execution-unit.scala:537:23]
wire _queue_io_deq_bits_uop_prs3_busy; // @[execution-unit.scala:537:23]
wire _queue_io_deq_bits_uop_ppred_busy; // @[execution-unit.scala:537:23]
wire [6:0] _queue_io_deq_bits_uop_stale_pdst; // @[execution-unit.scala:537:23]
wire _queue_io_deq_bits_uop_exception; // @[execution-unit.scala:537:23]
wire [63:0] _queue_io_deq_bits_uop_exc_cause; // @[execution-unit.scala:537:23]
wire _queue_io_deq_bits_uop_bypassable; // @[execution-unit.scala:537:23]
wire [4:0] _queue_io_deq_bits_uop_mem_cmd; // @[execution-unit.scala:537:23]
wire [1:0] _queue_io_deq_bits_uop_mem_size; // @[execution-unit.scala:537:23]
wire _queue_io_deq_bits_uop_mem_signed; // @[execution-unit.scala:537:23]
wire _queue_io_deq_bits_uop_is_fence; // @[execution-unit.scala:537:23]
wire _queue_io_deq_bits_uop_is_fencei; // @[execution-unit.scala:537:23]
wire _queue_io_deq_bits_uop_is_amo; // @[execution-unit.scala:537:23]
wire _queue_io_deq_bits_uop_uses_ldq; // @[execution-unit.scala:537:23]
wire _queue_io_deq_bits_uop_uses_stq; // @[execution-unit.scala:537:23]
wire _queue_io_deq_bits_uop_is_sys_pc2epc; // @[execution-unit.scala:537:23]
wire _queue_io_deq_bits_uop_is_unique; // @[execution-unit.scala:537:23]
wire _queue_io_deq_bits_uop_flush_on_commit; // @[execution-unit.scala:537:23]
wire _queue_io_deq_bits_uop_ldst_is_rs1; // @[execution-unit.scala:537:23]
wire [5:0] _queue_io_deq_bits_uop_ldst; // @[execution-unit.scala:537:23]
wire [5:0] _queue_io_deq_bits_uop_lrs1; // @[execution-unit.scala:537:23]
wire [5:0] _queue_io_deq_bits_uop_lrs2; // @[execution-unit.scala:537:23]
wire [5:0] _queue_io_deq_bits_uop_lrs3; // @[execution-unit.scala:537:23]
wire _queue_io_deq_bits_uop_ldst_val; // @[execution-unit.scala:537:23]
wire [1:0] _queue_io_deq_bits_uop_dst_rtype; // @[execution-unit.scala:537:23]
wire [1:0] _queue_io_deq_bits_uop_lrs1_rtype; // @[execution-unit.scala:537:23]
wire [1:0] _queue_io_deq_bits_uop_lrs2_rtype; // @[execution-unit.scala:537:23]
wire _queue_io_deq_bits_uop_frs3_en; // @[execution-unit.scala:537:23]
wire _queue_io_deq_bits_uop_fp_val; // @[execution-unit.scala:537:23]
wire _queue_io_deq_bits_uop_fp_single; // @[execution-unit.scala:537:23]
wire _queue_io_deq_bits_uop_xcpt_pf_if; // @[execution-unit.scala:537:23]
wire _queue_io_deq_bits_uop_xcpt_ae_if; // @[execution-unit.scala:537:23]
wire _queue_io_deq_bits_uop_xcpt_ma_if; // @[execution-unit.scala:537:23]
wire _queue_io_deq_bits_uop_bp_debug_if; // @[execution-unit.scala:537:23]
wire _queue_io_deq_bits_uop_bp_xcpt_if; // @[execution-unit.scala:537:23]
wire [1:0] _queue_io_deq_bits_uop_debug_fsrc; // @[execution-unit.scala:537:23]
wire [1:0] _queue_io_deq_bits_uop_debug_tsrc; // @[execution-unit.scala:537:23]
wire [64:0] _queue_io_deq_bits_data; // @[execution-unit.scala:537:23]
wire _queue_io_deq_bits_predicated; // @[execution-unit.scala:537:23]
wire _queue_io_deq_bits_fflags_valid; // @[execution-unit.scala:537:23]
wire [6:0] _queue_io_deq_bits_fflags_bits_uop_uopc; // @[execution-unit.scala:537:23]
wire [31:0] _queue_io_deq_bits_fflags_bits_uop_inst; // @[execution-unit.scala:537:23]
wire [31:0] _queue_io_deq_bits_fflags_bits_uop_debug_inst; // @[execution-unit.scala:537:23]
wire _queue_io_deq_bits_fflags_bits_uop_is_rvc; // @[execution-unit.scala:537:23]
wire [39:0] _queue_io_deq_bits_fflags_bits_uop_debug_pc; // @[execution-unit.scala:537:23]
wire [2:0] _queue_io_deq_bits_fflags_bits_uop_iq_type; // @[execution-unit.scala:537:23]
wire [9:0] _queue_io_deq_bits_fflags_bits_uop_fu_code; // @[execution-unit.scala:537:23]
wire [3:0] _queue_io_deq_bits_fflags_bits_uop_ctrl_br_type; // @[execution-unit.scala:537:23]
wire [1:0] _queue_io_deq_bits_fflags_bits_uop_ctrl_op1_sel; // @[execution-unit.scala:537:23]
wire [2:0] _queue_io_deq_bits_fflags_bits_uop_ctrl_op2_sel; // @[execution-unit.scala:537:23]
wire [2:0] _queue_io_deq_bits_fflags_bits_uop_ctrl_imm_sel; // @[execution-unit.scala:537:23]
wire [4:0] _queue_io_deq_bits_fflags_bits_uop_ctrl_op_fcn; // @[execution-unit.scala:537:23]
wire _queue_io_deq_bits_fflags_bits_uop_ctrl_fcn_dw; // @[execution-unit.scala:537:23]
wire [2:0] _queue_io_deq_bits_fflags_bits_uop_ctrl_csr_cmd; // @[execution-unit.scala:537:23]
wire _queue_io_deq_bits_fflags_bits_uop_ctrl_is_load; // @[execution-unit.scala:537:23]
wire _queue_io_deq_bits_fflags_bits_uop_ctrl_is_sta; // @[execution-unit.scala:537:23]
wire _queue_io_deq_bits_fflags_bits_uop_ctrl_is_std; // @[execution-unit.scala:537:23]
wire [1:0] _queue_io_deq_bits_fflags_bits_uop_iw_state; // @[execution-unit.scala:537:23]
wire _queue_io_deq_bits_fflags_bits_uop_iw_p1_poisoned; // @[execution-unit.scala:537:23]
wire _queue_io_deq_bits_fflags_bits_uop_iw_p2_poisoned; // @[execution-unit.scala:537:23]
wire _queue_io_deq_bits_fflags_bits_uop_is_br; // @[execution-unit.scala:537:23]
wire _queue_io_deq_bits_fflags_bits_uop_is_jalr; // @[execution-unit.scala:537:23]
wire _queue_io_deq_bits_fflags_bits_uop_is_jal; // @[execution-unit.scala:537:23]
wire _queue_io_deq_bits_fflags_bits_uop_is_sfb; // @[execution-unit.scala:537:23]
wire [15:0] _queue_io_deq_bits_fflags_bits_uop_br_mask; // @[execution-unit.scala:537:23]
wire [3:0] _queue_io_deq_bits_fflags_bits_uop_br_tag; // @[execution-unit.scala:537:23]
wire [4:0] _queue_io_deq_bits_fflags_bits_uop_ftq_idx; // @[execution-unit.scala:537:23]
wire _queue_io_deq_bits_fflags_bits_uop_edge_inst; // @[execution-unit.scala:537:23]
wire [5:0] _queue_io_deq_bits_fflags_bits_uop_pc_lob; // @[execution-unit.scala:537:23]
wire _queue_io_deq_bits_fflags_bits_uop_taken; // @[execution-unit.scala:537:23]
wire [19:0] _queue_io_deq_bits_fflags_bits_uop_imm_packed; // @[execution-unit.scala:537:23]
wire [11:0] _queue_io_deq_bits_fflags_bits_uop_csr_addr; // @[execution-unit.scala:537:23]
wire [6:0] _queue_io_deq_bits_fflags_bits_uop_rob_idx; // @[execution-unit.scala:537:23]
wire [4:0] _queue_io_deq_bits_fflags_bits_uop_ldq_idx; // @[execution-unit.scala:537:23]
wire [4:0] _queue_io_deq_bits_fflags_bits_uop_stq_idx; // @[execution-unit.scala:537:23]
wire [1:0] _queue_io_deq_bits_fflags_bits_uop_rxq_idx; // @[execution-unit.scala:537:23]
wire [6:0] _queue_io_deq_bits_fflags_bits_uop_pdst; // @[execution-unit.scala:537:23]
wire [6:0] _queue_io_deq_bits_fflags_bits_uop_prs1; // @[execution-unit.scala:537:23]
wire [6:0] _queue_io_deq_bits_fflags_bits_uop_prs2; // @[execution-unit.scala:537:23]
wire [6:0] _queue_io_deq_bits_fflags_bits_uop_prs3; // @[execution-unit.scala:537:23]
wire [4:0] _queue_io_deq_bits_fflags_bits_uop_ppred; // @[execution-unit.scala:537:23]
wire _queue_io_deq_bits_fflags_bits_uop_prs1_busy; // @[execution-unit.scala:537:23]
wire _queue_io_deq_bits_fflags_bits_uop_prs2_busy; // @[execution-unit.scala:537:23]
wire _queue_io_deq_bits_fflags_bits_uop_prs3_busy; // @[execution-unit.scala:537:23]
wire _queue_io_deq_bits_fflags_bits_uop_ppred_busy; // @[execution-unit.scala:537:23]
wire [6:0] _queue_io_deq_bits_fflags_bits_uop_stale_pdst; // @[execution-unit.scala:537:23]
wire _queue_io_deq_bits_fflags_bits_uop_exception; // @[execution-unit.scala:537:23]
wire [63:0] _queue_io_deq_bits_fflags_bits_uop_exc_cause; // @[execution-unit.scala:537:23]
wire _queue_io_deq_bits_fflags_bits_uop_bypassable; // @[execution-unit.scala:537:23]
wire [4:0] _queue_io_deq_bits_fflags_bits_uop_mem_cmd; // @[execution-unit.scala:537:23]
wire [1:0] _queue_io_deq_bits_fflags_bits_uop_mem_size; // @[execution-unit.scala:537:23]
wire _queue_io_deq_bits_fflags_bits_uop_mem_signed; // @[execution-unit.scala:537:23]
wire _queue_io_deq_bits_fflags_bits_uop_is_fence; // @[execution-unit.scala:537:23]
wire _queue_io_deq_bits_fflags_bits_uop_is_fencei; // @[execution-unit.scala:537:23]
wire _queue_io_deq_bits_fflags_bits_uop_is_amo; // @[execution-unit.scala:537:23]
wire _queue_io_deq_bits_fflags_bits_uop_uses_ldq; // @[execution-unit.scala:537:23]
wire _queue_io_deq_bits_fflags_bits_uop_uses_stq; // @[execution-unit.scala:537:23]
wire _queue_io_deq_bits_fflags_bits_uop_is_sys_pc2epc; // @[execution-unit.scala:537:23]
wire _queue_io_deq_bits_fflags_bits_uop_is_unique; // @[execution-unit.scala:537:23]
wire _queue_io_deq_bits_fflags_bits_uop_flush_on_commit; // @[execution-unit.scala:537:23]
wire _queue_io_deq_bits_fflags_bits_uop_ldst_is_rs1; // @[execution-unit.scala:537:23]
wire [5:0] _queue_io_deq_bits_fflags_bits_uop_ldst; // @[execution-unit.scala:537:23]
wire [5:0] _queue_io_deq_bits_fflags_bits_uop_lrs1; // @[execution-unit.scala:537:23]
wire [5:0] _queue_io_deq_bits_fflags_bits_uop_lrs2; // @[execution-unit.scala:537:23]
wire [5:0] _queue_io_deq_bits_fflags_bits_uop_lrs3; // @[execution-unit.scala:537:23]
wire _queue_io_deq_bits_fflags_bits_uop_ldst_val; // @[execution-unit.scala:537:23]
wire [1:0] _queue_io_deq_bits_fflags_bits_uop_dst_rtype; // @[execution-unit.scala:537:23]
wire [1:0] _queue_io_deq_bits_fflags_bits_uop_lrs1_rtype; // @[execution-unit.scala:537:23]
wire [1:0] _queue_io_deq_bits_fflags_bits_uop_lrs2_rtype; // @[execution-unit.scala:537:23]
wire _queue_io_deq_bits_fflags_bits_uop_frs3_en; // @[execution-unit.scala:537:23]
wire _queue_io_deq_bits_fflags_bits_uop_fp_val; // @[execution-unit.scala:537:23]
wire _queue_io_deq_bits_fflags_bits_uop_fp_single; // @[execution-unit.scala:537:23]
wire _queue_io_deq_bits_fflags_bits_uop_xcpt_pf_if; // @[execution-unit.scala:537:23]
wire _queue_io_deq_bits_fflags_bits_uop_xcpt_ae_if; // @[execution-unit.scala:537:23]
wire _queue_io_deq_bits_fflags_bits_uop_xcpt_ma_if; // @[execution-unit.scala:537:23]
wire _queue_io_deq_bits_fflags_bits_uop_bp_debug_if; // @[execution-unit.scala:537:23]
wire _queue_io_deq_bits_fflags_bits_uop_bp_xcpt_if; // @[execution-unit.scala:537:23]
wire [1:0] _queue_io_deq_bits_fflags_bits_uop_debug_fsrc; // @[execution-unit.scala:537:23]
wire [1:0] _queue_io_deq_bits_fflags_bits_uop_debug_tsrc; // @[execution-unit.scala:537:23]
wire [4:0] _queue_io_deq_bits_fflags_bits_flags; // @[execution-unit.scala:537:23]
wire _queue_io_empty; // @[execution-unit.scala:537:23]
wire _FDivSqrtUnit_io_req_ready; // @[execution-unit.scala:502:22]
wire _FDivSqrtUnit_io_resp_valid; // @[execution-unit.scala:502:22]
wire [6:0] _FDivSqrtUnit_io_resp_bits_uop_uopc; // @[execution-unit.scala:502:22]
wire [31:0] _FDivSqrtUnit_io_resp_bits_uop_inst; // @[execution-unit.scala:502:22]
wire [31:0] _FDivSqrtUnit_io_resp_bits_uop_debug_inst; // @[execution-unit.scala:502:22]
wire _FDivSqrtUnit_io_resp_bits_uop_is_rvc; // @[execution-unit.scala:502:22]
wire [39:0] _FDivSqrtUnit_io_resp_bits_uop_debug_pc; // @[execution-unit.scala:502:22]
wire [2:0] _FDivSqrtUnit_io_resp_bits_uop_iq_type; // @[execution-unit.scala:502:22]
wire [9:0] _FDivSqrtUnit_io_resp_bits_uop_fu_code; // @[execution-unit.scala:502:22]
wire [3:0] _FDivSqrtUnit_io_resp_bits_uop_ctrl_br_type; // @[execution-unit.scala:502:22]
wire [1:0] _FDivSqrtUnit_io_resp_bits_uop_ctrl_op1_sel; // @[execution-unit.scala:502:22]
wire [2:0] _FDivSqrtUnit_io_resp_bits_uop_ctrl_op2_sel; // @[execution-unit.scala:502:22]
wire [2:0] _FDivSqrtUnit_io_resp_bits_uop_ctrl_imm_sel; // @[execution-unit.scala:502:22]
wire [4:0] _FDivSqrtUnit_io_resp_bits_uop_ctrl_op_fcn; // @[execution-unit.scala:502:22]
wire _FDivSqrtUnit_io_resp_bits_uop_ctrl_fcn_dw; // @[execution-unit.scala:502:22]
wire [2:0] _FDivSqrtUnit_io_resp_bits_uop_ctrl_csr_cmd; // @[execution-unit.scala:502:22]
wire _FDivSqrtUnit_io_resp_bits_uop_ctrl_is_load; // @[execution-unit.scala:502:22]
wire _FDivSqrtUnit_io_resp_bits_uop_ctrl_is_sta; // @[execution-unit.scala:502:22]
wire _FDivSqrtUnit_io_resp_bits_uop_ctrl_is_std; // @[execution-unit.scala:502:22]
wire [1:0] _FDivSqrtUnit_io_resp_bits_uop_iw_state; // @[execution-unit.scala:502:22]
wire _FDivSqrtUnit_io_resp_bits_uop_iw_p1_poisoned; // @[execution-unit.scala:502:22]
wire _FDivSqrtUnit_io_resp_bits_uop_iw_p2_poisoned; // @[execution-unit.scala:502:22]
wire _FDivSqrtUnit_io_resp_bits_uop_is_br; // @[execution-unit.scala:502:22]
wire _FDivSqrtUnit_io_resp_bits_uop_is_jalr; // @[execution-unit.scala:502:22]
wire _FDivSqrtUnit_io_resp_bits_uop_is_jal; // @[execution-unit.scala:502:22]
wire _FDivSqrtUnit_io_resp_bits_uop_is_sfb; // @[execution-unit.scala:502:22]
wire [15:0] _FDivSqrtUnit_io_resp_bits_uop_br_mask; // @[execution-unit.scala:502:22]
wire [3:0] _FDivSqrtUnit_io_resp_bits_uop_br_tag; // @[execution-unit.scala:502:22]
wire [4:0] _FDivSqrtUnit_io_resp_bits_uop_ftq_idx; // @[execution-unit.scala:502:22]
wire _FDivSqrtUnit_io_resp_bits_uop_edge_inst; // @[execution-unit.scala:502:22]
wire [5:0] _FDivSqrtUnit_io_resp_bits_uop_pc_lob; // @[execution-unit.scala:502:22]
wire _FDivSqrtUnit_io_resp_bits_uop_taken; // @[execution-unit.scala:502:22]
wire [19:0] _FDivSqrtUnit_io_resp_bits_uop_imm_packed; // @[execution-unit.scala:502:22]
wire [11:0] _FDivSqrtUnit_io_resp_bits_uop_csr_addr; // @[execution-unit.scala:502:22]
wire [6:0] _FDivSqrtUnit_io_resp_bits_uop_rob_idx; // @[execution-unit.scala:502:22]
wire [4:0] _FDivSqrtUnit_io_resp_bits_uop_ldq_idx; // @[execution-unit.scala:502:22]
wire [4:0] _FDivSqrtUnit_io_resp_bits_uop_stq_idx; // @[execution-unit.scala:502:22]
wire [1:0] _FDivSqrtUnit_io_resp_bits_uop_rxq_idx; // @[execution-unit.scala:502:22]
wire [6:0] _FDivSqrtUnit_io_resp_bits_uop_pdst; // @[execution-unit.scala:502:22]
wire [6:0] _FDivSqrtUnit_io_resp_bits_uop_prs1; // @[execution-unit.scala:502:22]
wire [6:0] _FDivSqrtUnit_io_resp_bits_uop_prs2; // @[execution-unit.scala:502:22]
wire [6:0] _FDivSqrtUnit_io_resp_bits_uop_prs3; // @[execution-unit.scala:502:22]
wire [4:0] _FDivSqrtUnit_io_resp_bits_uop_ppred; // @[execution-unit.scala:502:22]
wire _FDivSqrtUnit_io_resp_bits_uop_prs1_busy; // @[execution-unit.scala:502:22]
wire _FDivSqrtUnit_io_resp_bits_uop_prs2_busy; // @[execution-unit.scala:502:22]
wire _FDivSqrtUnit_io_resp_bits_uop_prs3_busy; // @[execution-unit.scala:502:22]
wire _FDivSqrtUnit_io_resp_bits_uop_ppred_busy; // @[execution-unit.scala:502:22]
wire [6:0] _FDivSqrtUnit_io_resp_bits_uop_stale_pdst; // @[execution-unit.scala:502:22]
wire _FDivSqrtUnit_io_resp_bits_uop_exception; // @[execution-unit.scala:502:22]
wire [63:0] _FDivSqrtUnit_io_resp_bits_uop_exc_cause; // @[execution-unit.scala:502:22]
wire _FDivSqrtUnit_io_resp_bits_uop_bypassable; // @[execution-unit.scala:502:22]
wire [4:0] _FDivSqrtUnit_io_resp_bits_uop_mem_cmd; // @[execution-unit.scala:502:22]
wire [1:0] _FDivSqrtUnit_io_resp_bits_uop_mem_size; // @[execution-unit.scala:502:22]
wire _FDivSqrtUnit_io_resp_bits_uop_mem_signed; // @[execution-unit.scala:502:22]
wire _FDivSqrtUnit_io_resp_bits_uop_is_fence; // @[execution-unit.scala:502:22]
wire _FDivSqrtUnit_io_resp_bits_uop_is_fencei; // @[execution-unit.scala:502:22]
wire _FDivSqrtUnit_io_resp_bits_uop_is_amo; // @[execution-unit.scala:502:22]
wire _FDivSqrtUnit_io_resp_bits_uop_uses_ldq; // @[execution-unit.scala:502:22]
wire _FDivSqrtUnit_io_resp_bits_uop_uses_stq; // @[execution-unit.scala:502:22]
wire _FDivSqrtUnit_io_resp_bits_uop_is_sys_pc2epc; // @[execution-unit.scala:502:22]
wire _FDivSqrtUnit_io_resp_bits_uop_is_unique; // @[execution-unit.scala:502:22]
wire _FDivSqrtUnit_io_resp_bits_uop_flush_on_commit; // @[execution-unit.scala:502:22]
wire _FDivSqrtUnit_io_resp_bits_uop_ldst_is_rs1; // @[execution-unit.scala:502:22]
wire [5:0] _FDivSqrtUnit_io_resp_bits_uop_ldst; // @[execution-unit.scala:502:22]
wire [5:0] _FDivSqrtUnit_io_resp_bits_uop_lrs1; // @[execution-unit.scala:502:22]
wire [5:0] _FDivSqrtUnit_io_resp_bits_uop_lrs2; // @[execution-unit.scala:502:22]
wire [5:0] _FDivSqrtUnit_io_resp_bits_uop_lrs3; // @[execution-unit.scala:502:22]
wire _FDivSqrtUnit_io_resp_bits_uop_ldst_val; // @[execution-unit.scala:502:22]
wire [1:0] _FDivSqrtUnit_io_resp_bits_uop_dst_rtype; // @[execution-unit.scala:502:22]
wire [1:0] _FDivSqrtUnit_io_resp_bits_uop_lrs1_rtype; // @[execution-unit.scala:502:22]
wire [1:0] _FDivSqrtUnit_io_resp_bits_uop_lrs2_rtype; // @[execution-unit.scala:502:22]
wire _FDivSqrtUnit_io_resp_bits_uop_frs3_en; // @[execution-unit.scala:502:22]
wire _FDivSqrtUnit_io_resp_bits_uop_fp_val; // @[execution-unit.scala:502:22]
wire _FDivSqrtUnit_io_resp_bits_uop_fp_single; // @[execution-unit.scala:502:22]
wire _FDivSqrtUnit_io_resp_bits_uop_xcpt_pf_if; // @[execution-unit.scala:502:22]
wire _FDivSqrtUnit_io_resp_bits_uop_xcpt_ae_if; // @[execution-unit.scala:502:22]
wire _FDivSqrtUnit_io_resp_bits_uop_xcpt_ma_if; // @[execution-unit.scala:502:22]
wire _FDivSqrtUnit_io_resp_bits_uop_bp_debug_if; // @[execution-unit.scala:502:22]
wire _FDivSqrtUnit_io_resp_bits_uop_bp_xcpt_if; // @[execution-unit.scala:502:22]
wire [1:0] _FDivSqrtUnit_io_resp_bits_uop_debug_fsrc; // @[execution-unit.scala:502:22]
wire [1:0] _FDivSqrtUnit_io_resp_bits_uop_debug_tsrc; // @[execution-unit.scala:502:22]
wire [64:0] _FDivSqrtUnit_io_resp_bits_data; // @[execution-unit.scala:502:22]
wire _FPUUnit_io_resp_valid; // @[execution-unit.scala:477:17]
wire [6:0] _FPUUnit_io_resp_bits_uop_uopc; // @[execution-unit.scala:477:17]
wire [31:0] _FPUUnit_io_resp_bits_uop_inst; // @[execution-unit.scala:477:17]
wire [31:0] _FPUUnit_io_resp_bits_uop_debug_inst; // @[execution-unit.scala:477:17]
wire _FPUUnit_io_resp_bits_uop_is_rvc; // @[execution-unit.scala:477:17]
wire [39:0] _FPUUnit_io_resp_bits_uop_debug_pc; // @[execution-unit.scala:477:17]
wire [2:0] _FPUUnit_io_resp_bits_uop_iq_type; // @[execution-unit.scala:477:17]
wire [9:0] _FPUUnit_io_resp_bits_uop_fu_code; // @[execution-unit.scala:477:17]
wire [3:0] _FPUUnit_io_resp_bits_uop_ctrl_br_type; // @[execution-unit.scala:477:17]
wire [1:0] _FPUUnit_io_resp_bits_uop_ctrl_op1_sel; // @[execution-unit.scala:477:17]
wire [2:0] _FPUUnit_io_resp_bits_uop_ctrl_op2_sel; // @[execution-unit.scala:477:17]
wire [2:0] _FPUUnit_io_resp_bits_uop_ctrl_imm_sel; // @[execution-unit.scala:477:17]
wire [4:0] _FPUUnit_io_resp_bits_uop_ctrl_op_fcn; // @[execution-unit.scala:477:17]
wire _FPUUnit_io_resp_bits_uop_ctrl_fcn_dw; // @[execution-unit.scala:477:17]
wire [2:0] _FPUUnit_io_resp_bits_uop_ctrl_csr_cmd; // @[execution-unit.scala:477:17]
wire _FPUUnit_io_resp_bits_uop_ctrl_is_load; // @[execution-unit.scala:477:17]
wire _FPUUnit_io_resp_bits_uop_ctrl_is_sta; // @[execution-unit.scala:477:17]
wire _FPUUnit_io_resp_bits_uop_ctrl_is_std; // @[execution-unit.scala:477:17]
wire [1:0] _FPUUnit_io_resp_bits_uop_iw_state; // @[execution-unit.scala:477:17]
wire _FPUUnit_io_resp_bits_uop_iw_p1_poisoned; // @[execution-unit.scala:477:17]
wire _FPUUnit_io_resp_bits_uop_iw_p2_poisoned; // @[execution-unit.scala:477:17]
wire _FPUUnit_io_resp_bits_uop_is_br; // @[execution-unit.scala:477:17]
wire _FPUUnit_io_resp_bits_uop_is_jalr; // @[execution-unit.scala:477:17]
wire _FPUUnit_io_resp_bits_uop_is_jal; // @[execution-unit.scala:477:17]
wire _FPUUnit_io_resp_bits_uop_is_sfb; // @[execution-unit.scala:477:17]
wire [15:0] _FPUUnit_io_resp_bits_uop_br_mask; // @[execution-unit.scala:477:17]
wire [3:0] _FPUUnit_io_resp_bits_uop_br_tag; // @[execution-unit.scala:477:17]
wire [4:0] _FPUUnit_io_resp_bits_uop_ftq_idx; // @[execution-unit.scala:477:17]
wire _FPUUnit_io_resp_bits_uop_edge_inst; // @[execution-unit.scala:477:17]
wire [5:0] _FPUUnit_io_resp_bits_uop_pc_lob; // @[execution-unit.scala:477:17]
wire _FPUUnit_io_resp_bits_uop_taken; // @[execution-unit.scala:477:17]
wire [19:0] _FPUUnit_io_resp_bits_uop_imm_packed; // @[execution-unit.scala:477:17]
wire [11:0] _FPUUnit_io_resp_bits_uop_csr_addr; // @[execution-unit.scala:477:17]
wire [6:0] _FPUUnit_io_resp_bits_uop_rob_idx; // @[execution-unit.scala:477:17]
wire [4:0] _FPUUnit_io_resp_bits_uop_ldq_idx; // @[execution-unit.scala:477:17]
wire [4:0] _FPUUnit_io_resp_bits_uop_stq_idx; // @[execution-unit.scala:477:17]
wire [1:0] _FPUUnit_io_resp_bits_uop_rxq_idx; // @[execution-unit.scala:477:17]
wire [6:0] _FPUUnit_io_resp_bits_uop_pdst; // @[execution-unit.scala:477:17]
wire [6:0] _FPUUnit_io_resp_bits_uop_prs1; // @[execution-unit.scala:477:17]
wire [6:0] _FPUUnit_io_resp_bits_uop_prs2; // @[execution-unit.scala:477:17]
wire [6:0] _FPUUnit_io_resp_bits_uop_prs3; // @[execution-unit.scala:477:17]
wire [4:0] _FPUUnit_io_resp_bits_uop_ppred; // @[execution-unit.scala:477:17]
wire _FPUUnit_io_resp_bits_uop_prs1_busy; // @[execution-unit.scala:477:17]
wire _FPUUnit_io_resp_bits_uop_prs2_busy; // @[execution-unit.scala:477:17]
wire _FPUUnit_io_resp_bits_uop_prs3_busy; // @[execution-unit.scala:477:17]
wire _FPUUnit_io_resp_bits_uop_ppred_busy; // @[execution-unit.scala:477:17]
wire [6:0] _FPUUnit_io_resp_bits_uop_stale_pdst; // @[execution-unit.scala:477:17]
wire _FPUUnit_io_resp_bits_uop_exception; // @[execution-unit.scala:477:17]
wire [63:0] _FPUUnit_io_resp_bits_uop_exc_cause; // @[execution-unit.scala:477:17]
wire _FPUUnit_io_resp_bits_uop_bypassable; // @[execution-unit.scala:477:17]
wire [4:0] _FPUUnit_io_resp_bits_uop_mem_cmd; // @[execution-unit.scala:477:17]
wire [1:0] _FPUUnit_io_resp_bits_uop_mem_size; // @[execution-unit.scala:477:17]
wire _FPUUnit_io_resp_bits_uop_mem_signed; // @[execution-unit.scala:477:17]
wire _FPUUnit_io_resp_bits_uop_is_fence; // @[execution-unit.scala:477:17]
wire _FPUUnit_io_resp_bits_uop_is_fencei; // @[execution-unit.scala:477:17]
wire _FPUUnit_io_resp_bits_uop_is_amo; // @[execution-unit.scala:477:17]
wire _FPUUnit_io_resp_bits_uop_uses_ldq; // @[execution-unit.scala:477:17]
wire _FPUUnit_io_resp_bits_uop_uses_stq; // @[execution-unit.scala:477:17]
wire _FPUUnit_io_resp_bits_uop_is_sys_pc2epc; // @[execution-unit.scala:477:17]
wire _FPUUnit_io_resp_bits_uop_is_unique; // @[execution-unit.scala:477:17]
wire _FPUUnit_io_resp_bits_uop_flush_on_commit; // @[execution-unit.scala:477:17]
wire _FPUUnit_io_resp_bits_uop_ldst_is_rs1; // @[execution-unit.scala:477:17]
wire [5:0] _FPUUnit_io_resp_bits_uop_ldst; // @[execution-unit.scala:477:17]
wire [5:0] _FPUUnit_io_resp_bits_uop_lrs1; // @[execution-unit.scala:477:17]
wire [5:0] _FPUUnit_io_resp_bits_uop_lrs2; // @[execution-unit.scala:477:17]
wire [5:0] _FPUUnit_io_resp_bits_uop_lrs3; // @[execution-unit.scala:477:17]
wire _FPUUnit_io_resp_bits_uop_ldst_val; // @[execution-unit.scala:477:17]
wire [1:0] _FPUUnit_io_resp_bits_uop_dst_rtype; // @[execution-unit.scala:477:17]
wire [1:0] _FPUUnit_io_resp_bits_uop_lrs1_rtype; // @[execution-unit.scala:477:17]
wire [1:0] _FPUUnit_io_resp_bits_uop_lrs2_rtype; // @[execution-unit.scala:477:17]
wire _FPUUnit_io_resp_bits_uop_frs3_en; // @[execution-unit.scala:477:17]
wire _FPUUnit_io_resp_bits_uop_fp_val; // @[execution-unit.scala:477:17]
wire _FPUUnit_io_resp_bits_uop_fp_single; // @[execution-unit.scala:477:17]
wire _FPUUnit_io_resp_bits_uop_xcpt_pf_if; // @[execution-unit.scala:477:17]
wire _FPUUnit_io_resp_bits_uop_xcpt_ae_if; // @[execution-unit.scala:477:17]
wire _FPUUnit_io_resp_bits_uop_xcpt_ma_if; // @[execution-unit.scala:477:17]
wire _FPUUnit_io_resp_bits_uop_bp_debug_if; // @[execution-unit.scala:477:17]
wire _FPUUnit_io_resp_bits_uop_bp_xcpt_if; // @[execution-unit.scala:477:17]
wire [1:0] _FPUUnit_io_resp_bits_uop_debug_fsrc; // @[execution-unit.scala:477:17]
wire [1:0] _FPUUnit_io_resp_bits_uop_debug_tsrc; // @[execution-unit.scala:477:17]
wire [64:0] _FPUUnit_io_resp_bits_data; // @[execution-unit.scala:477:17]
wire _FPUUnit_io_resp_bits_fflags_valid; // @[execution-unit.scala:477:17]
wire [6:0] _FPUUnit_io_resp_bits_fflags_bits_uop_uopc; // @[execution-unit.scala:477:17]
wire [31:0] _FPUUnit_io_resp_bits_fflags_bits_uop_inst; // @[execution-unit.scala:477:17]
wire [31:0] _FPUUnit_io_resp_bits_fflags_bits_uop_debug_inst; // @[execution-unit.scala:477:17]
wire _FPUUnit_io_resp_bits_fflags_bits_uop_is_rvc; // @[execution-unit.scala:477:17]
wire [39:0] _FPUUnit_io_resp_bits_fflags_bits_uop_debug_pc; // @[execution-unit.scala:477:17]
wire [2:0] _FPUUnit_io_resp_bits_fflags_bits_uop_iq_type; // @[execution-unit.scala:477:17]
wire [9:0] _FPUUnit_io_resp_bits_fflags_bits_uop_fu_code; // @[execution-unit.scala:477:17]
wire [3:0] _FPUUnit_io_resp_bits_fflags_bits_uop_ctrl_br_type; // @[execution-unit.scala:477:17]
wire [1:0] _FPUUnit_io_resp_bits_fflags_bits_uop_ctrl_op1_sel; // @[execution-unit.scala:477:17]
wire [2:0] _FPUUnit_io_resp_bits_fflags_bits_uop_ctrl_op2_sel; // @[execution-unit.scala:477:17]
wire [2:0] _FPUUnit_io_resp_bits_fflags_bits_uop_ctrl_imm_sel; // @[execution-unit.scala:477:17]
wire [4:0] _FPUUnit_io_resp_bits_fflags_bits_uop_ctrl_op_fcn; // @[execution-unit.scala:477:17]
wire _FPUUnit_io_resp_bits_fflags_bits_uop_ctrl_fcn_dw; // @[execution-unit.scala:477:17]
wire [2:0] _FPUUnit_io_resp_bits_fflags_bits_uop_ctrl_csr_cmd; // @[execution-unit.scala:477:17]
wire _FPUUnit_io_resp_bits_fflags_bits_uop_ctrl_is_load; // @[execution-unit.scala:477:17]
wire _FPUUnit_io_resp_bits_fflags_bits_uop_ctrl_is_sta; // @[execution-unit.scala:477:17]
wire _FPUUnit_io_resp_bits_fflags_bits_uop_ctrl_is_std; // @[execution-unit.scala:477:17]
wire [1:0] _FPUUnit_io_resp_bits_fflags_bits_uop_iw_state; // @[execution-unit.scala:477:17]
wire _FPUUnit_io_resp_bits_fflags_bits_uop_iw_p1_poisoned; // @[execution-unit.scala:477:17]
wire _FPUUnit_io_resp_bits_fflags_bits_uop_iw_p2_poisoned; // @[execution-unit.scala:477:17]
wire _FPUUnit_io_resp_bits_fflags_bits_uop_is_br; // @[execution-unit.scala:477:17]
wire _FPUUnit_io_resp_bits_fflags_bits_uop_is_jalr; // @[execution-unit.scala:477:17]
wire _FPUUnit_io_resp_bits_fflags_bits_uop_is_jal; // @[execution-unit.scala:477:17]
wire _FPUUnit_io_resp_bits_fflags_bits_uop_is_sfb; // @[execution-unit.scala:477:17]
wire [15:0] _FPUUnit_io_resp_bits_fflags_bits_uop_br_mask; // @[execution-unit.scala:477:17]
wire [3:0] _FPUUnit_io_resp_bits_fflags_bits_uop_br_tag; // @[execution-unit.scala:477:17]
wire [4:0] _FPUUnit_io_resp_bits_fflags_bits_uop_ftq_idx; // @[execution-unit.scala:477:17]
wire _FPUUnit_io_resp_bits_fflags_bits_uop_edge_inst; // @[execution-unit.scala:477:17]
wire [5:0] _FPUUnit_io_resp_bits_fflags_bits_uop_pc_lob; // @[execution-unit.scala:477:17]
wire _FPUUnit_io_resp_bits_fflags_bits_uop_taken; // @[execution-unit.scala:477:17]
wire [19:0] _FPUUnit_io_resp_bits_fflags_bits_uop_imm_packed; // @[execution-unit.scala:477:17]
wire [11:0] _FPUUnit_io_resp_bits_fflags_bits_uop_csr_addr; // @[execution-unit.scala:477:17]
wire [6:0] _FPUUnit_io_resp_bits_fflags_bits_uop_rob_idx; // @[execution-unit.scala:477:17]
wire [4:0] _FPUUnit_io_resp_bits_fflags_bits_uop_ldq_idx; // @[execution-unit.scala:477:17]
wire [4:0] _FPUUnit_io_resp_bits_fflags_bits_uop_stq_idx; // @[execution-unit.scala:477:17]
wire [1:0] _FPUUnit_io_resp_bits_fflags_bits_uop_rxq_idx; // @[execution-unit.scala:477:17]
wire [6:0] _FPUUnit_io_resp_bits_fflags_bits_uop_pdst; // @[execution-unit.scala:477:17]
wire [6:0] _FPUUnit_io_resp_bits_fflags_bits_uop_prs1; // @[execution-unit.scala:477:17]
wire [6:0] _FPUUnit_io_resp_bits_fflags_bits_uop_prs2; // @[execution-unit.scala:477:17]
wire [6:0] _FPUUnit_io_resp_bits_fflags_bits_uop_prs3; // @[execution-unit.scala:477:17]
wire [4:0] _FPUUnit_io_resp_bits_fflags_bits_uop_ppred; // @[execution-unit.scala:477:17]
wire _FPUUnit_io_resp_bits_fflags_bits_uop_prs1_busy; // @[execution-unit.scala:477:17]
wire _FPUUnit_io_resp_bits_fflags_bits_uop_prs2_busy; // @[execution-unit.scala:477:17]
wire _FPUUnit_io_resp_bits_fflags_bits_uop_prs3_busy; // @[execution-unit.scala:477:17]
wire _FPUUnit_io_resp_bits_fflags_bits_uop_ppred_busy; // @[execution-unit.scala:477:17]
wire [6:0] _FPUUnit_io_resp_bits_fflags_bits_uop_stale_pdst; // @[execution-unit.scala:477:17]
wire _FPUUnit_io_resp_bits_fflags_bits_uop_exception; // @[execution-unit.scala:477:17]
wire [63:0] _FPUUnit_io_resp_bits_fflags_bits_uop_exc_cause; // @[execution-unit.scala:477:17]
wire _FPUUnit_io_resp_bits_fflags_bits_uop_bypassable; // @[execution-unit.scala:477:17]
wire [4:0] _FPUUnit_io_resp_bits_fflags_bits_uop_mem_cmd; // @[execution-unit.scala:477:17]
wire [1:0] _FPUUnit_io_resp_bits_fflags_bits_uop_mem_size; // @[execution-unit.scala:477:17]
wire _FPUUnit_io_resp_bits_fflags_bits_uop_mem_signed; // @[execution-unit.scala:477:17]
wire _FPUUnit_io_resp_bits_fflags_bits_uop_is_fence; // @[execution-unit.scala:477:17]
wire _FPUUnit_io_resp_bits_fflags_bits_uop_is_fencei; // @[execution-unit.scala:477:17]
wire _FPUUnit_io_resp_bits_fflags_bits_uop_is_amo; // @[execution-unit.scala:477:17]
wire _FPUUnit_io_resp_bits_fflags_bits_uop_uses_ldq; // @[execution-unit.scala:477:17]
wire _FPUUnit_io_resp_bits_fflags_bits_uop_uses_stq; // @[execution-unit.scala:477:17]
wire _FPUUnit_io_resp_bits_fflags_bits_uop_is_sys_pc2epc; // @[execution-unit.scala:477:17]
wire _FPUUnit_io_resp_bits_fflags_bits_uop_is_unique; // @[execution-unit.scala:477:17]
wire _FPUUnit_io_resp_bits_fflags_bits_uop_flush_on_commit; // @[execution-unit.scala:477:17]
wire _FPUUnit_io_resp_bits_fflags_bits_uop_ldst_is_rs1; // @[execution-unit.scala:477:17]
wire [5:0] _FPUUnit_io_resp_bits_fflags_bits_uop_ldst; // @[execution-unit.scala:477:17]
wire [5:0] _FPUUnit_io_resp_bits_fflags_bits_uop_lrs1; // @[execution-unit.scala:477:17]
wire [5:0] _FPUUnit_io_resp_bits_fflags_bits_uop_lrs2; // @[execution-unit.scala:477:17]
wire [5:0] _FPUUnit_io_resp_bits_fflags_bits_uop_lrs3; // @[execution-unit.scala:477:17]
wire _FPUUnit_io_resp_bits_fflags_bits_uop_ldst_val; // @[execution-unit.scala:477:17]
wire [1:0] _FPUUnit_io_resp_bits_fflags_bits_uop_dst_rtype; // @[execution-unit.scala:477:17]
wire [1:0] _FPUUnit_io_resp_bits_fflags_bits_uop_lrs1_rtype; // @[execution-unit.scala:477:17]
wire [1:0] _FPUUnit_io_resp_bits_fflags_bits_uop_lrs2_rtype; // @[execution-unit.scala:477:17]
wire _FPUUnit_io_resp_bits_fflags_bits_uop_frs3_en; // @[execution-unit.scala:477:17]
wire _FPUUnit_io_resp_bits_fflags_bits_uop_fp_val; // @[execution-unit.scala:477:17]
wire _FPUUnit_io_resp_bits_fflags_bits_uop_fp_single; // @[execution-unit.scala:477:17]
wire _FPUUnit_io_resp_bits_fflags_bits_uop_xcpt_pf_if; // @[execution-unit.scala:477:17]
wire _FPUUnit_io_resp_bits_fflags_bits_uop_xcpt_ae_if; // @[execution-unit.scala:477:17]
wire _FPUUnit_io_resp_bits_fflags_bits_uop_xcpt_ma_if; // @[execution-unit.scala:477:17]
wire _FPUUnit_io_resp_bits_fflags_bits_uop_bp_debug_if; // @[execution-unit.scala:477:17]
wire _FPUUnit_io_resp_bits_fflags_bits_uop_bp_xcpt_if; // @[execution-unit.scala:477:17]
wire [1:0] _FPUUnit_io_resp_bits_fflags_bits_uop_debug_fsrc; // @[execution-unit.scala:477:17]
wire [1:0] _FPUUnit_io_resp_bits_fflags_bits_uop_debug_tsrc; // @[execution-unit.scala:477:17]
wire [4:0] _FPUUnit_io_resp_bits_fflags_bits_flags; // @[execution-unit.scala:477:17]
wire io_req_valid_0 = io_req_valid; // @[execution-unit.scala:437:7]
wire [6:0] io_req_bits_uop_uopc_0 = io_req_bits_uop_uopc; // @[execution-unit.scala:437:7]
wire [31:0] io_req_bits_uop_inst_0 = io_req_bits_uop_inst; // @[execution-unit.scala:437:7]
wire [31:0] io_req_bits_uop_debug_inst_0 = io_req_bits_uop_debug_inst; // @[execution-unit.scala:437:7]
wire io_req_bits_uop_is_rvc_0 = io_req_bits_uop_is_rvc; // @[execution-unit.scala:437:7]
wire [39:0] io_req_bits_uop_debug_pc_0 = io_req_bits_uop_debug_pc; // @[execution-unit.scala:437:7]
wire [2:0] io_req_bits_uop_iq_type_0 = io_req_bits_uop_iq_type; // @[execution-unit.scala:437:7]
wire [9:0] io_req_bits_uop_fu_code_0 = io_req_bits_uop_fu_code; // @[execution-unit.scala:437:7]
wire [3:0] io_req_bits_uop_ctrl_br_type_0 = io_req_bits_uop_ctrl_br_type; // @[execution-unit.scala:437:7]
wire [1:0] io_req_bits_uop_ctrl_op1_sel_0 = io_req_bits_uop_ctrl_op1_sel; // @[execution-unit.scala:437:7]
wire [2:0] io_req_bits_uop_ctrl_op2_sel_0 = io_req_bits_uop_ctrl_op2_sel; // @[execution-unit.scala:437:7]
wire [2:0] io_req_bits_uop_ctrl_imm_sel_0 = io_req_bits_uop_ctrl_imm_sel; // @[execution-unit.scala:437:7]
wire [4:0] io_req_bits_uop_ctrl_op_fcn_0 = io_req_bits_uop_ctrl_op_fcn; // @[execution-unit.scala:437:7]
wire io_req_bits_uop_ctrl_fcn_dw_0 = io_req_bits_uop_ctrl_fcn_dw; // @[execution-unit.scala:437:7]
wire [2:0] io_req_bits_uop_ctrl_csr_cmd_0 = io_req_bits_uop_ctrl_csr_cmd; // @[execution-unit.scala:437:7]
wire io_req_bits_uop_ctrl_is_load_0 = io_req_bits_uop_ctrl_is_load; // @[execution-unit.scala:437:7]
wire io_req_bits_uop_ctrl_is_sta_0 = io_req_bits_uop_ctrl_is_sta; // @[execution-unit.scala:437:7]
wire io_req_bits_uop_ctrl_is_std_0 = io_req_bits_uop_ctrl_is_std; // @[execution-unit.scala:437:7]
wire [1:0] io_req_bits_uop_iw_state_0 = io_req_bits_uop_iw_state; // @[execution-unit.scala:437:7]
wire io_req_bits_uop_iw_p1_poisoned_0 = io_req_bits_uop_iw_p1_poisoned; // @[execution-unit.scala:437:7]
wire io_req_bits_uop_iw_p2_poisoned_0 = io_req_bits_uop_iw_p2_poisoned; // @[execution-unit.scala:437:7]
wire io_req_bits_uop_is_br_0 = io_req_bits_uop_is_br; // @[execution-unit.scala:437:7]
wire io_req_bits_uop_is_jalr_0 = io_req_bits_uop_is_jalr; // @[execution-unit.scala:437:7]
wire io_req_bits_uop_is_jal_0 = io_req_bits_uop_is_jal; // @[execution-unit.scala:437:7]
wire io_req_bits_uop_is_sfb_0 = io_req_bits_uop_is_sfb; // @[execution-unit.scala:437:7]
wire [15:0] io_req_bits_uop_br_mask_0 = io_req_bits_uop_br_mask; // @[execution-unit.scala:437:7]
wire [3:0] io_req_bits_uop_br_tag_0 = io_req_bits_uop_br_tag; // @[execution-unit.scala:437:7]
wire [4:0] io_req_bits_uop_ftq_idx_0 = io_req_bits_uop_ftq_idx; // @[execution-unit.scala:437:7]
wire io_req_bits_uop_edge_inst_0 = io_req_bits_uop_edge_inst; // @[execution-unit.scala:437:7]
wire [5:0] io_req_bits_uop_pc_lob_0 = io_req_bits_uop_pc_lob; // @[execution-unit.scala:437:7]
wire io_req_bits_uop_taken_0 = io_req_bits_uop_taken; // @[execution-unit.scala:437:7]
wire [19:0] io_req_bits_uop_imm_packed_0 = io_req_bits_uop_imm_packed; // @[execution-unit.scala:437:7]
wire [11:0] io_req_bits_uop_csr_addr_0 = io_req_bits_uop_csr_addr; // @[execution-unit.scala:437:7]
wire [6:0] io_req_bits_uop_rob_idx_0 = io_req_bits_uop_rob_idx; // @[execution-unit.scala:437:7]
wire [4:0] io_req_bits_uop_ldq_idx_0 = io_req_bits_uop_ldq_idx; // @[execution-unit.scala:437:7]
wire [4:0] io_req_bits_uop_stq_idx_0 = io_req_bits_uop_stq_idx; // @[execution-unit.scala:437:7]
wire [1:0] io_req_bits_uop_rxq_idx_0 = io_req_bits_uop_rxq_idx; // @[execution-unit.scala:437:7]
wire [6:0] io_req_bits_uop_pdst_0 = io_req_bits_uop_pdst; // @[execution-unit.scala:437:7]
wire [6:0] io_req_bits_uop_prs1_0 = io_req_bits_uop_prs1; // @[execution-unit.scala:437:7]
wire [6:0] io_req_bits_uop_prs2_0 = io_req_bits_uop_prs2; // @[execution-unit.scala:437:7]
wire [6:0] io_req_bits_uop_prs3_0 = io_req_bits_uop_prs3; // @[execution-unit.scala:437:7]
wire [4:0] io_req_bits_uop_ppred_0 = io_req_bits_uop_ppred; // @[execution-unit.scala:437:7]
wire io_req_bits_uop_prs1_busy_0 = io_req_bits_uop_prs1_busy; // @[execution-unit.scala:437:7]
wire io_req_bits_uop_prs2_busy_0 = io_req_bits_uop_prs2_busy; // @[execution-unit.scala:437:7]
wire io_req_bits_uop_prs3_busy_0 = io_req_bits_uop_prs3_busy; // @[execution-unit.scala:437:7]
wire io_req_bits_uop_ppred_busy_0 = io_req_bits_uop_ppred_busy; // @[execution-unit.scala:437:7]
wire [6:0] io_req_bits_uop_stale_pdst_0 = io_req_bits_uop_stale_pdst; // @[execution-unit.scala:437:7]
wire io_req_bits_uop_exception_0 = io_req_bits_uop_exception; // @[execution-unit.scala:437:7]
wire [63:0] io_req_bits_uop_exc_cause_0 = io_req_bits_uop_exc_cause; // @[execution-unit.scala:437:7]
wire io_req_bits_uop_bypassable_0 = io_req_bits_uop_bypassable; // @[execution-unit.scala:437:7]
wire [4:0] io_req_bits_uop_mem_cmd_0 = io_req_bits_uop_mem_cmd; // @[execution-unit.scala:437:7]
wire [1:0] io_req_bits_uop_mem_size_0 = io_req_bits_uop_mem_size; // @[execution-unit.scala:437:7]
wire io_req_bits_uop_mem_signed_0 = io_req_bits_uop_mem_signed; // @[execution-unit.scala:437:7]
wire io_req_bits_uop_is_fence_0 = io_req_bits_uop_is_fence; // @[execution-unit.scala:437:7]
wire io_req_bits_uop_is_fencei_0 = io_req_bits_uop_is_fencei; // @[execution-unit.scala:437:7]
wire io_req_bits_uop_is_amo_0 = io_req_bits_uop_is_amo; // @[execution-unit.scala:437:7]
wire io_req_bits_uop_uses_ldq_0 = io_req_bits_uop_uses_ldq; // @[execution-unit.scala:437:7]
wire io_req_bits_uop_uses_stq_0 = io_req_bits_uop_uses_stq; // @[execution-unit.scala:437:7]
wire io_req_bits_uop_is_sys_pc2epc_0 = io_req_bits_uop_is_sys_pc2epc; // @[execution-unit.scala:437:7]
wire io_req_bits_uop_is_unique_0 = io_req_bits_uop_is_unique; // @[execution-unit.scala:437:7]
wire io_req_bits_uop_flush_on_commit_0 = io_req_bits_uop_flush_on_commit; // @[execution-unit.scala:437:7]
wire io_req_bits_uop_ldst_is_rs1_0 = io_req_bits_uop_ldst_is_rs1; // @[execution-unit.scala:437:7]
wire [5:0] io_req_bits_uop_ldst_0 = io_req_bits_uop_ldst; // @[execution-unit.scala:437:7]
wire [5:0] io_req_bits_uop_lrs1_0 = io_req_bits_uop_lrs1; // @[execution-unit.scala:437:7]
wire [5:0] io_req_bits_uop_lrs2_0 = io_req_bits_uop_lrs2; // @[execution-unit.scala:437:7]
wire [5:0] io_req_bits_uop_lrs3_0 = io_req_bits_uop_lrs3; // @[execution-unit.scala:437:7]
wire io_req_bits_uop_ldst_val_0 = io_req_bits_uop_ldst_val; // @[execution-unit.scala:437:7]
wire [1:0] io_req_bits_uop_dst_rtype_0 = io_req_bits_uop_dst_rtype; // @[execution-unit.scala:437:7]
wire [1:0] io_req_bits_uop_lrs1_rtype_0 = io_req_bits_uop_lrs1_rtype; // @[execution-unit.scala:437:7]
wire [1:0] io_req_bits_uop_lrs2_rtype_0 = io_req_bits_uop_lrs2_rtype; // @[execution-unit.scala:437:7]
wire io_req_bits_uop_frs3_en_0 = io_req_bits_uop_frs3_en; // @[execution-unit.scala:437:7]
wire io_req_bits_uop_fp_val_0 = io_req_bits_uop_fp_val; // @[execution-unit.scala:437:7]
wire io_req_bits_uop_fp_single_0 = io_req_bits_uop_fp_single; // @[execution-unit.scala:437:7]
wire io_req_bits_uop_xcpt_pf_if_0 = io_req_bits_uop_xcpt_pf_if; // @[execution-unit.scala:437:7]
wire io_req_bits_uop_xcpt_ae_if_0 = io_req_bits_uop_xcpt_ae_if; // @[execution-unit.scala:437:7]
wire io_req_bits_uop_xcpt_ma_if_0 = io_req_bits_uop_xcpt_ma_if; // @[execution-unit.scala:437:7]
wire io_req_bits_uop_bp_debug_if_0 = io_req_bits_uop_bp_debug_if; // @[execution-unit.scala:437:7]
wire io_req_bits_uop_bp_xcpt_if_0 = io_req_bits_uop_bp_xcpt_if; // @[execution-unit.scala:437:7]
wire [1:0] io_req_bits_uop_debug_fsrc_0 = io_req_bits_uop_debug_fsrc; // @[execution-unit.scala:437:7]
wire [1:0] io_req_bits_uop_debug_tsrc_0 = io_req_bits_uop_debug_tsrc; // @[execution-unit.scala:437:7]
wire [64:0] io_req_bits_rs1_data_0 = io_req_bits_rs1_data; // @[execution-unit.scala:437:7]
wire [64:0] io_req_bits_rs2_data_0 = io_req_bits_rs2_data; // @[execution-unit.scala:437:7]
wire [64:0] io_req_bits_rs3_data_0 = io_req_bits_rs3_data; // @[execution-unit.scala:437:7]
wire io_req_bits_kill_0 = io_req_bits_kill; // @[execution-unit.scala:437:7]
wire io_ll_iresp_ready_0 = io_ll_iresp_ready; // @[execution-unit.scala:437:7]
wire [15:0] io_brupdate_b1_resolve_mask_0 = io_brupdate_b1_resolve_mask; // @[execution-unit.scala:437:7]
wire [15:0] io_brupdate_b1_mispredict_mask_0 = io_brupdate_b1_mispredict_mask; // @[execution-unit.scala:437:7]
wire [6:0] io_brupdate_b2_uop_uopc_0 = io_brupdate_b2_uop_uopc; // @[execution-unit.scala:437:7]
wire [31:0] io_brupdate_b2_uop_inst_0 = io_brupdate_b2_uop_inst; // @[execution-unit.scala:437:7]
wire [31:0] io_brupdate_b2_uop_debug_inst_0 = io_brupdate_b2_uop_debug_inst; // @[execution-unit.scala:437:7]
wire io_brupdate_b2_uop_is_rvc_0 = io_brupdate_b2_uop_is_rvc; // @[execution-unit.scala:437:7]
wire [39:0] io_brupdate_b2_uop_debug_pc_0 = io_brupdate_b2_uop_debug_pc; // @[execution-unit.scala:437:7]
wire [2:0] io_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type; // @[execution-unit.scala:437:7]
wire [9:0] io_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code; // @[execution-unit.scala:437:7]
wire [3:0] io_brupdate_b2_uop_ctrl_br_type_0 = io_brupdate_b2_uop_ctrl_br_type; // @[execution-unit.scala:437:7]
wire [1:0] io_brupdate_b2_uop_ctrl_op1_sel_0 = io_brupdate_b2_uop_ctrl_op1_sel; // @[execution-unit.scala:437:7]
wire [2:0] io_brupdate_b2_uop_ctrl_op2_sel_0 = io_brupdate_b2_uop_ctrl_op2_sel; // @[execution-unit.scala:437:7]
wire [2:0] io_brupdate_b2_uop_ctrl_imm_sel_0 = io_brupdate_b2_uop_ctrl_imm_sel; // @[execution-unit.scala:437:7]
wire [4:0] io_brupdate_b2_uop_ctrl_op_fcn_0 = io_brupdate_b2_uop_ctrl_op_fcn; // @[execution-unit.scala:437:7]
wire io_brupdate_b2_uop_ctrl_fcn_dw_0 = io_brupdate_b2_uop_ctrl_fcn_dw; // @[execution-unit.scala:437:7]
wire [2:0] io_brupdate_b2_uop_ctrl_csr_cmd_0 = io_brupdate_b2_uop_ctrl_csr_cmd; // @[execution-unit.scala:437:7]
wire io_brupdate_b2_uop_ctrl_is_load_0 = io_brupdate_b2_uop_ctrl_is_load; // @[execution-unit.scala:437:7]
wire io_brupdate_b2_uop_ctrl_is_sta_0 = io_brupdate_b2_uop_ctrl_is_sta; // @[execution-unit.scala:437:7]
wire io_brupdate_b2_uop_ctrl_is_std_0 = io_brupdate_b2_uop_ctrl_is_std; // @[execution-unit.scala:437:7]
wire [1:0] io_brupdate_b2_uop_iw_state_0 = io_brupdate_b2_uop_iw_state; // @[execution-unit.scala:437:7]
wire io_brupdate_b2_uop_iw_p1_poisoned_0 = io_brupdate_b2_uop_iw_p1_poisoned; // @[execution-unit.scala:437:7]
wire io_brupdate_b2_uop_iw_p2_poisoned_0 = io_brupdate_b2_uop_iw_p2_poisoned; // @[execution-unit.scala:437:7]
wire io_brupdate_b2_uop_is_br_0 = io_brupdate_b2_uop_is_br; // @[execution-unit.scala:437:7]
wire io_brupdate_b2_uop_is_jalr_0 = io_brupdate_b2_uop_is_jalr; // @[execution-unit.scala:437:7]
wire io_brupdate_b2_uop_is_jal_0 = io_brupdate_b2_uop_is_jal; // @[execution-unit.scala:437:7]
wire io_brupdate_b2_uop_is_sfb_0 = io_brupdate_b2_uop_is_sfb; // @[execution-unit.scala:437:7]
wire [15:0] io_brupdate_b2_uop_br_mask_0 = io_brupdate_b2_uop_br_mask; // @[execution-unit.scala:437:7]
wire [3:0] io_brupdate_b2_uop_br_tag_0 = io_brupdate_b2_uop_br_tag; // @[execution-unit.scala:437:7]
wire [4:0] io_brupdate_b2_uop_ftq_idx_0 = io_brupdate_b2_uop_ftq_idx; // @[execution-unit.scala:437:7]
wire io_brupdate_b2_uop_edge_inst_0 = io_brupdate_b2_uop_edge_inst; // @[execution-unit.scala:437:7]
wire [5:0] io_brupdate_b2_uop_pc_lob_0 = io_brupdate_b2_uop_pc_lob; // @[execution-unit.scala:437:7]
wire io_brupdate_b2_uop_taken_0 = io_brupdate_b2_uop_taken; // @[execution-unit.scala:437:7]
wire [19:0] io_brupdate_b2_uop_imm_packed_0 = io_brupdate_b2_uop_imm_packed; // @[execution-unit.scala:437:7]
wire [11:0] io_brupdate_b2_uop_csr_addr_0 = io_brupdate_b2_uop_csr_addr; // @[execution-unit.scala:437:7]
wire [6:0] io_brupdate_b2_uop_rob_idx_0 = io_brupdate_b2_uop_rob_idx; // @[execution-unit.scala:437:7]
wire [4:0] io_brupdate_b2_uop_ldq_idx_0 = io_brupdate_b2_uop_ldq_idx; // @[execution-unit.scala:437:7]
wire [4:0] io_brupdate_b2_uop_stq_idx_0 = io_brupdate_b2_uop_stq_idx; // @[execution-unit.scala:437:7]
wire [1:0] io_brupdate_b2_uop_rxq_idx_0 = io_brupdate_b2_uop_rxq_idx; // @[execution-unit.scala:437:7]
wire [6:0] io_brupdate_b2_uop_pdst_0 = io_brupdate_b2_uop_pdst; // @[execution-unit.scala:437:7]
wire [6:0] io_brupdate_b2_uop_prs1_0 = io_brupdate_b2_uop_prs1; // @[execution-unit.scala:437:7]
wire [6:0] io_brupdate_b2_uop_prs2_0 = io_brupdate_b2_uop_prs2; // @[execution-unit.scala:437:7]
wire [6:0] io_brupdate_b2_uop_prs3_0 = io_brupdate_b2_uop_prs3; // @[execution-unit.scala:437:7]
wire [4:0] io_brupdate_b2_uop_ppred_0 = io_brupdate_b2_uop_ppred; // @[execution-unit.scala:437:7]
wire io_brupdate_b2_uop_prs1_busy_0 = io_brupdate_b2_uop_prs1_busy; // @[execution-unit.scala:437:7]
wire io_brupdate_b2_uop_prs2_busy_0 = io_brupdate_b2_uop_prs2_busy; // @[execution-unit.scala:437:7]
wire io_brupdate_b2_uop_prs3_busy_0 = io_brupdate_b2_uop_prs3_busy; // @[execution-unit.scala:437:7]
wire io_brupdate_b2_uop_ppred_busy_0 = io_brupdate_b2_uop_ppred_busy; // @[execution-unit.scala:437:7]
wire [6:0] io_brupdate_b2_uop_stale_pdst_0 = io_brupdate_b2_uop_stale_pdst; // @[execution-unit.scala:437:7]
wire io_brupdate_b2_uop_exception_0 = io_brupdate_b2_uop_exception; // @[execution-unit.scala:437:7]
wire [63:0] io_brupdate_b2_uop_exc_cause_0 = io_brupdate_b2_uop_exc_cause; // @[execution-unit.scala:437:7]
wire io_brupdate_b2_uop_bypassable_0 = io_brupdate_b2_uop_bypassable; // @[execution-unit.scala:437:7]
wire [4:0] io_brupdate_b2_uop_mem_cmd_0 = io_brupdate_b2_uop_mem_cmd; // @[execution-unit.scala:437:7]
wire [1:0] io_brupdate_b2_uop_mem_size_0 = io_brupdate_b2_uop_mem_size; // @[execution-unit.scala:437:7]
wire io_brupdate_b2_uop_mem_signed_0 = io_brupdate_b2_uop_mem_signed; // @[execution-unit.scala:437:7]
wire io_brupdate_b2_uop_is_fence_0 = io_brupdate_b2_uop_is_fence; // @[execution-unit.scala:437:7]
wire io_brupdate_b2_uop_is_fencei_0 = io_brupdate_b2_uop_is_fencei; // @[execution-unit.scala:437:7]
wire io_brupdate_b2_uop_is_amo_0 = io_brupdate_b2_uop_is_amo; // @[execution-unit.scala:437:7]
wire io_brupdate_b2_uop_uses_ldq_0 = io_brupdate_b2_uop_uses_ldq; // @[execution-unit.scala:437:7]
wire io_brupdate_b2_uop_uses_stq_0 = io_brupdate_b2_uop_uses_stq; // @[execution-unit.scala:437:7]
wire io_brupdate_b2_uop_is_sys_pc2epc_0 = io_brupdate_b2_uop_is_sys_pc2epc; // @[execution-unit.scala:437:7]
wire io_brupdate_b2_uop_is_unique_0 = io_brupdate_b2_uop_is_unique; // @[execution-unit.scala:437:7]
wire io_brupdate_b2_uop_flush_on_commit_0 = io_brupdate_b2_uop_flush_on_commit; // @[execution-unit.scala:437:7]
wire io_brupdate_b2_uop_ldst_is_rs1_0 = io_brupdate_b2_uop_ldst_is_rs1; // @[execution-unit.scala:437:7]
wire [5:0] io_brupdate_b2_uop_ldst_0 = io_brupdate_b2_uop_ldst; // @[execution-unit.scala:437:7]
wire [5:0] io_brupdate_b2_uop_lrs1_0 = io_brupdate_b2_uop_lrs1; // @[execution-unit.scala:437:7]
wire [5:0] io_brupdate_b2_uop_lrs2_0 = io_brupdate_b2_uop_lrs2; // @[execution-unit.scala:437:7]
wire [5:0] io_brupdate_b2_uop_lrs3_0 = io_brupdate_b2_uop_lrs3; // @[execution-unit.scala:437:7]
wire io_brupdate_b2_uop_ldst_val_0 = io_brupdate_b2_uop_ldst_val; // @[execution-unit.scala:437:7]
wire [1:0] io_brupdate_b2_uop_dst_rtype_0 = io_brupdate_b2_uop_dst_rtype; // @[execution-unit.scala:437:7]
wire [1:0] io_brupdate_b2_uop_lrs1_rtype_0 = io_brupdate_b2_uop_lrs1_rtype; // @[execution-unit.scala:437:7]
wire [1:0] io_brupdate_b2_uop_lrs2_rtype_0 = io_brupdate_b2_uop_lrs2_rtype; // @[execution-unit.scala:437:7]
wire io_brupdate_b2_uop_frs3_en_0 = io_brupdate_b2_uop_frs3_en; // @[execution-unit.scala:437:7]
wire io_brupdate_b2_uop_fp_val_0 = io_brupdate_b2_uop_fp_val; // @[execution-unit.scala:437:7]
wire io_brupdate_b2_uop_fp_single_0 = io_brupdate_b2_uop_fp_single; // @[execution-unit.scala:437:7]
wire io_brupdate_b2_uop_xcpt_pf_if_0 = io_brupdate_b2_uop_xcpt_pf_if; // @[execution-unit.scala:437:7]
wire io_brupdate_b2_uop_xcpt_ae_if_0 = io_brupdate_b2_uop_xcpt_ae_if; // @[execution-unit.scala:437:7]
wire io_brupdate_b2_uop_xcpt_ma_if_0 = io_brupdate_b2_uop_xcpt_ma_if; // @[execution-unit.scala:437:7]
wire io_brupdate_b2_uop_bp_debug_if_0 = io_brupdate_b2_uop_bp_debug_if; // @[execution-unit.scala:437:7]
wire io_brupdate_b2_uop_bp_xcpt_if_0 = io_brupdate_b2_uop_bp_xcpt_if; // @[execution-unit.scala:437:7]
wire [1:0] io_brupdate_b2_uop_debug_fsrc_0 = io_brupdate_b2_uop_debug_fsrc; // @[execution-unit.scala:437:7]
wire [1:0] io_brupdate_b2_uop_debug_tsrc_0 = io_brupdate_b2_uop_debug_tsrc; // @[execution-unit.scala:437:7]
wire io_brupdate_b2_valid_0 = io_brupdate_b2_valid; // @[execution-unit.scala:437:7]
wire io_brupdate_b2_mispredict_0 = io_brupdate_b2_mispredict; // @[execution-unit.scala:437:7]
wire io_brupdate_b2_taken_0 = io_brupdate_b2_taken; // @[execution-unit.scala:437:7]
wire [2:0] io_brupdate_b2_cfi_type_0 = io_brupdate_b2_cfi_type; // @[execution-unit.scala:437:7]
wire [1:0] io_brupdate_b2_pc_sel_0 = io_brupdate_b2_pc_sel; // @[execution-unit.scala:437:7]
wire [39:0] io_brupdate_b2_jalr_target_0 = io_brupdate_b2_jalr_target; // @[execution-unit.scala:437:7]
wire [20:0] io_brupdate_b2_target_offset_0 = io_brupdate_b2_target_offset; // @[execution-unit.scala:437:7]
wire io_status_debug_0 = io_status_debug; // @[execution-unit.scala:437:7]
wire io_status_cease_0 = io_status_cease; // @[execution-unit.scala:437:7]
wire io_status_wfi_0 = io_status_wfi; // @[execution-unit.scala:437:7]
wire [1:0] io_status_dprv_0 = io_status_dprv; // @[execution-unit.scala:437:7]
wire io_status_dv_0 = io_status_dv; // @[execution-unit.scala:437:7]
wire [1:0] io_status_prv_0 = io_status_prv; // @[execution-unit.scala:437:7]
wire io_status_v_0 = io_status_v; // @[execution-unit.scala:437:7]
wire io_status_sd_0 = io_status_sd; // @[execution-unit.scala:437:7]
wire io_status_mpv_0 = io_status_mpv; // @[execution-unit.scala:437:7]
wire io_status_gva_0 = io_status_gva; // @[execution-unit.scala:437:7]
wire io_status_tsr_0 = io_status_tsr; // @[execution-unit.scala:437:7]
wire io_status_tw_0 = io_status_tw; // @[execution-unit.scala:437:7]
wire io_status_tvm_0 = io_status_tvm; // @[execution-unit.scala:437:7]
wire io_status_mxr_0 = io_status_mxr; // @[execution-unit.scala:437:7]
wire io_status_sum_0 = io_status_sum; // @[execution-unit.scala:437:7]
wire io_status_mprv_0 = io_status_mprv; // @[execution-unit.scala:437:7]
wire [1:0] io_status_fs_0 = io_status_fs; // @[execution-unit.scala:437:7]
wire [1:0] io_status_mpp_0 = io_status_mpp; // @[execution-unit.scala:437:7]
wire io_status_spp_0 = io_status_spp; // @[execution-unit.scala:437:7]
wire io_status_mpie_0 = io_status_mpie; // @[execution-unit.scala:437:7]
wire io_status_spie_0 = io_status_spie; // @[execution-unit.scala:437:7]
wire io_status_mie_0 = io_status_mie; // @[execution-unit.scala:437:7]
wire io_status_sie_0 = io_status_sie; // @[execution-unit.scala:437:7]
wire [2:0] io_fcsr_rm_0 = io_fcsr_rm; // @[execution-unit.scala:437:7]
wire [31:0] io_status_isa = 32'h14112D; // @[execution-unit.scala:437:7]
wire [22:0] io_status_zero2 = 23'h0; // @[execution-unit.scala:437:7]
wire io_req_ready = 1'h0; // @[execution-unit.scala:437:7]
wire io_req_bits_pred_data = 1'h0; // @[execution-unit.scala:437:7]
wire io_fresp_bits_predicated = 1'h0; // @[execution-unit.scala:437:7]
wire io_status_mbe = 1'h0; // @[execution-unit.scala:437:7]
wire io_status_sbe = 1'h0; // @[execution-unit.scala:437:7]
wire io_status_sd_rv32 = 1'h0; // @[execution-unit.scala:437:7]
wire io_status_ube = 1'h0; // @[execution-unit.scala:437:7]
wire io_status_upie = 1'h0; // @[execution-unit.scala:437:7]
wire io_status_hie = 1'h0; // @[execution-unit.scala:437:7]
wire io_status_uie = 1'h0; // @[execution-unit.scala:437:7]
wire [7:0] io_status_zero1 = 8'h0; // @[execution-unit.scala:437:7]
wire [1:0] io_status_xs = 2'h0; // @[execution-unit.scala:437:7]
wire [1:0] io_status_vs = 2'h0; // @[execution-unit.scala:437:7]
wire io_fresp_ready = 1'h1; // @[execution-unit.scala:437:7]
wire [1:0] io_status_sxl = 2'h2; // @[execution-unit.scala:437:7]
wire [1:0] io_status_uxl = 2'h2; // @[execution-unit.scala:437:7]
wire [9:0] _io_fu_types_T = 10'h40; // @[execution-unit.scala:467:21]
wire [9:0] _io_fu_types_T_8; // @[execution-unit.scala:468:60]
wire _io_fresp_valid_T_5; // @[execution-unit.scala:525:69]
wire [6:0] _io_fresp_bits_uop_T_uopc; // @[Mux.scala:50:70]
wire [31:0] _io_fresp_bits_uop_T_inst; // @[Mux.scala:50:70]
wire [31:0] _io_fresp_bits_uop_T_debug_inst; // @[Mux.scala:50:70]
wire _io_fresp_bits_uop_T_is_rvc; // @[Mux.scala:50:70]
wire [39:0] _io_fresp_bits_uop_T_debug_pc; // @[Mux.scala:50:70]
wire [2:0] _io_fresp_bits_uop_T_iq_type; // @[Mux.scala:50:70]
wire [9:0] _io_fresp_bits_uop_T_fu_code; // @[Mux.scala:50:70]
wire [3:0] _io_fresp_bits_uop_T_ctrl_br_type; // @[Mux.scala:50:70]
wire [1:0] _io_fresp_bits_uop_T_ctrl_op1_sel; // @[Mux.scala:50:70]
wire [2:0] _io_fresp_bits_uop_T_ctrl_op2_sel; // @[Mux.scala:50:70]
wire [2:0] _io_fresp_bits_uop_T_ctrl_imm_sel; // @[Mux.scala:50:70]
wire [4:0] _io_fresp_bits_uop_T_ctrl_op_fcn; // @[Mux.scala:50:70]
wire _io_fresp_bits_uop_T_ctrl_fcn_dw; // @[Mux.scala:50:70]
wire [2:0] _io_fresp_bits_uop_T_ctrl_csr_cmd; // @[Mux.scala:50:70]
wire _io_fresp_bits_uop_T_ctrl_is_load; // @[Mux.scala:50:70]
wire _io_fresp_bits_uop_T_ctrl_is_sta; // @[Mux.scala:50:70]
wire _io_fresp_bits_uop_T_ctrl_is_std; // @[Mux.scala:50:70]
wire [1:0] _io_fresp_bits_uop_T_iw_state; // @[Mux.scala:50:70]
wire _io_fresp_bits_uop_T_iw_p1_poisoned; // @[Mux.scala:50:70]
wire _io_fresp_bits_uop_T_iw_p2_poisoned; // @[Mux.scala:50:70]
wire _io_fresp_bits_uop_T_is_br; // @[Mux.scala:50:70]
wire _io_fresp_bits_uop_T_is_jalr; // @[Mux.scala:50:70]
wire _io_fresp_bits_uop_T_is_jal; // @[Mux.scala:50:70]
wire _io_fresp_bits_uop_T_is_sfb; // @[Mux.scala:50:70]
wire [15:0] _io_fresp_bits_uop_T_br_mask; // @[Mux.scala:50:70]
wire [3:0] _io_fresp_bits_uop_T_br_tag; // @[Mux.scala:50:70]
wire [4:0] _io_fresp_bits_uop_T_ftq_idx; // @[Mux.scala:50:70]
wire _io_fresp_bits_uop_T_edge_inst; // @[Mux.scala:50:70]
wire [5:0] _io_fresp_bits_uop_T_pc_lob; // @[Mux.scala:50:70]
wire _io_fresp_bits_uop_T_taken; // @[Mux.scala:50:70]
wire [19:0] _io_fresp_bits_uop_T_imm_packed; // @[Mux.scala:50:70]
wire [11:0] _io_fresp_bits_uop_T_csr_addr; // @[Mux.scala:50:70]
wire [6:0] _io_fresp_bits_uop_T_rob_idx; // @[Mux.scala:50:70]
wire [4:0] _io_fresp_bits_uop_T_ldq_idx; // @[Mux.scala:50:70]
wire [4:0] _io_fresp_bits_uop_T_stq_idx; // @[Mux.scala:50:70]
wire [1:0] _io_fresp_bits_uop_T_rxq_idx; // @[Mux.scala:50:70]
wire [6:0] _io_fresp_bits_uop_T_pdst; // @[Mux.scala:50:70]
wire [6:0] _io_fresp_bits_uop_T_prs1; // @[Mux.scala:50:70]
wire [6:0] _io_fresp_bits_uop_T_prs2; // @[Mux.scala:50:70]
wire [6:0] _io_fresp_bits_uop_T_prs3; // @[Mux.scala:50:70]
wire [4:0] _io_fresp_bits_uop_T_ppred; // @[Mux.scala:50:70]
wire _io_fresp_bits_uop_T_prs1_busy; // @[Mux.scala:50:70]
wire _io_fresp_bits_uop_T_prs2_busy; // @[Mux.scala:50:70]
wire _io_fresp_bits_uop_T_prs3_busy; // @[Mux.scala:50:70]
wire _io_fresp_bits_uop_T_ppred_busy; // @[Mux.scala:50:70]
wire [6:0] _io_fresp_bits_uop_T_stale_pdst; // @[Mux.scala:50:70]
wire _io_fresp_bits_uop_T_exception; // @[Mux.scala:50:70]
wire [63:0] _io_fresp_bits_uop_T_exc_cause; // @[Mux.scala:50:70]
wire _io_fresp_bits_uop_T_bypassable; // @[Mux.scala:50:70]
wire [4:0] _io_fresp_bits_uop_T_mem_cmd; // @[Mux.scala:50:70]
wire [1:0] _io_fresp_bits_uop_T_mem_size; // @[Mux.scala:50:70]
wire _io_fresp_bits_uop_T_mem_signed; // @[Mux.scala:50:70]
wire _io_fresp_bits_uop_T_is_fence; // @[Mux.scala:50:70]
wire _io_fresp_bits_uop_T_is_fencei; // @[Mux.scala:50:70]
wire _io_fresp_bits_uop_T_is_amo; // @[Mux.scala:50:70]
wire _io_fresp_bits_uop_T_uses_ldq; // @[Mux.scala:50:70]
wire _io_fresp_bits_uop_T_uses_stq; // @[Mux.scala:50:70]
wire _io_fresp_bits_uop_T_is_sys_pc2epc; // @[Mux.scala:50:70]
wire _io_fresp_bits_uop_T_is_unique; // @[Mux.scala:50:70]
wire _io_fresp_bits_uop_T_flush_on_commit; // @[Mux.scala:50:70]
wire _io_fresp_bits_uop_T_ldst_is_rs1; // @[Mux.scala:50:70]
wire [5:0] _io_fresp_bits_uop_T_ldst; // @[Mux.scala:50:70]
wire [5:0] _io_fresp_bits_uop_T_lrs1; // @[Mux.scala:50:70]
wire [5:0] _io_fresp_bits_uop_T_lrs2; // @[Mux.scala:50:70]
wire [5:0] _io_fresp_bits_uop_T_lrs3; // @[Mux.scala:50:70]
wire _io_fresp_bits_uop_T_ldst_val; // @[Mux.scala:50:70]
wire [1:0] _io_fresp_bits_uop_T_dst_rtype; // @[Mux.scala:50:70]
wire [1:0] _io_fresp_bits_uop_T_lrs1_rtype; // @[Mux.scala:50:70]
wire [1:0] _io_fresp_bits_uop_T_lrs2_rtype; // @[Mux.scala:50:70]
wire _io_fresp_bits_uop_T_frs3_en; // @[Mux.scala:50:70]
wire _io_fresp_bits_uop_T_fp_val; // @[Mux.scala:50:70]
wire _io_fresp_bits_uop_T_fp_single; // @[Mux.scala:50:70]
wire _io_fresp_bits_uop_T_xcpt_pf_if; // @[Mux.scala:50:70]
wire _io_fresp_bits_uop_T_xcpt_ae_if; // @[Mux.scala:50:70]
wire _io_fresp_bits_uop_T_xcpt_ma_if; // @[Mux.scala:50:70]
wire _io_fresp_bits_uop_T_bp_debug_if; // @[Mux.scala:50:70]
wire _io_fresp_bits_uop_T_bp_xcpt_if; // @[Mux.scala:50:70]
wire [1:0] _io_fresp_bits_uop_T_debug_fsrc; // @[Mux.scala:50:70]
wire [1:0] _io_fresp_bits_uop_T_debug_tsrc; // @[Mux.scala:50:70]
wire [64:0] _io_fresp_bits_data_T; // @[Mux.scala:50:70]
wire _io_fresp_bits_fflags_T_valid; // @[execution-unit.scala:530:30]
wire [6:0] _io_fresp_bits_fflags_T_bits_uop_uopc; // @[execution-unit.scala:530:30]
wire [31:0] _io_fresp_bits_fflags_T_bits_uop_inst; // @[execution-unit.scala:530:30]
wire [31:0] _io_fresp_bits_fflags_T_bits_uop_debug_inst; // @[execution-unit.scala:530:30]
wire _io_fresp_bits_fflags_T_bits_uop_is_rvc; // @[execution-unit.scala:530:30]
wire [39:0] _io_fresp_bits_fflags_T_bits_uop_debug_pc; // @[execution-unit.scala:530:30]
wire [2:0] _io_fresp_bits_fflags_T_bits_uop_iq_type; // @[execution-unit.scala:530:30]
wire [9:0] _io_fresp_bits_fflags_T_bits_uop_fu_code; // @[execution-unit.scala:530:30]
wire [3:0] _io_fresp_bits_fflags_T_bits_uop_ctrl_br_type; // @[execution-unit.scala:530:30]
wire [1:0] _io_fresp_bits_fflags_T_bits_uop_ctrl_op1_sel; // @[execution-unit.scala:530:30]
wire [2:0] _io_fresp_bits_fflags_T_bits_uop_ctrl_op2_sel; // @[execution-unit.scala:530:30]
wire [2:0] _io_fresp_bits_fflags_T_bits_uop_ctrl_imm_sel; // @[execution-unit.scala:530:30]
wire [4:0] _io_fresp_bits_fflags_T_bits_uop_ctrl_op_fcn; // @[execution-unit.scala:530:30]
wire _io_fresp_bits_fflags_T_bits_uop_ctrl_fcn_dw; // @[execution-unit.scala:530:30]
wire [2:0] _io_fresp_bits_fflags_T_bits_uop_ctrl_csr_cmd; // @[execution-unit.scala:530:30]
wire _io_fresp_bits_fflags_T_bits_uop_ctrl_is_load; // @[execution-unit.scala:530:30]
wire _io_fresp_bits_fflags_T_bits_uop_ctrl_is_sta; // @[execution-unit.scala:530:30]
wire _io_fresp_bits_fflags_T_bits_uop_ctrl_is_std; // @[execution-unit.scala:530:30]
wire [1:0] _io_fresp_bits_fflags_T_bits_uop_iw_state; // @[execution-unit.scala:530:30]
wire _io_fresp_bits_fflags_T_bits_uop_iw_p1_poisoned; // @[execution-unit.scala:530:30]
wire _io_fresp_bits_fflags_T_bits_uop_iw_p2_poisoned; // @[execution-unit.scala:530:30]
wire _io_fresp_bits_fflags_T_bits_uop_is_br; // @[execution-unit.scala:530:30]
wire _io_fresp_bits_fflags_T_bits_uop_is_jalr; // @[execution-unit.scala:530:30]
wire _io_fresp_bits_fflags_T_bits_uop_is_jal; // @[execution-unit.scala:530:30]
wire _io_fresp_bits_fflags_T_bits_uop_is_sfb; // @[execution-unit.scala:530:30]
wire [15:0] _io_fresp_bits_fflags_T_bits_uop_br_mask; // @[execution-unit.scala:530:30]
wire [3:0] _io_fresp_bits_fflags_T_bits_uop_br_tag; // @[execution-unit.scala:530:30]
wire [4:0] _io_fresp_bits_fflags_T_bits_uop_ftq_idx; // @[execution-unit.scala:530:30]
wire _io_fresp_bits_fflags_T_bits_uop_edge_inst; // @[execution-unit.scala:530:30]
wire [5:0] _io_fresp_bits_fflags_T_bits_uop_pc_lob; // @[execution-unit.scala:530:30]
wire _io_fresp_bits_fflags_T_bits_uop_taken; // @[execution-unit.scala:530:30]
wire [19:0] _io_fresp_bits_fflags_T_bits_uop_imm_packed; // @[execution-unit.scala:530:30]
wire [11:0] _io_fresp_bits_fflags_T_bits_uop_csr_addr; // @[execution-unit.scala:530:30]
wire [6:0] _io_fresp_bits_fflags_T_bits_uop_rob_idx; // @[execution-unit.scala:530:30]
wire [4:0] _io_fresp_bits_fflags_T_bits_uop_ldq_idx; // @[execution-unit.scala:530:30]
wire [4:0] _io_fresp_bits_fflags_T_bits_uop_stq_idx; // @[execution-unit.scala:530:30]
wire [1:0] _io_fresp_bits_fflags_T_bits_uop_rxq_idx; // @[execution-unit.scala:530:30]
wire [6:0] _io_fresp_bits_fflags_T_bits_uop_pdst; // @[execution-unit.scala:530:30]
wire [6:0] _io_fresp_bits_fflags_T_bits_uop_prs1; // @[execution-unit.scala:530:30]
wire [6:0] _io_fresp_bits_fflags_T_bits_uop_prs2; // @[execution-unit.scala:530:30]
wire [6:0] _io_fresp_bits_fflags_T_bits_uop_prs3; // @[execution-unit.scala:530:30]
wire [4:0] _io_fresp_bits_fflags_T_bits_uop_ppred; // @[execution-unit.scala:530:30]
wire _io_fresp_bits_fflags_T_bits_uop_prs1_busy; // @[execution-unit.scala:530:30]
wire _io_fresp_bits_fflags_T_bits_uop_prs2_busy; // @[execution-unit.scala:530:30]
wire _io_fresp_bits_fflags_T_bits_uop_prs3_busy; // @[execution-unit.scala:530:30]
wire _io_fresp_bits_fflags_T_bits_uop_ppred_busy; // @[execution-unit.scala:530:30]
wire [6:0] _io_fresp_bits_fflags_T_bits_uop_stale_pdst; // @[execution-unit.scala:530:30]
wire _io_fresp_bits_fflags_T_bits_uop_exception; // @[execution-unit.scala:530:30]
wire [63:0] _io_fresp_bits_fflags_T_bits_uop_exc_cause; // @[execution-unit.scala:530:30]
wire _io_fresp_bits_fflags_T_bits_uop_bypassable; // @[execution-unit.scala:530:30]
wire [4:0] _io_fresp_bits_fflags_T_bits_uop_mem_cmd; // @[execution-unit.scala:530:30]
wire [1:0] _io_fresp_bits_fflags_T_bits_uop_mem_size; // @[execution-unit.scala:530:30]
wire _io_fresp_bits_fflags_T_bits_uop_mem_signed; // @[execution-unit.scala:530:30]
wire _io_fresp_bits_fflags_T_bits_uop_is_fence; // @[execution-unit.scala:530:30]
wire _io_fresp_bits_fflags_T_bits_uop_is_fencei; // @[execution-unit.scala:530:30]
wire _io_fresp_bits_fflags_T_bits_uop_is_amo; // @[execution-unit.scala:530:30]
wire _io_fresp_bits_fflags_T_bits_uop_uses_ldq; // @[execution-unit.scala:530:30]
wire _io_fresp_bits_fflags_T_bits_uop_uses_stq; // @[execution-unit.scala:530:30]
wire _io_fresp_bits_fflags_T_bits_uop_is_sys_pc2epc; // @[execution-unit.scala:530:30]
wire _io_fresp_bits_fflags_T_bits_uop_is_unique; // @[execution-unit.scala:530:30]
wire _io_fresp_bits_fflags_T_bits_uop_flush_on_commit; // @[execution-unit.scala:530:30]
wire _io_fresp_bits_fflags_T_bits_uop_ldst_is_rs1; // @[execution-unit.scala:530:30]
wire [5:0] _io_fresp_bits_fflags_T_bits_uop_ldst; // @[execution-unit.scala:530:30]
wire [5:0] _io_fresp_bits_fflags_T_bits_uop_lrs1; // @[execution-unit.scala:530:30]
wire [5:0] _io_fresp_bits_fflags_T_bits_uop_lrs2; // @[execution-unit.scala:530:30]
wire [5:0] _io_fresp_bits_fflags_T_bits_uop_lrs3; // @[execution-unit.scala:530:30]
wire _io_fresp_bits_fflags_T_bits_uop_ldst_val; // @[execution-unit.scala:530:30]
wire [1:0] _io_fresp_bits_fflags_T_bits_uop_dst_rtype; // @[execution-unit.scala:530:30]
wire [1:0] _io_fresp_bits_fflags_T_bits_uop_lrs1_rtype; // @[execution-unit.scala:530:30]
wire [1:0] _io_fresp_bits_fflags_T_bits_uop_lrs2_rtype; // @[execution-unit.scala:530:30]
wire _io_fresp_bits_fflags_T_bits_uop_frs3_en; // @[execution-unit.scala:530:30]
wire _io_fresp_bits_fflags_T_bits_uop_fp_val; // @[execution-unit.scala:530:30]
wire _io_fresp_bits_fflags_T_bits_uop_fp_single; // @[execution-unit.scala:530:30]
wire _io_fresp_bits_fflags_T_bits_uop_xcpt_pf_if; // @[execution-unit.scala:530:30]
wire _io_fresp_bits_fflags_T_bits_uop_xcpt_ae_if; // @[execution-unit.scala:530:30]
wire _io_fresp_bits_fflags_T_bits_uop_xcpt_ma_if; // @[execution-unit.scala:530:30]
wire _io_fresp_bits_fflags_T_bits_uop_bp_debug_if; // @[execution-unit.scala:530:30]
wire _io_fresp_bits_fflags_T_bits_uop_bp_xcpt_if; // @[execution-unit.scala:530:30]
wire [1:0] _io_fresp_bits_fflags_T_bits_uop_debug_fsrc; // @[execution-unit.scala:530:30]
wire [1:0] _io_fresp_bits_fflags_T_bits_uop_debug_tsrc; // @[execution-unit.scala:530:30]
wire [4:0] _io_fresp_bits_fflags_T_bits_flags; // @[execution-unit.scala:530:30]
wire [3:0] io_fresp_bits_uop_ctrl_br_type_0; // @[execution-unit.scala:437:7]
wire [1:0] io_fresp_bits_uop_ctrl_op1_sel_0; // @[execution-unit.scala:437:7]
wire [2:0] io_fresp_bits_uop_ctrl_op2_sel_0; // @[execution-unit.scala:437:7]
wire [2:0] io_fresp_bits_uop_ctrl_imm_sel_0; // @[execution-unit.scala:437:7]
wire [4:0] io_fresp_bits_uop_ctrl_op_fcn_0; // @[execution-unit.scala:437:7]
wire io_fresp_bits_uop_ctrl_fcn_dw_0; // @[execution-unit.scala:437:7]
wire [2:0] io_fresp_bits_uop_ctrl_csr_cmd_0; // @[execution-unit.scala:437:7]
wire io_fresp_bits_uop_ctrl_is_load_0; // @[execution-unit.scala:437:7]
wire io_fresp_bits_uop_ctrl_is_sta_0; // @[execution-unit.scala:437:7]
wire io_fresp_bits_uop_ctrl_is_std_0; // @[execution-unit.scala:437:7]
wire [6:0] io_fresp_bits_uop_uopc_0; // @[execution-unit.scala:437:7]
wire [31:0] io_fresp_bits_uop_inst_0; // @[execution-unit.scala:437:7]
wire [31:0] io_fresp_bits_uop_debug_inst_0; // @[execution-unit.scala:437:7]
wire io_fresp_bits_uop_is_rvc_0; // @[execution-unit.scala:437:7]
wire [39:0] io_fresp_bits_uop_debug_pc_0; // @[execution-unit.scala:437:7]
wire [2:0] io_fresp_bits_uop_iq_type_0; // @[execution-unit.scala:437:7]
wire [9:0] io_fresp_bits_uop_fu_code_0; // @[execution-unit.scala:437:7]
wire [1:0] io_fresp_bits_uop_iw_state_0; // @[execution-unit.scala:437:7]
wire io_fresp_bits_uop_iw_p1_poisoned_0; // @[execution-unit.scala:437:7]
wire io_fresp_bits_uop_iw_p2_poisoned_0; // @[execution-unit.scala:437:7]
wire io_fresp_bits_uop_is_br_0; // @[execution-unit.scala:437:7]
wire io_fresp_bits_uop_is_jalr_0; // @[execution-unit.scala:437:7]
wire io_fresp_bits_uop_is_jal_0; // @[execution-unit.scala:437:7]
wire io_fresp_bits_uop_is_sfb_0; // @[execution-unit.scala:437:7]
wire [15:0] io_fresp_bits_uop_br_mask_0; // @[execution-unit.scala:437:7]
wire [3:0] io_fresp_bits_uop_br_tag_0; // @[execution-unit.scala:437:7]
wire [4:0] io_fresp_bits_uop_ftq_idx_0; // @[execution-unit.scala:437:7]
wire io_fresp_bits_uop_edge_inst_0; // @[execution-unit.scala:437:7]
wire [5:0] io_fresp_bits_uop_pc_lob_0; // @[execution-unit.scala:437:7]
wire io_fresp_bits_uop_taken_0; // @[execution-unit.scala:437:7]
wire [19:0] io_fresp_bits_uop_imm_packed_0; // @[execution-unit.scala:437:7]
wire [11:0] io_fresp_bits_uop_csr_addr_0; // @[execution-unit.scala:437:7]
wire [6:0] io_fresp_bits_uop_rob_idx_0; // @[execution-unit.scala:437:7]
wire [4:0] io_fresp_bits_uop_ldq_idx_0; // @[execution-unit.scala:437:7]
wire [4:0] io_fresp_bits_uop_stq_idx_0; // @[execution-unit.scala:437:7]
wire [1:0] io_fresp_bits_uop_rxq_idx_0; // @[execution-unit.scala:437:7]
wire [6:0] io_fresp_bits_uop_pdst_0; // @[execution-unit.scala:437:7]
wire [6:0] io_fresp_bits_uop_prs1_0; // @[execution-unit.scala:437:7]
wire [6:0] io_fresp_bits_uop_prs2_0; // @[execution-unit.scala:437:7]
wire [6:0] io_fresp_bits_uop_prs3_0; // @[execution-unit.scala:437:7]
wire [4:0] io_fresp_bits_uop_ppred_0; // @[execution-unit.scala:437:7]
wire io_fresp_bits_uop_prs1_busy_0; // @[execution-unit.scala:437:7]
wire io_fresp_bits_uop_prs2_busy_0; // @[execution-unit.scala:437:7]
wire io_fresp_bits_uop_prs3_busy_0; // @[execution-unit.scala:437:7]
wire io_fresp_bits_uop_ppred_busy_0; // @[execution-unit.scala:437:7]
wire [6:0] io_fresp_bits_uop_stale_pdst_0; // @[execution-unit.scala:437:7]
wire io_fresp_bits_uop_exception_0; // @[execution-unit.scala:437:7]
wire [63:0] io_fresp_bits_uop_exc_cause_0; // @[execution-unit.scala:437:7]
wire io_fresp_bits_uop_bypassable_0; // @[execution-unit.scala:437:7]
wire [4:0] io_fresp_bits_uop_mem_cmd_0; // @[execution-unit.scala:437:7]
wire [1:0] io_fresp_bits_uop_mem_size_0; // @[execution-unit.scala:437:7]
wire io_fresp_bits_uop_mem_signed_0; // @[execution-unit.scala:437:7]
wire io_fresp_bits_uop_is_fence_0; // @[execution-unit.scala:437:7]
wire io_fresp_bits_uop_is_fencei_0; // @[execution-unit.scala:437:7]
wire io_fresp_bits_uop_is_amo_0; // @[execution-unit.scala:437:7]
wire io_fresp_bits_uop_uses_ldq_0; // @[execution-unit.scala:437:7]
wire io_fresp_bits_uop_uses_stq_0; // @[execution-unit.scala:437:7]
wire io_fresp_bits_uop_is_sys_pc2epc_0; // @[execution-unit.scala:437:7]
wire io_fresp_bits_uop_is_unique_0; // @[execution-unit.scala:437:7]
wire io_fresp_bits_uop_flush_on_commit_0; // @[execution-unit.scala:437:7]
wire io_fresp_bits_uop_ldst_is_rs1_0; // @[execution-unit.scala:437:7]
wire [5:0] io_fresp_bits_uop_ldst_0; // @[execution-unit.scala:437:7]
wire [5:0] io_fresp_bits_uop_lrs1_0; // @[execution-unit.scala:437:7]
wire [5:0] io_fresp_bits_uop_lrs2_0; // @[execution-unit.scala:437:7]
wire [5:0] io_fresp_bits_uop_lrs3_0; // @[execution-unit.scala:437:7]
wire io_fresp_bits_uop_ldst_val_0; // @[execution-unit.scala:437:7]
wire [1:0] io_fresp_bits_uop_dst_rtype_0; // @[execution-unit.scala:437:7]
wire [1:0] io_fresp_bits_uop_lrs1_rtype_0; // @[execution-unit.scala:437:7]
wire [1:0] io_fresp_bits_uop_lrs2_rtype_0; // @[execution-unit.scala:437:7]
wire io_fresp_bits_uop_frs3_en_0; // @[execution-unit.scala:437:7]
wire io_fresp_bits_uop_fp_val_0; // @[execution-unit.scala:437:7]
wire io_fresp_bits_uop_fp_single_0; // @[execution-unit.scala:437:7]
wire io_fresp_bits_uop_xcpt_pf_if_0; // @[execution-unit.scala:437:7]
wire io_fresp_bits_uop_xcpt_ae_if_0; // @[execution-unit.scala:437:7]
wire io_fresp_bits_uop_xcpt_ma_if_0; // @[execution-unit.scala:437:7]
wire io_fresp_bits_uop_bp_debug_if_0; // @[execution-unit.scala:437:7]
wire io_fresp_bits_uop_bp_xcpt_if_0; // @[execution-unit.scala:437:7]
wire [1:0] io_fresp_bits_uop_debug_fsrc_0; // @[execution-unit.scala:437:7]
wire [1:0] io_fresp_bits_uop_debug_tsrc_0; // @[execution-unit.scala:437:7]
wire [3:0] io_fresp_bits_fflags_bits_uop_ctrl_br_type_0; // @[execution-unit.scala:437:7]
wire [1:0] io_fresp_bits_fflags_bits_uop_ctrl_op1_sel_0; // @[execution-unit.scala:437:7]
wire [2:0] io_fresp_bits_fflags_bits_uop_ctrl_op2_sel_0; // @[execution-unit.scala:437:7]
wire [2:0] io_fresp_bits_fflags_bits_uop_ctrl_imm_sel_0; // @[execution-unit.scala:437:7]
wire [4:0] io_fresp_bits_fflags_bits_uop_ctrl_op_fcn_0; // @[execution-unit.scala:437:7]
wire io_fresp_bits_fflags_bits_uop_ctrl_fcn_dw_0; // @[execution-unit.scala:437:7]
wire [2:0] io_fresp_bits_fflags_bits_uop_ctrl_csr_cmd_0; // @[execution-unit.scala:437:7]
wire io_fresp_bits_fflags_bits_uop_ctrl_is_load_0; // @[execution-unit.scala:437:7]
wire io_fresp_bits_fflags_bits_uop_ctrl_is_sta_0; // @[execution-unit.scala:437:7]
wire io_fresp_bits_fflags_bits_uop_ctrl_is_std_0; // @[execution-unit.scala:437:7]
wire [6:0] io_fresp_bits_fflags_bits_uop_uopc_0; // @[execution-unit.scala:437:7]
wire [31:0] io_fresp_bits_fflags_bits_uop_inst_0; // @[execution-unit.scala:437:7]
wire [31:0] io_fresp_bits_fflags_bits_uop_debug_inst_0; // @[execution-unit.scala:437:7]
wire io_fresp_bits_fflags_bits_uop_is_rvc_0; // @[execution-unit.scala:437:7]
wire [39:0] io_fresp_bits_fflags_bits_uop_debug_pc_0; // @[execution-unit.scala:437:7]
wire [2:0] io_fresp_bits_fflags_bits_uop_iq_type_0; // @[execution-unit.scala:437:7]
wire [9:0] io_fresp_bits_fflags_bits_uop_fu_code_0; // @[execution-unit.scala:437:7]
wire [1:0] io_fresp_bits_fflags_bits_uop_iw_state_0; // @[execution-unit.scala:437:7]
wire io_fresp_bits_fflags_bits_uop_iw_p1_poisoned_0; // @[execution-unit.scala:437:7]
wire io_fresp_bits_fflags_bits_uop_iw_p2_poisoned_0; // @[execution-unit.scala:437:7]
wire io_fresp_bits_fflags_bits_uop_is_br_0; // @[execution-unit.scala:437:7]
wire io_fresp_bits_fflags_bits_uop_is_jalr_0; // @[execution-unit.scala:437:7]
wire io_fresp_bits_fflags_bits_uop_is_jal_0; // @[execution-unit.scala:437:7]
wire io_fresp_bits_fflags_bits_uop_is_sfb_0; // @[execution-unit.scala:437:7]
wire [15:0] io_fresp_bits_fflags_bits_uop_br_mask_0; // @[execution-unit.scala:437:7]
wire [3:0] io_fresp_bits_fflags_bits_uop_br_tag_0; // @[execution-unit.scala:437:7]
wire [4:0] io_fresp_bits_fflags_bits_uop_ftq_idx_0; // @[execution-unit.scala:437:7]
wire io_fresp_bits_fflags_bits_uop_edge_inst_0; // @[execution-unit.scala:437:7]
wire [5:0] io_fresp_bits_fflags_bits_uop_pc_lob_0; // @[execution-unit.scala:437:7]
wire io_fresp_bits_fflags_bits_uop_taken_0; // @[execution-unit.scala:437:7]
wire [19:0] io_fresp_bits_fflags_bits_uop_imm_packed_0; // @[execution-unit.scala:437:7]
wire [11:0] io_fresp_bits_fflags_bits_uop_csr_addr_0; // @[execution-unit.scala:437:7]
wire [6:0] io_fresp_bits_fflags_bits_uop_rob_idx_0; // @[execution-unit.scala:437:7]
wire [4:0] io_fresp_bits_fflags_bits_uop_ldq_idx_0; // @[execution-unit.scala:437:7]
wire [4:0] io_fresp_bits_fflags_bits_uop_stq_idx_0; // @[execution-unit.scala:437:7]
wire [1:0] io_fresp_bits_fflags_bits_uop_rxq_idx_0; // @[execution-unit.scala:437:7]
wire [6:0] io_fresp_bits_fflags_bits_uop_pdst_0; // @[execution-unit.scala:437:7]
wire [6:0] io_fresp_bits_fflags_bits_uop_prs1_0; // @[execution-unit.scala:437:7]
wire [6:0] io_fresp_bits_fflags_bits_uop_prs2_0; // @[execution-unit.scala:437:7]
wire [6:0] io_fresp_bits_fflags_bits_uop_prs3_0; // @[execution-unit.scala:437:7]
wire [4:0] io_fresp_bits_fflags_bits_uop_ppred_0; // @[execution-unit.scala:437:7]
wire io_fresp_bits_fflags_bits_uop_prs1_busy_0; // @[execution-unit.scala:437:7]
wire io_fresp_bits_fflags_bits_uop_prs2_busy_0; // @[execution-unit.scala:437:7]
wire io_fresp_bits_fflags_bits_uop_prs3_busy_0; // @[execution-unit.scala:437:7]
wire io_fresp_bits_fflags_bits_uop_ppred_busy_0; // @[execution-unit.scala:437:7]
wire [6:0] io_fresp_bits_fflags_bits_uop_stale_pdst_0; // @[execution-unit.scala:437:7]
wire io_fresp_bits_fflags_bits_uop_exception_0; // @[execution-unit.scala:437:7]
wire [63:0] io_fresp_bits_fflags_bits_uop_exc_cause_0; // @[execution-unit.scala:437:7]
wire io_fresp_bits_fflags_bits_uop_bypassable_0; // @[execution-unit.scala:437:7]
wire [4:0] io_fresp_bits_fflags_bits_uop_mem_cmd_0; // @[execution-unit.scala:437:7]
wire [1:0] io_fresp_bits_fflags_bits_uop_mem_size_0; // @[execution-unit.scala:437:7]
wire io_fresp_bits_fflags_bits_uop_mem_signed_0; // @[execution-unit.scala:437:7]
wire io_fresp_bits_fflags_bits_uop_is_fence_0; // @[execution-unit.scala:437:7]
wire io_fresp_bits_fflags_bits_uop_is_fencei_0; // @[execution-unit.scala:437:7]
wire io_fresp_bits_fflags_bits_uop_is_amo_0; // @[execution-unit.scala:437:7]
wire io_fresp_bits_fflags_bits_uop_uses_ldq_0; // @[execution-unit.scala:437:7]
wire io_fresp_bits_fflags_bits_uop_uses_stq_0; // @[execution-unit.scala:437:7]
wire io_fresp_bits_fflags_bits_uop_is_sys_pc2epc_0; // @[execution-unit.scala:437:7]
wire io_fresp_bits_fflags_bits_uop_is_unique_0; // @[execution-unit.scala:437:7]
wire io_fresp_bits_fflags_bits_uop_flush_on_commit_0; // @[execution-unit.scala:437:7]
wire io_fresp_bits_fflags_bits_uop_ldst_is_rs1_0; // @[execution-unit.scala:437:7]
wire [5:0] io_fresp_bits_fflags_bits_uop_ldst_0; // @[execution-unit.scala:437:7]
wire [5:0] io_fresp_bits_fflags_bits_uop_lrs1_0; // @[execution-unit.scala:437:7]
wire [5:0] io_fresp_bits_fflags_bits_uop_lrs2_0; // @[execution-unit.scala:437:7]
wire [5:0] io_fresp_bits_fflags_bits_uop_lrs3_0; // @[execution-unit.scala:437:7]
wire io_fresp_bits_fflags_bits_uop_ldst_val_0; // @[execution-unit.scala:437:7]
wire [1:0] io_fresp_bits_fflags_bits_uop_dst_rtype_0; // @[execution-unit.scala:437:7]
wire [1:0] io_fresp_bits_fflags_bits_uop_lrs1_rtype_0; // @[execution-unit.scala:437:7]
wire [1:0] io_fresp_bits_fflags_bits_uop_lrs2_rtype_0; // @[execution-unit.scala:437:7]
wire io_fresp_bits_fflags_bits_uop_frs3_en_0; // @[execution-unit.scala:437:7]
wire io_fresp_bits_fflags_bits_uop_fp_val_0; // @[execution-unit.scala:437:7]
wire io_fresp_bits_fflags_bits_uop_fp_single_0; // @[execution-unit.scala:437:7]
wire io_fresp_bits_fflags_bits_uop_xcpt_pf_if_0; // @[execution-unit.scala:437:7]
wire io_fresp_bits_fflags_bits_uop_xcpt_ae_if_0; // @[execution-unit.scala:437:7]
wire io_fresp_bits_fflags_bits_uop_xcpt_ma_if_0; // @[execution-unit.scala:437:7]
wire io_fresp_bits_fflags_bits_uop_bp_debug_if_0; // @[execution-unit.scala:437:7]
wire io_fresp_bits_fflags_bits_uop_bp_xcpt_if_0; // @[execution-unit.scala:437:7]
wire [1:0] io_fresp_bits_fflags_bits_uop_debug_fsrc_0; // @[execution-unit.scala:437:7]
wire [1:0] io_fresp_bits_fflags_bits_uop_debug_tsrc_0; // @[execution-unit.scala:437:7]
wire [4:0] io_fresp_bits_fflags_bits_flags_0; // @[execution-unit.scala:437:7]
wire io_fresp_bits_fflags_valid_0; // @[execution-unit.scala:437:7]
wire [64:0] io_fresp_bits_data_0; // @[execution-unit.scala:437:7]
wire io_fresp_valid_0; // @[execution-unit.scala:437:7]
wire [3:0] io_ll_iresp_bits_uop_ctrl_br_type_0; // @[execution-unit.scala:437:7]
wire [1:0] io_ll_iresp_bits_uop_ctrl_op1_sel_0; // @[execution-unit.scala:437:7]
wire [2:0] io_ll_iresp_bits_uop_ctrl_op2_sel_0; // @[execution-unit.scala:437:7]
wire [2:0] io_ll_iresp_bits_uop_ctrl_imm_sel_0; // @[execution-unit.scala:437:7]
wire [4:0] io_ll_iresp_bits_uop_ctrl_op_fcn_0; // @[execution-unit.scala:437:7]
wire io_ll_iresp_bits_uop_ctrl_fcn_dw_0; // @[execution-unit.scala:437:7]
wire [2:0] io_ll_iresp_bits_uop_ctrl_csr_cmd_0; // @[execution-unit.scala:437:7]
wire io_ll_iresp_bits_uop_ctrl_is_load_0; // @[execution-unit.scala:437:7]
wire io_ll_iresp_bits_uop_ctrl_is_sta_0; // @[execution-unit.scala:437:7]
wire io_ll_iresp_bits_uop_ctrl_is_std_0; // @[execution-unit.scala:437:7]
wire [6:0] io_ll_iresp_bits_uop_uopc_0; // @[execution-unit.scala:437:7]
wire [31:0] io_ll_iresp_bits_uop_inst_0; // @[execution-unit.scala:437:7]
wire [31:0] io_ll_iresp_bits_uop_debug_inst_0; // @[execution-unit.scala:437:7]
wire io_ll_iresp_bits_uop_is_rvc_0; // @[execution-unit.scala:437:7]
wire [39:0] io_ll_iresp_bits_uop_debug_pc_0; // @[execution-unit.scala:437:7]
wire [2:0] io_ll_iresp_bits_uop_iq_type_0; // @[execution-unit.scala:437:7]
wire [9:0] io_ll_iresp_bits_uop_fu_code_0; // @[execution-unit.scala:437:7]
wire [1:0] io_ll_iresp_bits_uop_iw_state_0; // @[execution-unit.scala:437:7]
wire io_ll_iresp_bits_uop_iw_p1_poisoned_0; // @[execution-unit.scala:437:7]
wire io_ll_iresp_bits_uop_iw_p2_poisoned_0; // @[execution-unit.scala:437:7]
wire io_ll_iresp_bits_uop_is_br_0; // @[execution-unit.scala:437:7]
wire io_ll_iresp_bits_uop_is_jalr_0; // @[execution-unit.scala:437:7]
wire io_ll_iresp_bits_uop_is_jal_0; // @[execution-unit.scala:437:7]
wire io_ll_iresp_bits_uop_is_sfb_0; // @[execution-unit.scala:437:7]
wire [15:0] io_ll_iresp_bits_uop_br_mask_0; // @[execution-unit.scala:437:7]
wire [3:0] io_ll_iresp_bits_uop_br_tag_0; // @[execution-unit.scala:437:7]
wire [4:0] io_ll_iresp_bits_uop_ftq_idx_0; // @[execution-unit.scala:437:7]
wire io_ll_iresp_bits_uop_edge_inst_0; // @[execution-unit.scala:437:7]
wire [5:0] io_ll_iresp_bits_uop_pc_lob_0; // @[execution-unit.scala:437:7]
wire io_ll_iresp_bits_uop_taken_0; // @[execution-unit.scala:437:7]
wire [19:0] io_ll_iresp_bits_uop_imm_packed_0; // @[execution-unit.scala:437:7]
wire [11:0] io_ll_iresp_bits_uop_csr_addr_0; // @[execution-unit.scala:437:7]
wire [6:0] io_ll_iresp_bits_uop_rob_idx_0; // @[execution-unit.scala:437:7]
wire [4:0] io_ll_iresp_bits_uop_ldq_idx_0; // @[execution-unit.scala:437:7]
wire [4:0] io_ll_iresp_bits_uop_stq_idx_0; // @[execution-unit.scala:437:7]
wire [1:0] io_ll_iresp_bits_uop_rxq_idx_0; // @[execution-unit.scala:437:7]
wire [6:0] io_ll_iresp_bits_uop_pdst_0; // @[execution-unit.scala:437:7]
wire [6:0] io_ll_iresp_bits_uop_prs1_0; // @[execution-unit.scala:437:7]
wire [6:0] io_ll_iresp_bits_uop_prs2_0; // @[execution-unit.scala:437:7]
wire [6:0] io_ll_iresp_bits_uop_prs3_0; // @[execution-unit.scala:437:7]
wire [4:0] io_ll_iresp_bits_uop_ppred_0; // @[execution-unit.scala:437:7]
wire io_ll_iresp_bits_uop_prs1_busy_0; // @[execution-unit.scala:437:7]
wire io_ll_iresp_bits_uop_prs2_busy_0; // @[execution-unit.scala:437:7]
wire io_ll_iresp_bits_uop_prs3_busy_0; // @[execution-unit.scala:437:7]
wire io_ll_iresp_bits_uop_ppred_busy_0; // @[execution-unit.scala:437:7]
wire [6:0] io_ll_iresp_bits_uop_stale_pdst_0; // @[execution-unit.scala:437:7]
wire io_ll_iresp_bits_uop_exception_0; // @[execution-unit.scala:437:7]
wire [63:0] io_ll_iresp_bits_uop_exc_cause_0; // @[execution-unit.scala:437:7]
wire io_ll_iresp_bits_uop_bypassable_0; // @[execution-unit.scala:437:7]
wire [4:0] io_ll_iresp_bits_uop_mem_cmd_0; // @[execution-unit.scala:437:7]
wire [1:0] io_ll_iresp_bits_uop_mem_size_0; // @[execution-unit.scala:437:7]
wire io_ll_iresp_bits_uop_mem_signed_0; // @[execution-unit.scala:437:7]
wire io_ll_iresp_bits_uop_is_fence_0; // @[execution-unit.scala:437:7]
wire io_ll_iresp_bits_uop_is_fencei_0; // @[execution-unit.scala:437:7]
wire io_ll_iresp_bits_uop_is_amo_0; // @[execution-unit.scala:437:7]
wire io_ll_iresp_bits_uop_uses_ldq_0; // @[execution-unit.scala:437:7]
wire io_ll_iresp_bits_uop_uses_stq_0; // @[execution-unit.scala:437:7]
wire io_ll_iresp_bits_uop_is_sys_pc2epc_0; // @[execution-unit.scala:437:7]
wire io_ll_iresp_bits_uop_is_unique_0; // @[execution-unit.scala:437:7]
wire io_ll_iresp_bits_uop_flush_on_commit_0; // @[execution-unit.scala:437:7]
wire io_ll_iresp_bits_uop_ldst_is_rs1_0; // @[execution-unit.scala:437:7]
wire [5:0] io_ll_iresp_bits_uop_ldst_0; // @[execution-unit.scala:437:7]
wire [5:0] io_ll_iresp_bits_uop_lrs1_0; // @[execution-unit.scala:437:7]
wire [5:0] io_ll_iresp_bits_uop_lrs2_0; // @[execution-unit.scala:437:7]
wire [5:0] io_ll_iresp_bits_uop_lrs3_0; // @[execution-unit.scala:437:7]
wire io_ll_iresp_bits_uop_ldst_val_0; // @[execution-unit.scala:437:7]
wire [1:0] io_ll_iresp_bits_uop_dst_rtype_0; // @[execution-unit.scala:437:7]
wire [1:0] io_ll_iresp_bits_uop_lrs1_rtype_0; // @[execution-unit.scala:437:7]
wire [1:0] io_ll_iresp_bits_uop_lrs2_rtype_0; // @[execution-unit.scala:437:7]
wire io_ll_iresp_bits_uop_frs3_en_0; // @[execution-unit.scala:437:7]
wire io_ll_iresp_bits_uop_fp_val_0; // @[execution-unit.scala:437:7]
wire io_ll_iresp_bits_uop_fp_single_0; // @[execution-unit.scala:437:7]
wire io_ll_iresp_bits_uop_xcpt_pf_if_0; // @[execution-unit.scala:437:7]
wire io_ll_iresp_bits_uop_xcpt_ae_if_0; // @[execution-unit.scala:437:7]
wire io_ll_iresp_bits_uop_xcpt_ma_if_0; // @[execution-unit.scala:437:7]
wire io_ll_iresp_bits_uop_bp_debug_if_0; // @[execution-unit.scala:437:7]
wire io_ll_iresp_bits_uop_bp_xcpt_if_0; // @[execution-unit.scala:437:7]
wire [1:0] io_ll_iresp_bits_uop_debug_fsrc_0; // @[execution-unit.scala:437:7]
wire [1:0] io_ll_iresp_bits_uop_debug_tsrc_0; // @[execution-unit.scala:437:7]
wire [3:0] io_ll_iresp_bits_fflags_bits_uop_ctrl_br_type_0; // @[execution-unit.scala:437:7]
wire [1:0] io_ll_iresp_bits_fflags_bits_uop_ctrl_op1_sel_0; // @[execution-unit.scala:437:7]
wire [2:0] io_ll_iresp_bits_fflags_bits_uop_ctrl_op2_sel_0; // @[execution-unit.scala:437:7]
wire [2:0] io_ll_iresp_bits_fflags_bits_uop_ctrl_imm_sel_0; // @[execution-unit.scala:437:7]
wire [4:0] io_ll_iresp_bits_fflags_bits_uop_ctrl_op_fcn_0; // @[execution-unit.scala:437:7]
wire io_ll_iresp_bits_fflags_bits_uop_ctrl_fcn_dw_0; // @[execution-unit.scala:437:7]
wire [2:0] io_ll_iresp_bits_fflags_bits_uop_ctrl_csr_cmd_0; // @[execution-unit.scala:437:7]
wire io_ll_iresp_bits_fflags_bits_uop_ctrl_is_load_0; // @[execution-unit.scala:437:7]
wire io_ll_iresp_bits_fflags_bits_uop_ctrl_is_sta_0; // @[execution-unit.scala:437:7]
wire io_ll_iresp_bits_fflags_bits_uop_ctrl_is_std_0; // @[execution-unit.scala:437:7]
wire [6:0] io_ll_iresp_bits_fflags_bits_uop_uopc_0; // @[execution-unit.scala:437:7]
wire [31:0] io_ll_iresp_bits_fflags_bits_uop_inst_0; // @[execution-unit.scala:437:7]
wire [31:0] io_ll_iresp_bits_fflags_bits_uop_debug_inst_0; // @[execution-unit.scala:437:7]
wire io_ll_iresp_bits_fflags_bits_uop_is_rvc_0; // @[execution-unit.scala:437:7]
wire [39:0] io_ll_iresp_bits_fflags_bits_uop_debug_pc_0; // @[execution-unit.scala:437:7]
wire [2:0] io_ll_iresp_bits_fflags_bits_uop_iq_type_0; // @[execution-unit.scala:437:7]
wire [9:0] io_ll_iresp_bits_fflags_bits_uop_fu_code_0; // @[execution-unit.scala:437:7]
wire [1:0] io_ll_iresp_bits_fflags_bits_uop_iw_state_0; // @[execution-unit.scala:437:7]
wire io_ll_iresp_bits_fflags_bits_uop_iw_p1_poisoned_0; // @[execution-unit.scala:437:7]
wire io_ll_iresp_bits_fflags_bits_uop_iw_p2_poisoned_0; // @[execution-unit.scala:437:7]
wire io_ll_iresp_bits_fflags_bits_uop_is_br_0; // @[execution-unit.scala:437:7]
wire io_ll_iresp_bits_fflags_bits_uop_is_jalr_0; // @[execution-unit.scala:437:7]
wire io_ll_iresp_bits_fflags_bits_uop_is_jal_0; // @[execution-unit.scala:437:7]
wire io_ll_iresp_bits_fflags_bits_uop_is_sfb_0; // @[execution-unit.scala:437:7]
wire [15:0] io_ll_iresp_bits_fflags_bits_uop_br_mask_0; // @[execution-unit.scala:437:7]
wire [3:0] io_ll_iresp_bits_fflags_bits_uop_br_tag_0; // @[execution-unit.scala:437:7]
wire [4:0] io_ll_iresp_bits_fflags_bits_uop_ftq_idx_0; // @[execution-unit.scala:437:7]
wire io_ll_iresp_bits_fflags_bits_uop_edge_inst_0; // @[execution-unit.scala:437:7]
wire [5:0] io_ll_iresp_bits_fflags_bits_uop_pc_lob_0; // @[execution-unit.scala:437:7]
wire io_ll_iresp_bits_fflags_bits_uop_taken_0; // @[execution-unit.scala:437:7]
wire [19:0] io_ll_iresp_bits_fflags_bits_uop_imm_packed_0; // @[execution-unit.scala:437:7]
wire [11:0] io_ll_iresp_bits_fflags_bits_uop_csr_addr_0; // @[execution-unit.scala:437:7]
wire [6:0] io_ll_iresp_bits_fflags_bits_uop_rob_idx_0; // @[execution-unit.scala:437:7]
wire [4:0] io_ll_iresp_bits_fflags_bits_uop_ldq_idx_0; // @[execution-unit.scala:437:7]
wire [4:0] io_ll_iresp_bits_fflags_bits_uop_stq_idx_0; // @[execution-unit.scala:437:7]
wire [1:0] io_ll_iresp_bits_fflags_bits_uop_rxq_idx_0; // @[execution-unit.scala:437:7]
wire [6:0] io_ll_iresp_bits_fflags_bits_uop_pdst_0; // @[execution-unit.scala:437:7]
wire [6:0] io_ll_iresp_bits_fflags_bits_uop_prs1_0; // @[execution-unit.scala:437:7]
wire [6:0] io_ll_iresp_bits_fflags_bits_uop_prs2_0; // @[execution-unit.scala:437:7]
wire [6:0] io_ll_iresp_bits_fflags_bits_uop_prs3_0; // @[execution-unit.scala:437:7]
wire [4:0] io_ll_iresp_bits_fflags_bits_uop_ppred_0; // @[execution-unit.scala:437:7]
wire io_ll_iresp_bits_fflags_bits_uop_prs1_busy_0; // @[execution-unit.scala:437:7]
wire io_ll_iresp_bits_fflags_bits_uop_prs2_busy_0; // @[execution-unit.scala:437:7]
wire io_ll_iresp_bits_fflags_bits_uop_prs3_busy_0; // @[execution-unit.scala:437:7]
wire io_ll_iresp_bits_fflags_bits_uop_ppred_busy_0; // @[execution-unit.scala:437:7]
wire [6:0] io_ll_iresp_bits_fflags_bits_uop_stale_pdst_0; // @[execution-unit.scala:437:7]
wire io_ll_iresp_bits_fflags_bits_uop_exception_0; // @[execution-unit.scala:437:7]
wire [63:0] io_ll_iresp_bits_fflags_bits_uop_exc_cause_0; // @[execution-unit.scala:437:7]
wire io_ll_iresp_bits_fflags_bits_uop_bypassable_0; // @[execution-unit.scala:437:7]
wire [4:0] io_ll_iresp_bits_fflags_bits_uop_mem_cmd_0; // @[execution-unit.scala:437:7]
wire [1:0] io_ll_iresp_bits_fflags_bits_uop_mem_size_0; // @[execution-unit.scala:437:7]
wire io_ll_iresp_bits_fflags_bits_uop_mem_signed_0; // @[execution-unit.scala:437:7]
wire io_ll_iresp_bits_fflags_bits_uop_is_fence_0; // @[execution-unit.scala:437:7]
wire io_ll_iresp_bits_fflags_bits_uop_is_fencei_0; // @[execution-unit.scala:437:7]
wire io_ll_iresp_bits_fflags_bits_uop_is_amo_0; // @[execution-unit.scala:437:7]
wire io_ll_iresp_bits_fflags_bits_uop_uses_ldq_0; // @[execution-unit.scala:437:7]
wire io_ll_iresp_bits_fflags_bits_uop_uses_stq_0; // @[execution-unit.scala:437:7]
wire io_ll_iresp_bits_fflags_bits_uop_is_sys_pc2epc_0; // @[execution-unit.scala:437:7]
wire io_ll_iresp_bits_fflags_bits_uop_is_unique_0; // @[execution-unit.scala:437:7]
wire io_ll_iresp_bits_fflags_bits_uop_flush_on_commit_0; // @[execution-unit.scala:437:7]
wire io_ll_iresp_bits_fflags_bits_uop_ldst_is_rs1_0; // @[execution-unit.scala:437:7]
wire [5:0] io_ll_iresp_bits_fflags_bits_uop_ldst_0; // @[execution-unit.scala:437:7]
wire [5:0] io_ll_iresp_bits_fflags_bits_uop_lrs1_0; // @[execution-unit.scala:437:7]
wire [5:0] io_ll_iresp_bits_fflags_bits_uop_lrs2_0; // @[execution-unit.scala:437:7]
wire [5:0] io_ll_iresp_bits_fflags_bits_uop_lrs3_0; // @[execution-unit.scala:437:7]
wire io_ll_iresp_bits_fflags_bits_uop_ldst_val_0; // @[execution-unit.scala:437:7]
wire [1:0] io_ll_iresp_bits_fflags_bits_uop_dst_rtype_0; // @[execution-unit.scala:437:7]
wire [1:0] io_ll_iresp_bits_fflags_bits_uop_lrs1_rtype_0; // @[execution-unit.scala:437:7]
wire [1:0] io_ll_iresp_bits_fflags_bits_uop_lrs2_rtype_0; // @[execution-unit.scala:437:7]
wire io_ll_iresp_bits_fflags_bits_uop_frs3_en_0; // @[execution-unit.scala:437:7]
wire io_ll_iresp_bits_fflags_bits_uop_fp_val_0; // @[execution-unit.scala:437:7]
wire io_ll_iresp_bits_fflags_bits_uop_fp_single_0; // @[execution-unit.scala:437:7]
wire io_ll_iresp_bits_fflags_bits_uop_xcpt_pf_if_0; // @[execution-unit.scala:437:7]
wire io_ll_iresp_bits_fflags_bits_uop_xcpt_ae_if_0; // @[execution-unit.scala:437:7]
wire io_ll_iresp_bits_fflags_bits_uop_xcpt_ma_if_0; // @[execution-unit.scala:437:7]
wire io_ll_iresp_bits_fflags_bits_uop_bp_debug_if_0; // @[execution-unit.scala:437:7]
wire io_ll_iresp_bits_fflags_bits_uop_bp_xcpt_if_0; // @[execution-unit.scala:437:7]
wire [1:0] io_ll_iresp_bits_fflags_bits_uop_debug_fsrc_0; // @[execution-unit.scala:437:7]
wire [1:0] io_ll_iresp_bits_fflags_bits_uop_debug_tsrc_0; // @[execution-unit.scala:437:7]
wire [4:0] io_ll_iresp_bits_fflags_bits_flags_0; // @[execution-unit.scala:437:7]
wire io_ll_iresp_bits_fflags_valid_0; // @[execution-unit.scala:437:7]
wire [64:0] io_ll_iresp_bits_data_0; // @[execution-unit.scala:437:7]
wire io_ll_iresp_bits_predicated_0; // @[execution-unit.scala:437:7]
wire io_ll_iresp_valid_0; // @[execution-unit.scala:437:7]
wire [9:0] io_fu_types_0; // @[execution-unit.scala:437:7]
wire _fdiv_busy_T_4; // @[execution-unit.scala:516:41]
wire fdiv_busy; // @[execution-unit.scala:461:27]
wire _fpiu_busy_T_1; // @[execution-unit.scala:568:18]
wire fpiu_busy; // @[execution-unit.scala:462:27]
wire _io_fu_types_T_1 = ~fdiv_busy; // @[execution-unit.scala:461:27, :468:22]
wire _io_fu_types_T_2 = _io_fu_types_T_1; // @[execution-unit.scala:468:{22,33}]
wire [9:0] _io_fu_types_T_3 = {2'h0, _io_fu_types_T_2, 7'h0}; // @[execution-unit.scala:468:{21,33}]
wire [9:0] _io_fu_types_T_4 = _io_fu_types_T_3 | 10'h40; // @[execution-unit.scala:467:45, :468:21]
wire _io_fu_types_T_5 = ~fpiu_busy; // @[execution-unit.scala:462:27, :469:22]
wire _io_fu_types_T_6 = _io_fu_types_T_5; // @[execution-unit.scala:469:{22,33}]
wire [9:0] _io_fu_types_T_7 = {_io_fu_types_T_6, 9'h0}; // @[execution-unit.scala:469:{21,33}]
assign _io_fu_types_T_8 = _io_fu_types_T_4 | _io_fu_types_T_7; // @[execution-unit.scala:467:45, :468:60, :469:21]
assign io_fu_types_0 = _io_fu_types_T_8; // @[execution-unit.scala:437:7, :468:60]
wire fpu_resp_val; // @[execution-unit.scala:473:30]
wire [3:0] fpu_resp_fflags_bits_uop_ctrl_br_type; // @[execution-unit.scala:474:29]
wire [1:0] fpu_resp_fflags_bits_uop_ctrl_op1_sel; // @[execution-unit.scala:474:29]
wire [2:0] fpu_resp_fflags_bits_uop_ctrl_op2_sel; // @[execution-unit.scala:474:29]
wire [2:0] fpu_resp_fflags_bits_uop_ctrl_imm_sel; // @[execution-unit.scala:474:29]
wire [4:0] fpu_resp_fflags_bits_uop_ctrl_op_fcn; // @[execution-unit.scala:474:29]
wire fpu_resp_fflags_bits_uop_ctrl_fcn_dw; // @[execution-unit.scala:474:29]
wire [2:0] fpu_resp_fflags_bits_uop_ctrl_csr_cmd; // @[execution-unit.scala:474:29]
wire fpu_resp_fflags_bits_uop_ctrl_is_load; // @[execution-unit.scala:474:29]
wire fpu_resp_fflags_bits_uop_ctrl_is_sta; // @[execution-unit.scala:474:29]
wire fpu_resp_fflags_bits_uop_ctrl_is_std; // @[execution-unit.scala:474:29]
wire [6:0] fpu_resp_fflags_bits_uop_uopc; // @[execution-unit.scala:474:29]
wire [31:0] fpu_resp_fflags_bits_uop_inst; // @[execution-unit.scala:474:29]
wire [31:0] fpu_resp_fflags_bits_uop_debug_inst; // @[execution-unit.scala:474:29]
wire fpu_resp_fflags_bits_uop_is_rvc; // @[execution-unit.scala:474:29]
wire [39:0] fpu_resp_fflags_bits_uop_debug_pc; // @[execution-unit.scala:474:29]
wire [2:0] fpu_resp_fflags_bits_uop_iq_type; // @[execution-unit.scala:474:29]
wire [9:0] fpu_resp_fflags_bits_uop_fu_code; // @[execution-unit.scala:474:29]
wire [1:0] fpu_resp_fflags_bits_uop_iw_state; // @[execution-unit.scala:474:29]
wire fpu_resp_fflags_bits_uop_iw_p1_poisoned; // @[execution-unit.scala:474:29]
wire fpu_resp_fflags_bits_uop_iw_p2_poisoned; // @[execution-unit.scala:474:29]
wire fpu_resp_fflags_bits_uop_is_br; // @[execution-unit.scala:474:29]
wire fpu_resp_fflags_bits_uop_is_jalr; // @[execution-unit.scala:474:29]
wire fpu_resp_fflags_bits_uop_is_jal; // @[execution-unit.scala:474:29]
wire fpu_resp_fflags_bits_uop_is_sfb; // @[execution-unit.scala:474:29]
wire [15:0] fpu_resp_fflags_bits_uop_br_mask; // @[execution-unit.scala:474:29]
wire [3:0] fpu_resp_fflags_bits_uop_br_tag; // @[execution-unit.scala:474:29]
wire [4:0] fpu_resp_fflags_bits_uop_ftq_idx; // @[execution-unit.scala:474:29]
wire fpu_resp_fflags_bits_uop_edge_inst; // @[execution-unit.scala:474:29]
wire [5:0] fpu_resp_fflags_bits_uop_pc_lob; // @[execution-unit.scala:474:29]
wire fpu_resp_fflags_bits_uop_taken; // @[execution-unit.scala:474:29]
wire [19:0] fpu_resp_fflags_bits_uop_imm_packed; // @[execution-unit.scala:474:29]
wire [11:0] fpu_resp_fflags_bits_uop_csr_addr; // @[execution-unit.scala:474:29]
wire [6:0] fpu_resp_fflags_bits_uop_rob_idx; // @[execution-unit.scala:474:29]
wire [4:0] fpu_resp_fflags_bits_uop_ldq_idx; // @[execution-unit.scala:474:29]
wire [4:0] fpu_resp_fflags_bits_uop_stq_idx; // @[execution-unit.scala:474:29]
wire [1:0] fpu_resp_fflags_bits_uop_rxq_idx; // @[execution-unit.scala:474:29]
wire [6:0] fpu_resp_fflags_bits_uop_pdst; // @[execution-unit.scala:474:29]
wire [6:0] fpu_resp_fflags_bits_uop_prs1; // @[execution-unit.scala:474:29]
wire [6:0] fpu_resp_fflags_bits_uop_prs2; // @[execution-unit.scala:474:29]
wire [6:0] fpu_resp_fflags_bits_uop_prs3; // @[execution-unit.scala:474:29]
wire [4:0] fpu_resp_fflags_bits_uop_ppred; // @[execution-unit.scala:474:29]
wire fpu_resp_fflags_bits_uop_prs1_busy; // @[execution-unit.scala:474:29]
wire fpu_resp_fflags_bits_uop_prs2_busy; // @[execution-unit.scala:474:29]
wire fpu_resp_fflags_bits_uop_prs3_busy; // @[execution-unit.scala:474:29]
wire fpu_resp_fflags_bits_uop_ppred_busy; // @[execution-unit.scala:474:29]
wire [6:0] fpu_resp_fflags_bits_uop_stale_pdst; // @[execution-unit.scala:474:29]
wire fpu_resp_fflags_bits_uop_exception; // @[execution-unit.scala:474:29]
wire [63:0] fpu_resp_fflags_bits_uop_exc_cause; // @[execution-unit.scala:474:29]
wire fpu_resp_fflags_bits_uop_bypassable; // @[execution-unit.scala:474:29]
wire [4:0] fpu_resp_fflags_bits_uop_mem_cmd; // @[execution-unit.scala:474:29]
wire [1:0] fpu_resp_fflags_bits_uop_mem_size; // @[execution-unit.scala:474:29]
wire fpu_resp_fflags_bits_uop_mem_signed; // @[execution-unit.scala:474:29]
wire fpu_resp_fflags_bits_uop_is_fence; // @[execution-unit.scala:474:29]
wire fpu_resp_fflags_bits_uop_is_fencei; // @[execution-unit.scala:474:29]
wire fpu_resp_fflags_bits_uop_is_amo; // @[execution-unit.scala:474:29]
wire fpu_resp_fflags_bits_uop_uses_ldq; // @[execution-unit.scala:474:29]
wire fpu_resp_fflags_bits_uop_uses_stq; // @[execution-unit.scala:474:29]
wire fpu_resp_fflags_bits_uop_is_sys_pc2epc; // @[execution-unit.scala:474:29]
wire fpu_resp_fflags_bits_uop_is_unique; // @[execution-unit.scala:474:29]
wire fpu_resp_fflags_bits_uop_flush_on_commit; // @[execution-unit.scala:474:29]
wire fpu_resp_fflags_bits_uop_ldst_is_rs1; // @[execution-unit.scala:474:29]
wire [5:0] fpu_resp_fflags_bits_uop_ldst; // @[execution-unit.scala:474:29]
wire [5:0] fpu_resp_fflags_bits_uop_lrs1; // @[execution-unit.scala:474:29]
wire [5:0] fpu_resp_fflags_bits_uop_lrs2; // @[execution-unit.scala:474:29]
wire [5:0] fpu_resp_fflags_bits_uop_lrs3; // @[execution-unit.scala:474:29]
wire fpu_resp_fflags_bits_uop_ldst_val; // @[execution-unit.scala:474:29]
wire [1:0] fpu_resp_fflags_bits_uop_dst_rtype; // @[execution-unit.scala:474:29]
wire [1:0] fpu_resp_fflags_bits_uop_lrs1_rtype; // @[execution-unit.scala:474:29]
wire [1:0] fpu_resp_fflags_bits_uop_lrs2_rtype; // @[execution-unit.scala:474:29]
wire fpu_resp_fflags_bits_uop_frs3_en; // @[execution-unit.scala:474:29]
wire fpu_resp_fflags_bits_uop_fp_val; // @[execution-unit.scala:474:29]
wire fpu_resp_fflags_bits_uop_fp_single; // @[execution-unit.scala:474:29]
wire fpu_resp_fflags_bits_uop_xcpt_pf_if; // @[execution-unit.scala:474:29]
wire fpu_resp_fflags_bits_uop_xcpt_ae_if; // @[execution-unit.scala:474:29]
wire fpu_resp_fflags_bits_uop_xcpt_ma_if; // @[execution-unit.scala:474:29]
wire fpu_resp_fflags_bits_uop_bp_debug_if; // @[execution-unit.scala:474:29]
wire fpu_resp_fflags_bits_uop_bp_xcpt_if; // @[execution-unit.scala:474:29]
wire [1:0] fpu_resp_fflags_bits_uop_debug_fsrc; // @[execution-unit.scala:474:29]
wire [1:0] fpu_resp_fflags_bits_uop_debug_tsrc; // @[execution-unit.scala:474:29]
wire [4:0] fpu_resp_fflags_bits_flags; // @[execution-unit.scala:474:29]
wire fpu_resp_fflags_valid; // @[execution-unit.scala:474:29]
wire [3:0] fdiv_resp_fflags_bits_uop_ctrl_br_type; // @[execution-unit.scala:498:30]
wire [1:0] fdiv_resp_fflags_bits_uop_ctrl_op1_sel; // @[execution-unit.scala:498:30]
wire [2:0] fdiv_resp_fflags_bits_uop_ctrl_op2_sel; // @[execution-unit.scala:498:30]
wire [2:0] fdiv_resp_fflags_bits_uop_ctrl_imm_sel; // @[execution-unit.scala:498:30]
wire [4:0] fdiv_resp_fflags_bits_uop_ctrl_op_fcn; // @[execution-unit.scala:498:30]
wire fdiv_resp_fflags_bits_uop_ctrl_fcn_dw; // @[execution-unit.scala:498:30]
wire [2:0] fdiv_resp_fflags_bits_uop_ctrl_csr_cmd; // @[execution-unit.scala:498:30]
wire fdiv_resp_fflags_bits_uop_ctrl_is_load; // @[execution-unit.scala:498:30]
wire fdiv_resp_fflags_bits_uop_ctrl_is_sta; // @[execution-unit.scala:498:30]
wire fdiv_resp_fflags_bits_uop_ctrl_is_std; // @[execution-unit.scala:498:30]
wire [6:0] fdiv_resp_fflags_bits_uop_uopc; // @[execution-unit.scala:498:30]
wire [31:0] fdiv_resp_fflags_bits_uop_inst; // @[execution-unit.scala:498:30]
wire [31:0] fdiv_resp_fflags_bits_uop_debug_inst; // @[execution-unit.scala:498:30]
wire fdiv_resp_fflags_bits_uop_is_rvc; // @[execution-unit.scala:498:30]
wire [39:0] fdiv_resp_fflags_bits_uop_debug_pc; // @[execution-unit.scala:498:30]
wire [2:0] fdiv_resp_fflags_bits_uop_iq_type; // @[execution-unit.scala:498:30]
wire [9:0] fdiv_resp_fflags_bits_uop_fu_code; // @[execution-unit.scala:498:30]
wire [1:0] fdiv_resp_fflags_bits_uop_iw_state; // @[execution-unit.scala:498:30]
wire fdiv_resp_fflags_bits_uop_iw_p1_poisoned; // @[execution-unit.scala:498:30]
wire fdiv_resp_fflags_bits_uop_iw_p2_poisoned; // @[execution-unit.scala:498:30]
wire fdiv_resp_fflags_bits_uop_is_br; // @[execution-unit.scala:498:30]
wire fdiv_resp_fflags_bits_uop_is_jalr; // @[execution-unit.scala:498:30]
wire fdiv_resp_fflags_bits_uop_is_jal; // @[execution-unit.scala:498:30]
wire fdiv_resp_fflags_bits_uop_is_sfb; // @[execution-unit.scala:498:30]
wire [15:0] fdiv_resp_fflags_bits_uop_br_mask; // @[execution-unit.scala:498:30]
wire [3:0] fdiv_resp_fflags_bits_uop_br_tag; // @[execution-unit.scala:498:30]
wire [4:0] fdiv_resp_fflags_bits_uop_ftq_idx; // @[execution-unit.scala:498:30]
wire fdiv_resp_fflags_bits_uop_edge_inst; // @[execution-unit.scala:498:30]
wire [5:0] fdiv_resp_fflags_bits_uop_pc_lob; // @[execution-unit.scala:498:30]
wire fdiv_resp_fflags_bits_uop_taken; // @[execution-unit.scala:498:30]
wire [19:0] fdiv_resp_fflags_bits_uop_imm_packed; // @[execution-unit.scala:498:30]
wire [11:0] fdiv_resp_fflags_bits_uop_csr_addr; // @[execution-unit.scala:498:30]
wire [6:0] fdiv_resp_fflags_bits_uop_rob_idx; // @[execution-unit.scala:498:30]
wire [4:0] fdiv_resp_fflags_bits_uop_ldq_idx; // @[execution-unit.scala:498:30]
wire [4:0] fdiv_resp_fflags_bits_uop_stq_idx; // @[execution-unit.scala:498:30]
wire [1:0] fdiv_resp_fflags_bits_uop_rxq_idx; // @[execution-unit.scala:498:30]
wire [6:0] fdiv_resp_fflags_bits_uop_pdst; // @[execution-unit.scala:498:30]
wire [6:0] fdiv_resp_fflags_bits_uop_prs1; // @[execution-unit.scala:498:30]
wire [6:0] fdiv_resp_fflags_bits_uop_prs2; // @[execution-unit.scala:498:30]
wire [6:0] fdiv_resp_fflags_bits_uop_prs3; // @[execution-unit.scala:498:30]
wire [4:0] fdiv_resp_fflags_bits_uop_ppred; // @[execution-unit.scala:498:30]
wire fdiv_resp_fflags_bits_uop_prs1_busy; // @[execution-unit.scala:498:30]
wire fdiv_resp_fflags_bits_uop_prs2_busy; // @[execution-unit.scala:498:30]
wire fdiv_resp_fflags_bits_uop_prs3_busy; // @[execution-unit.scala:498:30]
wire fdiv_resp_fflags_bits_uop_ppred_busy; // @[execution-unit.scala:498:30]
wire [6:0] fdiv_resp_fflags_bits_uop_stale_pdst; // @[execution-unit.scala:498:30]
wire fdiv_resp_fflags_bits_uop_exception; // @[execution-unit.scala:498:30]
wire [63:0] fdiv_resp_fflags_bits_uop_exc_cause; // @[execution-unit.scala:498:30]
wire fdiv_resp_fflags_bits_uop_bypassable; // @[execution-unit.scala:498:30]
wire [4:0] fdiv_resp_fflags_bits_uop_mem_cmd; // @[execution-unit.scala:498:30]
wire [1:0] fdiv_resp_fflags_bits_uop_mem_size; // @[execution-unit.scala:498:30]
wire fdiv_resp_fflags_bits_uop_mem_signed; // @[execution-unit.scala:498:30]
wire fdiv_resp_fflags_bits_uop_is_fence; // @[execution-unit.scala:498:30]
wire fdiv_resp_fflags_bits_uop_is_fencei; // @[execution-unit.scala:498:30]
wire fdiv_resp_fflags_bits_uop_is_amo; // @[execution-unit.scala:498:30]
wire fdiv_resp_fflags_bits_uop_uses_ldq; // @[execution-unit.scala:498:30]
wire fdiv_resp_fflags_bits_uop_uses_stq; // @[execution-unit.scala:498:30]
wire fdiv_resp_fflags_bits_uop_is_sys_pc2epc; // @[execution-unit.scala:498:30]
wire fdiv_resp_fflags_bits_uop_is_unique; // @[execution-unit.scala:498:30]
wire fdiv_resp_fflags_bits_uop_flush_on_commit; // @[execution-unit.scala:498:30]
wire fdiv_resp_fflags_bits_uop_ldst_is_rs1; // @[execution-unit.scala:498:30]
wire [5:0] fdiv_resp_fflags_bits_uop_ldst; // @[execution-unit.scala:498:30]
wire [5:0] fdiv_resp_fflags_bits_uop_lrs1; // @[execution-unit.scala:498:30]
wire [5:0] fdiv_resp_fflags_bits_uop_lrs2; // @[execution-unit.scala:498:30]
wire [5:0] fdiv_resp_fflags_bits_uop_lrs3; // @[execution-unit.scala:498:30]
wire fdiv_resp_fflags_bits_uop_ldst_val; // @[execution-unit.scala:498:30]
wire [1:0] fdiv_resp_fflags_bits_uop_dst_rtype; // @[execution-unit.scala:498:30]
wire [1:0] fdiv_resp_fflags_bits_uop_lrs1_rtype; // @[execution-unit.scala:498:30]
wire [1:0] fdiv_resp_fflags_bits_uop_lrs2_rtype; // @[execution-unit.scala:498:30]
wire fdiv_resp_fflags_bits_uop_frs3_en; // @[execution-unit.scala:498:30]
wire fdiv_resp_fflags_bits_uop_fp_val; // @[execution-unit.scala:498:30]
wire fdiv_resp_fflags_bits_uop_fp_single; // @[execution-unit.scala:498:30]
wire fdiv_resp_fflags_bits_uop_xcpt_pf_if; // @[execution-unit.scala:498:30]
wire fdiv_resp_fflags_bits_uop_xcpt_ae_if; // @[execution-unit.scala:498:30]
wire fdiv_resp_fflags_bits_uop_xcpt_ma_if; // @[execution-unit.scala:498:30]
wire fdiv_resp_fflags_bits_uop_bp_debug_if; // @[execution-unit.scala:498:30]
wire fdiv_resp_fflags_bits_uop_bp_xcpt_if; // @[execution-unit.scala:498:30]
wire [1:0] fdiv_resp_fflags_bits_uop_debug_fsrc; // @[execution-unit.scala:498:30]
wire [1:0] fdiv_resp_fflags_bits_uop_debug_tsrc; // @[execution-unit.scala:498:30]
wire [4:0] fdiv_resp_fflags_bits_flags; // @[execution-unit.scala:498:30]
wire fdiv_resp_fflags_valid; // @[execution-unit.scala:498:30]
wire [9:0] _fdiv_busy_T_1 = io_req_bits_uop_fu_code_0 & 10'h80; // @[execution-unit.scala:437:7]
wire _fdiv_busy_T = ~_FDivSqrtUnit_io_req_ready; // @[execution-unit.scala:502:22, :516:18]
wire _fdiv_busy_T_2 = |_fdiv_busy_T_1; // @[micro-op.scala:154:{40,47}]
wire _fdiv_busy_T_3 = io_req_valid_0 & _fdiv_busy_T_2; // @[execution-unit.scala:437:7, :516:58]
assign _fdiv_busy_T_4 = _fdiv_busy_T | _fdiv_busy_T_3; // @[execution-unit.scala:516:{18,41,58}]
assign fdiv_busy = _fdiv_busy_T_4; // @[execution-unit.scala:461:27, :516:41]
wire _io_fresp_valid_T = _FPUUnit_io_resp_valid | _FDivSqrtUnit_io_resp_valid; // @[execution-unit.scala:477:17, :502:22, :525:65]
wire [9:0] _GEN = _FPUUnit_io_resp_bits_uop_fu_code & 10'h200; // @[execution-unit.scala:477:17]
wire [9:0] _io_fresp_valid_T_1; // @[micro-op.scala:154:40]
assign _io_fresp_valid_T_1 = _GEN; // @[micro-op.scala:154:40]
wire [9:0] _queue_io_enq_valid_T; // @[micro-op.scala:154:40]
assign _queue_io_enq_valid_T = _GEN; // @[micro-op.scala:154:40]
wire _io_fresp_valid_T_2 = |_io_fresp_valid_T_1; // @[micro-op.scala:154:{40,47}]
wire _io_fresp_valid_T_3 = _FPUUnit_io_resp_valid & _io_fresp_valid_T_2; // @[execution-unit.scala:477:17, :526:47]
wire _io_fresp_valid_T_4 = ~_io_fresp_valid_T_3; // @[execution-unit.scala:526:{27,47}]
assign _io_fresp_valid_T_5 = _io_fresp_valid_T & _io_fresp_valid_T_4; // @[execution-unit.scala:525:{65,69}, :526:27]
assign io_fresp_valid_0 = _io_fresp_valid_T_5; // @[execution-unit.scala:437:7, :525:69]
assign _io_fresp_bits_uop_T_uopc = _FPUUnit_io_resp_valid ? _FPUUnit_io_resp_bits_uop_uopc : _FDivSqrtUnit_io_resp_bits_uop_uopc; // @[Mux.scala:50:70]
assign _io_fresp_bits_uop_T_inst = _FPUUnit_io_resp_valid ? _FPUUnit_io_resp_bits_uop_inst : _FDivSqrtUnit_io_resp_bits_uop_inst; // @[Mux.scala:50:70]
assign _io_fresp_bits_uop_T_debug_inst = _FPUUnit_io_resp_valid ? _FPUUnit_io_resp_bits_uop_debug_inst : _FDivSqrtUnit_io_resp_bits_uop_debug_inst; // @[Mux.scala:50:70]
assign _io_fresp_bits_uop_T_is_rvc = _FPUUnit_io_resp_valid ? _FPUUnit_io_resp_bits_uop_is_rvc : _FDivSqrtUnit_io_resp_bits_uop_is_rvc; // @[Mux.scala:50:70]
assign _io_fresp_bits_uop_T_debug_pc = _FPUUnit_io_resp_valid ? _FPUUnit_io_resp_bits_uop_debug_pc : _FDivSqrtUnit_io_resp_bits_uop_debug_pc; // @[Mux.scala:50:70]
assign _io_fresp_bits_uop_T_iq_type = _FPUUnit_io_resp_valid ? _FPUUnit_io_resp_bits_uop_iq_type : _FDivSqrtUnit_io_resp_bits_uop_iq_type; // @[Mux.scala:50:70]
assign _io_fresp_bits_uop_T_fu_code = _FPUUnit_io_resp_valid ? _FPUUnit_io_resp_bits_uop_fu_code : _FDivSqrtUnit_io_resp_bits_uop_fu_code; // @[Mux.scala:50:70]
assign _io_fresp_bits_uop_T_ctrl_br_type = _FPUUnit_io_resp_valid ? _FPUUnit_io_resp_bits_uop_ctrl_br_type : _FDivSqrtUnit_io_resp_bits_uop_ctrl_br_type; // @[Mux.scala:50:70]
assign _io_fresp_bits_uop_T_ctrl_op1_sel = _FPUUnit_io_resp_valid ? _FPUUnit_io_resp_bits_uop_ctrl_op1_sel : _FDivSqrtUnit_io_resp_bits_uop_ctrl_op1_sel; // @[Mux.scala:50:70]
assign _io_fresp_bits_uop_T_ctrl_op2_sel = _FPUUnit_io_resp_valid ? _FPUUnit_io_resp_bits_uop_ctrl_op2_sel : _FDivSqrtUnit_io_resp_bits_uop_ctrl_op2_sel; // @[Mux.scala:50:70]
assign _io_fresp_bits_uop_T_ctrl_imm_sel = _FPUUnit_io_resp_valid ? _FPUUnit_io_resp_bits_uop_ctrl_imm_sel : _FDivSqrtUnit_io_resp_bits_uop_ctrl_imm_sel; // @[Mux.scala:50:70]
assign _io_fresp_bits_uop_T_ctrl_op_fcn = _FPUUnit_io_resp_valid ? _FPUUnit_io_resp_bits_uop_ctrl_op_fcn : _FDivSqrtUnit_io_resp_bits_uop_ctrl_op_fcn; // @[Mux.scala:50:70]
assign _io_fresp_bits_uop_T_ctrl_fcn_dw = _FPUUnit_io_resp_valid ? _FPUUnit_io_resp_bits_uop_ctrl_fcn_dw : _FDivSqrtUnit_io_resp_bits_uop_ctrl_fcn_dw; // @[Mux.scala:50:70]
assign _io_fresp_bits_uop_T_ctrl_csr_cmd = _FPUUnit_io_resp_valid ? _FPUUnit_io_resp_bits_uop_ctrl_csr_cmd : _FDivSqrtUnit_io_resp_bits_uop_ctrl_csr_cmd; // @[Mux.scala:50:70]
assign _io_fresp_bits_uop_T_ctrl_is_load = _FPUUnit_io_resp_valid ? _FPUUnit_io_resp_bits_uop_ctrl_is_load : _FDivSqrtUnit_io_resp_bits_uop_ctrl_is_load; // @[Mux.scala:50:70]
assign _io_fresp_bits_uop_T_ctrl_is_sta = _FPUUnit_io_resp_valid ? _FPUUnit_io_resp_bits_uop_ctrl_is_sta : _FDivSqrtUnit_io_resp_bits_uop_ctrl_is_sta; // @[Mux.scala:50:70]
assign _io_fresp_bits_uop_T_ctrl_is_std = _FPUUnit_io_resp_valid ? _FPUUnit_io_resp_bits_uop_ctrl_is_std : _FDivSqrtUnit_io_resp_bits_uop_ctrl_is_std; // @[Mux.scala:50:70]
assign _io_fresp_bits_uop_T_iw_state = _FPUUnit_io_resp_valid ? _FPUUnit_io_resp_bits_uop_iw_state : _FDivSqrtUnit_io_resp_bits_uop_iw_state; // @[Mux.scala:50:70]
assign _io_fresp_bits_uop_T_iw_p1_poisoned = _FPUUnit_io_resp_valid ? _FPUUnit_io_resp_bits_uop_iw_p1_poisoned : _FDivSqrtUnit_io_resp_bits_uop_iw_p1_poisoned; // @[Mux.scala:50:70]
assign _io_fresp_bits_uop_T_iw_p2_poisoned = _FPUUnit_io_resp_valid ? _FPUUnit_io_resp_bits_uop_iw_p2_poisoned : _FDivSqrtUnit_io_resp_bits_uop_iw_p2_poisoned; // @[Mux.scala:50:70]
assign _io_fresp_bits_uop_T_is_br = _FPUUnit_io_resp_valid ? _FPUUnit_io_resp_bits_uop_is_br : _FDivSqrtUnit_io_resp_bits_uop_is_br; // @[Mux.scala:50:70]
assign _io_fresp_bits_uop_T_is_jalr = _FPUUnit_io_resp_valid ? _FPUUnit_io_resp_bits_uop_is_jalr : _FDivSqrtUnit_io_resp_bits_uop_is_jalr; // @[Mux.scala:50:70]
assign _io_fresp_bits_uop_T_is_jal = _FPUUnit_io_resp_valid ? _FPUUnit_io_resp_bits_uop_is_jal : _FDivSqrtUnit_io_resp_bits_uop_is_jal; // @[Mux.scala:50:70]
assign _io_fresp_bits_uop_T_is_sfb = _FPUUnit_io_resp_valid ? _FPUUnit_io_resp_bits_uop_is_sfb : _FDivSqrtUnit_io_resp_bits_uop_is_sfb; // @[Mux.scala:50:70]
assign _io_fresp_bits_uop_T_br_mask = _FPUUnit_io_resp_valid ? _FPUUnit_io_resp_bits_uop_br_mask : _FDivSqrtUnit_io_resp_bits_uop_br_mask; // @[Mux.scala:50:70]
assign _io_fresp_bits_uop_T_br_tag = _FPUUnit_io_resp_valid ? _FPUUnit_io_resp_bits_uop_br_tag : _FDivSqrtUnit_io_resp_bits_uop_br_tag; // @[Mux.scala:50:70]
assign _io_fresp_bits_uop_T_ftq_idx = _FPUUnit_io_resp_valid ? _FPUUnit_io_resp_bits_uop_ftq_idx : _FDivSqrtUnit_io_resp_bits_uop_ftq_idx; // @[Mux.scala:50:70]
assign _io_fresp_bits_uop_T_edge_inst = _FPUUnit_io_resp_valid ? _FPUUnit_io_resp_bits_uop_edge_inst : _FDivSqrtUnit_io_resp_bits_uop_edge_inst; // @[Mux.scala:50:70]
assign _io_fresp_bits_uop_T_pc_lob = _FPUUnit_io_resp_valid ? _FPUUnit_io_resp_bits_uop_pc_lob : _FDivSqrtUnit_io_resp_bits_uop_pc_lob; // @[Mux.scala:50:70]
assign _io_fresp_bits_uop_T_taken = _FPUUnit_io_resp_valid ? _FPUUnit_io_resp_bits_uop_taken : _FDivSqrtUnit_io_resp_bits_uop_taken; // @[Mux.scala:50:70]
assign _io_fresp_bits_uop_T_imm_packed = _FPUUnit_io_resp_valid ? _FPUUnit_io_resp_bits_uop_imm_packed : _FDivSqrtUnit_io_resp_bits_uop_imm_packed; // @[Mux.scala:50:70]
assign _io_fresp_bits_uop_T_csr_addr = _FPUUnit_io_resp_valid ? _FPUUnit_io_resp_bits_uop_csr_addr : _FDivSqrtUnit_io_resp_bits_uop_csr_addr; // @[Mux.scala:50:70]
assign _io_fresp_bits_uop_T_rob_idx = _FPUUnit_io_resp_valid ? _FPUUnit_io_resp_bits_uop_rob_idx : _FDivSqrtUnit_io_resp_bits_uop_rob_idx; // @[Mux.scala:50:70]
assign _io_fresp_bits_uop_T_ldq_idx = _FPUUnit_io_resp_valid ? _FPUUnit_io_resp_bits_uop_ldq_idx : _FDivSqrtUnit_io_resp_bits_uop_ldq_idx; // @[Mux.scala:50:70]
assign _io_fresp_bits_uop_T_stq_idx = _FPUUnit_io_resp_valid ? _FPUUnit_io_resp_bits_uop_stq_idx : _FDivSqrtUnit_io_resp_bits_uop_stq_idx; // @[Mux.scala:50:70]
assign _io_fresp_bits_uop_T_rxq_idx = _FPUUnit_io_resp_valid ? _FPUUnit_io_resp_bits_uop_rxq_idx : _FDivSqrtUnit_io_resp_bits_uop_rxq_idx; // @[Mux.scala:50:70]
assign _io_fresp_bits_uop_T_pdst = _FPUUnit_io_resp_valid ? _FPUUnit_io_resp_bits_uop_pdst : _FDivSqrtUnit_io_resp_bits_uop_pdst; // @[Mux.scala:50:70]
assign _io_fresp_bits_uop_T_prs1 = _FPUUnit_io_resp_valid ? _FPUUnit_io_resp_bits_uop_prs1 : _FDivSqrtUnit_io_resp_bits_uop_prs1; // @[Mux.scala:50:70]
assign _io_fresp_bits_uop_T_prs2 = _FPUUnit_io_resp_valid ? _FPUUnit_io_resp_bits_uop_prs2 : _FDivSqrtUnit_io_resp_bits_uop_prs2; // @[Mux.scala:50:70]
assign _io_fresp_bits_uop_T_prs3 = _FPUUnit_io_resp_valid ? _FPUUnit_io_resp_bits_uop_prs3 : _FDivSqrtUnit_io_resp_bits_uop_prs3; // @[Mux.scala:50:70]
assign _io_fresp_bits_uop_T_ppred = _FPUUnit_io_resp_valid ? _FPUUnit_io_resp_bits_uop_ppred : _FDivSqrtUnit_io_resp_bits_uop_ppred; // @[Mux.scala:50:70]
assign _io_fresp_bits_uop_T_prs1_busy = _FPUUnit_io_resp_valid ? _FPUUnit_io_resp_bits_uop_prs1_busy : _FDivSqrtUnit_io_resp_bits_uop_prs1_busy; // @[Mux.scala:50:70]
assign _io_fresp_bits_uop_T_prs2_busy = _FPUUnit_io_resp_valid ? _FPUUnit_io_resp_bits_uop_prs2_busy : _FDivSqrtUnit_io_resp_bits_uop_prs2_busy; // @[Mux.scala:50:70]
assign _io_fresp_bits_uop_T_prs3_busy = _FPUUnit_io_resp_valid ? _FPUUnit_io_resp_bits_uop_prs3_busy : _FDivSqrtUnit_io_resp_bits_uop_prs3_busy; // @[Mux.scala:50:70]
assign _io_fresp_bits_uop_T_ppred_busy = _FPUUnit_io_resp_valid ? _FPUUnit_io_resp_bits_uop_ppred_busy : _FDivSqrtUnit_io_resp_bits_uop_ppred_busy; // @[Mux.scala:50:70]
assign _io_fresp_bits_uop_T_stale_pdst = _FPUUnit_io_resp_valid ? _FPUUnit_io_resp_bits_uop_stale_pdst : _FDivSqrtUnit_io_resp_bits_uop_stale_pdst; // @[Mux.scala:50:70]
assign _io_fresp_bits_uop_T_exception = _FPUUnit_io_resp_valid ? _FPUUnit_io_resp_bits_uop_exception : _FDivSqrtUnit_io_resp_bits_uop_exception; // @[Mux.scala:50:70]
assign _io_fresp_bits_uop_T_exc_cause = _FPUUnit_io_resp_valid ? _FPUUnit_io_resp_bits_uop_exc_cause : _FDivSqrtUnit_io_resp_bits_uop_exc_cause; // @[Mux.scala:50:70]
assign _io_fresp_bits_uop_T_bypassable = _FPUUnit_io_resp_valid ? _FPUUnit_io_resp_bits_uop_bypassable : _FDivSqrtUnit_io_resp_bits_uop_bypassable; // @[Mux.scala:50:70]
assign _io_fresp_bits_uop_T_mem_cmd = _FPUUnit_io_resp_valid ? _FPUUnit_io_resp_bits_uop_mem_cmd : _FDivSqrtUnit_io_resp_bits_uop_mem_cmd; // @[Mux.scala:50:70]
assign _io_fresp_bits_uop_T_mem_size = _FPUUnit_io_resp_valid ? _FPUUnit_io_resp_bits_uop_mem_size : _FDivSqrtUnit_io_resp_bits_uop_mem_size; // @[Mux.scala:50:70]
assign _io_fresp_bits_uop_T_mem_signed = _FPUUnit_io_resp_valid ? _FPUUnit_io_resp_bits_uop_mem_signed : _FDivSqrtUnit_io_resp_bits_uop_mem_signed; // @[Mux.scala:50:70]
assign _io_fresp_bits_uop_T_is_fence = _FPUUnit_io_resp_valid ? _FPUUnit_io_resp_bits_uop_is_fence : _FDivSqrtUnit_io_resp_bits_uop_is_fence; // @[Mux.scala:50:70]
assign _io_fresp_bits_uop_T_is_fencei = _FPUUnit_io_resp_valid ? _FPUUnit_io_resp_bits_uop_is_fencei : _FDivSqrtUnit_io_resp_bits_uop_is_fencei; // @[Mux.scala:50:70]
assign _io_fresp_bits_uop_T_is_amo = _FPUUnit_io_resp_valid ? _FPUUnit_io_resp_bits_uop_is_amo : _FDivSqrtUnit_io_resp_bits_uop_is_amo; // @[Mux.scala:50:70]
assign _io_fresp_bits_uop_T_uses_ldq = _FPUUnit_io_resp_valid ? _FPUUnit_io_resp_bits_uop_uses_ldq : _FDivSqrtUnit_io_resp_bits_uop_uses_ldq; // @[Mux.scala:50:70]
assign _io_fresp_bits_uop_T_uses_stq = _FPUUnit_io_resp_valid ? _FPUUnit_io_resp_bits_uop_uses_stq : _FDivSqrtUnit_io_resp_bits_uop_uses_stq; // @[Mux.scala:50:70]
assign _io_fresp_bits_uop_T_is_sys_pc2epc = _FPUUnit_io_resp_valid ? _FPUUnit_io_resp_bits_uop_is_sys_pc2epc : _FDivSqrtUnit_io_resp_bits_uop_is_sys_pc2epc; // @[Mux.scala:50:70]
assign _io_fresp_bits_uop_T_is_unique = _FPUUnit_io_resp_valid ? _FPUUnit_io_resp_bits_uop_is_unique : _FDivSqrtUnit_io_resp_bits_uop_is_unique; // @[Mux.scala:50:70]
assign _io_fresp_bits_uop_T_flush_on_commit = _FPUUnit_io_resp_valid ? _FPUUnit_io_resp_bits_uop_flush_on_commit : _FDivSqrtUnit_io_resp_bits_uop_flush_on_commit; // @[Mux.scala:50:70]
assign _io_fresp_bits_uop_T_ldst_is_rs1 = _FPUUnit_io_resp_valid ? _FPUUnit_io_resp_bits_uop_ldst_is_rs1 : _FDivSqrtUnit_io_resp_bits_uop_ldst_is_rs1; // @[Mux.scala:50:70]
assign _io_fresp_bits_uop_T_ldst = _FPUUnit_io_resp_valid ? _FPUUnit_io_resp_bits_uop_ldst : _FDivSqrtUnit_io_resp_bits_uop_ldst; // @[Mux.scala:50:70]
assign _io_fresp_bits_uop_T_lrs1 = _FPUUnit_io_resp_valid ? _FPUUnit_io_resp_bits_uop_lrs1 : _FDivSqrtUnit_io_resp_bits_uop_lrs1; // @[Mux.scala:50:70]
assign _io_fresp_bits_uop_T_lrs2 = _FPUUnit_io_resp_valid ? _FPUUnit_io_resp_bits_uop_lrs2 : _FDivSqrtUnit_io_resp_bits_uop_lrs2; // @[Mux.scala:50:70]
assign _io_fresp_bits_uop_T_lrs3 = _FPUUnit_io_resp_valid ? _FPUUnit_io_resp_bits_uop_lrs3 : _FDivSqrtUnit_io_resp_bits_uop_lrs3; // @[Mux.scala:50:70]
assign _io_fresp_bits_uop_T_ldst_val = _FPUUnit_io_resp_valid ? _FPUUnit_io_resp_bits_uop_ldst_val : _FDivSqrtUnit_io_resp_bits_uop_ldst_val; // @[Mux.scala:50:70]
assign _io_fresp_bits_uop_T_dst_rtype = _FPUUnit_io_resp_valid ? _FPUUnit_io_resp_bits_uop_dst_rtype : _FDivSqrtUnit_io_resp_bits_uop_dst_rtype; // @[Mux.scala:50:70]
assign _io_fresp_bits_uop_T_lrs1_rtype = _FPUUnit_io_resp_valid ? _FPUUnit_io_resp_bits_uop_lrs1_rtype : _FDivSqrtUnit_io_resp_bits_uop_lrs1_rtype; // @[Mux.scala:50:70]
assign _io_fresp_bits_uop_T_lrs2_rtype = _FPUUnit_io_resp_valid ? _FPUUnit_io_resp_bits_uop_lrs2_rtype : _FDivSqrtUnit_io_resp_bits_uop_lrs2_rtype; // @[Mux.scala:50:70]
assign _io_fresp_bits_uop_T_frs3_en = _FPUUnit_io_resp_valid ? _FPUUnit_io_resp_bits_uop_frs3_en : _FDivSqrtUnit_io_resp_bits_uop_frs3_en; // @[Mux.scala:50:70]
assign _io_fresp_bits_uop_T_fp_val = _FPUUnit_io_resp_valid ? _FPUUnit_io_resp_bits_uop_fp_val : _FDivSqrtUnit_io_resp_bits_uop_fp_val; // @[Mux.scala:50:70]
assign _io_fresp_bits_uop_T_fp_single = _FPUUnit_io_resp_valid ? _FPUUnit_io_resp_bits_uop_fp_single : _FDivSqrtUnit_io_resp_bits_uop_fp_single; // @[Mux.scala:50:70]
assign _io_fresp_bits_uop_T_xcpt_pf_if = _FPUUnit_io_resp_valid ? _FPUUnit_io_resp_bits_uop_xcpt_pf_if : _FDivSqrtUnit_io_resp_bits_uop_xcpt_pf_if; // @[Mux.scala:50:70]
assign _io_fresp_bits_uop_T_xcpt_ae_if = _FPUUnit_io_resp_valid ? _FPUUnit_io_resp_bits_uop_xcpt_ae_if : _FDivSqrtUnit_io_resp_bits_uop_xcpt_ae_if; // @[Mux.scala:50:70]
assign _io_fresp_bits_uop_T_xcpt_ma_if = _FPUUnit_io_resp_valid ? _FPUUnit_io_resp_bits_uop_xcpt_ma_if : _FDivSqrtUnit_io_resp_bits_uop_xcpt_ma_if; // @[Mux.scala:50:70]
assign _io_fresp_bits_uop_T_bp_debug_if = _FPUUnit_io_resp_valid ? _FPUUnit_io_resp_bits_uop_bp_debug_if : _FDivSqrtUnit_io_resp_bits_uop_bp_debug_if; // @[Mux.scala:50:70]
assign _io_fresp_bits_uop_T_bp_xcpt_if = _FPUUnit_io_resp_valid ? _FPUUnit_io_resp_bits_uop_bp_xcpt_if : _FDivSqrtUnit_io_resp_bits_uop_bp_xcpt_if; // @[Mux.scala:50:70]
assign _io_fresp_bits_uop_T_debug_fsrc = _FPUUnit_io_resp_valid ? _FPUUnit_io_resp_bits_uop_debug_fsrc : _FDivSqrtUnit_io_resp_bits_uop_debug_fsrc; // @[Mux.scala:50:70]
assign _io_fresp_bits_uop_T_debug_tsrc = _FPUUnit_io_resp_valid ? _FPUUnit_io_resp_bits_uop_debug_tsrc : _FDivSqrtUnit_io_resp_bits_uop_debug_tsrc; // @[Mux.scala:50:70]
assign io_fresp_bits_uop_uopc_0 = _io_fresp_bits_uop_T_uopc; // @[Mux.scala:50:70]
assign io_fresp_bits_uop_inst_0 = _io_fresp_bits_uop_T_inst; // @[Mux.scala:50:70]
assign io_fresp_bits_uop_debug_inst_0 = _io_fresp_bits_uop_T_debug_inst; // @[Mux.scala:50:70]
assign io_fresp_bits_uop_is_rvc_0 = _io_fresp_bits_uop_T_is_rvc; // @[Mux.scala:50:70]
assign io_fresp_bits_uop_debug_pc_0 = _io_fresp_bits_uop_T_debug_pc; // @[Mux.scala:50:70]
assign io_fresp_bits_uop_iq_type_0 = _io_fresp_bits_uop_T_iq_type; // @[Mux.scala:50:70]
assign io_fresp_bits_uop_fu_code_0 = _io_fresp_bits_uop_T_fu_code; // @[Mux.scala:50:70]
assign io_fresp_bits_uop_ctrl_br_type_0 = _io_fresp_bits_uop_T_ctrl_br_type; // @[Mux.scala:50:70]
assign io_fresp_bits_uop_ctrl_op1_sel_0 = _io_fresp_bits_uop_T_ctrl_op1_sel; // @[Mux.scala:50:70]
assign io_fresp_bits_uop_ctrl_op2_sel_0 = _io_fresp_bits_uop_T_ctrl_op2_sel; // @[Mux.scala:50:70]
assign io_fresp_bits_uop_ctrl_imm_sel_0 = _io_fresp_bits_uop_T_ctrl_imm_sel; // @[Mux.scala:50:70]
assign io_fresp_bits_uop_ctrl_op_fcn_0 = _io_fresp_bits_uop_T_ctrl_op_fcn; // @[Mux.scala:50:70]
assign io_fresp_bits_uop_ctrl_fcn_dw_0 = _io_fresp_bits_uop_T_ctrl_fcn_dw; // @[Mux.scala:50:70]
assign io_fresp_bits_uop_ctrl_csr_cmd_0 = _io_fresp_bits_uop_T_ctrl_csr_cmd; // @[Mux.scala:50:70]
assign io_fresp_bits_uop_ctrl_is_load_0 = _io_fresp_bits_uop_T_ctrl_is_load; // @[Mux.scala:50:70]
assign io_fresp_bits_uop_ctrl_is_sta_0 = _io_fresp_bits_uop_T_ctrl_is_sta; // @[Mux.scala:50:70]
assign io_fresp_bits_uop_ctrl_is_std_0 = _io_fresp_bits_uop_T_ctrl_is_std; // @[Mux.scala:50:70]
assign io_fresp_bits_uop_iw_state_0 = _io_fresp_bits_uop_T_iw_state; // @[Mux.scala:50:70]
assign io_fresp_bits_uop_iw_p1_poisoned_0 = _io_fresp_bits_uop_T_iw_p1_poisoned; // @[Mux.scala:50:70]
assign io_fresp_bits_uop_iw_p2_poisoned_0 = _io_fresp_bits_uop_T_iw_p2_poisoned; // @[Mux.scala:50:70]
assign io_fresp_bits_uop_is_br_0 = _io_fresp_bits_uop_T_is_br; // @[Mux.scala:50:70]
assign io_fresp_bits_uop_is_jalr_0 = _io_fresp_bits_uop_T_is_jalr; // @[Mux.scala:50:70]
assign io_fresp_bits_uop_is_jal_0 = _io_fresp_bits_uop_T_is_jal; // @[Mux.scala:50:70]
assign io_fresp_bits_uop_is_sfb_0 = _io_fresp_bits_uop_T_is_sfb; // @[Mux.scala:50:70]
assign io_fresp_bits_uop_br_mask_0 = _io_fresp_bits_uop_T_br_mask; // @[Mux.scala:50:70]
assign io_fresp_bits_uop_br_tag_0 = _io_fresp_bits_uop_T_br_tag; // @[Mux.scala:50:70]
assign io_fresp_bits_uop_ftq_idx_0 = _io_fresp_bits_uop_T_ftq_idx; // @[Mux.scala:50:70]
assign io_fresp_bits_uop_edge_inst_0 = _io_fresp_bits_uop_T_edge_inst; // @[Mux.scala:50:70]
assign io_fresp_bits_uop_pc_lob_0 = _io_fresp_bits_uop_T_pc_lob; // @[Mux.scala:50:70]
assign io_fresp_bits_uop_taken_0 = _io_fresp_bits_uop_T_taken; // @[Mux.scala:50:70]
assign io_fresp_bits_uop_imm_packed_0 = _io_fresp_bits_uop_T_imm_packed; // @[Mux.scala:50:70]
assign io_fresp_bits_uop_csr_addr_0 = _io_fresp_bits_uop_T_csr_addr; // @[Mux.scala:50:70]
assign io_fresp_bits_uop_rob_idx_0 = _io_fresp_bits_uop_T_rob_idx; // @[Mux.scala:50:70]
assign io_fresp_bits_uop_ldq_idx_0 = _io_fresp_bits_uop_T_ldq_idx; // @[Mux.scala:50:70]
assign io_fresp_bits_uop_stq_idx_0 = _io_fresp_bits_uop_T_stq_idx; // @[Mux.scala:50:70]
assign io_fresp_bits_uop_rxq_idx_0 = _io_fresp_bits_uop_T_rxq_idx; // @[Mux.scala:50:70]
assign io_fresp_bits_uop_pdst_0 = _io_fresp_bits_uop_T_pdst; // @[Mux.scala:50:70]
assign io_fresp_bits_uop_prs1_0 = _io_fresp_bits_uop_T_prs1; // @[Mux.scala:50:70]
assign io_fresp_bits_uop_prs2_0 = _io_fresp_bits_uop_T_prs2; // @[Mux.scala:50:70]
assign io_fresp_bits_uop_prs3_0 = _io_fresp_bits_uop_T_prs3; // @[Mux.scala:50:70]
assign io_fresp_bits_uop_ppred_0 = _io_fresp_bits_uop_T_ppred; // @[Mux.scala:50:70]
assign io_fresp_bits_uop_prs1_busy_0 = _io_fresp_bits_uop_T_prs1_busy; // @[Mux.scala:50:70]
assign io_fresp_bits_uop_prs2_busy_0 = _io_fresp_bits_uop_T_prs2_busy; // @[Mux.scala:50:70]
assign io_fresp_bits_uop_prs3_busy_0 = _io_fresp_bits_uop_T_prs3_busy; // @[Mux.scala:50:70]
assign io_fresp_bits_uop_ppred_busy_0 = _io_fresp_bits_uop_T_ppred_busy; // @[Mux.scala:50:70]
assign io_fresp_bits_uop_stale_pdst_0 = _io_fresp_bits_uop_T_stale_pdst; // @[Mux.scala:50:70]
assign io_fresp_bits_uop_exception_0 = _io_fresp_bits_uop_T_exception; // @[Mux.scala:50:70]
assign io_fresp_bits_uop_exc_cause_0 = _io_fresp_bits_uop_T_exc_cause; // @[Mux.scala:50:70]
assign io_fresp_bits_uop_bypassable_0 = _io_fresp_bits_uop_T_bypassable; // @[Mux.scala:50:70]
assign io_fresp_bits_uop_mem_cmd_0 = _io_fresp_bits_uop_T_mem_cmd; // @[Mux.scala:50:70]
assign io_fresp_bits_uop_mem_size_0 = _io_fresp_bits_uop_T_mem_size; // @[Mux.scala:50:70]
assign io_fresp_bits_uop_mem_signed_0 = _io_fresp_bits_uop_T_mem_signed; // @[Mux.scala:50:70]
assign io_fresp_bits_uop_is_fence_0 = _io_fresp_bits_uop_T_is_fence; // @[Mux.scala:50:70]
assign io_fresp_bits_uop_is_fencei_0 = _io_fresp_bits_uop_T_is_fencei; // @[Mux.scala:50:70]
assign io_fresp_bits_uop_is_amo_0 = _io_fresp_bits_uop_T_is_amo; // @[Mux.scala:50:70]
assign io_fresp_bits_uop_uses_ldq_0 = _io_fresp_bits_uop_T_uses_ldq; // @[Mux.scala:50:70]
assign io_fresp_bits_uop_uses_stq_0 = _io_fresp_bits_uop_T_uses_stq; // @[Mux.scala:50:70]
assign io_fresp_bits_uop_is_sys_pc2epc_0 = _io_fresp_bits_uop_T_is_sys_pc2epc; // @[Mux.scala:50:70]
assign io_fresp_bits_uop_is_unique_0 = _io_fresp_bits_uop_T_is_unique; // @[Mux.scala:50:70]
assign io_fresp_bits_uop_flush_on_commit_0 = _io_fresp_bits_uop_T_flush_on_commit; // @[Mux.scala:50:70]
assign io_fresp_bits_uop_ldst_is_rs1_0 = _io_fresp_bits_uop_T_ldst_is_rs1; // @[Mux.scala:50:70]
assign io_fresp_bits_uop_ldst_0 = _io_fresp_bits_uop_T_ldst; // @[Mux.scala:50:70]
assign io_fresp_bits_uop_lrs1_0 = _io_fresp_bits_uop_T_lrs1; // @[Mux.scala:50:70]
assign io_fresp_bits_uop_lrs2_0 = _io_fresp_bits_uop_T_lrs2; // @[Mux.scala:50:70]
assign io_fresp_bits_uop_lrs3_0 = _io_fresp_bits_uop_T_lrs3; // @[Mux.scala:50:70]
assign io_fresp_bits_uop_ldst_val_0 = _io_fresp_bits_uop_T_ldst_val; // @[Mux.scala:50:70]
assign io_fresp_bits_uop_dst_rtype_0 = _io_fresp_bits_uop_T_dst_rtype; // @[Mux.scala:50:70]
assign io_fresp_bits_uop_lrs1_rtype_0 = _io_fresp_bits_uop_T_lrs1_rtype; // @[Mux.scala:50:70]
assign io_fresp_bits_uop_lrs2_rtype_0 = _io_fresp_bits_uop_T_lrs2_rtype; // @[Mux.scala:50:70]
assign io_fresp_bits_uop_frs3_en_0 = _io_fresp_bits_uop_T_frs3_en; // @[Mux.scala:50:70]
assign io_fresp_bits_uop_fp_val_0 = _io_fresp_bits_uop_T_fp_val; // @[Mux.scala:50:70]
assign io_fresp_bits_uop_fp_single_0 = _io_fresp_bits_uop_T_fp_single; // @[Mux.scala:50:70]
assign io_fresp_bits_uop_xcpt_pf_if_0 = _io_fresp_bits_uop_T_xcpt_pf_if; // @[Mux.scala:50:70]
assign io_fresp_bits_uop_xcpt_ae_if_0 = _io_fresp_bits_uop_T_xcpt_ae_if; // @[Mux.scala:50:70]
assign io_fresp_bits_uop_xcpt_ma_if_0 = _io_fresp_bits_uop_T_xcpt_ma_if; // @[Mux.scala:50:70]
assign io_fresp_bits_uop_bp_debug_if_0 = _io_fresp_bits_uop_T_bp_debug_if; // @[Mux.scala:50:70]
assign io_fresp_bits_uop_bp_xcpt_if_0 = _io_fresp_bits_uop_T_bp_xcpt_if; // @[Mux.scala:50:70]
assign io_fresp_bits_uop_debug_fsrc_0 = _io_fresp_bits_uop_T_debug_fsrc; // @[Mux.scala:50:70]
assign io_fresp_bits_uop_debug_tsrc_0 = _io_fresp_bits_uop_T_debug_tsrc; // @[Mux.scala:50:70]
assign _io_fresp_bits_data_T = _FPUUnit_io_resp_valid ? _FPUUnit_io_resp_bits_data : _FDivSqrtUnit_io_resp_bits_data; // @[Mux.scala:50:70]
assign io_fresp_bits_data_0 = _io_fresp_bits_data_T; // @[Mux.scala:50:70]
assign _io_fresp_bits_fflags_T_valid = fpu_resp_val ? fpu_resp_fflags_valid : fdiv_resp_fflags_valid; // @[execution-unit.scala:473:30, :474:29, :498:30, :530:30]
assign _io_fresp_bits_fflags_T_bits_uop_uopc = fpu_resp_val ? fpu_resp_fflags_bits_uop_uopc : fdiv_resp_fflags_bits_uop_uopc; // @[execution-unit.scala:473:30, :474:29, :498:30, :530:30]
assign _io_fresp_bits_fflags_T_bits_uop_inst = fpu_resp_val ? fpu_resp_fflags_bits_uop_inst : fdiv_resp_fflags_bits_uop_inst; // @[execution-unit.scala:473:30, :474:29, :498:30, :530:30]
assign _io_fresp_bits_fflags_T_bits_uop_debug_inst = fpu_resp_val ? fpu_resp_fflags_bits_uop_debug_inst : fdiv_resp_fflags_bits_uop_debug_inst; // @[execution-unit.scala:473:30, :474:29, :498:30, :530:30]
assign _io_fresp_bits_fflags_T_bits_uop_is_rvc = fpu_resp_val ? fpu_resp_fflags_bits_uop_is_rvc : fdiv_resp_fflags_bits_uop_is_rvc; // @[execution-unit.scala:473:30, :474:29, :498:30, :530:30]
assign _io_fresp_bits_fflags_T_bits_uop_debug_pc = fpu_resp_val ? fpu_resp_fflags_bits_uop_debug_pc : fdiv_resp_fflags_bits_uop_debug_pc; // @[execution-unit.scala:473:30, :474:29, :498:30, :530:30]
assign _io_fresp_bits_fflags_T_bits_uop_iq_type = fpu_resp_val ? fpu_resp_fflags_bits_uop_iq_type : fdiv_resp_fflags_bits_uop_iq_type; // @[execution-unit.scala:473:30, :474:29, :498:30, :530:30]
assign _io_fresp_bits_fflags_T_bits_uop_fu_code = fpu_resp_val ? fpu_resp_fflags_bits_uop_fu_code : fdiv_resp_fflags_bits_uop_fu_code; // @[execution-unit.scala:473:30, :474:29, :498:30, :530:30]
assign _io_fresp_bits_fflags_T_bits_uop_ctrl_br_type = fpu_resp_val ? fpu_resp_fflags_bits_uop_ctrl_br_type : fdiv_resp_fflags_bits_uop_ctrl_br_type; // @[execution-unit.scala:473:30, :474:29, :498:30, :530:30]
assign _io_fresp_bits_fflags_T_bits_uop_ctrl_op1_sel = fpu_resp_val ? fpu_resp_fflags_bits_uop_ctrl_op1_sel : fdiv_resp_fflags_bits_uop_ctrl_op1_sel; // @[execution-unit.scala:473:30, :474:29, :498:30, :530:30]
assign _io_fresp_bits_fflags_T_bits_uop_ctrl_op2_sel = fpu_resp_val ? fpu_resp_fflags_bits_uop_ctrl_op2_sel : fdiv_resp_fflags_bits_uop_ctrl_op2_sel; // @[execution-unit.scala:473:30, :474:29, :498:30, :530:30]
assign _io_fresp_bits_fflags_T_bits_uop_ctrl_imm_sel = fpu_resp_val ? fpu_resp_fflags_bits_uop_ctrl_imm_sel : fdiv_resp_fflags_bits_uop_ctrl_imm_sel; // @[execution-unit.scala:473:30, :474:29, :498:30, :530:30]
assign _io_fresp_bits_fflags_T_bits_uop_ctrl_op_fcn = fpu_resp_val ? fpu_resp_fflags_bits_uop_ctrl_op_fcn : fdiv_resp_fflags_bits_uop_ctrl_op_fcn; // @[execution-unit.scala:473:30, :474:29, :498:30, :530:30]
assign _io_fresp_bits_fflags_T_bits_uop_ctrl_fcn_dw = fpu_resp_val ? fpu_resp_fflags_bits_uop_ctrl_fcn_dw : fdiv_resp_fflags_bits_uop_ctrl_fcn_dw; // @[execution-unit.scala:473:30, :474:29, :498:30, :530:30]
assign _io_fresp_bits_fflags_T_bits_uop_ctrl_csr_cmd = fpu_resp_val ? fpu_resp_fflags_bits_uop_ctrl_csr_cmd : fdiv_resp_fflags_bits_uop_ctrl_csr_cmd; // @[execution-unit.scala:473:30, :474:29, :498:30, :530:30]
assign _io_fresp_bits_fflags_T_bits_uop_ctrl_is_load = fpu_resp_val ? fpu_resp_fflags_bits_uop_ctrl_is_load : fdiv_resp_fflags_bits_uop_ctrl_is_load; // @[execution-unit.scala:473:30, :474:29, :498:30, :530:30]
assign _io_fresp_bits_fflags_T_bits_uop_ctrl_is_sta = fpu_resp_val ? fpu_resp_fflags_bits_uop_ctrl_is_sta : fdiv_resp_fflags_bits_uop_ctrl_is_sta; // @[execution-unit.scala:473:30, :474:29, :498:30, :530:30]
assign _io_fresp_bits_fflags_T_bits_uop_ctrl_is_std = fpu_resp_val ? fpu_resp_fflags_bits_uop_ctrl_is_std : fdiv_resp_fflags_bits_uop_ctrl_is_std; // @[execution-unit.scala:473:30, :474:29, :498:30, :530:30]
assign _io_fresp_bits_fflags_T_bits_uop_iw_state = fpu_resp_val ? fpu_resp_fflags_bits_uop_iw_state : fdiv_resp_fflags_bits_uop_iw_state; // @[execution-unit.scala:473:30, :474:29, :498:30, :530:30]
assign _io_fresp_bits_fflags_T_bits_uop_iw_p1_poisoned = fpu_resp_val ? fpu_resp_fflags_bits_uop_iw_p1_poisoned : fdiv_resp_fflags_bits_uop_iw_p1_poisoned; // @[execution-unit.scala:473:30, :474:29, :498:30, :530:30]
assign _io_fresp_bits_fflags_T_bits_uop_iw_p2_poisoned = fpu_resp_val ? fpu_resp_fflags_bits_uop_iw_p2_poisoned : fdiv_resp_fflags_bits_uop_iw_p2_poisoned; // @[execution-unit.scala:473:30, :474:29, :498:30, :530:30]
assign _io_fresp_bits_fflags_T_bits_uop_is_br = fpu_resp_val ? fpu_resp_fflags_bits_uop_is_br : fdiv_resp_fflags_bits_uop_is_br; // @[execution-unit.scala:473:30, :474:29, :498:30, :530:30]
assign _io_fresp_bits_fflags_T_bits_uop_is_jalr = fpu_resp_val ? fpu_resp_fflags_bits_uop_is_jalr : fdiv_resp_fflags_bits_uop_is_jalr; // @[execution-unit.scala:473:30, :474:29, :498:30, :530:30]
assign _io_fresp_bits_fflags_T_bits_uop_is_jal = fpu_resp_val ? fpu_resp_fflags_bits_uop_is_jal : fdiv_resp_fflags_bits_uop_is_jal; // @[execution-unit.scala:473:30, :474:29, :498:30, :530:30]
assign _io_fresp_bits_fflags_T_bits_uop_is_sfb = fpu_resp_val ? fpu_resp_fflags_bits_uop_is_sfb : fdiv_resp_fflags_bits_uop_is_sfb; // @[execution-unit.scala:473:30, :474:29, :498:30, :530:30]
assign _io_fresp_bits_fflags_T_bits_uop_br_mask = fpu_resp_val ? fpu_resp_fflags_bits_uop_br_mask : fdiv_resp_fflags_bits_uop_br_mask; // @[execution-unit.scala:473:30, :474:29, :498:30, :530:30]
assign _io_fresp_bits_fflags_T_bits_uop_br_tag = fpu_resp_val ? fpu_resp_fflags_bits_uop_br_tag : fdiv_resp_fflags_bits_uop_br_tag; // @[execution-unit.scala:473:30, :474:29, :498:30, :530:30]
assign _io_fresp_bits_fflags_T_bits_uop_ftq_idx = fpu_resp_val ? fpu_resp_fflags_bits_uop_ftq_idx : fdiv_resp_fflags_bits_uop_ftq_idx; // @[execution-unit.scala:473:30, :474:29, :498:30, :530:30]
assign _io_fresp_bits_fflags_T_bits_uop_edge_inst = fpu_resp_val ? fpu_resp_fflags_bits_uop_edge_inst : fdiv_resp_fflags_bits_uop_edge_inst; // @[execution-unit.scala:473:30, :474:29, :498:30, :530:30]
assign _io_fresp_bits_fflags_T_bits_uop_pc_lob = fpu_resp_val ? fpu_resp_fflags_bits_uop_pc_lob : fdiv_resp_fflags_bits_uop_pc_lob; // @[execution-unit.scala:473:30, :474:29, :498:30, :530:30]
assign _io_fresp_bits_fflags_T_bits_uop_taken = fpu_resp_val ? fpu_resp_fflags_bits_uop_taken : fdiv_resp_fflags_bits_uop_taken; // @[execution-unit.scala:473:30, :474:29, :498:30, :530:30]
assign _io_fresp_bits_fflags_T_bits_uop_imm_packed = fpu_resp_val ? fpu_resp_fflags_bits_uop_imm_packed : fdiv_resp_fflags_bits_uop_imm_packed; // @[execution-unit.scala:473:30, :474:29, :498:30, :530:30]
assign _io_fresp_bits_fflags_T_bits_uop_csr_addr = fpu_resp_val ? fpu_resp_fflags_bits_uop_csr_addr : fdiv_resp_fflags_bits_uop_csr_addr; // @[execution-unit.scala:473:30, :474:29, :498:30, :530:30]
assign _io_fresp_bits_fflags_T_bits_uop_rob_idx = fpu_resp_val ? fpu_resp_fflags_bits_uop_rob_idx : fdiv_resp_fflags_bits_uop_rob_idx; // @[execution-unit.scala:473:30, :474:29, :498:30, :530:30]
assign _io_fresp_bits_fflags_T_bits_uop_ldq_idx = fpu_resp_val ? fpu_resp_fflags_bits_uop_ldq_idx : fdiv_resp_fflags_bits_uop_ldq_idx; // @[execution-unit.scala:473:30, :474:29, :498:30, :530:30]
assign _io_fresp_bits_fflags_T_bits_uop_stq_idx = fpu_resp_val ? fpu_resp_fflags_bits_uop_stq_idx : fdiv_resp_fflags_bits_uop_stq_idx; // @[execution-unit.scala:473:30, :474:29, :498:30, :530:30]
assign _io_fresp_bits_fflags_T_bits_uop_rxq_idx = fpu_resp_val ? fpu_resp_fflags_bits_uop_rxq_idx : fdiv_resp_fflags_bits_uop_rxq_idx; // @[execution-unit.scala:473:30, :474:29, :498:30, :530:30]
assign _io_fresp_bits_fflags_T_bits_uop_pdst = fpu_resp_val ? fpu_resp_fflags_bits_uop_pdst : fdiv_resp_fflags_bits_uop_pdst; // @[execution-unit.scala:473:30, :474:29, :498:30, :530:30]
assign _io_fresp_bits_fflags_T_bits_uop_prs1 = fpu_resp_val ? fpu_resp_fflags_bits_uop_prs1 : fdiv_resp_fflags_bits_uop_prs1; // @[execution-unit.scala:473:30, :474:29, :498:30, :530:30]
assign _io_fresp_bits_fflags_T_bits_uop_prs2 = fpu_resp_val ? fpu_resp_fflags_bits_uop_prs2 : fdiv_resp_fflags_bits_uop_prs2; // @[execution-unit.scala:473:30, :474:29, :498:30, :530:30]
assign _io_fresp_bits_fflags_T_bits_uop_prs3 = fpu_resp_val ? fpu_resp_fflags_bits_uop_prs3 : fdiv_resp_fflags_bits_uop_prs3; // @[execution-unit.scala:473:30, :474:29, :498:30, :530:30]
assign _io_fresp_bits_fflags_T_bits_uop_ppred = fpu_resp_val ? fpu_resp_fflags_bits_uop_ppred : fdiv_resp_fflags_bits_uop_ppred; // @[execution-unit.scala:473:30, :474:29, :498:30, :530:30]
assign _io_fresp_bits_fflags_T_bits_uop_prs1_busy = fpu_resp_val ? fpu_resp_fflags_bits_uop_prs1_busy : fdiv_resp_fflags_bits_uop_prs1_busy; // @[execution-unit.scala:473:30, :474:29, :498:30, :530:30]
assign _io_fresp_bits_fflags_T_bits_uop_prs2_busy = fpu_resp_val ? fpu_resp_fflags_bits_uop_prs2_busy : fdiv_resp_fflags_bits_uop_prs2_busy; // @[execution-unit.scala:473:30, :474:29, :498:30, :530:30]
assign _io_fresp_bits_fflags_T_bits_uop_prs3_busy = fpu_resp_val ? fpu_resp_fflags_bits_uop_prs3_busy : fdiv_resp_fflags_bits_uop_prs3_busy; // @[execution-unit.scala:473:30, :474:29, :498:30, :530:30]
assign _io_fresp_bits_fflags_T_bits_uop_ppred_busy = fpu_resp_val ? fpu_resp_fflags_bits_uop_ppred_busy : fdiv_resp_fflags_bits_uop_ppred_busy; // @[execution-unit.scala:473:30, :474:29, :498:30, :530:30]
assign _io_fresp_bits_fflags_T_bits_uop_stale_pdst = fpu_resp_val ? fpu_resp_fflags_bits_uop_stale_pdst : fdiv_resp_fflags_bits_uop_stale_pdst; // @[execution-unit.scala:473:30, :474:29, :498:30, :530:30]
assign _io_fresp_bits_fflags_T_bits_uop_exception = fpu_resp_val ? fpu_resp_fflags_bits_uop_exception : fdiv_resp_fflags_bits_uop_exception; // @[execution-unit.scala:473:30, :474:29, :498:30, :530:30]
assign _io_fresp_bits_fflags_T_bits_uop_exc_cause = fpu_resp_val ? fpu_resp_fflags_bits_uop_exc_cause : fdiv_resp_fflags_bits_uop_exc_cause; // @[execution-unit.scala:473:30, :474:29, :498:30, :530:30]
assign _io_fresp_bits_fflags_T_bits_uop_bypassable = fpu_resp_val ? fpu_resp_fflags_bits_uop_bypassable : fdiv_resp_fflags_bits_uop_bypassable; // @[execution-unit.scala:473:30, :474:29, :498:30, :530:30]
assign _io_fresp_bits_fflags_T_bits_uop_mem_cmd = fpu_resp_val ? fpu_resp_fflags_bits_uop_mem_cmd : fdiv_resp_fflags_bits_uop_mem_cmd; // @[execution-unit.scala:473:30, :474:29, :498:30, :530:30]
assign _io_fresp_bits_fflags_T_bits_uop_mem_size = fpu_resp_val ? fpu_resp_fflags_bits_uop_mem_size : fdiv_resp_fflags_bits_uop_mem_size; // @[execution-unit.scala:473:30, :474:29, :498:30, :530:30]
assign _io_fresp_bits_fflags_T_bits_uop_mem_signed = fpu_resp_val ? fpu_resp_fflags_bits_uop_mem_signed : fdiv_resp_fflags_bits_uop_mem_signed; // @[execution-unit.scala:473:30, :474:29, :498:30, :530:30]
assign _io_fresp_bits_fflags_T_bits_uop_is_fence = fpu_resp_val ? fpu_resp_fflags_bits_uop_is_fence : fdiv_resp_fflags_bits_uop_is_fence; // @[execution-unit.scala:473:30, :474:29, :498:30, :530:30]
assign _io_fresp_bits_fflags_T_bits_uop_is_fencei = fpu_resp_val ? fpu_resp_fflags_bits_uop_is_fencei : fdiv_resp_fflags_bits_uop_is_fencei; // @[execution-unit.scala:473:30, :474:29, :498:30, :530:30]
assign _io_fresp_bits_fflags_T_bits_uop_is_amo = fpu_resp_val ? fpu_resp_fflags_bits_uop_is_amo : fdiv_resp_fflags_bits_uop_is_amo; // @[execution-unit.scala:473:30, :474:29, :498:30, :530:30]
assign _io_fresp_bits_fflags_T_bits_uop_uses_ldq = fpu_resp_val ? fpu_resp_fflags_bits_uop_uses_ldq : fdiv_resp_fflags_bits_uop_uses_ldq; // @[execution-unit.scala:473:30, :474:29, :498:30, :530:30]
assign _io_fresp_bits_fflags_T_bits_uop_uses_stq = fpu_resp_val ? fpu_resp_fflags_bits_uop_uses_stq : fdiv_resp_fflags_bits_uop_uses_stq; // @[execution-unit.scala:473:30, :474:29, :498:30, :530:30]
assign _io_fresp_bits_fflags_T_bits_uop_is_sys_pc2epc = fpu_resp_val ? fpu_resp_fflags_bits_uop_is_sys_pc2epc : fdiv_resp_fflags_bits_uop_is_sys_pc2epc; // @[execution-unit.scala:473:30, :474:29, :498:30, :530:30]
assign _io_fresp_bits_fflags_T_bits_uop_is_unique = fpu_resp_val ? fpu_resp_fflags_bits_uop_is_unique : fdiv_resp_fflags_bits_uop_is_unique; // @[execution-unit.scala:473:30, :474:29, :498:30, :530:30]
assign _io_fresp_bits_fflags_T_bits_uop_flush_on_commit = fpu_resp_val ? fpu_resp_fflags_bits_uop_flush_on_commit : fdiv_resp_fflags_bits_uop_flush_on_commit; // @[execution-unit.scala:473:30, :474:29, :498:30, :530:30]
assign _io_fresp_bits_fflags_T_bits_uop_ldst_is_rs1 = fpu_resp_val ? fpu_resp_fflags_bits_uop_ldst_is_rs1 : fdiv_resp_fflags_bits_uop_ldst_is_rs1; // @[execution-unit.scala:473:30, :474:29, :498:30, :530:30]
assign _io_fresp_bits_fflags_T_bits_uop_ldst = fpu_resp_val ? fpu_resp_fflags_bits_uop_ldst : fdiv_resp_fflags_bits_uop_ldst; // @[execution-unit.scala:473:30, :474:29, :498:30, :530:30]
assign _io_fresp_bits_fflags_T_bits_uop_lrs1 = fpu_resp_val ? fpu_resp_fflags_bits_uop_lrs1 : fdiv_resp_fflags_bits_uop_lrs1; // @[execution-unit.scala:473:30, :474:29, :498:30, :530:30]
assign _io_fresp_bits_fflags_T_bits_uop_lrs2 = fpu_resp_val ? fpu_resp_fflags_bits_uop_lrs2 : fdiv_resp_fflags_bits_uop_lrs2; // @[execution-unit.scala:473:30, :474:29, :498:30, :530:30]
assign _io_fresp_bits_fflags_T_bits_uop_lrs3 = fpu_resp_val ? fpu_resp_fflags_bits_uop_lrs3 : fdiv_resp_fflags_bits_uop_lrs3; // @[execution-unit.scala:473:30, :474:29, :498:30, :530:30]
assign _io_fresp_bits_fflags_T_bits_uop_ldst_val = fpu_resp_val ? fpu_resp_fflags_bits_uop_ldst_val : fdiv_resp_fflags_bits_uop_ldst_val; // @[execution-unit.scala:473:30, :474:29, :498:30, :530:30]
assign _io_fresp_bits_fflags_T_bits_uop_dst_rtype = fpu_resp_val ? fpu_resp_fflags_bits_uop_dst_rtype : fdiv_resp_fflags_bits_uop_dst_rtype; // @[execution-unit.scala:473:30, :474:29, :498:30, :530:30]
assign _io_fresp_bits_fflags_T_bits_uop_lrs1_rtype = fpu_resp_val ? fpu_resp_fflags_bits_uop_lrs1_rtype : fdiv_resp_fflags_bits_uop_lrs1_rtype; // @[execution-unit.scala:473:30, :474:29, :498:30, :530:30]
assign _io_fresp_bits_fflags_T_bits_uop_lrs2_rtype = fpu_resp_val ? fpu_resp_fflags_bits_uop_lrs2_rtype : fdiv_resp_fflags_bits_uop_lrs2_rtype; // @[execution-unit.scala:473:30, :474:29, :498:30, :530:30]
assign _io_fresp_bits_fflags_T_bits_uop_frs3_en = fpu_resp_val ? fpu_resp_fflags_bits_uop_frs3_en : fdiv_resp_fflags_bits_uop_frs3_en; // @[execution-unit.scala:473:30, :474:29, :498:30, :530:30]
assign _io_fresp_bits_fflags_T_bits_uop_fp_val = fpu_resp_val ? fpu_resp_fflags_bits_uop_fp_val : fdiv_resp_fflags_bits_uop_fp_val; // @[execution-unit.scala:473:30, :474:29, :498:30, :530:30]
assign _io_fresp_bits_fflags_T_bits_uop_fp_single = fpu_resp_val ? fpu_resp_fflags_bits_uop_fp_single : fdiv_resp_fflags_bits_uop_fp_single; // @[execution-unit.scala:473:30, :474:29, :498:30, :530:30]
assign _io_fresp_bits_fflags_T_bits_uop_xcpt_pf_if = fpu_resp_val ? fpu_resp_fflags_bits_uop_xcpt_pf_if : fdiv_resp_fflags_bits_uop_xcpt_pf_if; // @[execution-unit.scala:473:30, :474:29, :498:30, :530:30]
assign _io_fresp_bits_fflags_T_bits_uop_xcpt_ae_if = fpu_resp_val ? fpu_resp_fflags_bits_uop_xcpt_ae_if : fdiv_resp_fflags_bits_uop_xcpt_ae_if; // @[execution-unit.scala:473:30, :474:29, :498:30, :530:30]
assign _io_fresp_bits_fflags_T_bits_uop_xcpt_ma_if = fpu_resp_val ? fpu_resp_fflags_bits_uop_xcpt_ma_if : fdiv_resp_fflags_bits_uop_xcpt_ma_if; // @[execution-unit.scala:473:30, :474:29, :498:30, :530:30]
assign _io_fresp_bits_fflags_T_bits_uop_bp_debug_if = fpu_resp_val ? fpu_resp_fflags_bits_uop_bp_debug_if : fdiv_resp_fflags_bits_uop_bp_debug_if; // @[execution-unit.scala:473:30, :474:29, :498:30, :530:30]
assign _io_fresp_bits_fflags_T_bits_uop_bp_xcpt_if = fpu_resp_val ? fpu_resp_fflags_bits_uop_bp_xcpt_if : fdiv_resp_fflags_bits_uop_bp_xcpt_if; // @[execution-unit.scala:473:30, :474:29, :498:30, :530:30]
assign _io_fresp_bits_fflags_T_bits_uop_debug_fsrc = fpu_resp_val ? fpu_resp_fflags_bits_uop_debug_fsrc : fdiv_resp_fflags_bits_uop_debug_fsrc; // @[execution-unit.scala:473:30, :474:29, :498:30, :530:30]
assign _io_fresp_bits_fflags_T_bits_uop_debug_tsrc = fpu_resp_val ? fpu_resp_fflags_bits_uop_debug_tsrc : fdiv_resp_fflags_bits_uop_debug_tsrc; // @[execution-unit.scala:473:30, :474:29, :498:30, :530:30]
assign _io_fresp_bits_fflags_T_bits_flags = fpu_resp_val ? fpu_resp_fflags_bits_flags : fdiv_resp_fflags_bits_flags; // @[execution-unit.scala:473:30, :474:29, :498:30, :530:30]
assign io_fresp_bits_fflags_valid_0 = _io_fresp_bits_fflags_T_valid; // @[execution-unit.scala:437:7, :530:30]
assign io_fresp_bits_fflags_bits_uop_uopc_0 = _io_fresp_bits_fflags_T_bits_uop_uopc; // @[execution-unit.scala:437:7, :530:30]
assign io_fresp_bits_fflags_bits_uop_inst_0 = _io_fresp_bits_fflags_T_bits_uop_inst; // @[execution-unit.scala:437:7, :530:30]
assign io_fresp_bits_fflags_bits_uop_debug_inst_0 = _io_fresp_bits_fflags_T_bits_uop_debug_inst; // @[execution-unit.scala:437:7, :530:30]
assign io_fresp_bits_fflags_bits_uop_is_rvc_0 = _io_fresp_bits_fflags_T_bits_uop_is_rvc; // @[execution-unit.scala:437:7, :530:30]
assign io_fresp_bits_fflags_bits_uop_debug_pc_0 = _io_fresp_bits_fflags_T_bits_uop_debug_pc; // @[execution-unit.scala:437:7, :530:30]
assign io_fresp_bits_fflags_bits_uop_iq_type_0 = _io_fresp_bits_fflags_T_bits_uop_iq_type; // @[execution-unit.scala:437:7, :530:30]
assign io_fresp_bits_fflags_bits_uop_fu_code_0 = _io_fresp_bits_fflags_T_bits_uop_fu_code; // @[execution-unit.scala:437:7, :530:30]
assign io_fresp_bits_fflags_bits_uop_ctrl_br_type_0 = _io_fresp_bits_fflags_T_bits_uop_ctrl_br_type; // @[execution-unit.scala:437:7, :530:30]
assign io_fresp_bits_fflags_bits_uop_ctrl_op1_sel_0 = _io_fresp_bits_fflags_T_bits_uop_ctrl_op1_sel; // @[execution-unit.scala:437:7, :530:30]
assign io_fresp_bits_fflags_bits_uop_ctrl_op2_sel_0 = _io_fresp_bits_fflags_T_bits_uop_ctrl_op2_sel; // @[execution-unit.scala:437:7, :530:30]
assign io_fresp_bits_fflags_bits_uop_ctrl_imm_sel_0 = _io_fresp_bits_fflags_T_bits_uop_ctrl_imm_sel; // @[execution-unit.scala:437:7, :530:30]
assign io_fresp_bits_fflags_bits_uop_ctrl_op_fcn_0 = _io_fresp_bits_fflags_T_bits_uop_ctrl_op_fcn; // @[execution-unit.scala:437:7, :530:30]
assign io_fresp_bits_fflags_bits_uop_ctrl_fcn_dw_0 = _io_fresp_bits_fflags_T_bits_uop_ctrl_fcn_dw; // @[execution-unit.scala:437:7, :530:30]
assign io_fresp_bits_fflags_bits_uop_ctrl_csr_cmd_0 = _io_fresp_bits_fflags_T_bits_uop_ctrl_csr_cmd; // @[execution-unit.scala:437:7, :530:30]
assign io_fresp_bits_fflags_bits_uop_ctrl_is_load_0 = _io_fresp_bits_fflags_T_bits_uop_ctrl_is_load; // @[execution-unit.scala:437:7, :530:30]
assign io_fresp_bits_fflags_bits_uop_ctrl_is_sta_0 = _io_fresp_bits_fflags_T_bits_uop_ctrl_is_sta; // @[execution-unit.scala:437:7, :530:30]
assign io_fresp_bits_fflags_bits_uop_ctrl_is_std_0 = _io_fresp_bits_fflags_T_bits_uop_ctrl_is_std; // @[execution-unit.scala:437:7, :530:30]
assign io_fresp_bits_fflags_bits_uop_iw_state_0 = _io_fresp_bits_fflags_T_bits_uop_iw_state; // @[execution-unit.scala:437:7, :530:30]
assign io_fresp_bits_fflags_bits_uop_iw_p1_poisoned_0 = _io_fresp_bits_fflags_T_bits_uop_iw_p1_poisoned; // @[execution-unit.scala:437:7, :530:30]
assign io_fresp_bits_fflags_bits_uop_iw_p2_poisoned_0 = _io_fresp_bits_fflags_T_bits_uop_iw_p2_poisoned; // @[execution-unit.scala:437:7, :530:30]
assign io_fresp_bits_fflags_bits_uop_is_br_0 = _io_fresp_bits_fflags_T_bits_uop_is_br; // @[execution-unit.scala:437:7, :530:30]
assign io_fresp_bits_fflags_bits_uop_is_jalr_0 = _io_fresp_bits_fflags_T_bits_uop_is_jalr; // @[execution-unit.scala:437:7, :530:30]
assign io_fresp_bits_fflags_bits_uop_is_jal_0 = _io_fresp_bits_fflags_T_bits_uop_is_jal; // @[execution-unit.scala:437:7, :530:30]
assign io_fresp_bits_fflags_bits_uop_is_sfb_0 = _io_fresp_bits_fflags_T_bits_uop_is_sfb; // @[execution-unit.scala:437:7, :530:30]
assign io_fresp_bits_fflags_bits_uop_br_mask_0 = _io_fresp_bits_fflags_T_bits_uop_br_mask; // @[execution-unit.scala:437:7, :530:30]
assign io_fresp_bits_fflags_bits_uop_br_tag_0 = _io_fresp_bits_fflags_T_bits_uop_br_tag; // @[execution-unit.scala:437:7, :530:30]
assign io_fresp_bits_fflags_bits_uop_ftq_idx_0 = _io_fresp_bits_fflags_T_bits_uop_ftq_idx; // @[execution-unit.scala:437:7, :530:30]
assign io_fresp_bits_fflags_bits_uop_edge_inst_0 = _io_fresp_bits_fflags_T_bits_uop_edge_inst; // @[execution-unit.scala:437:7, :530:30]
assign io_fresp_bits_fflags_bits_uop_pc_lob_0 = _io_fresp_bits_fflags_T_bits_uop_pc_lob; // @[execution-unit.scala:437:7, :530:30]
assign io_fresp_bits_fflags_bits_uop_taken_0 = _io_fresp_bits_fflags_T_bits_uop_taken; // @[execution-unit.scala:437:7, :530:30]
assign io_fresp_bits_fflags_bits_uop_imm_packed_0 = _io_fresp_bits_fflags_T_bits_uop_imm_packed; // @[execution-unit.scala:437:7, :530:30]
assign io_fresp_bits_fflags_bits_uop_csr_addr_0 = _io_fresp_bits_fflags_T_bits_uop_csr_addr; // @[execution-unit.scala:437:7, :530:30]
assign io_fresp_bits_fflags_bits_uop_rob_idx_0 = _io_fresp_bits_fflags_T_bits_uop_rob_idx; // @[execution-unit.scala:437:7, :530:30]
assign io_fresp_bits_fflags_bits_uop_ldq_idx_0 = _io_fresp_bits_fflags_T_bits_uop_ldq_idx; // @[execution-unit.scala:437:7, :530:30]
assign io_fresp_bits_fflags_bits_uop_stq_idx_0 = _io_fresp_bits_fflags_T_bits_uop_stq_idx; // @[execution-unit.scala:437:7, :530:30]
assign io_fresp_bits_fflags_bits_uop_rxq_idx_0 = _io_fresp_bits_fflags_T_bits_uop_rxq_idx; // @[execution-unit.scala:437:7, :530:30]
assign io_fresp_bits_fflags_bits_uop_pdst_0 = _io_fresp_bits_fflags_T_bits_uop_pdst; // @[execution-unit.scala:437:7, :530:30]
assign io_fresp_bits_fflags_bits_uop_prs1_0 = _io_fresp_bits_fflags_T_bits_uop_prs1; // @[execution-unit.scala:437:7, :530:30]
assign io_fresp_bits_fflags_bits_uop_prs2_0 = _io_fresp_bits_fflags_T_bits_uop_prs2; // @[execution-unit.scala:437:7, :530:30]
assign io_fresp_bits_fflags_bits_uop_prs3_0 = _io_fresp_bits_fflags_T_bits_uop_prs3; // @[execution-unit.scala:437:7, :530:30]
assign io_fresp_bits_fflags_bits_uop_ppred_0 = _io_fresp_bits_fflags_T_bits_uop_ppred; // @[execution-unit.scala:437:7, :530:30]
assign io_fresp_bits_fflags_bits_uop_prs1_busy_0 = _io_fresp_bits_fflags_T_bits_uop_prs1_busy; // @[execution-unit.scala:437:7, :530:30]
assign io_fresp_bits_fflags_bits_uop_prs2_busy_0 = _io_fresp_bits_fflags_T_bits_uop_prs2_busy; // @[execution-unit.scala:437:7, :530:30]
assign io_fresp_bits_fflags_bits_uop_prs3_busy_0 = _io_fresp_bits_fflags_T_bits_uop_prs3_busy; // @[execution-unit.scala:437:7, :530:30]
assign io_fresp_bits_fflags_bits_uop_ppred_busy_0 = _io_fresp_bits_fflags_T_bits_uop_ppred_busy; // @[execution-unit.scala:437:7, :530:30]
assign io_fresp_bits_fflags_bits_uop_stale_pdst_0 = _io_fresp_bits_fflags_T_bits_uop_stale_pdst; // @[execution-unit.scala:437:7, :530:30]
assign io_fresp_bits_fflags_bits_uop_exception_0 = _io_fresp_bits_fflags_T_bits_uop_exception; // @[execution-unit.scala:437:7, :530:30]
assign io_fresp_bits_fflags_bits_uop_exc_cause_0 = _io_fresp_bits_fflags_T_bits_uop_exc_cause; // @[execution-unit.scala:437:7, :530:30]
assign io_fresp_bits_fflags_bits_uop_bypassable_0 = _io_fresp_bits_fflags_T_bits_uop_bypassable; // @[execution-unit.scala:437:7, :530:30]
assign io_fresp_bits_fflags_bits_uop_mem_cmd_0 = _io_fresp_bits_fflags_T_bits_uop_mem_cmd; // @[execution-unit.scala:437:7, :530:30]
assign io_fresp_bits_fflags_bits_uop_mem_size_0 = _io_fresp_bits_fflags_T_bits_uop_mem_size; // @[execution-unit.scala:437:7, :530:30]
assign io_fresp_bits_fflags_bits_uop_mem_signed_0 = _io_fresp_bits_fflags_T_bits_uop_mem_signed; // @[execution-unit.scala:437:7, :530:30]
assign io_fresp_bits_fflags_bits_uop_is_fence_0 = _io_fresp_bits_fflags_T_bits_uop_is_fence; // @[execution-unit.scala:437:7, :530:30]
assign io_fresp_bits_fflags_bits_uop_is_fencei_0 = _io_fresp_bits_fflags_T_bits_uop_is_fencei; // @[execution-unit.scala:437:7, :530:30]
assign io_fresp_bits_fflags_bits_uop_is_amo_0 = _io_fresp_bits_fflags_T_bits_uop_is_amo; // @[execution-unit.scala:437:7, :530:30]
assign io_fresp_bits_fflags_bits_uop_uses_ldq_0 = _io_fresp_bits_fflags_T_bits_uop_uses_ldq; // @[execution-unit.scala:437:7, :530:30]
assign io_fresp_bits_fflags_bits_uop_uses_stq_0 = _io_fresp_bits_fflags_T_bits_uop_uses_stq; // @[execution-unit.scala:437:7, :530:30]
assign io_fresp_bits_fflags_bits_uop_is_sys_pc2epc_0 = _io_fresp_bits_fflags_T_bits_uop_is_sys_pc2epc; // @[execution-unit.scala:437:7, :530:30]
assign io_fresp_bits_fflags_bits_uop_is_unique_0 = _io_fresp_bits_fflags_T_bits_uop_is_unique; // @[execution-unit.scala:437:7, :530:30]
assign io_fresp_bits_fflags_bits_uop_flush_on_commit_0 = _io_fresp_bits_fflags_T_bits_uop_flush_on_commit; // @[execution-unit.scala:437:7, :530:30]
assign io_fresp_bits_fflags_bits_uop_ldst_is_rs1_0 = _io_fresp_bits_fflags_T_bits_uop_ldst_is_rs1; // @[execution-unit.scala:437:7, :530:30]
assign io_fresp_bits_fflags_bits_uop_ldst_0 = _io_fresp_bits_fflags_T_bits_uop_ldst; // @[execution-unit.scala:437:7, :530:30]
assign io_fresp_bits_fflags_bits_uop_lrs1_0 = _io_fresp_bits_fflags_T_bits_uop_lrs1; // @[execution-unit.scala:437:7, :530:30]
assign io_fresp_bits_fflags_bits_uop_lrs2_0 = _io_fresp_bits_fflags_T_bits_uop_lrs2; // @[execution-unit.scala:437:7, :530:30]
assign io_fresp_bits_fflags_bits_uop_lrs3_0 = _io_fresp_bits_fflags_T_bits_uop_lrs3; // @[execution-unit.scala:437:7, :530:30]
assign io_fresp_bits_fflags_bits_uop_ldst_val_0 = _io_fresp_bits_fflags_T_bits_uop_ldst_val; // @[execution-unit.scala:437:7, :530:30]
assign io_fresp_bits_fflags_bits_uop_dst_rtype_0 = _io_fresp_bits_fflags_T_bits_uop_dst_rtype; // @[execution-unit.scala:437:7, :530:30]
assign io_fresp_bits_fflags_bits_uop_lrs1_rtype_0 = _io_fresp_bits_fflags_T_bits_uop_lrs1_rtype; // @[execution-unit.scala:437:7, :530:30]
assign io_fresp_bits_fflags_bits_uop_lrs2_rtype_0 = _io_fresp_bits_fflags_T_bits_uop_lrs2_rtype; // @[execution-unit.scala:437:7, :530:30]
assign io_fresp_bits_fflags_bits_uop_frs3_en_0 = _io_fresp_bits_fflags_T_bits_uop_frs3_en; // @[execution-unit.scala:437:7, :530:30]
assign io_fresp_bits_fflags_bits_uop_fp_val_0 = _io_fresp_bits_fflags_T_bits_uop_fp_val; // @[execution-unit.scala:437:7, :530:30]
assign io_fresp_bits_fflags_bits_uop_fp_single_0 = _io_fresp_bits_fflags_T_bits_uop_fp_single; // @[execution-unit.scala:437:7, :530:30]
assign io_fresp_bits_fflags_bits_uop_xcpt_pf_if_0 = _io_fresp_bits_fflags_T_bits_uop_xcpt_pf_if; // @[execution-unit.scala:437:7, :530:30]
assign io_fresp_bits_fflags_bits_uop_xcpt_ae_if_0 = _io_fresp_bits_fflags_T_bits_uop_xcpt_ae_if; // @[execution-unit.scala:437:7, :530:30]
assign io_fresp_bits_fflags_bits_uop_xcpt_ma_if_0 = _io_fresp_bits_fflags_T_bits_uop_xcpt_ma_if; // @[execution-unit.scala:437:7, :530:30]
assign io_fresp_bits_fflags_bits_uop_bp_debug_if_0 = _io_fresp_bits_fflags_T_bits_uop_bp_debug_if; // @[execution-unit.scala:437:7, :530:30]
assign io_fresp_bits_fflags_bits_uop_bp_xcpt_if_0 = _io_fresp_bits_fflags_T_bits_uop_bp_xcpt_if; // @[execution-unit.scala:437:7, :530:30]
assign io_fresp_bits_fflags_bits_uop_debug_fsrc_0 = _io_fresp_bits_fflags_T_bits_uop_debug_fsrc; // @[execution-unit.scala:437:7, :530:30]
assign io_fresp_bits_fflags_bits_uop_debug_tsrc_0 = _io_fresp_bits_fflags_T_bits_uop_debug_tsrc; // @[execution-unit.scala:437:7, :530:30]
assign io_fresp_bits_fflags_bits_flags_0 = _io_fresp_bits_fflags_T_bits_flags; // @[execution-unit.scala:437:7, :530:30]
wire _queue_io_enq_valid_T_1 = |_queue_io_enq_valid_T; // @[micro-op.scala:154:{40,47}]
wire _queue_io_enq_valid_T_2 = _FPUUnit_io_resp_valid & _queue_io_enq_valid_T_1; // @[execution-unit.scala:477:17, :539:52]
wire _queue_io_enq_valid_T_3 = _FPUUnit_io_resp_bits_uop_uopc != 7'h2; // @[execution-unit.scala:477:17, :541:60]
wire _queue_io_enq_valid_T_4 = _queue_io_enq_valid_T_2 & _queue_io_enq_valid_T_3; // @[execution-unit.scala:539:52, :540:74, :541:60]
wire _fp_sdq_io_enq_valid_T = io_req_bits_uop_uopc_0 == 7'h2; // @[execution-unit.scala:437:7, :553:70]
wire _fp_sdq_io_enq_valid_T_1 = io_req_valid_0 & _fp_sdq_io_enq_valid_T; // @[execution-unit.scala:437:7, :553:{46,70}]
wire [15:0] _fp_sdq_io_enq_valid_T_2 = io_brupdate_b1_mispredict_mask_0 & io_req_bits_uop_br_mask_0; // @[util.scala:118:51]
wire _fp_sdq_io_enq_valid_T_3 = |_fp_sdq_io_enq_valid_T_2; // @[util.scala:118:{51,59}]
wire _fp_sdq_io_enq_valid_T_4 = ~_fp_sdq_io_enq_valid_T_3; // @[util.scala:118:59]
wire _fp_sdq_io_enq_valid_T_5 = _fp_sdq_io_enq_valid_T_1 & _fp_sdq_io_enq_valid_T_4; // @[execution-unit.scala:553:{46,81,84}]
wire [11:0] fp_sdq_io_enq_bits_data_unrecoded_rawIn_exp = io_req_bits_rs2_data_0[63:52]; // @[rawFloatFromRecFN.scala:51:21]
wire [2:0] _fp_sdq_io_enq_bits_data_unrecoded_rawIn_isZero_T = fp_sdq_io_enq_bits_data_unrecoded_rawIn_exp[11:9]; // @[rawFloatFromRecFN.scala:51:21, :52:28]
wire fp_sdq_io_enq_bits_data_unrecoded_rawIn_isZero = _fp_sdq_io_enq_bits_data_unrecoded_rawIn_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}]
wire fp_sdq_io_enq_bits_data_unrecoded_rawIn_isZero_0 = fp_sdq_io_enq_bits_data_unrecoded_rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23]
wire [1:0] _fp_sdq_io_enq_bits_data_unrecoded_rawIn_isSpecial_T = fp_sdq_io_enq_bits_data_unrecoded_rawIn_exp[11:10]; // @[rawFloatFromRecFN.scala:51:21, :53:28]
wire fp_sdq_io_enq_bits_data_unrecoded_rawIn_isSpecial = &_fp_sdq_io_enq_bits_data_unrecoded_rawIn_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}]
wire _fp_sdq_io_enq_bits_data_unrecoded_rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33]
wire _fp_sdq_io_enq_bits_data_unrecoded_rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33]
wire _fp_sdq_io_enq_bits_data_unrecoded_rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:59:25]
wire [12:0] _fp_sdq_io_enq_bits_data_unrecoded_rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27]
wire [53:0] _fp_sdq_io_enq_bits_data_unrecoded_rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44]
wire fp_sdq_io_enq_bits_data_unrecoded_rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23]
wire fp_sdq_io_enq_bits_data_unrecoded_rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire fp_sdq_io_enq_bits_data_unrecoded_rawIn_sign; // @[rawFloatFromRecFN.scala:55:23]
wire [12:0] fp_sdq_io_enq_bits_data_unrecoded_rawIn_sExp; // @[rawFloatFromRecFN.scala:55:23]
wire [53:0] fp_sdq_io_enq_bits_data_unrecoded_rawIn_sig; // @[rawFloatFromRecFN.scala:55:23]
wire _fp_sdq_io_enq_bits_data_unrecoded_rawIn_out_isNaN_T = fp_sdq_io_enq_bits_data_unrecoded_rawIn_exp[9]; // @[rawFloatFromRecFN.scala:51:21, :56:41]
wire _fp_sdq_io_enq_bits_data_unrecoded_rawIn_out_isInf_T = fp_sdq_io_enq_bits_data_unrecoded_rawIn_exp[9]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41]
assign _fp_sdq_io_enq_bits_data_unrecoded_rawIn_out_isNaN_T_1 = fp_sdq_io_enq_bits_data_unrecoded_rawIn_isSpecial & _fp_sdq_io_enq_bits_data_unrecoded_rawIn_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}]
assign fp_sdq_io_enq_bits_data_unrecoded_rawIn_isNaN = _fp_sdq_io_enq_bits_data_unrecoded_rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33]
wire _fp_sdq_io_enq_bits_data_unrecoded_rawIn_out_isInf_T_1 = ~_fp_sdq_io_enq_bits_data_unrecoded_rawIn_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}]
assign _fp_sdq_io_enq_bits_data_unrecoded_rawIn_out_isInf_T_2 = fp_sdq_io_enq_bits_data_unrecoded_rawIn_isSpecial & _fp_sdq_io_enq_bits_data_unrecoded_rawIn_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}]
assign fp_sdq_io_enq_bits_data_unrecoded_rawIn_isInf = _fp_sdq_io_enq_bits_data_unrecoded_rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33]
assign _fp_sdq_io_enq_bits_data_unrecoded_rawIn_out_sign_T = io_req_bits_rs2_data_0[64]; // @[rawFloatFromRecFN.scala:59:25]
assign fp_sdq_io_enq_bits_data_unrecoded_rawIn_sign = _fp_sdq_io_enq_bits_data_unrecoded_rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25]
assign _fp_sdq_io_enq_bits_data_unrecoded_rawIn_out_sExp_T = {1'h0, fp_sdq_io_enq_bits_data_unrecoded_rawIn_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27]
assign fp_sdq_io_enq_bits_data_unrecoded_rawIn_sExp = _fp_sdq_io_enq_bits_data_unrecoded_rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire _fp_sdq_io_enq_bits_data_unrecoded_rawIn_out_sig_T = ~fp_sdq_io_enq_bits_data_unrecoded_rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35]
wire [1:0] _fp_sdq_io_enq_bits_data_unrecoded_rawIn_out_sig_T_1 = {1'h0, _fp_sdq_io_enq_bits_data_unrecoded_rawIn_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}]
wire [51:0] _fp_sdq_io_enq_bits_data_unrecoded_rawIn_out_sig_T_2 = io_req_bits_rs2_data_0[51:0]; // @[rawFloatFromRecFN.scala:61:49]
assign _fp_sdq_io_enq_bits_data_unrecoded_rawIn_out_sig_T_3 = {_fp_sdq_io_enq_bits_data_unrecoded_rawIn_out_sig_T_1, _fp_sdq_io_enq_bits_data_unrecoded_rawIn_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}]
assign fp_sdq_io_enq_bits_data_unrecoded_rawIn_sig = _fp_sdq_io_enq_bits_data_unrecoded_rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44]
wire fp_sdq_io_enq_bits_data_unrecoded_isSubnormal = $signed(fp_sdq_io_enq_bits_data_unrecoded_rawIn_sExp) < 13'sh402; // @[rawFloatFromRecFN.scala:55:23]
wire [5:0] _fp_sdq_io_enq_bits_data_unrecoded_denormShiftDist_T = fp_sdq_io_enq_bits_data_unrecoded_rawIn_sExp[5:0]; // @[rawFloatFromRecFN.scala:55:23]
wire [6:0] _fp_sdq_io_enq_bits_data_unrecoded_denormShiftDist_T_1 = 7'h1 - {1'h0, _fp_sdq_io_enq_bits_data_unrecoded_denormShiftDist_T}; // @[fNFromRecFN.scala:52:{35,47}]
wire [5:0] fp_sdq_io_enq_bits_data_unrecoded_denormShiftDist = _fp_sdq_io_enq_bits_data_unrecoded_denormShiftDist_T_1[5:0]; // @[fNFromRecFN.scala:52:35]
wire [52:0] _fp_sdq_io_enq_bits_data_unrecoded_denormFract_T = fp_sdq_io_enq_bits_data_unrecoded_rawIn_sig[53:1]; // @[rawFloatFromRecFN.scala:55:23]
wire [52:0] _fp_sdq_io_enq_bits_data_unrecoded_denormFract_T_1 = _fp_sdq_io_enq_bits_data_unrecoded_denormFract_T >> fp_sdq_io_enq_bits_data_unrecoded_denormShiftDist; // @[fNFromRecFN.scala:52:35, :53:{38,42}]
wire [51:0] fp_sdq_io_enq_bits_data_unrecoded_denormFract = _fp_sdq_io_enq_bits_data_unrecoded_denormFract_T_1[51:0]; // @[fNFromRecFN.scala:53:{42,60}]
wire [10:0] _fp_sdq_io_enq_bits_data_unrecoded_expOut_T = fp_sdq_io_enq_bits_data_unrecoded_rawIn_sExp[10:0]; // @[rawFloatFromRecFN.scala:55:23]
wire [11:0] _fp_sdq_io_enq_bits_data_unrecoded_expOut_T_1 = {1'h0, _fp_sdq_io_enq_bits_data_unrecoded_expOut_T} - 12'h401; // @[fNFromRecFN.scala:58:{27,45}]
wire [10:0] _fp_sdq_io_enq_bits_data_unrecoded_expOut_T_2 = _fp_sdq_io_enq_bits_data_unrecoded_expOut_T_1[10:0]; // @[fNFromRecFN.scala:58:45]
wire [10:0] _fp_sdq_io_enq_bits_data_unrecoded_expOut_T_3 = fp_sdq_io_enq_bits_data_unrecoded_isSubnormal ? 11'h0 : _fp_sdq_io_enq_bits_data_unrecoded_expOut_T_2; // @[fNFromRecFN.scala:51:38, :56:16, :58:45]
wire _fp_sdq_io_enq_bits_data_unrecoded_expOut_T_4 = fp_sdq_io_enq_bits_data_unrecoded_rawIn_isNaN | fp_sdq_io_enq_bits_data_unrecoded_rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire [10:0] _fp_sdq_io_enq_bits_data_unrecoded_expOut_T_5 = {11{_fp_sdq_io_enq_bits_data_unrecoded_expOut_T_4}}; // @[fNFromRecFN.scala:60:{21,44}]
wire [10:0] fp_sdq_io_enq_bits_data_unrecoded_expOut = _fp_sdq_io_enq_bits_data_unrecoded_expOut_T_3 | _fp_sdq_io_enq_bits_data_unrecoded_expOut_T_5; // @[fNFromRecFN.scala:56:16, :60:{15,21}]
wire [51:0] _fp_sdq_io_enq_bits_data_unrecoded_fractOut_T = fp_sdq_io_enq_bits_data_unrecoded_rawIn_sig[51:0]; // @[rawFloatFromRecFN.scala:55:23]
wire [51:0] _fp_sdq_io_enq_bits_data_unrecoded_fractOut_T_1 = fp_sdq_io_enq_bits_data_unrecoded_rawIn_isInf ? 52'h0 : _fp_sdq_io_enq_bits_data_unrecoded_fractOut_T; // @[rawFloatFromRecFN.scala:55:23]
wire [51:0] fp_sdq_io_enq_bits_data_unrecoded_fractOut = fp_sdq_io_enq_bits_data_unrecoded_isSubnormal ? fp_sdq_io_enq_bits_data_unrecoded_denormFract : _fp_sdq_io_enq_bits_data_unrecoded_fractOut_T_1; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20]
wire [11:0] fp_sdq_io_enq_bits_data_unrecoded_hi = {fp_sdq_io_enq_bits_data_unrecoded_rawIn_sign, fp_sdq_io_enq_bits_data_unrecoded_expOut}; // @[rawFloatFromRecFN.scala:55:23]
wire [63:0] fp_sdq_io_enq_bits_data_unrecoded = {fp_sdq_io_enq_bits_data_unrecoded_hi, fp_sdq_io_enq_bits_data_unrecoded_fractOut}; // @[fNFromRecFN.scala:62:16, :66:12]
wire _fp_sdq_io_enq_bits_data_prevRecoded_T = io_req_bits_rs2_data_0[31]; // @[FPU.scala:442:10]
wire _fp_sdq_io_enq_bits_data_prevRecoded_T_1 = io_req_bits_rs2_data_0[52]; // @[FPU.scala:443:10]
wire [30:0] _fp_sdq_io_enq_bits_data_prevRecoded_T_2 = io_req_bits_rs2_data_0[30:0]; // @[FPU.scala:444:10]
wire [1:0] fp_sdq_io_enq_bits_data_prevRecoded_hi = {_fp_sdq_io_enq_bits_data_prevRecoded_T, _fp_sdq_io_enq_bits_data_prevRecoded_T_1}; // @[FPU.scala:441:28, :442:10, :443:10]
wire [32:0] fp_sdq_io_enq_bits_data_prevRecoded = {fp_sdq_io_enq_bits_data_prevRecoded_hi, _fp_sdq_io_enq_bits_data_prevRecoded_T_2}; // @[FPU.scala:441:28, :444:10]
wire [8:0] fp_sdq_io_enq_bits_data_prevUnrecoded_rawIn_exp = fp_sdq_io_enq_bits_data_prevRecoded[31:23]; // @[FPU.scala:441:28]
wire [2:0] _fp_sdq_io_enq_bits_data_prevUnrecoded_rawIn_isZero_T = fp_sdq_io_enq_bits_data_prevUnrecoded_rawIn_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28]
wire fp_sdq_io_enq_bits_data_prevUnrecoded_rawIn_isZero = _fp_sdq_io_enq_bits_data_prevUnrecoded_rawIn_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}]
wire fp_sdq_io_enq_bits_data_prevUnrecoded_rawIn_isZero_0 = fp_sdq_io_enq_bits_data_prevUnrecoded_rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23]
wire [1:0] _fp_sdq_io_enq_bits_data_prevUnrecoded_rawIn_isSpecial_T = fp_sdq_io_enq_bits_data_prevUnrecoded_rawIn_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28]
wire fp_sdq_io_enq_bits_data_prevUnrecoded_rawIn_isSpecial = &_fp_sdq_io_enq_bits_data_prevUnrecoded_rawIn_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}]
wire _fp_sdq_io_enq_bits_data_prevUnrecoded_rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33]
wire _fp_sdq_io_enq_bits_data_prevUnrecoded_rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33]
wire _fp_sdq_io_enq_bits_data_prevUnrecoded_rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:59:25]
wire [9:0] _fp_sdq_io_enq_bits_data_prevUnrecoded_rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27]
wire [24:0] _fp_sdq_io_enq_bits_data_prevUnrecoded_rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44]
wire fp_sdq_io_enq_bits_data_prevUnrecoded_rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23]
wire fp_sdq_io_enq_bits_data_prevUnrecoded_rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire fp_sdq_io_enq_bits_data_prevUnrecoded_rawIn_sign; // @[rawFloatFromRecFN.scala:55:23]
wire [9:0] fp_sdq_io_enq_bits_data_prevUnrecoded_rawIn_sExp; // @[rawFloatFromRecFN.scala:55:23]
wire [24:0] fp_sdq_io_enq_bits_data_prevUnrecoded_rawIn_sig; // @[rawFloatFromRecFN.scala:55:23]
wire _fp_sdq_io_enq_bits_data_prevUnrecoded_rawIn_out_isNaN_T = fp_sdq_io_enq_bits_data_prevUnrecoded_rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41]
wire _fp_sdq_io_enq_bits_data_prevUnrecoded_rawIn_out_isInf_T = fp_sdq_io_enq_bits_data_prevUnrecoded_rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41]
assign _fp_sdq_io_enq_bits_data_prevUnrecoded_rawIn_out_isNaN_T_1 = fp_sdq_io_enq_bits_data_prevUnrecoded_rawIn_isSpecial & _fp_sdq_io_enq_bits_data_prevUnrecoded_rawIn_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}]
assign fp_sdq_io_enq_bits_data_prevUnrecoded_rawIn_isNaN = _fp_sdq_io_enq_bits_data_prevUnrecoded_rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33]
wire _fp_sdq_io_enq_bits_data_prevUnrecoded_rawIn_out_isInf_T_1 = ~_fp_sdq_io_enq_bits_data_prevUnrecoded_rawIn_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}]
assign _fp_sdq_io_enq_bits_data_prevUnrecoded_rawIn_out_isInf_T_2 = fp_sdq_io_enq_bits_data_prevUnrecoded_rawIn_isSpecial & _fp_sdq_io_enq_bits_data_prevUnrecoded_rawIn_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}]
assign fp_sdq_io_enq_bits_data_prevUnrecoded_rawIn_isInf = _fp_sdq_io_enq_bits_data_prevUnrecoded_rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33]
assign _fp_sdq_io_enq_bits_data_prevUnrecoded_rawIn_out_sign_T = fp_sdq_io_enq_bits_data_prevRecoded[32]; // @[FPU.scala:441:28]
assign fp_sdq_io_enq_bits_data_prevUnrecoded_rawIn_sign = _fp_sdq_io_enq_bits_data_prevUnrecoded_rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25]
assign _fp_sdq_io_enq_bits_data_prevUnrecoded_rawIn_out_sExp_T = {1'h0, fp_sdq_io_enq_bits_data_prevUnrecoded_rawIn_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27]
assign fp_sdq_io_enq_bits_data_prevUnrecoded_rawIn_sExp = _fp_sdq_io_enq_bits_data_prevUnrecoded_rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire _fp_sdq_io_enq_bits_data_prevUnrecoded_rawIn_out_sig_T = ~fp_sdq_io_enq_bits_data_prevUnrecoded_rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35]
wire [1:0] _fp_sdq_io_enq_bits_data_prevUnrecoded_rawIn_out_sig_T_1 = {1'h0, _fp_sdq_io_enq_bits_data_prevUnrecoded_rawIn_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}]
wire [22:0] _fp_sdq_io_enq_bits_data_prevUnrecoded_rawIn_out_sig_T_2 = fp_sdq_io_enq_bits_data_prevRecoded[22:0]; // @[FPU.scala:441:28]
assign _fp_sdq_io_enq_bits_data_prevUnrecoded_rawIn_out_sig_T_3 = {_fp_sdq_io_enq_bits_data_prevUnrecoded_rawIn_out_sig_T_1, _fp_sdq_io_enq_bits_data_prevUnrecoded_rawIn_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}]
assign fp_sdq_io_enq_bits_data_prevUnrecoded_rawIn_sig = _fp_sdq_io_enq_bits_data_prevUnrecoded_rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44]
wire fp_sdq_io_enq_bits_data_prevUnrecoded_isSubnormal = $signed(fp_sdq_io_enq_bits_data_prevUnrecoded_rawIn_sExp) < 10'sh82; // @[rawFloatFromRecFN.scala:55:23]
wire [4:0] _fp_sdq_io_enq_bits_data_prevUnrecoded_denormShiftDist_T = fp_sdq_io_enq_bits_data_prevUnrecoded_rawIn_sExp[4:0]; // @[rawFloatFromRecFN.scala:55:23]
wire [5:0] _fp_sdq_io_enq_bits_data_prevUnrecoded_denormShiftDist_T_1 = 6'h1 - {1'h0, _fp_sdq_io_enq_bits_data_prevUnrecoded_denormShiftDist_T}; // @[fNFromRecFN.scala:52:{35,47}]
wire [4:0] fp_sdq_io_enq_bits_data_prevUnrecoded_denormShiftDist = _fp_sdq_io_enq_bits_data_prevUnrecoded_denormShiftDist_T_1[4:0]; // @[fNFromRecFN.scala:52:35]
wire [23:0] _fp_sdq_io_enq_bits_data_prevUnrecoded_denormFract_T = fp_sdq_io_enq_bits_data_prevUnrecoded_rawIn_sig[24:1]; // @[rawFloatFromRecFN.scala:55:23]
wire [23:0] _fp_sdq_io_enq_bits_data_prevUnrecoded_denormFract_T_1 = _fp_sdq_io_enq_bits_data_prevUnrecoded_denormFract_T >> fp_sdq_io_enq_bits_data_prevUnrecoded_denormShiftDist; // @[fNFromRecFN.scala:52:35, :53:{38,42}]
wire [22:0] fp_sdq_io_enq_bits_data_prevUnrecoded_denormFract = _fp_sdq_io_enq_bits_data_prevUnrecoded_denormFract_T_1[22:0]; // @[fNFromRecFN.scala:53:{42,60}]
wire [7:0] _fp_sdq_io_enq_bits_data_prevUnrecoded_expOut_T = fp_sdq_io_enq_bits_data_prevUnrecoded_rawIn_sExp[7:0]; // @[rawFloatFromRecFN.scala:55:23]
wire [8:0] _fp_sdq_io_enq_bits_data_prevUnrecoded_expOut_T_1 = {1'h0, _fp_sdq_io_enq_bits_data_prevUnrecoded_expOut_T} - 9'h81; // @[fNFromRecFN.scala:58:{27,45}]
wire [7:0] _fp_sdq_io_enq_bits_data_prevUnrecoded_expOut_T_2 = _fp_sdq_io_enq_bits_data_prevUnrecoded_expOut_T_1[7:0]; // @[fNFromRecFN.scala:58:45]
wire [7:0] _fp_sdq_io_enq_bits_data_prevUnrecoded_expOut_T_3 = fp_sdq_io_enq_bits_data_prevUnrecoded_isSubnormal ? 8'h0 : _fp_sdq_io_enq_bits_data_prevUnrecoded_expOut_T_2; // @[fNFromRecFN.scala:51:38, :56:16, :58:45]
wire _fp_sdq_io_enq_bits_data_prevUnrecoded_expOut_T_4 = fp_sdq_io_enq_bits_data_prevUnrecoded_rawIn_isNaN | fp_sdq_io_enq_bits_data_prevUnrecoded_rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire [7:0] _fp_sdq_io_enq_bits_data_prevUnrecoded_expOut_T_5 = {8{_fp_sdq_io_enq_bits_data_prevUnrecoded_expOut_T_4}}; // @[fNFromRecFN.scala:60:{21,44}]
wire [7:0] fp_sdq_io_enq_bits_data_prevUnrecoded_expOut = _fp_sdq_io_enq_bits_data_prevUnrecoded_expOut_T_3 | _fp_sdq_io_enq_bits_data_prevUnrecoded_expOut_T_5; // @[fNFromRecFN.scala:56:16, :60:{15,21}]
wire [22:0] _fp_sdq_io_enq_bits_data_prevUnrecoded_fractOut_T = fp_sdq_io_enq_bits_data_prevUnrecoded_rawIn_sig[22:0]; // @[rawFloatFromRecFN.scala:55:23]
wire [22:0] _fp_sdq_io_enq_bits_data_prevUnrecoded_fractOut_T_1 = fp_sdq_io_enq_bits_data_prevUnrecoded_rawIn_isInf ? 23'h0 : _fp_sdq_io_enq_bits_data_prevUnrecoded_fractOut_T; // @[rawFloatFromRecFN.scala:55:23]
wire [22:0] fp_sdq_io_enq_bits_data_prevUnrecoded_fractOut = fp_sdq_io_enq_bits_data_prevUnrecoded_isSubnormal ? fp_sdq_io_enq_bits_data_prevUnrecoded_denormFract : _fp_sdq_io_enq_bits_data_prevUnrecoded_fractOut_T_1; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20]
wire [8:0] fp_sdq_io_enq_bits_data_prevUnrecoded_hi = {fp_sdq_io_enq_bits_data_prevUnrecoded_rawIn_sign, fp_sdq_io_enq_bits_data_prevUnrecoded_expOut}; // @[rawFloatFromRecFN.scala:55:23]
wire [31:0] fp_sdq_io_enq_bits_data_prevUnrecoded = {fp_sdq_io_enq_bits_data_prevUnrecoded_hi, fp_sdq_io_enq_bits_data_prevUnrecoded_fractOut}; // @[fNFromRecFN.scala:62:16, :66:12]
wire [31:0] _fp_sdq_io_enq_bits_data_T = fp_sdq_io_enq_bits_data_unrecoded[63:32]; // @[FPU.scala:446:21]
wire [2:0] _fp_sdq_io_enq_bits_data_T_1 = io_req_bits_rs2_data_0[63:61]; // @[FPU.scala:249:25]
wire _fp_sdq_io_enq_bits_data_T_2 = &_fp_sdq_io_enq_bits_data_T_1; // @[FPU.scala:249:{25,56}]
wire [31:0] _fp_sdq_io_enq_bits_data_T_3 = fp_sdq_io_enq_bits_data_unrecoded[31:0]; // @[FPU.scala:446:81]
wire [31:0] _fp_sdq_io_enq_bits_data_T_4 = _fp_sdq_io_enq_bits_data_T_2 ? fp_sdq_io_enq_bits_data_prevUnrecoded : _fp_sdq_io_enq_bits_data_T_3; // @[FPU.scala:249:56, :446:{44,81}]
wire [63:0] _fp_sdq_io_enq_bits_data_T_5 = {_fp_sdq_io_enq_bits_data_T, _fp_sdq_io_enq_bits_data_T_4}; // @[FPU.scala:446:{10,21,44}] |
Generate the Verilog code corresponding to the following Chisel files.
File PE.scala:
// See README.md for license details.
package gemmini
import chisel3._
import chisel3.util._
class PEControl[T <: Data : Arithmetic](accType: T) extends Bundle {
val dataflow = UInt(1.W) // TODO make this an Enum
val propagate = UInt(1.W) // Which register should be propagated (and which should be accumulated)?
val shift = UInt(log2Up(accType.getWidth).W) // TODO this isn't correct for Floats
}
class MacUnit[T <: Data](inputType: T, cType: T, dType: T) (implicit ev: Arithmetic[T]) extends Module {
import ev._
val io = IO(new Bundle {
val in_a = Input(inputType)
val in_b = Input(inputType)
val in_c = Input(cType)
val out_d = Output(dType)
})
io.out_d := io.in_c.mac(io.in_a, io.in_b)
}
// TODO update documentation
/**
* A PE implementing a MAC operation. Configured as fully combinational when integrated into a Mesh.
* @param width Data width of operands
*/
class PE[T <: Data](inputType: T, outputType: T, accType: T, df: Dataflow.Value, max_simultaneous_matmuls: Int)
(implicit ev: Arithmetic[T]) extends Module { // Debugging variables
import ev._
val io = IO(new Bundle {
val in_a = Input(inputType)
val in_b = Input(outputType)
val in_d = Input(outputType)
val out_a = Output(inputType)
val out_b = Output(outputType)
val out_c = Output(outputType)
val in_control = Input(new PEControl(accType))
val out_control = Output(new PEControl(accType))
val in_id = Input(UInt(log2Up(max_simultaneous_matmuls).W))
val out_id = Output(UInt(log2Up(max_simultaneous_matmuls).W))
val in_last = Input(Bool())
val out_last = Output(Bool())
val in_valid = Input(Bool())
val out_valid = Output(Bool())
val bad_dataflow = Output(Bool())
})
val cType = if (df == Dataflow.WS) inputType else accType
// When creating PEs that support multiple dataflows, the
// elaboration/synthesis tools often fail to consolidate and de-duplicate
// MAC units. To force mac circuitry to be re-used, we create a "mac_unit"
// module here which just performs a single MAC operation
val mac_unit = Module(new MacUnit(inputType,
if (df == Dataflow.WS) outputType else accType, outputType))
val a = io.in_a
val b = io.in_b
val d = io.in_d
val c1 = Reg(cType)
val c2 = Reg(cType)
val dataflow = io.in_control.dataflow
val prop = io.in_control.propagate
val shift = io.in_control.shift
val id = io.in_id
val last = io.in_last
val valid = io.in_valid
io.out_a := a
io.out_control.dataflow := dataflow
io.out_control.propagate := prop
io.out_control.shift := shift
io.out_id := id
io.out_last := last
io.out_valid := valid
mac_unit.io.in_a := a
val last_s = RegEnable(prop, valid)
val flip = last_s =/= prop
val shift_offset = Mux(flip, shift, 0.U)
// Which dataflow are we using?
val OUTPUT_STATIONARY = Dataflow.OS.id.U(1.W)
val WEIGHT_STATIONARY = Dataflow.WS.id.U(1.W)
// Is c1 being computed on, or propagated forward (in the output-stationary dataflow)?
val COMPUTE = 0.U(1.W)
val PROPAGATE = 1.U(1.W)
io.bad_dataflow := false.B
when ((df == Dataflow.OS).B || ((df == Dataflow.BOTH).B && dataflow === OUTPUT_STATIONARY)) {
when(prop === PROPAGATE) {
io.out_c := (c1 >> shift_offset).clippedToWidthOf(outputType)
io.out_b := b
mac_unit.io.in_b := b.asTypeOf(inputType)
mac_unit.io.in_c := c2
c2 := mac_unit.io.out_d
c1 := d.withWidthOf(cType)
}.otherwise {
io.out_c := (c2 >> shift_offset).clippedToWidthOf(outputType)
io.out_b := b
mac_unit.io.in_b := b.asTypeOf(inputType)
mac_unit.io.in_c := c1
c1 := mac_unit.io.out_d
c2 := d.withWidthOf(cType)
}
}.elsewhen ((df == Dataflow.WS).B || ((df == Dataflow.BOTH).B && dataflow === WEIGHT_STATIONARY)) {
when(prop === PROPAGATE) {
io.out_c := c1
mac_unit.io.in_b := c2.asTypeOf(inputType)
mac_unit.io.in_c := b
io.out_b := mac_unit.io.out_d
c1 := d
}.otherwise {
io.out_c := c2
mac_unit.io.in_b := c1.asTypeOf(inputType)
mac_unit.io.in_c := b
io.out_b := mac_unit.io.out_d
c2 := d
}
}.otherwise {
io.bad_dataflow := true.B
//assert(false.B, "unknown dataflow")
io.out_c := DontCare
io.out_b := DontCare
mac_unit.io.in_b := b.asTypeOf(inputType)
mac_unit.io.in_c := c2
}
when (!valid) {
c1 := c1
c2 := c2
mac_unit.io.in_b := DontCare
mac_unit.io.in_c := DontCare
}
}
File Arithmetic.scala:
// A simple type class for Chisel datatypes that can add and multiply. To add your own type, simply create your own:
// implicit MyTypeArithmetic extends Arithmetic[MyType] { ... }
package gemmini
import chisel3._
import chisel3.util._
import hardfloat._
// Bundles that represent the raw bits of custom datatypes
case class Float(expWidth: Int, sigWidth: Int) extends Bundle {
val bits = UInt((expWidth + sigWidth).W)
val bias: Int = (1 << (expWidth-1)) - 1
}
case class DummySInt(w: Int) extends Bundle {
val bits = UInt(w.W)
def dontCare: DummySInt = {
val o = Wire(new DummySInt(w))
o.bits := 0.U
o
}
}
// The Arithmetic typeclass which implements various arithmetic operations on custom datatypes
abstract class Arithmetic[T <: Data] {
implicit def cast(t: T): ArithmeticOps[T]
}
abstract class ArithmeticOps[T <: Data](self: T) {
def *(t: T): T
def mac(m1: T, m2: T): T // Returns (m1 * m2 + self)
def +(t: T): T
def -(t: T): T
def >>(u: UInt): T // This is a rounding shift! Rounds away from 0
def >(t: T): Bool
def identity: T
def withWidthOf(t: T): T
def clippedToWidthOf(t: T): T // Like "withWidthOf", except that it saturates
def relu: T
def zero: T
def minimum: T
// Optional parameters, which only need to be defined if you want to enable various optimizations for transformers
def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[T])] = None
def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[T])] = None
def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = None
def mult_with_reciprocal[U <: Data](reciprocal: U) = self
}
object Arithmetic {
implicit object UIntArithmetic extends Arithmetic[UInt] {
override implicit def cast(self: UInt) = new ArithmeticOps(self) {
override def *(t: UInt) = self * t
override def mac(m1: UInt, m2: UInt) = m1 * m2 + self
override def +(t: UInt) = self + t
override def -(t: UInt) = self - t
override def >>(u: UInt) = {
// The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm
// TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here?
val point_five = Mux(u === 0.U, 0.U, self(u - 1.U))
val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U
val ones_digit = self(u)
val r = point_five & (zeros | ones_digit)
(self >> u).asUInt + r
}
override def >(t: UInt): Bool = self > t
override def withWidthOf(t: UInt) = self.asTypeOf(t)
override def clippedToWidthOf(t: UInt) = {
val sat = ((1 << (t.getWidth-1))-1).U
Mux(self > sat, sat, self)(t.getWidth-1, 0)
}
override def relu: UInt = self
override def zero: UInt = 0.U
override def identity: UInt = 1.U
override def minimum: UInt = 0.U
}
}
implicit object SIntArithmetic extends Arithmetic[SInt] {
override implicit def cast(self: SInt) = new ArithmeticOps(self) {
override def *(t: SInt) = self * t
override def mac(m1: SInt, m2: SInt) = m1 * m2 + self
override def +(t: SInt) = self + t
override def -(t: SInt) = self - t
override def >>(u: UInt) = {
// The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm
// TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here?
val point_five = Mux(u === 0.U, 0.U, self(u - 1.U))
val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U
val ones_digit = self(u)
val r = (point_five & (zeros | ones_digit)).asBool
(self >> u).asSInt + Mux(r, 1.S, 0.S)
}
override def >(t: SInt): Bool = self > t
override def withWidthOf(t: SInt) = {
if (self.getWidth >= t.getWidth)
self(t.getWidth-1, 0).asSInt
else {
val sign_bits = t.getWidth - self.getWidth
val sign = self(self.getWidth-1)
Cat(Cat(Seq.fill(sign_bits)(sign)), self).asTypeOf(t)
}
}
override def clippedToWidthOf(t: SInt): SInt = {
val maxsat = ((1 << (t.getWidth-1))-1).S
val minsat = (-(1 << (t.getWidth-1))).S
MuxCase(self, Seq((self > maxsat) -> maxsat, (self < minsat) -> minsat))(t.getWidth-1, 0).asSInt
}
override def relu: SInt = Mux(self >= 0.S, self, 0.S)
override def zero: SInt = 0.S
override def identity: SInt = 1.S
override def minimum: SInt = (-(1 << (self.getWidth-1))).S
override def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = {
// TODO this uses a floating point divider, but we should use an integer divider instead
val input = Wire(Decoupled(denom_t.cloneType))
val output = Wire(Decoupled(self.cloneType))
// We translate our integer to floating-point form so that we can use the hardfloat divider
val expWidth = log2Up(self.getWidth) + 1
val sigWidth = self.getWidth
def sin_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def uin_to_float(x: UInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := false.B
in_to_rec_fn.io.in := x
in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def float_to_in(x: UInt) = {
val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth))
rec_fn_to_in.io.signedOut := true.B
rec_fn_to_in.io.in := x
rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
rec_fn_to_in.io.out.asSInt
}
val self_rec = sin_to_float(self)
val denom_rec = uin_to_float(input.bits)
// Instantiate the hardloat divider
val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options))
input.ready := divider.io.inReady
divider.io.inValid := input.valid
divider.io.sqrtOp := false.B
divider.io.a := self_rec
divider.io.b := denom_rec
divider.io.roundingMode := consts.round_minMag
divider.io.detectTininess := consts.tininess_afterRounding
output.valid := divider.io.outValid_div
output.bits := float_to_in(divider.io.out)
assert(!output.valid || output.ready)
Some((input, output))
}
override def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = {
// TODO this uses a floating point divider, but we should use an integer divider instead
val input = Wire(Decoupled(UInt(0.W)))
val output = Wire(Decoupled(self.cloneType))
input.bits := DontCare
// We translate our integer to floating-point form so that we can use the hardfloat divider
val expWidth = log2Up(self.getWidth) + 1
val sigWidth = self.getWidth
def in_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def float_to_in(x: UInt) = {
val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth))
rec_fn_to_in.io.signedOut := true.B
rec_fn_to_in.io.in := x
rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
rec_fn_to_in.io.out.asSInt
}
val self_rec = in_to_float(self)
// Instantiate the hardloat sqrt
val sqrter = Module(new DivSqrtRecFN_small(expWidth, sigWidth, 0))
input.ready := sqrter.io.inReady
sqrter.io.inValid := input.valid
sqrter.io.sqrtOp := true.B
sqrter.io.a := self_rec
sqrter.io.b := DontCare
sqrter.io.roundingMode := consts.round_minMag
sqrter.io.detectTininess := consts.tininess_afterRounding
output.valid := sqrter.io.outValid_sqrt
output.bits := float_to_in(sqrter.io.out)
assert(!output.valid || output.ready)
Some((input, output))
}
override def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = u match {
case Float(expWidth, sigWidth) =>
val input = Wire(Decoupled(UInt(0.W)))
val output = Wire(Decoupled(u.cloneType))
input.bits := DontCare
// We translate our integer to floating-point form so that we can use the hardfloat divider
def in_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
val self_rec = in_to_float(self)
val one_rec = in_to_float(1.S)
// Instantiate the hardloat divider
val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options))
input.ready := divider.io.inReady
divider.io.inValid := input.valid
divider.io.sqrtOp := false.B
divider.io.a := one_rec
divider.io.b := self_rec
divider.io.roundingMode := consts.round_near_even
divider.io.detectTininess := consts.tininess_afterRounding
output.valid := divider.io.outValid_div
output.bits := fNFromRecFN(expWidth, sigWidth, divider.io.out).asTypeOf(u)
assert(!output.valid || output.ready)
Some((input, output))
case _ => None
}
override def mult_with_reciprocal[U <: Data](reciprocal: U): SInt = reciprocal match {
case recip @ Float(expWidth, sigWidth) =>
def in_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def float_to_in(x: UInt) = {
val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth))
rec_fn_to_in.io.signedOut := true.B
rec_fn_to_in.io.in := x
rec_fn_to_in.io.roundingMode := consts.round_minMag
rec_fn_to_in.io.out.asSInt
}
val self_rec = in_to_float(self)
val reciprocal_rec = recFNFromFN(expWidth, sigWidth, recip.bits)
// Instantiate the hardloat divider
val muladder = Module(new MulRecFN(expWidth, sigWidth))
muladder.io.roundingMode := consts.round_near_even
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := self_rec
muladder.io.b := reciprocal_rec
float_to_in(muladder.io.out)
case _ => self
}
}
}
implicit object FloatArithmetic extends Arithmetic[Float] {
// TODO Floating point arithmetic currently switches between recoded and standard formats for every operation. However, it should stay in the recoded format as it travels through the systolic array
override implicit def cast(self: Float): ArithmeticOps[Float] = new ArithmeticOps(self) {
override def *(t: Float): Float = {
val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth))
t_resizer.io.in := t_rec
t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
t_resizer.io.detectTininess := consts.tininess_afterRounding
val t_rec_resized = t_resizer.io.out
val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth))
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := self_rec
muladder.io.b := t_rec_resized
val out = Wire(Float(self.expWidth, self.sigWidth))
out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
out
}
override def mac(m1: Float, m2: Float): Float = {
// Recode all operands
val m1_rec = recFNFromFN(m1.expWidth, m1.sigWidth, m1.bits)
val m2_rec = recFNFromFN(m2.expWidth, m2.sigWidth, m2.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Resize m1 to self's width
val m1_resizer = Module(new RecFNToRecFN(m1.expWidth, m1.sigWidth, self.expWidth, self.sigWidth))
m1_resizer.io.in := m1_rec
m1_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
m1_resizer.io.detectTininess := consts.tininess_afterRounding
val m1_rec_resized = m1_resizer.io.out
// Resize m2 to self's width
val m2_resizer = Module(new RecFNToRecFN(m2.expWidth, m2.sigWidth, self.expWidth, self.sigWidth))
m2_resizer.io.in := m2_rec
m2_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
m2_resizer.io.detectTininess := consts.tininess_afterRounding
val m2_rec_resized = m2_resizer.io.out
// Perform multiply-add
val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth))
muladder.io.op := 0.U
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := m1_rec_resized
muladder.io.b := m2_rec_resized
muladder.io.c := self_rec
// Convert result to standard format // TODO remove these intermediate recodings
val out = Wire(Float(self.expWidth, self.sigWidth))
out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
out
}
override def +(t: Float): Float = {
require(self.getWidth >= t.getWidth) // This just makes it easier to write the resizing code
// Recode all operands
val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Generate 1 as a float
val in_to_rec_fn = Module(new INToRecFN(1, self.expWidth, self.sigWidth))
in_to_rec_fn.io.signedIn := false.B
in_to_rec_fn.io.in := 1.U
in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
val one_rec = in_to_rec_fn.io.out
// Resize t
val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth))
t_resizer.io.in := t_rec
t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
t_resizer.io.detectTininess := consts.tininess_afterRounding
val t_rec_resized = t_resizer.io.out
// Perform addition
val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth))
muladder.io.op := 0.U
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := t_rec_resized
muladder.io.b := one_rec
muladder.io.c := self_rec
val result = Wire(Float(self.expWidth, self.sigWidth))
result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
result
}
override def -(t: Float): Float = {
val t_sgn = t.bits(t.getWidth-1)
val neg_t = Cat(~t_sgn, t.bits(t.getWidth-2,0)).asTypeOf(t)
self + neg_t
}
override def >>(u: UInt): Float = {
// Recode self
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Get 2^(-u) as a recoded float
val shift_exp = Wire(UInt(self.expWidth.W))
shift_exp := self.bias.U - u
val shift_fn = Cat(0.U(1.W), shift_exp, 0.U((self.sigWidth-1).W))
val shift_rec = recFNFromFN(self.expWidth, self.sigWidth, shift_fn)
assert(shift_exp =/= 0.U, "scaling by denormalized numbers is not currently supported")
// Multiply self and 2^(-u)
val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth))
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := self_rec
muladder.io.b := shift_rec
val result = Wire(Float(self.expWidth, self.sigWidth))
result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
result
}
override def >(t: Float): Bool = {
// Recode all operands
val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Resize t to self's width
val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth))
t_resizer.io.in := t_rec
t_resizer.io.roundingMode := consts.round_near_even
t_resizer.io.detectTininess := consts.tininess_afterRounding
val t_rec_resized = t_resizer.io.out
val comparator = Module(new CompareRecFN(self.expWidth, self.sigWidth))
comparator.io.a := self_rec
comparator.io.b := t_rec_resized
comparator.io.signaling := false.B
comparator.io.gt
}
override def withWidthOf(t: Float): Float = {
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth))
resizer.io.in := self_rec
resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
resizer.io.detectTininess := consts.tininess_afterRounding
val result = Wire(Float(t.expWidth, t.sigWidth))
result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out)
result
}
override def clippedToWidthOf(t: Float): Float = {
// TODO check for overflow. Right now, we just assume that overflow doesn't happen
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth))
resizer.io.in := self_rec
resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
resizer.io.detectTininess := consts.tininess_afterRounding
val result = Wire(Float(t.expWidth, t.sigWidth))
result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out)
result
}
override def relu: Float = {
val raw = rawFloatFromFN(self.expWidth, self.sigWidth, self.bits)
val result = Wire(Float(self.expWidth, self.sigWidth))
result.bits := Mux(!raw.isZero && raw.sign, 0.U, self.bits)
result
}
override def zero: Float = 0.U.asTypeOf(self)
override def identity: Float = Cat(0.U(2.W), ~(0.U((self.expWidth-1).W)), 0.U((self.sigWidth-1).W)).asTypeOf(self)
override def minimum: Float = Cat(1.U, ~(0.U(self.expWidth.W)), 0.U((self.sigWidth-1).W)).asTypeOf(self)
}
}
implicit object DummySIntArithmetic extends Arithmetic[DummySInt] {
override implicit def cast(self: DummySInt) = new ArithmeticOps(self) {
override def *(t: DummySInt) = self.dontCare
override def mac(m1: DummySInt, m2: DummySInt) = self.dontCare
override def +(t: DummySInt) = self.dontCare
override def -(t: DummySInt) = self.dontCare
override def >>(t: UInt) = self.dontCare
override def >(t: DummySInt): Bool = false.B
override def identity = self.dontCare
override def withWidthOf(t: DummySInt) = self.dontCare
override def clippedToWidthOf(t: DummySInt) = self.dontCare
override def relu = self.dontCare
override def zero = self.dontCare
override def minimum: DummySInt = self.dontCare
}
}
}
| module PE_387( // @[PE.scala:31:7]
input clock, // @[PE.scala:31:7]
input reset, // @[PE.scala:31:7]
input [7:0] io_in_a, // @[PE.scala:35:14]
input [19:0] io_in_b, // @[PE.scala:35:14]
input [19:0] io_in_d, // @[PE.scala:35:14]
output [7:0] io_out_a, // @[PE.scala:35:14]
output [19:0] io_out_b, // @[PE.scala:35:14]
output [19:0] io_out_c, // @[PE.scala:35:14]
input io_in_control_dataflow, // @[PE.scala:35:14]
input io_in_control_propagate, // @[PE.scala:35:14]
input [4:0] io_in_control_shift, // @[PE.scala:35:14]
output io_out_control_dataflow, // @[PE.scala:35:14]
output io_out_control_propagate, // @[PE.scala:35:14]
output [4:0] io_out_control_shift, // @[PE.scala:35:14]
input [2:0] io_in_id, // @[PE.scala:35:14]
output [2:0] io_out_id, // @[PE.scala:35:14]
input io_in_last, // @[PE.scala:35:14]
output io_out_last, // @[PE.scala:35:14]
input io_in_valid, // @[PE.scala:35:14]
output io_out_valid // @[PE.scala:35:14]
);
wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:31:7]
wire [19:0] io_in_b_0 = io_in_b; // @[PE.scala:31:7]
wire [19:0] io_in_d_0 = io_in_d; // @[PE.scala:31:7]
wire io_in_control_dataflow_0 = io_in_control_dataflow; // @[PE.scala:31:7]
wire io_in_control_propagate_0 = io_in_control_propagate; // @[PE.scala:31:7]
wire [4:0] io_in_control_shift_0 = io_in_control_shift; // @[PE.scala:31:7]
wire [2:0] io_in_id_0 = io_in_id; // @[PE.scala:31:7]
wire io_in_last_0 = io_in_last; // @[PE.scala:31:7]
wire io_in_valid_0 = io_in_valid; // @[PE.scala:31:7]
wire io_bad_dataflow = 1'h0; // @[PE.scala:31:7]
wire _io_out_c_T_5 = 1'h0; // @[Arithmetic.scala:125:33]
wire _io_out_c_T_6 = 1'h0; // @[Arithmetic.scala:125:60]
wire _io_out_c_T_16 = 1'h0; // @[Arithmetic.scala:125:33]
wire _io_out_c_T_17 = 1'h0; // @[Arithmetic.scala:125:60]
wire [7:0] io_out_a_0 = io_in_a_0; // @[PE.scala:31:7]
wire [19:0] _mac_unit_io_in_b_T = io_in_b_0; // @[PE.scala:31:7, :106:37]
wire [19:0] _mac_unit_io_in_b_T_2 = io_in_b_0; // @[PE.scala:31:7, :113:37]
wire [19:0] _mac_unit_io_in_b_T_8 = io_in_b_0; // @[PE.scala:31:7, :137:35]
wire io_out_control_dataflow_0 = io_in_control_dataflow_0; // @[PE.scala:31:7]
wire io_out_control_propagate_0 = io_in_control_propagate_0; // @[PE.scala:31:7]
wire [4:0] io_out_control_shift_0 = io_in_control_shift_0; // @[PE.scala:31:7]
wire [2:0] io_out_id_0 = io_in_id_0; // @[PE.scala:31:7]
wire io_out_last_0 = io_in_last_0; // @[PE.scala:31:7]
wire io_out_valid_0 = io_in_valid_0; // @[PE.scala:31:7]
wire [19:0] io_out_b_0; // @[PE.scala:31:7]
wire [19:0] io_out_c_0; // @[PE.scala:31:7]
reg [7:0] c1; // @[PE.scala:70:15]
wire [7:0] _io_out_c_zeros_T_1 = c1; // @[PE.scala:70:15]
wire [7:0] _mac_unit_io_in_b_T_6 = c1; // @[PE.scala:70:15, :127:38]
reg [7:0] c2; // @[PE.scala:71:15]
wire [7:0] _io_out_c_zeros_T_10 = c2; // @[PE.scala:71:15]
wire [7:0] _mac_unit_io_in_b_T_4 = c2; // @[PE.scala:71:15, :121:38]
reg last_s; // @[PE.scala:89:25]
wire flip = last_s != io_in_control_propagate_0; // @[PE.scala:31:7, :89:25, :90:21]
wire [4:0] shift_offset = flip ? io_in_control_shift_0 : 5'h0; // @[PE.scala:31:7, :90:21, :91:25]
wire _GEN = shift_offset == 5'h0; // @[PE.scala:91:25]
wire _io_out_c_point_five_T; // @[Arithmetic.scala:101:32]
assign _io_out_c_point_five_T = _GEN; // @[Arithmetic.scala:101:32]
wire _io_out_c_point_five_T_5; // @[Arithmetic.scala:101:32]
assign _io_out_c_point_five_T_5 = _GEN; // @[Arithmetic.scala:101:32]
wire [5:0] _GEN_0 = {1'h0, shift_offset} - 6'h1; // @[PE.scala:91:25]
wire [5:0] _io_out_c_point_five_T_1; // @[Arithmetic.scala:101:53]
assign _io_out_c_point_five_T_1 = _GEN_0; // @[Arithmetic.scala:101:53]
wire [5:0] _io_out_c_zeros_T_2; // @[Arithmetic.scala:102:66]
assign _io_out_c_zeros_T_2 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66]
wire [5:0] _io_out_c_point_five_T_6; // @[Arithmetic.scala:101:53]
assign _io_out_c_point_five_T_6 = _GEN_0; // @[Arithmetic.scala:101:53]
wire [5:0] _io_out_c_zeros_T_11; // @[Arithmetic.scala:102:66]
assign _io_out_c_zeros_T_11 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66]
wire [4:0] _io_out_c_point_five_T_2 = _io_out_c_point_five_T_1[4:0]; // @[Arithmetic.scala:101:53]
wire [7:0] _io_out_c_point_five_T_3 = $signed($signed(c1) >>> _io_out_c_point_five_T_2); // @[PE.scala:70:15]
wire _io_out_c_point_five_T_4 = _io_out_c_point_five_T_3[0]; // @[Arithmetic.scala:101:50]
wire io_out_c_point_five = ~_io_out_c_point_five_T & _io_out_c_point_five_T_4; // @[Arithmetic.scala:101:{29,32,50}]
wire _GEN_1 = shift_offset < 5'h2; // @[PE.scala:91:25]
wire _io_out_c_zeros_T; // @[Arithmetic.scala:102:27]
assign _io_out_c_zeros_T = _GEN_1; // @[Arithmetic.scala:102:27]
wire _io_out_c_zeros_T_9; // @[Arithmetic.scala:102:27]
assign _io_out_c_zeros_T_9 = _GEN_1; // @[Arithmetic.scala:102:27]
wire [4:0] _io_out_c_zeros_T_3 = _io_out_c_zeros_T_2[4:0]; // @[Arithmetic.scala:102:66]
wire [31:0] _io_out_c_zeros_T_4 = 32'h1 << _io_out_c_zeros_T_3; // @[Arithmetic.scala:102:{60,66}]
wire [32:0] _io_out_c_zeros_T_5 = {1'h0, _io_out_c_zeros_T_4} - 33'h1; // @[Arithmetic.scala:102:{60,81}]
wire [31:0] _io_out_c_zeros_T_6 = _io_out_c_zeros_T_5[31:0]; // @[Arithmetic.scala:102:81]
wire [31:0] _io_out_c_zeros_T_7 = {24'h0, _io_out_c_zeros_T_6[7:0] & _io_out_c_zeros_T_1}; // @[Arithmetic.scala:102:{45,52,81}]
wire [31:0] _io_out_c_zeros_T_8 = _io_out_c_zeros_T ? 32'h0 : _io_out_c_zeros_T_7; // @[Arithmetic.scala:102:{24,27,52}]
wire io_out_c_zeros = |_io_out_c_zeros_T_8; // @[Arithmetic.scala:102:{24,89}]
wire [7:0] _GEN_2 = {3'h0, shift_offset}; // @[PE.scala:91:25]
wire [7:0] _GEN_3 = $signed($signed(c1) >>> _GEN_2); // @[PE.scala:70:15]
wire [7:0] _io_out_c_ones_digit_T; // @[Arithmetic.scala:103:30]
assign _io_out_c_ones_digit_T = _GEN_3; // @[Arithmetic.scala:103:30]
wire [7:0] _io_out_c_T; // @[Arithmetic.scala:107:15]
assign _io_out_c_T = _GEN_3; // @[Arithmetic.scala:103:30, :107:15]
wire io_out_c_ones_digit = _io_out_c_ones_digit_T[0]; // @[Arithmetic.scala:103:30]
wire _io_out_c_r_T = io_out_c_zeros | io_out_c_ones_digit; // @[Arithmetic.scala:102:89, :103:30, :105:38]
wire _io_out_c_r_T_1 = io_out_c_point_five & _io_out_c_r_T; // @[Arithmetic.scala:101:29, :105:{29,38}]
wire io_out_c_r = _io_out_c_r_T_1; // @[Arithmetic.scala:105:{29,53}]
wire [1:0] _io_out_c_T_1 = {1'h0, io_out_c_r}; // @[Arithmetic.scala:105:53, :107:33]
wire [8:0] _io_out_c_T_2 = {_io_out_c_T[7], _io_out_c_T} + {{7{_io_out_c_T_1[1]}}, _io_out_c_T_1}; // @[Arithmetic.scala:107:{15,28,33}]
wire [7:0] _io_out_c_T_3 = _io_out_c_T_2[7:0]; // @[Arithmetic.scala:107:28]
wire [7:0] _io_out_c_T_4 = _io_out_c_T_3; // @[Arithmetic.scala:107:28]
wire [19:0] _io_out_c_T_7 = {{12{_io_out_c_T_4[7]}}, _io_out_c_T_4}; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_8 = _io_out_c_T_7; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_9 = _io_out_c_T_8; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_10 = _io_out_c_T_9; // @[Arithmetic.scala:125:{81,99}]
wire [19:0] _mac_unit_io_in_b_T_1 = _mac_unit_io_in_b_T; // @[PE.scala:106:37]
wire [7:0] _mac_unit_io_in_b_WIRE = _mac_unit_io_in_b_T_1[7:0]; // @[PE.scala:106:37]
wire [7:0] _c1_T = io_in_d_0[7:0]; // @[PE.scala:31:7]
wire [7:0] _c2_T = io_in_d_0[7:0]; // @[PE.scala:31:7]
wire [7:0] _c1_T_1 = _c1_T; // @[Arithmetic.scala:114:{15,33}]
wire [4:0] _io_out_c_point_five_T_7 = _io_out_c_point_five_T_6[4:0]; // @[Arithmetic.scala:101:53]
wire [7:0] _io_out_c_point_five_T_8 = $signed($signed(c2) >>> _io_out_c_point_five_T_7); // @[PE.scala:71:15]
wire _io_out_c_point_five_T_9 = _io_out_c_point_five_T_8[0]; // @[Arithmetic.scala:101:50]
wire io_out_c_point_five_1 = ~_io_out_c_point_five_T_5 & _io_out_c_point_five_T_9; // @[Arithmetic.scala:101:{29,32,50}]
wire [4:0] _io_out_c_zeros_T_12 = _io_out_c_zeros_T_11[4:0]; // @[Arithmetic.scala:102:66]
wire [31:0] _io_out_c_zeros_T_13 = 32'h1 << _io_out_c_zeros_T_12; // @[Arithmetic.scala:102:{60,66}]
wire [32:0] _io_out_c_zeros_T_14 = {1'h0, _io_out_c_zeros_T_13} - 33'h1; // @[Arithmetic.scala:102:{60,81}]
wire [31:0] _io_out_c_zeros_T_15 = _io_out_c_zeros_T_14[31:0]; // @[Arithmetic.scala:102:81]
wire [31:0] _io_out_c_zeros_T_16 = {24'h0, _io_out_c_zeros_T_15[7:0] & _io_out_c_zeros_T_10}; // @[Arithmetic.scala:102:{45,52,81}]
wire [31:0] _io_out_c_zeros_T_17 = _io_out_c_zeros_T_9 ? 32'h0 : _io_out_c_zeros_T_16; // @[Arithmetic.scala:102:{24,27,52}]
wire io_out_c_zeros_1 = |_io_out_c_zeros_T_17; // @[Arithmetic.scala:102:{24,89}]
wire [7:0] _GEN_4 = $signed($signed(c2) >>> _GEN_2); // @[PE.scala:71:15]
wire [7:0] _io_out_c_ones_digit_T_1; // @[Arithmetic.scala:103:30]
assign _io_out_c_ones_digit_T_1 = _GEN_4; // @[Arithmetic.scala:103:30]
wire [7:0] _io_out_c_T_11; // @[Arithmetic.scala:107:15]
assign _io_out_c_T_11 = _GEN_4; // @[Arithmetic.scala:103:30, :107:15]
wire io_out_c_ones_digit_1 = _io_out_c_ones_digit_T_1[0]; // @[Arithmetic.scala:103:30]
wire _io_out_c_r_T_2 = io_out_c_zeros_1 | io_out_c_ones_digit_1; // @[Arithmetic.scala:102:89, :103:30, :105:38]
wire _io_out_c_r_T_3 = io_out_c_point_five_1 & _io_out_c_r_T_2; // @[Arithmetic.scala:101:29, :105:{29,38}]
wire io_out_c_r_1 = _io_out_c_r_T_3; // @[Arithmetic.scala:105:{29,53}]
wire [1:0] _io_out_c_T_12 = {1'h0, io_out_c_r_1}; // @[Arithmetic.scala:105:53, :107:33]
wire [8:0] _io_out_c_T_13 = {_io_out_c_T_11[7], _io_out_c_T_11} + {{7{_io_out_c_T_12[1]}}, _io_out_c_T_12}; // @[Arithmetic.scala:107:{15,28,33}]
wire [7:0] _io_out_c_T_14 = _io_out_c_T_13[7:0]; // @[Arithmetic.scala:107:28]
wire [7:0] _io_out_c_T_15 = _io_out_c_T_14; // @[Arithmetic.scala:107:28]
wire [19:0] _io_out_c_T_18 = {{12{_io_out_c_T_15[7]}}, _io_out_c_T_15}; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_19 = _io_out_c_T_18; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_20 = _io_out_c_T_19; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_21 = _io_out_c_T_20; // @[Arithmetic.scala:125:{81,99}]
wire [19:0] _mac_unit_io_in_b_T_3 = _mac_unit_io_in_b_T_2; // @[PE.scala:113:37]
wire [7:0] _mac_unit_io_in_b_WIRE_1 = _mac_unit_io_in_b_T_3[7:0]; // @[PE.scala:113:37]
wire [7:0] _c2_T_1 = _c2_T; // @[Arithmetic.scala:114:{15,33}]
wire [7:0] _mac_unit_io_in_b_T_5; // @[PE.scala:121:38]
assign _mac_unit_io_in_b_T_5 = _mac_unit_io_in_b_T_4; // @[PE.scala:121:38]
wire [7:0] _mac_unit_io_in_b_WIRE_2 = _mac_unit_io_in_b_T_5; // @[PE.scala:121:38]
assign io_out_c_0 = io_in_control_propagate_0 ? {{12{c1[7]}}, c1} : {{12{c2[7]}}, c2}; // @[PE.scala:31:7, :70:15, :71:15, :119:30, :120:16, :126:16]
wire [7:0] _mac_unit_io_in_b_T_7; // @[PE.scala:127:38]
assign _mac_unit_io_in_b_T_7 = _mac_unit_io_in_b_T_6; // @[PE.scala:127:38]
wire [7:0] _mac_unit_io_in_b_WIRE_3 = _mac_unit_io_in_b_T_7; // @[PE.scala:127:38]
wire [19:0] _mac_unit_io_in_b_T_9 = _mac_unit_io_in_b_T_8; // @[PE.scala:137:35]
wire [7:0] _mac_unit_io_in_b_WIRE_4 = _mac_unit_io_in_b_T_9[7:0]; // @[PE.scala:137:35]
always @(posedge clock) begin // @[PE.scala:31:7]
if (io_in_valid_0 & io_in_control_propagate_0) // @[PE.scala:31:7, :102:95, :141:17, :142:8]
c1 <= io_in_d_0[7:0]; // @[PE.scala:31:7, :70:15]
if (~(~io_in_valid_0 | io_in_control_propagate_0)) // @[PE.scala:31:7, :71:15, :102:95, :119:30, :130:10, :141:{9,17}, :143:8]
c2 <= io_in_d_0[7:0]; // @[PE.scala:31:7, :71:15]
if (io_in_valid_0) // @[PE.scala:31:7]
last_s <= io_in_control_propagate_0; // @[PE.scala:31:7, :89:25]
always @(posedge)
MacUnit_131 mac_unit ( // @[PE.scala:64:24]
.clock (clock),
.reset (reset),
.io_in_a (io_in_a_0), // @[PE.scala:31:7]
.io_in_b (io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE_2 : _mac_unit_io_in_b_WIRE_3), // @[PE.scala:31:7, :119:30, :121:{24,38}, :127:{24,38}]
.io_in_c (io_in_b_0), // @[PE.scala:31:7]
.io_out_d (io_out_b_0)
); // @[PE.scala:64:24]
assign io_out_a = io_out_a_0; // @[PE.scala:31:7]
assign io_out_b = io_out_b_0; // @[PE.scala:31:7]
assign io_out_c = io_out_c_0; // @[PE.scala:31:7]
assign io_out_control_dataflow = io_out_control_dataflow_0; // @[PE.scala:31:7]
assign io_out_control_propagate = io_out_control_propagate_0; // @[PE.scala:31:7]
assign io_out_control_shift = io_out_control_shift_0; // @[PE.scala:31:7]
assign io_out_id = io_out_id_0; // @[PE.scala:31:7]
assign io_out_last = io_out_last_0; // @[PE.scala:31:7]
assign io_out_valid = io_out_valid_0; // @[PE.scala:31:7]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File Monitor.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceLine
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import freechips.rocketchip.diplomacy.EnableMonitors
import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode}
import freechips.rocketchip.util.PlusArg
case class TLMonitorArgs(edge: TLEdge)
abstract class TLMonitorBase(args: TLMonitorArgs) extends Module
{
val io = IO(new Bundle {
val in = Input(new TLBundle(args.edge.bundle))
})
def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit
legalize(io.in, args.edge, reset)
}
object TLMonitor {
def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = {
if (enable) {
EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) }
} else { node }
}
}
class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args)
{
require (args.edge.params(TLMonitorStrictMode) || (! args.edge.params(TestplanTestType).formal))
val cover_prop_class = PropertyClass.Default
//Like assert but can flip to being an assumption for formal verification
def monAssert(cond: Bool, message: String): Unit =
if (monitorDir == MonitorDirection.Monitor) {
assert(cond, message)
} else {
Property(monitorDir, cond, message, PropertyClass.Default)
}
def assume(cond: Bool, message: String): Unit =
if (monitorDir == MonitorDirection.Monitor) {
assert(cond, message)
} else {
Property(monitorDir.flip, cond, message, PropertyClass.Default)
}
def extra = {
args.edge.sourceInfo match {
case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)"
case _ => ""
}
}
def visible(address: UInt, source: UInt, edge: TLEdge) =
edge.client.clients.map { c =>
!c.sourceId.contains(source) ||
c.visibility.map(_.contains(address)).reduce(_ || _)
}.reduce(_ && _)
def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = {
//switch this flag to turn on diplomacy in error messages
def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n"
monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra)
// Reuse these subexpressions to save some firrtl lines
val source_ok = edge.client.contains(bundle.source)
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val mask = edge.full_mask(bundle)
monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility")
//The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B
//TODO: check for acquireT?
when (bundle.opcode === TLMessages.AcquireBlock) {
monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra)
monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra)
monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra)
monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra)
}
when (bundle.opcode === TLMessages.AcquirePerm) {
monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra)
monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra)
monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra)
monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra)
monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra)
}
when (bundle.opcode === TLMessages.Get) {
monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra)
monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra)
monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra)
}
when (bundle.opcode === TLMessages.PutFullData) {
monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra)
monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.PutPartialData) {
monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra)
monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.ArithmeticData) {
monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra)
monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.LogicalData) {
monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra)
monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.Hint) {
monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra)
monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra)
}
}
def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = {
monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra)
monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility")
// Reuse these subexpressions to save some firrtl lines
val address_ok = edge.manager.containsSafe(edge.address(bundle))
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val mask = edge.full_mask(bundle)
val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source
when (bundle.opcode === TLMessages.Probe) {
assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra)
assume (address_ok, "'B' channel Probe carries unmanaged address" + extra)
assume (legal_source, "'B' channel Probe carries source that is not first source" + extra)
assume (is_aligned, "'B' channel Probe address not aligned to size" + extra)
assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra)
assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra)
assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra)
}
when (bundle.opcode === TLMessages.Get) {
monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra)
monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra)
}
when (bundle.opcode === TLMessages.PutFullData) {
monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra)
monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.PutPartialData) {
monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra)
monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.ArithmeticData) {
monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra)
monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra)
monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.LogicalData) {
monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra)
monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra)
monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.Hint) {
monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra)
monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra)
monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra)
}
}
def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = {
monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra)
val source_ok = edge.client.contains(bundle.source)
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val address_ok = edge.manager.containsSafe(edge.address(bundle))
monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility")
when (bundle.opcode === TLMessages.ProbeAck) {
monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra)
monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra)
}
when (bundle.opcode === TLMessages.ProbeAckData) {
monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra)
}
when (bundle.opcode === TLMessages.Release) {
monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra)
monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra)
monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra)
}
when (bundle.opcode === TLMessages.ReleaseData) {
monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra)
monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra)
}
when (bundle.opcode === TLMessages.AccessAck) {
monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra)
monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra)
}
when (bundle.opcode === TLMessages.AccessAckData) {
monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra)
}
when (bundle.opcode === TLMessages.HintAck) {
monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra)
monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra)
}
}
def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = {
assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra)
val source_ok = edge.client.contains(bundle.source)
val sink_ok = bundle.sink < edge.manager.endSinkId.U
val deny_put_ok = edge.manager.mayDenyPut.B
val deny_get_ok = edge.manager.mayDenyGet.B
when (bundle.opcode === TLMessages.ReleaseAck) {
assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra)
assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra)
assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra)
}
when (bundle.opcode === TLMessages.Grant) {
assume (source_ok, "'D' channel Grant carries invalid source ID" + extra)
assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra)
assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra)
assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra)
assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel Grant is denied" + extra)
}
when (bundle.opcode === TLMessages.GrantData) {
assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra)
assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra)
assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra)
assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra)
assume (!bundle.denied || bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra)
assume (deny_get_ok || !bundle.denied, "'D' channel GrantData is denied" + extra)
}
when (bundle.opcode === TLMessages.AccessAck) {
assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel AccessAck is denied" + extra)
}
when (bundle.opcode === TLMessages.AccessAckData) {
assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra)
assume (!bundle.denied || bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra)
assume (deny_get_ok || !bundle.denied, "'D' channel AccessAckData is denied" + extra)
}
when (bundle.opcode === TLMessages.HintAck) {
assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel HintAck is denied" + extra)
}
}
def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = {
val sink_ok = bundle.sink < edge.manager.endSinkId.U
monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra)
}
def legalizeFormat(bundle: TLBundle, edge: TLEdge) = {
when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) }
when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) }
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) }
when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) }
when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) }
} else {
monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra)
monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra)
monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra)
}
}
def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = {
val a_first = edge.first(a.bits, a.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (a.valid && !a_first) {
monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra)
monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra)
monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra)
monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra)
monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra)
}
when (a.fire && a_first) {
opcode := a.bits.opcode
param := a.bits.param
size := a.bits.size
source := a.bits.source
address := a.bits.address
}
}
def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = {
val b_first = edge.first(b.bits, b.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (b.valid && !b_first) {
monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra)
monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra)
monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra)
monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra)
monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra)
}
when (b.fire && b_first) {
opcode := b.bits.opcode
param := b.bits.param
size := b.bits.size
source := b.bits.source
address := b.bits.address
}
}
def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = {
// Symbolic variable
val sym_source = Wire(UInt(edge.client.endSourceId.W))
// TODO: Connect sym_source to a fixed value for simulation and to a
// free wire in formal
sym_source := 0.U
// Type casting Int to UInt
val maxSourceId = Wire(UInt(edge.client.endSourceId.W))
maxSourceId := edge.client.endSourceId.U
// Delayed verison of sym_source
val sym_source_d = Reg(UInt(edge.client.endSourceId.W))
sym_source_d := sym_source
// These will be constraints for FV setup
Property(
MonitorDirection.Monitor,
(sym_source === sym_source_d),
"sym_source should remain stable",
PropertyClass.Default)
Property(
MonitorDirection.Monitor,
(sym_source <= maxSourceId),
"sym_source should take legal value",
PropertyClass.Default)
val my_resp_pend = RegInit(false.B)
val my_opcode = Reg(UInt())
val my_size = Reg(UInt())
val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire)
val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire)
val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source)
val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source)
val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat)
val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend)
when (my_set_resp_pend) {
my_resp_pend := true.B
} .elsewhen (my_clr_resp_pend) {
my_resp_pend := false.B
}
when (my_a_first_beat) {
my_opcode := bundle.a.bits.opcode
my_size := bundle.a.bits.size
}
val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size)
val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode)
val my_resp_opcode_legal = Wire(Bool())
when ((my_resp_opcode === TLMessages.Get) || (my_resp_opcode === TLMessages.ArithmeticData) ||
(my_resp_opcode === TLMessages.LogicalData)) {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData)
} .elsewhen ((my_resp_opcode === TLMessages.PutFullData) || (my_resp_opcode === TLMessages.PutPartialData)) {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck)
} .otherwise {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck)
}
monAssert (IfThen(my_resp_pend, !my_a_first_beat),
"Request message should not be sent with a source ID, for which a response message" +
"is already pending (not received until current cycle) for a prior request message" +
"with the same source ID" + extra)
assume (IfThen(my_clr_resp_pend, (my_set_resp_pend || my_resp_pend)),
"Response message should be accepted with a source ID only if a request message with the" +
"same source ID has been accepted or is being accepted in the current cycle" + extra)
assume (IfThen(my_d_first_beat, (my_a_first_beat || my_resp_pend)),
"Response message should be sent with a source ID only if a request message with the" +
"same source ID has been accepted or is being sent in the current cycle" + extra)
assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)),
"If d_valid is 1, then d_size should be same as a_size of the corresponding request" +
"message" + extra)
assume (IfThen(my_d_first_beat, my_resp_opcode_legal),
"If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" +
"request message" + extra)
}
def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = {
val c_first = edge.first(c.bits, c.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (c.valid && !c_first) {
monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra)
monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra)
monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra)
monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra)
monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra)
}
when (c.fire && c_first) {
opcode := c.bits.opcode
param := c.bits.param
size := c.bits.size
source := c.bits.source
address := c.bits.address
}
}
def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = {
val d_first = edge.first(d.bits, d.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val sink = Reg(UInt())
val denied = Reg(Bool())
when (d.valid && !d_first) {
assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra)
assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra)
assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra)
assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra)
assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra)
assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra)
}
when (d.fire && d_first) {
opcode := d.bits.opcode
param := d.bits.param
size := d.bits.size
source := d.bits.source
sink := d.bits.sink
denied := d.bits.denied
}
}
def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = {
legalizeMultibeatA(bundle.a, edge)
legalizeMultibeatD(bundle.d, edge)
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
legalizeMultibeatB(bundle.b, edge)
legalizeMultibeatC(bundle.c, edge)
}
}
//This is left in for almond which doesn't adhere to the tilelink protocol
@deprecated("Use legalizeADSource instead if possible","")
def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = {
val inflight = RegInit(0.U(edge.client.endSourceId.W))
val a_first = edge.first(bundle.a.bits, bundle.a.fire)
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
val a_set = WireInit(0.U(edge.client.endSourceId.W))
when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) {
a_set := UIntToOH(bundle.a.bits.source)
assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra)
}
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
assume((a_set | inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra)
}
if (edge.manager.minLatency > 0) {
assume(a_set =/= d_clr || !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra)
}
inflight := (inflight | a_set) & ~d_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
assert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = {
val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset)
val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything
val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size)
val log_a_size_bus_size = log2Ceil(a_size_bus_size)
def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits
val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error
inflight.suggestName("inflight")
val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
inflight_opcodes.suggestName("inflight_opcodes")
val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
inflight_sizes.suggestName("inflight_sizes")
val a_first = edge.first(bundle.a.bits, bundle.a.fire)
a_first.suggestName("a_first")
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
d_first.suggestName("d_first")
val a_set = WireInit(0.U(edge.client.endSourceId.W))
val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
a_set.suggestName("a_set")
a_set_wo_ready.suggestName("a_set_wo_ready")
val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
a_opcodes_set.suggestName("a_opcodes_set")
val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
a_sizes_set.suggestName("a_sizes_set")
val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W))
a_opcode_lookup.suggestName("a_opcode_lookup")
a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U
val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W))
a_size_lookup.suggestName("a_size_lookup")
a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U
val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant))
val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant))
val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W))
a_opcodes_set_interm.suggestName("a_opcodes_set_interm")
val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W))
a_sizes_set_interm.suggestName("a_sizes_set_interm")
when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) {
a_set_wo_ready := UIntToOH(bundle.a.bits.source)
}
when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) {
a_set := UIntToOH(bundle.a.bits.source)
a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) | 1.U
a_sizes_set_interm := (bundle.a.bits.size << 1.U) | 1.U
a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U)
a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U)
monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra)
}
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
d_clr.suggestName("d_clr")
d_clr_wo_ready.suggestName("d_clr_wo_ready")
val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
d_opcodes_clr.suggestName("d_opcodes_clr")
val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
d_sizes_clr.suggestName("d_sizes_clr")
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr_wo_ready := UIntToOH(bundle.d.bits.source)
}
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U)
d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U)
}
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source)
assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra)
when (same_cycle_resp) {
assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) ||
(bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra)
assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra)
} .otherwise {
assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) ||
(bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra)
assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra)
}
}
when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) {
assume((!bundle.d.ready) || bundle.a.ready, "ready check")
}
if (edge.manager.minLatency > 0) {
assume(a_set_wo_ready =/= d_clr_wo_ready || !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra)
}
inflight := (inflight | a_set) & ~d_clr
inflight_opcodes := (inflight_opcodes | a_opcodes_set) & ~d_opcodes_clr
inflight_sizes := (inflight_sizes | a_sizes_set) & ~d_sizes_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = {
val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset)
val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything
val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size)
val log_c_size_bus_size = log2Ceil(c_size_bus_size)
def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits
val inflight = RegInit(0.U((2 max edge.client.endSourceId).W))
val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
inflight.suggestName("inflight")
inflight_opcodes.suggestName("inflight_opcodes")
inflight_sizes.suggestName("inflight_sizes")
val c_first = edge.first(bundle.c.bits, bundle.c.fire)
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
c_first.suggestName("c_first")
d_first.suggestName("d_first")
val c_set = WireInit(0.U(edge.client.endSourceId.W))
val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
c_set.suggestName("c_set")
c_set_wo_ready.suggestName("c_set_wo_ready")
c_opcodes_set.suggestName("c_opcodes_set")
c_sizes_set.suggestName("c_sizes_set")
val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W))
val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W))
c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U
c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U
c_opcode_lookup.suggestName("c_opcode_lookup")
c_size_lookup.suggestName("c_size_lookup")
val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W))
val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W))
c_opcodes_set_interm.suggestName("c_opcodes_set_interm")
c_sizes_set_interm.suggestName("c_sizes_set_interm")
when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) {
c_set_wo_ready := UIntToOH(bundle.c.bits.source)
}
when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) {
c_set := UIntToOH(bundle.c.bits.source)
c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) | 1.U
c_sizes_set_interm := (bundle.c.bits.size << 1.U) | 1.U
c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U)
c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U)
monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra)
}
val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck || bundle.c.bits.opcode === TLMessages.ProbeAckData
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
d_clr.suggestName("d_clr")
d_clr_wo_ready.suggestName("d_clr_wo_ready")
d_opcodes_clr.suggestName("d_opcodes_clr")
d_sizes_clr.suggestName("d_sizes_clr")
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
d_clr_wo_ready := UIntToOH(bundle.d.bits.source)
}
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U)
d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U)
}
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source)
assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra)
when (same_cycle_resp) {
assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra)
} .otherwise {
assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra)
}
}
when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) {
assume((!bundle.d.ready) || bundle.c.ready, "ready check")
}
if (edge.manager.minLatency > 0) {
when (c_set_wo_ready.orR) {
assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra)
}
}
inflight := (inflight | c_set) & ~d_clr
inflight_opcodes := (inflight_opcodes | c_opcodes_set) & ~d_opcodes_clr
inflight_sizes := (inflight_sizes | c_sizes_set) & ~d_sizes_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.c.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = {
val inflight = RegInit(0.U(edge.manager.endSinkId.W))
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
val e_first = true.B
val d_set = WireInit(0.U(edge.manager.endSinkId.W))
when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) {
d_set := UIntToOH(bundle.d.bits.sink)
assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra)
}
val e_clr = WireInit(0.U(edge.manager.endSinkId.W))
when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) {
e_clr := UIntToOH(bundle.e.bits.sink)
monAssert((d_set | inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra)
}
// edge.client.minLatency applies to BC, not DE
inflight := (inflight | d_set) & ~e_clr
}
def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = {
val sourceBits = log2Ceil(edge.client.endSourceId)
val tooBig = 14 // >16kB worth of flight information gets to be too much
if (sourceBits > tooBig) {
println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked")
} else {
if (args.edge.params(TestplanTestType).simulation) {
if (args.edge.params(TLMonitorStrictMode)) {
legalizeADSource(bundle, edge)
legalizeCDSource(bundle, edge)
} else {
legalizeADSourceOld(bundle, edge)
}
}
if (args.edge.params(TestplanTestType).formal) {
legalizeADSourceFormal(bundle, edge)
}
}
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
// legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize...
val sinkBits = log2Ceil(edge.manager.endSinkId)
if (sinkBits > tooBig) {
println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked")
} else {
legalizeDESink(bundle, edge)
}
}
}
def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = {
legalizeFormat (bundle, edge)
legalizeMultibeat (bundle, edge)
legalizeUnique (bundle, edge)
}
}
File PlusArg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.experimental._
import chisel3.util.HasBlackBoxResource
@deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05")
case class PlusArgInfo(default: BigInt, docstring: String)
/** Case class for PlusArg information
*
* @tparam A scala type of the PlusArg value
* @param default optional default value
* @param docstring text to include in the help
* @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT)
*/
private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String)
/** Typeclass for converting a type to a doctype string
* @tparam A some type
*/
trait Doctypeable[A] {
/** Return the doctype string for some option */
def toDoctype(a: Option[A]): String
}
/** Object containing implementations of the Doctypeable typeclass */
object Doctypes {
/** Converts an Int => "INT" */
implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" }
/** Converts a BigInt => "INT" */
implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" }
/** Converts a String => "STRING" */
implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" }
}
class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map(
"FORMAT" -> StringParam(format),
"DEFAULT" -> IntParam(default),
"WIDTH" -> IntParam(width)
)) with HasBlackBoxResource {
val io = IO(new Bundle {
val out = Output(UInt(width.W))
})
addResource("/vsrc/plusarg_reader.v")
}
/* This wrapper class has no outputs, making it clear it is a simulation-only construct */
class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module {
val io = IO(new Bundle {
val count = Input(UInt(width.W))
})
val max = Module(new plusarg_reader(format, default, docstring, width)).io.out
when (max > 0.U) {
assert (io.count < max, s"Timeout exceeded: $docstring")
}
}
import Doctypes._
object PlusArg
{
/** PlusArg("foo") will return 42.U if the simulation is run with +foo=42
* Do not use this as an initial register value. The value is set in an
* initial block and thus accessing it from another initial is racey.
* Add a docstring to document the arg, which can be dumped in an elaboration
* pass.
*/
def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = {
PlusArgArtefacts.append(name, Some(default), docstring)
Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out
}
/** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert
* to kill the simulation when count exceeds the specified integer argument.
* Default 0 will never assert.
*/
def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = {
PlusArgArtefacts.append(name, Some(default), docstring)
Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count
}
}
object PlusArgArtefacts {
private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty
/* Add a new PlusArg */
@deprecated(
"Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08",
"Rocket Chip 2020.05"
)
def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring)
/** Add a new PlusArg
*
* @tparam A scala type of the PlusArg value
* @param name name for the PlusArg
* @param default optional default value
* @param docstring text to include in the help
*/
def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit =
artefacts = artefacts ++
Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default)))
/* From plus args, generate help text */
private def serializeHelp_cHeader(tab: String = ""): String = artefacts
.map{ case(arg, info) =>
s"""|$tab+$arg=${info.doctype}\\n\\
|$tab${" "*20}${info.docstring}\\n\\
|""".stripMargin ++ info.default.map{ case default =>
s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("")
}.toSeq.mkString("\\n\\\n") ++ "\""
/* From plus args, generate a char array of their names */
private def serializeArray_cHeader(tab: String = ""): String = {
val prettyTab = tab + " " * 44 // Length of 'static const ...'
s"${tab}static const char * verilog_plusargs [] = {\\\n" ++
artefacts
.map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" }
.mkString("")++
s"${prettyTab}0};"
}
/* Generate C code to be included in emulator.cc that helps with
* argument parsing based on available Verilog PlusArgs */
def serialize_cHeader(): String =
s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\
|${serializeHelp_cHeader(" "*7)}
|${serializeArray_cHeader()}
|""".stripMargin
}
File Parameters.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.diplomacy
import chisel3._
import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor}
import freechips.rocketchip.util.ShiftQueue
/** Options for describing the attributes of memory regions */
object RegionType {
// Define the 'more relaxed than' ordering
val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS)
sealed trait T extends Ordered[T] {
def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this)
}
case object CACHED extends T // an intermediate agent may have cached a copy of the region for you
case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided
case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible
case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached
case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects
case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed
case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively
}
// A non-empty half-open range; [start, end)
case class IdRange(start: Int, end: Int) extends Ordered[IdRange]
{
require (start >= 0, s"Ids cannot be negative, but got: $start.")
require (start <= end, "Id ranges cannot be negative.")
def compare(x: IdRange) = {
val primary = (this.start - x.start).signum
val secondary = (x.end - this.end).signum
if (primary != 0) primary else secondary
}
def overlaps(x: IdRange) = start < x.end && x.start < end
def contains(x: IdRange) = start <= x.start && x.end <= end
def contains(x: Int) = start <= x && x < end
def contains(x: UInt) =
if (size == 0) {
false.B
} else if (size == 1) { // simple comparison
x === start.U
} else {
// find index of largest different bit
val largestDeltaBit = log2Floor(start ^ (end-1))
val smallestCommonBit = largestDeltaBit + 1 // may not exist in x
val uncommonMask = (1 << smallestCommonBit) - 1
val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0)
// the prefix must match exactly (note: may shift ALL bits away)
(x >> smallestCommonBit) === (start >> smallestCommonBit).U &&
// firrtl constant prop range analysis can eliminate these two:
(start & uncommonMask).U <= uncommonBits &&
uncommonBits <= ((end-1) & uncommonMask).U
}
def shift(x: Int) = IdRange(start+x, end+x)
def size = end - start
def isEmpty = end == start
def range = start until end
}
object IdRange
{
def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else {
val ranges = s.sorted
(ranges.tail zip ranges.init) find { case (a, b) => a overlaps b }
}
}
// An potentially empty inclusive range of 2-powers [min, max] (in bytes)
case class TransferSizes(min: Int, max: Int)
{
def this(x: Int) = this(x, x)
require (min <= max, s"Min transfer $min > max transfer $max")
require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)")
require (max == 0 || isPow2(max), s"TransferSizes must be a power of 2, got: $max")
require (min == 0 || isPow2(min), s"TransferSizes must be a power of 2, got: $min")
require (max == 0 || min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)")
def none = min == 0
def contains(x: Int) = isPow2(x) && min <= x && x <= max
def containsLg(x: Int) = contains(1 << x)
def containsLg(x: UInt) =
if (none) false.B
else if (min == max) { log2Ceil(min).U === x }
else { log2Ceil(min).U <= x && x <= log2Ceil(max).U }
def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max)
def intersect(x: TransferSizes) =
if (x.max < min || max < x.min) TransferSizes.none
else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max))
// Not a union, because the result may contain sizes contained by neither term
// NOT TO BE CONFUSED WITH COVERPOINTS
def mincover(x: TransferSizes) = {
if (none) {
x
} else if (x.none) {
this
} else {
TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max))
}
}
override def toString() = "TransferSizes[%d, %d]".format(min, max)
}
object TransferSizes {
def apply(x: Int) = new TransferSizes(x)
val none = new TransferSizes(0)
def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _)
def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _)
implicit def asBool(x: TransferSizes) = !x.none
}
// AddressSets specify the address space managed by the manager
// Base is the base address, and mask are the bits consumed by the manager
// e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff
// e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ...
case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet]
{
// Forbid misaligned base address (and empty sets)
require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}")
require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous
// We do allow negative mask (=> ignore all high bits)
def contains(x: BigInt) = ((x ^ base) & ~mask) == 0
def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S
// turn x into an address contained in this set
def legalize(x: UInt): UInt = base.U | (mask.U & x)
// overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1)
def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0
// contains iff bitwise: x.mask => mask && contains(x.base)
def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0
// The number of bytes to which the manager must be aligned
def alignment = ((mask + 1) & ~mask)
// Is this a contiguous memory range
def contiguous = alignment == mask+1
def finite = mask >= 0
def max = { require (finite, "Max cannot be calculated on infinite mask"); base | mask }
// Widen the match function to ignore all bits in imask
def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask)
// Return an AddressSet that only contains the addresses both sets contain
def intersect(x: AddressSet): Option[AddressSet] = {
if (!overlaps(x)) {
None
} else {
val r_mask = mask & x.mask
val r_base = base | x.base
Some(AddressSet(r_base, r_mask))
}
}
def subtract(x: AddressSet): Seq[AddressSet] = {
intersect(x) match {
case None => Seq(this)
case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit =>
val nmask = (mask & (bit-1)) | remove.mask
val nbase = (remove.base ^ bit) & ~nmask
AddressSet(nbase, nmask)
}
}
}
// AddressSets have one natural Ordering (the containment order, if contiguous)
def compare(x: AddressSet) = {
val primary = (this.base - x.base).signum // smallest address first
val secondary = (x.mask - this.mask).signum // largest mask first
if (primary != 0) primary else secondary
}
// We always want to see things in hex
override def toString() = {
if (mask >= 0) {
"AddressSet(0x%x, 0x%x)".format(base, mask)
} else {
"AddressSet(0x%x, ~0x%x)".format(base, ~mask)
}
}
def toRanges = {
require (finite, "Ranges cannot be calculated on infinite mask")
val size = alignment
val fragments = mask & ~(size-1)
val bits = bitIndexes(fragments)
(BigInt(0) until (BigInt(1) << bits.size)).map { i =>
val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) }
AddressRange(off, size)
}
}
}
object AddressSet
{
val everything = AddressSet(0, -1)
def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = {
if (size == 0) tail.reverse else {
val maxBaseAlignment = base & (-base) // 0 for infinite (LSB)
val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size
val step =
if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment)
maxSizeAlignment else maxBaseAlignment
misaligned(base+step, size-step, AddressSet(base, step-1) +: tail)
}
}
def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = {
// Pair terms up by ignoring 'bit'
seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) =>
if (seq.size == 1) {
seq.head // singleton -> unaffected
} else {
key.copy(mask = key.mask | bit) // pair - widen mask by bit
}
}.toList
}
def unify(seq: Seq[AddressSet]): Seq[AddressSet] = {
val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _)
AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted
}
def enumerateMask(mask: BigInt): Seq[BigInt] = {
def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] =
if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail)
helper(0, Nil)
}
def enumerateBits(mask: BigInt): Seq[BigInt] = {
def helper(x: BigInt): Seq[BigInt] = {
if (x == 0) {
Nil
} else {
val bit = x & (-x)
bit +: helper(x & ~bit)
}
}
helper(mask)
}
}
case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean)
{
require (depth >= 0, "Buffer depth must be >= 0")
def isDefined = depth > 0
def latency = if (isDefined && !flow) 1 else 0
def apply[T <: Data](x: DecoupledIO[T]) =
if (isDefined) Queue(x, depth, flow=flow, pipe=pipe)
else x
def irrevocable[T <: Data](x: ReadyValidIO[T]) =
if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe)
else x
def sq[T <: Data](x: DecoupledIO[T]) =
if (!isDefined) x else {
val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe))
sq.io.enq <> x
sq.io.deq
}
override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "")
}
object BufferParams
{
implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false)
val default = BufferParams(2)
val none = BufferParams(0)
val flow = BufferParams(1, true, false)
val pipe = BufferParams(1, false, true)
}
case class TriStateValue(value: Boolean, set: Boolean)
{
def update(orig: Boolean) = if (set) value else orig
}
object TriStateValue
{
implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true)
def unset = TriStateValue(false, false)
}
trait DirectedBuffers[T] {
def copyIn(x: BufferParams): T
def copyOut(x: BufferParams): T
def copyInOut(x: BufferParams): T
}
trait IdMapEntry {
def name: String
def from: IdRange
def to: IdRange
def isCache: Boolean
def requestFifo: Boolean
def maxTransactionsInFlight: Option[Int]
def pretty(fmt: String) =
if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5
fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "")
} else {
fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "")
}
}
abstract class IdMap[T <: IdMapEntry] {
protected val fmt: String
val mapping: Seq[T]
def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n")
}
File Edges.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.util._
class TLEdge(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdgeParameters(client, manager, params, sourceInfo)
{
def isAligned(address: UInt, lgSize: UInt): Bool = {
if (maxLgSize == 0) true.B else {
val mask = UIntToOH1(lgSize, maxLgSize)
(address & mask) === 0.U
}
}
def mask(address: UInt, lgSize: UInt): UInt =
MaskGen(address, lgSize, manager.beatBytes)
def staticHasData(bundle: TLChannel): Option[Boolean] = {
bundle match {
case _:TLBundleA => {
// Do there exist A messages with Data?
val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial
// Do there exist A messages without Data?
val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint
// Statically optimize the case where hasData is a constant
if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None
}
case _:TLBundleB => {
// Do there exist B messages with Data?
val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial
// Do there exist B messages without Data?
val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint
// Statically optimize the case where hasData is a constant
if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None
}
case _:TLBundleC => {
// Do there eixst C messages with Data?
val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe
// Do there exist C messages without Data?
val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe
if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None
}
case _:TLBundleD => {
// Do there eixst D messages with Data?
val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB
// Do there exist D messages without Data?
val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT
if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None
}
case _:TLBundleE => Some(false)
}
}
def isRequest(x: TLChannel): Bool = {
x match {
case a: TLBundleA => true.B
case b: TLBundleB => true.B
case c: TLBundleC => c.opcode(2) && c.opcode(1)
// opcode === TLMessages.Release ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(2) && !d.opcode(1)
// opcode === TLMessages.Grant ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
}
def isResponse(x: TLChannel): Bool = {
x match {
case a: TLBundleA => false.B
case b: TLBundleB => false.B
case c: TLBundleC => !c.opcode(2) || !c.opcode(1)
// opcode =/= TLMessages.Release &&
// opcode =/= TLMessages.ReleaseData
case d: TLBundleD => true.B // Grant isResponse + isRequest
case e: TLBundleE => true.B
}
}
def hasData(x: TLChannel): Bool = {
val opdata = x match {
case a: TLBundleA => !a.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case b: TLBundleB => !b.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case c: TLBundleC => c.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.ProbeAckData ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
staticHasData(x).map(_.B).getOrElse(opdata)
}
def opcode(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.opcode
case b: TLBundleB => b.opcode
case c: TLBundleC => c.opcode
case d: TLBundleD => d.opcode
}
}
def param(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.param
case b: TLBundleB => b.param
case c: TLBundleC => c.param
case d: TLBundleD => d.param
}
}
def size(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.size
case b: TLBundleB => b.size
case c: TLBundleC => c.size
case d: TLBundleD => d.size
}
}
def data(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.data
case b: TLBundleB => b.data
case c: TLBundleC => c.data
case d: TLBundleD => d.data
}
}
def corrupt(x: TLDataChannel): Bool = {
x match {
case a: TLBundleA => a.corrupt
case b: TLBundleB => b.corrupt
case c: TLBundleC => c.corrupt
case d: TLBundleD => d.corrupt
}
}
def mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.mask
case b: TLBundleB => b.mask
case c: TLBundleC => mask(c.address, c.size)
}
}
def full_mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => mask(a.address, a.size)
case b: TLBundleB => mask(b.address, b.size)
case c: TLBundleC => mask(c.address, c.size)
}
}
def address(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.address
case b: TLBundleB => b.address
case c: TLBundleC => c.address
}
}
def source(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.source
case b: TLBundleB => b.source
case c: TLBundleC => c.source
case d: TLBundleD => d.source
}
}
def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes)
def addr_lo(x: UInt): UInt =
if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0)
def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x))
def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x))
def numBeats(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 1.U
case bundle: TLDataChannel => {
val hasData = this.hasData(bundle)
val size = this.size(bundle)
val cutoff = log2Ceil(manager.beatBytes)
val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U
val decode = UIntToOH(size, maxLgSize+1) >> cutoff
Mux(hasData, decode | small.asUInt, 1.U)
}
}
}
def numBeats1(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 0.U
case bundle: TLDataChannel => {
if (maxLgSize == 0) {
0.U
} else {
val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes)
Mux(hasData(bundle), decode, 0.U)
}
}
}
}
def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val beats1 = numBeats1(bits)
val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W))
val counter1 = counter - 1.U
val first = counter === 0.U
val last = counter === 1.U || beats1 === 0.U
val done = last && fire
val count = (beats1 & ~counter1)
when (fire) {
counter := Mux(first, beats1, counter1)
}
(first, last, done, count)
}
def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1
def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire)
def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid)
def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2
def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire)
def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid)
def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3
def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire)
def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid)
def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3)
}
def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire)
def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid)
def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4)
}
def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire)
def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid)
def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes))
}
def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire)
def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid)
// Does the request need T permissions to be executed?
def needT(a: TLBundleA): Bool = {
val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLPermissions.NtoB -> false.B,
TLPermissions.NtoT -> true.B,
TLPermissions.BtoT -> true.B))
MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array(
TLMessages.PutFullData -> true.B,
TLMessages.PutPartialData -> true.B,
TLMessages.ArithmeticData -> true.B,
TLMessages.LogicalData -> true.B,
TLMessages.Get -> false.B,
TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLHints.PREFETCH_READ -> false.B,
TLHints.PREFETCH_WRITE -> true.B)),
TLMessages.AcquireBlock -> acq_needT,
TLMessages.AcquirePerm -> acq_needT))
}
// This is a very expensive circuit; use only if you really mean it!
def inFlight(x: TLBundle): (UInt, UInt) = {
val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W))
val bce = manager.anySupportAcquireB && client.anySupportProbe
val (a_first, a_last, _) = firstlast(x.a)
val (b_first, b_last, _) = firstlast(x.b)
val (c_first, c_last, _) = firstlast(x.c)
val (d_first, d_last, _) = firstlast(x.d)
val (e_first, e_last, _) = firstlast(x.e)
val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits))
val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits))
val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits))
val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits))
val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits))
val a_inc = x.a.fire && a_first && a_request
val b_inc = x.b.fire && b_first && b_request
val c_inc = x.c.fire && c_first && c_request
val d_inc = x.d.fire && d_first && d_request
val e_inc = x.e.fire && e_first && e_request
val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil))
val a_dec = x.a.fire && a_last && a_response
val b_dec = x.b.fire && b_last && b_response
val c_dec = x.c.fire && c_last && c_response
val d_dec = x.d.fire && d_last && d_response
val e_dec = x.e.fire && e_last && e_response
val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil))
val next_flight = flight + PopCount(inc) - PopCount(dec)
flight := next_flight
(flight, next_flight)
}
def prettySourceMapping(context: String): String = {
s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n"
}
}
class TLEdgeOut(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
// Transfers
def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquireBlock
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquirePerm
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.Release
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ReleaseData
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) =
Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B)
def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAck
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions, data)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAckData
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B)
def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink)
def GrantAck(toSink: UInt): TLBundleE = {
val e = Wire(new TLBundleE(bundle))
e.sink := toSink
e
}
// Accesses
def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsGetFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Get
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutFullFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutFullData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, mask, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutPartialFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutPartialData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = {
require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsArithmeticFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.ArithmeticData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsLogicalFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.LogicalData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = {
require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsHintFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Hint
a.param := param
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data)
def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAckData
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size)
def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.HintAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
}
class TLEdgeIn(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = {
val todo = x.filter(!_.isEmpty)
val heads = todo.map(_.head)
val tails = todo.map(_.tail)
if (todo.isEmpty) Nil else { heads +: myTranspose(tails) }
}
// Transfers
def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = {
require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}")
val legal = client.supportsProbe(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Probe
b.param := capPermissions
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.Grant
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.GrantData
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B)
def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.ReleaseAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
// Accesses
def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = {
require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsGet(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Get
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsPutFull(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutFullData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, mask, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsPutPartial(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutPartialData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsArithmetic(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.ArithmeticData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsLogical(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.LogicalData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = {
require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsHint(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Hint
b.param := param
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size)
def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied)
def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data)
def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAckData
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B)
def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied)
def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B)
def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.HintAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
}
| module TLMonitor_94( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [8:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14]
input [1:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input io_in_d_bits_source, // @[Monitor.scala:20:14]
input io_in_d_bits_sink, // @[Monitor.scala:20:14]
input io_in_d_bits_denied, // @[Monitor.scala:20:14]
input io_in_d_bits_corrupt // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire a_first_done = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35]
reg a_first_counter; // @[Edges.scala:229:27]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [8:0] address; // @[Monitor.scala:391:22]
reg d_first_counter; // @[Edges.scala:229:27]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [1:0] param_1; // @[Monitor.scala:539:22]
reg [1:0] size_1; // @[Monitor.scala:540:22]
reg source_1; // @[Monitor.scala:541:22]
reg sink; // @[Monitor.scala:542:22]
reg denied; // @[Monitor.scala:543:22]
reg [1:0] inflight; // @[Monitor.scala:614:27]
reg [3:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [3:0] inflight_sizes; // @[Monitor.scala:618:33]
reg a_first_counter_1; // @[Edges.scala:229:27]
reg d_first_counter_1; // @[Edges.scala:229:27]
wire a_set = a_first_done & ~a_first_counter_1; // @[Decoupled.scala:51:35]
wire d_release_ack = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala:673:46]
wire _GEN = io_in_d_bits_opcode != 3'h6; // @[Monitor.scala:673:46, :674:74]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
reg [1:0] inflight_1; // @[Monitor.scala:726:35]
reg [3:0] inflight_sizes_1; // @[Monitor.scala:728:35]
reg d_first_counter_2; // @[Edges.scala:229:27]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27] |
Generate the Verilog code corresponding to the following Chisel files.
File Repeater.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util.{Decoupled, DecoupledIO}
// A Repeater passes its input to its output, unless repeat is asserted.
// When repeat is asserted, the Repeater copies the input and repeats it next cycle.
class Repeater[T <: Data](gen: T) extends Module
{
override def desiredName = s"Repeater_${gen.typeName}"
val io = IO( new Bundle {
val repeat = Input(Bool())
val full = Output(Bool())
val enq = Flipped(Decoupled(gen.cloneType))
val deq = Decoupled(gen.cloneType)
} )
val full = RegInit(false.B)
val saved = Reg(gen.cloneType)
// When !full, a repeater is pass-through
io.deq.valid := io.enq.valid || full
io.enq.ready := io.deq.ready && !full
io.deq.bits := Mux(full, saved, io.enq.bits)
io.full := full
when (io.enq.fire && io.repeat) { full := true.B; saved := io.enq.bits }
when (io.deq.fire && !io.repeat) { full := false.B }
}
object Repeater
{
def apply[T <: Data](enq: DecoupledIO[T], repeat: Bool): DecoupledIO[T] = {
val repeater = Module(new Repeater(chiselTypeOf(enq.bits)))
repeater.io.repeat := repeat
repeater.io.enq <> enq
repeater.io.deq
}
}
| module Repeater_TLBundleA_a13d64s8k1z3u( // @[Repeater.scala:10:7]
input clock, // @[Repeater.scala:10:7]
input reset, // @[Repeater.scala:10:7]
input io_repeat, // @[Repeater.scala:13:14]
output io_full, // @[Repeater.scala:13:14]
output io_enq_ready, // @[Repeater.scala:13:14]
input io_enq_valid, // @[Repeater.scala:13:14]
input [2:0] io_enq_bits_opcode, // @[Repeater.scala:13:14]
input [2:0] io_enq_bits_param, // @[Repeater.scala:13:14]
input [2:0] io_enq_bits_size, // @[Repeater.scala:13:14]
input [7:0] io_enq_bits_source, // @[Repeater.scala:13:14]
input [12:0] io_enq_bits_address, // @[Repeater.scala:13:14]
input [7:0] io_enq_bits_mask, // @[Repeater.scala:13:14]
input io_enq_bits_corrupt, // @[Repeater.scala:13:14]
input io_deq_ready, // @[Repeater.scala:13:14]
output io_deq_valid, // @[Repeater.scala:13:14]
output [2:0] io_deq_bits_opcode, // @[Repeater.scala:13:14]
output [2:0] io_deq_bits_param, // @[Repeater.scala:13:14]
output [2:0] io_deq_bits_size, // @[Repeater.scala:13:14]
output [7:0] io_deq_bits_source, // @[Repeater.scala:13:14]
output [12:0] io_deq_bits_address, // @[Repeater.scala:13:14]
output [7:0] io_deq_bits_mask, // @[Repeater.scala:13:14]
output io_deq_bits_corrupt // @[Repeater.scala:13:14]
);
reg full; // @[Repeater.scala:20:21]
reg [2:0] saved_opcode; // @[Repeater.scala:21:18]
reg [2:0] saved_param; // @[Repeater.scala:21:18]
reg [2:0] saved_size; // @[Repeater.scala:21:18]
reg [7:0] saved_source; // @[Repeater.scala:21:18]
reg [12:0] saved_address; // @[Repeater.scala:21:18]
reg [7:0] saved_mask; // @[Repeater.scala:21:18]
reg saved_corrupt; // @[Repeater.scala:21:18]
wire io_deq_valid_0 = io_enq_valid | full; // @[Repeater.scala:20:21, :24:32]
wire io_enq_ready_0 = io_deq_ready & ~full; // @[Repeater.scala:20:21, :25:{32,35}]
wire _GEN = io_enq_ready_0 & io_enq_valid & io_repeat; // @[Decoupled.scala:51:35]
always @(posedge clock) begin // @[Repeater.scala:10:7]
if (reset) // @[Repeater.scala:10:7]
full <= 1'h0; // @[Repeater.scala:20:21]
else // @[Repeater.scala:10:7]
full <= ~(io_deq_ready & io_deq_valid_0 & ~io_repeat) & (_GEN | full); // @[Decoupled.scala:51:35]
if (_GEN) begin // @[Decoupled.scala:51:35]
saved_opcode <= io_enq_bits_opcode; // @[Repeater.scala:21:18]
saved_param <= io_enq_bits_param; // @[Repeater.scala:21:18]
saved_size <= io_enq_bits_size; // @[Repeater.scala:21:18]
saved_source <= io_enq_bits_source; // @[Repeater.scala:21:18]
saved_address <= io_enq_bits_address; // @[Repeater.scala:21:18]
saved_mask <= io_enq_bits_mask; // @[Repeater.scala:21:18]
saved_corrupt <= io_enq_bits_corrupt; // @[Repeater.scala:21:18]
end
always @(posedge) |
Generate the Verilog code corresponding to the following Chisel files.
File ShiftReg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
// Similar to the Chisel ShiftRegister but allows the user to suggest a
// name to the registers that get instantiated, and
// to provide a reset value.
object ShiftRegInit {
def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T =
(0 until n).foldRight(in) {
case (i, next) => {
val r = RegNext(next, init)
name.foreach { na => r.suggestName(s"${na}_${i}") }
r
}
}
}
/** These wrap behavioral
* shift registers into specific modules to allow for
* backend flows to replace or constrain
* them properly when used for CDC synchronization,
* rather than buffering.
*
* The different types vary in their reset behavior:
* AsyncResetShiftReg -- Asynchronously reset register array
* A W(width) x D(depth) sized array is constructed from D instantiations of a
* W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg,
* but only used for timing applications
*/
abstract class AbstractPipelineReg(w: Int = 1) extends Module {
val io = IO(new Bundle {
val d = Input(UInt(w.W))
val q = Output(UInt(w.W))
}
)
}
object AbstractPipelineReg {
def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = {
val chain = Module(gen)
name.foreach{ chain.suggestName(_) }
chain.io.d := in.asUInt
chain.io.q.asTypeOf(in)
}
}
class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) {
require(depth > 0, "Depth must be greater than 0.")
override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}"
val chain = List.tabulate(depth) { i =>
Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}")
}
chain.last.io.d := io.d
chain.last.io.en := true.B
(chain.init zip chain.tail).foreach { case (sink, source) =>
sink.io.d := source.io.q
sink.io.en := true.B
}
io.q := chain.head.io.q
}
object AsyncResetShiftReg {
def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T =
AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name)
def apply [T <: Data](in: T, depth: Int, name: Option[String]): T =
apply(in, depth, 0, name)
def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T =
apply(in, depth, init.litValue.toInt, name)
def apply [T <: Data](in: T, depth: Int, init: T): T =
apply (in, depth, init.litValue.toInt, None)
}
File SynchronizerReg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util.{RegEnable, Cat}
/** These wrap behavioral
* shift and next registers into specific modules to allow for
* backend flows to replace or constrain
* them properly when used for CDC synchronization,
* rather than buffering.
*
*
* These are built up of *ResetSynchronizerPrimitiveShiftReg,
* intended to be replaced by the integrator's metastable flops chains or replaced
* at this level if they have a multi-bit wide synchronizer primitive.
* The different types vary in their reset behavior:
* NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin
* AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep
* 1-bit-wide shift registers.
* SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg
*
* [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference.
*
* ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross
* Clock Domains.
*/
object SynchronizerResetType extends Enumeration {
val NonSync, Inferred, Sync, Async = Value
}
// Note: this should not be used directly.
// Use the companion object to generate this with the correct reset type mixin.
private class SynchronizerPrimitiveShiftReg(
sync: Int,
init: Boolean,
resetType: SynchronizerResetType.Value)
extends AbstractPipelineReg(1) {
val initInt = if (init) 1 else 0
val initPostfix = resetType match {
case SynchronizerResetType.NonSync => ""
case _ => s"_i${initInt}"
}
override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}"
val chain = List.tabulate(sync) { i =>
val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B)
reg.suggestName(s"sync_$i")
}
chain.last := io.d.asBool
(chain.init zip chain.tail).foreach { case (sink, source) =>
sink := source
}
io.q := chain.head.asUInt
}
private object SynchronizerPrimitiveShiftReg {
def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = {
val gen: () => SynchronizerPrimitiveShiftReg = resetType match {
case SynchronizerResetType.NonSync =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType)
case SynchronizerResetType.Async =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset
case SynchronizerResetType.Sync =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset
case SynchronizerResetType.Inferred =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType)
}
AbstractPipelineReg(gen(), in)
}
}
// Note: This module may end up with a non-AsyncReset type reset.
// But the Primitives within will always have AsyncReset type.
class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int)
extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
withReset(reset.asAsyncReset){
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async)
}
}
io.q := Cat(output.reverse)
}
object AsyncResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
// Note: This module may end up with a non-Bool type reset.
// But the Primitives within will always have Bool reset type.
@deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2")
class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
withReset(reset.asBool){
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync)
}
}
io.q := Cat(output.reverse)
}
object SyncResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred)
}
io.q := Cat(output.reverse)
}
object ResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}"
val output = Seq.tabulate(w) { i =>
SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync)
}
io.q := Cat(output.reverse)
}
object SynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T =
if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, None)
def apply [T <: Data](in: T): T =
apply (in, 3, None)
}
class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module {
override def desiredName = s"ClockCrossingReg_w${w}"
val io = IO(new Bundle{
val d = Input(UInt(w.W))
val q = Output(UInt(w.W))
val en = Input(Bool())
})
val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en)
io.q := cdc_reg
}
object ClockCrossingReg {
def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = {
val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit))
name.foreach{ cdc_reg.suggestName(_) }
cdc_reg.io.d := in.asUInt
cdc_reg.io.en := en
cdc_reg.io.q.asTypeOf(in)
}
}
| module AsyncResetSynchronizerShiftReg_w1_d3_i0_20( // @[SynchronizerReg.scala:80:7]
input clock, // @[SynchronizerReg.scala:80:7]
input reset, // @[SynchronizerReg.scala:80:7]
input io_d, // @[ShiftReg.scala:36:14]
output io_q // @[ShiftReg.scala:36:14]
);
wire io_d_0 = io_d; // @[SynchronizerReg.scala:80:7]
wire _output_T = reset; // @[SynchronizerReg.scala:86:21]
wire _output_T_1 = io_d_0; // @[SynchronizerReg.scala:80:7, :87:41]
wire output_0; // @[ShiftReg.scala:48:24]
wire io_q_0; // @[SynchronizerReg.scala:80:7]
assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7]
AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_20 output_chain ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (_output_T), // @[SynchronizerReg.scala:86:21]
.io_d (_output_T_1), // @[SynchronizerReg.scala:87:41]
.io_q (output_0)
); // @[ShiftReg.scala:45:23]
assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File ShiftReg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
// Similar to the Chisel ShiftRegister but allows the user to suggest a
// name to the registers that get instantiated, and
// to provide a reset value.
object ShiftRegInit {
def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T =
(0 until n).foldRight(in) {
case (i, next) => {
val r = RegNext(next, init)
name.foreach { na => r.suggestName(s"${na}_${i}") }
r
}
}
}
/** These wrap behavioral
* shift registers into specific modules to allow for
* backend flows to replace or constrain
* them properly when used for CDC synchronization,
* rather than buffering.
*
* The different types vary in their reset behavior:
* AsyncResetShiftReg -- Asynchronously reset register array
* A W(width) x D(depth) sized array is constructed from D instantiations of a
* W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg,
* but only used for timing applications
*/
abstract class AbstractPipelineReg(w: Int = 1) extends Module {
val io = IO(new Bundle {
val d = Input(UInt(w.W))
val q = Output(UInt(w.W))
}
)
}
object AbstractPipelineReg {
def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = {
val chain = Module(gen)
name.foreach{ chain.suggestName(_) }
chain.io.d := in.asUInt
chain.io.q.asTypeOf(in)
}
}
class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) {
require(depth > 0, "Depth must be greater than 0.")
override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}"
val chain = List.tabulate(depth) { i =>
Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}")
}
chain.last.io.d := io.d
chain.last.io.en := true.B
(chain.init zip chain.tail).foreach { case (sink, source) =>
sink.io.d := source.io.q
sink.io.en := true.B
}
io.q := chain.head.io.q
}
object AsyncResetShiftReg {
def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T =
AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name)
def apply [T <: Data](in: T, depth: Int, name: Option[String]): T =
apply(in, depth, 0, name)
def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T =
apply(in, depth, init.litValue.toInt, name)
def apply [T <: Data](in: T, depth: Int, init: T): T =
apply (in, depth, init.litValue.toInt, None)
}
File SynchronizerReg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util.{RegEnable, Cat}
/** These wrap behavioral
* shift and next registers into specific modules to allow for
* backend flows to replace or constrain
* them properly when used for CDC synchronization,
* rather than buffering.
*
*
* These are built up of *ResetSynchronizerPrimitiveShiftReg,
* intended to be replaced by the integrator's metastable flops chains or replaced
* at this level if they have a multi-bit wide synchronizer primitive.
* The different types vary in their reset behavior:
* NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin
* AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep
* 1-bit-wide shift registers.
* SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg
*
* [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference.
*
* ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross
* Clock Domains.
*/
object SynchronizerResetType extends Enumeration {
val NonSync, Inferred, Sync, Async = Value
}
// Note: this should not be used directly.
// Use the companion object to generate this with the correct reset type mixin.
private class SynchronizerPrimitiveShiftReg(
sync: Int,
init: Boolean,
resetType: SynchronizerResetType.Value)
extends AbstractPipelineReg(1) {
val initInt = if (init) 1 else 0
val initPostfix = resetType match {
case SynchronizerResetType.NonSync => ""
case _ => s"_i${initInt}"
}
override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}"
val chain = List.tabulate(sync) { i =>
val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B)
reg.suggestName(s"sync_$i")
}
chain.last := io.d.asBool
(chain.init zip chain.tail).foreach { case (sink, source) =>
sink := source
}
io.q := chain.head.asUInt
}
private object SynchronizerPrimitiveShiftReg {
def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = {
val gen: () => SynchronizerPrimitiveShiftReg = resetType match {
case SynchronizerResetType.NonSync =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType)
case SynchronizerResetType.Async =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset
case SynchronizerResetType.Sync =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset
case SynchronizerResetType.Inferred =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType)
}
AbstractPipelineReg(gen(), in)
}
}
// Note: This module may end up with a non-AsyncReset type reset.
// But the Primitives within will always have AsyncReset type.
class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int)
extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
withReset(reset.asAsyncReset){
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async)
}
}
io.q := Cat(output.reverse)
}
object AsyncResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
// Note: This module may end up with a non-Bool type reset.
// But the Primitives within will always have Bool reset type.
@deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2")
class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
withReset(reset.asBool){
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync)
}
}
io.q := Cat(output.reverse)
}
object SyncResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred)
}
io.q := Cat(output.reverse)
}
object ResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}"
val output = Seq.tabulate(w) { i =>
SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync)
}
io.q := Cat(output.reverse)
}
object SynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T =
if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, None)
def apply [T <: Data](in: T): T =
apply (in, 3, None)
}
class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module {
override def desiredName = s"ClockCrossingReg_w${w}"
val io = IO(new Bundle{
val d = Input(UInt(w.W))
val q = Output(UInt(w.W))
val en = Input(Bool())
})
val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en)
io.q := cdc_reg
}
object ClockCrossingReg {
def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = {
val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit))
name.foreach{ cdc_reg.suggestName(_) }
cdc_reg.io.d := in.asUInt
cdc_reg.io.en := en
cdc_reg.io.q.asTypeOf(in)
}
}
| module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_485( // @[SynchronizerReg.scala:68:19]
input clock, // @[SynchronizerReg.scala:68:19]
input reset, // @[SynchronizerReg.scala:68:19]
output io_q // @[ShiftReg.scala:36:14]
);
wire io_d = 1'h1; // @[SynchronizerReg.scala:54:22, :68:19]
wire _sync_2_T = 1'h1; // @[SynchronizerReg.scala:54:22, :68:19]
wire io_q_0; // @[SynchronizerReg.scala:68:19]
reg sync_0; // @[SynchronizerReg.scala:51:87]
assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19]
reg sync_1; // @[SynchronizerReg.scala:51:87]
reg sync_2; // @[SynchronizerReg.scala:51:87]
always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19]
if (reset) begin // @[SynchronizerReg.scala:68:19]
sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87]
sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87]
sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87]
end
else begin // @[SynchronizerReg.scala:68:19]
sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87]
sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87]
sync_2 <= 1'h1; // @[SynchronizerReg.scala:51:87, :54:22, :68:19]
end
always @(posedge, posedge) |
Generate the Verilog code corresponding to the following Chisel files.
File PE.scala:
// See README.md for license details.
package gemmini
import chisel3._
import chisel3.util._
class PEControl[T <: Data : Arithmetic](accType: T) extends Bundle {
val dataflow = UInt(1.W) // TODO make this an Enum
val propagate = UInt(1.W) // Which register should be propagated (and which should be accumulated)?
val shift = UInt(log2Up(accType.getWidth).W) // TODO this isn't correct for Floats
}
class MacUnit[T <: Data](inputType: T, cType: T, dType: T) (implicit ev: Arithmetic[T]) extends Module {
import ev._
val io = IO(new Bundle {
val in_a = Input(inputType)
val in_b = Input(inputType)
val in_c = Input(cType)
val out_d = Output(dType)
})
io.out_d := io.in_c.mac(io.in_a, io.in_b)
}
// TODO update documentation
/**
* A PE implementing a MAC operation. Configured as fully combinational when integrated into a Mesh.
* @param width Data width of operands
*/
class PE[T <: Data](inputType: T, outputType: T, accType: T, df: Dataflow.Value, max_simultaneous_matmuls: Int)
(implicit ev: Arithmetic[T]) extends Module { // Debugging variables
import ev._
val io = IO(new Bundle {
val in_a = Input(inputType)
val in_b = Input(outputType)
val in_d = Input(outputType)
val out_a = Output(inputType)
val out_b = Output(outputType)
val out_c = Output(outputType)
val in_control = Input(new PEControl(accType))
val out_control = Output(new PEControl(accType))
val in_id = Input(UInt(log2Up(max_simultaneous_matmuls).W))
val out_id = Output(UInt(log2Up(max_simultaneous_matmuls).W))
val in_last = Input(Bool())
val out_last = Output(Bool())
val in_valid = Input(Bool())
val out_valid = Output(Bool())
val bad_dataflow = Output(Bool())
})
val cType = if (df == Dataflow.WS) inputType else accType
// When creating PEs that support multiple dataflows, the
// elaboration/synthesis tools often fail to consolidate and de-duplicate
// MAC units. To force mac circuitry to be re-used, we create a "mac_unit"
// module here which just performs a single MAC operation
val mac_unit = Module(new MacUnit(inputType,
if (df == Dataflow.WS) outputType else accType, outputType))
val a = io.in_a
val b = io.in_b
val d = io.in_d
val c1 = Reg(cType)
val c2 = Reg(cType)
val dataflow = io.in_control.dataflow
val prop = io.in_control.propagate
val shift = io.in_control.shift
val id = io.in_id
val last = io.in_last
val valid = io.in_valid
io.out_a := a
io.out_control.dataflow := dataflow
io.out_control.propagate := prop
io.out_control.shift := shift
io.out_id := id
io.out_last := last
io.out_valid := valid
mac_unit.io.in_a := a
val last_s = RegEnable(prop, valid)
val flip = last_s =/= prop
val shift_offset = Mux(flip, shift, 0.U)
// Which dataflow are we using?
val OUTPUT_STATIONARY = Dataflow.OS.id.U(1.W)
val WEIGHT_STATIONARY = Dataflow.WS.id.U(1.W)
// Is c1 being computed on, or propagated forward (in the output-stationary dataflow)?
val COMPUTE = 0.U(1.W)
val PROPAGATE = 1.U(1.W)
io.bad_dataflow := false.B
when ((df == Dataflow.OS).B || ((df == Dataflow.BOTH).B && dataflow === OUTPUT_STATIONARY)) {
when(prop === PROPAGATE) {
io.out_c := (c1 >> shift_offset).clippedToWidthOf(outputType)
io.out_b := b
mac_unit.io.in_b := b.asTypeOf(inputType)
mac_unit.io.in_c := c2
c2 := mac_unit.io.out_d
c1 := d.withWidthOf(cType)
}.otherwise {
io.out_c := (c2 >> shift_offset).clippedToWidthOf(outputType)
io.out_b := b
mac_unit.io.in_b := b.asTypeOf(inputType)
mac_unit.io.in_c := c1
c1 := mac_unit.io.out_d
c2 := d.withWidthOf(cType)
}
}.elsewhen ((df == Dataflow.WS).B || ((df == Dataflow.BOTH).B && dataflow === WEIGHT_STATIONARY)) {
when(prop === PROPAGATE) {
io.out_c := c1
mac_unit.io.in_b := c2.asTypeOf(inputType)
mac_unit.io.in_c := b
io.out_b := mac_unit.io.out_d
c1 := d
}.otherwise {
io.out_c := c2
mac_unit.io.in_b := c1.asTypeOf(inputType)
mac_unit.io.in_c := b
io.out_b := mac_unit.io.out_d
c2 := d
}
}.otherwise {
io.bad_dataflow := true.B
//assert(false.B, "unknown dataflow")
io.out_c := DontCare
io.out_b := DontCare
mac_unit.io.in_b := b.asTypeOf(inputType)
mac_unit.io.in_c := c2
}
when (!valid) {
c1 := c1
c2 := c2
mac_unit.io.in_b := DontCare
mac_unit.io.in_c := DontCare
}
}
File Arithmetic.scala:
// A simple type class for Chisel datatypes that can add and multiply. To add your own type, simply create your own:
// implicit MyTypeArithmetic extends Arithmetic[MyType] { ... }
package gemmini
import chisel3._
import chisel3.util._
import hardfloat._
// Bundles that represent the raw bits of custom datatypes
case class Float(expWidth: Int, sigWidth: Int) extends Bundle {
val bits = UInt((expWidth + sigWidth).W)
val bias: Int = (1 << (expWidth-1)) - 1
}
case class DummySInt(w: Int) extends Bundle {
val bits = UInt(w.W)
def dontCare: DummySInt = {
val o = Wire(new DummySInt(w))
o.bits := 0.U
o
}
}
// The Arithmetic typeclass which implements various arithmetic operations on custom datatypes
abstract class Arithmetic[T <: Data] {
implicit def cast(t: T): ArithmeticOps[T]
}
abstract class ArithmeticOps[T <: Data](self: T) {
def *(t: T): T
def mac(m1: T, m2: T): T // Returns (m1 * m2 + self)
def +(t: T): T
def -(t: T): T
def >>(u: UInt): T // This is a rounding shift! Rounds away from 0
def >(t: T): Bool
def identity: T
def withWidthOf(t: T): T
def clippedToWidthOf(t: T): T // Like "withWidthOf", except that it saturates
def relu: T
def zero: T
def minimum: T
// Optional parameters, which only need to be defined if you want to enable various optimizations for transformers
def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[T])] = None
def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[T])] = None
def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = None
def mult_with_reciprocal[U <: Data](reciprocal: U) = self
}
object Arithmetic {
implicit object UIntArithmetic extends Arithmetic[UInt] {
override implicit def cast(self: UInt) = new ArithmeticOps(self) {
override def *(t: UInt) = self * t
override def mac(m1: UInt, m2: UInt) = m1 * m2 + self
override def +(t: UInt) = self + t
override def -(t: UInt) = self - t
override def >>(u: UInt) = {
// The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm
// TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here?
val point_five = Mux(u === 0.U, 0.U, self(u - 1.U))
val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U
val ones_digit = self(u)
val r = point_five & (zeros | ones_digit)
(self >> u).asUInt + r
}
override def >(t: UInt): Bool = self > t
override def withWidthOf(t: UInt) = self.asTypeOf(t)
override def clippedToWidthOf(t: UInt) = {
val sat = ((1 << (t.getWidth-1))-1).U
Mux(self > sat, sat, self)(t.getWidth-1, 0)
}
override def relu: UInt = self
override def zero: UInt = 0.U
override def identity: UInt = 1.U
override def minimum: UInt = 0.U
}
}
implicit object SIntArithmetic extends Arithmetic[SInt] {
override implicit def cast(self: SInt) = new ArithmeticOps(self) {
override def *(t: SInt) = self * t
override def mac(m1: SInt, m2: SInt) = m1 * m2 + self
override def +(t: SInt) = self + t
override def -(t: SInt) = self - t
override def >>(u: UInt) = {
// The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm
// TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here?
val point_five = Mux(u === 0.U, 0.U, self(u - 1.U))
val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U
val ones_digit = self(u)
val r = (point_five & (zeros | ones_digit)).asBool
(self >> u).asSInt + Mux(r, 1.S, 0.S)
}
override def >(t: SInt): Bool = self > t
override def withWidthOf(t: SInt) = {
if (self.getWidth >= t.getWidth)
self(t.getWidth-1, 0).asSInt
else {
val sign_bits = t.getWidth - self.getWidth
val sign = self(self.getWidth-1)
Cat(Cat(Seq.fill(sign_bits)(sign)), self).asTypeOf(t)
}
}
override def clippedToWidthOf(t: SInt): SInt = {
val maxsat = ((1 << (t.getWidth-1))-1).S
val minsat = (-(1 << (t.getWidth-1))).S
MuxCase(self, Seq((self > maxsat) -> maxsat, (self < minsat) -> minsat))(t.getWidth-1, 0).asSInt
}
override def relu: SInt = Mux(self >= 0.S, self, 0.S)
override def zero: SInt = 0.S
override def identity: SInt = 1.S
override def minimum: SInt = (-(1 << (self.getWidth-1))).S
override def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = {
// TODO this uses a floating point divider, but we should use an integer divider instead
val input = Wire(Decoupled(denom_t.cloneType))
val output = Wire(Decoupled(self.cloneType))
// We translate our integer to floating-point form so that we can use the hardfloat divider
val expWidth = log2Up(self.getWidth) + 1
val sigWidth = self.getWidth
def sin_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def uin_to_float(x: UInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := false.B
in_to_rec_fn.io.in := x
in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def float_to_in(x: UInt) = {
val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth))
rec_fn_to_in.io.signedOut := true.B
rec_fn_to_in.io.in := x
rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
rec_fn_to_in.io.out.asSInt
}
val self_rec = sin_to_float(self)
val denom_rec = uin_to_float(input.bits)
// Instantiate the hardloat divider
val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options))
input.ready := divider.io.inReady
divider.io.inValid := input.valid
divider.io.sqrtOp := false.B
divider.io.a := self_rec
divider.io.b := denom_rec
divider.io.roundingMode := consts.round_minMag
divider.io.detectTininess := consts.tininess_afterRounding
output.valid := divider.io.outValid_div
output.bits := float_to_in(divider.io.out)
assert(!output.valid || output.ready)
Some((input, output))
}
override def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = {
// TODO this uses a floating point divider, but we should use an integer divider instead
val input = Wire(Decoupled(UInt(0.W)))
val output = Wire(Decoupled(self.cloneType))
input.bits := DontCare
// We translate our integer to floating-point form so that we can use the hardfloat divider
val expWidth = log2Up(self.getWidth) + 1
val sigWidth = self.getWidth
def in_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def float_to_in(x: UInt) = {
val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth))
rec_fn_to_in.io.signedOut := true.B
rec_fn_to_in.io.in := x
rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
rec_fn_to_in.io.out.asSInt
}
val self_rec = in_to_float(self)
// Instantiate the hardloat sqrt
val sqrter = Module(new DivSqrtRecFN_small(expWidth, sigWidth, 0))
input.ready := sqrter.io.inReady
sqrter.io.inValid := input.valid
sqrter.io.sqrtOp := true.B
sqrter.io.a := self_rec
sqrter.io.b := DontCare
sqrter.io.roundingMode := consts.round_minMag
sqrter.io.detectTininess := consts.tininess_afterRounding
output.valid := sqrter.io.outValid_sqrt
output.bits := float_to_in(sqrter.io.out)
assert(!output.valid || output.ready)
Some((input, output))
}
override def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = u match {
case Float(expWidth, sigWidth) =>
val input = Wire(Decoupled(UInt(0.W)))
val output = Wire(Decoupled(u.cloneType))
input.bits := DontCare
// We translate our integer to floating-point form so that we can use the hardfloat divider
def in_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
val self_rec = in_to_float(self)
val one_rec = in_to_float(1.S)
// Instantiate the hardloat divider
val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options))
input.ready := divider.io.inReady
divider.io.inValid := input.valid
divider.io.sqrtOp := false.B
divider.io.a := one_rec
divider.io.b := self_rec
divider.io.roundingMode := consts.round_near_even
divider.io.detectTininess := consts.tininess_afterRounding
output.valid := divider.io.outValid_div
output.bits := fNFromRecFN(expWidth, sigWidth, divider.io.out).asTypeOf(u)
assert(!output.valid || output.ready)
Some((input, output))
case _ => None
}
override def mult_with_reciprocal[U <: Data](reciprocal: U): SInt = reciprocal match {
case recip @ Float(expWidth, sigWidth) =>
def in_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def float_to_in(x: UInt) = {
val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth))
rec_fn_to_in.io.signedOut := true.B
rec_fn_to_in.io.in := x
rec_fn_to_in.io.roundingMode := consts.round_minMag
rec_fn_to_in.io.out.asSInt
}
val self_rec = in_to_float(self)
val reciprocal_rec = recFNFromFN(expWidth, sigWidth, recip.bits)
// Instantiate the hardloat divider
val muladder = Module(new MulRecFN(expWidth, sigWidth))
muladder.io.roundingMode := consts.round_near_even
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := self_rec
muladder.io.b := reciprocal_rec
float_to_in(muladder.io.out)
case _ => self
}
}
}
implicit object FloatArithmetic extends Arithmetic[Float] {
// TODO Floating point arithmetic currently switches between recoded and standard formats for every operation. However, it should stay in the recoded format as it travels through the systolic array
override implicit def cast(self: Float): ArithmeticOps[Float] = new ArithmeticOps(self) {
override def *(t: Float): Float = {
val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth))
t_resizer.io.in := t_rec
t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
t_resizer.io.detectTininess := consts.tininess_afterRounding
val t_rec_resized = t_resizer.io.out
val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth))
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := self_rec
muladder.io.b := t_rec_resized
val out = Wire(Float(self.expWidth, self.sigWidth))
out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
out
}
override def mac(m1: Float, m2: Float): Float = {
// Recode all operands
val m1_rec = recFNFromFN(m1.expWidth, m1.sigWidth, m1.bits)
val m2_rec = recFNFromFN(m2.expWidth, m2.sigWidth, m2.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Resize m1 to self's width
val m1_resizer = Module(new RecFNToRecFN(m1.expWidth, m1.sigWidth, self.expWidth, self.sigWidth))
m1_resizer.io.in := m1_rec
m1_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
m1_resizer.io.detectTininess := consts.tininess_afterRounding
val m1_rec_resized = m1_resizer.io.out
// Resize m2 to self's width
val m2_resizer = Module(new RecFNToRecFN(m2.expWidth, m2.sigWidth, self.expWidth, self.sigWidth))
m2_resizer.io.in := m2_rec
m2_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
m2_resizer.io.detectTininess := consts.tininess_afterRounding
val m2_rec_resized = m2_resizer.io.out
// Perform multiply-add
val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth))
muladder.io.op := 0.U
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := m1_rec_resized
muladder.io.b := m2_rec_resized
muladder.io.c := self_rec
// Convert result to standard format // TODO remove these intermediate recodings
val out = Wire(Float(self.expWidth, self.sigWidth))
out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
out
}
override def +(t: Float): Float = {
require(self.getWidth >= t.getWidth) // This just makes it easier to write the resizing code
// Recode all operands
val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Generate 1 as a float
val in_to_rec_fn = Module(new INToRecFN(1, self.expWidth, self.sigWidth))
in_to_rec_fn.io.signedIn := false.B
in_to_rec_fn.io.in := 1.U
in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
val one_rec = in_to_rec_fn.io.out
// Resize t
val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth))
t_resizer.io.in := t_rec
t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
t_resizer.io.detectTininess := consts.tininess_afterRounding
val t_rec_resized = t_resizer.io.out
// Perform addition
val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth))
muladder.io.op := 0.U
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := t_rec_resized
muladder.io.b := one_rec
muladder.io.c := self_rec
val result = Wire(Float(self.expWidth, self.sigWidth))
result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
result
}
override def -(t: Float): Float = {
val t_sgn = t.bits(t.getWidth-1)
val neg_t = Cat(~t_sgn, t.bits(t.getWidth-2,0)).asTypeOf(t)
self + neg_t
}
override def >>(u: UInt): Float = {
// Recode self
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Get 2^(-u) as a recoded float
val shift_exp = Wire(UInt(self.expWidth.W))
shift_exp := self.bias.U - u
val shift_fn = Cat(0.U(1.W), shift_exp, 0.U((self.sigWidth-1).W))
val shift_rec = recFNFromFN(self.expWidth, self.sigWidth, shift_fn)
assert(shift_exp =/= 0.U, "scaling by denormalized numbers is not currently supported")
// Multiply self and 2^(-u)
val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth))
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := self_rec
muladder.io.b := shift_rec
val result = Wire(Float(self.expWidth, self.sigWidth))
result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
result
}
override def >(t: Float): Bool = {
// Recode all operands
val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Resize t to self's width
val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth))
t_resizer.io.in := t_rec
t_resizer.io.roundingMode := consts.round_near_even
t_resizer.io.detectTininess := consts.tininess_afterRounding
val t_rec_resized = t_resizer.io.out
val comparator = Module(new CompareRecFN(self.expWidth, self.sigWidth))
comparator.io.a := self_rec
comparator.io.b := t_rec_resized
comparator.io.signaling := false.B
comparator.io.gt
}
override def withWidthOf(t: Float): Float = {
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth))
resizer.io.in := self_rec
resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
resizer.io.detectTininess := consts.tininess_afterRounding
val result = Wire(Float(t.expWidth, t.sigWidth))
result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out)
result
}
override def clippedToWidthOf(t: Float): Float = {
// TODO check for overflow. Right now, we just assume that overflow doesn't happen
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth))
resizer.io.in := self_rec
resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
resizer.io.detectTininess := consts.tininess_afterRounding
val result = Wire(Float(t.expWidth, t.sigWidth))
result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out)
result
}
override def relu: Float = {
val raw = rawFloatFromFN(self.expWidth, self.sigWidth, self.bits)
val result = Wire(Float(self.expWidth, self.sigWidth))
result.bits := Mux(!raw.isZero && raw.sign, 0.U, self.bits)
result
}
override def zero: Float = 0.U.asTypeOf(self)
override def identity: Float = Cat(0.U(2.W), ~(0.U((self.expWidth-1).W)), 0.U((self.sigWidth-1).W)).asTypeOf(self)
override def minimum: Float = Cat(1.U, ~(0.U(self.expWidth.W)), 0.U((self.sigWidth-1).W)).asTypeOf(self)
}
}
implicit object DummySIntArithmetic extends Arithmetic[DummySInt] {
override implicit def cast(self: DummySInt) = new ArithmeticOps(self) {
override def *(t: DummySInt) = self.dontCare
override def mac(m1: DummySInt, m2: DummySInt) = self.dontCare
override def +(t: DummySInt) = self.dontCare
override def -(t: DummySInt) = self.dontCare
override def >>(t: UInt) = self.dontCare
override def >(t: DummySInt): Bool = false.B
override def identity = self.dontCare
override def withWidthOf(t: DummySInt) = self.dontCare
override def clippedToWidthOf(t: DummySInt) = self.dontCare
override def relu = self.dontCare
override def zero = self.dontCare
override def minimum: DummySInt = self.dontCare
}
}
}
| module PE_375( // @[PE.scala:31:7]
input clock, // @[PE.scala:31:7]
input reset, // @[PE.scala:31:7]
input [7:0] io_in_a, // @[PE.scala:35:14]
input [19:0] io_in_b, // @[PE.scala:35:14]
input [19:0] io_in_d, // @[PE.scala:35:14]
output [7:0] io_out_a, // @[PE.scala:35:14]
output [19:0] io_out_b, // @[PE.scala:35:14]
output [19:0] io_out_c, // @[PE.scala:35:14]
input io_in_control_dataflow, // @[PE.scala:35:14]
input io_in_control_propagate, // @[PE.scala:35:14]
input [4:0] io_in_control_shift, // @[PE.scala:35:14]
output io_out_control_dataflow, // @[PE.scala:35:14]
output io_out_control_propagate, // @[PE.scala:35:14]
output [4:0] io_out_control_shift, // @[PE.scala:35:14]
input [2:0] io_in_id, // @[PE.scala:35:14]
output [2:0] io_out_id, // @[PE.scala:35:14]
input io_in_last, // @[PE.scala:35:14]
output io_out_last, // @[PE.scala:35:14]
input io_in_valid, // @[PE.scala:35:14]
output io_out_valid // @[PE.scala:35:14]
);
wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:31:7]
wire [19:0] io_in_b_0 = io_in_b; // @[PE.scala:31:7]
wire [19:0] io_in_d_0 = io_in_d; // @[PE.scala:31:7]
wire io_in_control_dataflow_0 = io_in_control_dataflow; // @[PE.scala:31:7]
wire io_in_control_propagate_0 = io_in_control_propagate; // @[PE.scala:31:7]
wire [4:0] io_in_control_shift_0 = io_in_control_shift; // @[PE.scala:31:7]
wire [2:0] io_in_id_0 = io_in_id; // @[PE.scala:31:7]
wire io_in_last_0 = io_in_last; // @[PE.scala:31:7]
wire io_in_valid_0 = io_in_valid; // @[PE.scala:31:7]
wire io_bad_dataflow = 1'h0; // @[PE.scala:31:7]
wire _io_out_c_T_5 = 1'h0; // @[Arithmetic.scala:125:33]
wire _io_out_c_T_6 = 1'h0; // @[Arithmetic.scala:125:60]
wire _io_out_c_T_16 = 1'h0; // @[Arithmetic.scala:125:33]
wire _io_out_c_T_17 = 1'h0; // @[Arithmetic.scala:125:60]
wire [7:0] io_out_a_0 = io_in_a_0; // @[PE.scala:31:7]
wire [19:0] _mac_unit_io_in_b_T = io_in_b_0; // @[PE.scala:31:7, :106:37]
wire [19:0] _mac_unit_io_in_b_T_2 = io_in_b_0; // @[PE.scala:31:7, :113:37]
wire [19:0] _mac_unit_io_in_b_T_8 = io_in_b_0; // @[PE.scala:31:7, :137:35]
wire io_out_control_dataflow_0 = io_in_control_dataflow_0; // @[PE.scala:31:7]
wire io_out_control_propagate_0 = io_in_control_propagate_0; // @[PE.scala:31:7]
wire [4:0] io_out_control_shift_0 = io_in_control_shift_0; // @[PE.scala:31:7]
wire [2:0] io_out_id_0 = io_in_id_0; // @[PE.scala:31:7]
wire io_out_last_0 = io_in_last_0; // @[PE.scala:31:7]
wire io_out_valid_0 = io_in_valid_0; // @[PE.scala:31:7]
wire [19:0] io_out_b_0; // @[PE.scala:31:7]
wire [19:0] io_out_c_0; // @[PE.scala:31:7]
reg [7:0] c1; // @[PE.scala:70:15]
wire [7:0] _io_out_c_zeros_T_1 = c1; // @[PE.scala:70:15]
wire [7:0] _mac_unit_io_in_b_T_6 = c1; // @[PE.scala:70:15, :127:38]
reg [7:0] c2; // @[PE.scala:71:15]
wire [7:0] _io_out_c_zeros_T_10 = c2; // @[PE.scala:71:15]
wire [7:0] _mac_unit_io_in_b_T_4 = c2; // @[PE.scala:71:15, :121:38]
reg last_s; // @[PE.scala:89:25]
wire flip = last_s != io_in_control_propagate_0; // @[PE.scala:31:7, :89:25, :90:21]
wire [4:0] shift_offset = flip ? io_in_control_shift_0 : 5'h0; // @[PE.scala:31:7, :90:21, :91:25]
wire _GEN = shift_offset == 5'h0; // @[PE.scala:91:25]
wire _io_out_c_point_five_T; // @[Arithmetic.scala:101:32]
assign _io_out_c_point_five_T = _GEN; // @[Arithmetic.scala:101:32]
wire _io_out_c_point_five_T_5; // @[Arithmetic.scala:101:32]
assign _io_out_c_point_five_T_5 = _GEN; // @[Arithmetic.scala:101:32]
wire [5:0] _GEN_0 = {1'h0, shift_offset} - 6'h1; // @[PE.scala:91:25]
wire [5:0] _io_out_c_point_five_T_1; // @[Arithmetic.scala:101:53]
assign _io_out_c_point_five_T_1 = _GEN_0; // @[Arithmetic.scala:101:53]
wire [5:0] _io_out_c_zeros_T_2; // @[Arithmetic.scala:102:66]
assign _io_out_c_zeros_T_2 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66]
wire [5:0] _io_out_c_point_five_T_6; // @[Arithmetic.scala:101:53]
assign _io_out_c_point_five_T_6 = _GEN_0; // @[Arithmetic.scala:101:53]
wire [5:0] _io_out_c_zeros_T_11; // @[Arithmetic.scala:102:66]
assign _io_out_c_zeros_T_11 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66]
wire [4:0] _io_out_c_point_five_T_2 = _io_out_c_point_five_T_1[4:0]; // @[Arithmetic.scala:101:53]
wire [7:0] _io_out_c_point_five_T_3 = $signed($signed(c1) >>> _io_out_c_point_five_T_2); // @[PE.scala:70:15]
wire _io_out_c_point_five_T_4 = _io_out_c_point_five_T_3[0]; // @[Arithmetic.scala:101:50]
wire io_out_c_point_five = ~_io_out_c_point_five_T & _io_out_c_point_five_T_4; // @[Arithmetic.scala:101:{29,32,50}]
wire _GEN_1 = shift_offset < 5'h2; // @[PE.scala:91:25]
wire _io_out_c_zeros_T; // @[Arithmetic.scala:102:27]
assign _io_out_c_zeros_T = _GEN_1; // @[Arithmetic.scala:102:27]
wire _io_out_c_zeros_T_9; // @[Arithmetic.scala:102:27]
assign _io_out_c_zeros_T_9 = _GEN_1; // @[Arithmetic.scala:102:27]
wire [4:0] _io_out_c_zeros_T_3 = _io_out_c_zeros_T_2[4:0]; // @[Arithmetic.scala:102:66]
wire [31:0] _io_out_c_zeros_T_4 = 32'h1 << _io_out_c_zeros_T_3; // @[Arithmetic.scala:102:{60,66}]
wire [32:0] _io_out_c_zeros_T_5 = {1'h0, _io_out_c_zeros_T_4} - 33'h1; // @[Arithmetic.scala:102:{60,81}]
wire [31:0] _io_out_c_zeros_T_6 = _io_out_c_zeros_T_5[31:0]; // @[Arithmetic.scala:102:81]
wire [31:0] _io_out_c_zeros_T_7 = {24'h0, _io_out_c_zeros_T_6[7:0] & _io_out_c_zeros_T_1}; // @[Arithmetic.scala:102:{45,52,81}]
wire [31:0] _io_out_c_zeros_T_8 = _io_out_c_zeros_T ? 32'h0 : _io_out_c_zeros_T_7; // @[Arithmetic.scala:102:{24,27,52}]
wire io_out_c_zeros = |_io_out_c_zeros_T_8; // @[Arithmetic.scala:102:{24,89}]
wire [7:0] _GEN_2 = {3'h0, shift_offset}; // @[PE.scala:91:25]
wire [7:0] _GEN_3 = $signed($signed(c1) >>> _GEN_2); // @[PE.scala:70:15]
wire [7:0] _io_out_c_ones_digit_T; // @[Arithmetic.scala:103:30]
assign _io_out_c_ones_digit_T = _GEN_3; // @[Arithmetic.scala:103:30]
wire [7:0] _io_out_c_T; // @[Arithmetic.scala:107:15]
assign _io_out_c_T = _GEN_3; // @[Arithmetic.scala:103:30, :107:15]
wire io_out_c_ones_digit = _io_out_c_ones_digit_T[0]; // @[Arithmetic.scala:103:30]
wire _io_out_c_r_T = io_out_c_zeros | io_out_c_ones_digit; // @[Arithmetic.scala:102:89, :103:30, :105:38]
wire _io_out_c_r_T_1 = io_out_c_point_five & _io_out_c_r_T; // @[Arithmetic.scala:101:29, :105:{29,38}]
wire io_out_c_r = _io_out_c_r_T_1; // @[Arithmetic.scala:105:{29,53}]
wire [1:0] _io_out_c_T_1 = {1'h0, io_out_c_r}; // @[Arithmetic.scala:105:53, :107:33]
wire [8:0] _io_out_c_T_2 = {_io_out_c_T[7], _io_out_c_T} + {{7{_io_out_c_T_1[1]}}, _io_out_c_T_1}; // @[Arithmetic.scala:107:{15,28,33}]
wire [7:0] _io_out_c_T_3 = _io_out_c_T_2[7:0]; // @[Arithmetic.scala:107:28]
wire [7:0] _io_out_c_T_4 = _io_out_c_T_3; // @[Arithmetic.scala:107:28]
wire [19:0] _io_out_c_T_7 = {{12{_io_out_c_T_4[7]}}, _io_out_c_T_4}; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_8 = _io_out_c_T_7; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_9 = _io_out_c_T_8; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_10 = _io_out_c_T_9; // @[Arithmetic.scala:125:{81,99}]
wire [19:0] _mac_unit_io_in_b_T_1 = _mac_unit_io_in_b_T; // @[PE.scala:106:37]
wire [7:0] _mac_unit_io_in_b_WIRE = _mac_unit_io_in_b_T_1[7:0]; // @[PE.scala:106:37]
wire [7:0] _c1_T = io_in_d_0[7:0]; // @[PE.scala:31:7]
wire [7:0] _c2_T = io_in_d_0[7:0]; // @[PE.scala:31:7]
wire [7:0] _c1_T_1 = _c1_T; // @[Arithmetic.scala:114:{15,33}]
wire [4:0] _io_out_c_point_five_T_7 = _io_out_c_point_five_T_6[4:0]; // @[Arithmetic.scala:101:53]
wire [7:0] _io_out_c_point_five_T_8 = $signed($signed(c2) >>> _io_out_c_point_five_T_7); // @[PE.scala:71:15]
wire _io_out_c_point_five_T_9 = _io_out_c_point_five_T_8[0]; // @[Arithmetic.scala:101:50]
wire io_out_c_point_five_1 = ~_io_out_c_point_five_T_5 & _io_out_c_point_five_T_9; // @[Arithmetic.scala:101:{29,32,50}]
wire [4:0] _io_out_c_zeros_T_12 = _io_out_c_zeros_T_11[4:0]; // @[Arithmetic.scala:102:66]
wire [31:0] _io_out_c_zeros_T_13 = 32'h1 << _io_out_c_zeros_T_12; // @[Arithmetic.scala:102:{60,66}]
wire [32:0] _io_out_c_zeros_T_14 = {1'h0, _io_out_c_zeros_T_13} - 33'h1; // @[Arithmetic.scala:102:{60,81}]
wire [31:0] _io_out_c_zeros_T_15 = _io_out_c_zeros_T_14[31:0]; // @[Arithmetic.scala:102:81]
wire [31:0] _io_out_c_zeros_T_16 = {24'h0, _io_out_c_zeros_T_15[7:0] & _io_out_c_zeros_T_10}; // @[Arithmetic.scala:102:{45,52,81}]
wire [31:0] _io_out_c_zeros_T_17 = _io_out_c_zeros_T_9 ? 32'h0 : _io_out_c_zeros_T_16; // @[Arithmetic.scala:102:{24,27,52}]
wire io_out_c_zeros_1 = |_io_out_c_zeros_T_17; // @[Arithmetic.scala:102:{24,89}]
wire [7:0] _GEN_4 = $signed($signed(c2) >>> _GEN_2); // @[PE.scala:71:15]
wire [7:0] _io_out_c_ones_digit_T_1; // @[Arithmetic.scala:103:30]
assign _io_out_c_ones_digit_T_1 = _GEN_4; // @[Arithmetic.scala:103:30]
wire [7:0] _io_out_c_T_11; // @[Arithmetic.scala:107:15]
assign _io_out_c_T_11 = _GEN_4; // @[Arithmetic.scala:103:30, :107:15]
wire io_out_c_ones_digit_1 = _io_out_c_ones_digit_T_1[0]; // @[Arithmetic.scala:103:30]
wire _io_out_c_r_T_2 = io_out_c_zeros_1 | io_out_c_ones_digit_1; // @[Arithmetic.scala:102:89, :103:30, :105:38]
wire _io_out_c_r_T_3 = io_out_c_point_five_1 & _io_out_c_r_T_2; // @[Arithmetic.scala:101:29, :105:{29,38}]
wire io_out_c_r_1 = _io_out_c_r_T_3; // @[Arithmetic.scala:105:{29,53}]
wire [1:0] _io_out_c_T_12 = {1'h0, io_out_c_r_1}; // @[Arithmetic.scala:105:53, :107:33]
wire [8:0] _io_out_c_T_13 = {_io_out_c_T_11[7], _io_out_c_T_11} + {{7{_io_out_c_T_12[1]}}, _io_out_c_T_12}; // @[Arithmetic.scala:107:{15,28,33}]
wire [7:0] _io_out_c_T_14 = _io_out_c_T_13[7:0]; // @[Arithmetic.scala:107:28]
wire [7:0] _io_out_c_T_15 = _io_out_c_T_14; // @[Arithmetic.scala:107:28]
wire [19:0] _io_out_c_T_18 = {{12{_io_out_c_T_15[7]}}, _io_out_c_T_15}; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_19 = _io_out_c_T_18; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_20 = _io_out_c_T_19; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_21 = _io_out_c_T_20; // @[Arithmetic.scala:125:{81,99}]
wire [19:0] _mac_unit_io_in_b_T_3 = _mac_unit_io_in_b_T_2; // @[PE.scala:113:37]
wire [7:0] _mac_unit_io_in_b_WIRE_1 = _mac_unit_io_in_b_T_3[7:0]; // @[PE.scala:113:37]
wire [7:0] _c2_T_1 = _c2_T; // @[Arithmetic.scala:114:{15,33}]
wire [7:0] _mac_unit_io_in_b_T_5; // @[PE.scala:121:38]
assign _mac_unit_io_in_b_T_5 = _mac_unit_io_in_b_T_4; // @[PE.scala:121:38]
wire [7:0] _mac_unit_io_in_b_WIRE_2 = _mac_unit_io_in_b_T_5; // @[PE.scala:121:38]
assign io_out_c_0 = io_in_control_propagate_0 ? {{12{c1[7]}}, c1} : {{12{c2[7]}}, c2}; // @[PE.scala:31:7, :70:15, :71:15, :119:30, :120:16, :126:16]
wire [7:0] _mac_unit_io_in_b_T_7; // @[PE.scala:127:38]
assign _mac_unit_io_in_b_T_7 = _mac_unit_io_in_b_T_6; // @[PE.scala:127:38]
wire [7:0] _mac_unit_io_in_b_WIRE_3 = _mac_unit_io_in_b_T_7; // @[PE.scala:127:38]
wire [19:0] _mac_unit_io_in_b_T_9 = _mac_unit_io_in_b_T_8; // @[PE.scala:137:35]
wire [7:0] _mac_unit_io_in_b_WIRE_4 = _mac_unit_io_in_b_T_9[7:0]; // @[PE.scala:137:35]
always @(posedge clock) begin // @[PE.scala:31:7]
if (io_in_valid_0 & io_in_control_propagate_0) // @[PE.scala:31:7, :102:95, :141:17, :142:8]
c1 <= io_in_d_0[7:0]; // @[PE.scala:31:7, :70:15]
if (~(~io_in_valid_0 | io_in_control_propagate_0)) // @[PE.scala:31:7, :71:15, :102:95, :119:30, :130:10, :141:{9,17}, :143:8]
c2 <= io_in_d_0[7:0]; // @[PE.scala:31:7, :71:15]
if (io_in_valid_0) // @[PE.scala:31:7]
last_s <= io_in_control_propagate_0; // @[PE.scala:31:7, :89:25]
always @(posedge)
MacUnit_119 mac_unit ( // @[PE.scala:64:24]
.clock (clock),
.reset (reset),
.io_in_a (io_in_a_0), // @[PE.scala:31:7]
.io_in_b (io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE_2 : _mac_unit_io_in_b_WIRE_3), // @[PE.scala:31:7, :119:30, :121:{24,38}, :127:{24,38}]
.io_in_c (io_in_b_0), // @[PE.scala:31:7]
.io_out_d (io_out_b_0)
); // @[PE.scala:64:24]
assign io_out_a = io_out_a_0; // @[PE.scala:31:7]
assign io_out_b = io_out_b_0; // @[PE.scala:31:7]
assign io_out_c = io_out_c_0; // @[PE.scala:31:7]
assign io_out_control_dataflow = io_out_control_dataflow_0; // @[PE.scala:31:7]
assign io_out_control_propagate = io_out_control_propagate_0; // @[PE.scala:31:7]
assign io_out_control_shift = io_out_control_shift_0; // @[PE.scala:31:7]
assign io_out_id = io_out_id_0; // @[PE.scala:31:7]
assign io_out_last = io_out_last_0; // @[PE.scala:31:7]
assign io_out_valid = io_out_valid_0; // @[PE.scala:31:7]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File primitives.scala:
/*============================================================================
This Chisel source file is part of a pre-release version of the HardFloat IEEE
Floating-Point Arithmetic Package, by John R. Hauser (with some contributions
from Yunsup Lee and Andrew Waterman, mainly concerning testing).
Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
University of California. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
package hardfloat
import chisel3._
import chisel3.util._
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
object lowMask
{
def apply(in: UInt, topBound: BigInt, bottomBound: BigInt): UInt =
{
require(topBound != bottomBound)
val numInVals = BigInt(1)<<in.getWidth
if (topBound < bottomBound) {
lowMask(~in, numInVals - 1 - topBound, numInVals - 1 - bottomBound)
} else if (numInVals > 64 /* Empirical */) {
// For simulation performance, we should avoid generating
// exteremely wide shifters, so we divide and conquer.
// Empirically, this does not impact synthesis QoR.
val mid = numInVals / 2
val msb = in(in.getWidth - 1)
val lsbs = in(in.getWidth - 2, 0)
if (mid < topBound) {
if (mid <= bottomBound) {
Mux(msb,
lowMask(lsbs, topBound - mid, bottomBound - mid),
0.U
)
} else {
Mux(msb,
lowMask(lsbs, topBound - mid, 0) ## ((BigInt(1)<<(mid - bottomBound).toInt) - 1).U,
lowMask(lsbs, mid, bottomBound)
)
}
} else {
~Mux(msb, 0.U, ~lowMask(lsbs, topBound, bottomBound))
}
} else {
val shift = (BigInt(-1)<<numInVals.toInt).S>>in
Reverse(
shift(
(numInVals - 1 - bottomBound).toInt,
(numInVals - topBound).toInt
)
)
}
}
}
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
object countLeadingZeros
{
def apply(in: UInt): UInt = PriorityEncoder(in.asBools.reverse)
}
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
object orReduceBy2
{
def apply(in: UInt): UInt =
{
val reducedWidth = (in.getWidth + 1)>>1
val reducedVec = Wire(Vec(reducedWidth, Bool()))
for (ix <- 0 until reducedWidth - 1) {
reducedVec(ix) := in(ix * 2 + 1, ix * 2).orR
}
reducedVec(reducedWidth - 1) :=
in(in.getWidth - 1, (reducedWidth - 1) * 2).orR
reducedVec.asUInt
}
}
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
object orReduceBy4
{
def apply(in: UInt): UInt =
{
val reducedWidth = (in.getWidth + 3)>>2
val reducedVec = Wire(Vec(reducedWidth, Bool()))
for (ix <- 0 until reducedWidth - 1) {
reducedVec(ix) := in(ix * 4 + 3, ix * 4).orR
}
reducedVec(reducedWidth - 1) :=
in(in.getWidth - 1, (reducedWidth - 1) * 4).orR
reducedVec.asUInt
}
}
File MulAddRecFN.scala:
/*============================================================================
This Chisel source file is part of a pre-release version of the HardFloat IEEE
Floating-Point Arithmetic Package, by John R. Hauser (with some contributions
from Yunsup Lee and Andrew Waterman, mainly concerning testing).
Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
University of California. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
package hardfloat
import chisel3._
import chisel3.util._
import consts._
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
class MulAddRecFN_interIo(expWidth: Int, sigWidth: Int) extends Bundle
{
//*** ENCODE SOME OF THESE CASES IN FEWER BITS?:
val isSigNaNAny = Bool()
val isNaNAOrB = Bool()
val isInfA = Bool()
val isZeroA = Bool()
val isInfB = Bool()
val isZeroB = Bool()
val signProd = Bool()
val isNaNC = Bool()
val isInfC = Bool()
val isZeroC = Bool()
val sExpSum = SInt((expWidth + 2).W)
val doSubMags = Bool()
val CIsDominant = Bool()
val CDom_CAlignDist = UInt(log2Ceil(sigWidth + 1).W)
val highAlignedSigC = UInt((sigWidth + 2).W)
val bit0AlignedSigC = UInt(1.W)
}
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
class MulAddRecFNToRaw_preMul(expWidth: Int, sigWidth: Int) extends RawModule
{
override def desiredName = s"MulAddRecFNToRaw_preMul_e${expWidth}_s${sigWidth}"
val io = IO(new Bundle {
val op = Input(Bits(2.W))
val a = Input(Bits((expWidth + sigWidth + 1).W))
val b = Input(Bits((expWidth + sigWidth + 1).W))
val c = Input(Bits((expWidth + sigWidth + 1).W))
val mulAddA = Output(UInt(sigWidth.W))
val mulAddB = Output(UInt(sigWidth.W))
val mulAddC = Output(UInt((sigWidth * 2).W))
val toPostMul = Output(new MulAddRecFN_interIo(expWidth, sigWidth))
})
//------------------------------------------------------------------------
//------------------------------------------------------------------------
//*** POSSIBLE TO REDUCE THIS BY 1 OR 2 BITS? (CURRENTLY 2 BITS BETWEEN
//*** UNSHIFTED C AND PRODUCT):
val sigSumWidth = sigWidth * 3 + 3
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val rawA = rawFloatFromRecFN(expWidth, sigWidth, io.a)
val rawB = rawFloatFromRecFN(expWidth, sigWidth, io.b)
val rawC = rawFloatFromRecFN(expWidth, sigWidth, io.c)
val signProd = rawA.sign ^ rawB.sign ^ io.op(1)
//*** REVIEW THE BIAS FOR 'sExpAlignedProd':
val sExpAlignedProd =
rawA.sExp +& rawB.sExp + (-(BigInt(1)<<expWidth) + sigWidth + 3).S
val doSubMags = signProd ^ rawC.sign ^ io.op(0)
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val sNatCAlignDist = sExpAlignedProd - rawC.sExp
val posNatCAlignDist = sNatCAlignDist(expWidth + 1, 0)
val isMinCAlign = rawA.isZero || rawB.isZero || (sNatCAlignDist < 0.S)
val CIsDominant =
! rawC.isZero && (isMinCAlign || (posNatCAlignDist <= sigWidth.U))
val CAlignDist =
Mux(isMinCAlign,
0.U,
Mux(posNatCAlignDist < (sigSumWidth - 1).U,
posNatCAlignDist(log2Ceil(sigSumWidth) - 1, 0),
(sigSumWidth - 1).U
)
)
val mainAlignedSigC =
(Mux(doSubMags, ~rawC.sig, rawC.sig) ## Fill(sigSumWidth - sigWidth + 2, doSubMags)).asSInt>>CAlignDist
val reduced4CExtra =
(orReduceBy4(rawC.sig<<((sigSumWidth - sigWidth - 1) & 3)) &
lowMask(
CAlignDist>>2,
//*** NOT NEEDED?:
// (sigSumWidth + 2)>>2,
(sigSumWidth - 1)>>2,
(sigSumWidth - sigWidth - 1)>>2
)
).orR
val alignedSigC =
Cat(mainAlignedSigC>>3,
Mux(doSubMags,
mainAlignedSigC(2, 0).andR && ! reduced4CExtra,
mainAlignedSigC(2, 0).orR || reduced4CExtra
)
)
//------------------------------------------------------------------------
//------------------------------------------------------------------------
io.mulAddA := rawA.sig
io.mulAddB := rawB.sig
io.mulAddC := alignedSigC(sigWidth * 2, 1)
io.toPostMul.isSigNaNAny :=
isSigNaNRawFloat(rawA) || isSigNaNRawFloat(rawB) ||
isSigNaNRawFloat(rawC)
io.toPostMul.isNaNAOrB := rawA.isNaN || rawB.isNaN
io.toPostMul.isInfA := rawA.isInf
io.toPostMul.isZeroA := rawA.isZero
io.toPostMul.isInfB := rawB.isInf
io.toPostMul.isZeroB := rawB.isZero
io.toPostMul.signProd := signProd
io.toPostMul.isNaNC := rawC.isNaN
io.toPostMul.isInfC := rawC.isInf
io.toPostMul.isZeroC := rawC.isZero
io.toPostMul.sExpSum :=
Mux(CIsDominant, rawC.sExp, sExpAlignedProd - sigWidth.S)
io.toPostMul.doSubMags := doSubMags
io.toPostMul.CIsDominant := CIsDominant
io.toPostMul.CDom_CAlignDist := CAlignDist(log2Ceil(sigWidth + 1) - 1, 0)
io.toPostMul.highAlignedSigC :=
alignedSigC(sigSumWidth - 1, sigWidth * 2 + 1)
io.toPostMul.bit0AlignedSigC := alignedSigC(0)
}
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
class MulAddRecFNToRaw_postMul(expWidth: Int, sigWidth: Int) extends RawModule
{
override def desiredName = s"MulAddRecFNToRaw_postMul_e${expWidth}_s${sigWidth}"
val io = IO(new Bundle {
val fromPreMul = Input(new MulAddRecFN_interIo(expWidth, sigWidth))
val mulAddResult = Input(UInt((sigWidth * 2 + 1).W))
val roundingMode = Input(UInt(3.W))
val invalidExc = Output(Bool())
val rawOut = Output(new RawFloat(expWidth, sigWidth + 2))
})
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val sigSumWidth = sigWidth * 3 + 3
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val roundingMode_min = (io.roundingMode === round_min)
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val opSignC = io.fromPreMul.signProd ^ io.fromPreMul.doSubMags
val sigSum =
Cat(Mux(io.mulAddResult(sigWidth * 2),
io.fromPreMul.highAlignedSigC + 1.U,
io.fromPreMul.highAlignedSigC
),
io.mulAddResult(sigWidth * 2 - 1, 0),
io.fromPreMul.bit0AlignedSigC
)
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val CDom_sign = opSignC
val CDom_sExp = io.fromPreMul.sExpSum - io.fromPreMul.doSubMags.zext
val CDom_absSigSum =
Mux(io.fromPreMul.doSubMags,
~sigSum(sigSumWidth - 1, sigWidth + 1),
0.U(1.W) ##
//*** IF GAP IS REDUCED TO 1 BIT, MUST REDUCE THIS COMPONENT TO 1 BIT TOO:
io.fromPreMul.highAlignedSigC(sigWidth + 1, sigWidth) ##
sigSum(sigSumWidth - 3, sigWidth + 2)
)
val CDom_absSigSumExtra =
Mux(io.fromPreMul.doSubMags,
(~sigSum(sigWidth, 1)).orR,
sigSum(sigWidth + 1, 1).orR
)
val CDom_mainSig =
(CDom_absSigSum<<io.fromPreMul.CDom_CAlignDist)(
sigWidth * 2 + 1, sigWidth - 3)
val CDom_reduced4SigExtra =
(orReduceBy4(CDom_absSigSum(sigWidth - 1, 0)<<(~sigWidth & 3)) &
lowMask(io.fromPreMul.CDom_CAlignDist>>2, 0, sigWidth>>2)).orR
val CDom_sig =
Cat(CDom_mainSig>>3,
CDom_mainSig(2, 0).orR || CDom_reduced4SigExtra ||
CDom_absSigSumExtra
)
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val notCDom_signSigSum = sigSum(sigWidth * 2 + 3)
val notCDom_absSigSum =
Mux(notCDom_signSigSum,
~sigSum(sigWidth * 2 + 2, 0),
sigSum(sigWidth * 2 + 2, 0) + io.fromPreMul.doSubMags
)
val notCDom_reduced2AbsSigSum = orReduceBy2(notCDom_absSigSum)
val notCDom_normDistReduced2 = countLeadingZeros(notCDom_reduced2AbsSigSum)
val notCDom_nearNormDist = notCDom_normDistReduced2<<1
val notCDom_sExp = io.fromPreMul.sExpSum - notCDom_nearNormDist.asUInt.zext
val notCDom_mainSig =
(notCDom_absSigSum<<notCDom_nearNormDist)(
sigWidth * 2 + 3, sigWidth - 1)
val notCDom_reduced4SigExtra =
(orReduceBy2(
notCDom_reduced2AbsSigSum(sigWidth>>1, 0)<<((sigWidth>>1) & 1)) &
lowMask(notCDom_normDistReduced2>>1, 0, (sigWidth + 2)>>2)
).orR
val notCDom_sig =
Cat(notCDom_mainSig>>3,
notCDom_mainSig(2, 0).orR || notCDom_reduced4SigExtra
)
val notCDom_completeCancellation =
(notCDom_sig(sigWidth + 2, sigWidth + 1) === 0.U)
val notCDom_sign =
Mux(notCDom_completeCancellation,
roundingMode_min,
io.fromPreMul.signProd ^ notCDom_signSigSum
)
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val notNaN_isInfProd = io.fromPreMul.isInfA || io.fromPreMul.isInfB
val notNaN_isInfOut = notNaN_isInfProd || io.fromPreMul.isInfC
val notNaN_addZeros =
(io.fromPreMul.isZeroA || io.fromPreMul.isZeroB) &&
io.fromPreMul.isZeroC
io.invalidExc :=
io.fromPreMul.isSigNaNAny ||
(io.fromPreMul.isInfA && io.fromPreMul.isZeroB) ||
(io.fromPreMul.isZeroA && io.fromPreMul.isInfB) ||
(! io.fromPreMul.isNaNAOrB &&
(io.fromPreMul.isInfA || io.fromPreMul.isInfB) &&
io.fromPreMul.isInfC &&
io.fromPreMul.doSubMags)
io.rawOut.isNaN := io.fromPreMul.isNaNAOrB || io.fromPreMul.isNaNC
io.rawOut.isInf := notNaN_isInfOut
//*** IMPROVE?:
io.rawOut.isZero :=
notNaN_addZeros ||
(! io.fromPreMul.CIsDominant && notCDom_completeCancellation)
io.rawOut.sign :=
(notNaN_isInfProd && io.fromPreMul.signProd) ||
(io.fromPreMul.isInfC && opSignC) ||
(notNaN_addZeros && ! roundingMode_min &&
io.fromPreMul.signProd && opSignC) ||
(notNaN_addZeros && roundingMode_min &&
(io.fromPreMul.signProd || opSignC)) ||
(! notNaN_isInfOut && ! notNaN_addZeros &&
Mux(io.fromPreMul.CIsDominant, CDom_sign, notCDom_sign))
io.rawOut.sExp := Mux(io.fromPreMul.CIsDominant, CDom_sExp, notCDom_sExp)
io.rawOut.sig := Mux(io.fromPreMul.CIsDominant, CDom_sig, notCDom_sig)
}
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
class MulAddRecFN(expWidth: Int, sigWidth: Int) extends RawModule
{
override def desiredName = s"MulAddRecFN_e${expWidth}_s${sigWidth}"
val io = IO(new Bundle {
val op = Input(Bits(2.W))
val a = Input(Bits((expWidth + sigWidth + 1).W))
val b = Input(Bits((expWidth + sigWidth + 1).W))
val c = Input(Bits((expWidth + sigWidth + 1).W))
val roundingMode = Input(UInt(3.W))
val detectTininess = Input(UInt(1.W))
val out = Output(Bits((expWidth + sigWidth + 1).W))
val exceptionFlags = Output(Bits(5.W))
})
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val mulAddRecFNToRaw_preMul =
Module(new MulAddRecFNToRaw_preMul(expWidth, sigWidth))
val mulAddRecFNToRaw_postMul =
Module(new MulAddRecFNToRaw_postMul(expWidth, sigWidth))
mulAddRecFNToRaw_preMul.io.op := io.op
mulAddRecFNToRaw_preMul.io.a := io.a
mulAddRecFNToRaw_preMul.io.b := io.b
mulAddRecFNToRaw_preMul.io.c := io.c
val mulAddResult =
(mulAddRecFNToRaw_preMul.io.mulAddA *
mulAddRecFNToRaw_preMul.io.mulAddB) +&
mulAddRecFNToRaw_preMul.io.mulAddC
mulAddRecFNToRaw_postMul.io.fromPreMul :=
mulAddRecFNToRaw_preMul.io.toPostMul
mulAddRecFNToRaw_postMul.io.mulAddResult := mulAddResult
mulAddRecFNToRaw_postMul.io.roundingMode := io.roundingMode
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val roundRawFNToRecFN =
Module(new RoundRawFNToRecFN(expWidth, sigWidth, 0))
roundRawFNToRecFN.io.invalidExc := mulAddRecFNToRaw_postMul.io.invalidExc
roundRawFNToRecFN.io.infiniteExc := false.B
roundRawFNToRecFN.io.in := mulAddRecFNToRaw_postMul.io.rawOut
roundRawFNToRecFN.io.roundingMode := io.roundingMode
roundRawFNToRecFN.io.detectTininess := io.detectTininess
io.out := roundRawFNToRecFN.io.out
io.exceptionFlags := roundRawFNToRecFN.io.exceptionFlags
}
| module MulAddRecFNToRaw_postMul_e8_s24_9( // @[MulAddRecFN.scala:169:7]
input io_fromPreMul_isSigNaNAny, // @[MulAddRecFN.scala:172:16]
input io_fromPreMul_isNaNAOrB, // @[MulAddRecFN.scala:172:16]
input io_fromPreMul_isInfA, // @[MulAddRecFN.scala:172:16]
input io_fromPreMul_isZeroA, // @[MulAddRecFN.scala:172:16]
input io_fromPreMul_isInfB, // @[MulAddRecFN.scala:172:16]
input io_fromPreMul_isZeroB, // @[MulAddRecFN.scala:172:16]
input io_fromPreMul_signProd, // @[MulAddRecFN.scala:172:16]
input [9:0] io_fromPreMul_sExpSum, // @[MulAddRecFN.scala:172:16]
input io_fromPreMul_doSubMags, // @[MulAddRecFN.scala:172:16]
input [4:0] io_fromPreMul_CDom_CAlignDist, // @[MulAddRecFN.scala:172:16]
input [25:0] io_fromPreMul_highAlignedSigC, // @[MulAddRecFN.scala:172:16]
input io_fromPreMul_bit0AlignedSigC, // @[MulAddRecFN.scala:172:16]
input [48:0] io_mulAddResult, // @[MulAddRecFN.scala:172:16]
output io_invalidExc, // @[MulAddRecFN.scala:172:16]
output io_rawOut_isNaN, // @[MulAddRecFN.scala:172:16]
output io_rawOut_isInf, // @[MulAddRecFN.scala:172:16]
output io_rawOut_isZero, // @[MulAddRecFN.scala:172:16]
output io_rawOut_sign, // @[MulAddRecFN.scala:172:16]
output [9:0] io_rawOut_sExp, // @[MulAddRecFN.scala:172:16]
output [26:0] io_rawOut_sig // @[MulAddRecFN.scala:172:16]
);
wire io_fromPreMul_isSigNaNAny_0 = io_fromPreMul_isSigNaNAny; // @[MulAddRecFN.scala:169:7]
wire io_fromPreMul_isNaNAOrB_0 = io_fromPreMul_isNaNAOrB; // @[MulAddRecFN.scala:169:7]
wire io_fromPreMul_isInfA_0 = io_fromPreMul_isInfA; // @[MulAddRecFN.scala:169:7]
wire io_fromPreMul_isZeroA_0 = io_fromPreMul_isZeroA; // @[MulAddRecFN.scala:169:7]
wire io_fromPreMul_isInfB_0 = io_fromPreMul_isInfB; // @[MulAddRecFN.scala:169:7]
wire io_fromPreMul_isZeroB_0 = io_fromPreMul_isZeroB; // @[MulAddRecFN.scala:169:7]
wire io_fromPreMul_signProd_0 = io_fromPreMul_signProd; // @[MulAddRecFN.scala:169:7]
wire [9:0] io_fromPreMul_sExpSum_0 = io_fromPreMul_sExpSum; // @[MulAddRecFN.scala:169:7]
wire io_fromPreMul_doSubMags_0 = io_fromPreMul_doSubMags; // @[MulAddRecFN.scala:169:7]
wire [4:0] io_fromPreMul_CDom_CAlignDist_0 = io_fromPreMul_CDom_CAlignDist; // @[MulAddRecFN.scala:169:7]
wire [25:0] io_fromPreMul_highAlignedSigC_0 = io_fromPreMul_highAlignedSigC; // @[MulAddRecFN.scala:169:7]
wire io_fromPreMul_bit0AlignedSigC_0 = io_fromPreMul_bit0AlignedSigC; // @[MulAddRecFN.scala:169:7]
wire [48:0] io_mulAddResult_0 = io_mulAddResult; // @[MulAddRecFN.scala:169:7]
wire [2:0] io_roundingMode = 3'h0; // @[MulAddRecFN.scala:169:7, :172:16]
wire io_fromPreMul_isZeroC = 1'h1; // @[MulAddRecFN.scala:169:7]
wire _io_rawOut_isZero_T = 1'h1; // @[MulAddRecFN.scala:283:14]
wire _io_rawOut_sign_T_3 = 1'h1; // @[MulAddRecFN.scala:287:29]
wire io_fromPreMul_isNaNC = 1'h0; // @[MulAddRecFN.scala:169:7]
wire io_fromPreMul_isInfC = 1'h0; // @[MulAddRecFN.scala:169:7]
wire io_fromPreMul_CIsDominant = 1'h0; // @[MulAddRecFN.scala:169:7]
wire roundingMode_min = 1'h0; // @[MulAddRecFN.scala:186:45]
wire _io_invalidExc_T_7 = 1'h0; // @[MulAddRecFN.scala:275:61]
wire _io_invalidExc_T_8 = 1'h0; // @[MulAddRecFN.scala:276:35]
wire _io_rawOut_sign_T_1 = 1'h0; // @[MulAddRecFN.scala:286:31]
wire _io_rawOut_sign_T_8 = 1'h0; // @[MulAddRecFN.scala:289:26]
wire _io_rawOut_sign_T_10 = 1'h0; // @[MulAddRecFN.scala:289:46]
wire _io_rawOut_isNaN_T = io_fromPreMul_isNaNAOrB_0; // @[MulAddRecFN.scala:169:7, :278:48]
wire _io_invalidExc_T_9; // @[MulAddRecFN.scala:273:57]
wire notNaN_isInfOut; // @[MulAddRecFN.scala:265:44]
wire _io_rawOut_isZero_T_2; // @[MulAddRecFN.scala:282:25]
wire _io_rawOut_sign_T_17; // @[MulAddRecFN.scala:290:50]
wire [9:0] _io_rawOut_sExp_T; // @[MulAddRecFN.scala:293:26]
wire [26:0] _io_rawOut_sig_T; // @[MulAddRecFN.scala:294:25]
wire io_rawOut_isNaN_0; // @[MulAddRecFN.scala:169:7]
wire io_rawOut_isInf_0; // @[MulAddRecFN.scala:169:7]
wire io_rawOut_isZero_0; // @[MulAddRecFN.scala:169:7]
wire io_rawOut_sign_0; // @[MulAddRecFN.scala:169:7]
wire [9:0] io_rawOut_sExp_0; // @[MulAddRecFN.scala:169:7]
wire [26:0] io_rawOut_sig_0; // @[MulAddRecFN.scala:169:7]
wire io_invalidExc_0; // @[MulAddRecFN.scala:169:7]
wire opSignC = io_fromPreMul_signProd_0 ^ io_fromPreMul_doSubMags_0; // @[MulAddRecFN.scala:169:7, :190:42]
wire _sigSum_T = io_mulAddResult_0[48]; // @[MulAddRecFN.scala:169:7, :192:32]
wire [26:0] _sigSum_T_1 = {1'h0, io_fromPreMul_highAlignedSigC_0} + 27'h1; // @[MulAddRecFN.scala:169:7, :193:47]
wire [25:0] _sigSum_T_2 = _sigSum_T_1[25:0]; // @[MulAddRecFN.scala:193:47]
wire [25:0] _sigSum_T_3 = _sigSum_T ? _sigSum_T_2 : io_fromPreMul_highAlignedSigC_0; // @[MulAddRecFN.scala:169:7, :192:{16,32}, :193:47]
wire [47:0] _sigSum_T_4 = io_mulAddResult_0[47:0]; // @[MulAddRecFN.scala:169:7, :196:28]
wire [73:0] sigSum_hi = {_sigSum_T_3, _sigSum_T_4}; // @[MulAddRecFN.scala:192:{12,16}, :196:28]
wire [74:0] sigSum = {sigSum_hi, io_fromPreMul_bit0AlignedSigC_0}; // @[MulAddRecFN.scala:169:7, :192:12]
wire [1:0] _CDom_sExp_T = {1'h0, io_fromPreMul_doSubMags_0}; // @[MulAddRecFN.scala:169:7, :203:69]
wire [10:0] _GEN = {io_fromPreMul_sExpSum_0[9], io_fromPreMul_sExpSum_0}; // @[MulAddRecFN.scala:169:7, :203:43]
wire [10:0] _CDom_sExp_T_1 = _GEN - {{9{_CDom_sExp_T[1]}}, _CDom_sExp_T}; // @[MulAddRecFN.scala:203:{43,69}]
wire [9:0] _CDom_sExp_T_2 = _CDom_sExp_T_1[9:0]; // @[MulAddRecFN.scala:203:43]
wire [9:0] CDom_sExp = _CDom_sExp_T_2; // @[MulAddRecFN.scala:203:43]
wire [49:0] _CDom_absSigSum_T = sigSum[74:25]; // @[MulAddRecFN.scala:192:12, :206:20]
wire [49:0] _CDom_absSigSum_T_1 = ~_CDom_absSigSum_T; // @[MulAddRecFN.scala:206:{13,20}]
wire [1:0] _CDom_absSigSum_T_2 = io_fromPreMul_highAlignedSigC_0[25:24]; // @[MulAddRecFN.scala:169:7, :209:46]
wire [2:0] _CDom_absSigSum_T_3 = {1'h0, _CDom_absSigSum_T_2}; // @[MulAddRecFN.scala:207:22, :209:46]
wire [46:0] _CDom_absSigSum_T_4 = sigSum[72:26]; // @[MulAddRecFN.scala:192:12, :210:23]
wire [49:0] _CDom_absSigSum_T_5 = {_CDom_absSigSum_T_3, _CDom_absSigSum_T_4}; // @[MulAddRecFN.scala:207:22, :209:71, :210:23]
wire [49:0] CDom_absSigSum = io_fromPreMul_doSubMags_0 ? _CDom_absSigSum_T_1 : _CDom_absSigSum_T_5; // @[MulAddRecFN.scala:169:7, :205:12, :206:13, :209:71]
wire [23:0] _CDom_absSigSumExtra_T = sigSum[24:1]; // @[MulAddRecFN.scala:192:12, :215:21]
wire [23:0] _CDom_absSigSumExtra_T_1 = ~_CDom_absSigSumExtra_T; // @[MulAddRecFN.scala:215:{14,21}]
wire _CDom_absSigSumExtra_T_2 = |_CDom_absSigSumExtra_T_1; // @[MulAddRecFN.scala:215:{14,36}]
wire [24:0] _CDom_absSigSumExtra_T_3 = sigSum[25:1]; // @[MulAddRecFN.scala:192:12, :216:19]
wire _CDom_absSigSumExtra_T_4 = |_CDom_absSigSumExtra_T_3; // @[MulAddRecFN.scala:216:{19,37}]
wire CDom_absSigSumExtra = io_fromPreMul_doSubMags_0 ? _CDom_absSigSumExtra_T_2 : _CDom_absSigSumExtra_T_4; // @[MulAddRecFN.scala:169:7, :214:12, :215:36, :216:37]
wire [80:0] _CDom_mainSig_T = {31'h0, CDom_absSigSum} << io_fromPreMul_CDom_CAlignDist_0; // @[MulAddRecFN.scala:169:7, :205:12, :219:24]
wire [28:0] CDom_mainSig = _CDom_mainSig_T[49:21]; // @[MulAddRecFN.scala:219:{24,56}]
wire [23:0] _CDom_reduced4SigExtra_T = CDom_absSigSum[23:0]; // @[MulAddRecFN.scala:205:12, :222:36]
wire [26:0] _CDom_reduced4SigExtra_T_1 = {_CDom_reduced4SigExtra_T, 3'h0}; // @[MulAddRecFN.scala:169:7, :172:16, :222:{36,53}]
wire _CDom_reduced4SigExtra_reducedVec_0_T_1; // @[primitives.scala:120:54]
wire _CDom_reduced4SigExtra_reducedVec_1_T_1; // @[primitives.scala:120:54]
wire _CDom_reduced4SigExtra_reducedVec_2_T_1; // @[primitives.scala:120:54]
wire _CDom_reduced4SigExtra_reducedVec_3_T_1; // @[primitives.scala:120:54]
wire _CDom_reduced4SigExtra_reducedVec_4_T_1; // @[primitives.scala:120:54]
wire _CDom_reduced4SigExtra_reducedVec_5_T_1; // @[primitives.scala:120:54]
wire _CDom_reduced4SigExtra_reducedVec_6_T_1; // @[primitives.scala:123:57]
wire CDom_reduced4SigExtra_reducedVec_0; // @[primitives.scala:118:30]
wire CDom_reduced4SigExtra_reducedVec_1; // @[primitives.scala:118:30]
wire CDom_reduced4SigExtra_reducedVec_2; // @[primitives.scala:118:30]
wire CDom_reduced4SigExtra_reducedVec_3; // @[primitives.scala:118:30]
wire CDom_reduced4SigExtra_reducedVec_4; // @[primitives.scala:118:30]
wire CDom_reduced4SigExtra_reducedVec_5; // @[primitives.scala:118:30]
wire CDom_reduced4SigExtra_reducedVec_6; // @[primitives.scala:118:30]
wire [3:0] _CDom_reduced4SigExtra_reducedVec_0_T = _CDom_reduced4SigExtra_T_1[3:0]; // @[primitives.scala:120:33]
assign _CDom_reduced4SigExtra_reducedVec_0_T_1 = |_CDom_reduced4SigExtra_reducedVec_0_T; // @[primitives.scala:120:{33,54}]
assign CDom_reduced4SigExtra_reducedVec_0 = _CDom_reduced4SigExtra_reducedVec_0_T_1; // @[primitives.scala:118:30, :120:54]
wire [3:0] _CDom_reduced4SigExtra_reducedVec_1_T = _CDom_reduced4SigExtra_T_1[7:4]; // @[primitives.scala:120:33]
assign _CDom_reduced4SigExtra_reducedVec_1_T_1 = |_CDom_reduced4SigExtra_reducedVec_1_T; // @[primitives.scala:120:{33,54}]
assign CDom_reduced4SigExtra_reducedVec_1 = _CDom_reduced4SigExtra_reducedVec_1_T_1; // @[primitives.scala:118:30, :120:54]
wire [3:0] _CDom_reduced4SigExtra_reducedVec_2_T = _CDom_reduced4SigExtra_T_1[11:8]; // @[primitives.scala:120:33]
assign _CDom_reduced4SigExtra_reducedVec_2_T_1 = |_CDom_reduced4SigExtra_reducedVec_2_T; // @[primitives.scala:120:{33,54}]
assign CDom_reduced4SigExtra_reducedVec_2 = _CDom_reduced4SigExtra_reducedVec_2_T_1; // @[primitives.scala:118:30, :120:54]
wire [3:0] _CDom_reduced4SigExtra_reducedVec_3_T = _CDom_reduced4SigExtra_T_1[15:12]; // @[primitives.scala:120:33]
assign _CDom_reduced4SigExtra_reducedVec_3_T_1 = |_CDom_reduced4SigExtra_reducedVec_3_T; // @[primitives.scala:120:{33,54}]
assign CDom_reduced4SigExtra_reducedVec_3 = _CDom_reduced4SigExtra_reducedVec_3_T_1; // @[primitives.scala:118:30, :120:54]
wire [3:0] _CDom_reduced4SigExtra_reducedVec_4_T = _CDom_reduced4SigExtra_T_1[19:16]; // @[primitives.scala:120:33]
assign _CDom_reduced4SigExtra_reducedVec_4_T_1 = |_CDom_reduced4SigExtra_reducedVec_4_T; // @[primitives.scala:120:{33,54}]
assign CDom_reduced4SigExtra_reducedVec_4 = _CDom_reduced4SigExtra_reducedVec_4_T_1; // @[primitives.scala:118:30, :120:54]
wire [3:0] _CDom_reduced4SigExtra_reducedVec_5_T = _CDom_reduced4SigExtra_T_1[23:20]; // @[primitives.scala:120:33]
assign _CDom_reduced4SigExtra_reducedVec_5_T_1 = |_CDom_reduced4SigExtra_reducedVec_5_T; // @[primitives.scala:120:{33,54}]
assign CDom_reduced4SigExtra_reducedVec_5 = _CDom_reduced4SigExtra_reducedVec_5_T_1; // @[primitives.scala:118:30, :120:54]
wire [2:0] _CDom_reduced4SigExtra_reducedVec_6_T = _CDom_reduced4SigExtra_T_1[26:24]; // @[primitives.scala:123:15]
assign _CDom_reduced4SigExtra_reducedVec_6_T_1 = |_CDom_reduced4SigExtra_reducedVec_6_T; // @[primitives.scala:123:{15,57}]
assign CDom_reduced4SigExtra_reducedVec_6 = _CDom_reduced4SigExtra_reducedVec_6_T_1; // @[primitives.scala:118:30, :123:57]
wire [1:0] CDom_reduced4SigExtra_lo_hi = {CDom_reduced4SigExtra_reducedVec_2, CDom_reduced4SigExtra_reducedVec_1}; // @[primitives.scala:118:30, :124:20]
wire [2:0] CDom_reduced4SigExtra_lo = {CDom_reduced4SigExtra_lo_hi, CDom_reduced4SigExtra_reducedVec_0}; // @[primitives.scala:118:30, :124:20]
wire [1:0] CDom_reduced4SigExtra_hi_lo = {CDom_reduced4SigExtra_reducedVec_4, CDom_reduced4SigExtra_reducedVec_3}; // @[primitives.scala:118:30, :124:20]
wire [1:0] CDom_reduced4SigExtra_hi_hi = {CDom_reduced4SigExtra_reducedVec_6, CDom_reduced4SigExtra_reducedVec_5}; // @[primitives.scala:118:30, :124:20]
wire [3:0] CDom_reduced4SigExtra_hi = {CDom_reduced4SigExtra_hi_hi, CDom_reduced4SigExtra_hi_lo}; // @[primitives.scala:124:20]
wire [6:0] _CDom_reduced4SigExtra_T_2 = {CDom_reduced4SigExtra_hi, CDom_reduced4SigExtra_lo}; // @[primitives.scala:124:20]
wire [2:0] _CDom_reduced4SigExtra_T_3 = io_fromPreMul_CDom_CAlignDist_0[4:2]; // @[MulAddRecFN.scala:169:7, :223:51]
wire [2:0] _CDom_reduced4SigExtra_T_4 = ~_CDom_reduced4SigExtra_T_3; // @[primitives.scala:52:21]
wire [8:0] CDom_reduced4SigExtra_shift = $signed(9'sh100 >>> _CDom_reduced4SigExtra_T_4); // @[primitives.scala:52:21, :76:56]
wire [5:0] _CDom_reduced4SigExtra_T_5 = CDom_reduced4SigExtra_shift[6:1]; // @[primitives.scala:76:56, :78:22]
wire [3:0] _CDom_reduced4SigExtra_T_6 = _CDom_reduced4SigExtra_T_5[3:0]; // @[primitives.scala:77:20, :78:22]
wire [1:0] _CDom_reduced4SigExtra_T_7 = _CDom_reduced4SigExtra_T_6[1:0]; // @[primitives.scala:77:20]
wire _CDom_reduced4SigExtra_T_8 = _CDom_reduced4SigExtra_T_7[0]; // @[primitives.scala:77:20]
wire _CDom_reduced4SigExtra_T_9 = _CDom_reduced4SigExtra_T_7[1]; // @[primitives.scala:77:20]
wire [1:0] _CDom_reduced4SigExtra_T_10 = {_CDom_reduced4SigExtra_T_8, _CDom_reduced4SigExtra_T_9}; // @[primitives.scala:77:20]
wire [1:0] _CDom_reduced4SigExtra_T_11 = _CDom_reduced4SigExtra_T_6[3:2]; // @[primitives.scala:77:20]
wire _CDom_reduced4SigExtra_T_12 = _CDom_reduced4SigExtra_T_11[0]; // @[primitives.scala:77:20]
wire _CDom_reduced4SigExtra_T_13 = _CDom_reduced4SigExtra_T_11[1]; // @[primitives.scala:77:20]
wire [1:0] _CDom_reduced4SigExtra_T_14 = {_CDom_reduced4SigExtra_T_12, _CDom_reduced4SigExtra_T_13}; // @[primitives.scala:77:20]
wire [3:0] _CDom_reduced4SigExtra_T_15 = {_CDom_reduced4SigExtra_T_10, _CDom_reduced4SigExtra_T_14}; // @[primitives.scala:77:20]
wire [1:0] _CDom_reduced4SigExtra_T_16 = _CDom_reduced4SigExtra_T_5[5:4]; // @[primitives.scala:77:20, :78:22]
wire _CDom_reduced4SigExtra_T_17 = _CDom_reduced4SigExtra_T_16[0]; // @[primitives.scala:77:20]
wire _CDom_reduced4SigExtra_T_18 = _CDom_reduced4SigExtra_T_16[1]; // @[primitives.scala:77:20]
wire [1:0] _CDom_reduced4SigExtra_T_19 = {_CDom_reduced4SigExtra_T_17, _CDom_reduced4SigExtra_T_18}; // @[primitives.scala:77:20]
wire [5:0] _CDom_reduced4SigExtra_T_20 = {_CDom_reduced4SigExtra_T_15, _CDom_reduced4SigExtra_T_19}; // @[primitives.scala:77:20]
wire [6:0] _CDom_reduced4SigExtra_T_21 = {1'h0, _CDom_reduced4SigExtra_T_2[5:0] & _CDom_reduced4SigExtra_T_20}; // @[primitives.scala:77:20, :124:20]
wire CDom_reduced4SigExtra = |_CDom_reduced4SigExtra_T_21; // @[MulAddRecFN.scala:222:72, :223:73]
wire [25:0] _CDom_sig_T = CDom_mainSig[28:3]; // @[MulAddRecFN.scala:219:56, :225:25]
wire [2:0] _CDom_sig_T_1 = CDom_mainSig[2:0]; // @[MulAddRecFN.scala:219:56, :226:25]
wire _CDom_sig_T_2 = |_CDom_sig_T_1; // @[MulAddRecFN.scala:226:{25,32}]
wire _CDom_sig_T_3 = _CDom_sig_T_2 | CDom_reduced4SigExtra; // @[MulAddRecFN.scala:223:73, :226:{32,36}]
wire _CDom_sig_T_4 = _CDom_sig_T_3 | CDom_absSigSumExtra; // @[MulAddRecFN.scala:214:12, :226:{36,61}]
wire [26:0] CDom_sig = {_CDom_sig_T, _CDom_sig_T_4}; // @[MulAddRecFN.scala:225:{12,25}, :226:61]
wire notCDom_signSigSum = sigSum[51]; // @[MulAddRecFN.scala:192:12, :232:36]
wire [50:0] _notCDom_absSigSum_T = sigSum[50:0]; // @[MulAddRecFN.scala:192:12, :235:20]
wire [50:0] _notCDom_absSigSum_T_2 = sigSum[50:0]; // @[MulAddRecFN.scala:192:12, :235:20, :236:19]
wire [50:0] _notCDom_absSigSum_T_1 = ~_notCDom_absSigSum_T; // @[MulAddRecFN.scala:235:{13,20}]
wire [51:0] _notCDom_absSigSum_T_3 = {1'h0, _notCDom_absSigSum_T_2} + {51'h0, io_fromPreMul_doSubMags_0}; // @[MulAddRecFN.scala:169:7, :236:{19,41}]
wire [50:0] _notCDom_absSigSum_T_4 = _notCDom_absSigSum_T_3[50:0]; // @[MulAddRecFN.scala:236:41]
wire [50:0] notCDom_absSigSum = notCDom_signSigSum ? _notCDom_absSigSum_T_1 : _notCDom_absSigSum_T_4; // @[MulAddRecFN.scala:232:36, :234:12, :235:13, :236:41]
wire _notCDom_reduced2AbsSigSum_reducedVec_0_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_1_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_2_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_3_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_4_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_5_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_6_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_7_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_8_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_9_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_10_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_11_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_12_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_13_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_14_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_15_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_16_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_17_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_18_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_19_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_20_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_21_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_22_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_23_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_24_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_25_T_1; // @[primitives.scala:106:57]
wire notCDom_reduced2AbsSigSum_reducedVec_0; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_1; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_2; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_3; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_4; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_5; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_6; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_7; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_8; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_9; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_10; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_11; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_12; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_13; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_14; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_15; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_16; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_17; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_18; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_19; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_20; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_21; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_22; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_23; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_24; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_25; // @[primitives.scala:101:30]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_0_T = notCDom_absSigSum[1:0]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_0_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_0_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_0 = _notCDom_reduced2AbsSigSum_reducedVec_0_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_1_T = notCDom_absSigSum[3:2]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_1_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_1_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_1 = _notCDom_reduced2AbsSigSum_reducedVec_1_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_2_T = notCDom_absSigSum[5:4]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_2_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_2_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_2 = _notCDom_reduced2AbsSigSum_reducedVec_2_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_3_T = notCDom_absSigSum[7:6]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_3_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_3_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_3 = _notCDom_reduced2AbsSigSum_reducedVec_3_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_4_T = notCDom_absSigSum[9:8]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_4_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_4_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_4 = _notCDom_reduced2AbsSigSum_reducedVec_4_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_5_T = notCDom_absSigSum[11:10]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_5_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_5_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_5 = _notCDom_reduced2AbsSigSum_reducedVec_5_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_6_T = notCDom_absSigSum[13:12]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_6_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_6_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_6 = _notCDom_reduced2AbsSigSum_reducedVec_6_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_7_T = notCDom_absSigSum[15:14]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_7_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_7_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_7 = _notCDom_reduced2AbsSigSum_reducedVec_7_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_8_T = notCDom_absSigSum[17:16]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_8_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_8_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_8 = _notCDom_reduced2AbsSigSum_reducedVec_8_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_9_T = notCDom_absSigSum[19:18]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_9_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_9_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_9 = _notCDom_reduced2AbsSigSum_reducedVec_9_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_10_T = notCDom_absSigSum[21:20]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_10_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_10_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_10 = _notCDom_reduced2AbsSigSum_reducedVec_10_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_11_T = notCDom_absSigSum[23:22]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_11_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_11_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_11 = _notCDom_reduced2AbsSigSum_reducedVec_11_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_12_T = notCDom_absSigSum[25:24]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_12_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_12_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_12 = _notCDom_reduced2AbsSigSum_reducedVec_12_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_13_T = notCDom_absSigSum[27:26]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_13_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_13_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_13 = _notCDom_reduced2AbsSigSum_reducedVec_13_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_14_T = notCDom_absSigSum[29:28]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_14_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_14_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_14 = _notCDom_reduced2AbsSigSum_reducedVec_14_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_15_T = notCDom_absSigSum[31:30]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_15_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_15_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_15 = _notCDom_reduced2AbsSigSum_reducedVec_15_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_16_T = notCDom_absSigSum[33:32]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_16_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_16_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_16 = _notCDom_reduced2AbsSigSum_reducedVec_16_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_17_T = notCDom_absSigSum[35:34]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_17_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_17_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_17 = _notCDom_reduced2AbsSigSum_reducedVec_17_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_18_T = notCDom_absSigSum[37:36]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_18_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_18_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_18 = _notCDom_reduced2AbsSigSum_reducedVec_18_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_19_T = notCDom_absSigSum[39:38]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_19_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_19_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_19 = _notCDom_reduced2AbsSigSum_reducedVec_19_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_20_T = notCDom_absSigSum[41:40]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_20_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_20_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_20 = _notCDom_reduced2AbsSigSum_reducedVec_20_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_21_T = notCDom_absSigSum[43:42]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_21_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_21_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_21 = _notCDom_reduced2AbsSigSum_reducedVec_21_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_22_T = notCDom_absSigSum[45:44]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_22_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_22_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_22 = _notCDom_reduced2AbsSigSum_reducedVec_22_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_23_T = notCDom_absSigSum[47:46]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_23_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_23_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_23 = _notCDom_reduced2AbsSigSum_reducedVec_23_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_24_T = notCDom_absSigSum[49:48]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_24_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_24_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_24 = _notCDom_reduced2AbsSigSum_reducedVec_24_T_1; // @[primitives.scala:101:30, :103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_25_T = notCDom_absSigSum[50]; // @[primitives.scala:106:15]
assign _notCDom_reduced2AbsSigSum_reducedVec_25_T_1 = _notCDom_reduced2AbsSigSum_reducedVec_25_T; // @[primitives.scala:106:{15,57}]
assign notCDom_reduced2AbsSigSum_reducedVec_25 = _notCDom_reduced2AbsSigSum_reducedVec_25_T_1; // @[primitives.scala:101:30, :106:57]
wire [1:0] notCDom_reduced2AbsSigSum_lo_lo_lo_hi = {notCDom_reduced2AbsSigSum_reducedVec_2, notCDom_reduced2AbsSigSum_reducedVec_1}; // @[primitives.scala:101:30, :107:20]
wire [2:0] notCDom_reduced2AbsSigSum_lo_lo_lo = {notCDom_reduced2AbsSigSum_lo_lo_lo_hi, notCDom_reduced2AbsSigSum_reducedVec_0}; // @[primitives.scala:101:30, :107:20]
wire [1:0] notCDom_reduced2AbsSigSum_lo_lo_hi_hi = {notCDom_reduced2AbsSigSum_reducedVec_5, notCDom_reduced2AbsSigSum_reducedVec_4}; // @[primitives.scala:101:30, :107:20]
wire [2:0] notCDom_reduced2AbsSigSum_lo_lo_hi = {notCDom_reduced2AbsSigSum_lo_lo_hi_hi, notCDom_reduced2AbsSigSum_reducedVec_3}; // @[primitives.scala:101:30, :107:20]
wire [5:0] notCDom_reduced2AbsSigSum_lo_lo = {notCDom_reduced2AbsSigSum_lo_lo_hi, notCDom_reduced2AbsSigSum_lo_lo_lo}; // @[primitives.scala:107:20]
wire [1:0] notCDom_reduced2AbsSigSum_lo_hi_lo_hi = {notCDom_reduced2AbsSigSum_reducedVec_8, notCDom_reduced2AbsSigSum_reducedVec_7}; // @[primitives.scala:101:30, :107:20]
wire [2:0] notCDom_reduced2AbsSigSum_lo_hi_lo = {notCDom_reduced2AbsSigSum_lo_hi_lo_hi, notCDom_reduced2AbsSigSum_reducedVec_6}; // @[primitives.scala:101:30, :107:20]
wire [1:0] notCDom_reduced2AbsSigSum_lo_hi_hi_lo = {notCDom_reduced2AbsSigSum_reducedVec_10, notCDom_reduced2AbsSigSum_reducedVec_9}; // @[primitives.scala:101:30, :107:20]
wire [1:0] notCDom_reduced2AbsSigSum_lo_hi_hi_hi = {notCDom_reduced2AbsSigSum_reducedVec_12, notCDom_reduced2AbsSigSum_reducedVec_11}; // @[primitives.scala:101:30, :107:20]
wire [3:0] notCDom_reduced2AbsSigSum_lo_hi_hi = {notCDom_reduced2AbsSigSum_lo_hi_hi_hi, notCDom_reduced2AbsSigSum_lo_hi_hi_lo}; // @[primitives.scala:107:20]
wire [6:0] notCDom_reduced2AbsSigSum_lo_hi = {notCDom_reduced2AbsSigSum_lo_hi_hi, notCDom_reduced2AbsSigSum_lo_hi_lo}; // @[primitives.scala:107:20]
wire [12:0] notCDom_reduced2AbsSigSum_lo = {notCDom_reduced2AbsSigSum_lo_hi, notCDom_reduced2AbsSigSum_lo_lo}; // @[primitives.scala:107:20]
wire [1:0] notCDom_reduced2AbsSigSum_hi_lo_lo_hi = {notCDom_reduced2AbsSigSum_reducedVec_15, notCDom_reduced2AbsSigSum_reducedVec_14}; // @[primitives.scala:101:30, :107:20]
wire [2:0] notCDom_reduced2AbsSigSum_hi_lo_lo = {notCDom_reduced2AbsSigSum_hi_lo_lo_hi, notCDom_reduced2AbsSigSum_reducedVec_13}; // @[primitives.scala:101:30, :107:20]
wire [1:0] notCDom_reduced2AbsSigSum_hi_lo_hi_hi = {notCDom_reduced2AbsSigSum_reducedVec_18, notCDom_reduced2AbsSigSum_reducedVec_17}; // @[primitives.scala:101:30, :107:20]
wire [2:0] notCDom_reduced2AbsSigSum_hi_lo_hi = {notCDom_reduced2AbsSigSum_hi_lo_hi_hi, notCDom_reduced2AbsSigSum_reducedVec_16}; // @[primitives.scala:101:30, :107:20]
wire [5:0] notCDom_reduced2AbsSigSum_hi_lo = {notCDom_reduced2AbsSigSum_hi_lo_hi, notCDom_reduced2AbsSigSum_hi_lo_lo}; // @[primitives.scala:107:20]
wire [1:0] notCDom_reduced2AbsSigSum_hi_hi_lo_hi = {notCDom_reduced2AbsSigSum_reducedVec_21, notCDom_reduced2AbsSigSum_reducedVec_20}; // @[primitives.scala:101:30, :107:20]
wire [2:0] notCDom_reduced2AbsSigSum_hi_hi_lo = {notCDom_reduced2AbsSigSum_hi_hi_lo_hi, notCDom_reduced2AbsSigSum_reducedVec_19}; // @[primitives.scala:101:30, :107:20]
wire [1:0] notCDom_reduced2AbsSigSum_hi_hi_hi_lo = {notCDom_reduced2AbsSigSum_reducedVec_23, notCDom_reduced2AbsSigSum_reducedVec_22}; // @[primitives.scala:101:30, :107:20]
wire [1:0] notCDom_reduced2AbsSigSum_hi_hi_hi_hi = {notCDom_reduced2AbsSigSum_reducedVec_25, notCDom_reduced2AbsSigSum_reducedVec_24}; // @[primitives.scala:101:30, :107:20]
wire [3:0] notCDom_reduced2AbsSigSum_hi_hi_hi = {notCDom_reduced2AbsSigSum_hi_hi_hi_hi, notCDom_reduced2AbsSigSum_hi_hi_hi_lo}; // @[primitives.scala:107:20]
wire [6:0] notCDom_reduced2AbsSigSum_hi_hi = {notCDom_reduced2AbsSigSum_hi_hi_hi, notCDom_reduced2AbsSigSum_hi_hi_lo}; // @[primitives.scala:107:20]
wire [12:0] notCDom_reduced2AbsSigSum_hi = {notCDom_reduced2AbsSigSum_hi_hi, notCDom_reduced2AbsSigSum_hi_lo}; // @[primitives.scala:107:20]
wire [25:0] notCDom_reduced2AbsSigSum = {notCDom_reduced2AbsSigSum_hi, notCDom_reduced2AbsSigSum_lo}; // @[primitives.scala:107:20]
wire _notCDom_normDistReduced2_T = notCDom_reduced2AbsSigSum[0]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_1 = notCDom_reduced2AbsSigSum[1]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_2 = notCDom_reduced2AbsSigSum[2]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_3 = notCDom_reduced2AbsSigSum[3]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_4 = notCDom_reduced2AbsSigSum[4]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_5 = notCDom_reduced2AbsSigSum[5]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_6 = notCDom_reduced2AbsSigSum[6]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_7 = notCDom_reduced2AbsSigSum[7]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_8 = notCDom_reduced2AbsSigSum[8]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_9 = notCDom_reduced2AbsSigSum[9]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_10 = notCDom_reduced2AbsSigSum[10]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_11 = notCDom_reduced2AbsSigSum[11]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_12 = notCDom_reduced2AbsSigSum[12]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_13 = notCDom_reduced2AbsSigSum[13]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_14 = notCDom_reduced2AbsSigSum[14]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_15 = notCDom_reduced2AbsSigSum[15]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_16 = notCDom_reduced2AbsSigSum[16]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_17 = notCDom_reduced2AbsSigSum[17]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_18 = notCDom_reduced2AbsSigSum[18]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_19 = notCDom_reduced2AbsSigSum[19]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_20 = notCDom_reduced2AbsSigSum[20]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_21 = notCDom_reduced2AbsSigSum[21]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_22 = notCDom_reduced2AbsSigSum[22]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_23 = notCDom_reduced2AbsSigSum[23]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_24 = notCDom_reduced2AbsSigSum[24]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_25 = notCDom_reduced2AbsSigSum[25]; // @[primitives.scala:91:52, :107:20]
wire [4:0] _notCDom_normDistReduced2_T_26 = {4'hC, ~_notCDom_normDistReduced2_T_1}; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_27 = _notCDom_normDistReduced2_T_2 ? 5'h17 : _notCDom_normDistReduced2_T_26; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_28 = _notCDom_normDistReduced2_T_3 ? 5'h16 : _notCDom_normDistReduced2_T_27; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_29 = _notCDom_normDistReduced2_T_4 ? 5'h15 : _notCDom_normDistReduced2_T_28; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_30 = _notCDom_normDistReduced2_T_5 ? 5'h14 : _notCDom_normDistReduced2_T_29; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_31 = _notCDom_normDistReduced2_T_6 ? 5'h13 : _notCDom_normDistReduced2_T_30; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_32 = _notCDom_normDistReduced2_T_7 ? 5'h12 : _notCDom_normDistReduced2_T_31; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_33 = _notCDom_normDistReduced2_T_8 ? 5'h11 : _notCDom_normDistReduced2_T_32; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_34 = _notCDom_normDistReduced2_T_9 ? 5'h10 : _notCDom_normDistReduced2_T_33; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_35 = _notCDom_normDistReduced2_T_10 ? 5'hF : _notCDom_normDistReduced2_T_34; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_36 = _notCDom_normDistReduced2_T_11 ? 5'hE : _notCDom_normDistReduced2_T_35; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_37 = _notCDom_normDistReduced2_T_12 ? 5'hD : _notCDom_normDistReduced2_T_36; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_38 = _notCDom_normDistReduced2_T_13 ? 5'hC : _notCDom_normDistReduced2_T_37; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_39 = _notCDom_normDistReduced2_T_14 ? 5'hB : _notCDom_normDistReduced2_T_38; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_40 = _notCDom_normDistReduced2_T_15 ? 5'hA : _notCDom_normDistReduced2_T_39; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_41 = _notCDom_normDistReduced2_T_16 ? 5'h9 : _notCDom_normDistReduced2_T_40; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_42 = _notCDom_normDistReduced2_T_17 ? 5'h8 : _notCDom_normDistReduced2_T_41; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_43 = _notCDom_normDistReduced2_T_18 ? 5'h7 : _notCDom_normDistReduced2_T_42; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_44 = _notCDom_normDistReduced2_T_19 ? 5'h6 : _notCDom_normDistReduced2_T_43; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_45 = _notCDom_normDistReduced2_T_20 ? 5'h5 : _notCDom_normDistReduced2_T_44; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_46 = _notCDom_normDistReduced2_T_21 ? 5'h4 : _notCDom_normDistReduced2_T_45; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_47 = _notCDom_normDistReduced2_T_22 ? 5'h3 : _notCDom_normDistReduced2_T_46; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_48 = _notCDom_normDistReduced2_T_23 ? 5'h2 : _notCDom_normDistReduced2_T_47; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_49 = _notCDom_normDistReduced2_T_24 ? 5'h1 : _notCDom_normDistReduced2_T_48; // @[Mux.scala:50:70]
wire [4:0] notCDom_normDistReduced2 = _notCDom_normDistReduced2_T_25 ? 5'h0 : _notCDom_normDistReduced2_T_49; // @[Mux.scala:50:70]
wire [5:0] notCDom_nearNormDist = {notCDom_normDistReduced2, 1'h0}; // @[Mux.scala:50:70]
wire [6:0] _notCDom_sExp_T = {1'h0, notCDom_nearNormDist}; // @[MulAddRecFN.scala:240:56, :241:76]
wire [10:0] _notCDom_sExp_T_1 = _GEN - {{4{_notCDom_sExp_T[6]}}, _notCDom_sExp_T}; // @[MulAddRecFN.scala:203:43, :241:{46,76}]
wire [9:0] _notCDom_sExp_T_2 = _notCDom_sExp_T_1[9:0]; // @[MulAddRecFN.scala:241:46]
wire [9:0] notCDom_sExp = _notCDom_sExp_T_2; // @[MulAddRecFN.scala:241:46]
assign _io_rawOut_sExp_T = notCDom_sExp; // @[MulAddRecFN.scala:241:46, :293:26]
wire [113:0] _notCDom_mainSig_T = {63'h0, notCDom_absSigSum} << notCDom_nearNormDist; // @[MulAddRecFN.scala:234:12, :240:56, :243:27]
wire [28:0] notCDom_mainSig = _notCDom_mainSig_T[51:23]; // @[MulAddRecFN.scala:243:{27,50}]
wire [12:0] _notCDom_reduced4SigExtra_T = notCDom_reduced2AbsSigSum[12:0]; // @[primitives.scala:107:20]
wire [12:0] _notCDom_reduced4SigExtra_T_1 = _notCDom_reduced4SigExtra_T; // @[MulAddRecFN.scala:247:{39,55}]
wire _notCDom_reduced4SigExtra_reducedVec_0_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced4SigExtra_reducedVec_1_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced4SigExtra_reducedVec_2_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced4SigExtra_reducedVec_3_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced4SigExtra_reducedVec_4_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced4SigExtra_reducedVec_5_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced4SigExtra_reducedVec_6_T_1; // @[primitives.scala:106:57]
wire notCDom_reduced4SigExtra_reducedVec_0; // @[primitives.scala:101:30]
wire notCDom_reduced4SigExtra_reducedVec_1; // @[primitives.scala:101:30]
wire notCDom_reduced4SigExtra_reducedVec_2; // @[primitives.scala:101:30]
wire notCDom_reduced4SigExtra_reducedVec_3; // @[primitives.scala:101:30]
wire notCDom_reduced4SigExtra_reducedVec_4; // @[primitives.scala:101:30]
wire notCDom_reduced4SigExtra_reducedVec_5; // @[primitives.scala:101:30]
wire notCDom_reduced4SigExtra_reducedVec_6; // @[primitives.scala:101:30]
wire [1:0] _notCDom_reduced4SigExtra_reducedVec_0_T = _notCDom_reduced4SigExtra_T_1[1:0]; // @[primitives.scala:103:33]
assign _notCDom_reduced4SigExtra_reducedVec_0_T_1 = |_notCDom_reduced4SigExtra_reducedVec_0_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced4SigExtra_reducedVec_0 = _notCDom_reduced4SigExtra_reducedVec_0_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced4SigExtra_reducedVec_1_T = _notCDom_reduced4SigExtra_T_1[3:2]; // @[primitives.scala:103:33]
assign _notCDom_reduced4SigExtra_reducedVec_1_T_1 = |_notCDom_reduced4SigExtra_reducedVec_1_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced4SigExtra_reducedVec_1 = _notCDom_reduced4SigExtra_reducedVec_1_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced4SigExtra_reducedVec_2_T = _notCDom_reduced4SigExtra_T_1[5:4]; // @[primitives.scala:103:33]
assign _notCDom_reduced4SigExtra_reducedVec_2_T_1 = |_notCDom_reduced4SigExtra_reducedVec_2_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced4SigExtra_reducedVec_2 = _notCDom_reduced4SigExtra_reducedVec_2_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced4SigExtra_reducedVec_3_T = _notCDom_reduced4SigExtra_T_1[7:6]; // @[primitives.scala:103:33]
assign _notCDom_reduced4SigExtra_reducedVec_3_T_1 = |_notCDom_reduced4SigExtra_reducedVec_3_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced4SigExtra_reducedVec_3 = _notCDom_reduced4SigExtra_reducedVec_3_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced4SigExtra_reducedVec_4_T = _notCDom_reduced4SigExtra_T_1[9:8]; // @[primitives.scala:103:33]
assign _notCDom_reduced4SigExtra_reducedVec_4_T_1 = |_notCDom_reduced4SigExtra_reducedVec_4_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced4SigExtra_reducedVec_4 = _notCDom_reduced4SigExtra_reducedVec_4_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced4SigExtra_reducedVec_5_T = _notCDom_reduced4SigExtra_T_1[11:10]; // @[primitives.scala:103:33]
assign _notCDom_reduced4SigExtra_reducedVec_5_T_1 = |_notCDom_reduced4SigExtra_reducedVec_5_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced4SigExtra_reducedVec_5 = _notCDom_reduced4SigExtra_reducedVec_5_T_1; // @[primitives.scala:101:30, :103:54]
wire _notCDom_reduced4SigExtra_reducedVec_6_T = _notCDom_reduced4SigExtra_T_1[12]; // @[primitives.scala:106:15]
assign _notCDom_reduced4SigExtra_reducedVec_6_T_1 = _notCDom_reduced4SigExtra_reducedVec_6_T; // @[primitives.scala:106:{15,57}]
assign notCDom_reduced4SigExtra_reducedVec_6 = _notCDom_reduced4SigExtra_reducedVec_6_T_1; // @[primitives.scala:101:30, :106:57]
wire [1:0] notCDom_reduced4SigExtra_lo_hi = {notCDom_reduced4SigExtra_reducedVec_2, notCDom_reduced4SigExtra_reducedVec_1}; // @[primitives.scala:101:30, :107:20]
wire [2:0] notCDom_reduced4SigExtra_lo = {notCDom_reduced4SigExtra_lo_hi, notCDom_reduced4SigExtra_reducedVec_0}; // @[primitives.scala:101:30, :107:20]
wire [1:0] notCDom_reduced4SigExtra_hi_lo = {notCDom_reduced4SigExtra_reducedVec_4, notCDom_reduced4SigExtra_reducedVec_3}; // @[primitives.scala:101:30, :107:20]
wire [1:0] notCDom_reduced4SigExtra_hi_hi = {notCDom_reduced4SigExtra_reducedVec_6, notCDom_reduced4SigExtra_reducedVec_5}; // @[primitives.scala:101:30, :107:20]
wire [3:0] notCDom_reduced4SigExtra_hi = {notCDom_reduced4SigExtra_hi_hi, notCDom_reduced4SigExtra_hi_lo}; // @[primitives.scala:107:20]
wire [6:0] _notCDom_reduced4SigExtra_T_2 = {notCDom_reduced4SigExtra_hi, notCDom_reduced4SigExtra_lo}; // @[primitives.scala:107:20]
wire [3:0] _notCDom_reduced4SigExtra_T_3 = notCDom_normDistReduced2[4:1]; // @[Mux.scala:50:70]
wire [3:0] _notCDom_reduced4SigExtra_T_4 = ~_notCDom_reduced4SigExtra_T_3; // @[primitives.scala:52:21]
wire [16:0] notCDom_reduced4SigExtra_shift = $signed(17'sh10000 >>> _notCDom_reduced4SigExtra_T_4); // @[primitives.scala:52:21, :76:56]
wire [5:0] _notCDom_reduced4SigExtra_T_5 = notCDom_reduced4SigExtra_shift[6:1]; // @[primitives.scala:76:56, :78:22]
wire [3:0] _notCDom_reduced4SigExtra_T_6 = _notCDom_reduced4SigExtra_T_5[3:0]; // @[primitives.scala:77:20, :78:22]
wire [1:0] _notCDom_reduced4SigExtra_T_7 = _notCDom_reduced4SigExtra_T_6[1:0]; // @[primitives.scala:77:20]
wire _notCDom_reduced4SigExtra_T_8 = _notCDom_reduced4SigExtra_T_7[0]; // @[primitives.scala:77:20]
wire _notCDom_reduced4SigExtra_T_9 = _notCDom_reduced4SigExtra_T_7[1]; // @[primitives.scala:77:20]
wire [1:0] _notCDom_reduced4SigExtra_T_10 = {_notCDom_reduced4SigExtra_T_8, _notCDom_reduced4SigExtra_T_9}; // @[primitives.scala:77:20]
wire [1:0] _notCDom_reduced4SigExtra_T_11 = _notCDom_reduced4SigExtra_T_6[3:2]; // @[primitives.scala:77:20]
wire _notCDom_reduced4SigExtra_T_12 = _notCDom_reduced4SigExtra_T_11[0]; // @[primitives.scala:77:20]
wire _notCDom_reduced4SigExtra_T_13 = _notCDom_reduced4SigExtra_T_11[1]; // @[primitives.scala:77:20]
wire [1:0] _notCDom_reduced4SigExtra_T_14 = {_notCDom_reduced4SigExtra_T_12, _notCDom_reduced4SigExtra_T_13}; // @[primitives.scala:77:20]
wire [3:0] _notCDom_reduced4SigExtra_T_15 = {_notCDom_reduced4SigExtra_T_10, _notCDom_reduced4SigExtra_T_14}; // @[primitives.scala:77:20]
wire [1:0] _notCDom_reduced4SigExtra_T_16 = _notCDom_reduced4SigExtra_T_5[5:4]; // @[primitives.scala:77:20, :78:22]
wire _notCDom_reduced4SigExtra_T_17 = _notCDom_reduced4SigExtra_T_16[0]; // @[primitives.scala:77:20]
wire _notCDom_reduced4SigExtra_T_18 = _notCDom_reduced4SigExtra_T_16[1]; // @[primitives.scala:77:20]
wire [1:0] _notCDom_reduced4SigExtra_T_19 = {_notCDom_reduced4SigExtra_T_17, _notCDom_reduced4SigExtra_T_18}; // @[primitives.scala:77:20]
wire [5:0] _notCDom_reduced4SigExtra_T_20 = {_notCDom_reduced4SigExtra_T_15, _notCDom_reduced4SigExtra_T_19}; // @[primitives.scala:77:20]
wire [6:0] _notCDom_reduced4SigExtra_T_21 = {1'h0, _notCDom_reduced4SigExtra_T_2[5:0] & _notCDom_reduced4SigExtra_T_20}; // @[primitives.scala:77:20, :107:20]
wire notCDom_reduced4SigExtra = |_notCDom_reduced4SigExtra_T_21; // @[MulAddRecFN.scala:247:78, :249:11]
wire [25:0] _notCDom_sig_T = notCDom_mainSig[28:3]; // @[MulAddRecFN.scala:243:50, :251:28]
wire [2:0] _notCDom_sig_T_1 = notCDom_mainSig[2:0]; // @[MulAddRecFN.scala:243:50, :252:28]
wire _notCDom_sig_T_2 = |_notCDom_sig_T_1; // @[MulAddRecFN.scala:252:{28,35}]
wire _notCDom_sig_T_3 = _notCDom_sig_T_2 | notCDom_reduced4SigExtra; // @[MulAddRecFN.scala:249:11, :252:{35,39}]
wire [26:0] notCDom_sig = {_notCDom_sig_T, _notCDom_sig_T_3}; // @[MulAddRecFN.scala:251:{12,28}, :252:39]
assign _io_rawOut_sig_T = notCDom_sig; // @[MulAddRecFN.scala:251:12, :294:25]
wire [1:0] _notCDom_completeCancellation_T = notCDom_sig[26:25]; // @[MulAddRecFN.scala:251:12, :255:21]
wire notCDom_completeCancellation = _notCDom_completeCancellation_T == 2'h0; // @[primitives.scala:103:54]
wire _io_rawOut_isZero_T_1 = notCDom_completeCancellation; // @[MulAddRecFN.scala:255:50, :283:42]
wire _notCDom_sign_T = io_fromPreMul_signProd_0 ^ notCDom_signSigSum; // @[MulAddRecFN.scala:169:7, :232:36, :259:36]
wire notCDom_sign = ~notCDom_completeCancellation & _notCDom_sign_T; // @[MulAddRecFN.scala:255:50, :257:12, :259:36]
wire _io_rawOut_sign_T_15 = notCDom_sign; // @[MulAddRecFN.scala:257:12, :292:17]
wire _GEN_0 = io_fromPreMul_isInfA_0 | io_fromPreMul_isInfB_0; // @[MulAddRecFN.scala:169:7, :264:49]
wire notNaN_isInfProd; // @[MulAddRecFN.scala:264:49]
assign notNaN_isInfProd = _GEN_0; // @[MulAddRecFN.scala:264:49]
wire _io_invalidExc_T_5; // @[MulAddRecFN.scala:275:36]
assign _io_invalidExc_T_5 = _GEN_0; // @[MulAddRecFN.scala:264:49, :275:36]
assign notNaN_isInfOut = notNaN_isInfProd; // @[MulAddRecFN.scala:264:49, :265:44]
assign io_rawOut_isInf_0 = notNaN_isInfOut; // @[MulAddRecFN.scala:169:7, :265:44]
wire _notNaN_addZeros_T = io_fromPreMul_isZeroA_0 | io_fromPreMul_isZeroB_0; // @[MulAddRecFN.scala:169:7, :267:32]
wire notNaN_addZeros = _notNaN_addZeros_T; // @[MulAddRecFN.scala:267:{32,58}]
wire _io_rawOut_sign_T_4 = notNaN_addZeros; // @[MulAddRecFN.scala:267:58, :287:26]
wire _io_invalidExc_T = io_fromPreMul_isInfA_0 & io_fromPreMul_isZeroB_0; // @[MulAddRecFN.scala:169:7, :272:31]
wire _io_invalidExc_T_1 = io_fromPreMul_isSigNaNAny_0 | _io_invalidExc_T; // @[MulAddRecFN.scala:169:7, :271:35, :272:31]
wire _io_invalidExc_T_2 = io_fromPreMul_isZeroA_0 & io_fromPreMul_isInfB_0; // @[MulAddRecFN.scala:169:7, :273:32]
wire _io_invalidExc_T_3 = _io_invalidExc_T_1 | _io_invalidExc_T_2; // @[MulAddRecFN.scala:271:35, :272:57, :273:32]
assign _io_invalidExc_T_9 = _io_invalidExc_T_3; // @[MulAddRecFN.scala:272:57, :273:57]
wire _io_invalidExc_T_4 = ~io_fromPreMul_isNaNAOrB_0; // @[MulAddRecFN.scala:169:7, :274:10]
wire _io_invalidExc_T_6 = _io_invalidExc_T_4 & _io_invalidExc_T_5; // @[MulAddRecFN.scala:274:{10,36}, :275:36]
assign io_invalidExc_0 = _io_invalidExc_T_9; // @[MulAddRecFN.scala:169:7, :273:57]
assign io_rawOut_isNaN_0 = _io_rawOut_isNaN_T; // @[MulAddRecFN.scala:169:7, :278:48]
assign _io_rawOut_isZero_T_2 = notNaN_addZeros | _io_rawOut_isZero_T_1; // @[MulAddRecFN.scala:267:58, :282:25, :283:42]
assign io_rawOut_isZero_0 = _io_rawOut_isZero_T_2; // @[MulAddRecFN.scala:169:7, :282:25]
wire _io_rawOut_sign_T = notNaN_isInfProd & io_fromPreMul_signProd_0; // @[MulAddRecFN.scala:169:7, :264:49, :285:27]
wire _io_rawOut_sign_T_2 = _io_rawOut_sign_T; // @[MulAddRecFN.scala:285:{27,54}]
wire _io_rawOut_sign_T_5 = _io_rawOut_sign_T_4 & io_fromPreMul_signProd_0; // @[MulAddRecFN.scala:169:7, :287:{26,48}]
wire _io_rawOut_sign_T_6 = _io_rawOut_sign_T_5 & opSignC; // @[MulAddRecFN.scala:190:42, :287:48, :288:36]
wire _io_rawOut_sign_T_7 = _io_rawOut_sign_T_2 | _io_rawOut_sign_T_6; // @[MulAddRecFN.scala:285:54, :286:43, :288:36]
wire _io_rawOut_sign_T_11 = _io_rawOut_sign_T_7; // @[MulAddRecFN.scala:286:43, :288:48]
wire _io_rawOut_sign_T_9 = io_fromPreMul_signProd_0 | opSignC; // @[MulAddRecFN.scala:169:7, :190:42, :290:37]
wire _io_rawOut_sign_T_12 = ~notNaN_isInfOut; // @[MulAddRecFN.scala:265:44, :291:10]
wire _io_rawOut_sign_T_13 = ~notNaN_addZeros; // @[MulAddRecFN.scala:267:58, :291:31]
wire _io_rawOut_sign_T_14 = _io_rawOut_sign_T_12 & _io_rawOut_sign_T_13; // @[MulAddRecFN.scala:291:{10,28,31}]
wire _io_rawOut_sign_T_16 = _io_rawOut_sign_T_14 & _io_rawOut_sign_T_15; // @[MulAddRecFN.scala:291:{28,49}, :292:17]
assign _io_rawOut_sign_T_17 = _io_rawOut_sign_T_11 | _io_rawOut_sign_T_16; // @[MulAddRecFN.scala:288:48, :290:50, :291:49]
assign io_rawOut_sign_0 = _io_rawOut_sign_T_17; // @[MulAddRecFN.scala:169:7, :290:50]
assign io_rawOut_sExp_0 = _io_rawOut_sExp_T; // @[MulAddRecFN.scala:169:7, :293:26]
assign io_rawOut_sig_0 = _io_rawOut_sig_T; // @[MulAddRecFN.scala:169:7, :294:25]
assign io_invalidExc = io_invalidExc_0; // @[MulAddRecFN.scala:169:7]
assign io_rawOut_isNaN = io_rawOut_isNaN_0; // @[MulAddRecFN.scala:169:7]
assign io_rawOut_isInf = io_rawOut_isInf_0; // @[MulAddRecFN.scala:169:7]
assign io_rawOut_isZero = io_rawOut_isZero_0; // @[MulAddRecFN.scala:169:7]
assign io_rawOut_sign = io_rawOut_sign_0; // @[MulAddRecFN.scala:169:7]
assign io_rawOut_sExp = io_rawOut_sExp_0; // @[MulAddRecFN.scala:169:7]
assign io_rawOut_sig = io_rawOut_sig_0; // @[MulAddRecFN.scala:169:7]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File RecFNToRecFN.scala:
/*============================================================================
This Chisel source file is part of a pre-release version of the HardFloat IEEE
Floating-Point Arithmetic Package, by John R. Hauser (with some contributions
from Yunsup Lee and Andrew Waterman, mainly concerning testing).
Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the
University of California. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
package hardfloat
import chisel3._
import consts._
class
RecFNToRecFN(
inExpWidth: Int, inSigWidth: Int, outExpWidth: Int, outSigWidth: Int)
extends chisel3.RawModule
{
val io = IO(new Bundle {
val in = Input(Bits((inExpWidth + inSigWidth + 1).W))
val roundingMode = Input(UInt(3.W))
val detectTininess = Input(UInt(1.W))
val out = Output(Bits((outExpWidth + outSigWidth + 1).W))
val exceptionFlags = Output(Bits(5.W))
})
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val rawIn = rawFloatFromRecFN(inExpWidth, inSigWidth, io.in);
if ((inExpWidth == outExpWidth) && (inSigWidth <= outSigWidth)) {
//--------------------------------------------------------------------
//--------------------------------------------------------------------
io.out := io.in<<(outSigWidth - inSigWidth)
io.exceptionFlags := isSigNaNRawFloat(rawIn) ## 0.U(4.W)
} else {
//--------------------------------------------------------------------
//--------------------------------------------------------------------
val roundAnyRawFNToRecFN =
Module(
new RoundAnyRawFNToRecFN(
inExpWidth,
inSigWidth,
outExpWidth,
outSigWidth,
flRoundOpt_sigMSBitAlwaysZero
))
roundAnyRawFNToRecFN.io.invalidExc := isSigNaNRawFloat(rawIn)
roundAnyRawFNToRecFN.io.infiniteExc := false.B
roundAnyRawFNToRecFN.io.in := rawIn
roundAnyRawFNToRecFN.io.roundingMode := io.roundingMode
roundAnyRawFNToRecFN.io.detectTininess := io.detectTininess
io.out := roundAnyRawFNToRecFN.io.out
io.exceptionFlags := roundAnyRawFNToRecFN.io.exceptionFlags
}
}
File rawFloatFromRecFN.scala:
/*============================================================================
This Chisel source file is part of a pre-release version of the HardFloat IEEE
Floating-Point Arithmetic Package, by John R. Hauser (with some contributions
from Yunsup Lee and Andrew Waterman, mainly concerning testing).
Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the
University of California. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
package hardfloat
import chisel3._
import chisel3.util._
/*----------------------------------------------------------------------------
| In the result, no more than one of 'isNaN', 'isInf', and 'isZero' will be
| set.
*----------------------------------------------------------------------------*/
object rawFloatFromRecFN
{
def apply(expWidth: Int, sigWidth: Int, in: Bits): RawFloat =
{
val exp = in(expWidth + sigWidth - 1, sigWidth - 1)
val isZero = exp(expWidth, expWidth - 2) === 0.U
val isSpecial = exp(expWidth, expWidth - 1) === 3.U
val out = Wire(new RawFloat(expWidth, sigWidth))
out.isNaN := isSpecial && exp(expWidth - 2)
out.isInf := isSpecial && ! exp(expWidth - 2)
out.isZero := isZero
out.sign := in(expWidth + sigWidth)
out.sExp := exp.zext
out.sig := 0.U(1.W) ## ! isZero ## in(sigWidth - 2, 0)
out
}
}
| module RecFNToRecFN_172( // @[RecFNToRecFN.scala:44:5]
input [32:0] io_in, // @[RecFNToRecFN.scala:48:16]
output [32:0] io_out // @[RecFNToRecFN.scala:48:16]
);
wire [32:0] io_in_0 = io_in; // @[RecFNToRecFN.scala:44:5]
wire io_detectTininess = 1'h1; // @[RecFNToRecFN.scala:44:5, :48:16]
wire [2:0] io_roundingMode = 3'h0; // @[RecFNToRecFN.scala:44:5, :48:16]
wire [32:0] _io_out_T = io_in_0; // @[RecFNToRecFN.scala:44:5, :64:35]
wire [4:0] _io_exceptionFlags_T_3; // @[RecFNToRecFN.scala:65:54]
wire [32:0] io_out_0; // @[RecFNToRecFN.scala:44:5]
wire [4:0] io_exceptionFlags; // @[RecFNToRecFN.scala:44:5]
wire [8:0] rawIn_exp = io_in_0[31:23]; // @[rawFloatFromRecFN.scala:51:21]
wire [2:0] _rawIn_isZero_T = rawIn_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28]
wire rawIn_isZero = _rawIn_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}]
wire rawIn_isZero_0 = rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23]
wire [1:0] _rawIn_isSpecial_T = rawIn_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28]
wire rawIn_isSpecial = &_rawIn_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}]
wire _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33]
wire _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33]
wire _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:59:25]
wire [9:0] _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27]
wire [24:0] _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44]
wire rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23]
wire rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire rawIn_sign; // @[rawFloatFromRecFN.scala:55:23]
wire [9:0] rawIn_sExp; // @[rawFloatFromRecFN.scala:55:23]
wire [24:0] rawIn_sig; // @[rawFloatFromRecFN.scala:55:23]
wire _rawIn_out_isNaN_T = rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41]
wire _rawIn_out_isInf_T = rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41]
assign _rawIn_out_isNaN_T_1 = rawIn_isSpecial & _rawIn_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}]
assign rawIn_isNaN = _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33]
wire _rawIn_out_isInf_T_1 = ~_rawIn_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}]
assign _rawIn_out_isInf_T_2 = rawIn_isSpecial & _rawIn_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}]
assign rawIn_isInf = _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33]
assign _rawIn_out_sign_T = io_in_0[32]; // @[rawFloatFromRecFN.scala:59:25]
assign rawIn_sign = _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25]
assign _rawIn_out_sExp_T = {1'h0, rawIn_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27]
assign rawIn_sExp = _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire _rawIn_out_sig_T = ~rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35]
wire [1:0] _rawIn_out_sig_T_1 = {1'h0, _rawIn_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}]
wire [22:0] _rawIn_out_sig_T_2 = io_in_0[22:0]; // @[rawFloatFromRecFN.scala:61:49]
assign _rawIn_out_sig_T_3 = {_rawIn_out_sig_T_1, _rawIn_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}]
assign rawIn_sig = _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44]
assign io_out_0 = _io_out_T; // @[RecFNToRecFN.scala:44:5, :64:35]
wire _io_exceptionFlags_T = rawIn_sig[22]; // @[rawFloatFromRecFN.scala:55:23]
wire _io_exceptionFlags_T_1 = ~_io_exceptionFlags_T; // @[common.scala:82:{49,56}]
wire _io_exceptionFlags_T_2 = rawIn_isNaN & _io_exceptionFlags_T_1; // @[rawFloatFromRecFN.scala:55:23]
assign _io_exceptionFlags_T_3 = {_io_exceptionFlags_T_2, 4'h0}; // @[common.scala:82:46]
assign io_exceptionFlags = _io_exceptionFlags_T_3; // @[RecFNToRecFN.scala:44:5, :65:54]
assign io_out = io_out_0; // @[RecFNToRecFN.scala:44:5]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File ShiftReg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
// Similar to the Chisel ShiftRegister but allows the user to suggest a
// name to the registers that get instantiated, and
// to provide a reset value.
object ShiftRegInit {
def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T =
(0 until n).foldRight(in) {
case (i, next) => {
val r = RegNext(next, init)
name.foreach { na => r.suggestName(s"${na}_${i}") }
r
}
}
}
/** These wrap behavioral
* shift registers into specific modules to allow for
* backend flows to replace or constrain
* them properly when used for CDC synchronization,
* rather than buffering.
*
* The different types vary in their reset behavior:
* AsyncResetShiftReg -- Asynchronously reset register array
* A W(width) x D(depth) sized array is constructed from D instantiations of a
* W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg,
* but only used for timing applications
*/
abstract class AbstractPipelineReg(w: Int = 1) extends Module {
val io = IO(new Bundle {
val d = Input(UInt(w.W))
val q = Output(UInt(w.W))
}
)
}
object AbstractPipelineReg {
def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = {
val chain = Module(gen)
name.foreach{ chain.suggestName(_) }
chain.io.d := in.asUInt
chain.io.q.asTypeOf(in)
}
}
class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) {
require(depth > 0, "Depth must be greater than 0.")
override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}"
val chain = List.tabulate(depth) { i =>
Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}")
}
chain.last.io.d := io.d
chain.last.io.en := true.B
(chain.init zip chain.tail).foreach { case (sink, source) =>
sink.io.d := source.io.q
sink.io.en := true.B
}
io.q := chain.head.io.q
}
object AsyncResetShiftReg {
def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T =
AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name)
def apply [T <: Data](in: T, depth: Int, name: Option[String]): T =
apply(in, depth, 0, name)
def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T =
apply(in, depth, init.litValue.toInt, name)
def apply [T <: Data](in: T, depth: Int, init: T): T =
apply (in, depth, init.litValue.toInt, None)
}
File AsyncQueue.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util._
case class AsyncQueueParams(
depth: Int = 8,
sync: Int = 3,
safe: Boolean = true,
// If safe is true, then effort is made to resynchronize the crossing indices when either side is reset.
// This makes it safe/possible to reset one side of the crossing (but not the other) when the queue is empty.
narrow: Boolean = false)
// If narrow is true then the read mux is moved to the source side of the crossing.
// This reduces the number of level shifters in the case where the clock crossing is also a voltage crossing,
// at the expense of a combinational path from the sink to the source and back to the sink.
{
require (depth > 0 && isPow2(depth))
require (sync >= 2)
val bits = log2Ceil(depth)
val wires = if (narrow) 1 else depth
}
object AsyncQueueParams {
// When there is only one entry, we don't need narrow.
def singleton(sync: Int = 3, safe: Boolean = true) = AsyncQueueParams(1, sync, safe, false)
}
class AsyncBundleSafety extends Bundle {
val ridx_valid = Input (Bool())
val widx_valid = Output(Bool())
val source_reset_n = Output(Bool())
val sink_reset_n = Input (Bool())
}
class AsyncBundle[T <: Data](private val gen: T, val params: AsyncQueueParams = AsyncQueueParams()) extends Bundle {
// Data-path synchronization
val mem = Output(Vec(params.wires, gen))
val ridx = Input (UInt((params.bits+1).W))
val widx = Output(UInt((params.bits+1).W))
val index = params.narrow.option(Input(UInt(params.bits.W)))
// Signals used to self-stabilize a safe AsyncQueue
val safe = params.safe.option(new AsyncBundleSafety)
}
object GrayCounter {
def apply(bits: Int, increment: Bool = true.B, clear: Bool = false.B, name: String = "binary"): UInt = {
val incremented = Wire(UInt(bits.W))
val binary = RegNext(next=incremented, init=0.U).suggestName(name)
incremented := Mux(clear, 0.U, binary + increment.asUInt)
incremented ^ (incremented >> 1)
}
}
class AsyncValidSync(sync: Int, desc: String) extends RawModule {
val io = IO(new Bundle {
val in = Input(Bool())
val out = Output(Bool())
})
val clock = IO(Input(Clock()))
val reset = IO(Input(AsyncReset()))
withClockAndReset(clock, reset){
io.out := AsyncResetSynchronizerShiftReg(io.in, sync, Some(desc))
}
}
class AsyncQueueSource[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module {
override def desiredName = s"AsyncQueueSource_${gen.typeName}"
val io = IO(new Bundle {
// These come from the source domain
val enq = Flipped(Decoupled(gen))
// These cross to the sink clock domain
val async = new AsyncBundle(gen, params)
})
val bits = params.bits
val sink_ready = WireInit(true.B)
val mem = Reg(Vec(params.depth, gen)) // This does NOT need to be reset at all.
val widx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.enq.fire, !sink_ready, "widx_bin"))
val ridx = AsyncResetSynchronizerShiftReg(io.async.ridx, params.sync, Some("ridx_gray"))
val ready = sink_ready && widx =/= (ridx ^ (params.depth | params.depth >> 1).U)
val index = if (bits == 0) 0.U else io.async.widx(bits-1, 0) ^ (io.async.widx(bits, bits) << (bits-1))
when (io.enq.fire) { mem(index) := io.enq.bits }
val ready_reg = withReset(reset.asAsyncReset)(RegNext(next=ready, init=false.B).suggestName("ready_reg"))
io.enq.ready := ready_reg && sink_ready
val widx_reg = withReset(reset.asAsyncReset)(RegNext(next=widx, init=0.U).suggestName("widx_gray"))
io.async.widx := widx_reg
io.async.index match {
case Some(index) => io.async.mem(0) := mem(index)
case None => io.async.mem := mem
}
io.async.safe.foreach { sio =>
val source_valid_0 = Module(new AsyncValidSync(params.sync, "source_valid_0"))
val source_valid_1 = Module(new AsyncValidSync(params.sync, "source_valid_1"))
val sink_extend = Module(new AsyncValidSync(params.sync, "sink_extend"))
val sink_valid = Module(new AsyncValidSync(params.sync, "sink_valid"))
source_valid_0.reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset
source_valid_1.reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset
sink_extend .reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset
sink_valid .reset := reset.asAsyncReset
source_valid_0.clock := clock
source_valid_1.clock := clock
sink_extend .clock := clock
sink_valid .clock := clock
source_valid_0.io.in := true.B
source_valid_1.io.in := source_valid_0.io.out
sio.widx_valid := source_valid_1.io.out
sink_extend.io.in := sio.ridx_valid
sink_valid.io.in := sink_extend.io.out
sink_ready := sink_valid.io.out
sio.source_reset_n := !reset.asBool
// Assert that if there is stuff in the queue, then reset cannot happen
// Impossible to write because dequeue can occur on the receiving side,
// then reset allowed to happen, but write side cannot know that dequeue
// occurred.
// TODO: write some sort of sanity check assertion for users
// that denote don't reset when there is activity
// assert (!(reset || !sio.sink_reset_n) || !io.enq.valid, "Enqueue while sink is reset and AsyncQueueSource is unprotected")
// assert (!reset_rise || prev_idx_match.asBool, "Sink reset while AsyncQueueSource not empty")
}
}
class AsyncQueueSink[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module {
override def desiredName = s"AsyncQueueSink_${gen.typeName}"
val io = IO(new Bundle {
// These come from the sink domain
val deq = Decoupled(gen)
// These cross to the source clock domain
val async = Flipped(new AsyncBundle(gen, params))
})
val bits = params.bits
val source_ready = WireInit(true.B)
val ridx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.deq.fire, !source_ready, "ridx_bin"))
val widx = AsyncResetSynchronizerShiftReg(io.async.widx, params.sync, Some("widx_gray"))
val valid = source_ready && ridx =/= widx
// The mux is safe because timing analysis ensures ridx has reached the register
// On an ASIC, changes to the unread location cannot affect the selected value
// On an FPGA, only one input changes at a time => mem updates don't cause glitches
// The register only latches when the selected valued is not being written
val index = if (bits == 0) 0.U else ridx(bits-1, 0) ^ (ridx(bits, bits) << (bits-1))
io.async.index.foreach { _ := index }
// This register does not NEED to be reset, as its contents will not
// be considered unless the asynchronously reset deq valid register is set.
// It is possible that bits latches when the source domain is reset / has power cut
// This is safe, because isolation gates brought mem low before the zeroed widx reached us
val deq_bits_nxt = io.async.mem(if (params.narrow) 0.U else index)
io.deq.bits := ClockCrossingReg(deq_bits_nxt, en = valid, doInit = false, name = Some("deq_bits_reg"))
val valid_reg = withReset(reset.asAsyncReset)(RegNext(next=valid, init=false.B).suggestName("valid_reg"))
io.deq.valid := valid_reg && source_ready
val ridx_reg = withReset(reset.asAsyncReset)(RegNext(next=ridx, init=0.U).suggestName("ridx_gray"))
io.async.ridx := ridx_reg
io.async.safe.foreach { sio =>
val sink_valid_0 = Module(new AsyncValidSync(params.sync, "sink_valid_0"))
val sink_valid_1 = Module(new AsyncValidSync(params.sync, "sink_valid_1"))
val source_extend = Module(new AsyncValidSync(params.sync, "source_extend"))
val source_valid = Module(new AsyncValidSync(params.sync, "source_valid"))
sink_valid_0 .reset := (reset.asBool || !sio.source_reset_n).asAsyncReset
sink_valid_1 .reset := (reset.asBool || !sio.source_reset_n).asAsyncReset
source_extend.reset := (reset.asBool || !sio.source_reset_n).asAsyncReset
source_valid .reset := reset.asAsyncReset
sink_valid_0 .clock := clock
sink_valid_1 .clock := clock
source_extend.clock := clock
source_valid .clock := clock
sink_valid_0.io.in := true.B
sink_valid_1.io.in := sink_valid_0.io.out
sio.ridx_valid := sink_valid_1.io.out
source_extend.io.in := sio.widx_valid
source_valid.io.in := source_extend.io.out
source_ready := source_valid.io.out
sio.sink_reset_n := !reset.asBool
// TODO: write some sort of sanity check assertion for users
// that denote don't reset when there is activity
//
// val reset_and_extend = !source_ready || !sio.source_reset_n || reset.asBool
// val reset_and_extend_prev = RegNext(reset_and_extend, true.B)
// val reset_rise = !reset_and_extend_prev && reset_and_extend
// val prev_idx_match = AsyncResetReg(updateData=(io.async.widx===io.async.ridx), resetData=0)
// assert (!reset_rise || prev_idx_match.asBool, "Source reset while AsyncQueueSink not empty")
}
}
object FromAsyncBundle
{
// Sometimes it makes sense for the sink to have different sync than the source
def apply[T <: Data](x: AsyncBundle[T]): DecoupledIO[T] = apply(x, x.params.sync)
def apply[T <: Data](x: AsyncBundle[T], sync: Int): DecoupledIO[T] = {
val sink = Module(new AsyncQueueSink(chiselTypeOf(x.mem(0)), x.params.copy(sync = sync)))
sink.io.async <> x
sink.io.deq
}
}
object ToAsyncBundle
{
def apply[T <: Data](x: ReadyValidIO[T], params: AsyncQueueParams = AsyncQueueParams()): AsyncBundle[T] = {
val source = Module(new AsyncQueueSource(chiselTypeOf(x.bits), params))
source.io.enq <> x
source.io.async
}
}
class AsyncQueue[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Crossing[T] {
val io = IO(new CrossingIO(gen))
val source = withClockAndReset(io.enq_clock, io.enq_reset) { Module(new AsyncQueueSource(gen, params)) }
val sink = withClockAndReset(io.deq_clock, io.deq_reset) { Module(new AsyncQueueSink (gen, params)) }
source.io.enq <> io.enq
io.deq <> sink.io.deq
sink.io.async <> source.io.async
}
| module AsyncValidSync_125( // @[AsyncQueue.scala:58:7]
input io_in, // @[AsyncQueue.scala:59:14]
output io_out, // @[AsyncQueue.scala:59:14]
input clock, // @[AsyncQueue.scala:63:17]
input reset // @[AsyncQueue.scala:64:17]
);
wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7]
wire _io_out_WIRE; // @[ShiftReg.scala:48:24]
wire io_out_0; // @[AsyncQueue.scala:58:7]
assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24]
AsyncResetSynchronizerShiftReg_w1_d3_i0_142 io_out_sink_valid_1 ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (reset),
.io_d (io_in_0), // @[AsyncQueue.scala:58:7]
.io_q (_io_out_WIRE)
); // @[ShiftReg.scala:45:23]
assign io_out = io_out_0; // @[AsyncQueue.scala:58:7]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File RoundAnyRawFNToRecFN.scala:
/*============================================================================
This Chisel source file is part of a pre-release version of the HardFloat IEEE
Floating-Point Arithmetic Package, by John R. Hauser (with some contributions
from Yunsup Lee and Andrew Waterman, mainly concerning testing).
Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
University of California. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
package hardfloat
import chisel3._
import chisel3.util.Fill
import consts._
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
class
RoundAnyRawFNToRecFN(
inExpWidth: Int,
inSigWidth: Int,
outExpWidth: Int,
outSigWidth: Int,
options: Int
)
extends RawModule
{
override def desiredName = s"RoundAnyRawFNToRecFN_ie${inExpWidth}_is${inSigWidth}_oe${outExpWidth}_os${outSigWidth}"
val io = IO(new Bundle {
val invalidExc = Input(Bool()) // overrides 'infiniteExc' and 'in'
val infiniteExc = Input(Bool()) // overrides 'in' except for 'in.sign'
val in = Input(new RawFloat(inExpWidth, inSigWidth))
// (allowed exponent range has limits)
val roundingMode = Input(UInt(3.W))
val detectTininess = Input(UInt(1.W))
val out = Output(Bits((outExpWidth + outSigWidth + 1).W))
val exceptionFlags = Output(Bits(5.W))
})
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val sigMSBitAlwaysZero = ((options & flRoundOpt_sigMSBitAlwaysZero) != 0)
val effectiveInSigWidth =
if (sigMSBitAlwaysZero) inSigWidth else inSigWidth + 1
val neverUnderflows =
((options &
(flRoundOpt_neverUnderflows | flRoundOpt_subnormsAlwaysExact)
) != 0) ||
(inExpWidth < outExpWidth)
val neverOverflows =
((options & flRoundOpt_neverOverflows) != 0) ||
(inExpWidth < outExpWidth)
val outNaNExp = BigInt(7)<<(outExpWidth - 2)
val outInfExp = BigInt(6)<<(outExpWidth - 2)
val outMaxFiniteExp = outInfExp - 1
val outMinNormExp = (BigInt(1)<<(outExpWidth - 1)) + 2
val outMinNonzeroExp = outMinNormExp - outSigWidth + 1
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val roundingMode_near_even = (io.roundingMode === round_near_even)
val roundingMode_minMag = (io.roundingMode === round_minMag)
val roundingMode_min = (io.roundingMode === round_min)
val roundingMode_max = (io.roundingMode === round_max)
val roundingMode_near_maxMag = (io.roundingMode === round_near_maxMag)
val roundingMode_odd = (io.roundingMode === round_odd)
val roundMagUp =
(roundingMode_min && io.in.sign) || (roundingMode_max && ! io.in.sign)
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val sAdjustedExp =
if (inExpWidth < outExpWidth)
(io.in.sExp +&
((BigInt(1)<<outExpWidth) - (BigInt(1)<<inExpWidth)).S
)(outExpWidth, 0).zext
else if (inExpWidth == outExpWidth)
io.in.sExp
else
io.in.sExp +&
((BigInt(1)<<outExpWidth) - (BigInt(1)<<inExpWidth)).S
val adjustedSig =
if (inSigWidth <= outSigWidth + 2)
io.in.sig<<(outSigWidth - inSigWidth + 2)
else
(io.in.sig(inSigWidth, inSigWidth - outSigWidth - 1) ##
io.in.sig(inSigWidth - outSigWidth - 2, 0).orR
)
val doShiftSigDown1 =
if (sigMSBitAlwaysZero) false.B else adjustedSig(outSigWidth + 2)
val common_expOut = Wire(UInt((outExpWidth + 1).W))
val common_fractOut = Wire(UInt((outSigWidth - 1).W))
val common_overflow = Wire(Bool())
val common_totalUnderflow = Wire(Bool())
val common_underflow = Wire(Bool())
val common_inexact = Wire(Bool())
if (
neverOverflows && neverUnderflows
&& (effectiveInSigWidth <= outSigWidth)
) {
//--------------------------------------------------------------------
//--------------------------------------------------------------------
common_expOut := sAdjustedExp(outExpWidth, 0) + doShiftSigDown1
common_fractOut :=
Mux(doShiftSigDown1,
adjustedSig(outSigWidth + 1, 3),
adjustedSig(outSigWidth, 2)
)
common_overflow := false.B
common_totalUnderflow := false.B
common_underflow := false.B
common_inexact := false.B
} else {
//--------------------------------------------------------------------
//--------------------------------------------------------------------
val roundMask =
if (neverUnderflows)
0.U(outSigWidth.W) ## doShiftSigDown1 ## 3.U(2.W)
else
(lowMask(
sAdjustedExp(outExpWidth, 0),
outMinNormExp - outSigWidth - 1,
outMinNormExp
) | doShiftSigDown1) ##
3.U(2.W)
val shiftedRoundMask = 0.U(1.W) ## roundMask>>1
val roundPosMask = ~shiftedRoundMask & roundMask
val roundPosBit = (adjustedSig & roundPosMask).orR
val anyRoundExtra = (adjustedSig & shiftedRoundMask).orR
val anyRound = roundPosBit || anyRoundExtra
val roundIncr =
((roundingMode_near_even || roundingMode_near_maxMag) &&
roundPosBit) ||
(roundMagUp && anyRound)
val roundedSig: Bits =
Mux(roundIncr,
(((adjustedSig | roundMask)>>2) +& 1.U) &
~Mux(roundingMode_near_even && roundPosBit &&
! anyRoundExtra,
roundMask>>1,
0.U((outSigWidth + 2).W)
),
(adjustedSig & ~roundMask)>>2 |
Mux(roundingMode_odd && anyRound, roundPosMask>>1, 0.U)
)
//*** IF SIG WIDTH IS VERY NARROW, NEED TO ACCOUNT FOR ROUND-EVEN ZEROING
//*** M.S. BIT OF SUBNORMAL SIG?
val sRoundedExp = sAdjustedExp +& (roundedSig>>outSigWidth).asUInt.zext
common_expOut := sRoundedExp(outExpWidth, 0)
common_fractOut :=
Mux(doShiftSigDown1,
roundedSig(outSigWidth - 1, 1),
roundedSig(outSigWidth - 2, 0)
)
common_overflow :=
(if (neverOverflows) false.B else
//*** REWRITE BASED ON BEFORE-ROUNDING EXPONENT?:
(sRoundedExp>>(outExpWidth - 1) >= 3.S))
common_totalUnderflow :=
(if (neverUnderflows) false.B else
//*** WOULD BE GOOD ENOUGH TO USE EXPONENT BEFORE ROUNDING?:
(sRoundedExp < outMinNonzeroExp.S))
val unboundedRange_roundPosBit =
Mux(doShiftSigDown1, adjustedSig(2), adjustedSig(1))
val unboundedRange_anyRound =
(doShiftSigDown1 && adjustedSig(2)) || adjustedSig(1, 0).orR
val unboundedRange_roundIncr =
((roundingMode_near_even || roundingMode_near_maxMag) &&
unboundedRange_roundPosBit) ||
(roundMagUp && unboundedRange_anyRound)
val roundCarry =
Mux(doShiftSigDown1,
roundedSig(outSigWidth + 1),
roundedSig(outSigWidth)
)
common_underflow :=
(if (neverUnderflows) false.B else
common_totalUnderflow ||
//*** IF SIG WIDTH IS VERY NARROW, NEED TO ACCOUNT FOR ROUND-EVEN ZEROING
//*** M.S. BIT OF SUBNORMAL SIG?
(anyRound && ((sAdjustedExp>>outExpWidth) <= 0.S) &&
Mux(doShiftSigDown1, roundMask(3), roundMask(2)) &&
! ((io.detectTininess === tininess_afterRounding) &&
! Mux(doShiftSigDown1,
roundMask(4),
roundMask(3)
) &&
roundCarry && roundPosBit &&
unboundedRange_roundIncr)))
common_inexact := common_totalUnderflow || anyRound
}
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val isNaNOut = io.invalidExc || io.in.isNaN
val notNaN_isSpecialInfOut = io.infiniteExc || io.in.isInf
val commonCase = ! isNaNOut && ! notNaN_isSpecialInfOut && ! io.in.isZero
val overflow = commonCase && common_overflow
val underflow = commonCase && common_underflow
val inexact = overflow || (commonCase && common_inexact)
val overflow_roundMagUp =
roundingMode_near_even || roundingMode_near_maxMag || roundMagUp
val pegMinNonzeroMagOut =
commonCase && common_totalUnderflow && (roundMagUp || roundingMode_odd)
val pegMaxFiniteMagOut = overflow && ! overflow_roundMagUp
val notNaN_isInfOut =
notNaN_isSpecialInfOut || (overflow && overflow_roundMagUp)
val signOut = Mux(isNaNOut, false.B, io.in.sign)
val expOut =
(common_expOut &
~Mux(io.in.isZero || common_totalUnderflow,
(BigInt(7)<<(outExpWidth - 2)).U((outExpWidth + 1).W),
0.U
) &
~Mux(pegMinNonzeroMagOut,
~outMinNonzeroExp.U((outExpWidth + 1).W),
0.U
) &
~Mux(pegMaxFiniteMagOut,
(BigInt(1)<<(outExpWidth - 1)).U((outExpWidth + 1).W),
0.U
) &
~Mux(notNaN_isInfOut,
(BigInt(1)<<(outExpWidth - 2)).U((outExpWidth + 1).W),
0.U
)) |
Mux(pegMinNonzeroMagOut,
outMinNonzeroExp.U((outExpWidth + 1).W),
0.U
) |
Mux(pegMaxFiniteMagOut,
outMaxFiniteExp.U((outExpWidth + 1).W),
0.U
) |
Mux(notNaN_isInfOut, outInfExp.U((outExpWidth + 1).W), 0.U) |
Mux(isNaNOut, outNaNExp.U((outExpWidth + 1).W), 0.U)
val fractOut =
Mux(isNaNOut || io.in.isZero || common_totalUnderflow,
Mux(isNaNOut, (BigInt(1)<<(outSigWidth - 2)).U, 0.U),
common_fractOut
) |
Fill(outSigWidth - 1, pegMaxFiniteMagOut)
io.out := signOut ## expOut ## fractOut
io.exceptionFlags :=
io.invalidExc ## io.infiniteExc ## overflow ## underflow ## inexact
}
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
class
RoundRawFNToRecFN(expWidth: Int, sigWidth: Int, options: Int)
extends RawModule
{
override def desiredName = s"RoundRawFNToRecFN_e${expWidth}_s${sigWidth}"
val io = IO(new Bundle {
val invalidExc = Input(Bool()) // overrides 'infiniteExc' and 'in'
val infiniteExc = Input(Bool()) // overrides 'in' except for 'in.sign'
val in = Input(new RawFloat(expWidth, sigWidth + 2))
val roundingMode = Input(UInt(3.W))
val detectTininess = Input(UInt(1.W))
val out = Output(Bits((expWidth + sigWidth + 1).W))
val exceptionFlags = Output(Bits(5.W))
})
val roundAnyRawFNToRecFN =
Module(
new RoundAnyRawFNToRecFN(
expWidth, sigWidth + 2, expWidth, sigWidth, options))
roundAnyRawFNToRecFN.io.invalidExc := io.invalidExc
roundAnyRawFNToRecFN.io.infiniteExc := io.infiniteExc
roundAnyRawFNToRecFN.io.in := io.in
roundAnyRawFNToRecFN.io.roundingMode := io.roundingMode
roundAnyRawFNToRecFN.io.detectTininess := io.detectTininess
io.out := roundAnyRawFNToRecFN.io.out
io.exceptionFlags := roundAnyRawFNToRecFN.io.exceptionFlags
}
| module RoundRawFNToRecFN_e8_s24_50( // @[RoundAnyRawFNToRecFN.scala:295:5]
input io_invalidExc, // @[RoundAnyRawFNToRecFN.scala:299:16]
input io_in_isNaN, // @[RoundAnyRawFNToRecFN.scala:299:16]
input io_in_isInf, // @[RoundAnyRawFNToRecFN.scala:299:16]
input io_in_isZero, // @[RoundAnyRawFNToRecFN.scala:299:16]
input io_in_sign, // @[RoundAnyRawFNToRecFN.scala:299:16]
input [9:0] io_in_sExp, // @[RoundAnyRawFNToRecFN.scala:299:16]
input [26:0] io_in_sig, // @[RoundAnyRawFNToRecFN.scala:299:16]
output [32:0] io_out, // @[RoundAnyRawFNToRecFN.scala:299:16]
output [4:0] io_exceptionFlags // @[RoundAnyRawFNToRecFN.scala:299:16]
);
wire io_invalidExc_0 = io_invalidExc; // @[RoundAnyRawFNToRecFN.scala:295:5]
wire io_in_isNaN_0 = io_in_isNaN; // @[RoundAnyRawFNToRecFN.scala:295:5]
wire io_in_isInf_0 = io_in_isInf; // @[RoundAnyRawFNToRecFN.scala:295:5]
wire io_in_isZero_0 = io_in_isZero; // @[RoundAnyRawFNToRecFN.scala:295:5]
wire io_in_sign_0 = io_in_sign; // @[RoundAnyRawFNToRecFN.scala:295:5]
wire [9:0] io_in_sExp_0 = io_in_sExp; // @[RoundAnyRawFNToRecFN.scala:295:5]
wire [26:0] io_in_sig_0 = io_in_sig; // @[RoundAnyRawFNToRecFN.scala:295:5]
wire io_detectTininess = 1'h1; // @[RoundAnyRawFNToRecFN.scala:295:5, :299:16, :310:15]
wire [2:0] io_roundingMode = 3'h0; // @[RoundAnyRawFNToRecFN.scala:295:5, :299:16, :310:15]
wire io_infiniteExc = 1'h0; // @[RoundAnyRawFNToRecFN.scala:295:5, :299:16, :310:15]
wire [32:0] io_out_0; // @[RoundAnyRawFNToRecFN.scala:295:5]
wire [4:0] io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:295:5]
RoundAnyRawFNToRecFN_ie8_is26_oe8_os24_50 roundAnyRawFNToRecFN ( // @[RoundAnyRawFNToRecFN.scala:310:15]
.io_invalidExc (io_invalidExc_0), // @[RoundAnyRawFNToRecFN.scala:295:5]
.io_in_isNaN (io_in_isNaN_0), // @[RoundAnyRawFNToRecFN.scala:295:5]
.io_in_isInf (io_in_isInf_0), // @[RoundAnyRawFNToRecFN.scala:295:5]
.io_in_isZero (io_in_isZero_0), // @[RoundAnyRawFNToRecFN.scala:295:5]
.io_in_sign (io_in_sign_0), // @[RoundAnyRawFNToRecFN.scala:295:5]
.io_in_sExp (io_in_sExp_0), // @[RoundAnyRawFNToRecFN.scala:295:5]
.io_in_sig (io_in_sig_0), // @[RoundAnyRawFNToRecFN.scala:295:5]
.io_out (io_out_0),
.io_exceptionFlags (io_exceptionFlags_0)
); // @[RoundAnyRawFNToRecFN.scala:310:15]
assign io_out = io_out_0; // @[RoundAnyRawFNToRecFN.scala:295:5]
assign io_exceptionFlags = io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:295:5]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File HistoryBufferSRAM.scala:
package compressacc
import chisel3._
import chisel3.util._
import chisel3.{Printable, SyncReadMem}
import freechips.rocketchip.tile._
import org.chipsalliance.cde.config._
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.rocket.{TLBConfig}
import freechips.rocketchip.util.DecoupledHelper
import freechips.rocketchip.rocket.constants.MemoryOpConstants
// there is no offset here, because we always just add on at the current
// pointer
class HBSRAMWrite extends Bundle {
val data = UInt(256.W)
val valid_bytes = UInt(6.W)
}
class HBSRAMReadReq extends Bundle {
val offset = UInt(48.W)
}
class HBSRAMReadResp extends Bundle {
val data = UInt(256.W)
}
class HBSRAMAdvanceReadPtr extends Bundle {
val advance_bytes = UInt(6.W)
}
/*
* This block maintains the history of everything that has been
* loaded from a buffer to compress. It runs at least one cycle
* AHEAD of the state machine doing compression, so that handling
* cases where the offset is less than 32B is easy.
*
* The write interface is "valid" only, it does not have the ability
* to backpressure.
*/
class HistoryBufferSRAM()(implicit p: Parameters) extends Module with MemoryOpConstants {
val io = IO(new Bundle {
val writes_in = Flipped((Valid(new HBSRAMWrite)))
// these valids are technically not necessary, but useful for debugging/
// tracking purposes
val read_req_in = Flipped((Valid(new HBSRAMReadReq)))
val read_resp_out = (Valid(new HBSRAMReadResp))
val read_advance_ptr = Flipped((Valid(new HBSRAMAdvanceReadPtr)))
})
println(s"HIST BUF OVERPROV FACTOR: ${p(LZ77HistBufOverProvisionFactor)}")
val HIST_BUF_WIDTH = 32
val HIST_BUF_ELEMS_PER_CHUNK = 4 * 512 * p(LZ77HistBufOverProvisionFactor)
val HIST_SIZE_BYTES = HIST_BUF_WIDTH * HIST_BUF_ELEMS_PER_CHUNK
val HIST_BUF_INDEX_WIDTH = log2Up(HIST_SIZE_BYTES)
val BYTE_SIZE = 8
println(s"HIST BUF WIDTH: ${HIST_BUF_WIDTH}")
println(s"HIST BUF ELEMS PER CHUNK: ${HIST_BUF_ELEMS_PER_CHUNK}")
println(s"TOTAL HIST BUF SIZE (B): ${HIST_SIZE_BYTES}")
val recent_history_vec = Array.fill(HIST_BUF_WIDTH) {SyncReadMem(HIST_BUF_ELEMS_PER_CHUNK, UInt(BYTE_SIZE.W))}
val read_indexing_vec = Wire(Vec(HIST_BUF_WIDTH, UInt(HIST_BUF_INDEX_WIDTH.W)))
val read_ports_vec = Wire(Vec(HIST_BUF_WIDTH, UInt(BYTE_SIZE.W)))
for (i <- 0 until HIST_BUF_WIDTH) {
read_indexing_vec(i) := DontCare
}
// shift amount to remove memindex part of addr (low # of bits required to count HIST BUF WIDTH items)
val MEMINDEX_BITS = log2Up(HIST_BUF_WIDTH)
// mask to get only memindex part of addr
val MEMINDEX_MASK = (1 << MEMINDEX_BITS) - 1
// HANDLE READS:
val read_addr_ptr = RegInit(0.U(HIST_BUF_INDEX_WIDTH.W))
when (io.read_advance_ptr.valid) {
// TODO: should an ongoing read account for advance_bytes?
read_addr_ptr := read_addr_ptr + io.read_advance_ptr.bits.advance_bytes
}
val read_result_valid = RegNext(io.read_req_in.valid)
val read_result_addr_ptr = RegNext(read_addr_ptr)
val read_result_offset = RegNext(io.read_req_in.bits.offset)
io.read_resp_out.valid := read_result_valid
for (elemno <- 0 until HIST_BUF_WIDTH) {
read_ports_vec(elemno) := recent_history_vec(elemno)(read_indexing_vec(elemno))
}
for (elemno <- 0 until HIST_BUF_WIDTH) {
val read_memaddr = (read_addr_ptr + 32.U - io.read_req_in.bits.offset - elemno.U - 1.U) >> MEMINDEX_BITS
val read_memno = (read_addr_ptr + 32.U - io.read_req_in.bits.offset - elemno.U - 1.U) & MEMINDEX_MASK.U
read_indexing_vec(read_memno) := read_memaddr
when (io.read_req_in.valid) {
CompressAccelLogger.logInfo("issued hist_read(elemno:%d): from memno:%d,memaddr:%d\n", elemno.U, read_memno, read_memaddr)
}
}
val read_output_vec = Wire(Vec(HIST_BUF_WIDTH, UInt(BYTE_SIZE.W)))
for (elemno <- 0 until HIST_BUF_WIDTH) {
// get read data
val read_memaddr = (read_result_addr_ptr + 32.U - read_result_offset - elemno.U - 1.U) >> MEMINDEX_BITS
val read_memno = (read_result_addr_ptr + 32.U - read_result_offset - elemno.U - 1.U) & MEMINDEX_MASK.U
read_output_vec(elemno) := read_ports_vec(read_memno)
val print_read_ports_vec = Wire(UInt(BYTE_SIZE.W))
print_read_ports_vec := read_ports_vec(read_memno)
when (read_result_valid) {
CompressAccelLogger.logInfo("got hist_read(elemno:%d): from memno:%d,memaddr:%d = val:0x%x\n", elemno.U, read_memno, read_memaddr, print_read_ports_vec)
}
}
io.read_resp_out.bits.data := Cat(read_output_vec)
when (read_result_valid) {
CompressAccelLogger.logInfo("read_resp: 0x%x\n", io.read_resp_out.bits.data)
}
// HANDLE WRITES:
val write_addr_ptr = RegInit(0.U(HIST_BUF_INDEX_WIDTH.W))
when (io.writes_in.valid) {
write_addr_ptr := write_addr_ptr + io.writes_in.bits.valid_bytes
}
val write_indexing_vec = Wire(Vec(HIST_BUF_WIDTH, UInt(HIST_BUF_INDEX_WIDTH.W)))
val write_ports_vec = Wire(Vec(HIST_BUF_WIDTH, UInt(BYTE_SIZE.W)))
val write_ports_write_enable = Wire(Vec(HIST_BUF_WIDTH, Bool()))
for (elemno <- 0 until HIST_BUF_WIDTH) {
write_ports_write_enable(elemno) := false.B
write_indexing_vec(elemno) := DontCare
write_ports_vec(elemno) := DontCare
}
for (elemno <- 0 until HIST_BUF_WIDTH) {
when (write_ports_write_enable(elemno)) {
recent_history_vec(elemno)(write_indexing_vec(elemno)) := write_ports_vec(elemno)
}
}
val recent_history_vec_next = Wire(Vec(HIST_BUF_WIDTH, UInt(BYTE_SIZE.W)))
for (elemno <- 0 until HIST_BUF_WIDTH) {
recent_history_vec_next(elemno) := DontCare
}
for (elemno <- 0 until HIST_BUF_WIDTH) {
recent_history_vec_next(io.writes_in.bits.valid_bytes - elemno.U - 1.U) := io.writes_in.bits.data(((elemno+1) << 3) - 1, elemno << 3)
}
for (elemno <- 0 until HIST_BUF_WIDTH) {
when (io.writes_in.valid && (elemno.U(MEMINDEX_BITS.W) < io.writes_in.bits.valid_bytes)) {
val full_address = write_addr_ptr + io.writes_in.bits.valid_bytes - elemno.U - 1.U
val memno = full_address & (MEMINDEX_MASK).U
val memaddr = full_address >> MEMINDEX_BITS
write_indexing_vec(memno) := memaddr
write_ports_vec(memno) := recent_history_vec_next(elemno)
write_ports_write_enable(memno) := true.B
val print_recent_history_vec = Wire(UInt(BYTE_SIZE.W))
//recent_history_vec_next(elemno))
print_recent_history_vec := recent_history_vec_next(elemno)
CompressAccelLogger.logInfo("do_write:mem(memno:%d,memaddr:%d): from rhvn(elemno:%d) = val:0x%x\n", memno, memaddr, elemno.U, print_recent_history_vec)
}
}
}
| module MEM_6( // @[HistoryBufferSRAM.scala:66:67]
input [11:0] R0_addr,
input R0_clk,
output [7:0] R0_data,
input [11:0] W0_addr,
input W0_en,
input W0_clk,
input [7:0] W0_data
);
MEM_ext MEM_ext ( // @[HistoryBufferSRAM.scala:66:67]
.R0_addr (R0_addr),
.R0_en (1'h1), // @[HistoryBufferSRAM.scala:66:67]
.R0_clk (R0_clk),
.R0_data (R0_data),
.W0_addr (W0_addr),
.W0_en (W0_en),
.W0_clk (W0_clk),
.W0_data (W0_data)
); // @[HistoryBufferSRAM.scala:66:67]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File RegMapFIFO.scala:
package sifive.blocks.util
import chisel3._
import chisel3.util._
import freechips.rocketchip.regmapper._
// MSB indicates full status
object NonBlockingEnqueue {
def apply(enq: DecoupledIO[UInt], regWidth: Int = 32): Seq[RegField] = {
val enqWidth = enq.bits.getWidth
val quash = Wire(Bool())
require(enqWidth > 0)
require(regWidth > enqWidth)
Seq(
RegField(enqWidth,
RegReadFn(0.U),
RegWriteFn((valid, data) => {
enq.valid := valid && !quash
enq.bits := data
true.B
}), RegFieldDesc("data", "Transmit data", access=RegFieldAccessType.W)),
RegField(regWidth - enqWidth - 1),
RegField(1,
!enq.ready,
RegWriteFn((valid, data) => {
quash := valid && data(0)
true.B
}), RegFieldDesc("full", "Transmit FIFO full", access=RegFieldAccessType.R, volatile=true)))
}
}
// MSB indicates empty status
object NonBlockingDequeue {
def apply(deq: DecoupledIO[UInt], regWidth: Int = 32): Seq[RegField] = {
val deqWidth = deq.bits.getWidth
require(deqWidth > 0)
require(regWidth > deqWidth)
Seq(
RegField.r(deqWidth,
RegReadFn(ready => {
deq.ready := ready
(true.B, deq.bits)
}), RegFieldDesc("data", "Receive data", volatile=true)),
RegField(regWidth - deqWidth - 1),
RegField.r(1, !deq.valid,
RegFieldDesc("empty", "Receive FIFO empty", volatile=true)))
}
}
/*
Copyright 2016 SiFive, Inc.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
File Buffer.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import org.chipsalliance.diplomacy.lazymodule._
import freechips.rocketchip.diplomacy.BufferParams
class TLBufferNode (
a: BufferParams,
b: BufferParams,
c: BufferParams,
d: BufferParams,
e: BufferParams)(implicit valName: ValName) extends TLAdapterNode(
clientFn = { p => p.v1copy(minLatency = p.minLatency + b.latency + c.latency) },
managerFn = { p => p.v1copy(minLatency = p.minLatency + a.latency + d.latency) }
) {
override lazy val nodedebugstring = s"a:${a.toString}, b:${b.toString}, c:${c.toString}, d:${d.toString}, e:${e.toString}"
override def circuitIdentity = List(a,b,c,d,e).forall(_ == BufferParams.none)
}
class TLBuffer(
a: BufferParams,
b: BufferParams,
c: BufferParams,
d: BufferParams,
e: BufferParams)(implicit p: Parameters) extends LazyModule
{
def this(ace: BufferParams, bd: BufferParams)(implicit p: Parameters) = this(ace, bd, ace, bd, ace)
def this(abcde: BufferParams)(implicit p: Parameters) = this(abcde, abcde)
def this()(implicit p: Parameters) = this(BufferParams.default)
val node = new TLBufferNode(a, b, c, d, e)
lazy val module = new Impl
class Impl extends LazyModuleImp(this) {
def headBundle = node.out.head._2.bundle
override def desiredName = (Seq("TLBuffer") ++ node.out.headOption.map(_._2.bundle.shortName)).mkString("_")
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
out.a <> a(in .a)
in .d <> d(out.d)
if (edgeOut.manager.anySupportAcquireB && edgeOut.client.anySupportProbe) {
in .b <> b(out.b)
out.c <> c(in .c)
out.e <> e(in .e)
} else {
in.b.valid := false.B
in.c.ready := true.B
in.e.ready := true.B
out.b.ready := true.B
out.c.valid := false.B
out.e.valid := false.B
}
}
}
}
object TLBuffer
{
def apply() (implicit p: Parameters): TLNode = apply(BufferParams.default)
def apply(abcde: BufferParams) (implicit p: Parameters): TLNode = apply(abcde, abcde)
def apply(ace: BufferParams, bd: BufferParams)(implicit p: Parameters): TLNode = apply(ace, bd, ace, bd, ace)
def apply(
a: BufferParams,
b: BufferParams,
c: BufferParams,
d: BufferParams,
e: BufferParams)(implicit p: Parameters): TLNode =
{
val buffer = LazyModule(new TLBuffer(a, b, c, d, e))
buffer.node
}
def chain(depth: Int, name: Option[String] = None)(implicit p: Parameters): Seq[TLNode] = {
val buffers = Seq.fill(depth) { LazyModule(new TLBuffer()) }
name.foreach { n => buffers.zipWithIndex.foreach { case (b, i) => b.suggestName(s"${n}_${i}") } }
buffers.map(_.node)
}
def chainNode(depth: Int, name: Option[String] = None)(implicit p: Parameters): TLNode = {
chain(depth, name)
.reduceLeftOption(_ :*=* _)
.getOrElse(TLNameNode("no_buffer"))
}
}
File UART.scala:
package sifive.blocks.devices.uart
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.{Field, Parameters}
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.interrupts._
import freechips.rocketchip.prci._
import freechips.rocketchip.regmapper._
import freechips.rocketchip.subsystem._
import freechips.rocketchip.tilelink._
import freechips.rocketchip.devices.tilelink._
import freechips.rocketchip.util._
import sifive.blocks.util._
/** UART parameters
*
* @param address uart device TL base address
* @param dataBits number of bits in data frame
* @param stopBits number of stop bits
* @param divisorBits width of baud rate divisor
* @param oversample constructs the times of sampling for every data bit
* @param nSamples number of reserved Rx sampling result for decide one data bit
* @param nTxEntries number of entries in fifo between TL bus and Tx
* @param nRxEntries number of entries in fifo between TL bus and Rx
* @param includeFourWire additional CTS/RTS ports for flow control
* @param includeParity parity support
* @param includeIndependentParity Tx and Rx have opposite parity modes
* @param initBaudRate initial baud rate
*
* @note baud rate divisor = clk frequency / baud rate. It means the number of clk period for one data bit.
* Calculated in [[UARTAttachParams.attachTo()]]
*
* @example To configure a 8N1 UART with features below:
* {{{
* 8 entries of Tx and Rx fifo
* Baud rate = 115200
* Rx samples each data bit 16 times
* Uses 3 sample result for each data bit
* }}}
* Set the stopBits as below and keep the other parameter unchanged
* {{{
* stopBits = 1
* }}}
*
*/
case class UARTParams(
address: BigInt,
dataBits: Int = 8,
stopBits: Int = 2,
divisorBits: Int = 16,
oversample: Int = 4,
nSamples: Int = 3,
nTxEntries: Int = 8,
nRxEntries: Int = 8,
includeFourWire: Boolean = false,
includeParity: Boolean = false,
includeIndependentParity: Boolean = false, // Tx and Rx have opposite parity modes
initBaudRate: BigInt = BigInt(115200),
) extends DeviceParams
{
def oversampleFactor = 1 << oversample
require(divisorBits > oversample)
require(oversampleFactor > nSamples)
require((dataBits == 8) || (dataBits == 9))
}
class UARTPortIO(val c: UARTParams) extends Bundle {
val txd = Output(Bool())
val rxd = Input(Bool())
val cts_n = c.includeFourWire.option(Input(Bool()))
val rts_n = c.includeFourWire.option(Output(Bool()))
}
class UARTInterrupts extends Bundle {
val rxwm = Bool()
val txwm = Bool()
}
//abstract class UART(busWidthBytes: Int, val c: UARTParams, divisorInit: Int = 0)
/** UART Module organizes Tx and Rx module with fifo and generates control signals for them according to CSRs and UART parameters.
*
* ==Component==
* - Tx
* - Tx fifo
* - Rx
* - Rx fifo
* - TL bus to soc
*
* ==IO==
* [[UARTPortIO]]
*
* ==Datapass==
* {{{
* TL bus -> Tx fifo -> Tx
* TL bus <- Rx fifo <- Rx
* }}}
*
* @param divisorInit: number of clk period for one data bit
*/
class UART(busWidthBytes: Int, val c: UARTParams, divisorInit: Int = 0)
(implicit p: Parameters)
extends IORegisterRouter(
RegisterRouterParams(
name = "serial",
compat = Seq("sifive,uart0"),
base = c.address,
beatBytes = busWidthBytes),
new UARTPortIO(c))
//with HasInterruptSources {
with HasInterruptSources with HasTLControlRegMap {
def nInterrupts = 1 + c.includeParity.toInt
ResourceBinding {
Resource(ResourceAnchors.aliases, "uart").bind(ResourceAlias(device.label))
}
require(divisorInit != 0, "UART divisor wasn't initialized during instantiation")
require(divisorInit >> c.divisorBits == 0, s"UART divisor reg (width $c.divisorBits) not wide enough to hold $divisorInit")
lazy val module = new LazyModuleImp(this) {
val txm = Module(new UARTTx(c))
val txq = Module(new Queue(UInt(c.dataBits.W), c.nTxEntries))
val rxm = Module(new UARTRx(c))
val rxq = Module(new Queue(UInt(c.dataBits.W), c.nRxEntries))
val div = RegInit(divisorInit.U(c.divisorBits.W))
private val stopCountBits = log2Up(c.stopBits)
private val txCountBits = log2Floor(c.nTxEntries) + 1
private val rxCountBits = log2Floor(c.nRxEntries) + 1
val txen = RegInit(false.B)
val rxen = RegInit(false.B)
val enwire4 = RegInit(false.B)
val invpol = RegInit(false.B)
val enparity = RegInit(false.B)
val parity = RegInit(false.B) // Odd parity - 1 , Even parity - 0
val errorparity = RegInit(false.B)
val errie = RegInit(false.B)
val txwm = RegInit(0.U(txCountBits.W))
val rxwm = RegInit(0.U(rxCountBits.W))
val nstop = RegInit(0.U(stopCountBits.W))
val data8or9 = RegInit(true.B)
if (c.includeFourWire){
txm.io.en := txen && (!port.cts_n.get || !enwire4)
txm.io.cts_n.get := port.cts_n.get
}
else
txm.io.en := txen
txm.io.in <> txq.io.deq
txm.io.div := div
txm.io.nstop := nstop
port.txd := txm.io.out
if (c.dataBits == 9) {
txm.io.data8or9.get := data8or9
rxm.io.data8or9.get := data8or9
}
rxm.io.en := rxen
rxm.io.in := port.rxd
rxq.io.enq.valid := rxm.io.out.valid
rxq.io.enq.bits := rxm.io.out.bits
rxm.io.div := div
val tx_busy = (txm.io.tx_busy || txq.io.count.orR) && txen
port.rts_n.foreach { r => r := Mux(enwire4, !(rxq.io.count < c.nRxEntries.U), tx_busy ^ invpol) }
if (c.includeParity) {
txm.io.enparity.get := enparity
txm.io.parity.get := parity
rxm.io.parity.get := parity ^ c.includeIndependentParity.B // independent parity on tx and rx
rxm.io.enparity.get := enparity
errorparity := rxm.io.errorparity.get || errorparity
interrupts(1) := errorparity && errie
}
val ie = RegInit(0.U.asTypeOf(new UARTInterrupts()))
val ip = Wire(new UARTInterrupts)
ip.txwm := (txq.io.count < txwm)
ip.rxwm := (rxq.io.count > rxwm)
interrupts(0) := (ip.txwm && ie.txwm) || (ip.rxwm && ie.rxwm)
val mapping = Seq(
UARTCtrlRegs.txfifo -> RegFieldGroup("txdata",Some("Transmit data"),
NonBlockingEnqueue(txq.io.enq)),
UARTCtrlRegs.rxfifo -> RegFieldGroup("rxdata",Some("Receive data"),
NonBlockingDequeue(rxq.io.deq)),
UARTCtrlRegs.txctrl -> RegFieldGroup("txctrl",Some("Serial transmit control"),Seq(
RegField(1, txen,
RegFieldDesc("txen","Transmit enable", reset=Some(0))),
RegField(stopCountBits, nstop,
RegFieldDesc("nstop","Number of stop bits", reset=Some(0))))),
UARTCtrlRegs.rxctrl -> Seq(RegField(1, rxen,
RegFieldDesc("rxen","Receive enable", reset=Some(0)))),
UARTCtrlRegs.txmark -> Seq(RegField(txCountBits, txwm,
RegFieldDesc("txcnt","Transmit watermark level", reset=Some(0)))),
UARTCtrlRegs.rxmark -> Seq(RegField(rxCountBits, rxwm,
RegFieldDesc("rxcnt","Receive watermark level", reset=Some(0)))),
UARTCtrlRegs.ie -> RegFieldGroup("ie",Some("Serial interrupt enable"),Seq(
RegField(1, ie.txwm,
RegFieldDesc("txwm_ie","Transmit watermark interrupt enable", reset=Some(0))),
RegField(1, ie.rxwm,
RegFieldDesc("rxwm_ie","Receive watermark interrupt enable", reset=Some(0))))),
UARTCtrlRegs.ip -> RegFieldGroup("ip",Some("Serial interrupt pending"),Seq(
RegField.r(1, ip.txwm,
RegFieldDesc("txwm_ip","Transmit watermark interrupt pending", volatile=true)),
RegField.r(1, ip.rxwm,
RegFieldDesc("rxwm_ip","Receive watermark interrupt pending", volatile=true)))),
UARTCtrlRegs.div -> Seq(
RegField(c.divisorBits, div,
RegFieldDesc("div","Baud rate divisor",reset=Some(divisorInit))))
)
val optionalparity = if (c.includeParity) Seq(
UARTCtrlRegs.parity -> RegFieldGroup("paritygenandcheck",Some("Odd/Even Parity Generation/Checking"),Seq(
RegField(1, enparity,
RegFieldDesc("enparity","Enable Parity Generation/Checking", reset=Some(0))),
RegField(1, parity,
RegFieldDesc("parity","Odd(1)/Even(0) Parity", reset=Some(0))),
RegField(1, errorparity,
RegFieldDesc("errorparity","Parity Status Sticky Bit", reset=Some(0))),
RegField(1, errie,
RegFieldDesc("errie","Interrupt on error in parity enable", reset=Some(0)))))) else Nil
val optionalwire4 = if (c.includeFourWire) Seq(
UARTCtrlRegs.wire4 -> RegFieldGroup("wire4",Some("Configure Clear-to-send / Request-to-send ports / RS-485"),Seq(
RegField(1, enwire4,
RegFieldDesc("enwire4","Enable CTS/RTS(1) or RS-485(0)", reset=Some(0))),
RegField(1, invpol,
RegFieldDesc("invpol","Invert polarity of RTS in RS-485 mode", reset=Some(0)))
))) else Nil
val optional8or9 = if (c.dataBits == 9) Seq(
UARTCtrlRegs.either8or9 -> RegFieldGroup("ConfigurableDataBits",Some("Configure number of data bits to be transmitted"),Seq(
RegField(1, data8or9,
RegFieldDesc("databits8or9","Data Bits to be 8(1) or 9(0)", reset=Some(1)))))) else Nil
regmap(mapping ++ optionalparity ++ optionalwire4 ++ optional8or9:_*)
}
}
class TLUART(busWidthBytes: Int, params: UARTParams, divinit: Int)(implicit p: Parameters)
extends UART(busWidthBytes, params, divinit) with HasTLControlRegMap
case class UARTLocated(loc: HierarchicalLocation) extends Field[Seq[UARTAttachParams]](Nil)
case class UARTAttachParams(
device: UARTParams,
controlWhere: TLBusWrapperLocation = PBUS,
blockerAddr: Option[BigInt] = None,
controlXType: ClockCrossingType = NoCrossing,
intXType: ClockCrossingType = NoCrossing) extends DeviceAttachParams
{
def attachTo(where: Attachable)(implicit p: Parameters): TLUART = where {
val name = s"uart_${UART.nextId()}"
val tlbus = where.locateTLBusWrapper(controlWhere)
val divinit = (tlbus.dtsFrequency.get / device.initBaudRate).toInt
val uartClockDomainWrapper = LazyModule(new ClockSinkDomain(take = None, name = Some("TLUART")))
val uart = uartClockDomainWrapper { LazyModule(new TLUART(tlbus.beatBytes, device, divinit)) }
uart.suggestName(name)
tlbus.coupleTo(s"device_named_$name") { bus =>
val blockerOpt = blockerAddr.map { a =>
val blocker = LazyModule(new TLClockBlocker(BasicBusBlockerParams(a, tlbus.beatBytes, tlbus.beatBytes)))
tlbus.coupleTo(s"bus_blocker_for_$name") { blocker.controlNode := TLFragmenter(tlbus, Some("UART_Blocker")) := _ }
blocker
}
uartClockDomainWrapper.clockNode := (controlXType match {
case _: SynchronousCrossing =>
tlbus.dtsClk.map(_.bind(uart.device))
tlbus.fixedClockNode
case _: RationalCrossing =>
tlbus.clockNode
case _: AsynchronousCrossing =>
val uartClockGroup = ClockGroup()
uartClockGroup := where.allClockGroupsNode
blockerOpt.map { _.clockNode := uartClockGroup } .getOrElse { uartClockGroup }
})
(uart.controlXing(controlXType)
:= TLFragmenter(tlbus, Some("UART"))
:= blockerOpt.map { _.node := bus } .getOrElse { bus })
}
(intXType match {
case _: SynchronousCrossing => where.ibus.fromSync
case _: RationalCrossing => where.ibus.fromRational
case _: AsynchronousCrossing => where.ibus.fromAsync
}) := uart.intXing(intXType)
uart
}
}
object UART {
val nextId = { var i = -1; () => { i += 1; i} }
def makePort(node: BundleBridgeSource[UARTPortIO], name: String)(implicit p: Parameters): ModuleValue[UARTPortIO] = {
val uartNode = node.makeSink()
InModuleBody { uartNode.makeIO()(ValName(name)) }
}
def tieoff(port: UARTPortIO) {
port.rxd := 1.U
if (port.c.includeFourWire) {
port.cts_n.foreach { ct => ct := false.B } // active-low
}
}
def loopback(port: UARTPortIO) {
port.rxd := port.txd
if (port.c.includeFourWire) {
port.cts_n.get := port.rts_n.get
}
}
}
/*
Copyright 2016 SiFive, Inc.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
File Crossing.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.interrupts
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy.lazymodule._
import freechips.rocketchip.util.{SynchronizerShiftReg, AsyncResetReg}
@deprecated("IntXing does not ensure interrupt source is glitch free. Use IntSyncSource and IntSyncSink", "rocket-chip 1.2")
class IntXing(sync: Int = 3)(implicit p: Parameters) extends LazyModule
{
val intnode = IntAdapterNode()
lazy val module = new Impl
class Impl extends LazyModuleImp(this) {
(intnode.in zip intnode.out) foreach { case ((in, _), (out, _)) =>
out := SynchronizerShiftReg(in, sync)
}
}
}
object IntSyncCrossingSource
{
def apply(alreadyRegistered: Boolean = false)(implicit p: Parameters) =
{
val intsource = LazyModule(new IntSyncCrossingSource(alreadyRegistered))
intsource.node
}
}
class IntSyncCrossingSource(alreadyRegistered: Boolean = false)(implicit p: Parameters) extends LazyModule
{
val node = IntSyncSourceNode(alreadyRegistered)
lazy val module = if (alreadyRegistered) (new ImplRegistered) else (new Impl)
class Impl extends LazyModuleImp(this) {
def outSize = node.out.headOption.map(_._1.sync.size).getOrElse(0)
override def desiredName = s"IntSyncCrossingSource_n${node.out.size}x${outSize}"
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
out.sync := AsyncResetReg(Cat(in.reverse)).asBools
}
}
class ImplRegistered extends LazyRawModuleImp(this) {
def outSize = node.out.headOption.map(_._1.sync.size).getOrElse(0)
override def desiredName = s"IntSyncCrossingSource_n${node.out.size}x${outSize}_Registered"
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
out.sync := in
}
}
}
object IntSyncCrossingSink
{
@deprecated("IntSyncCrossingSink which used the `sync` parameter to determine crossing type is deprecated. Use IntSyncAsyncCrossingSink, IntSyncRationalCrossingSink, or IntSyncSyncCrossingSink instead for > 1, 1, and 0 sync values respectively", "rocket-chip 1.2")
def apply(sync: Int = 3)(implicit p: Parameters) =
{
val intsink = LazyModule(new IntSyncAsyncCrossingSink(sync))
intsink.node
}
}
class IntSyncAsyncCrossingSink(sync: Int = 3)(implicit p: Parameters) extends LazyModule
{
val node = IntSyncSinkNode(sync)
lazy val module = new Impl
class Impl extends LazyModuleImp(this) {
override def desiredName = s"IntSyncAsyncCrossingSink_n${node.out.size}x${node.out.head._1.size}"
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
out := SynchronizerShiftReg(in.sync, sync)
}
}
}
object IntSyncAsyncCrossingSink
{
def apply(sync: Int = 3)(implicit p: Parameters) =
{
val intsink = LazyModule(new IntSyncAsyncCrossingSink(sync))
intsink.node
}
}
class IntSyncSyncCrossingSink()(implicit p: Parameters) extends LazyModule
{
val node = IntSyncSinkNode(0)
lazy val module = new Impl
class Impl extends LazyRawModuleImp(this) {
def outSize = node.out.headOption.map(_._1.size).getOrElse(0)
override def desiredName = s"IntSyncSyncCrossingSink_n${node.out.size}x${outSize}"
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
out := in.sync
}
}
}
object IntSyncSyncCrossingSink
{
def apply()(implicit p: Parameters) =
{
val intsink = LazyModule(new IntSyncSyncCrossingSink())
intsink.node
}
}
class IntSyncRationalCrossingSink()(implicit p: Parameters) extends LazyModule
{
val node = IntSyncSinkNode(1)
lazy val module = new Impl
class Impl extends LazyModuleImp(this) {
def outSize = node.out.headOption.map(_._1.size).getOrElse(0)
override def desiredName = s"IntSyncRationalCrossingSink_n${node.out.size}x${outSize}"
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
out := RegNext(in.sync)
}
}
}
object IntSyncRationalCrossingSink
{
def apply()(implicit p: Parameters) =
{
val intsink = LazyModule(new IntSyncRationalCrossingSink())
intsink.node
}
}
File Nodes.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import org.chipsalliance.diplomacy.nodes._
import freechips.rocketchip.util.{AsyncQueueParams,RationalDirection}
case object TLMonitorBuilder extends Field[TLMonitorArgs => TLMonitorBase](args => new TLMonitor(args))
object TLImp extends NodeImp[TLMasterPortParameters, TLSlavePortParameters, TLEdgeOut, TLEdgeIn, TLBundle]
{
def edgeO(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeOut(pd, pu, p, sourceInfo)
def edgeI(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeIn (pd, pu, p, sourceInfo)
def bundleO(eo: TLEdgeOut) = TLBundle(eo.bundle)
def bundleI(ei: TLEdgeIn) = TLBundle(ei.bundle)
def render(ei: TLEdgeIn) = RenderedEdge(colour = "#000000" /* black */, label = (ei.manager.beatBytes * 8).toString)
override def monitor(bundle: TLBundle, edge: TLEdgeIn): Unit = {
val monitor = Module(edge.params(TLMonitorBuilder)(TLMonitorArgs(edge)))
monitor.io.in := bundle
}
override def mixO(pd: TLMasterPortParameters, node: OutwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLMasterPortParameters =
pd.v1copy(clients = pd.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })
override def mixI(pu: TLSlavePortParameters, node: InwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLSlavePortParameters =
pu.v1copy(managers = pu.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })
}
trait TLFormatNode extends FormatNode[TLEdgeIn, TLEdgeOut]
case class TLClientNode(portParams: Seq[TLMasterPortParameters])(implicit valName: ValName) extends SourceNode(TLImp)(portParams) with TLFormatNode
case class TLManagerNode(portParams: Seq[TLSlavePortParameters])(implicit valName: ValName) extends SinkNode(TLImp)(portParams) with TLFormatNode
case class TLAdapterNode(
clientFn: TLMasterPortParameters => TLMasterPortParameters = { s => s },
managerFn: TLSlavePortParameters => TLSlavePortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLImp)(clientFn, managerFn) with TLFormatNode
case class TLJunctionNode(
clientFn: Seq[TLMasterPortParameters] => Seq[TLMasterPortParameters],
managerFn: Seq[TLSlavePortParameters] => Seq[TLSlavePortParameters])(
implicit valName: ValName)
extends JunctionNode(TLImp)(clientFn, managerFn) with TLFormatNode
case class TLIdentityNode()(implicit valName: ValName) extends IdentityNode(TLImp)() with TLFormatNode
object TLNameNode {
def apply(name: ValName) = TLIdentityNode()(name)
def apply(name: Option[String]): TLIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLIdentityNode = apply(Some(name))
}
case class TLEphemeralNode()(implicit valName: ValName) extends EphemeralNode(TLImp)()
object TLTempNode {
def apply(): TLEphemeralNode = TLEphemeralNode()(ValName("temp"))
}
case class TLNexusNode(
clientFn: Seq[TLMasterPortParameters] => TLMasterPortParameters,
managerFn: Seq[TLSlavePortParameters] => TLSlavePortParameters)(
implicit valName: ValName)
extends NexusNode(TLImp)(clientFn, managerFn) with TLFormatNode
abstract class TLCustomNode(implicit valName: ValName)
extends CustomNode(TLImp) with TLFormatNode
// Asynchronous crossings
trait TLAsyncFormatNode extends FormatNode[TLAsyncEdgeParameters, TLAsyncEdgeParameters]
object TLAsyncImp extends SimpleNodeImp[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncEdgeParameters, TLAsyncBundle]
{
def edge(pd: TLAsyncClientPortParameters, pu: TLAsyncManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLAsyncEdgeParameters(pd, pu, p, sourceInfo)
def bundle(e: TLAsyncEdgeParameters) = new TLAsyncBundle(e.bundle)
def render(e: TLAsyncEdgeParameters) = RenderedEdge(colour = "#ff0000" /* red */, label = e.manager.async.depth.toString)
override def mixO(pd: TLAsyncClientPortParameters, node: OutwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncClientPortParameters =
pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }))
override def mixI(pu: TLAsyncManagerPortParameters, node: InwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncManagerPortParameters =
pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }))
}
case class TLAsyncAdapterNode(
clientFn: TLAsyncClientPortParameters => TLAsyncClientPortParameters = { s => s },
managerFn: TLAsyncManagerPortParameters => TLAsyncManagerPortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLAsyncImp)(clientFn, managerFn) with TLAsyncFormatNode
case class TLAsyncIdentityNode()(implicit valName: ValName) extends IdentityNode(TLAsyncImp)() with TLAsyncFormatNode
object TLAsyncNameNode {
def apply(name: ValName) = TLAsyncIdentityNode()(name)
def apply(name: Option[String]): TLAsyncIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLAsyncIdentityNode = apply(Some(name))
}
case class TLAsyncSourceNode(sync: Option[Int])(implicit valName: ValName)
extends MixedAdapterNode(TLImp, TLAsyncImp)(
dFn = { p => TLAsyncClientPortParameters(p) },
uFn = { p => p.base.v1copy(minLatency = p.base.minLatency + sync.getOrElse(p.async.sync)) }) with FormatNode[TLEdgeIn, TLAsyncEdgeParameters] // discard cycles in other clock domain
case class TLAsyncSinkNode(async: AsyncQueueParams)(implicit valName: ValName)
extends MixedAdapterNode(TLAsyncImp, TLImp)(
dFn = { p => p.base.v1copy(minLatency = p.base.minLatency + async.sync) },
uFn = { p => TLAsyncManagerPortParameters(async, p) }) with FormatNode[TLAsyncEdgeParameters, TLEdgeOut]
// Rationally related crossings
trait TLRationalFormatNode extends FormatNode[TLRationalEdgeParameters, TLRationalEdgeParameters]
object TLRationalImp extends SimpleNodeImp[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalEdgeParameters, TLRationalBundle]
{
def edge(pd: TLRationalClientPortParameters, pu: TLRationalManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLRationalEdgeParameters(pd, pu, p, sourceInfo)
def bundle(e: TLRationalEdgeParameters) = new TLRationalBundle(e.bundle)
def render(e: TLRationalEdgeParameters) = RenderedEdge(colour = "#00ff00" /* green */)
override def mixO(pd: TLRationalClientPortParameters, node: OutwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalClientPortParameters =
pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }))
override def mixI(pu: TLRationalManagerPortParameters, node: InwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalManagerPortParameters =
pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }))
}
case class TLRationalAdapterNode(
clientFn: TLRationalClientPortParameters => TLRationalClientPortParameters = { s => s },
managerFn: TLRationalManagerPortParameters => TLRationalManagerPortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLRationalImp)(clientFn, managerFn) with TLRationalFormatNode
case class TLRationalIdentityNode()(implicit valName: ValName) extends IdentityNode(TLRationalImp)() with TLRationalFormatNode
object TLRationalNameNode {
def apply(name: ValName) = TLRationalIdentityNode()(name)
def apply(name: Option[String]): TLRationalIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLRationalIdentityNode = apply(Some(name))
}
case class TLRationalSourceNode()(implicit valName: ValName)
extends MixedAdapterNode(TLImp, TLRationalImp)(
dFn = { p => TLRationalClientPortParameters(p) },
uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLRationalEdgeParameters] // discard cycles from other clock domain
case class TLRationalSinkNode(direction: RationalDirection)(implicit valName: ValName)
extends MixedAdapterNode(TLRationalImp, TLImp)(
dFn = { p => p.base.v1copy(minLatency = 1) },
uFn = { p => TLRationalManagerPortParameters(direction, p) }) with FormatNode[TLRationalEdgeParameters, TLEdgeOut]
// Credited version of TileLink channels
trait TLCreditedFormatNode extends FormatNode[TLCreditedEdgeParameters, TLCreditedEdgeParameters]
object TLCreditedImp extends SimpleNodeImp[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedEdgeParameters, TLCreditedBundle]
{
def edge(pd: TLCreditedClientPortParameters, pu: TLCreditedManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLCreditedEdgeParameters(pd, pu, p, sourceInfo)
def bundle(e: TLCreditedEdgeParameters) = new TLCreditedBundle(e.bundle)
def render(e: TLCreditedEdgeParameters) = RenderedEdge(colour = "#ffff00" /* yellow */, e.delay.toString)
override def mixO(pd: TLCreditedClientPortParameters, node: OutwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedClientPortParameters =
pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }))
override def mixI(pu: TLCreditedManagerPortParameters, node: InwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedManagerPortParameters =
pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }))
}
case class TLCreditedAdapterNode(
clientFn: TLCreditedClientPortParameters => TLCreditedClientPortParameters = { s => s },
managerFn: TLCreditedManagerPortParameters => TLCreditedManagerPortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLCreditedImp)(clientFn, managerFn) with TLCreditedFormatNode
case class TLCreditedIdentityNode()(implicit valName: ValName) extends IdentityNode(TLCreditedImp)() with TLCreditedFormatNode
object TLCreditedNameNode {
def apply(name: ValName) = TLCreditedIdentityNode()(name)
def apply(name: Option[String]): TLCreditedIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLCreditedIdentityNode = apply(Some(name))
}
case class TLCreditedSourceNode(delay: TLCreditedDelay)(implicit valName: ValName)
extends MixedAdapterNode(TLImp, TLCreditedImp)(
dFn = { p => TLCreditedClientPortParameters(delay, p) },
uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLCreditedEdgeParameters] // discard cycles from other clock domain
case class TLCreditedSinkNode(delay: TLCreditedDelay)(implicit valName: ValName)
extends MixedAdapterNode(TLCreditedImp, TLImp)(
dFn = { p => p.base.v1copy(minLatency = 1) },
uFn = { p => TLCreditedManagerPortParameters(delay, p) }) with FormatNode[TLCreditedEdgeParameters, TLEdgeOut]
File RegisterRouter.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import org.chipsalliance.diplomacy.nodes._
import freechips.rocketchip.diplomacy.{AddressSet, TransferSizes}
import freechips.rocketchip.resources.{Device, Resource, ResourceBindings}
import freechips.rocketchip.prci.{NoCrossing}
import freechips.rocketchip.regmapper.{RegField, RegMapper, RegMapperParams, RegMapperInput, RegisterRouter}
import freechips.rocketchip.util.{BundleField, ControlKey, ElaborationArtefacts, GenRegDescsAnno}
import scala.math.min
class TLRegisterRouterExtraBundle(val sourceBits: Int, val sizeBits: Int) extends Bundle {
val source = UInt((sourceBits max 1).W)
val size = UInt((sizeBits max 1).W)
}
case object TLRegisterRouterExtra extends ControlKey[TLRegisterRouterExtraBundle]("tlrr_extra")
case class TLRegisterRouterExtraField(sourceBits: Int, sizeBits: Int) extends BundleField[TLRegisterRouterExtraBundle](TLRegisterRouterExtra, Output(new TLRegisterRouterExtraBundle(sourceBits, sizeBits)), x => {
x.size := 0.U
x.source := 0.U
})
/** TLRegisterNode is a specialized TL SinkNode that encapsulates MMIO registers.
* It provides functionality for describing and outputting metdata about the registers in several formats.
* It also provides a concrete implementation of a regmap function that will be used
* to wire a map of internal registers associated with this node to the node's interconnect port.
*/
case class TLRegisterNode(
address: Seq[AddressSet],
device: Device,
deviceKey: String = "reg/control",
concurrency: Int = 0,
beatBytes: Int = 4,
undefZero: Boolean = true,
executable: Boolean = false)(
implicit valName: ValName)
extends SinkNode(TLImp)(Seq(TLSlavePortParameters.v1(
Seq(TLSlaveParameters.v1(
address = address,
resources = Seq(Resource(device, deviceKey)),
executable = executable,
supportsGet = TransferSizes(1, beatBytes),
supportsPutPartial = TransferSizes(1, beatBytes),
supportsPutFull = TransferSizes(1, beatBytes),
fifoId = Some(0))), // requests are handled in order
beatBytes = beatBytes,
minLatency = min(concurrency, 1)))) with TLFormatNode // the Queue adds at most one cycle
{
val size = 1 << log2Ceil(1 + address.map(_.max).max - address.map(_.base).min)
require (size >= beatBytes)
address.foreach { case a =>
require (a.widen(size-1).base == address.head.widen(size-1).base,
s"TLRegisterNode addresses (${address}) must be aligned to its size ${size}")
}
// Calling this method causes the matching TL2 bundle to be
// configured to route all requests to the listed RegFields.
def regmap(mapping: RegField.Map*) = {
val (bundleIn, edge) = this.in(0)
val a = bundleIn.a
val d = bundleIn.d
val fields = TLRegisterRouterExtraField(edge.bundle.sourceBits, edge.bundle.sizeBits) +: a.bits.params.echoFields
val params = RegMapperParams(log2Up(size/beatBytes), beatBytes, fields)
val in = Wire(Decoupled(new RegMapperInput(params)))
in.bits.read := a.bits.opcode === TLMessages.Get
in.bits.index := edge.addr_hi(a.bits)
in.bits.data := a.bits.data
in.bits.mask := a.bits.mask
Connectable.waiveUnmatched(in.bits.extra, a.bits.echo) match {
case (lhs, rhs) => lhs :<= rhs
}
val a_extra = in.bits.extra(TLRegisterRouterExtra)
a_extra.source := a.bits.source
a_extra.size := a.bits.size
// Invoke the register map builder
val out = RegMapper(beatBytes, concurrency, undefZero, in, mapping:_*)
// No flow control needed
in.valid := a.valid
a.ready := in.ready
d.valid := out.valid
out.ready := d.ready
// We must restore the size to enable width adapters to work
val d_extra = out.bits.extra(TLRegisterRouterExtra)
d.bits := edge.AccessAck(toSource = d_extra.source, lgSize = d_extra.size)
// avoid a Mux on the data bus by manually overriding two fields
d.bits.data := out.bits.data
Connectable.waiveUnmatched(d.bits.echo, out.bits.extra) match {
case (lhs, rhs) => lhs :<= rhs
}
d.bits.opcode := Mux(out.bits.read, TLMessages.AccessAckData, TLMessages.AccessAck)
// Tie off unused channels
bundleIn.b.valid := false.B
bundleIn.c.ready := true.B
bundleIn.e.ready := true.B
genRegDescsJson(mapping:_*)
}
def genRegDescsJson(mapping: RegField.Map*): Unit = {
// Dump out the register map for documentation purposes.
val base = address.head.base
val baseHex = s"0x${base.toInt.toHexString}"
val name = s"${device.describe(ResourceBindings()).name}.At${baseHex}"
val json = GenRegDescsAnno.serialize(base, name, mapping:_*)
var suffix = 0
while( ElaborationArtefacts.contains(s"${baseHex}.${suffix}.regmap.json")) {
suffix = suffix + 1
}
ElaborationArtefacts.add(s"${baseHex}.${suffix}.regmap.json", json)
val module = Module.currentModule.get.asInstanceOf[RawModule]
GenRegDescsAnno.anno(
module,
base,
mapping:_*)
}
}
/** Mix HasTLControlRegMap into any subclass of RegisterRouter to gain helper functions for attaching a device control register map to TileLink.
* - The intended use case is that controlNode will diplomatically publish a SW-visible device's memory-mapped control registers.
* - Use the clock crossing helper controlXing to externally connect controlNode to a TileLink interconnect.
* - Use the mapping helper function regmap to internally fill out the space of device control registers.
*/
trait HasTLControlRegMap { this: RegisterRouter =>
protected val controlNode = TLRegisterNode(
address = address,
device = device,
deviceKey = "reg/control",
concurrency = concurrency,
beatBytes = beatBytes,
undefZero = undefZero,
executable = executable)
// Externally, this helper should be used to connect the register control port to a bus
val controlXing: TLInwardClockCrossingHelper = this.crossIn(controlNode)
// Backwards-compatibility default node accessor with no clock crossing
lazy val node: TLInwardNode = controlXing(NoCrossing)
// Internally, this function should be used to populate the control port with registers
protected def regmap(mapping: RegField.Map*): Unit = { controlNode.regmap(mapping:_*) }
}
File MuxLiteral.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util.log2Ceil
import scala.reflect.ClassTag
/* MuxLiteral creates a lookup table from a key to a list of values.
* Unlike MuxLookup, the table keys must be exclusive literals.
*/
object MuxLiteral
{
def apply[T <: Data:ClassTag](index: UInt, default: T, first: (UInt, T), rest: (UInt, T)*): T =
apply(index, default, first :: rest.toList)
def apply[T <: Data:ClassTag](index: UInt, default: T, cases: Seq[(UInt, T)]): T =
MuxTable(index, default, cases.map { case (k, v) => (k.litValue, v) })
}
object MuxSeq
{
def apply[T <: Data:ClassTag](index: UInt, default: T, first: T, rest: T*): T =
apply(index, default, first :: rest.toList)
def apply[T <: Data:ClassTag](index: UInt, default: T, cases: Seq[T]): T =
MuxTable(index, default, cases.zipWithIndex.map { case (v, i) => (BigInt(i), v) })
}
object MuxTable
{
def apply[T <: Data:ClassTag](index: UInt, default: T, first: (BigInt, T), rest: (BigInt, T)*): T =
apply(index, default, first :: rest.toList)
def apply[T <: Data:ClassTag](index: UInt, default: T, cases: Seq[(BigInt, T)]): T = {
/* All keys must be >= 0 and distinct */
cases.foreach { case (k, _) => require (k >= 0) }
require (cases.map(_._1).distinct.size == cases.size)
/* Filter out any cases identical to the default */
val simple = cases.filter { case (k, v) => !default.isLit || !v.isLit || v.litValue != default.litValue }
val maxKey = (BigInt(0) +: simple.map(_._1)).max
val endIndex = BigInt(1) << log2Ceil(maxKey+1)
if (simple.isEmpty) {
default
} else if (endIndex <= 2*simple.size) {
/* The dense encoding case uses a Vec */
val table = Array.fill(endIndex.toInt) { default }
simple.foreach { case (k, v) => table(k.toInt) = v }
Mux(index >= endIndex.U, default, VecInit(table)(index))
} else {
/* The sparse encoding case uses switch */
val out = WireDefault(default)
simple.foldLeft(new chisel3.util.SwitchContext(index, None, Set.empty)) { case (acc, (k, v)) =>
acc.is (k.U) { out := v }
}
out
}
}
}
File LazyModuleImp.scala:
package org.chipsalliance.diplomacy.lazymodule
import chisel3.{withClockAndReset, Module, RawModule, Reset, _}
import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo}
import firrtl.passes.InlineAnnotation
import org.chipsalliance.cde.config.Parameters
import org.chipsalliance.diplomacy.nodes.Dangle
import scala.collection.immutable.SortedMap
/** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]].
*
* This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy.
*/
sealed trait LazyModuleImpLike extends RawModule {
/** [[LazyModule]] that contains this instance. */
val wrapper: LazyModule
/** IOs that will be automatically "punched" for this instance. */
val auto: AutoBundle
/** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */
protected[diplomacy] val dangles: Seq[Dangle]
// [[wrapper.module]] had better not be accessed while LazyModules are still being built!
require(
LazyModule.scope.isEmpty,
s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}"
)
/** Set module name. Defaults to the containing LazyModule's desiredName. */
override def desiredName: String = wrapper.desiredName
suggestName(wrapper.suggestedName)
/** [[Parameters]] for chisel [[Module]]s. */
implicit val p: Parameters = wrapper.p
/** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and
* submodules.
*/
protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = {
// 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]],
// 2. return [[Dangle]]s from each module.
val childDangles = wrapper.children.reverse.flatMap { c =>
implicit val sourceInfo: SourceInfo = c.info
c.cloneProto.map { cp =>
// If the child is a clone, then recursively set cloneProto of its children as well
def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = {
require(bases.size == clones.size)
(bases.zip(clones)).map { case (l, r) =>
require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}")
l.cloneProto = Some(r)
assignCloneProtos(l.children, r.children)
}
}
assignCloneProtos(c.children, cp.children)
// Clone the child module as a record, and get its [[AutoBundle]]
val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName)
val clonedAuto = clone("auto").asInstanceOf[AutoBundle]
// Get the empty [[Dangle]]'s of the cloned child
val rawDangles = c.cloneDangles()
require(rawDangles.size == clonedAuto.elements.size)
// Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s
val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) }
dangles
}.getOrElse {
// For non-clones, instantiate the child module
val mod = try {
Module(c.module)
} catch {
case e: ChiselException => {
println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}")
throw e
}
}
mod.dangles
}
}
// Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]].
// This will result in a sequence of [[Dangle]] from these [[BaseNode]]s.
val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate())
// Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]]
val allDangles = nodeDangles ++ childDangles
// Group [[allDangles]] by their [[source]].
val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*)
// For each [[source]] set of [[Dangle]]s of size 2, ensure that these
// can be connected as a source-sink pair (have opposite flipped value).
// Make the connection and mark them as [[done]].
val done = Set() ++ pairing.values.filter(_.size == 2).map {
case Seq(a, b) =>
require(a.flipped != b.flipped)
// @todo <> in chisel3 makes directionless connection.
if (a.flipped) {
a.data <> b.data
} else {
b.data <> a.data
}
a.source
case _ => None
}
// Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module.
val forward = allDangles.filter(d => !done(d.source))
// Generate [[AutoBundle]] IO from [[forward]].
val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*))
// Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]]
val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) =>
if (d.flipped) {
d.data <> io
} else {
io <> d.data
}
d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name)
}
// Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]].
wrapper.inModuleBody.reverse.foreach {
_()
}
if (wrapper.shouldBeInlined) {
chisel3.experimental.annotate(new ChiselAnnotation {
def toFirrtl = InlineAnnotation(toNamed)
})
}
// Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]].
(auto, dangles)
}
}
/** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike {
/** Instantiate hardware of this `Module`. */
val (auto, dangles) = instantiate()
}
/** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike {
// These wires are the default clock+reset for all LazyModule children.
// It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the
// [[LazyRawModuleImp]] children.
// Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly.
/** drive clock explicitly. */
val childClock: Clock = Wire(Clock())
/** drive reset explicitly. */
val childReset: Reset = Wire(Reset())
// the default is that these are disabled
childClock := false.B.asClock
childReset := chisel3.DontCare
def provideImplicitClockToLazyChildren: Boolean = false
val (auto, dangles) =
if (provideImplicitClockToLazyChildren) {
withClockAndReset(childClock, childReset) { instantiate() }
} else {
instantiate()
}
}
File MixedNode.scala:
package org.chipsalliance.diplomacy.nodes
import chisel3.{Data, DontCare, Wire}
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.{Field, Parameters}
import org.chipsalliance.diplomacy.ValName
import org.chipsalliance.diplomacy.sourceLine
/** One side metadata of a [[Dangle]].
*
* Describes one side of an edge going into or out of a [[BaseNode]].
*
* @param serial
* the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to.
* @param index
* the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to.
*/
case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] {
import scala.math.Ordered.orderingToOrdered
def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that))
}
/** [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]]
* connects.
*
* [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] ,
* [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]].
*
* @param source
* the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within
* that [[BaseNode]].
* @param sink
* sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that
* [[BaseNode]].
* @param flipped
* flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to
* `danglesIn`.
* @param dataOpt
* actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module
*/
case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) {
def data = dataOpt.get
}
/** [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often
* derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually
* implement the protocol.
*/
case class Edges[EI, EO](in: Seq[EI], out: Seq[EO])
/** A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. */
case object MonitorsEnabled extends Field[Boolean](true)
/** When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented.
*
* For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but
* [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink
* nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the
* [[LazyModule]].
*/
case object RenderFlipped extends Field[Boolean](false)
/** The sealed node class in the package, all node are derived from it.
*
* @param inner
* Sink interface implementation.
* @param outer
* Source interface implementation.
* @param valName
* val name of this node.
* @tparam DI
* Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters
* describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected
* [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port
* parameters.
* @tparam UI
* Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing
* the protocol parameters of a sink. For an [[InwardNode]], it is determined itself.
* @tparam EI
* Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers
* specified for a sink according to protocol.
* @tparam BI
* Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface.
* It should extends from [[chisel3.Data]], which represents the real hardware.
* @tparam DO
* Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters
* describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself.
* @tparam UO
* Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing
* the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]].
* Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters.
* @tparam EO
* Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers
* specified for a source according to protocol.
* @tparam BO
* Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source
* interface. It should extends from [[chisel3.Data]], which represents the real hardware.
*
* @note
* Call Graph of [[MixedNode]]
* - line `─`: source is process by a function and generate pass to others
* - Arrow `→`: target of arrow is generated by source
*
* {{{
* (from the other node)
* ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐
* ↓ │
* (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │
* [[InwardNode.accPI]] │ │ │
* │ │ (based on protocol) │
* │ │ [[MixedNode.inner.edgeI]] │
* │ │ ↓ │
* ↓ │ │ │
* (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │
* [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │
* │ │ ↑ │ │ │
* │ │ │ [[OutwardNode.doParams]] │ │
* │ │ │ (from the other node) │ │
* │ │ │ │ │ │
* │ │ │ │ │ │
* │ │ │ └────────┬──────────────┤ │
* │ │ │ │ │ │
* │ │ │ │ (based on protocol) │
* │ │ │ │ [[MixedNode.inner.edgeI]] │
* │ │ │ │ │ │
* │ │ (from the other node) │ ↓ │
* │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │
* │ ↑ ↑ │ │ ↓ │
* │ │ │ │ │ [[MixedNode.in]] │
* │ │ │ │ ↓ ↑ │
* │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │
* ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │
* │ │ │ [[MixedNode.bundleOut]]─┐ │ │
* │ │ │ ↑ ↓ │ │
* │ │ │ │ [[MixedNode.out]] │ │
* │ ↓ ↓ │ ↑ │ │
* │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │
* │ │ (from the other node) ↑ │ │
* │ │ │ │ │ │
* │ │ │ [[MixedNode.outer.edgeO]] │ │
* │ │ │ (based on protocol) │ │
* │ │ │ │ │ │
* │ │ │ ┌────────────────────────────────────────┤ │ │
* │ │ │ │ │ │ │
* │ │ │ │ │ │ │
* │ │ │ │ │ │ │
* (immobilize after elaboration)│ ↓ │ │ │ │
* [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │
* ↑ (inward port from [[OutwardNode]]) │ │ │ │
* │ ┌─────────────────────────────────────────┤ │ │ │
* │ │ │ │ │ │
* │ │ │ │ │ │
* [[OutwardNode.accPO]] │ ↓ │ │ │
* (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │
* │ ↑ │ │
* │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │
* └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘
* }}}
*/
abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data](
val inner: InwardNodeImp[DI, UI, EI, BI],
val outer: OutwardNodeImp[DO, UO, EO, BO]
)(
implicit valName: ValName)
extends BaseNode
with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO]
with InwardNode[DI, UI, BI]
with OutwardNode[DO, UO, BO] {
// Generate a [[NodeHandle]] with inward and outward node are both this node.
val inward = this
val outward = this
/** Debug info of nodes binding. */
def bindingInfo: String = s"""$iBindingInfo
|$oBindingInfo
|""".stripMargin
/** Debug info of ports connecting. */
def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}]
|${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}]
|""".stripMargin
/** Debug info of parameters propagations. */
def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}]
|${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}]
|${diParams.size} downstream inward parameters: [${diParams.mkString(",")}]
|${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}]
|""".stripMargin
/** For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and
* [[MixedNode.iPortMapping]].
*
* Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward
* stars and outward stars.
*
* This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type
* of node.
*
* @param iKnown
* Number of known-size ([[BIND_ONCE]]) input bindings.
* @param oKnown
* Number of known-size ([[BIND_ONCE]]) output bindings.
* @param iStar
* Number of unknown size ([[BIND_STAR]]) input bindings.
* @param oStar
* Number of unknown size ([[BIND_STAR]]) output bindings.
* @return
* A Tuple of the resolved number of input and output connections.
*/
protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int)
/** Function to generate downward-flowing outward params from the downward-flowing input params and the current output
* ports.
*
* @param n
* The size of the output sequence to generate.
* @param p
* Sequence of downward-flowing input parameters of this node.
* @return
* A `n`-sized sequence of downward-flowing output edge parameters.
*/
protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO]
/** Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]].
*
* @param n
* Size of the output sequence.
* @param p
* Upward-flowing output edge parameters.
* @return
* A n-sized sequence of upward-flowing input edge parameters.
*/
protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI]
/** @return
* The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with
* [[BIND_STAR]].
*/
protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR)
/** @return
* The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of
* output bindings bound with [[BIND_STAR]].
*/
protected[diplomacy] lazy val sourceCard: Int =
iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR)
/** @return list of nodes involved in flex bindings with this node. */
protected[diplomacy] lazy val flexes: Seq[BaseNode] =
oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2)
/** Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin
* greedily taking up the remaining connections.
*
* @return
* A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return
* value is not relevant.
*/
protected[diplomacy] lazy val flexOffset: Int = {
/** Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex
* operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a
* connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of
* each node in the current set and decide whether they should be added to the set or not.
*
* @return
* the mapping of [[BaseNode]] indexed by their serial numbers.
*/
def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = {
if (visited.contains(v.serial) || !v.flexibleArityDirection) {
visited
} else {
v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum))
}
}
/** Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node.
*
* @example
* {{{
* a :*=* b :*=* c
* d :*=* b
* e :*=* f
* }}}
*
* `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)`
*/
val flexSet = DFS(this, Map()).values
/** The total number of :*= operators where we're on the left. */
val allSink = flexSet.map(_.sinkCard).sum
/** The total number of :=* operators used when we're on the right. */
val allSource = flexSet.map(_.sourceCard).sum
require(
allSink == 0 || allSource == 0,
s"The nodes ${flexSet.map(_.name)} which are inter-connected by :*=* have ${allSink} :*= operators and ${allSource} :=* operators connected to them, making it impossible to determine cardinality inference direction."
)
allSink - allSource
}
/** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. */
protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = {
if (flexibleArityDirection) flexOffset
else if (n.flexibleArityDirection) n.flexOffset
else 0
}
/** For a node which is connected between two nodes, select the one that will influence the direction of the flex
* resolution.
*/
protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = {
val dir = edgeArityDirection(n)
if (dir < 0) l
else if (dir > 0) r
else 1
}
/** Ensure that the same node is not visited twice in resolving `:*=`, etc operators. */
private var starCycleGuard = false
/** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star"
* connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also
* need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct
* edge parameters and later build up correct bundle connections.
*
* [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding
* operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort
* (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N :*= foo` or `N :*=* foo :*=
* bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo :*=* N`
*/
protected[diplomacy] lazy val (
oPortMapping: Seq[(Int, Int)],
iPortMapping: Seq[(Int, Int)],
oStar: Int,
iStar: Int
) = {
try {
if (starCycleGuard) throw StarCycleException()
starCycleGuard = true
// For a given node N...
// Number of foo :=* N
// + Number of bar :=* foo :*=* N
val oStars = oBindings.count { case (_, n, b, _, _) =>
b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) < 0)
}
// Number of N :*= foo
// + Number of N :*=* foo :*= bar
val iStars = iBindings.count { case (_, n, b, _, _) =>
b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) > 0)
}
// 1 for foo := N
// + bar.iStar for bar :*= foo :*=* N
// + foo.iStar for foo :*= N
// + 0 for foo :=* N
val oKnown = oBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, 0, n.iStar)
case BIND_QUERY => n.iStar
case BIND_STAR => 0
}
}.sum
// 1 for N := foo
// + bar.oStar for N :*=* foo :=* bar
// + foo.oStar for N :=* foo
// + 0 for N :*= foo
val iKnown = iBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, n.oStar, 0)
case BIND_QUERY => n.oStar
case BIND_STAR => 0
}
}.sum
// Resolve star depends on the node subclass to implement the algorithm for this.
val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars)
// Cumulative list of resolved outward binding range starting points
val oSum = oBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar)
case BIND_QUERY => n.iStar
case BIND_STAR => oStar
}
}.scanLeft(0)(_ + _)
// Cumulative list of resolved inward binding range starting points
val iSum = iBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar)
case BIND_QUERY => n.oStar
case BIND_STAR => iStar
}
}.scanLeft(0)(_ + _)
// Create ranges for each binding based on the running sums and return
// those along with resolved values for the star operations.
(oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar)
} catch {
case c: StarCycleException => throw c.copy(loop = context +: c.loop)
}
}
/** Sequence of inward ports.
*
* This should be called after all star bindings are resolved.
*
* Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding.
* `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this
* connection was made in the source code.
*/
protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] =
oBindings.flatMap { case (i, n, _, p, s) =>
// for each binding operator in this node, look at what it connects to
val (start, end) = n.iPortMapping(i)
(start until end).map { j => (j, n, p, s) }
}
/** Sequence of outward ports.
*
* This should be called after all star bindings are resolved.
*
* `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of
* outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection
* was made in the source code.
*/
protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] =
iBindings.flatMap { case (i, n, _, p, s) =>
// query this port index range of this node in the other side of node.
val (start, end) = n.oPortMapping(i)
(start until end).map { j => (j, n, p, s) }
}
// Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree
// Thus, there must exist an Eulerian path and the below algorithms terminate
@scala.annotation.tailrec
private def oTrace(
tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)
): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match {
case (i, n, p, s) => n.iForward(i) match {
case None => (i, n, p, s)
case Some((j, m)) => oTrace((j, m, p, s))
}
}
@scala.annotation.tailrec
private def iTrace(
tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)
): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match {
case (i, n, p, s) => n.oForward(i) match {
case None => (i, n, p, s)
case Some((j, m)) => iTrace((j, m, p, s))
}
}
/** Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved.
*
* Each Port is a tuple of:
* - Numeric index of this binding in the [[InwardNode]] on the other end.
* - [[InwardNode]] on the other end of this binding.
* - A view of [[Parameters]] where the binding occurred.
* - [[SourceInfo]] for source-level error reporting.
*/
lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace)
/** Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved.
*
* Each Port is a tuple of:
* - numeric index of this binding in [[OutwardNode]] on the other end.
* - [[OutwardNode]] on the other end of this binding.
* - a view of [[Parameters]] where the binding occurred.
* - [[SourceInfo]] for source-level error reporting.
*/
lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace)
private var oParamsCycleGuard = false
protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) }
protected[diplomacy] lazy val doParams: Seq[DO] = {
try {
if (oParamsCycleGuard) throw DownwardCycleException()
oParamsCycleGuard = true
val o = mapParamsD(oPorts.size, diParams)
require(
o.size == oPorts.size,
s"""Diplomacy has detected a problem with your graph:
|At the following node, the number of outward ports should equal the number of produced outward parameters.
|$context
|$connectedPortsInfo
|Downstreamed inward parameters: [${diParams.mkString(",")}]
|Produced outward parameters: [${o.mkString(",")}]
|""".stripMargin
)
o.map(outer.mixO(_, this))
} catch {
case c: DownwardCycleException => throw c.copy(loop = context +: c.loop)
}
}
private var iParamsCycleGuard = false
protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) }
protected[diplomacy] lazy val uiParams: Seq[UI] = {
try {
if (iParamsCycleGuard) throw UpwardCycleException()
iParamsCycleGuard = true
val i = mapParamsU(iPorts.size, uoParams)
require(
i.size == iPorts.size,
s"""Diplomacy has detected a problem with your graph:
|At the following node, the number of inward ports should equal the number of produced inward parameters.
|$context
|$connectedPortsInfo
|Upstreamed outward parameters: [${uoParams.mkString(",")}]
|Produced inward parameters: [${i.mkString(",")}]
|""".stripMargin
)
i.map(inner.mixI(_, this))
} catch {
case c: UpwardCycleException => throw c.copy(loop = context +: c.loop)
}
}
/** Outward edge parameters. */
protected[diplomacy] lazy val edgesOut: Seq[EO] =
(oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) }
/** Inward edge parameters. */
protected[diplomacy] lazy val edgesIn: Seq[EI] =
(iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) }
/** A tuple of the input edge parameters and output edge parameters for the edges bound to this node.
*
* If you need to access to the edges of a foreign Node, use this method (in/out create bundles).
*/
lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut)
/** Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. */
protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e =>
val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out")
// TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue,
// In the future, we should add an option to decide whether allowing unconnected in the LazyModule
x := DontCare
x
}
/** Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. */
protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e =>
val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In")
// TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue,
// In the future, we should add an option to decide whether allowing unconnected in the LazyModule
x := DontCare
x
}
private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) =>
Dangle(
source = HalfEdge(serial, i),
sink = HalfEdge(n.serial, j),
flipped = false,
name = wirePrefix + "out",
dataOpt = None
)
}
private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) =>
Dangle(
source = HalfEdge(n.serial, j),
sink = HalfEdge(serial, i),
flipped = true,
name = wirePrefix + "in",
dataOpt = None
)
}
/** Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. */
protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) =>
d.copy(dataOpt = Some(bundleOut(i)))
}
/** Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. */
protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) =>
d.copy(dataOpt = Some(bundleIn(i)))
}
private[diplomacy] var instantiated = false
/** Gather Bundle and edge parameters of outward ports.
*
* Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within
* [[LazyModuleImp]] code or after its instantiation has completed.
*/
def out: Seq[(BO, EO)] = {
require(
instantiated,
s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun"
)
bundleOut.zip(edgesOut)
}
/** Gather Bundle and edge parameters of inward ports.
*
* Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within
* [[LazyModuleImp]] code or after its instantiation has completed.
*/
def in: Seq[(BI, EI)] = {
require(
instantiated,
s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun"
)
bundleIn.zip(edgesIn)
}
/** Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires,
* instantiate monitors on all input ports if appropriate, and return all the dangles of this node.
*/
protected[diplomacy] def instantiate(): Seq[Dangle] = {
instantiated = true
if (!circuitIdentity) {
(iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) }
}
danglesOut ++ danglesIn
}
protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn
/** Connects the outward part of a node with the inward part of this node. */
protected[diplomacy] def bind(
h: OutwardNode[DI, UI, BI],
binding: NodeBinding
)(
implicit p: Parameters,
sourceInfo: SourceInfo
): Unit = {
val x = this // x := y
val y = h
sourceLine(sourceInfo, " at ", "")
val i = x.iPushed
val o = y.oPushed
y.oPush(
i,
x,
binding match {
case BIND_ONCE => BIND_ONCE
case BIND_FLEX => BIND_FLEX
case BIND_STAR => BIND_QUERY
case BIND_QUERY => BIND_STAR
}
)
x.iPush(o, y, binding)
}
/* Metadata for printing the node graph. */
def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) =>
val re = inner.render(e)
(n, re.copy(flipped = re.flipped != p(RenderFlipped)))
}
/** Metadata for printing the node graph */
def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) }
}
File Edges.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.util._
class TLEdge(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdgeParameters(client, manager, params, sourceInfo)
{
def isAligned(address: UInt, lgSize: UInt): Bool = {
if (maxLgSize == 0) true.B else {
val mask = UIntToOH1(lgSize, maxLgSize)
(address & mask) === 0.U
}
}
def mask(address: UInt, lgSize: UInt): UInt =
MaskGen(address, lgSize, manager.beatBytes)
def staticHasData(bundle: TLChannel): Option[Boolean] = {
bundle match {
case _:TLBundleA => {
// Do there exist A messages with Data?
val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial
// Do there exist A messages without Data?
val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint
// Statically optimize the case where hasData is a constant
if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None
}
case _:TLBundleB => {
// Do there exist B messages with Data?
val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial
// Do there exist B messages without Data?
val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint
// Statically optimize the case where hasData is a constant
if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None
}
case _:TLBundleC => {
// Do there eixst C messages with Data?
val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe
// Do there exist C messages without Data?
val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe
if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None
}
case _:TLBundleD => {
// Do there eixst D messages with Data?
val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB
// Do there exist D messages without Data?
val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT
if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None
}
case _:TLBundleE => Some(false)
}
}
def isRequest(x: TLChannel): Bool = {
x match {
case a: TLBundleA => true.B
case b: TLBundleB => true.B
case c: TLBundleC => c.opcode(2) && c.opcode(1)
// opcode === TLMessages.Release ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(2) && !d.opcode(1)
// opcode === TLMessages.Grant ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
}
def isResponse(x: TLChannel): Bool = {
x match {
case a: TLBundleA => false.B
case b: TLBundleB => false.B
case c: TLBundleC => !c.opcode(2) || !c.opcode(1)
// opcode =/= TLMessages.Release &&
// opcode =/= TLMessages.ReleaseData
case d: TLBundleD => true.B // Grant isResponse + isRequest
case e: TLBundleE => true.B
}
}
def hasData(x: TLChannel): Bool = {
val opdata = x match {
case a: TLBundleA => !a.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case b: TLBundleB => !b.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case c: TLBundleC => c.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.ProbeAckData ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
staticHasData(x).map(_.B).getOrElse(opdata)
}
def opcode(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.opcode
case b: TLBundleB => b.opcode
case c: TLBundleC => c.opcode
case d: TLBundleD => d.opcode
}
}
def param(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.param
case b: TLBundleB => b.param
case c: TLBundleC => c.param
case d: TLBundleD => d.param
}
}
def size(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.size
case b: TLBundleB => b.size
case c: TLBundleC => c.size
case d: TLBundleD => d.size
}
}
def data(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.data
case b: TLBundleB => b.data
case c: TLBundleC => c.data
case d: TLBundleD => d.data
}
}
def corrupt(x: TLDataChannel): Bool = {
x match {
case a: TLBundleA => a.corrupt
case b: TLBundleB => b.corrupt
case c: TLBundleC => c.corrupt
case d: TLBundleD => d.corrupt
}
}
def mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.mask
case b: TLBundleB => b.mask
case c: TLBundleC => mask(c.address, c.size)
}
}
def full_mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => mask(a.address, a.size)
case b: TLBundleB => mask(b.address, b.size)
case c: TLBundleC => mask(c.address, c.size)
}
}
def address(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.address
case b: TLBundleB => b.address
case c: TLBundleC => c.address
}
}
def source(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.source
case b: TLBundleB => b.source
case c: TLBundleC => c.source
case d: TLBundleD => d.source
}
}
def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes)
def addr_lo(x: UInt): UInt =
if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0)
def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x))
def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x))
def numBeats(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 1.U
case bundle: TLDataChannel => {
val hasData = this.hasData(bundle)
val size = this.size(bundle)
val cutoff = log2Ceil(manager.beatBytes)
val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U
val decode = UIntToOH(size, maxLgSize+1) >> cutoff
Mux(hasData, decode | small.asUInt, 1.U)
}
}
}
def numBeats1(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 0.U
case bundle: TLDataChannel => {
if (maxLgSize == 0) {
0.U
} else {
val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes)
Mux(hasData(bundle), decode, 0.U)
}
}
}
}
def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val beats1 = numBeats1(bits)
val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W))
val counter1 = counter - 1.U
val first = counter === 0.U
val last = counter === 1.U || beats1 === 0.U
val done = last && fire
val count = (beats1 & ~counter1)
when (fire) {
counter := Mux(first, beats1, counter1)
}
(first, last, done, count)
}
def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1
def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire)
def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid)
def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2
def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire)
def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid)
def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3
def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire)
def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid)
def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3)
}
def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire)
def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid)
def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4)
}
def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire)
def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid)
def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes))
}
def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire)
def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid)
// Does the request need T permissions to be executed?
def needT(a: TLBundleA): Bool = {
val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLPermissions.NtoB -> false.B,
TLPermissions.NtoT -> true.B,
TLPermissions.BtoT -> true.B))
MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array(
TLMessages.PutFullData -> true.B,
TLMessages.PutPartialData -> true.B,
TLMessages.ArithmeticData -> true.B,
TLMessages.LogicalData -> true.B,
TLMessages.Get -> false.B,
TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLHints.PREFETCH_READ -> false.B,
TLHints.PREFETCH_WRITE -> true.B)),
TLMessages.AcquireBlock -> acq_needT,
TLMessages.AcquirePerm -> acq_needT))
}
// This is a very expensive circuit; use only if you really mean it!
def inFlight(x: TLBundle): (UInt, UInt) = {
val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W))
val bce = manager.anySupportAcquireB && client.anySupportProbe
val (a_first, a_last, _) = firstlast(x.a)
val (b_first, b_last, _) = firstlast(x.b)
val (c_first, c_last, _) = firstlast(x.c)
val (d_first, d_last, _) = firstlast(x.d)
val (e_first, e_last, _) = firstlast(x.e)
val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits))
val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits))
val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits))
val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits))
val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits))
val a_inc = x.a.fire && a_first && a_request
val b_inc = x.b.fire && b_first && b_request
val c_inc = x.c.fire && c_first && c_request
val d_inc = x.d.fire && d_first && d_request
val e_inc = x.e.fire && e_first && e_request
val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil))
val a_dec = x.a.fire && a_last && a_response
val b_dec = x.b.fire && b_last && b_response
val c_dec = x.c.fire && c_last && c_response
val d_dec = x.d.fire && d_last && d_response
val e_dec = x.e.fire && e_last && e_response
val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil))
val next_flight = flight + PopCount(inc) - PopCount(dec)
flight := next_flight
(flight, next_flight)
}
def prettySourceMapping(context: String): String = {
s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n"
}
}
class TLEdgeOut(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
// Transfers
def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquireBlock
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquirePerm
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.Release
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ReleaseData
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) =
Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B)
def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAck
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions, data)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAckData
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B)
def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink)
def GrantAck(toSink: UInt): TLBundleE = {
val e = Wire(new TLBundleE(bundle))
e.sink := toSink
e
}
// Accesses
def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsGetFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Get
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutFullFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutFullData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, mask, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutPartialFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutPartialData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = {
require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsArithmeticFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.ArithmeticData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsLogicalFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.LogicalData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = {
require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsHintFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Hint
a.param := param
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data)
def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAckData
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size)
def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.HintAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
}
class TLEdgeIn(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = {
val todo = x.filter(!_.isEmpty)
val heads = todo.map(_.head)
val tails = todo.map(_.tail)
if (todo.isEmpty) Nil else { heads +: myTranspose(tails) }
}
// Transfers
def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = {
require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}")
val legal = client.supportsProbe(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Probe
b.param := capPermissions
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.Grant
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.GrantData
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B)
def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.ReleaseAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
// Accesses
def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = {
require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsGet(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Get
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsPutFull(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutFullData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, mask, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsPutPartial(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutPartialData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsArithmetic(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.ArithmeticData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsLogical(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.LogicalData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = {
require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsHint(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Hint
b.param := param
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size)
def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied)
def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data)
def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAckData
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B)
def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied)
def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B)
def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.HintAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
}
| module TLUART( // @[UART.scala:127:25]
input clock, // @[UART.scala:127:25]
input reset, // @[UART.scala:127:25]
output auto_int_xing_out_sync_0, // @[LazyModuleImp.scala:107:25]
output auto_control_xing_in_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_control_xing_in_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_control_xing_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_control_xing_in_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_control_xing_in_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [12:0] auto_control_xing_in_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [28:0] auto_control_xing_in_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_control_xing_in_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_control_xing_in_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_control_xing_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_control_xing_in_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_control_xing_in_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_control_xing_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_control_xing_in_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [12:0] auto_control_xing_in_d_bits_source, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_control_xing_in_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_io_out_txd, // @[LazyModuleImp.scala:107:25]
input auto_io_out_rxd // @[LazyModuleImp.scala:107:25]
);
wire out_front_valid; // @[RegisterRouter.scala:87:24]
wire out_front_ready; // @[RegisterRouter.scala:87:24]
wire out_bits_read; // @[RegisterRouter.scala:87:24]
wire [12:0] out_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:87:24]
wire [8:0] in_bits_index; // @[RegisterRouter.scala:73:18]
wire in_bits_read; // @[RegisterRouter.scala:73:18]
wire buffer_auto_out_d_valid; // @[Buffer.scala:40:9]
wire buffer_auto_out_d_ready; // @[Buffer.scala:40:9]
wire [63:0] buffer_auto_out_d_bits_data; // @[Buffer.scala:40:9]
wire [12:0] buffer_auto_out_d_bits_source; // @[Buffer.scala:40:9]
wire [1:0] buffer_auto_out_d_bits_size; // @[Buffer.scala:40:9]
wire [2:0] buffer_auto_out_d_bits_opcode; // @[Buffer.scala:40:9]
wire buffer_auto_out_a_valid; // @[Buffer.scala:40:9]
wire buffer_auto_out_a_ready; // @[Buffer.scala:40:9]
wire buffer_auto_out_a_bits_corrupt; // @[Buffer.scala:40:9]
wire [63:0] buffer_auto_out_a_bits_data; // @[Buffer.scala:40:9]
wire [7:0] buffer_auto_out_a_bits_mask; // @[Buffer.scala:40:9]
wire [28:0] buffer_auto_out_a_bits_address; // @[Buffer.scala:40:9]
wire [12:0] buffer_auto_out_a_bits_source; // @[Buffer.scala:40:9]
wire [1:0] buffer_auto_out_a_bits_size; // @[Buffer.scala:40:9]
wire [2:0] buffer_auto_out_a_bits_param; // @[Buffer.scala:40:9]
wire [2:0] buffer_auto_out_a_bits_opcode; // @[Buffer.scala:40:9]
wire buffer_auto_in_d_valid; // @[Buffer.scala:40:9]
wire buffer_auto_in_d_ready; // @[Buffer.scala:40:9]
wire [63:0] buffer_auto_in_d_bits_data; // @[Buffer.scala:40:9]
wire [12:0] buffer_auto_in_d_bits_source; // @[Buffer.scala:40:9]
wire [1:0] buffer_auto_in_d_bits_size; // @[Buffer.scala:40:9]
wire [2:0] buffer_auto_in_d_bits_opcode; // @[Buffer.scala:40:9]
wire buffer_auto_in_a_valid; // @[Buffer.scala:40:9]
wire buffer_auto_in_a_ready; // @[Buffer.scala:40:9]
wire buffer_auto_in_a_bits_corrupt; // @[Buffer.scala:40:9]
wire [63:0] buffer_auto_in_a_bits_data; // @[Buffer.scala:40:9]
wire [7:0] buffer_auto_in_a_bits_mask; // @[Buffer.scala:40:9]
wire [28:0] buffer_auto_in_a_bits_address; // @[Buffer.scala:40:9]
wire [12:0] buffer_auto_in_a_bits_source; // @[Buffer.scala:40:9]
wire [1:0] buffer_auto_in_a_bits_size; // @[Buffer.scala:40:9]
wire [2:0] buffer_auto_in_a_bits_param; // @[Buffer.scala:40:9]
wire [2:0] buffer_auto_in_a_bits_opcode; // @[Buffer.scala:40:9]
wire _rxq_io_deq_valid; // @[UART.scala:133:19]
wire [7:0] _rxq_io_deq_bits; // @[UART.scala:133:19]
wire [3:0] _rxq_io_count; // @[UART.scala:133:19]
wire _rxm_io_out_valid; // @[UART.scala:132:19]
wire [7:0] _rxm_io_out_bits; // @[UART.scala:132:19]
wire _txq_io_enq_ready; // @[UART.scala:130:19]
wire _txq_io_deq_valid; // @[UART.scala:130:19]
wire [7:0] _txq_io_deq_bits; // @[UART.scala:130:19]
wire [3:0] _txq_io_count; // @[UART.scala:130:19]
wire _txm_io_in_ready; // @[UART.scala:129:19]
wire _txm_io_tx_busy; // @[UART.scala:129:19]
wire auto_control_xing_in_a_valid_0 = auto_control_xing_in_a_valid; // @[UART.scala:127:25]
wire [2:0] auto_control_xing_in_a_bits_opcode_0 = auto_control_xing_in_a_bits_opcode; // @[UART.scala:127:25]
wire [2:0] auto_control_xing_in_a_bits_param_0 = auto_control_xing_in_a_bits_param; // @[UART.scala:127:25]
wire [1:0] auto_control_xing_in_a_bits_size_0 = auto_control_xing_in_a_bits_size; // @[UART.scala:127:25]
wire [12:0] auto_control_xing_in_a_bits_source_0 = auto_control_xing_in_a_bits_source; // @[UART.scala:127:25]
wire [28:0] auto_control_xing_in_a_bits_address_0 = auto_control_xing_in_a_bits_address; // @[UART.scala:127:25]
wire [7:0] auto_control_xing_in_a_bits_mask_0 = auto_control_xing_in_a_bits_mask; // @[UART.scala:127:25]
wire [63:0] auto_control_xing_in_a_bits_data_0 = auto_control_xing_in_a_bits_data; // @[UART.scala:127:25]
wire auto_control_xing_in_a_bits_corrupt_0 = auto_control_xing_in_a_bits_corrupt; // @[UART.scala:127:25]
wire auto_control_xing_in_d_ready_0 = auto_control_xing_in_d_ready; // @[UART.scala:127:25]
wire auto_io_out_rxd_0 = auto_io_out_rxd; // @[UART.scala:127:25]
wire [8:0] out_maskMatch = 9'h1FC; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_15 = 8'h0; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_16 = 8'h0; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_prepend_T = 8'h0; // @[RegisterRouter.scala:87:24]
wire [8:0] out_prepend = 9'h0; // @[RegisterRouter.scala:87:24]
wire [30:0] _out_T_24 = 31'h0; // @[RegisterRouter.scala:87:24]
wire [30:0] _out_T_25 = 31'h0; // @[RegisterRouter.scala:87:24]
wire [30:0] _out_prepend_T_1 = 31'h0; // @[RegisterRouter.scala:87:24]
wire [2:0] controlNodeIn_d_bits_d_opcode = 3'h0; // @[Edges.scala:792:17]
wire [63:0] controlNodeIn_d_bits_d_data = 64'h0; // @[Edges.scala:792:17]
wire auto_control_xing_in_d_bits_sink = 1'h0; // @[UART.scala:127:25]
wire auto_control_xing_in_d_bits_denied = 1'h0; // @[UART.scala:127:25]
wire auto_control_xing_in_d_bits_corrupt = 1'h0; // @[UART.scala:127:25]
wire buffer_auto_in_d_bits_sink = 1'h0; // @[Buffer.scala:40:9]
wire buffer_auto_in_d_bits_denied = 1'h0; // @[Buffer.scala:40:9]
wire buffer_auto_in_d_bits_corrupt = 1'h0; // @[Buffer.scala:40:9]
wire buffer_auto_out_d_bits_sink = 1'h0; // @[Buffer.scala:40:9]
wire buffer_auto_out_d_bits_denied = 1'h0; // @[Buffer.scala:40:9]
wire buffer_auto_out_d_bits_corrupt = 1'h0; // @[Buffer.scala:40:9]
wire buffer_nodeOut_d_bits_sink = 1'h0; // @[MixedNode.scala:542:17]
wire buffer_nodeOut_d_bits_denied = 1'h0; // @[MixedNode.scala:542:17]
wire buffer_nodeOut_d_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17]
wire buffer_nodeIn_d_bits_sink = 1'h0; // @[MixedNode.scala:551:17]
wire buffer_nodeIn_d_bits_denied = 1'h0; // @[MixedNode.scala:551:17]
wire buffer_nodeIn_d_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17]
wire controlNodeIn_d_bits_sink = 1'h0; // @[MixedNode.scala:551:17]
wire controlNodeIn_d_bits_denied = 1'h0; // @[MixedNode.scala:551:17]
wire controlNodeIn_d_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17]
wire controlXingOut_d_bits_sink = 1'h0; // @[MixedNode.scala:542:17]
wire controlXingOut_d_bits_denied = 1'h0; // @[MixedNode.scala:542:17]
wire controlXingOut_d_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17]
wire controlXingIn_d_bits_sink = 1'h0; // @[MixedNode.scala:551:17]
wire controlXingIn_d_bits_denied = 1'h0; // @[MixedNode.scala:551:17]
wire controlXingIn_d_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17]
wire _ie_WIRE_rxwm = 1'h0; // @[UART.scala:186:32]
wire _ie_WIRE_txwm = 1'h0; // @[UART.scala:186:32]
wire _out_rifireMux_T_18 = 1'h0; // @[MuxLiteral.scala:49:17]
wire _out_wifireMux_T_19 = 1'h0; // @[MuxLiteral.scala:49:17]
wire _out_rofireMux_T_18 = 1'h0; // @[MuxLiteral.scala:49:17]
wire _out_wofireMux_T_19 = 1'h0; // @[MuxLiteral.scala:49:17]
wire _out_out_bits_data_T = 1'h0; // @[MuxLiteral.scala:49:17]
wire _out_out_bits_data_T_2 = 1'h0; // @[MuxLiteral.scala:49:17]
wire controlNodeIn_d_bits_d_sink = 1'h0; // @[Edges.scala:792:17]
wire controlNodeIn_d_bits_d_denied = 1'h0; // @[Edges.scala:792:17]
wire controlNodeIn_d_bits_d_corrupt = 1'h0; // @[Edges.scala:792:17]
wire [1:0] auto_control_xing_in_d_bits_param = 2'h0; // @[UART.scala:127:25]
wire [1:0] buffer_auto_in_d_bits_param = 2'h0; // @[Buffer.scala:40:9]
wire [1:0] buffer_auto_out_d_bits_param = 2'h0; // @[Buffer.scala:40:9]
wire [1:0] buffer_nodeOut_d_bits_param = 2'h0; // @[MixedNode.scala:542:17]
wire [1:0] buffer_nodeIn_d_bits_param = 2'h0; // @[MixedNode.scala:551:17]
wire [1:0] controlNodeIn_d_bits_param = 2'h0; // @[MixedNode.scala:551:17]
wire [1:0] controlXingOut_d_bits_param = 2'h0; // @[MixedNode.scala:542:17]
wire [1:0] controlXingIn_d_bits_param = 2'h0; // @[MixedNode.scala:551:17]
wire [1:0] controlNodeIn_d_bits_d_param = 2'h0; // @[Edges.scala:792:17]
wire intXingOut_sync_0; // @[MixedNode.scala:542:17]
wire out_rifireMux_out = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_5 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_1 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_9 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_2 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_13 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_3 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_17 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_2 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_3 = 1'h1; // @[MuxLiteral.scala:49:48]
wire out_rifireMux = 1'h1; // @[MuxLiteral.scala:49:10]
wire out_wifireMux_out = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_6 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_1 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_10 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_2 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_14 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_3 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_18 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_2 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_3 = 1'h1; // @[MuxLiteral.scala:49:48]
wire out_wifireMux = 1'h1; // @[MuxLiteral.scala:49:10]
wire out_rofireMux_out = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_5 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_1 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_9 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_2 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_13 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_3 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_17 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_2 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_3 = 1'h1; // @[MuxLiteral.scala:49:48]
wire out_rofireMux = 1'h1; // @[MuxLiteral.scala:49:10]
wire out_wofireMux_out = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_6 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_1 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_10 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_2 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_14 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_3 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_18 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_2 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_3 = 1'h1; // @[MuxLiteral.scala:49:48]
wire out_wofireMux = 1'h1; // @[MuxLiteral.scala:49:10]
wire out_iready = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_oready = 1'h1; // @[RegisterRouter.scala:87:24]
wire controlXingIn_a_ready; // @[MixedNode.scala:551:17]
wire controlXingIn_a_valid = auto_control_xing_in_a_valid_0; // @[UART.scala:127:25]
wire [2:0] controlXingIn_a_bits_opcode = auto_control_xing_in_a_bits_opcode_0; // @[UART.scala:127:25]
wire [2:0] controlXingIn_a_bits_param = auto_control_xing_in_a_bits_param_0; // @[UART.scala:127:25]
wire [1:0] controlXingIn_a_bits_size = auto_control_xing_in_a_bits_size_0; // @[UART.scala:127:25]
wire [12:0] controlXingIn_a_bits_source = auto_control_xing_in_a_bits_source_0; // @[UART.scala:127:25]
wire [28:0] controlXingIn_a_bits_address = auto_control_xing_in_a_bits_address_0; // @[UART.scala:127:25]
wire [7:0] controlXingIn_a_bits_mask = auto_control_xing_in_a_bits_mask_0; // @[UART.scala:127:25]
wire [63:0] controlXingIn_a_bits_data = auto_control_xing_in_a_bits_data_0; // @[UART.scala:127:25]
wire controlXingIn_a_bits_corrupt = auto_control_xing_in_a_bits_corrupt_0; // @[UART.scala:127:25]
wire controlXingIn_d_ready = auto_control_xing_in_d_ready_0; // @[UART.scala:127:25]
wire controlXingIn_d_valid; // @[MixedNode.scala:551:17]
wire [2:0] controlXingIn_d_bits_opcode; // @[MixedNode.scala:551:17]
wire [1:0] controlXingIn_d_bits_size; // @[MixedNode.scala:551:17]
wire [12:0] controlXingIn_d_bits_source; // @[MixedNode.scala:551:17]
wire [63:0] controlXingIn_d_bits_data; // @[MixedNode.scala:551:17]
wire ioNodeOut_txd; // @[MixedNode.scala:542:17]
wire ioNodeOut_rxd = auto_io_out_rxd_0; // @[UART.scala:127:25]
wire auto_int_xing_out_sync_0_0; // @[UART.scala:127:25]
wire auto_control_xing_in_a_ready_0; // @[UART.scala:127:25]
wire [2:0] auto_control_xing_in_d_bits_opcode_0; // @[UART.scala:127:25]
wire [1:0] auto_control_xing_in_d_bits_size_0; // @[UART.scala:127:25]
wire [12:0] auto_control_xing_in_d_bits_source_0; // @[UART.scala:127:25]
wire [63:0] auto_control_xing_in_d_bits_data_0; // @[UART.scala:127:25]
wire auto_control_xing_in_d_valid_0; // @[UART.scala:127:25]
wire auto_io_out_txd_0; // @[UART.scala:127:25]
wire buffer_nodeIn_a_ready; // @[MixedNode.scala:551:17]
wire controlXingOut_a_ready = buffer_auto_in_a_ready; // @[Buffer.scala:40:9]
wire controlXingOut_a_valid; // @[MixedNode.scala:542:17]
wire buffer_nodeIn_a_valid = buffer_auto_in_a_valid; // @[Buffer.scala:40:9]
wire [2:0] controlXingOut_a_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] buffer_nodeIn_a_bits_opcode = buffer_auto_in_a_bits_opcode; // @[Buffer.scala:40:9]
wire [2:0] controlXingOut_a_bits_param; // @[MixedNode.scala:542:17]
wire [2:0] buffer_nodeIn_a_bits_param = buffer_auto_in_a_bits_param; // @[Buffer.scala:40:9]
wire [1:0] controlXingOut_a_bits_size; // @[MixedNode.scala:542:17]
wire [1:0] buffer_nodeIn_a_bits_size = buffer_auto_in_a_bits_size; // @[Buffer.scala:40:9]
wire [12:0] controlXingOut_a_bits_source; // @[MixedNode.scala:542:17]
wire [12:0] buffer_nodeIn_a_bits_source = buffer_auto_in_a_bits_source; // @[Buffer.scala:40:9]
wire [28:0] controlXingOut_a_bits_address; // @[MixedNode.scala:542:17]
wire [28:0] buffer_nodeIn_a_bits_address = buffer_auto_in_a_bits_address; // @[Buffer.scala:40:9]
wire [7:0] controlXingOut_a_bits_mask; // @[MixedNode.scala:542:17]
wire [7:0] buffer_nodeIn_a_bits_mask = buffer_auto_in_a_bits_mask; // @[Buffer.scala:40:9]
wire [63:0] controlXingOut_a_bits_data; // @[MixedNode.scala:542:17]
wire [63:0] buffer_nodeIn_a_bits_data = buffer_auto_in_a_bits_data; // @[Buffer.scala:40:9]
wire controlXingOut_a_bits_corrupt; // @[MixedNode.scala:542:17]
wire buffer_nodeIn_a_bits_corrupt = buffer_auto_in_a_bits_corrupt; // @[Buffer.scala:40:9]
wire controlXingOut_d_ready; // @[MixedNode.scala:542:17]
wire buffer_nodeIn_d_ready = buffer_auto_in_d_ready; // @[Buffer.scala:40:9]
wire buffer_nodeIn_d_valid; // @[MixedNode.scala:551:17]
wire [2:0] buffer_nodeIn_d_bits_opcode; // @[MixedNode.scala:551:17]
wire controlXingOut_d_valid = buffer_auto_in_d_valid; // @[Buffer.scala:40:9]
wire [2:0] controlXingOut_d_bits_opcode = buffer_auto_in_d_bits_opcode; // @[Buffer.scala:40:9]
wire [1:0] buffer_nodeIn_d_bits_size; // @[MixedNode.scala:551:17]
wire [12:0] buffer_nodeIn_d_bits_source; // @[MixedNode.scala:551:17]
wire [1:0] controlXingOut_d_bits_size = buffer_auto_in_d_bits_size; // @[Buffer.scala:40:9]
wire [12:0] controlXingOut_d_bits_source = buffer_auto_in_d_bits_source; // @[Buffer.scala:40:9]
wire [63:0] buffer_nodeIn_d_bits_data; // @[MixedNode.scala:551:17]
wire [63:0] controlXingOut_d_bits_data = buffer_auto_in_d_bits_data; // @[Buffer.scala:40:9]
wire controlNodeIn_a_ready; // @[MixedNode.scala:551:17]
wire buffer_nodeOut_a_ready = buffer_auto_out_a_ready; // @[Buffer.scala:40:9]
wire buffer_nodeOut_a_valid; // @[MixedNode.scala:542:17]
wire [2:0] buffer_nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17]
wire controlNodeIn_a_valid = buffer_auto_out_a_valid; // @[Buffer.scala:40:9]
wire [2:0] buffer_nodeOut_a_bits_param; // @[MixedNode.scala:542:17]
wire [2:0] controlNodeIn_a_bits_opcode = buffer_auto_out_a_bits_opcode; // @[Buffer.scala:40:9]
wire [1:0] buffer_nodeOut_a_bits_size; // @[MixedNode.scala:542:17]
wire [2:0] controlNodeIn_a_bits_param = buffer_auto_out_a_bits_param; // @[Buffer.scala:40:9]
wire [12:0] buffer_nodeOut_a_bits_source; // @[MixedNode.scala:542:17]
wire [1:0] controlNodeIn_a_bits_size = buffer_auto_out_a_bits_size; // @[Buffer.scala:40:9]
wire [28:0] buffer_nodeOut_a_bits_address; // @[MixedNode.scala:542:17]
wire [12:0] controlNodeIn_a_bits_source = buffer_auto_out_a_bits_source; // @[Buffer.scala:40:9]
wire [7:0] buffer_nodeOut_a_bits_mask; // @[MixedNode.scala:542:17]
wire [28:0] controlNodeIn_a_bits_address = buffer_auto_out_a_bits_address; // @[Buffer.scala:40:9]
wire [63:0] buffer_nodeOut_a_bits_data; // @[MixedNode.scala:542:17]
wire [7:0] controlNodeIn_a_bits_mask = buffer_auto_out_a_bits_mask; // @[Buffer.scala:40:9]
wire buffer_nodeOut_a_bits_corrupt; // @[MixedNode.scala:542:17]
wire [63:0] controlNodeIn_a_bits_data = buffer_auto_out_a_bits_data; // @[Buffer.scala:40:9]
wire buffer_nodeOut_d_ready; // @[MixedNode.scala:542:17]
wire controlNodeIn_a_bits_corrupt = buffer_auto_out_a_bits_corrupt; // @[Buffer.scala:40:9]
wire controlNodeIn_d_ready = buffer_auto_out_d_ready; // @[Buffer.scala:40:9]
wire controlNodeIn_d_valid; // @[MixedNode.scala:551:17]
wire buffer_nodeOut_d_valid = buffer_auto_out_d_valid; // @[Buffer.scala:40:9]
wire [2:0] controlNodeIn_d_bits_opcode; // @[MixedNode.scala:551:17]
wire [2:0] buffer_nodeOut_d_bits_opcode = buffer_auto_out_d_bits_opcode; // @[Buffer.scala:40:9]
wire [1:0] controlNodeIn_d_bits_size; // @[MixedNode.scala:551:17]
wire [1:0] buffer_nodeOut_d_bits_size = buffer_auto_out_d_bits_size; // @[Buffer.scala:40:9]
wire [12:0] controlNodeIn_d_bits_source; // @[MixedNode.scala:551:17]
wire [12:0] buffer_nodeOut_d_bits_source = buffer_auto_out_d_bits_source; // @[Buffer.scala:40:9]
wire [63:0] controlNodeIn_d_bits_data; // @[MixedNode.scala:551:17]
wire [63:0] buffer_nodeOut_d_bits_data = buffer_auto_out_d_bits_data; // @[Buffer.scala:40:9]
assign buffer_nodeIn_a_ready = buffer_nodeOut_a_ready; // @[MixedNode.scala:542:17, :551:17]
assign buffer_auto_out_a_valid = buffer_nodeOut_a_valid; // @[Buffer.scala:40:9]
assign buffer_auto_out_a_bits_opcode = buffer_nodeOut_a_bits_opcode; // @[Buffer.scala:40:9]
assign buffer_auto_out_a_bits_param = buffer_nodeOut_a_bits_param; // @[Buffer.scala:40:9]
assign buffer_auto_out_a_bits_size = buffer_nodeOut_a_bits_size; // @[Buffer.scala:40:9]
assign buffer_auto_out_a_bits_source = buffer_nodeOut_a_bits_source; // @[Buffer.scala:40:9]
assign buffer_auto_out_a_bits_address = buffer_nodeOut_a_bits_address; // @[Buffer.scala:40:9]
assign buffer_auto_out_a_bits_mask = buffer_nodeOut_a_bits_mask; // @[Buffer.scala:40:9]
assign buffer_auto_out_a_bits_data = buffer_nodeOut_a_bits_data; // @[Buffer.scala:40:9]
assign buffer_auto_out_a_bits_corrupt = buffer_nodeOut_a_bits_corrupt; // @[Buffer.scala:40:9]
assign buffer_auto_out_d_ready = buffer_nodeOut_d_ready; // @[Buffer.scala:40:9]
assign buffer_nodeIn_d_valid = buffer_nodeOut_d_valid; // @[MixedNode.scala:542:17, :551:17]
assign buffer_nodeIn_d_bits_opcode = buffer_nodeOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign buffer_nodeIn_d_bits_size = buffer_nodeOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign buffer_nodeIn_d_bits_source = buffer_nodeOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign buffer_nodeIn_d_bits_data = buffer_nodeOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign buffer_auto_in_a_ready = buffer_nodeIn_a_ready; // @[Buffer.scala:40:9]
assign buffer_nodeOut_a_valid = buffer_nodeIn_a_valid; // @[MixedNode.scala:542:17, :551:17]
assign buffer_nodeOut_a_bits_opcode = buffer_nodeIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign buffer_nodeOut_a_bits_param = buffer_nodeIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign buffer_nodeOut_a_bits_size = buffer_nodeIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign buffer_nodeOut_a_bits_source = buffer_nodeIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign buffer_nodeOut_a_bits_address = buffer_nodeIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17]
assign buffer_nodeOut_a_bits_mask = buffer_nodeIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17]
assign buffer_nodeOut_a_bits_data = buffer_nodeIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign buffer_nodeOut_a_bits_corrupt = buffer_nodeIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign buffer_nodeOut_d_ready = buffer_nodeIn_d_ready; // @[MixedNode.scala:542:17, :551:17]
assign buffer_auto_in_d_valid = buffer_nodeIn_d_valid; // @[Buffer.scala:40:9]
assign buffer_auto_in_d_bits_opcode = buffer_nodeIn_d_bits_opcode; // @[Buffer.scala:40:9]
assign buffer_auto_in_d_bits_size = buffer_nodeIn_d_bits_size; // @[Buffer.scala:40:9]
assign buffer_auto_in_d_bits_source = buffer_nodeIn_d_bits_source; // @[Buffer.scala:40:9]
assign buffer_auto_in_d_bits_data = buffer_nodeIn_d_bits_data; // @[Buffer.scala:40:9]
assign auto_io_out_txd_0 = ioNodeOut_txd; // @[UART.scala:127:25]
wire _intnodeOut_0_T_2; // @[UART.scala:191:41]
wire intnodeOut_0; // @[MixedNode.scala:542:17]
wire in_ready; // @[RegisterRouter.scala:73:18]
assign buffer_auto_out_a_ready = controlNodeIn_a_ready; // @[Buffer.scala:40:9]
wire in_valid = controlNodeIn_a_valid; // @[RegisterRouter.scala:73:18]
wire [1:0] in_bits_extra_tlrr_extra_size = controlNodeIn_a_bits_size; // @[RegisterRouter.scala:73:18]
wire [12:0] in_bits_extra_tlrr_extra_source = controlNodeIn_a_bits_source; // @[RegisterRouter.scala:73:18]
wire [7:0] in_bits_mask = controlNodeIn_a_bits_mask; // @[RegisterRouter.scala:73:18]
wire [63:0] in_bits_data = controlNodeIn_a_bits_data; // @[RegisterRouter.scala:73:18]
wire out_ready = controlNodeIn_d_ready; // @[RegisterRouter.scala:87:24]
wire out_valid; // @[RegisterRouter.scala:87:24]
assign buffer_auto_out_d_valid = controlNodeIn_d_valid; // @[Buffer.scala:40:9]
assign buffer_auto_out_d_bits_opcode = controlNodeIn_d_bits_opcode; // @[Buffer.scala:40:9]
wire [1:0] controlNodeIn_d_bits_d_size; // @[Edges.scala:792:17]
assign buffer_auto_out_d_bits_size = controlNodeIn_d_bits_size; // @[Buffer.scala:40:9]
wire [12:0] controlNodeIn_d_bits_d_source; // @[Edges.scala:792:17]
assign buffer_auto_out_d_bits_source = controlNodeIn_d_bits_source; // @[Buffer.scala:40:9]
wire [63:0] out_bits_data; // @[RegisterRouter.scala:87:24]
assign buffer_auto_out_d_bits_data = controlNodeIn_d_bits_data; // @[Buffer.scala:40:9]
assign controlXingIn_a_ready = controlXingOut_a_ready; // @[MixedNode.scala:542:17, :551:17]
assign buffer_auto_in_a_valid = controlXingOut_a_valid; // @[Buffer.scala:40:9]
assign buffer_auto_in_a_bits_opcode = controlXingOut_a_bits_opcode; // @[Buffer.scala:40:9]
assign buffer_auto_in_a_bits_param = controlXingOut_a_bits_param; // @[Buffer.scala:40:9]
assign buffer_auto_in_a_bits_size = controlXingOut_a_bits_size; // @[Buffer.scala:40:9]
assign buffer_auto_in_a_bits_source = controlXingOut_a_bits_source; // @[Buffer.scala:40:9]
assign buffer_auto_in_a_bits_address = controlXingOut_a_bits_address; // @[Buffer.scala:40:9]
assign buffer_auto_in_a_bits_mask = controlXingOut_a_bits_mask; // @[Buffer.scala:40:9]
assign buffer_auto_in_a_bits_data = controlXingOut_a_bits_data; // @[Buffer.scala:40:9]
assign buffer_auto_in_a_bits_corrupt = controlXingOut_a_bits_corrupt; // @[Buffer.scala:40:9]
assign buffer_auto_in_d_ready = controlXingOut_d_ready; // @[Buffer.scala:40:9]
assign controlXingIn_d_valid = controlXingOut_d_valid; // @[MixedNode.scala:542:17, :551:17]
assign controlXingIn_d_bits_opcode = controlXingOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign controlXingIn_d_bits_size = controlXingOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign controlXingIn_d_bits_source = controlXingOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign controlXingIn_d_bits_data = controlXingOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign auto_control_xing_in_a_ready_0 = controlXingIn_a_ready; // @[UART.scala:127:25]
assign controlXingOut_a_valid = controlXingIn_a_valid; // @[MixedNode.scala:542:17, :551:17]
assign controlXingOut_a_bits_opcode = controlXingIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign controlXingOut_a_bits_param = controlXingIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign controlXingOut_a_bits_size = controlXingIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign controlXingOut_a_bits_source = controlXingIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign controlXingOut_a_bits_address = controlXingIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17]
assign controlXingOut_a_bits_mask = controlXingIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17]
assign controlXingOut_a_bits_data = controlXingIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign controlXingOut_a_bits_corrupt = controlXingIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign controlXingOut_d_ready = controlXingIn_d_ready; // @[MixedNode.scala:542:17, :551:17]
assign auto_control_xing_in_d_valid_0 = controlXingIn_d_valid; // @[UART.scala:127:25]
assign auto_control_xing_in_d_bits_opcode_0 = controlXingIn_d_bits_opcode; // @[UART.scala:127:25]
assign auto_control_xing_in_d_bits_size_0 = controlXingIn_d_bits_size; // @[UART.scala:127:25]
assign auto_control_xing_in_d_bits_source_0 = controlXingIn_d_bits_source; // @[UART.scala:127:25]
assign auto_control_xing_in_d_bits_data_0 = controlXingIn_d_bits_data; // @[UART.scala:127:25]
wire intXingIn_sync_0; // @[MixedNode.scala:551:17]
assign auto_int_xing_out_sync_0_0 = intXingOut_sync_0; // @[UART.scala:127:25]
assign intXingOut_sync_0 = intXingIn_sync_0; // @[MixedNode.scala:542:17, :551:17]
reg [15:0] div; // @[UART.scala:135:20]
wire [15:0] _out_T_166 = div; // @[RegisterRouter.scala:87:24]
reg txen; // @[UART.scala:141:21]
wire _out_T_71 = txen; // @[RegisterRouter.scala:87:24]
reg rxen; // @[UART.scala:142:21]
reg [3:0] txwm; // @[UART.scala:149:21]
reg [3:0] rxwm; // @[UART.scala:150:21]
reg nstop; // @[UART.scala:151:22]
wire _tx_busy_T = |_txq_io_count; // @[UART.scala:130:19, :175:49]
wire _tx_busy_T_1 = _txm_io_tx_busy | _tx_busy_T; // @[UART.scala:129:19, :175:{33,49}]
wire tx_busy = _tx_busy_T_1 & txen; // @[UART.scala:141:21, :175:{33,54}]
reg ie_rxwm; // @[UART.scala:186:19]
reg ie_txwm; // @[UART.scala:186:19]
wire _out_T_126 = ie_txwm; // @[RegisterRouter.scala:87:24]
wire _ip_rxwm_T; // @[UART.scala:190:28]
wire _ip_txwm_T; // @[UART.scala:189:28]
wire ip_rxwm; // @[UART.scala:187:16]
wire ip_txwm; // @[UART.scala:187:16]
assign _ip_txwm_T = _txq_io_count < txwm; // @[UART.scala:130:19, :149:21, :189:28]
assign ip_txwm = _ip_txwm_T; // @[UART.scala:187:16, :189:28]
assign _ip_rxwm_T = _rxq_io_count > rxwm; // @[UART.scala:133:19, :150:21, :190:28]
assign ip_rxwm = _ip_rxwm_T; // @[UART.scala:187:16, :190:28]
wire _intnodeOut_0_T = ip_txwm & ie_txwm; // @[UART.scala:186:19, :187:16, :191:29]
wire _intnodeOut_0_T_1 = ip_rxwm & ie_rxwm; // @[UART.scala:186:19, :187:16, :191:53]
assign _intnodeOut_0_T_2 = _intnodeOut_0_T | _intnodeOut_0_T_1; // @[UART.scala:191:{29,41,53}]
assign intnodeOut_0 = _intnodeOut_0_T_2; // @[UART.scala:191:41]
wire _out_quash_T_1; // @[RegMapFIFO.scala:26:26]
wire quash; // @[RegMapFIFO.scala:11:21]
wire _out_in_ready_T; // @[RegisterRouter.scala:87:24]
assign controlNodeIn_a_ready = in_ready; // @[RegisterRouter.scala:73:18]
wire _in_bits_read_T; // @[RegisterRouter.scala:74:36]
wire _out_front_valid_T = in_valid; // @[RegisterRouter.scala:73:18, :87:24]
wire out_front_bits_read = in_bits_read; // @[RegisterRouter.scala:73:18, :87:24]
wire [8:0] out_front_bits_index = in_bits_index; // @[RegisterRouter.scala:73:18, :87:24]
wire [63:0] out_front_bits_data = in_bits_data; // @[RegisterRouter.scala:73:18, :87:24]
wire [7:0] out_front_bits_mask = in_bits_mask; // @[RegisterRouter.scala:73:18, :87:24]
wire [12:0] out_front_bits_extra_tlrr_extra_source = in_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:73:18, :87:24]
wire [1:0] out_front_bits_extra_tlrr_extra_size = in_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:73:18, :87:24]
assign _in_bits_read_T = controlNodeIn_a_bits_opcode == 3'h4; // @[RegisterRouter.scala:74:36]
assign in_bits_read = _in_bits_read_T; // @[RegisterRouter.scala:73:18, :74:36]
wire [25:0] _in_bits_index_T = controlNodeIn_a_bits_address[28:3]; // @[Edges.scala:192:34]
assign in_bits_index = _in_bits_index_T[8:0]; // @[RegisterRouter.scala:73:18, :75:19]
wire _out_front_ready_T = out_ready; // @[RegisterRouter.scala:87:24]
wire _out_out_valid_T; // @[RegisterRouter.scala:87:24]
assign controlNodeIn_d_valid = out_valid; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_out_bits_data_T_4; // @[RegisterRouter.scala:87:24]
wire _controlNodeIn_d_bits_opcode_T = out_bits_read; // @[RegisterRouter.scala:87:24, :105:25]
assign controlNodeIn_d_bits_data = out_bits_data; // @[RegisterRouter.scala:87:24]
assign controlNodeIn_d_bits_d_source = out_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:87:24]
wire [1:0] out_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:87:24]
assign controlNodeIn_d_bits_d_size = out_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:87:24]
assign _out_in_ready_T = out_front_ready; // @[RegisterRouter.scala:87:24]
assign _out_out_valid_T = out_front_valid; // @[RegisterRouter.scala:87:24]
assign out_bits_read = out_front_bits_read; // @[RegisterRouter.scala:87:24]
assign out_bits_extra_tlrr_extra_source = out_front_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:87:24]
assign out_bits_extra_tlrr_extra_size = out_front_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:87:24]
wire [8:0] _GEN = out_front_bits_index & 9'h1FC; // @[RegisterRouter.scala:87:24]
wire [8:0] out_findex; // @[RegisterRouter.scala:87:24]
assign out_findex = _GEN; // @[RegisterRouter.scala:87:24]
wire [8:0] out_bindex; // @[RegisterRouter.scala:87:24]
assign out_bindex = _GEN; // @[RegisterRouter.scala:87:24]
wire _GEN_0 = out_findex == 9'h0; // @[RegisterRouter.scala:87:24]
wire _out_T; // @[RegisterRouter.scala:87:24]
assign _out_T = _GEN_0; // @[RegisterRouter.scala:87:24]
wire _out_T_2; // @[RegisterRouter.scala:87:24]
assign _out_T_2 = _GEN_0; // @[RegisterRouter.scala:87:24]
wire _out_T_4; // @[RegisterRouter.scala:87:24]
assign _out_T_4 = _GEN_0; // @[RegisterRouter.scala:87:24]
wire _out_T_6; // @[RegisterRouter.scala:87:24]
assign _out_T_6 = _GEN_0; // @[RegisterRouter.scala:87:24]
wire _GEN_1 = out_bindex == 9'h0; // @[RegisterRouter.scala:87:24]
wire _out_T_1; // @[RegisterRouter.scala:87:24]
assign _out_T_1 = _GEN_1; // @[RegisterRouter.scala:87:24]
wire _out_T_3; // @[RegisterRouter.scala:87:24]
assign _out_T_3 = _GEN_1; // @[RegisterRouter.scala:87:24]
wire _out_T_5; // @[RegisterRouter.scala:87:24]
assign _out_T_5 = _GEN_1; // @[RegisterRouter.scala:87:24]
wire _out_T_7; // @[RegisterRouter.scala:87:24]
assign _out_T_7 = _GEN_1; // @[RegisterRouter.scala:87:24]
wire _out_out_bits_data_WIRE_0 = _out_T_1; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_1 = _out_T_3; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_2 = _out_T_5; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24]
wire _out_out_bits_data_WIRE_3 = _out_T_7; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_T_7; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_11; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_15; // @[RegisterRouter.scala:87:24]
wire out_rivalid_0; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1; // @[RegisterRouter.scala:87:24]
wire out_rivalid_2; // @[RegisterRouter.scala:87:24]
wire out_rivalid_3; // @[RegisterRouter.scala:87:24]
wire out_rivalid_4; // @[RegisterRouter.scala:87:24]
wire out_rivalid_5; // @[RegisterRouter.scala:87:24]
wire out_rivalid_6; // @[RegisterRouter.scala:87:24]
wire out_rivalid_7; // @[RegisterRouter.scala:87:24]
wire out_rivalid_8; // @[RegisterRouter.scala:87:24]
wire out_rivalid_9; // @[RegisterRouter.scala:87:24]
wire out_rivalid_10; // @[RegisterRouter.scala:87:24]
wire out_rivalid_11; // @[RegisterRouter.scala:87:24]
wire out_rivalid_12; // @[RegisterRouter.scala:87:24]
wire out_rivalid_13; // @[RegisterRouter.scala:87:24]
wire out_rivalid_14; // @[RegisterRouter.scala:87:24]
wire out_rivalid_15; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_8; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_12; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_16; // @[RegisterRouter.scala:87:24]
wire out_wivalid_0; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1; // @[RegisterRouter.scala:87:24]
wire out_wivalid_2; // @[RegisterRouter.scala:87:24]
wire out_wivalid_3; // @[RegisterRouter.scala:87:24]
wire out_wivalid_4; // @[RegisterRouter.scala:87:24]
wire out_wivalid_5; // @[RegisterRouter.scala:87:24]
wire out_wivalid_6; // @[RegisterRouter.scala:87:24]
wire out_wivalid_7; // @[RegisterRouter.scala:87:24]
wire out_wivalid_8; // @[RegisterRouter.scala:87:24]
wire out_wivalid_9; // @[RegisterRouter.scala:87:24]
wire out_wivalid_10; // @[RegisterRouter.scala:87:24]
wire out_wivalid_11; // @[RegisterRouter.scala:87:24]
wire out_wivalid_12; // @[RegisterRouter.scala:87:24]
wire out_wivalid_13; // @[RegisterRouter.scala:87:24]
wire out_wivalid_14; // @[RegisterRouter.scala:87:24]
wire out_wivalid_15; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_7; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_11; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_15; // @[RegisterRouter.scala:87:24]
wire out_roready_0; // @[RegisterRouter.scala:87:24]
wire out_roready_1; // @[RegisterRouter.scala:87:24]
wire out_roready_2; // @[RegisterRouter.scala:87:24]
wire out_roready_3; // @[RegisterRouter.scala:87:24]
wire out_roready_4; // @[RegisterRouter.scala:87:24]
wire out_roready_5; // @[RegisterRouter.scala:87:24]
wire out_roready_6; // @[RegisterRouter.scala:87:24]
wire out_roready_7; // @[RegisterRouter.scala:87:24]
wire out_roready_8; // @[RegisterRouter.scala:87:24]
wire out_roready_9; // @[RegisterRouter.scala:87:24]
wire out_roready_10; // @[RegisterRouter.scala:87:24]
wire out_roready_11; // @[RegisterRouter.scala:87:24]
wire out_roready_12; // @[RegisterRouter.scala:87:24]
wire out_roready_13; // @[RegisterRouter.scala:87:24]
wire out_roready_14; // @[RegisterRouter.scala:87:24]
wire out_roready_15; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_8; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_12; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_16; // @[RegisterRouter.scala:87:24]
wire out_woready_0; // @[RegisterRouter.scala:87:24]
wire out_woready_1; // @[RegisterRouter.scala:87:24]
wire out_woready_2; // @[RegisterRouter.scala:87:24]
wire out_woready_3; // @[RegisterRouter.scala:87:24]
wire out_woready_4; // @[RegisterRouter.scala:87:24]
wire out_woready_5; // @[RegisterRouter.scala:87:24]
wire out_woready_6; // @[RegisterRouter.scala:87:24]
wire out_woready_7; // @[RegisterRouter.scala:87:24]
wire out_woready_8; // @[RegisterRouter.scala:87:24]
wire out_woready_9; // @[RegisterRouter.scala:87:24]
wire out_woready_10; // @[RegisterRouter.scala:87:24]
wire out_woready_11; // @[RegisterRouter.scala:87:24]
wire out_woready_12; // @[RegisterRouter.scala:87:24]
wire out_woready_13; // @[RegisterRouter.scala:87:24]
wire out_woready_14; // @[RegisterRouter.scala:87:24]
wire out_woready_15; // @[RegisterRouter.scala:87:24]
wire _out_frontMask_T = out_front_bits_mask[0]; // @[RegisterRouter.scala:87:24]
wire _out_backMask_T = out_front_bits_mask[0]; // @[RegisterRouter.scala:87:24]
wire _out_frontMask_T_1 = out_front_bits_mask[1]; // @[RegisterRouter.scala:87:24]
wire _out_backMask_T_1 = out_front_bits_mask[1]; // @[RegisterRouter.scala:87:24]
wire _out_frontMask_T_2 = out_front_bits_mask[2]; // @[RegisterRouter.scala:87:24]
wire _out_backMask_T_2 = out_front_bits_mask[2]; // @[RegisterRouter.scala:87:24]
wire _out_frontMask_T_3 = out_front_bits_mask[3]; // @[RegisterRouter.scala:87:24]
wire _out_backMask_T_3 = out_front_bits_mask[3]; // @[RegisterRouter.scala:87:24]
wire _out_frontMask_T_4 = out_front_bits_mask[4]; // @[RegisterRouter.scala:87:24]
wire _out_backMask_T_4 = out_front_bits_mask[4]; // @[RegisterRouter.scala:87:24]
wire _out_frontMask_T_5 = out_front_bits_mask[5]; // @[RegisterRouter.scala:87:24]
wire _out_backMask_T_5 = out_front_bits_mask[5]; // @[RegisterRouter.scala:87:24]
wire _out_frontMask_T_6 = out_front_bits_mask[6]; // @[RegisterRouter.scala:87:24]
wire _out_backMask_T_6 = out_front_bits_mask[6]; // @[RegisterRouter.scala:87:24]
wire _out_frontMask_T_7 = out_front_bits_mask[7]; // @[RegisterRouter.scala:87:24]
wire _out_backMask_T_7 = out_front_bits_mask[7]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_frontMask_T_8 = {8{_out_frontMask_T}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_frontMask_T_9 = {8{_out_frontMask_T_1}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_frontMask_T_10 = {8{_out_frontMask_T_2}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_frontMask_T_11 = {8{_out_frontMask_T_3}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_frontMask_T_12 = {8{_out_frontMask_T_4}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_frontMask_T_13 = {8{_out_frontMask_T_5}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_frontMask_T_14 = {8{_out_frontMask_T_6}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_frontMask_T_15 = {8{_out_frontMask_T_7}}; // @[RegisterRouter.scala:87:24]
wire [15:0] out_frontMask_lo_lo = {_out_frontMask_T_9, _out_frontMask_T_8}; // @[RegisterRouter.scala:87:24]
wire [15:0] out_frontMask_lo_hi = {_out_frontMask_T_11, _out_frontMask_T_10}; // @[RegisterRouter.scala:87:24]
wire [31:0] out_frontMask_lo = {out_frontMask_lo_hi, out_frontMask_lo_lo}; // @[RegisterRouter.scala:87:24]
wire [15:0] out_frontMask_hi_lo = {_out_frontMask_T_13, _out_frontMask_T_12}; // @[RegisterRouter.scala:87:24]
wire [15:0] out_frontMask_hi_hi = {_out_frontMask_T_15, _out_frontMask_T_14}; // @[RegisterRouter.scala:87:24]
wire [31:0] out_frontMask_hi = {out_frontMask_hi_hi, out_frontMask_hi_lo}; // @[RegisterRouter.scala:87:24]
wire [63:0] out_frontMask = {out_frontMask_hi, out_frontMask_lo}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_backMask_T_8 = {8{_out_backMask_T}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_backMask_T_9 = {8{_out_backMask_T_1}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_backMask_T_10 = {8{_out_backMask_T_2}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_backMask_T_11 = {8{_out_backMask_T_3}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_backMask_T_12 = {8{_out_backMask_T_4}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_backMask_T_13 = {8{_out_backMask_T_5}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_backMask_T_14 = {8{_out_backMask_T_6}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_backMask_T_15 = {8{_out_backMask_T_7}}; // @[RegisterRouter.scala:87:24]
wire [15:0] out_backMask_lo_lo = {_out_backMask_T_9, _out_backMask_T_8}; // @[RegisterRouter.scala:87:24]
wire [15:0] out_backMask_lo_hi = {_out_backMask_T_11, _out_backMask_T_10}; // @[RegisterRouter.scala:87:24]
wire [31:0] out_backMask_lo = {out_backMask_lo_hi, out_backMask_lo_lo}; // @[RegisterRouter.scala:87:24]
wire [15:0] out_backMask_hi_lo = {_out_backMask_T_13, _out_backMask_T_12}; // @[RegisterRouter.scala:87:24]
wire [15:0] out_backMask_hi_hi = {_out_backMask_T_15, _out_backMask_T_14}; // @[RegisterRouter.scala:87:24]
wire [31:0] out_backMask_hi = {out_backMask_hi_hi, out_backMask_hi_lo}; // @[RegisterRouter.scala:87:24]
wire [63:0] out_backMask = {out_backMask_hi, out_backMask_lo}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24]
wire out_rimask = |_out_rimask_T; // @[RegisterRouter.scala:87:24]
wire out_wimask = &_out_wimask_T; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T = out_backMask[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T = out_backMask[7:0]; // @[RegisterRouter.scala:87:24]
wire out_romask = |_out_romask_T; // @[RegisterRouter.scala:87:24]
wire out_womask = &_out_womask_T; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid = out_rivalid_0 & out_rimask; // @[RegisterRouter.scala:87:24]
wire out_f_roready = out_roready_0 & out_romask; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid = out_wivalid_0 & out_wimask; // @[RegisterRouter.scala:87:24]
wire _out_T_9 = out_f_wivalid; // @[RegisterRouter.scala:87:24]
wire out_f_woready = out_woready_0 & out_womask; // @[RegisterRouter.scala:87:24]
wire _out_T_10 = out_f_woready; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_8 = out_front_bits_data[7:0]; // @[RegisterRouter.scala:87:24]
wire _out_txq_io_enq_valid_T = ~quash; // @[RegMapFIFO.scala:11:21, :18:33]
wire _out_txq_io_enq_valid_T_1 = out_f_woready & _out_txq_io_enq_valid_T; // @[RegisterRouter.scala:87:24]
wire _out_T_11 = ~out_rimask; // @[RegisterRouter.scala:87:24]
wire _out_T_12 = ~out_wimask; // @[RegisterRouter.scala:87:24]
wire _out_T_13 = ~out_romask; // @[RegisterRouter.scala:87:24]
wire _out_T_14 = ~out_womask; // @[RegisterRouter.scala:87:24]
wire [22:0] _out_rimask_T_1 = out_frontMask[30:8]; // @[RegisterRouter.scala:87:24]
wire [22:0] _out_wimask_T_1 = out_frontMask[30:8]; // @[RegisterRouter.scala:87:24]
wire out_rimask_1 = |_out_rimask_T_1; // @[RegisterRouter.scala:87:24]
wire out_wimask_1 = &_out_wimask_T_1; // @[RegisterRouter.scala:87:24]
wire [22:0] _out_romask_T_1 = out_backMask[30:8]; // @[RegisterRouter.scala:87:24]
wire [22:0] _out_womask_T_1 = out_backMask[30:8]; // @[RegisterRouter.scala:87:24]
wire out_romask_1 = |_out_romask_T_1; // @[RegisterRouter.scala:87:24]
wire out_womask_1 = &_out_womask_T_1; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1 = out_rivalid_1 & out_rimask_1; // @[RegisterRouter.scala:87:24]
wire _out_T_18 = out_f_rivalid_1; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1 = out_roready_1 & out_romask_1; // @[RegisterRouter.scala:87:24]
wire _out_T_19 = out_f_roready_1; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1 = out_wivalid_1 & out_wimask_1; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1 = out_woready_1 & out_womask_1; // @[RegisterRouter.scala:87:24]
wire [22:0] _out_T_17 = out_front_bits_data[30:8]; // @[RegisterRouter.scala:87:24]
wire _out_T_20 = ~out_rimask_1; // @[RegisterRouter.scala:87:24]
wire _out_T_21 = ~out_wimask_1; // @[RegisterRouter.scala:87:24]
wire _out_T_22 = ~out_romask_1; // @[RegisterRouter.scala:87:24]
wire _out_T_23 = ~out_womask_1; // @[RegisterRouter.scala:87:24]
wire _out_rimask_T_2 = out_frontMask[31]; // @[RegisterRouter.scala:87:24]
wire _out_wimask_T_2 = out_frontMask[31]; // @[RegisterRouter.scala:87:24]
wire out_rimask_2 = _out_rimask_T_2; // @[RegisterRouter.scala:87:24]
wire out_wimask_2 = _out_wimask_T_2; // @[RegisterRouter.scala:87:24]
wire _out_romask_T_2 = out_backMask[31]; // @[RegisterRouter.scala:87:24]
wire _out_womask_T_2 = out_backMask[31]; // @[RegisterRouter.scala:87:24]
wire out_romask_2 = _out_romask_T_2; // @[RegisterRouter.scala:87:24]
wire out_womask_2 = _out_womask_T_2; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_2 = out_rivalid_2 & out_rimask_2; // @[RegisterRouter.scala:87:24]
wire _out_T_27 = out_f_rivalid_2; // @[RegisterRouter.scala:87:24]
wire out_f_roready_2 = out_roready_2 & out_romask_2; // @[RegisterRouter.scala:87:24]
wire _out_T_28 = out_f_roready_2; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_2 = out_wivalid_2 & out_wimask_2; // @[RegisterRouter.scala:87:24]
wire out_f_woready_2 = out_woready_2 & out_womask_2; // @[RegisterRouter.scala:87:24]
wire _out_T_26 = out_front_bits_data[31]; // @[RegisterRouter.scala:87:24]
wire _out_quash_T = _out_T_26; // @[RegisterRouter.scala:87:24]
assign _out_quash_T_1 = out_f_woready_2 & _out_quash_T; // @[RegisterRouter.scala:87:24]
assign quash = _out_quash_T_1; // @[RegMapFIFO.scala:11:21, :26:26]
wire _out_T_29 = ~out_rimask_2; // @[RegisterRouter.scala:87:24]
wire _out_T_30 = ~out_wimask_2; // @[RegisterRouter.scala:87:24]
wire _out_T_31 = ~out_romask_2; // @[RegisterRouter.scala:87:24]
wire _out_T_32 = ~out_womask_2; // @[RegisterRouter.scala:87:24]
wire [31:0] out_prepend_1 = {~_txq_io_enq_ready, 31'h0}; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_33 = out_prepend_1; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_34 = _out_T_33; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_prepend_T_2 = _out_T_34; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_3 = out_frontMask[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_3 = out_frontMask[39:32]; // @[RegisterRouter.scala:87:24]
wire out_rimask_3 = |_out_rimask_T_3; // @[RegisterRouter.scala:87:24]
wire out_wimask_3 = &_out_wimask_T_3; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_3 = out_backMask[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_3 = out_backMask[39:32]; // @[RegisterRouter.scala:87:24]
wire out_romask_3 = |_out_romask_T_3; // @[RegisterRouter.scala:87:24]
wire out_womask_3 = &_out_womask_T_3; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_3 = out_rivalid_3 & out_rimask_3; // @[RegisterRouter.scala:87:24]
wire _out_T_36 = out_f_rivalid_3; // @[RegisterRouter.scala:87:24]
wire out_f_roready_3 = out_roready_3 & out_romask_3; // @[RegisterRouter.scala:87:24]
wire _out_T_37 = out_f_roready_3; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_3 = out_wivalid_3 & out_wimask_3; // @[RegisterRouter.scala:87:24]
wire out_f_woready_3 = out_woready_3 & out_womask_3; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_35 = out_front_bits_data[39:32]; // @[RegisterRouter.scala:87:24]
wire _out_T_38 = ~out_rimask_3; // @[RegisterRouter.scala:87:24]
wire _out_T_39 = ~out_wimask_3; // @[RegisterRouter.scala:87:24]
wire _out_T_40 = ~out_romask_3; // @[RegisterRouter.scala:87:24]
wire _out_T_41 = ~out_womask_3; // @[RegisterRouter.scala:87:24]
wire [39:0] out_prepend_2 = {_rxq_io_deq_bits, _out_prepend_T_2}; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_42 = out_prepend_2; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_43 = _out_T_42; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_prepend_T_3 = _out_T_43; // @[RegisterRouter.scala:87:24]
wire [22:0] _out_rimask_T_4 = out_frontMask[62:40]; // @[RegisterRouter.scala:87:24]
wire [22:0] _out_wimask_T_4 = out_frontMask[62:40]; // @[RegisterRouter.scala:87:24]
wire out_rimask_4 = |_out_rimask_T_4; // @[RegisterRouter.scala:87:24]
wire out_wimask_4 = &_out_wimask_T_4; // @[RegisterRouter.scala:87:24]
wire [22:0] _out_romask_T_4 = out_backMask[62:40]; // @[RegisterRouter.scala:87:24]
wire [22:0] _out_womask_T_4 = out_backMask[62:40]; // @[RegisterRouter.scala:87:24]
wire out_romask_4 = |_out_romask_T_4; // @[RegisterRouter.scala:87:24]
wire out_womask_4 = &_out_womask_T_4; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_4 = out_rivalid_4 & out_rimask_4; // @[RegisterRouter.scala:87:24]
wire _out_T_45 = out_f_rivalid_4; // @[RegisterRouter.scala:87:24]
wire out_f_roready_4 = out_roready_4 & out_romask_4; // @[RegisterRouter.scala:87:24]
wire _out_T_46 = out_f_roready_4; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_4 = out_wivalid_4 & out_wimask_4; // @[RegisterRouter.scala:87:24]
wire out_f_woready_4 = out_woready_4 & out_womask_4; // @[RegisterRouter.scala:87:24]
wire [22:0] _out_T_44 = out_front_bits_data[62:40]; // @[RegisterRouter.scala:87:24]
wire _out_T_47 = ~out_rimask_4; // @[RegisterRouter.scala:87:24]
wire _out_T_48 = ~out_wimask_4; // @[RegisterRouter.scala:87:24]
wire _out_T_49 = ~out_romask_4; // @[RegisterRouter.scala:87:24]
wire _out_T_50 = ~out_womask_4; // @[RegisterRouter.scala:87:24]
wire [40:0] out_prepend_3 = {1'h0, _out_prepend_T_3}; // @[RegisterRouter.scala:87:24]
wire [62:0] _out_T_51 = {22'h0, out_prepend_3}; // @[RegisterRouter.scala:87:24]
wire [62:0] _out_T_52 = _out_T_51; // @[RegisterRouter.scala:87:24]
wire [62:0] _out_prepend_T_4 = _out_T_52; // @[RegisterRouter.scala:87:24]
wire _out_rimask_T_5 = out_frontMask[63]; // @[RegisterRouter.scala:87:24]
wire _out_wimask_T_5 = out_frontMask[63]; // @[RegisterRouter.scala:87:24]
wire out_rimask_5 = _out_rimask_T_5; // @[RegisterRouter.scala:87:24]
wire out_wimask_5 = _out_wimask_T_5; // @[RegisterRouter.scala:87:24]
wire _out_romask_T_5 = out_backMask[63]; // @[RegisterRouter.scala:87:24]
wire _out_womask_T_5 = out_backMask[63]; // @[RegisterRouter.scala:87:24]
wire out_romask_5 = _out_romask_T_5; // @[RegisterRouter.scala:87:24]
wire out_womask_5 = _out_womask_T_5; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_5 = out_rivalid_5 & out_rimask_5; // @[RegisterRouter.scala:87:24]
wire _out_T_54 = out_f_rivalid_5; // @[RegisterRouter.scala:87:24]
wire out_f_roready_5 = out_roready_5 & out_romask_5; // @[RegisterRouter.scala:87:24]
wire _out_T_55 = out_f_roready_5; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_5 = out_wivalid_5 & out_wimask_5; // @[RegisterRouter.scala:87:24]
wire out_f_woready_5 = out_woready_5 & out_womask_5; // @[RegisterRouter.scala:87:24]
wire _out_T_53 = out_front_bits_data[63]; // @[RegisterRouter.scala:87:24]
wire _out_T_56 = ~out_rimask_5; // @[RegisterRouter.scala:87:24]
wire _out_T_57 = ~out_wimask_5; // @[RegisterRouter.scala:87:24]
wire _out_T_58 = ~out_romask_5; // @[RegisterRouter.scala:87:24]
wire _out_T_59 = ~out_womask_5; // @[RegisterRouter.scala:87:24]
wire [63:0] out_prepend_4 = {~_rxq_io_deq_valid, _out_prepend_T_4}; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_60 = out_prepend_4; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_61 = _out_T_60; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_out_bits_data_WIRE_1_0 = _out_T_61; // @[MuxLiteral.scala:49:48]
wire _out_rimask_T_6 = out_frontMask[0]; // @[RegisterRouter.scala:87:24]
wire _out_wimask_T_6 = out_frontMask[0]; // @[RegisterRouter.scala:87:24]
wire _out_rimask_T_11 = out_frontMask[0]; // @[RegisterRouter.scala:87:24]
wire _out_wimask_T_11 = out_frontMask[0]; // @[RegisterRouter.scala:87:24]
wire out_rimask_6 = _out_rimask_T_6; // @[RegisterRouter.scala:87:24]
wire out_wimask_6 = _out_wimask_T_6; // @[RegisterRouter.scala:87:24]
wire _out_romask_T_6 = out_backMask[0]; // @[RegisterRouter.scala:87:24]
wire _out_womask_T_6 = out_backMask[0]; // @[RegisterRouter.scala:87:24]
wire _out_romask_T_11 = out_backMask[0]; // @[RegisterRouter.scala:87:24]
wire _out_womask_T_11 = out_backMask[0]; // @[RegisterRouter.scala:87:24]
wire out_romask_6 = _out_romask_T_6; // @[RegisterRouter.scala:87:24]
wire out_womask_6 = _out_womask_T_6; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_6 = out_rivalid_6 & out_rimask_6; // @[RegisterRouter.scala:87:24]
wire _out_T_63 = out_f_rivalid_6; // @[RegisterRouter.scala:87:24]
wire out_f_roready_6 = out_roready_6 & out_romask_6; // @[RegisterRouter.scala:87:24]
wire _out_T_64 = out_f_roready_6; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_6 = out_wivalid_6 & out_wimask_6; // @[RegisterRouter.scala:87:24]
wire _out_T_65 = out_f_wivalid_6; // @[RegisterRouter.scala:87:24]
wire out_f_woready_6 = out_woready_6 & out_womask_6; // @[RegisterRouter.scala:87:24]
wire _out_T_66 = out_f_woready_6; // @[RegisterRouter.scala:87:24]
wire _out_T_62 = out_front_bits_data[0]; // @[RegisterRouter.scala:87:24]
wire _out_T_117 = out_front_bits_data[0]; // @[RegisterRouter.scala:87:24]
wire _out_T_67 = ~out_rimask_6; // @[RegisterRouter.scala:87:24]
wire _out_T_68 = ~out_wimask_6; // @[RegisterRouter.scala:87:24]
wire _out_T_69 = ~out_romask_6; // @[RegisterRouter.scala:87:24]
wire _out_T_70 = ~out_womask_6; // @[RegisterRouter.scala:87:24]
wire _out_T_72 = _out_T_71; // @[RegisterRouter.scala:87:24]
wire _out_prepend_T_5 = _out_T_72; // @[RegisterRouter.scala:87:24]
wire _out_rimask_T_7 = out_frontMask[1]; // @[RegisterRouter.scala:87:24]
wire _out_wimask_T_7 = out_frontMask[1]; // @[RegisterRouter.scala:87:24]
wire _out_rimask_T_12 = out_frontMask[1]; // @[RegisterRouter.scala:87:24]
wire _out_wimask_T_12 = out_frontMask[1]; // @[RegisterRouter.scala:87:24]
wire out_rimask_7 = _out_rimask_T_7; // @[RegisterRouter.scala:87:24]
wire out_wimask_7 = _out_wimask_T_7; // @[RegisterRouter.scala:87:24]
wire _out_romask_T_7 = out_backMask[1]; // @[RegisterRouter.scala:87:24]
wire _out_womask_T_7 = out_backMask[1]; // @[RegisterRouter.scala:87:24]
wire _out_romask_T_12 = out_backMask[1]; // @[RegisterRouter.scala:87:24]
wire _out_womask_T_12 = out_backMask[1]; // @[RegisterRouter.scala:87:24]
wire out_romask_7 = _out_romask_T_7; // @[RegisterRouter.scala:87:24]
wire out_womask_7 = _out_womask_T_7; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_7 = out_rivalid_7 & out_rimask_7; // @[RegisterRouter.scala:87:24]
wire _out_T_74 = out_f_rivalid_7; // @[RegisterRouter.scala:87:24]
wire out_f_roready_7 = out_roready_7 & out_romask_7; // @[RegisterRouter.scala:87:24]
wire _out_T_75 = out_f_roready_7; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_7 = out_wivalid_7 & out_wimask_7; // @[RegisterRouter.scala:87:24]
wire _out_T_76 = out_f_wivalid_7; // @[RegisterRouter.scala:87:24]
wire out_f_woready_7 = out_woready_7 & out_womask_7; // @[RegisterRouter.scala:87:24]
wire _out_T_77 = out_f_woready_7; // @[RegisterRouter.scala:87:24]
wire _out_T_73 = out_front_bits_data[1]; // @[RegisterRouter.scala:87:24]
wire _out_T_128 = out_front_bits_data[1]; // @[RegisterRouter.scala:87:24]
wire _out_T_78 = ~out_rimask_7; // @[RegisterRouter.scala:87:24]
wire _out_T_79 = ~out_wimask_7; // @[RegisterRouter.scala:87:24]
wire _out_T_80 = ~out_romask_7; // @[RegisterRouter.scala:87:24]
wire _out_T_81 = ~out_womask_7; // @[RegisterRouter.scala:87:24]
wire [1:0] out_prepend_5 = {nstop, _out_prepend_T_5}; // @[RegisterRouter.scala:87:24]
wire [1:0] _out_T_82 = out_prepend_5; // @[RegisterRouter.scala:87:24]
wire [1:0] _out_T_83 = _out_T_82; // @[RegisterRouter.scala:87:24]
wire [3:0] _out_rimask_T_8 = out_frontMask[19:16]; // @[RegisterRouter.scala:87:24]
wire [3:0] _out_wimask_T_8 = out_frontMask[19:16]; // @[RegisterRouter.scala:87:24]
wire out_rimask_8 = |_out_rimask_T_8; // @[RegisterRouter.scala:87:24]
wire out_wimask_8 = &_out_wimask_T_8; // @[RegisterRouter.scala:87:24]
wire [3:0] _out_romask_T_8 = out_backMask[19:16]; // @[RegisterRouter.scala:87:24]
wire [3:0] _out_womask_T_8 = out_backMask[19:16]; // @[RegisterRouter.scala:87:24]
wire out_romask_8 = |_out_romask_T_8; // @[RegisterRouter.scala:87:24]
wire out_womask_8 = &_out_womask_T_8; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_8 = out_rivalid_8 & out_rimask_8; // @[RegisterRouter.scala:87:24]
wire _out_T_85 = out_f_rivalid_8; // @[RegisterRouter.scala:87:24]
wire out_f_roready_8 = out_roready_8 & out_romask_8; // @[RegisterRouter.scala:87:24]
wire _out_T_86 = out_f_roready_8; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_8 = out_wivalid_8 & out_wimask_8; // @[RegisterRouter.scala:87:24]
wire _out_T_87 = out_f_wivalid_8; // @[RegisterRouter.scala:87:24]
wire out_f_woready_8 = out_woready_8 & out_womask_8; // @[RegisterRouter.scala:87:24]
wire _out_T_88 = out_f_woready_8; // @[RegisterRouter.scala:87:24]
wire [3:0] _out_T_84 = out_front_bits_data[19:16]; // @[RegisterRouter.scala:87:24]
wire _out_T_89 = ~out_rimask_8; // @[RegisterRouter.scala:87:24]
wire _out_T_90 = ~out_wimask_8; // @[RegisterRouter.scala:87:24]
wire _out_T_91 = ~out_romask_8; // @[RegisterRouter.scala:87:24]
wire _out_T_92 = ~out_womask_8; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_prepend_T_6 = {14'h0, _out_T_83}; // @[RegisterRouter.scala:87:24]
wire [19:0] out_prepend_6 = {txwm, _out_prepend_T_6}; // @[RegisterRouter.scala:87:24]
wire [19:0] _out_T_93 = out_prepend_6; // @[RegisterRouter.scala:87:24]
wire [19:0] _out_T_94 = _out_T_93; // @[RegisterRouter.scala:87:24]
wire _out_rimask_T_9 = out_frontMask[32]; // @[RegisterRouter.scala:87:24]
wire _out_wimask_T_9 = out_frontMask[32]; // @[RegisterRouter.scala:87:24]
wire _out_rimask_T_13 = out_frontMask[32]; // @[RegisterRouter.scala:87:24]
wire _out_wimask_T_13 = out_frontMask[32]; // @[RegisterRouter.scala:87:24]
wire out_rimask_9 = _out_rimask_T_9; // @[RegisterRouter.scala:87:24]
wire out_wimask_9 = _out_wimask_T_9; // @[RegisterRouter.scala:87:24]
wire _out_romask_T_9 = out_backMask[32]; // @[RegisterRouter.scala:87:24]
wire _out_womask_T_9 = out_backMask[32]; // @[RegisterRouter.scala:87:24]
wire _out_romask_T_13 = out_backMask[32]; // @[RegisterRouter.scala:87:24]
wire _out_womask_T_13 = out_backMask[32]; // @[RegisterRouter.scala:87:24]
wire out_romask_9 = _out_romask_T_9; // @[RegisterRouter.scala:87:24]
wire out_womask_9 = _out_womask_T_9; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_9 = out_rivalid_9 & out_rimask_9; // @[RegisterRouter.scala:87:24]
wire _out_T_96 = out_f_rivalid_9; // @[RegisterRouter.scala:87:24]
wire out_f_roready_9 = out_roready_9 & out_romask_9; // @[RegisterRouter.scala:87:24]
wire _out_T_97 = out_f_roready_9; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_9 = out_wivalid_9 & out_wimask_9; // @[RegisterRouter.scala:87:24]
wire _out_T_98 = out_f_wivalid_9; // @[RegisterRouter.scala:87:24]
wire out_f_woready_9 = out_woready_9 & out_womask_9; // @[RegisterRouter.scala:87:24]
wire _out_T_99 = out_f_woready_9; // @[RegisterRouter.scala:87:24]
wire _out_T_95 = out_front_bits_data[32]; // @[RegisterRouter.scala:87:24]
wire _out_T_139 = out_front_bits_data[32]; // @[RegisterRouter.scala:87:24]
wire _out_T_100 = ~out_rimask_9; // @[RegisterRouter.scala:87:24]
wire _out_T_101 = ~out_wimask_9; // @[RegisterRouter.scala:87:24]
wire _out_T_102 = ~out_romask_9; // @[RegisterRouter.scala:87:24]
wire _out_T_103 = ~out_womask_9; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_prepend_T_7 = {12'h0, _out_T_94}; // @[RegisterRouter.scala:87:24]
wire [32:0] out_prepend_7 = {rxen, _out_prepend_T_7}; // @[RegisterRouter.scala:87:24]
wire [32:0] _out_T_104 = out_prepend_7; // @[RegisterRouter.scala:87:24]
wire [32:0] _out_T_105 = _out_T_104; // @[RegisterRouter.scala:87:24]
wire [3:0] _out_rimask_T_10 = out_frontMask[51:48]; // @[RegisterRouter.scala:87:24]
wire [3:0] _out_wimask_T_10 = out_frontMask[51:48]; // @[RegisterRouter.scala:87:24]
wire out_rimask_10 = |_out_rimask_T_10; // @[RegisterRouter.scala:87:24]
wire out_wimask_10 = &_out_wimask_T_10; // @[RegisterRouter.scala:87:24]
wire [3:0] _out_romask_T_10 = out_backMask[51:48]; // @[RegisterRouter.scala:87:24]
wire [3:0] _out_womask_T_10 = out_backMask[51:48]; // @[RegisterRouter.scala:87:24]
wire out_romask_10 = |_out_romask_T_10; // @[RegisterRouter.scala:87:24]
wire out_womask_10 = &_out_womask_T_10; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_10 = out_rivalid_10 & out_rimask_10; // @[RegisterRouter.scala:87:24]
wire _out_T_107 = out_f_rivalid_10; // @[RegisterRouter.scala:87:24]
wire out_f_roready_10 = out_roready_10 & out_romask_10; // @[RegisterRouter.scala:87:24]
wire _out_T_108 = out_f_roready_10; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_10 = out_wivalid_10 & out_wimask_10; // @[RegisterRouter.scala:87:24]
wire _out_T_109 = out_f_wivalid_10; // @[RegisterRouter.scala:87:24]
wire out_f_woready_10 = out_woready_10 & out_womask_10; // @[RegisterRouter.scala:87:24]
wire _out_T_110 = out_f_woready_10; // @[RegisterRouter.scala:87:24]
wire [3:0] _out_T_106 = out_front_bits_data[51:48]; // @[RegisterRouter.scala:87:24]
wire _out_T_111 = ~out_rimask_10; // @[RegisterRouter.scala:87:24]
wire _out_T_112 = ~out_wimask_10; // @[RegisterRouter.scala:87:24]
wire _out_T_113 = ~out_romask_10; // @[RegisterRouter.scala:87:24]
wire _out_T_114 = ~out_womask_10; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_prepend_T_8 = {15'h0, _out_T_105}; // @[RegisterRouter.scala:87:24]
wire [51:0] out_prepend_8 = {rxwm, _out_prepend_T_8}; // @[RegisterRouter.scala:87:24]
wire [51:0] _out_T_115 = out_prepend_8; // @[RegisterRouter.scala:87:24]
wire [51:0] _out_T_116 = _out_T_115; // @[RegisterRouter.scala:87:24]
wire out_rimask_11 = _out_rimask_T_11; // @[RegisterRouter.scala:87:24]
wire out_wimask_11 = _out_wimask_T_11; // @[RegisterRouter.scala:87:24]
wire out_romask_11 = _out_romask_T_11; // @[RegisterRouter.scala:87:24]
wire out_womask_11 = _out_womask_T_11; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_11 = out_rivalid_11 & out_rimask_11; // @[RegisterRouter.scala:87:24]
wire _out_T_118 = out_f_rivalid_11; // @[RegisterRouter.scala:87:24]
wire out_f_roready_11 = out_roready_11 & out_romask_11; // @[RegisterRouter.scala:87:24]
wire _out_T_119 = out_f_roready_11; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_11 = out_wivalid_11 & out_wimask_11; // @[RegisterRouter.scala:87:24]
wire _out_T_120 = out_f_wivalid_11; // @[RegisterRouter.scala:87:24]
wire out_f_woready_11 = out_woready_11 & out_womask_11; // @[RegisterRouter.scala:87:24]
wire _out_T_121 = out_f_woready_11; // @[RegisterRouter.scala:87:24]
wire _out_T_122 = ~out_rimask_11; // @[RegisterRouter.scala:87:24]
wire _out_T_123 = ~out_wimask_11; // @[RegisterRouter.scala:87:24]
wire _out_T_124 = ~out_romask_11; // @[RegisterRouter.scala:87:24]
wire _out_T_125 = ~out_womask_11; // @[RegisterRouter.scala:87:24]
wire _out_T_127 = _out_T_126; // @[RegisterRouter.scala:87:24]
wire _out_prepend_T_9 = _out_T_127; // @[RegisterRouter.scala:87:24]
wire out_rimask_12 = _out_rimask_T_12; // @[RegisterRouter.scala:87:24]
wire out_wimask_12 = _out_wimask_T_12; // @[RegisterRouter.scala:87:24]
wire out_romask_12 = _out_romask_T_12; // @[RegisterRouter.scala:87:24]
wire out_womask_12 = _out_womask_T_12; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_12 = out_rivalid_12 & out_rimask_12; // @[RegisterRouter.scala:87:24]
wire _out_T_129 = out_f_rivalid_12; // @[RegisterRouter.scala:87:24]
wire out_f_roready_12 = out_roready_12 & out_romask_12; // @[RegisterRouter.scala:87:24]
wire _out_T_130 = out_f_roready_12; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_12 = out_wivalid_12 & out_wimask_12; // @[RegisterRouter.scala:87:24]
wire _out_T_131 = out_f_wivalid_12; // @[RegisterRouter.scala:87:24]
wire out_f_woready_12 = out_woready_12 & out_womask_12; // @[RegisterRouter.scala:87:24]
wire _out_T_132 = out_f_woready_12; // @[RegisterRouter.scala:87:24]
wire _out_T_133 = ~out_rimask_12; // @[RegisterRouter.scala:87:24]
wire _out_T_134 = ~out_wimask_12; // @[RegisterRouter.scala:87:24]
wire _out_T_135 = ~out_romask_12; // @[RegisterRouter.scala:87:24]
wire _out_T_136 = ~out_womask_12; // @[RegisterRouter.scala:87:24]
wire [1:0] out_prepend_9 = {ie_rxwm, _out_prepend_T_9}; // @[RegisterRouter.scala:87:24]
wire [1:0] _out_T_137 = out_prepend_9; // @[RegisterRouter.scala:87:24]
wire [1:0] _out_T_138 = _out_T_137; // @[RegisterRouter.scala:87:24]
wire out_rimask_13 = _out_rimask_T_13; // @[RegisterRouter.scala:87:24]
wire out_wimask_13 = _out_wimask_T_13; // @[RegisterRouter.scala:87:24]
wire out_romask_13 = _out_romask_T_13; // @[RegisterRouter.scala:87:24]
wire out_womask_13 = _out_womask_T_13; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_13 = out_rivalid_13 & out_rimask_13; // @[RegisterRouter.scala:87:24]
wire _out_T_140 = out_f_rivalid_13; // @[RegisterRouter.scala:87:24]
wire out_f_roready_13 = out_roready_13 & out_romask_13; // @[RegisterRouter.scala:87:24]
wire _out_T_141 = out_f_roready_13; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_13 = out_wivalid_13 & out_wimask_13; // @[RegisterRouter.scala:87:24]
wire out_f_woready_13 = out_woready_13 & out_womask_13; // @[RegisterRouter.scala:87:24]
wire _out_T_142 = ~out_rimask_13; // @[RegisterRouter.scala:87:24]
wire _out_T_143 = ~out_wimask_13; // @[RegisterRouter.scala:87:24]
wire _out_T_144 = ~out_romask_13; // @[RegisterRouter.scala:87:24]
wire _out_T_145 = ~out_womask_13; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_prepend_T_10 = {30'h0, _out_T_138}; // @[RegisterRouter.scala:87:24]
wire [32:0] out_prepend_10 = {ip_txwm, _out_prepend_T_10}; // @[RegisterRouter.scala:87:24]
wire [32:0] _out_T_146 = out_prepend_10; // @[RegisterRouter.scala:87:24]
wire [32:0] _out_T_147 = _out_T_146; // @[RegisterRouter.scala:87:24]
wire [32:0] _out_prepend_T_11 = _out_T_147; // @[RegisterRouter.scala:87:24]
wire _out_rimask_T_14 = out_frontMask[33]; // @[RegisterRouter.scala:87:24]
wire _out_wimask_T_14 = out_frontMask[33]; // @[RegisterRouter.scala:87:24]
wire out_rimask_14 = _out_rimask_T_14; // @[RegisterRouter.scala:87:24]
wire out_wimask_14 = _out_wimask_T_14; // @[RegisterRouter.scala:87:24]
wire _out_romask_T_14 = out_backMask[33]; // @[RegisterRouter.scala:87:24]
wire _out_womask_T_14 = out_backMask[33]; // @[RegisterRouter.scala:87:24]
wire out_romask_14 = _out_romask_T_14; // @[RegisterRouter.scala:87:24]
wire out_womask_14 = _out_womask_T_14; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_14 = out_rivalid_14 & out_rimask_14; // @[RegisterRouter.scala:87:24]
wire _out_T_149 = out_f_rivalid_14; // @[RegisterRouter.scala:87:24]
wire out_f_roready_14 = out_roready_14 & out_romask_14; // @[RegisterRouter.scala:87:24]
wire _out_T_150 = out_f_roready_14; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_14 = out_wivalid_14 & out_wimask_14; // @[RegisterRouter.scala:87:24]
wire out_f_woready_14 = out_woready_14 & out_womask_14; // @[RegisterRouter.scala:87:24]
wire _out_T_148 = out_front_bits_data[33]; // @[RegisterRouter.scala:87:24]
wire _out_T_151 = ~out_rimask_14; // @[RegisterRouter.scala:87:24]
wire _out_T_152 = ~out_wimask_14; // @[RegisterRouter.scala:87:24]
wire _out_T_153 = ~out_romask_14; // @[RegisterRouter.scala:87:24]
wire _out_T_154 = ~out_womask_14; // @[RegisterRouter.scala:87:24]
wire [33:0] out_prepend_11 = {ip_rxwm, _out_prepend_T_11}; // @[RegisterRouter.scala:87:24]
wire [33:0] _out_T_155 = out_prepend_11; // @[RegisterRouter.scala:87:24]
wire [33:0] _out_T_156 = _out_T_155; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_rimask_T_15 = out_frontMask[15:0]; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_wimask_T_15 = out_frontMask[15:0]; // @[RegisterRouter.scala:87:24]
wire out_rimask_15 = |_out_rimask_T_15; // @[RegisterRouter.scala:87:24]
wire out_wimask_15 = &_out_wimask_T_15; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_romask_T_15 = out_backMask[15:0]; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_womask_T_15 = out_backMask[15:0]; // @[RegisterRouter.scala:87:24]
wire out_romask_15 = |_out_romask_T_15; // @[RegisterRouter.scala:87:24]
wire out_womask_15 = &_out_womask_T_15; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_15 = out_rivalid_15 & out_rimask_15; // @[RegisterRouter.scala:87:24]
wire _out_T_158 = out_f_rivalid_15; // @[RegisterRouter.scala:87:24]
wire out_f_roready_15 = out_roready_15 & out_romask_15; // @[RegisterRouter.scala:87:24]
wire _out_T_159 = out_f_roready_15; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_15 = out_wivalid_15 & out_wimask_15; // @[RegisterRouter.scala:87:24]
wire _out_T_160 = out_f_wivalid_15; // @[RegisterRouter.scala:87:24]
wire out_f_woready_15 = out_woready_15 & out_womask_15; // @[RegisterRouter.scala:87:24]
wire _out_T_161 = out_f_woready_15; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_157 = out_front_bits_data[15:0]; // @[RegisterRouter.scala:87:24]
wire _out_T_162 = ~out_rimask_15; // @[RegisterRouter.scala:87:24]
wire _out_T_163 = ~out_wimask_15; // @[RegisterRouter.scala:87:24]
wire _out_T_164 = ~out_romask_15; // @[RegisterRouter.scala:87:24]
wire _out_T_165 = ~out_womask_15; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_167 = _out_T_166; // @[RegisterRouter.scala:87:24]
wire _out_iindex_T = out_front_bits_index[0]; // @[RegisterRouter.scala:87:24]
wire _out_oindex_T = out_front_bits_index[0]; // @[RegisterRouter.scala:87:24]
wire _out_iindex_T_1 = out_front_bits_index[1]; // @[RegisterRouter.scala:87:24]
wire _out_oindex_T_1 = out_front_bits_index[1]; // @[RegisterRouter.scala:87:24]
wire _out_iindex_T_2 = out_front_bits_index[2]; // @[RegisterRouter.scala:87:24]
wire _out_oindex_T_2 = out_front_bits_index[2]; // @[RegisterRouter.scala:87:24]
wire _out_iindex_T_3 = out_front_bits_index[3]; // @[RegisterRouter.scala:87:24]
wire _out_oindex_T_3 = out_front_bits_index[3]; // @[RegisterRouter.scala:87:24]
wire _out_iindex_T_4 = out_front_bits_index[4]; // @[RegisterRouter.scala:87:24]
wire _out_oindex_T_4 = out_front_bits_index[4]; // @[RegisterRouter.scala:87:24]
wire _out_iindex_T_5 = out_front_bits_index[5]; // @[RegisterRouter.scala:87:24]
wire _out_oindex_T_5 = out_front_bits_index[5]; // @[RegisterRouter.scala:87:24]
wire _out_iindex_T_6 = out_front_bits_index[6]; // @[RegisterRouter.scala:87:24]
wire _out_oindex_T_6 = out_front_bits_index[6]; // @[RegisterRouter.scala:87:24]
wire _out_iindex_T_7 = out_front_bits_index[7]; // @[RegisterRouter.scala:87:24]
wire _out_oindex_T_7 = out_front_bits_index[7]; // @[RegisterRouter.scala:87:24]
wire _out_iindex_T_8 = out_front_bits_index[8]; // @[RegisterRouter.scala:87:24]
wire _out_oindex_T_8 = out_front_bits_index[8]; // @[RegisterRouter.scala:87:24]
wire [1:0] out_iindex = {_out_iindex_T_1, _out_iindex_T}; // @[RegisterRouter.scala:87:24]
wire [1:0] out_oindex = {_out_oindex_T_1, _out_oindex_T}; // @[RegisterRouter.scala:87:24]
wire [3:0] _out_frontSel_T = 4'h1 << out_iindex; // @[OneHot.scala:58:35]
wire out_frontSel_0 = _out_frontSel_T[0]; // @[OneHot.scala:58:35]
wire out_frontSel_1 = _out_frontSel_T[1]; // @[OneHot.scala:58:35]
wire out_frontSel_2 = _out_frontSel_T[2]; // @[OneHot.scala:58:35]
wire out_frontSel_3 = _out_frontSel_T[3]; // @[OneHot.scala:58:35]
wire [3:0] _out_backSel_T = 4'h1 << out_oindex; // @[OneHot.scala:58:35]
wire out_backSel_0 = _out_backSel_T[0]; // @[OneHot.scala:58:35]
wire out_backSel_1 = _out_backSel_T[1]; // @[OneHot.scala:58:35]
wire out_backSel_2 = _out_backSel_T[2]; // @[OneHot.scala:58:35]
wire out_backSel_3 = _out_backSel_T[3]; // @[OneHot.scala:58:35]
wire _GEN_2 = in_valid & out_front_ready; // @[RegisterRouter.scala:73:18, :87:24]
wire _out_rifireMux_T; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T = _GEN_2; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T = _GEN_2; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1 = _out_rifireMux_T & out_front_bits_read; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_2 = _out_rifireMux_T_1 & out_frontSel_0; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_3 = _out_rifireMux_T_2 & _out_T; // @[RegisterRouter.scala:87:24]
assign out_rivalid_0 = _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1 = _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24]
assign out_rivalid_2 = _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24]
assign out_rivalid_3 = _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24]
assign out_rivalid_4 = _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24]
assign out_rivalid_5 = _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_4 = ~_out_T; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_6 = _out_rifireMux_T_1 & out_frontSel_1; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_7 = _out_rifireMux_T_6 & _out_T_2; // @[RegisterRouter.scala:87:24]
assign out_rivalid_6 = _out_rifireMux_T_7; // @[RegisterRouter.scala:87:24]
assign out_rivalid_7 = _out_rifireMux_T_7; // @[RegisterRouter.scala:87:24]
assign out_rivalid_8 = _out_rifireMux_T_7; // @[RegisterRouter.scala:87:24]
assign out_rivalid_9 = _out_rifireMux_T_7; // @[RegisterRouter.scala:87:24]
assign out_rivalid_10 = _out_rifireMux_T_7; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_8 = ~_out_T_2; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_10 = _out_rifireMux_T_1 & out_frontSel_2; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_11 = _out_rifireMux_T_10 & _out_T_4; // @[RegisterRouter.scala:87:24]
assign out_rivalid_11 = _out_rifireMux_T_11; // @[RegisterRouter.scala:87:24]
assign out_rivalid_12 = _out_rifireMux_T_11; // @[RegisterRouter.scala:87:24]
assign out_rivalid_13 = _out_rifireMux_T_11; // @[RegisterRouter.scala:87:24]
assign out_rivalid_14 = _out_rifireMux_T_11; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_12 = ~_out_T_4; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_14 = _out_rifireMux_T_1 & out_frontSel_3; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_15 = _out_rifireMux_T_14 & _out_T_6; // @[RegisterRouter.scala:87:24]
assign out_rivalid_15 = _out_rifireMux_T_15; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_16 = ~_out_T_6; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1 = ~out_front_bits_read; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_2 = _out_wifireMux_T & _out_wifireMux_T_1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_3 = _out_wifireMux_T_2 & out_frontSel_0; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_4 = _out_wifireMux_T_3 & _out_T; // @[RegisterRouter.scala:87:24]
assign out_wivalid_0 = _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1 = _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24]
assign out_wivalid_2 = _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24]
assign out_wivalid_3 = _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24]
assign out_wivalid_4 = _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24]
assign out_wivalid_5 = _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_5 = ~_out_T; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_7 = _out_wifireMux_T_2 & out_frontSel_1; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_8 = _out_wifireMux_T_7 & _out_T_2; // @[RegisterRouter.scala:87:24]
assign out_wivalid_6 = _out_wifireMux_T_8; // @[RegisterRouter.scala:87:24]
assign out_wivalid_7 = _out_wifireMux_T_8; // @[RegisterRouter.scala:87:24]
assign out_wivalid_8 = _out_wifireMux_T_8; // @[RegisterRouter.scala:87:24]
assign out_wivalid_9 = _out_wifireMux_T_8; // @[RegisterRouter.scala:87:24]
assign out_wivalid_10 = _out_wifireMux_T_8; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_9 = ~_out_T_2; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_11 = _out_wifireMux_T_2 & out_frontSel_2; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_12 = _out_wifireMux_T_11 & _out_T_4; // @[RegisterRouter.scala:87:24]
assign out_wivalid_11 = _out_wifireMux_T_12; // @[RegisterRouter.scala:87:24]
assign out_wivalid_12 = _out_wifireMux_T_12; // @[RegisterRouter.scala:87:24]
assign out_wivalid_13 = _out_wifireMux_T_12; // @[RegisterRouter.scala:87:24]
assign out_wivalid_14 = _out_wifireMux_T_12; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_13 = ~_out_T_4; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_15 = _out_wifireMux_T_2 & out_frontSel_3; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_16 = _out_wifireMux_T_15 & _out_T_6; // @[RegisterRouter.scala:87:24]
assign out_wivalid_15 = _out_wifireMux_T_16; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_17 = ~_out_T_6; // @[RegisterRouter.scala:87:24]
wire _GEN_3 = out_front_valid & out_ready; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T = _GEN_3; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T = _GEN_3; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1 = _out_rofireMux_T & out_front_bits_read; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_2 = _out_rofireMux_T_1 & out_backSel_0; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_3 = _out_rofireMux_T_2 & _out_T_1; // @[RegisterRouter.scala:87:24]
assign out_roready_0 = _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24]
assign out_roready_1 = _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24]
assign out_roready_2 = _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24]
assign out_roready_3 = _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24]
assign out_roready_4 = _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24]
assign out_roready_5 = _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_4 = ~_out_T_1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_6 = _out_rofireMux_T_1 & out_backSel_1; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_7 = _out_rofireMux_T_6 & _out_T_3; // @[RegisterRouter.scala:87:24]
assign out_roready_6 = _out_rofireMux_T_7; // @[RegisterRouter.scala:87:24]
assign out_roready_7 = _out_rofireMux_T_7; // @[RegisterRouter.scala:87:24]
assign out_roready_8 = _out_rofireMux_T_7; // @[RegisterRouter.scala:87:24]
assign out_roready_9 = _out_rofireMux_T_7; // @[RegisterRouter.scala:87:24]
assign out_roready_10 = _out_rofireMux_T_7; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_8 = ~_out_T_3; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_10 = _out_rofireMux_T_1 & out_backSel_2; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_11 = _out_rofireMux_T_10 & _out_T_5; // @[RegisterRouter.scala:87:24]
assign out_roready_11 = _out_rofireMux_T_11; // @[RegisterRouter.scala:87:24]
assign out_roready_12 = _out_rofireMux_T_11; // @[RegisterRouter.scala:87:24]
assign out_roready_13 = _out_rofireMux_T_11; // @[RegisterRouter.scala:87:24]
assign out_roready_14 = _out_rofireMux_T_11; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_12 = ~_out_T_5; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_14 = _out_rofireMux_T_1 & out_backSel_3; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_15 = _out_rofireMux_T_14 & _out_T_7; // @[RegisterRouter.scala:87:24]
assign out_roready_15 = _out_rofireMux_T_15; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_16 = ~_out_T_7; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1 = ~out_front_bits_read; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_2 = _out_wofireMux_T & _out_wofireMux_T_1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_3 = _out_wofireMux_T_2 & out_backSel_0; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_4 = _out_wofireMux_T_3 & _out_T_1; // @[RegisterRouter.scala:87:24]
assign out_woready_0 = _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24]
assign out_woready_1 = _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24]
assign out_woready_2 = _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24]
assign out_woready_3 = _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24]
assign out_woready_4 = _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24]
assign out_woready_5 = _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_5 = ~_out_T_1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_7 = _out_wofireMux_T_2 & out_backSel_1; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_8 = _out_wofireMux_T_7 & _out_T_3; // @[RegisterRouter.scala:87:24]
assign out_woready_6 = _out_wofireMux_T_8; // @[RegisterRouter.scala:87:24]
assign out_woready_7 = _out_wofireMux_T_8; // @[RegisterRouter.scala:87:24]
assign out_woready_8 = _out_wofireMux_T_8; // @[RegisterRouter.scala:87:24]
assign out_woready_9 = _out_wofireMux_T_8; // @[RegisterRouter.scala:87:24]
assign out_woready_10 = _out_wofireMux_T_8; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_9 = ~_out_T_3; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_11 = _out_wofireMux_T_2 & out_backSel_2; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_12 = _out_wofireMux_T_11 & _out_T_5; // @[RegisterRouter.scala:87:24]
assign out_woready_11 = _out_wofireMux_T_12; // @[RegisterRouter.scala:87:24]
assign out_woready_12 = _out_wofireMux_T_12; // @[RegisterRouter.scala:87:24]
assign out_woready_13 = _out_wofireMux_T_12; // @[RegisterRouter.scala:87:24]
assign out_woready_14 = _out_wofireMux_T_12; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_13 = ~_out_T_5; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_15 = _out_wofireMux_T_2 & out_backSel_3; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_16 = _out_wofireMux_T_15 & _out_T_7; // @[RegisterRouter.scala:87:24]
assign out_woready_15 = _out_wofireMux_T_16; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_17 = ~_out_T_7; // @[RegisterRouter.scala:87:24]
assign in_ready = _out_in_ready_T; // @[RegisterRouter.scala:73:18, :87:24]
assign out_front_valid = _out_front_valid_T; // @[RegisterRouter.scala:87:24]
assign out_front_ready = _out_front_ready_T; // @[RegisterRouter.scala:87:24]
assign out_valid = _out_out_valid_T; // @[RegisterRouter.scala:87:24]
wire [3:0] _GEN_4 = {{_out_out_bits_data_WIRE_3}, {_out_out_bits_data_WIRE_2}, {_out_out_bits_data_WIRE_1}, {_out_out_bits_data_WIRE_0}}; // @[MuxLiteral.scala:49:{10,48}]
wire _out_out_bits_data_T_1 = _GEN_4[out_oindex]; // @[MuxLiteral.scala:49:10]
wire [63:0] _out_out_bits_data_WIRE_1_1 = {12'h0, _out_T_116}; // @[MuxLiteral.scala:49:48]
wire [63:0] _out_out_bits_data_WIRE_1_2 = {30'h0, _out_T_156}; // @[MuxLiteral.scala:49:48]
wire [63:0] _out_out_bits_data_WIRE_1_3 = {48'h0, _out_T_167}; // @[MuxLiteral.scala:49:48]
wire [3:0][63:0] _GEN_5 = {{_out_out_bits_data_WIRE_1_3}, {_out_out_bits_data_WIRE_1_2}, {_out_out_bits_data_WIRE_1_1}, {_out_out_bits_data_WIRE_1_0}}; // @[MuxLiteral.scala:49:{10,48}]
wire [63:0] _out_out_bits_data_T_3 = _GEN_5[out_oindex]; // @[MuxLiteral.scala:49:10]
assign _out_out_bits_data_T_4 = _out_out_bits_data_T_1 ? _out_out_bits_data_T_3 : 64'h0; // @[MuxLiteral.scala:49:10]
assign out_bits_data = _out_out_bits_data_T_4; // @[RegisterRouter.scala:87:24]
assign controlNodeIn_d_bits_size = controlNodeIn_d_bits_d_size; // @[Edges.scala:792:17]
assign controlNodeIn_d_bits_source = controlNodeIn_d_bits_d_source; // @[Edges.scala:792:17]
assign controlNodeIn_d_bits_opcode = {2'h0, _controlNodeIn_d_bits_opcode_T}; // @[RegisterRouter.scala:105:{19,25}]
always @(posedge clock) begin // @[UART.scala:127:25]
if (reset) begin // @[UART.scala:127:25]
div <= 16'h10F4; // @[UART.scala:135:20]
txen <= 1'h0; // @[UART.scala:141:21]
rxen <= 1'h0; // @[UART.scala:142:21]
txwm <= 4'h0; // @[UART.scala:149:21]
rxwm <= 4'h0; // @[UART.scala:150:21]
nstop <= 1'h0; // @[UART.scala:151:22]
ie_rxwm <= 1'h0; // @[UART.scala:186:19]
ie_txwm <= 1'h0; // @[UART.scala:186:19]
end
else begin // @[UART.scala:127:25]
if (out_f_woready_15) // @[RegisterRouter.scala:87:24]
div <= _out_T_157; // @[RegisterRouter.scala:87:24]
if (out_f_woready_6) // @[RegisterRouter.scala:87:24]
txen <= _out_T_62; // @[RegisterRouter.scala:87:24]
if (out_f_woready_9) // @[RegisterRouter.scala:87:24]
rxen <= _out_T_95; // @[RegisterRouter.scala:87:24]
if (out_f_woready_8) // @[RegisterRouter.scala:87:24]
txwm <= _out_T_84; // @[RegisterRouter.scala:87:24]
if (out_f_woready_10) // @[RegisterRouter.scala:87:24]
rxwm <= _out_T_106; // @[RegisterRouter.scala:87:24]
if (out_f_woready_7) // @[RegisterRouter.scala:87:24]
nstop <= _out_T_73; // @[RegisterRouter.scala:87:24]
if (out_f_woready_12) // @[RegisterRouter.scala:87:24]
ie_rxwm <= _out_T_128; // @[RegisterRouter.scala:87:24]
if (out_f_woready_11) // @[RegisterRouter.scala:87:24]
ie_txwm <= _out_T_117; // @[RegisterRouter.scala:87:24]
end
always @(posedge)
IntSyncCrossingSource_n1x1_5 intsource ( // @[Crossing.scala:29:31]
.clock (clock),
.reset (reset),
.auto_in_0 (intnodeOut_0), // @[MixedNode.scala:542:17]
.auto_out_sync_0 (intXingIn_sync_0)
); // @[Crossing.scala:29:31]
TLMonitor_60 monitor ( // @[Nodes.scala:27:25]
.clock (clock),
.reset (reset),
.io_in_a_ready (controlNodeIn_a_ready), // @[MixedNode.scala:551:17]
.io_in_a_valid (controlNodeIn_a_valid), // @[MixedNode.scala:551:17]
.io_in_a_bits_opcode (controlNodeIn_a_bits_opcode), // @[MixedNode.scala:551:17]
.io_in_a_bits_param (controlNodeIn_a_bits_param), // @[MixedNode.scala:551:17]
.io_in_a_bits_size (controlNodeIn_a_bits_size), // @[MixedNode.scala:551:17]
.io_in_a_bits_source (controlNodeIn_a_bits_source), // @[MixedNode.scala:551:17]
.io_in_a_bits_address (controlNodeIn_a_bits_address), // @[MixedNode.scala:551:17]
.io_in_a_bits_mask (controlNodeIn_a_bits_mask), // @[MixedNode.scala:551:17]
.io_in_a_bits_data (controlNodeIn_a_bits_data), // @[MixedNode.scala:551:17]
.io_in_a_bits_corrupt (controlNodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17]
.io_in_d_ready (controlNodeIn_d_ready), // @[MixedNode.scala:551:17]
.io_in_d_valid (controlNodeIn_d_valid), // @[MixedNode.scala:551:17]
.io_in_d_bits_opcode (controlNodeIn_d_bits_opcode), // @[MixedNode.scala:551:17]
.io_in_d_bits_size (controlNodeIn_d_bits_size), // @[MixedNode.scala:551:17]
.io_in_d_bits_source (controlNodeIn_d_bits_source), // @[MixedNode.scala:551:17]
.io_in_d_bits_data (controlNodeIn_d_bits_data) // @[MixedNode.scala:551:17]
); // @[Nodes.scala:27:25]
UARTTx txm ( // @[UART.scala:129:19]
.clock (clock),
.reset (reset),
.io_en (txen), // @[UART.scala:141:21]
.io_in_ready (_txm_io_in_ready),
.io_in_valid (_txq_io_deq_valid), // @[UART.scala:130:19]
.io_in_bits (_txq_io_deq_bits), // @[UART.scala:130:19]
.io_out (ioNodeOut_txd),
.io_div (div), // @[UART.scala:135:20]
.io_nstop (nstop), // @[UART.scala:151:22]
.io_tx_busy (_txm_io_tx_busy)
); // @[UART.scala:129:19]
Queue8_UInt8 txq ( // @[UART.scala:130:19]
.clock (clock),
.reset (reset),
.io_enq_ready (_txq_io_enq_ready),
.io_enq_valid (_out_txq_io_enq_valid_T_1), // @[RegMapFIFO.scala:18:30]
.io_enq_bits (_out_T_8), // @[RegisterRouter.scala:87:24]
.io_deq_ready (_txm_io_in_ready), // @[UART.scala:129:19]
.io_deq_valid (_txq_io_deq_valid),
.io_deq_bits (_txq_io_deq_bits),
.io_count (_txq_io_count)
); // @[UART.scala:130:19]
UARTRx rxm ( // @[UART.scala:132:19]
.clock (clock),
.reset (reset),
.io_en (rxen), // @[UART.scala:142:21]
.io_in (ioNodeOut_rxd), // @[MixedNode.scala:542:17]
.io_out_valid (_rxm_io_out_valid),
.io_out_bits (_rxm_io_out_bits),
.io_div (div) // @[UART.scala:135:20]
); // @[UART.scala:132:19]
Queue8_UInt8_1 rxq ( // @[UART.scala:133:19]
.clock (clock),
.reset (reset),
.io_enq_valid (_rxm_io_out_valid), // @[UART.scala:132:19]
.io_enq_bits (_rxm_io_out_bits), // @[UART.scala:132:19]
.io_deq_ready (out_f_roready_3), // @[RegisterRouter.scala:87:24]
.io_deq_valid (_rxq_io_deq_valid),
.io_deq_bits (_rxq_io_deq_bits),
.io_count (_rxq_io_count)
); // @[UART.scala:133:19]
assign auto_int_xing_out_sync_0 = auto_int_xing_out_sync_0_0; // @[UART.scala:127:25]
assign auto_control_xing_in_a_ready = auto_control_xing_in_a_ready_0; // @[UART.scala:127:25]
assign auto_control_xing_in_d_valid = auto_control_xing_in_d_valid_0; // @[UART.scala:127:25]
assign auto_control_xing_in_d_bits_opcode = auto_control_xing_in_d_bits_opcode_0; // @[UART.scala:127:25]
assign auto_control_xing_in_d_bits_size = auto_control_xing_in_d_bits_size_0; // @[UART.scala:127:25]
assign auto_control_xing_in_d_bits_source = auto_control_xing_in_d_bits_source_0; // @[UART.scala:127:25]
assign auto_control_xing_in_d_bits_data = auto_control_xing_in_d_bits_data_0; // @[UART.scala:127:25]
assign auto_io_out_txd = auto_io_out_txd_0; // @[UART.scala:127:25]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File MSHR.scala:
/*
* Copyright 2019 SiFive, Inc.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You should have received a copy of LICENSE.Apache2 along with
* this software. If not, you may obtain a copy at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
package sifive.blocks.inclusivecache
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceInfo
import freechips.rocketchip.tilelink._
import TLPermissions._
import TLMessages._
import MetaData._
import chisel3.PrintableHelper
import chisel3.experimental.dataview._
class ScheduleRequest(params: InclusiveCacheParameters) extends InclusiveCacheBundle(params)
{
val a = Valid(new SourceARequest(params))
val b = Valid(new SourceBRequest(params))
val c = Valid(new SourceCRequest(params))
val d = Valid(new SourceDRequest(params))
val e = Valid(new SourceERequest(params))
val x = Valid(new SourceXRequest(params))
val dir = Valid(new DirectoryWrite(params))
val reload = Bool() // get next request via allocate (if any)
}
class MSHRStatus(params: InclusiveCacheParameters) extends InclusiveCacheBundle(params)
{
val set = UInt(params.setBits.W)
val tag = UInt(params.tagBits.W)
val way = UInt(params.wayBits.W)
val blockB = Bool()
val nestB = Bool()
val blockC = Bool()
val nestC = Bool()
}
class NestedWriteback(params: InclusiveCacheParameters) extends InclusiveCacheBundle(params)
{
val set = UInt(params.setBits.W)
val tag = UInt(params.tagBits.W)
val b_toN = Bool() // nested Probes may unhit us
val b_toB = Bool() // nested Probes may demote us
val b_clr_dirty = Bool() // nested Probes clear dirty
val c_set_dirty = Bool() // nested Releases MAY set dirty
}
sealed trait CacheState
{
val code = CacheState.index.U
CacheState.index = CacheState.index + 1
}
object CacheState
{
var index = 0
}
case object S_INVALID extends CacheState
case object S_BRANCH extends CacheState
case object S_BRANCH_C extends CacheState
case object S_TIP extends CacheState
case object S_TIP_C extends CacheState
case object S_TIP_CD extends CacheState
case object S_TIP_D extends CacheState
case object S_TRUNK_C extends CacheState
case object S_TRUNK_CD extends CacheState
class MSHR(params: InclusiveCacheParameters) extends Module
{
val io = IO(new Bundle {
val allocate = Flipped(Valid(new AllocateRequest(params))) // refills MSHR for next cycle
val directory = Flipped(Valid(new DirectoryResult(params))) // triggers schedule setup
val status = Valid(new MSHRStatus(params))
val schedule = Decoupled(new ScheduleRequest(params))
val sinkc = Flipped(Valid(new SinkCResponse(params)))
val sinkd = Flipped(Valid(new SinkDResponse(params)))
val sinke = Flipped(Valid(new SinkEResponse(params)))
val nestedwb = Flipped(new NestedWriteback(params))
})
val request_valid = RegInit(false.B)
val request = Reg(new FullRequest(params))
val meta_valid = RegInit(false.B)
val meta = Reg(new DirectoryResult(params))
// Define which states are valid
when (meta_valid) {
when (meta.state === INVALID) {
assert (!meta.clients.orR)
assert (!meta.dirty)
}
when (meta.state === BRANCH) {
assert (!meta.dirty)
}
when (meta.state === TRUNK) {
assert (meta.clients.orR)
assert ((meta.clients & (meta.clients - 1.U)) === 0.U) // at most one
}
when (meta.state === TIP) {
// noop
}
}
// Completed transitions (s_ = scheduled), (w_ = waiting)
val s_rprobe = RegInit(true.B) // B
val w_rprobeackfirst = RegInit(true.B)
val w_rprobeacklast = RegInit(true.B)
val s_release = RegInit(true.B) // CW w_rprobeackfirst
val w_releaseack = RegInit(true.B)
val s_pprobe = RegInit(true.B) // B
val s_acquire = RegInit(true.B) // A s_release, s_pprobe [1]
val s_flush = RegInit(true.B) // X w_releaseack
val w_grantfirst = RegInit(true.B)
val w_grantlast = RegInit(true.B)
val w_grant = RegInit(true.B) // first | last depending on wormhole
val w_pprobeackfirst = RegInit(true.B)
val w_pprobeacklast = RegInit(true.B)
val w_pprobeack = RegInit(true.B) // first | last depending on wormhole
val s_probeack = RegInit(true.B) // C w_pprobeackfirst (mutually exclusive with next two s_*)
val s_grantack = RegInit(true.B) // E w_grantfirst ... CAN require both outE&inD to service outD
val s_execute = RegInit(true.B) // D w_pprobeack, w_grant
val w_grantack = RegInit(true.B)
val s_writeback = RegInit(true.B) // W w_*
// [1]: We cannot issue outer Acquire while holding blockB (=> outA can stall)
// However, inB and outC are higher priority than outB, so s_release and s_pprobe
// may be safely issued while blockB. Thus we must NOT try to schedule the
// potentially stuck s_acquire with either of them (scheduler is all or none).
// Meta-data that we discover underway
val sink = Reg(UInt(params.outer.bundle.sinkBits.W))
val gotT = Reg(Bool())
val bad_grant = Reg(Bool())
val probes_done = Reg(UInt(params.clientBits.W))
val probes_toN = Reg(UInt(params.clientBits.W))
val probes_noT = Reg(Bool())
// When a nested transaction completes, update our meta data
when (meta_valid && meta.state =/= INVALID &&
io.nestedwb.set === request.set && io.nestedwb.tag === meta.tag) {
when (io.nestedwb.b_clr_dirty) { meta.dirty := false.B }
when (io.nestedwb.c_set_dirty) { meta.dirty := true.B }
when (io.nestedwb.b_toB) { meta.state := BRANCH }
when (io.nestedwb.b_toN) { meta.hit := false.B }
}
// Scheduler status
io.status.valid := request_valid
io.status.bits.set := request.set
io.status.bits.tag := request.tag
io.status.bits.way := meta.way
io.status.bits.blockB := !meta_valid || ((!w_releaseack || !w_rprobeacklast || !w_pprobeacklast) && !w_grantfirst)
io.status.bits.nestB := meta_valid && w_releaseack && w_rprobeacklast && w_pprobeacklast && !w_grantfirst
// The above rules ensure we will block and not nest an outer probe while still doing our
// own inner probes. Thus every probe wakes exactly one MSHR.
io.status.bits.blockC := !meta_valid
io.status.bits.nestC := meta_valid && (!w_rprobeackfirst || !w_pprobeackfirst || !w_grantfirst)
// The w_grantfirst in nestC is necessary to deal with:
// acquire waiting for grant, inner release gets queued, outer probe -> inner probe -> deadlock
// ... this is possible because the release+probe can be for same set, but different tag
// We can only demand: block, nest, or queue
assert (!io.status.bits.nestB || !io.status.bits.blockB)
assert (!io.status.bits.nestC || !io.status.bits.blockC)
// Scheduler requests
val no_wait = w_rprobeacklast && w_releaseack && w_grantlast && w_pprobeacklast && w_grantack
io.schedule.bits.a.valid := !s_acquire && s_release && s_pprobe
io.schedule.bits.b.valid := !s_rprobe || !s_pprobe
io.schedule.bits.c.valid := (!s_release && w_rprobeackfirst) || (!s_probeack && w_pprobeackfirst)
io.schedule.bits.d.valid := !s_execute && w_pprobeack && w_grant
io.schedule.bits.e.valid := !s_grantack && w_grantfirst
io.schedule.bits.x.valid := !s_flush && w_releaseack
io.schedule.bits.dir.valid := (!s_release && w_rprobeackfirst) || (!s_writeback && no_wait)
io.schedule.bits.reload := no_wait
io.schedule.valid := io.schedule.bits.a.valid || io.schedule.bits.b.valid || io.schedule.bits.c.valid ||
io.schedule.bits.d.valid || io.schedule.bits.e.valid || io.schedule.bits.x.valid ||
io.schedule.bits.dir.valid
// Schedule completions
when (io.schedule.ready) {
s_rprobe := true.B
when (w_rprobeackfirst) { s_release := true.B }
s_pprobe := true.B
when (s_release && s_pprobe) { s_acquire := true.B }
when (w_releaseack) { s_flush := true.B }
when (w_pprobeackfirst) { s_probeack := true.B }
when (w_grantfirst) { s_grantack := true.B }
when (w_pprobeack && w_grant) { s_execute := true.B }
when (no_wait) { s_writeback := true.B }
// Await the next operation
when (no_wait) {
request_valid := false.B
meta_valid := false.B
}
}
// Resulting meta-data
val final_meta_writeback = WireInit(meta)
val req_clientBit = params.clientBit(request.source)
val req_needT = needT(request.opcode, request.param)
val req_acquire = request.opcode === AcquireBlock || request.opcode === AcquirePerm
val meta_no_clients = !meta.clients.orR
val req_promoteT = req_acquire && Mux(meta.hit, meta_no_clients && meta.state === TIP, gotT)
when (request.prio(2) && (!params.firstLevel).B) { // always a hit
final_meta_writeback.dirty := meta.dirty || request.opcode(0)
final_meta_writeback.state := Mux(request.param =/= TtoT && meta.state === TRUNK, TIP, meta.state)
final_meta_writeback.clients := meta.clients & ~Mux(isToN(request.param), req_clientBit, 0.U)
final_meta_writeback.hit := true.B // chained requests are hits
} .elsewhen (request.control && params.control.B) { // request.prio(0)
when (meta.hit) {
final_meta_writeback.dirty := false.B
final_meta_writeback.state := INVALID
final_meta_writeback.clients := meta.clients & ~probes_toN
}
final_meta_writeback.hit := false.B
} .otherwise {
final_meta_writeback.dirty := (meta.hit && meta.dirty) || !request.opcode(2)
final_meta_writeback.state := Mux(req_needT,
Mux(req_acquire, TRUNK, TIP),
Mux(!meta.hit, Mux(gotT, Mux(req_acquire, TRUNK, TIP), BRANCH),
MuxLookup(meta.state, 0.U(2.W))(Seq(
INVALID -> BRANCH,
BRANCH -> BRANCH,
TRUNK -> TIP,
TIP -> Mux(meta_no_clients && req_acquire, TRUNK, TIP)))))
final_meta_writeback.clients := Mux(meta.hit, meta.clients & ~probes_toN, 0.U) |
Mux(req_acquire, req_clientBit, 0.U)
final_meta_writeback.tag := request.tag
final_meta_writeback.hit := true.B
}
when (bad_grant) {
when (meta.hit) {
// upgrade failed (B -> T)
assert (!meta_valid || meta.state === BRANCH)
final_meta_writeback.hit := true.B
final_meta_writeback.dirty := false.B
final_meta_writeback.state := BRANCH
final_meta_writeback.clients := meta.clients & ~probes_toN
} .otherwise {
// failed N -> (T or B)
final_meta_writeback.hit := false.B
final_meta_writeback.dirty := false.B
final_meta_writeback.state := INVALID
final_meta_writeback.clients := 0.U
}
}
val invalid = Wire(new DirectoryEntry(params))
invalid.dirty := false.B
invalid.state := INVALID
invalid.clients := 0.U
invalid.tag := 0.U
// Just because a client says BtoT, by the time we process the request he may be N.
// Therefore, we must consult our own meta-data state to confirm he owns the line still.
val honour_BtoT = meta.hit && (meta.clients & req_clientBit).orR
// The client asking us to act is proof they don't have permissions.
val excluded_client = Mux(meta.hit && request.prio(0) && skipProbeN(request.opcode, params.cache.hintsSkipProbe), req_clientBit, 0.U)
io.schedule.bits.a.bits.tag := request.tag
io.schedule.bits.a.bits.set := request.set
io.schedule.bits.a.bits.param := Mux(req_needT, Mux(meta.hit, BtoT, NtoT), NtoB)
io.schedule.bits.a.bits.block := request.size =/= log2Ceil(params.cache.blockBytes).U ||
!(request.opcode === PutFullData || request.opcode === AcquirePerm)
io.schedule.bits.a.bits.source := 0.U
io.schedule.bits.b.bits.param := Mux(!s_rprobe, toN, Mux(request.prio(1), request.param, Mux(req_needT, toN, toB)))
io.schedule.bits.b.bits.tag := Mux(!s_rprobe, meta.tag, request.tag)
io.schedule.bits.b.bits.set := request.set
io.schedule.bits.b.bits.clients := meta.clients & ~excluded_client
io.schedule.bits.c.bits.opcode := Mux(meta.dirty, ReleaseData, Release)
io.schedule.bits.c.bits.param := Mux(meta.state === BRANCH, BtoN, TtoN)
io.schedule.bits.c.bits.source := 0.U
io.schedule.bits.c.bits.tag := meta.tag
io.schedule.bits.c.bits.set := request.set
io.schedule.bits.c.bits.way := meta.way
io.schedule.bits.c.bits.dirty := meta.dirty
io.schedule.bits.d.bits.viewAsSupertype(chiselTypeOf(request)) := request
io.schedule.bits.d.bits.param := Mux(!req_acquire, request.param,
MuxLookup(request.param, request.param)(Seq(
NtoB -> Mux(req_promoteT, NtoT, NtoB),
BtoT -> Mux(honour_BtoT, BtoT, NtoT),
NtoT -> NtoT)))
io.schedule.bits.d.bits.sink := 0.U
io.schedule.bits.d.bits.way := meta.way
io.schedule.bits.d.bits.bad := bad_grant
io.schedule.bits.e.bits.sink := sink
io.schedule.bits.x.bits.fail := false.B
io.schedule.bits.dir.bits.set := request.set
io.schedule.bits.dir.bits.way := meta.way
io.schedule.bits.dir.bits.data := Mux(!s_release, invalid, WireInit(new DirectoryEntry(params), init = final_meta_writeback))
// Coverage of state transitions
def cacheState(entry: DirectoryEntry, hit: Bool) = {
val out = WireDefault(0.U)
val c = entry.clients.orR
val d = entry.dirty
switch (entry.state) {
is (BRANCH) { out := Mux(c, S_BRANCH_C.code, S_BRANCH.code) }
is (TRUNK) { out := Mux(d, S_TRUNK_CD.code, S_TRUNK_C.code) }
is (TIP) { out := Mux(c, Mux(d, S_TIP_CD.code, S_TIP_C.code), Mux(d, S_TIP_D.code, S_TIP.code)) }
is (INVALID) { out := S_INVALID.code }
}
when (!hit) { out := S_INVALID.code }
out
}
val p = !params.lastLevel // can be probed
val c = !params.firstLevel // can be acquired
val m = params.inner.client.clients.exists(!_.supports.probe) // can be written (or read)
val r = params.outer.manager.managers.exists(!_.alwaysGrantsT) // read-only devices exist
val f = params.control // flush control register exists
val cfg = (p, c, m, r, f)
val b = r || p // can reach branch state (via probe downgrade or read-only device)
// The cache must be used for something or we would not be here
require(c || m)
val evict = cacheState(meta, !meta.hit)
val before = cacheState(meta, meta.hit)
val after = cacheState(final_meta_writeback, true.B)
def eviction(from: CacheState, cover: Boolean)(implicit sourceInfo: SourceInfo) {
if (cover) {
params.ccover(evict === from.code, s"MSHR_${from}_EVICT", s"State transition from ${from} to evicted ${cfg}")
} else {
assert(!(evict === from.code), cf"State transition from ${from} to evicted should be impossible ${cfg}")
}
if (cover && f) {
params.ccover(before === from.code, s"MSHR_${from}_FLUSH", s"State transition from ${from} to flushed ${cfg}")
} else {
assert(!(before === from.code), cf"State transition from ${from} to flushed should be impossible ${cfg}")
}
}
def transition(from: CacheState, to: CacheState, cover: Boolean)(implicit sourceInfo: SourceInfo) {
if (cover) {
params.ccover(before === from.code && after === to.code, s"MSHR_${from}_${to}", s"State transition from ${from} to ${to} ${cfg}")
} else {
assert(!(before === from.code && after === to.code), cf"State transition from ${from} to ${to} should be impossible ${cfg}")
}
}
when ((!s_release && w_rprobeackfirst) && io.schedule.ready) {
eviction(S_BRANCH, b) // MMIO read to read-only device
eviction(S_BRANCH_C, b && c) // you need children to become C
eviction(S_TIP, true) // MMIO read || clean release can lead to this state
eviction(S_TIP_C, c) // needs two clients || client + mmio || downgrading client
eviction(S_TIP_CD, c) // needs two clients || client + mmio || downgrading client
eviction(S_TIP_D, true) // MMIO write || dirty release lead here
eviction(S_TRUNK_C, c) // acquire for write
eviction(S_TRUNK_CD, c) // dirty release then reacquire
}
when ((!s_writeback && no_wait) && io.schedule.ready) {
transition(S_INVALID, S_BRANCH, b && m) // only MMIO can bring us to BRANCH state
transition(S_INVALID, S_BRANCH_C, b && c) // C state is only possible if there are inner caches
transition(S_INVALID, S_TIP, m) // MMIO read
transition(S_INVALID, S_TIP_C, false) // we would go S_TRUNK_C instead
transition(S_INVALID, S_TIP_CD, false) // acquire does not cause dirty immediately
transition(S_INVALID, S_TIP_D, m) // MMIO write
transition(S_INVALID, S_TRUNK_C, c) // acquire
transition(S_INVALID, S_TRUNK_CD, false) // acquire does not cause dirty immediately
transition(S_BRANCH, S_INVALID, b && p) // probe can do this (flushes run as evictions)
transition(S_BRANCH, S_BRANCH_C, b && c) // acquire
transition(S_BRANCH, S_TIP, b && m) // prefetch write
transition(S_BRANCH, S_TIP_C, false) // we would go S_TRUNK_C instead
transition(S_BRANCH, S_TIP_CD, false) // acquire does not cause dirty immediately
transition(S_BRANCH, S_TIP_D, b && m) // MMIO write
transition(S_BRANCH, S_TRUNK_C, b && c) // acquire
transition(S_BRANCH, S_TRUNK_CD, false) // acquire does not cause dirty immediately
transition(S_BRANCH_C, S_INVALID, b && c && p)
transition(S_BRANCH_C, S_BRANCH, b && c) // clean release (optional)
transition(S_BRANCH_C, S_TIP, b && c && m) // prefetch write
transition(S_BRANCH_C, S_TIP_C, false) // we would go S_TRUNK_C instead
transition(S_BRANCH_C, S_TIP_D, b && c && m) // MMIO write
transition(S_BRANCH_C, S_TIP_CD, false) // going dirty means we must shoot down clients
transition(S_BRANCH_C, S_TRUNK_C, b && c) // acquire
transition(S_BRANCH_C, S_TRUNK_CD, false) // acquire does not cause dirty immediately
transition(S_TIP, S_INVALID, p)
transition(S_TIP, S_BRANCH, p) // losing TIP only possible via probe
transition(S_TIP, S_BRANCH_C, false) // we would go S_TRUNK_C instead
transition(S_TIP, S_TIP_C, false) // we would go S_TRUNK_C instead
transition(S_TIP, S_TIP_D, m) // direct dirty only via MMIO write
transition(S_TIP, S_TIP_CD, false) // acquire does not make us dirty immediately
transition(S_TIP, S_TRUNK_C, c) // acquire
transition(S_TIP, S_TRUNK_CD, false) // acquire does not make us dirty immediately
transition(S_TIP_C, S_INVALID, c && p)
transition(S_TIP_C, S_BRANCH, c && p) // losing TIP only possible via probe
transition(S_TIP_C, S_BRANCH_C, c && p) // losing TIP only possible via probe
transition(S_TIP_C, S_TIP, c) // probed while MMIO read || clean release (optional)
transition(S_TIP_C, S_TIP_D, c && m) // direct dirty only via MMIO write
transition(S_TIP_C, S_TIP_CD, false) // going dirty means we must shoot down clients
transition(S_TIP_C, S_TRUNK_C, c) // acquire
transition(S_TIP_C, S_TRUNK_CD, false) // acquire does not make us immediately dirty
transition(S_TIP_D, S_INVALID, p)
transition(S_TIP_D, S_BRANCH, p) // losing D is only possible via probe
transition(S_TIP_D, S_BRANCH_C, p && c) // probed while acquire shared
transition(S_TIP_D, S_TIP, p) // probed while MMIO read || outer probe.toT (optional)
transition(S_TIP_D, S_TIP_C, false) // we would go S_TRUNK_C instead
transition(S_TIP_D, S_TIP_CD, false) // we would go S_TRUNK_CD instead
transition(S_TIP_D, S_TRUNK_C, p && c) // probed while acquired
transition(S_TIP_D, S_TRUNK_CD, c) // acquire
transition(S_TIP_CD, S_INVALID, c && p)
transition(S_TIP_CD, S_BRANCH, c && p) // losing D is only possible via probe
transition(S_TIP_CD, S_BRANCH_C, c && p) // losing D is only possible via probe
transition(S_TIP_CD, S_TIP, c && p) // probed while MMIO read || outer probe.toT (optional)
transition(S_TIP_CD, S_TIP_C, false) // we would go S_TRUNK_C instead
transition(S_TIP_CD, S_TIP_D, c) // MMIO write || clean release (optional)
transition(S_TIP_CD, S_TRUNK_C, c && p) // probed while acquire
transition(S_TIP_CD, S_TRUNK_CD, c) // acquire
transition(S_TRUNK_C, S_INVALID, c && p)
transition(S_TRUNK_C, S_BRANCH, c && p) // losing TIP only possible via probe
transition(S_TRUNK_C, S_BRANCH_C, c && p) // losing TIP only possible via probe
transition(S_TRUNK_C, S_TIP, c) // MMIO read || clean release (optional)
transition(S_TRUNK_C, S_TIP_C, c) // bounce shared
transition(S_TRUNK_C, S_TIP_D, c) // dirty release
transition(S_TRUNK_C, S_TIP_CD, c) // dirty bounce shared
transition(S_TRUNK_C, S_TRUNK_CD, c) // dirty bounce
transition(S_TRUNK_CD, S_INVALID, c && p)
transition(S_TRUNK_CD, S_BRANCH, c && p) // losing D only possible via probe
transition(S_TRUNK_CD, S_BRANCH_C, c && p) // losing D only possible via probe
transition(S_TRUNK_CD, S_TIP, c && p) // probed while MMIO read || outer probe.toT (optional)
transition(S_TRUNK_CD, S_TIP_C, false) // we would go S_TRUNK_C instead
transition(S_TRUNK_CD, S_TIP_D, c) // dirty release
transition(S_TRUNK_CD, S_TIP_CD, c) // bounce shared
transition(S_TRUNK_CD, S_TRUNK_C, c && p) // probed while acquire
}
// Handle response messages
val probe_bit = params.clientBit(io.sinkc.bits.source)
val last_probe = (probes_done | probe_bit) === (meta.clients & ~excluded_client)
val probe_toN = isToN(io.sinkc.bits.param)
if (!params.firstLevel) when (io.sinkc.valid) {
params.ccover( probe_toN && io.schedule.bits.b.bits.param === toB, "MSHR_PROBE_FULL", "Client downgraded to N when asked only to do B")
params.ccover(!probe_toN && io.schedule.bits.b.bits.param === toB, "MSHR_PROBE_HALF", "Client downgraded to B when asked only to do B")
// Caution: the probe matches us only in set.
// We would never allow an outer probe to nest until both w_[rp]probeack complete, so
// it is safe to just unguardedly update the probe FSM.
probes_done := probes_done | probe_bit
probes_toN := probes_toN | Mux(probe_toN, probe_bit, 0.U)
probes_noT := probes_noT || io.sinkc.bits.param =/= TtoT
w_rprobeackfirst := w_rprobeackfirst || last_probe
w_rprobeacklast := w_rprobeacklast || (last_probe && io.sinkc.bits.last)
w_pprobeackfirst := w_pprobeackfirst || last_probe
w_pprobeacklast := w_pprobeacklast || (last_probe && io.sinkc.bits.last)
// Allow wormhole routing from sinkC if the first request beat has offset 0
val set_pprobeack = last_probe && (io.sinkc.bits.last || request.offset === 0.U)
w_pprobeack := w_pprobeack || set_pprobeack
params.ccover(!set_pprobeack && w_rprobeackfirst, "MSHR_PROBE_SERIAL", "Sequential routing of probe response data")
params.ccover( set_pprobeack && w_rprobeackfirst, "MSHR_PROBE_WORMHOLE", "Wormhole routing of probe response data")
// However, meta-data updates need to be done more cautiously
when (meta.state =/= INVALID && io.sinkc.bits.tag === meta.tag && io.sinkc.bits.data) { meta.dirty := true.B } // !!!
}
when (io.sinkd.valid) {
when (io.sinkd.bits.opcode === Grant || io.sinkd.bits.opcode === GrantData) {
sink := io.sinkd.bits.sink
w_grantfirst := true.B
w_grantlast := io.sinkd.bits.last
// Record if we need to prevent taking ownership
bad_grant := io.sinkd.bits.denied
// Allow wormhole routing for requests whose first beat has offset 0
w_grant := request.offset === 0.U || io.sinkd.bits.last
params.ccover(io.sinkd.bits.opcode === GrantData && request.offset === 0.U, "MSHR_GRANT_WORMHOLE", "Wormhole routing of grant response data")
params.ccover(io.sinkd.bits.opcode === GrantData && request.offset =/= 0.U, "MSHR_GRANT_SERIAL", "Sequential routing of grant response data")
gotT := io.sinkd.bits.param === toT
}
.elsewhen (io.sinkd.bits.opcode === ReleaseAck) {
w_releaseack := true.B
}
}
when (io.sinke.valid) {
w_grantack := true.B
}
// Bootstrap new requests
val allocate_as_full = WireInit(new FullRequest(params), init = io.allocate.bits)
val new_meta = Mux(io.allocate.valid && io.allocate.bits.repeat, final_meta_writeback, io.directory.bits)
val new_request = Mux(io.allocate.valid, allocate_as_full, request)
val new_needT = needT(new_request.opcode, new_request.param)
val new_clientBit = params.clientBit(new_request.source)
val new_skipProbe = Mux(skipProbeN(new_request.opcode, params.cache.hintsSkipProbe), new_clientBit, 0.U)
val prior = cacheState(final_meta_writeback, true.B)
def bypass(from: CacheState, cover: Boolean)(implicit sourceInfo: SourceInfo) {
if (cover) {
params.ccover(prior === from.code, s"MSHR_${from}_BYPASS", s"State bypass transition from ${from} ${cfg}")
} else {
assert(!(prior === from.code), cf"State bypass from ${from} should be impossible ${cfg}")
}
}
when (io.allocate.valid && io.allocate.bits.repeat) {
bypass(S_INVALID, f || p) // Can lose permissions (probe/flush)
bypass(S_BRANCH, b) // MMIO read to read-only device
bypass(S_BRANCH_C, b && c) // you need children to become C
bypass(S_TIP, true) // MMIO read || clean release can lead to this state
bypass(S_TIP_C, c) // needs two clients || client + mmio || downgrading client
bypass(S_TIP_CD, c) // needs two clients || client + mmio || downgrading client
bypass(S_TIP_D, true) // MMIO write || dirty release lead here
bypass(S_TRUNK_C, c) // acquire for write
bypass(S_TRUNK_CD, c) // dirty release then reacquire
}
when (io.allocate.valid) {
assert (!request_valid || (no_wait && io.schedule.fire))
request_valid := true.B
request := io.allocate.bits
}
// Create execution plan
when (io.directory.valid || (io.allocate.valid && io.allocate.bits.repeat)) {
meta_valid := true.B
meta := new_meta
probes_done := 0.U
probes_toN := 0.U
probes_noT := false.B
gotT := false.B
bad_grant := false.B
// These should already be either true or turning true
// We clear them here explicitly to simplify the mux tree
s_rprobe := true.B
w_rprobeackfirst := true.B
w_rprobeacklast := true.B
s_release := true.B
w_releaseack := true.B
s_pprobe := true.B
s_acquire := true.B
s_flush := true.B
w_grantfirst := true.B
w_grantlast := true.B
w_grant := true.B
w_pprobeackfirst := true.B
w_pprobeacklast := true.B
w_pprobeack := true.B
s_probeack := true.B
s_grantack := true.B
s_execute := true.B
w_grantack := true.B
s_writeback := true.B
// For C channel requests (ie: Release[Data])
when (new_request.prio(2) && (!params.firstLevel).B) {
s_execute := false.B
// Do we need to go dirty?
when (new_request.opcode(0) && !new_meta.dirty) {
s_writeback := false.B
}
// Does our state change?
when (isToB(new_request.param) && new_meta.state === TRUNK) {
s_writeback := false.B
}
// Do our clients change?
when (isToN(new_request.param) && (new_meta.clients & new_clientBit) =/= 0.U) {
s_writeback := false.B
}
assert (new_meta.hit)
}
// For X channel requests (ie: flush)
.elsewhen (new_request.control && params.control.B) { // new_request.prio(0)
s_flush := false.B
// Do we need to actually do something?
when (new_meta.hit) {
s_release := false.B
w_releaseack := false.B
// Do we need to shoot-down inner caches?
when ((!params.firstLevel).B && (new_meta.clients =/= 0.U)) {
s_rprobe := false.B
w_rprobeackfirst := false.B
w_rprobeacklast := false.B
}
}
}
// For A channel requests
.otherwise { // new_request.prio(0) && !new_request.control
s_execute := false.B
// Do we need an eviction?
when (!new_meta.hit && new_meta.state =/= INVALID) {
s_release := false.B
w_releaseack := false.B
// Do we need to shoot-down inner caches?
when ((!params.firstLevel).B & (new_meta.clients =/= 0.U)) {
s_rprobe := false.B
w_rprobeackfirst := false.B
w_rprobeacklast := false.B
}
}
// Do we need an acquire?
when (!new_meta.hit || (new_meta.state === BRANCH && new_needT)) {
s_acquire := false.B
w_grantfirst := false.B
w_grantlast := false.B
w_grant := false.B
s_grantack := false.B
s_writeback := false.B
}
// Do we need a probe?
when ((!params.firstLevel).B && (new_meta.hit &&
(new_needT || new_meta.state === TRUNK) &&
(new_meta.clients & ~new_skipProbe) =/= 0.U)) {
s_pprobe := false.B
w_pprobeackfirst := false.B
w_pprobeacklast := false.B
w_pprobeack := false.B
s_writeback := false.B
}
// Do we need a grantack?
when (new_request.opcode === AcquireBlock || new_request.opcode === AcquirePerm) {
w_grantack := false.B
s_writeback := false.B
}
// Becomes dirty?
when (!new_request.opcode(2) && new_meta.hit && !new_meta.dirty) {
s_writeback := false.B
}
}
}
}
File Parameters.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.diplomacy
import chisel3._
import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor}
import freechips.rocketchip.util.ShiftQueue
/** Options for describing the attributes of memory regions */
object RegionType {
// Define the 'more relaxed than' ordering
val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS)
sealed trait T extends Ordered[T] {
def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this)
}
case object CACHED extends T // an intermediate agent may have cached a copy of the region for you
case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided
case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible
case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached
case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects
case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed
case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively
}
// A non-empty half-open range; [start, end)
case class IdRange(start: Int, end: Int) extends Ordered[IdRange]
{
require (start >= 0, s"Ids cannot be negative, but got: $start.")
require (start <= end, "Id ranges cannot be negative.")
def compare(x: IdRange) = {
val primary = (this.start - x.start).signum
val secondary = (x.end - this.end).signum
if (primary != 0) primary else secondary
}
def overlaps(x: IdRange) = start < x.end && x.start < end
def contains(x: IdRange) = start <= x.start && x.end <= end
def contains(x: Int) = start <= x && x < end
def contains(x: UInt) =
if (size == 0) {
false.B
} else if (size == 1) { // simple comparison
x === start.U
} else {
// find index of largest different bit
val largestDeltaBit = log2Floor(start ^ (end-1))
val smallestCommonBit = largestDeltaBit + 1 // may not exist in x
val uncommonMask = (1 << smallestCommonBit) - 1
val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0)
// the prefix must match exactly (note: may shift ALL bits away)
(x >> smallestCommonBit) === (start >> smallestCommonBit).U &&
// firrtl constant prop range analysis can eliminate these two:
(start & uncommonMask).U <= uncommonBits &&
uncommonBits <= ((end-1) & uncommonMask).U
}
def shift(x: Int) = IdRange(start+x, end+x)
def size = end - start
def isEmpty = end == start
def range = start until end
}
object IdRange
{
def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else {
val ranges = s.sorted
(ranges.tail zip ranges.init) find { case (a, b) => a overlaps b }
}
}
// An potentially empty inclusive range of 2-powers [min, max] (in bytes)
case class TransferSizes(min: Int, max: Int)
{
def this(x: Int) = this(x, x)
require (min <= max, s"Min transfer $min > max transfer $max")
require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)")
require (max == 0 || isPow2(max), s"TransferSizes must be a power of 2, got: $max")
require (min == 0 || isPow2(min), s"TransferSizes must be a power of 2, got: $min")
require (max == 0 || min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)")
def none = min == 0
def contains(x: Int) = isPow2(x) && min <= x && x <= max
def containsLg(x: Int) = contains(1 << x)
def containsLg(x: UInt) =
if (none) false.B
else if (min == max) { log2Ceil(min).U === x }
else { log2Ceil(min).U <= x && x <= log2Ceil(max).U }
def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max)
def intersect(x: TransferSizes) =
if (x.max < min || max < x.min) TransferSizes.none
else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max))
// Not a union, because the result may contain sizes contained by neither term
// NOT TO BE CONFUSED WITH COVERPOINTS
def mincover(x: TransferSizes) = {
if (none) {
x
} else if (x.none) {
this
} else {
TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max))
}
}
override def toString() = "TransferSizes[%d, %d]".format(min, max)
}
object TransferSizes {
def apply(x: Int) = new TransferSizes(x)
val none = new TransferSizes(0)
def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _)
def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _)
implicit def asBool(x: TransferSizes) = !x.none
}
// AddressSets specify the address space managed by the manager
// Base is the base address, and mask are the bits consumed by the manager
// e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff
// e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ...
case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet]
{
// Forbid misaligned base address (and empty sets)
require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}")
require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous
// We do allow negative mask (=> ignore all high bits)
def contains(x: BigInt) = ((x ^ base) & ~mask) == 0
def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S
// turn x into an address contained in this set
def legalize(x: UInt): UInt = base.U | (mask.U & x)
// overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1)
def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0
// contains iff bitwise: x.mask => mask && contains(x.base)
def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0
// The number of bytes to which the manager must be aligned
def alignment = ((mask + 1) & ~mask)
// Is this a contiguous memory range
def contiguous = alignment == mask+1
def finite = mask >= 0
def max = { require (finite, "Max cannot be calculated on infinite mask"); base | mask }
// Widen the match function to ignore all bits in imask
def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask)
// Return an AddressSet that only contains the addresses both sets contain
def intersect(x: AddressSet): Option[AddressSet] = {
if (!overlaps(x)) {
None
} else {
val r_mask = mask & x.mask
val r_base = base | x.base
Some(AddressSet(r_base, r_mask))
}
}
def subtract(x: AddressSet): Seq[AddressSet] = {
intersect(x) match {
case None => Seq(this)
case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit =>
val nmask = (mask & (bit-1)) | remove.mask
val nbase = (remove.base ^ bit) & ~nmask
AddressSet(nbase, nmask)
}
}
}
// AddressSets have one natural Ordering (the containment order, if contiguous)
def compare(x: AddressSet) = {
val primary = (this.base - x.base).signum // smallest address first
val secondary = (x.mask - this.mask).signum // largest mask first
if (primary != 0) primary else secondary
}
// We always want to see things in hex
override def toString() = {
if (mask >= 0) {
"AddressSet(0x%x, 0x%x)".format(base, mask)
} else {
"AddressSet(0x%x, ~0x%x)".format(base, ~mask)
}
}
def toRanges = {
require (finite, "Ranges cannot be calculated on infinite mask")
val size = alignment
val fragments = mask & ~(size-1)
val bits = bitIndexes(fragments)
(BigInt(0) until (BigInt(1) << bits.size)).map { i =>
val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) }
AddressRange(off, size)
}
}
}
object AddressSet
{
val everything = AddressSet(0, -1)
def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = {
if (size == 0) tail.reverse else {
val maxBaseAlignment = base & (-base) // 0 for infinite (LSB)
val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size
val step =
if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment)
maxSizeAlignment else maxBaseAlignment
misaligned(base+step, size-step, AddressSet(base, step-1) +: tail)
}
}
def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = {
// Pair terms up by ignoring 'bit'
seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) =>
if (seq.size == 1) {
seq.head // singleton -> unaffected
} else {
key.copy(mask = key.mask | bit) // pair - widen mask by bit
}
}.toList
}
def unify(seq: Seq[AddressSet]): Seq[AddressSet] = {
val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _)
AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted
}
def enumerateMask(mask: BigInt): Seq[BigInt] = {
def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] =
if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail)
helper(0, Nil)
}
def enumerateBits(mask: BigInt): Seq[BigInt] = {
def helper(x: BigInt): Seq[BigInt] = {
if (x == 0) {
Nil
} else {
val bit = x & (-x)
bit +: helper(x & ~bit)
}
}
helper(mask)
}
}
case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean)
{
require (depth >= 0, "Buffer depth must be >= 0")
def isDefined = depth > 0
def latency = if (isDefined && !flow) 1 else 0
def apply[T <: Data](x: DecoupledIO[T]) =
if (isDefined) Queue(x, depth, flow=flow, pipe=pipe)
else x
def irrevocable[T <: Data](x: ReadyValidIO[T]) =
if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe)
else x
def sq[T <: Data](x: DecoupledIO[T]) =
if (!isDefined) x else {
val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe))
sq.io.enq <> x
sq.io.deq
}
override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "")
}
object BufferParams
{
implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false)
val default = BufferParams(2)
val none = BufferParams(0)
val flow = BufferParams(1, true, false)
val pipe = BufferParams(1, false, true)
}
case class TriStateValue(value: Boolean, set: Boolean)
{
def update(orig: Boolean) = if (set) value else orig
}
object TriStateValue
{
implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true)
def unset = TriStateValue(false, false)
}
trait DirectedBuffers[T] {
def copyIn(x: BufferParams): T
def copyOut(x: BufferParams): T
def copyInOut(x: BufferParams): T
}
trait IdMapEntry {
def name: String
def from: IdRange
def to: IdRange
def isCache: Boolean
def requestFifo: Boolean
def maxTransactionsInFlight: Option[Int]
def pretty(fmt: String) =
if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5
fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "")
} else {
fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "")
}
}
abstract class IdMap[T <: IdMapEntry] {
protected val fmt: String
val mapping: Seq[T]
def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n")
}
| module MSHR_10( // @[MSHR.scala:84:7]
input clock, // @[MSHR.scala:84:7]
input reset, // @[MSHR.scala:84:7]
input io_allocate_valid, // @[MSHR.scala:86:14]
input io_allocate_bits_prio_1, // @[MSHR.scala:86:14]
input io_allocate_bits_prio_2, // @[MSHR.scala:86:14]
input io_allocate_bits_control, // @[MSHR.scala:86:14]
input [2:0] io_allocate_bits_opcode, // @[MSHR.scala:86:14]
input [2:0] io_allocate_bits_param, // @[MSHR.scala:86:14]
input [2:0] io_allocate_bits_size, // @[MSHR.scala:86:14]
input [6:0] io_allocate_bits_source, // @[MSHR.scala:86:14]
input [12:0] io_allocate_bits_tag, // @[MSHR.scala:86:14]
input [5:0] io_allocate_bits_offset, // @[MSHR.scala:86:14]
input [5:0] io_allocate_bits_put, // @[MSHR.scala:86:14]
input [9:0] io_allocate_bits_set, // @[MSHR.scala:86:14]
input io_allocate_bits_repeat, // @[MSHR.scala:86:14]
input io_directory_valid, // @[MSHR.scala:86:14]
input io_directory_bits_dirty, // @[MSHR.scala:86:14]
input [1:0] io_directory_bits_state, // @[MSHR.scala:86:14]
input [3:0] io_directory_bits_clients, // @[MSHR.scala:86:14]
input [12:0] io_directory_bits_tag, // @[MSHR.scala:86:14]
input io_directory_bits_hit, // @[MSHR.scala:86:14]
input [2:0] io_directory_bits_way, // @[MSHR.scala:86:14]
output io_status_valid, // @[MSHR.scala:86:14]
output [9:0] io_status_bits_set, // @[MSHR.scala:86:14]
output [12:0] io_status_bits_tag, // @[MSHR.scala:86:14]
output [2:0] io_status_bits_way, // @[MSHR.scala:86:14]
output io_status_bits_blockB, // @[MSHR.scala:86:14]
output io_status_bits_nestB, // @[MSHR.scala:86:14]
output io_status_bits_blockC, // @[MSHR.scala:86:14]
output io_status_bits_nestC, // @[MSHR.scala:86:14]
input io_schedule_ready, // @[MSHR.scala:86:14]
output io_schedule_valid, // @[MSHR.scala:86:14]
output io_schedule_bits_a_valid, // @[MSHR.scala:86:14]
output [12:0] io_schedule_bits_a_bits_tag, // @[MSHR.scala:86:14]
output [9:0] io_schedule_bits_a_bits_set, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_a_bits_param, // @[MSHR.scala:86:14]
output io_schedule_bits_a_bits_block, // @[MSHR.scala:86:14]
output io_schedule_bits_b_valid, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_b_bits_param, // @[MSHR.scala:86:14]
output [12:0] io_schedule_bits_b_bits_tag, // @[MSHR.scala:86:14]
output [9:0] io_schedule_bits_b_bits_set, // @[MSHR.scala:86:14]
output [3:0] io_schedule_bits_b_bits_clients, // @[MSHR.scala:86:14]
output io_schedule_bits_c_valid, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_c_bits_opcode, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_c_bits_param, // @[MSHR.scala:86:14]
output [12:0] io_schedule_bits_c_bits_tag, // @[MSHR.scala:86:14]
output [9:0] io_schedule_bits_c_bits_set, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_c_bits_way, // @[MSHR.scala:86:14]
output io_schedule_bits_c_bits_dirty, // @[MSHR.scala:86:14]
output io_schedule_bits_d_valid, // @[MSHR.scala:86:14]
output io_schedule_bits_d_bits_prio_1, // @[MSHR.scala:86:14]
output io_schedule_bits_d_bits_prio_2, // @[MSHR.scala:86:14]
output io_schedule_bits_d_bits_control, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_d_bits_opcode, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_d_bits_param, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_d_bits_size, // @[MSHR.scala:86:14]
output [6:0] io_schedule_bits_d_bits_source, // @[MSHR.scala:86:14]
output [12:0] io_schedule_bits_d_bits_tag, // @[MSHR.scala:86:14]
output [5:0] io_schedule_bits_d_bits_offset, // @[MSHR.scala:86:14]
output [5:0] io_schedule_bits_d_bits_put, // @[MSHR.scala:86:14]
output [9:0] io_schedule_bits_d_bits_set, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_d_bits_way, // @[MSHR.scala:86:14]
output io_schedule_bits_d_bits_bad, // @[MSHR.scala:86:14]
output io_schedule_bits_e_valid, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_e_bits_sink, // @[MSHR.scala:86:14]
output io_schedule_bits_x_valid, // @[MSHR.scala:86:14]
output io_schedule_bits_dir_valid, // @[MSHR.scala:86:14]
output [9:0] io_schedule_bits_dir_bits_set, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_dir_bits_way, // @[MSHR.scala:86:14]
output io_schedule_bits_dir_bits_data_dirty, // @[MSHR.scala:86:14]
output [1:0] io_schedule_bits_dir_bits_data_state, // @[MSHR.scala:86:14]
output [3:0] io_schedule_bits_dir_bits_data_clients, // @[MSHR.scala:86:14]
output [12:0] io_schedule_bits_dir_bits_data_tag, // @[MSHR.scala:86:14]
output io_schedule_bits_reload, // @[MSHR.scala:86:14]
input io_sinkc_valid, // @[MSHR.scala:86:14]
input io_sinkc_bits_last, // @[MSHR.scala:86:14]
input [9:0] io_sinkc_bits_set, // @[MSHR.scala:86:14]
input [12:0] io_sinkc_bits_tag, // @[MSHR.scala:86:14]
input [6:0] io_sinkc_bits_source, // @[MSHR.scala:86:14]
input [2:0] io_sinkc_bits_param, // @[MSHR.scala:86:14]
input io_sinkc_bits_data, // @[MSHR.scala:86:14]
input io_sinkd_valid, // @[MSHR.scala:86:14]
input io_sinkd_bits_last, // @[MSHR.scala:86:14]
input [2:0] io_sinkd_bits_opcode, // @[MSHR.scala:86:14]
input [2:0] io_sinkd_bits_param, // @[MSHR.scala:86:14]
input [3:0] io_sinkd_bits_source, // @[MSHR.scala:86:14]
input [2:0] io_sinkd_bits_sink, // @[MSHR.scala:86:14]
input io_sinkd_bits_denied, // @[MSHR.scala:86:14]
input io_sinke_valid, // @[MSHR.scala:86:14]
input [3:0] io_sinke_bits_sink, // @[MSHR.scala:86:14]
input [9:0] io_nestedwb_set, // @[MSHR.scala:86:14]
input [12:0] io_nestedwb_tag, // @[MSHR.scala:86:14]
input io_nestedwb_b_toN, // @[MSHR.scala:86:14]
input io_nestedwb_b_toB, // @[MSHR.scala:86:14]
input io_nestedwb_b_clr_dirty, // @[MSHR.scala:86:14]
input io_nestedwb_c_set_dirty // @[MSHR.scala:86:14]
);
wire [12:0] final_meta_writeback_tag; // @[MSHR.scala:215:38]
wire [3:0] final_meta_writeback_clients; // @[MSHR.scala:215:38]
wire [1:0] final_meta_writeback_state; // @[MSHR.scala:215:38]
wire final_meta_writeback_dirty; // @[MSHR.scala:215:38]
wire io_allocate_valid_0 = io_allocate_valid; // @[MSHR.scala:84:7]
wire io_allocate_bits_prio_1_0 = io_allocate_bits_prio_1; // @[MSHR.scala:84:7]
wire io_allocate_bits_prio_2_0 = io_allocate_bits_prio_2; // @[MSHR.scala:84:7]
wire io_allocate_bits_control_0 = io_allocate_bits_control; // @[MSHR.scala:84:7]
wire [2:0] io_allocate_bits_opcode_0 = io_allocate_bits_opcode; // @[MSHR.scala:84:7]
wire [2:0] io_allocate_bits_param_0 = io_allocate_bits_param; // @[MSHR.scala:84:7]
wire [2:0] io_allocate_bits_size_0 = io_allocate_bits_size; // @[MSHR.scala:84:7]
wire [6:0] io_allocate_bits_source_0 = io_allocate_bits_source; // @[MSHR.scala:84:7]
wire [12:0] io_allocate_bits_tag_0 = io_allocate_bits_tag; // @[MSHR.scala:84:7]
wire [5:0] io_allocate_bits_offset_0 = io_allocate_bits_offset; // @[MSHR.scala:84:7]
wire [5:0] io_allocate_bits_put_0 = io_allocate_bits_put; // @[MSHR.scala:84:7]
wire [9:0] io_allocate_bits_set_0 = io_allocate_bits_set; // @[MSHR.scala:84:7]
wire io_allocate_bits_repeat_0 = io_allocate_bits_repeat; // @[MSHR.scala:84:7]
wire io_directory_valid_0 = io_directory_valid; // @[MSHR.scala:84:7]
wire io_directory_bits_dirty_0 = io_directory_bits_dirty; // @[MSHR.scala:84:7]
wire [1:0] io_directory_bits_state_0 = io_directory_bits_state; // @[MSHR.scala:84:7]
wire [3:0] io_directory_bits_clients_0 = io_directory_bits_clients; // @[MSHR.scala:84:7]
wire [12:0] io_directory_bits_tag_0 = io_directory_bits_tag; // @[MSHR.scala:84:7]
wire io_directory_bits_hit_0 = io_directory_bits_hit; // @[MSHR.scala:84:7]
wire [2:0] io_directory_bits_way_0 = io_directory_bits_way; // @[MSHR.scala:84:7]
wire io_schedule_ready_0 = io_schedule_ready; // @[MSHR.scala:84:7]
wire io_sinkc_valid_0 = io_sinkc_valid; // @[MSHR.scala:84:7]
wire io_sinkc_bits_last_0 = io_sinkc_bits_last; // @[MSHR.scala:84:7]
wire [9:0] io_sinkc_bits_set_0 = io_sinkc_bits_set; // @[MSHR.scala:84:7]
wire [12:0] io_sinkc_bits_tag_0 = io_sinkc_bits_tag; // @[MSHR.scala:84:7]
wire [6:0] io_sinkc_bits_source_0 = io_sinkc_bits_source; // @[MSHR.scala:84:7]
wire [2:0] io_sinkc_bits_param_0 = io_sinkc_bits_param; // @[MSHR.scala:84:7]
wire io_sinkc_bits_data_0 = io_sinkc_bits_data; // @[MSHR.scala:84:7]
wire io_sinkd_valid_0 = io_sinkd_valid; // @[MSHR.scala:84:7]
wire io_sinkd_bits_last_0 = io_sinkd_bits_last; // @[MSHR.scala:84:7]
wire [2:0] io_sinkd_bits_opcode_0 = io_sinkd_bits_opcode; // @[MSHR.scala:84:7]
wire [2:0] io_sinkd_bits_param_0 = io_sinkd_bits_param; // @[MSHR.scala:84:7]
wire [3:0] io_sinkd_bits_source_0 = io_sinkd_bits_source; // @[MSHR.scala:84:7]
wire [2:0] io_sinkd_bits_sink_0 = io_sinkd_bits_sink; // @[MSHR.scala:84:7]
wire io_sinkd_bits_denied_0 = io_sinkd_bits_denied; // @[MSHR.scala:84:7]
wire io_sinke_valid_0 = io_sinke_valid; // @[MSHR.scala:84:7]
wire [3:0] io_sinke_bits_sink_0 = io_sinke_bits_sink; // @[MSHR.scala:84:7]
wire [9:0] io_nestedwb_set_0 = io_nestedwb_set; // @[MSHR.scala:84:7]
wire [12:0] io_nestedwb_tag_0 = io_nestedwb_tag; // @[MSHR.scala:84:7]
wire io_nestedwb_b_toN_0 = io_nestedwb_b_toN; // @[MSHR.scala:84:7]
wire io_nestedwb_b_toB_0 = io_nestedwb_b_toB; // @[MSHR.scala:84:7]
wire io_nestedwb_b_clr_dirty_0 = io_nestedwb_b_clr_dirty; // @[MSHR.scala:84:7]
wire io_nestedwb_c_set_dirty_0 = io_nestedwb_c_set_dirty; // @[MSHR.scala:84:7]
wire io_allocate_bits_prio_0 = 1'h0; // @[MSHR.scala:84:7]
wire io_schedule_bits_d_bits_prio_0 = 1'h0; // @[MSHR.scala:84:7]
wire io_schedule_bits_x_bits_fail = 1'h0; // @[MSHR.scala:84:7]
wire _io_schedule_bits_c_valid_T_2 = 1'h0; // @[MSHR.scala:186:68]
wire _io_schedule_bits_c_valid_T_3 = 1'h0; // @[MSHR.scala:186:80]
wire invalid_dirty = 1'h0; // @[MSHR.scala:268:21]
wire _excluded_client_T = 1'h0; // @[MSHR.scala:279:38]
wire _excluded_client_T_7 = 1'h0; // @[Parameters.scala:279:137]
wire _excluded_client_T_9 = 1'h0; // @[MSHR.scala:279:57]
wire _after_T_4 = 1'h0; // @[MSHR.scala:323:11]
wire allocate_as_full_prio_0 = 1'h0; // @[MSHR.scala:504:34]
wire new_request_prio_0 = 1'h0; // @[MSHR.scala:506:24]
wire _new_skipProbe_T_6 = 1'h0; // @[Parameters.scala:279:137]
wire _prior_T_4 = 1'h0; // @[MSHR.scala:323:11]
wire [3:0] _io_schedule_bits_b_bits_clients_T = 4'hF; // @[MSHR.scala:289:53]
wire [3:0] _last_probe_T_1 = 4'hF; // @[MSHR.scala:459:66]
wire [3:0] io_schedule_bits_a_bits_source = 4'h0; // @[MSHR.scala:84:7]
wire [3:0] io_schedule_bits_c_bits_source = 4'h0; // @[MSHR.scala:84:7]
wire [3:0] io_schedule_bits_d_bits_sink = 4'h0; // @[MSHR.scala:84:7]
wire [3:0] invalid_clients = 4'h0; // @[MSHR.scala:268:21]
wire [3:0] excluded_client = 4'h0; // @[MSHR.scala:279:28]
wire _req_clientBit_T_4 = 1'h1; // @[Parameters.scala:56:32]
wire _req_clientBit_T_10 = 1'h1; // @[Parameters.scala:56:32]
wire _probe_bit_T_4 = 1'h1; // @[Parameters.scala:56:32]
wire _probe_bit_T_10 = 1'h1; // @[Parameters.scala:56:32]
wire _new_clientBit_T_4 = 1'h1; // @[Parameters.scala:56:32]
wire _new_clientBit_T_10 = 1'h1; // @[Parameters.scala:56:32]
wire [12:0] invalid_tag = 13'h0; // @[MSHR.scala:268:21]
wire [1:0] invalid_state = 2'h0; // @[MSHR.scala:268:21]
wire [1:0] _final_meta_writeback_state_T_11 = 2'h1; // @[MSHR.scala:240:70]
wire allocate_as_full_prio_1 = io_allocate_bits_prio_1_0; // @[MSHR.scala:84:7, :504:34]
wire allocate_as_full_prio_2 = io_allocate_bits_prio_2_0; // @[MSHR.scala:84:7, :504:34]
wire allocate_as_full_control = io_allocate_bits_control_0; // @[MSHR.scala:84:7, :504:34]
wire [2:0] allocate_as_full_opcode = io_allocate_bits_opcode_0; // @[MSHR.scala:84:7, :504:34]
wire [2:0] allocate_as_full_param = io_allocate_bits_param_0; // @[MSHR.scala:84:7, :504:34]
wire [2:0] allocate_as_full_size = io_allocate_bits_size_0; // @[MSHR.scala:84:7, :504:34]
wire [6:0] allocate_as_full_source = io_allocate_bits_source_0; // @[MSHR.scala:84:7, :504:34]
wire [12:0] allocate_as_full_tag = io_allocate_bits_tag_0; // @[MSHR.scala:84:7, :504:34]
wire [5:0] allocate_as_full_offset = io_allocate_bits_offset_0; // @[MSHR.scala:84:7, :504:34]
wire [5:0] allocate_as_full_put = io_allocate_bits_put_0; // @[MSHR.scala:84:7, :504:34]
wire [9:0] allocate_as_full_set = io_allocate_bits_set_0; // @[MSHR.scala:84:7, :504:34]
wire _io_status_bits_blockB_T_8; // @[MSHR.scala:168:40]
wire _io_status_bits_nestB_T_4; // @[MSHR.scala:169:93]
wire _io_status_bits_blockC_T; // @[MSHR.scala:172:28]
wire _io_status_bits_nestC_T_5; // @[MSHR.scala:173:39]
wire _io_schedule_valid_T_5; // @[MSHR.scala:193:105]
wire _io_schedule_bits_a_valid_T_2; // @[MSHR.scala:184:55]
wire _io_schedule_bits_a_bits_block_T_5; // @[MSHR.scala:283:91]
wire _io_schedule_bits_b_valid_T_2; // @[MSHR.scala:185:41]
wire [2:0] _io_schedule_bits_b_bits_param_T_3; // @[MSHR.scala:286:41]
wire [12:0] _io_schedule_bits_b_bits_tag_T_1; // @[MSHR.scala:287:41]
wire [3:0] _io_schedule_bits_b_bits_clients_T_1; // @[MSHR.scala:289:51]
wire _io_schedule_bits_c_valid_T_4; // @[MSHR.scala:186:64]
wire [2:0] _io_schedule_bits_c_bits_opcode_T; // @[MSHR.scala:290:41]
wire [2:0] _io_schedule_bits_c_bits_param_T_1; // @[MSHR.scala:291:41]
wire _io_schedule_bits_d_valid_T_2; // @[MSHR.scala:187:57]
wire [2:0] _io_schedule_bits_d_bits_param_T_9; // @[MSHR.scala:298:41]
wire _io_schedule_bits_e_valid_T_1; // @[MSHR.scala:188:43]
wire _io_schedule_bits_x_valid_T_1; // @[MSHR.scala:189:40]
wire _io_schedule_bits_dir_valid_T_4; // @[MSHR.scala:190:66]
wire _io_schedule_bits_dir_bits_data_T_1_dirty; // @[MSHR.scala:310:41]
wire [1:0] _io_schedule_bits_dir_bits_data_T_1_state; // @[MSHR.scala:310:41]
wire [3:0] _io_schedule_bits_dir_bits_data_T_1_clients; // @[MSHR.scala:310:41]
wire [12:0] _io_schedule_bits_dir_bits_data_T_1_tag; // @[MSHR.scala:310:41]
wire no_wait; // @[MSHR.scala:183:83]
wire [6:0] _probe_bit_uncommonBits_T = io_sinkc_bits_source_0; // @[Parameters.scala:52:29]
wire [6:0] _probe_bit_uncommonBits_T_1 = io_sinkc_bits_source_0; // @[Parameters.scala:52:29]
wire [9:0] io_status_bits_set_0; // @[MSHR.scala:84:7]
wire [12:0] io_status_bits_tag_0; // @[MSHR.scala:84:7]
wire [2:0] io_status_bits_way_0; // @[MSHR.scala:84:7]
wire io_status_bits_blockB_0; // @[MSHR.scala:84:7]
wire io_status_bits_nestB_0; // @[MSHR.scala:84:7]
wire io_status_bits_blockC_0; // @[MSHR.scala:84:7]
wire io_status_bits_nestC_0; // @[MSHR.scala:84:7]
wire io_status_valid_0; // @[MSHR.scala:84:7]
wire [12:0] io_schedule_bits_a_bits_tag_0; // @[MSHR.scala:84:7]
wire [9:0] io_schedule_bits_a_bits_set_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_a_bits_param_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_a_bits_block_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_a_valid_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_b_bits_param_0; // @[MSHR.scala:84:7]
wire [12:0] io_schedule_bits_b_bits_tag_0; // @[MSHR.scala:84:7]
wire [9:0] io_schedule_bits_b_bits_set_0; // @[MSHR.scala:84:7]
wire [3:0] io_schedule_bits_b_bits_clients_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_b_valid_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_c_bits_opcode_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_c_bits_param_0; // @[MSHR.scala:84:7]
wire [12:0] io_schedule_bits_c_bits_tag_0; // @[MSHR.scala:84:7]
wire [9:0] io_schedule_bits_c_bits_set_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_c_bits_way_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_c_bits_dirty_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_c_valid_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_d_bits_prio_1_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_d_bits_prio_2_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_d_bits_control_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_d_bits_opcode_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_d_bits_param_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_d_bits_size_0; // @[MSHR.scala:84:7]
wire [6:0] io_schedule_bits_d_bits_source_0; // @[MSHR.scala:84:7]
wire [12:0] io_schedule_bits_d_bits_tag_0; // @[MSHR.scala:84:7]
wire [5:0] io_schedule_bits_d_bits_offset_0; // @[MSHR.scala:84:7]
wire [5:0] io_schedule_bits_d_bits_put_0; // @[MSHR.scala:84:7]
wire [9:0] io_schedule_bits_d_bits_set_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_d_bits_way_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_d_bits_bad_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_d_valid_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_e_bits_sink_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_e_valid_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_x_valid_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_dir_bits_data_dirty_0; // @[MSHR.scala:84:7]
wire [1:0] io_schedule_bits_dir_bits_data_state_0; // @[MSHR.scala:84:7]
wire [3:0] io_schedule_bits_dir_bits_data_clients_0; // @[MSHR.scala:84:7]
wire [12:0] io_schedule_bits_dir_bits_data_tag_0; // @[MSHR.scala:84:7]
wire [9:0] io_schedule_bits_dir_bits_set_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_dir_bits_way_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_dir_valid_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_reload_0; // @[MSHR.scala:84:7]
wire io_schedule_valid_0; // @[MSHR.scala:84:7]
reg request_valid; // @[MSHR.scala:97:30]
assign io_status_valid_0 = request_valid; // @[MSHR.scala:84:7, :97:30]
reg request_prio_1; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_prio_1_0 = request_prio_1; // @[MSHR.scala:84:7, :98:20]
reg request_prio_2; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_prio_2_0 = request_prio_2; // @[MSHR.scala:84:7, :98:20]
reg request_control; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_control_0 = request_control; // @[MSHR.scala:84:7, :98:20]
reg [2:0] request_opcode; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_opcode_0 = request_opcode; // @[MSHR.scala:84:7, :98:20]
reg [2:0] request_param; // @[MSHR.scala:98:20]
reg [2:0] request_size; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_size_0 = request_size; // @[MSHR.scala:84:7, :98:20]
reg [6:0] request_source; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_source_0 = request_source; // @[MSHR.scala:84:7, :98:20]
wire [6:0] _req_clientBit_uncommonBits_T = request_source; // @[Parameters.scala:52:29]
wire [6:0] _req_clientBit_uncommonBits_T_1 = request_source; // @[Parameters.scala:52:29]
reg [12:0] request_tag; // @[MSHR.scala:98:20]
assign io_status_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20]
assign io_schedule_bits_a_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20]
assign io_schedule_bits_d_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20]
reg [5:0] request_offset; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_offset_0 = request_offset; // @[MSHR.scala:84:7, :98:20]
reg [5:0] request_put; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_put_0 = request_put; // @[MSHR.scala:84:7, :98:20]
reg [9:0] request_set; // @[MSHR.scala:98:20]
assign io_status_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20]
assign io_schedule_bits_a_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20]
assign io_schedule_bits_b_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20]
assign io_schedule_bits_c_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20]
assign io_schedule_bits_d_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20]
assign io_schedule_bits_dir_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20]
reg meta_valid; // @[MSHR.scala:99:27]
reg meta_dirty; // @[MSHR.scala:100:17]
assign io_schedule_bits_c_bits_dirty_0 = meta_dirty; // @[MSHR.scala:84:7, :100:17]
reg [1:0] meta_state; // @[MSHR.scala:100:17]
reg [3:0] meta_clients; // @[MSHR.scala:100:17]
assign _io_schedule_bits_b_bits_clients_T_1 = meta_clients; // @[MSHR.scala:100:17, :289:51]
wire [3:0] _last_probe_T_2 = meta_clients; // @[MSHR.scala:100:17, :459:64]
reg [12:0] meta_tag; // @[MSHR.scala:100:17]
assign io_schedule_bits_c_bits_tag_0 = meta_tag; // @[MSHR.scala:84:7, :100:17]
reg meta_hit; // @[MSHR.scala:100:17]
reg [2:0] meta_way; // @[MSHR.scala:100:17]
assign io_status_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17]
assign io_schedule_bits_c_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17]
assign io_schedule_bits_d_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17]
assign io_schedule_bits_dir_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17]
wire [2:0] final_meta_writeback_way = meta_way; // @[MSHR.scala:100:17, :215:38]
reg s_rprobe; // @[MSHR.scala:121:33]
reg w_rprobeackfirst; // @[MSHR.scala:122:33]
reg w_rprobeacklast; // @[MSHR.scala:123:33]
reg s_release; // @[MSHR.scala:124:33]
reg w_releaseack; // @[MSHR.scala:125:33]
reg s_pprobe; // @[MSHR.scala:126:33]
reg s_acquire; // @[MSHR.scala:127:33]
reg s_flush; // @[MSHR.scala:128:33]
reg w_grantfirst; // @[MSHR.scala:129:33]
reg w_grantlast; // @[MSHR.scala:130:33]
reg w_grant; // @[MSHR.scala:131:33]
reg w_pprobeackfirst; // @[MSHR.scala:132:33]
reg w_pprobeacklast; // @[MSHR.scala:133:33]
reg w_pprobeack; // @[MSHR.scala:134:33]
reg s_grantack; // @[MSHR.scala:136:33]
reg s_execute; // @[MSHR.scala:137:33]
reg w_grantack; // @[MSHR.scala:138:33]
reg s_writeback; // @[MSHR.scala:139:33]
reg [2:0] sink; // @[MSHR.scala:147:17]
assign io_schedule_bits_e_bits_sink_0 = sink; // @[MSHR.scala:84:7, :147:17]
reg gotT; // @[MSHR.scala:148:17]
reg bad_grant; // @[MSHR.scala:149:22]
assign io_schedule_bits_d_bits_bad_0 = bad_grant; // @[MSHR.scala:84:7, :149:22]
reg [3:0] probes_done; // @[MSHR.scala:150:24]
reg [3:0] probes_toN; // @[MSHR.scala:151:23]
reg probes_noT; // @[MSHR.scala:152:23]
wire _io_status_bits_blockB_T = ~meta_valid; // @[MSHR.scala:99:27, :168:28]
wire _io_status_bits_blockB_T_1 = ~w_releaseack; // @[MSHR.scala:125:33, :168:45]
wire _io_status_bits_blockB_T_2 = ~w_rprobeacklast; // @[MSHR.scala:123:33, :168:62]
wire _io_status_bits_blockB_T_3 = _io_status_bits_blockB_T_1 | _io_status_bits_blockB_T_2; // @[MSHR.scala:168:{45,59,62}]
wire _io_status_bits_blockB_T_4 = ~w_pprobeacklast; // @[MSHR.scala:133:33, :168:82]
wire _io_status_bits_blockB_T_5 = _io_status_bits_blockB_T_3 | _io_status_bits_blockB_T_4; // @[MSHR.scala:168:{59,79,82}]
wire _io_status_bits_blockB_T_6 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103]
wire _io_status_bits_blockB_T_7 = _io_status_bits_blockB_T_5 & _io_status_bits_blockB_T_6; // @[MSHR.scala:168:{79,100,103}]
assign _io_status_bits_blockB_T_8 = _io_status_bits_blockB_T | _io_status_bits_blockB_T_7; // @[MSHR.scala:168:{28,40,100}]
assign io_status_bits_blockB_0 = _io_status_bits_blockB_T_8; // @[MSHR.scala:84:7, :168:40]
wire _io_status_bits_nestB_T = meta_valid & w_releaseack; // @[MSHR.scala:99:27, :125:33, :169:39]
wire _io_status_bits_nestB_T_1 = _io_status_bits_nestB_T & w_rprobeacklast; // @[MSHR.scala:123:33, :169:{39,55}]
wire _io_status_bits_nestB_T_2 = _io_status_bits_nestB_T_1 & w_pprobeacklast; // @[MSHR.scala:133:33, :169:{55,74}]
wire _io_status_bits_nestB_T_3 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103, :169:96]
assign _io_status_bits_nestB_T_4 = _io_status_bits_nestB_T_2 & _io_status_bits_nestB_T_3; // @[MSHR.scala:169:{74,93,96}]
assign io_status_bits_nestB_0 = _io_status_bits_nestB_T_4; // @[MSHR.scala:84:7, :169:93]
assign _io_status_bits_blockC_T = ~meta_valid; // @[MSHR.scala:99:27, :168:28, :172:28]
assign io_status_bits_blockC_0 = _io_status_bits_blockC_T; // @[MSHR.scala:84:7, :172:28]
wire _io_status_bits_nestC_T = ~w_rprobeackfirst; // @[MSHR.scala:122:33, :173:43]
wire _io_status_bits_nestC_T_1 = ~w_pprobeackfirst; // @[MSHR.scala:132:33, :173:64]
wire _io_status_bits_nestC_T_2 = _io_status_bits_nestC_T | _io_status_bits_nestC_T_1; // @[MSHR.scala:173:{43,61,64}]
wire _io_status_bits_nestC_T_3 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103, :173:85]
wire _io_status_bits_nestC_T_4 = _io_status_bits_nestC_T_2 | _io_status_bits_nestC_T_3; // @[MSHR.scala:173:{61,82,85}]
assign _io_status_bits_nestC_T_5 = meta_valid & _io_status_bits_nestC_T_4; // @[MSHR.scala:99:27, :173:{39,82}]
assign io_status_bits_nestC_0 = _io_status_bits_nestC_T_5; // @[MSHR.scala:84:7, :173:39]
wire _no_wait_T = w_rprobeacklast & w_releaseack; // @[MSHR.scala:123:33, :125:33, :183:33]
wire _no_wait_T_1 = _no_wait_T & w_grantlast; // @[MSHR.scala:130:33, :183:{33,49}]
wire _no_wait_T_2 = _no_wait_T_1 & w_pprobeacklast; // @[MSHR.scala:133:33, :183:{49,64}]
assign no_wait = _no_wait_T_2 & w_grantack; // @[MSHR.scala:138:33, :183:{64,83}]
assign io_schedule_bits_reload_0 = no_wait; // @[MSHR.scala:84:7, :183:83]
wire _io_schedule_bits_a_valid_T = ~s_acquire; // @[MSHR.scala:127:33, :184:31]
wire _io_schedule_bits_a_valid_T_1 = _io_schedule_bits_a_valid_T & s_release; // @[MSHR.scala:124:33, :184:{31,42}]
assign _io_schedule_bits_a_valid_T_2 = _io_schedule_bits_a_valid_T_1 & s_pprobe; // @[MSHR.scala:126:33, :184:{42,55}]
assign io_schedule_bits_a_valid_0 = _io_schedule_bits_a_valid_T_2; // @[MSHR.scala:84:7, :184:55]
wire _io_schedule_bits_b_valid_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31]
wire _io_schedule_bits_b_valid_T_1 = ~s_pprobe; // @[MSHR.scala:126:33, :185:44]
assign _io_schedule_bits_b_valid_T_2 = _io_schedule_bits_b_valid_T | _io_schedule_bits_b_valid_T_1; // @[MSHR.scala:185:{31,41,44}]
assign io_schedule_bits_b_valid_0 = _io_schedule_bits_b_valid_T_2; // @[MSHR.scala:84:7, :185:41]
wire _io_schedule_bits_c_valid_T = ~s_release; // @[MSHR.scala:124:33, :186:32]
wire _io_schedule_bits_c_valid_T_1 = _io_schedule_bits_c_valid_T & w_rprobeackfirst; // @[MSHR.scala:122:33, :186:{32,43}]
assign _io_schedule_bits_c_valid_T_4 = _io_schedule_bits_c_valid_T_1; // @[MSHR.scala:186:{43,64}]
assign io_schedule_bits_c_valid_0 = _io_schedule_bits_c_valid_T_4; // @[MSHR.scala:84:7, :186:64]
wire _io_schedule_bits_d_valid_T = ~s_execute; // @[MSHR.scala:137:33, :187:31]
wire _io_schedule_bits_d_valid_T_1 = _io_schedule_bits_d_valid_T & w_pprobeack; // @[MSHR.scala:134:33, :187:{31,42}]
assign _io_schedule_bits_d_valid_T_2 = _io_schedule_bits_d_valid_T_1 & w_grant; // @[MSHR.scala:131:33, :187:{42,57}]
assign io_schedule_bits_d_valid_0 = _io_schedule_bits_d_valid_T_2; // @[MSHR.scala:84:7, :187:57]
wire _io_schedule_bits_e_valid_T = ~s_grantack; // @[MSHR.scala:136:33, :188:31]
assign _io_schedule_bits_e_valid_T_1 = _io_schedule_bits_e_valid_T & w_grantfirst; // @[MSHR.scala:129:33, :188:{31,43}]
assign io_schedule_bits_e_valid_0 = _io_schedule_bits_e_valid_T_1; // @[MSHR.scala:84:7, :188:43]
wire _io_schedule_bits_x_valid_T = ~s_flush; // @[MSHR.scala:128:33, :189:31]
assign _io_schedule_bits_x_valid_T_1 = _io_schedule_bits_x_valid_T & w_releaseack; // @[MSHR.scala:125:33, :189:{31,40}]
assign io_schedule_bits_x_valid_0 = _io_schedule_bits_x_valid_T_1; // @[MSHR.scala:84:7, :189:40]
wire _io_schedule_bits_dir_valid_T = ~s_release; // @[MSHR.scala:124:33, :186:32, :190:34]
wire _io_schedule_bits_dir_valid_T_1 = _io_schedule_bits_dir_valid_T & w_rprobeackfirst; // @[MSHR.scala:122:33, :190:{34,45}]
wire _io_schedule_bits_dir_valid_T_2 = ~s_writeback; // @[MSHR.scala:139:33, :190:70]
wire _io_schedule_bits_dir_valid_T_3 = _io_schedule_bits_dir_valid_T_2 & no_wait; // @[MSHR.scala:183:83, :190:{70,83}]
assign _io_schedule_bits_dir_valid_T_4 = _io_schedule_bits_dir_valid_T_1 | _io_schedule_bits_dir_valid_T_3; // @[MSHR.scala:190:{45,66,83}]
assign io_schedule_bits_dir_valid_0 = _io_schedule_bits_dir_valid_T_4; // @[MSHR.scala:84:7, :190:66]
wire _io_schedule_valid_T = io_schedule_bits_a_valid_0 | io_schedule_bits_b_valid_0; // @[MSHR.scala:84:7, :192:49]
wire _io_schedule_valid_T_1 = _io_schedule_valid_T | io_schedule_bits_c_valid_0; // @[MSHR.scala:84:7, :192:{49,77}]
wire _io_schedule_valid_T_2 = _io_schedule_valid_T_1 | io_schedule_bits_d_valid_0; // @[MSHR.scala:84:7, :192:{77,105}]
wire _io_schedule_valid_T_3 = _io_schedule_valid_T_2 | io_schedule_bits_e_valid_0; // @[MSHR.scala:84:7, :192:105, :193:49]
wire _io_schedule_valid_T_4 = _io_schedule_valid_T_3 | io_schedule_bits_x_valid_0; // @[MSHR.scala:84:7, :193:{49,77}]
assign _io_schedule_valid_T_5 = _io_schedule_valid_T_4 | io_schedule_bits_dir_valid_0; // @[MSHR.scala:84:7, :193:{77,105}]
assign io_schedule_valid_0 = _io_schedule_valid_T_5; // @[MSHR.scala:84:7, :193:105]
wire _io_schedule_bits_dir_bits_data_WIRE_dirty = final_meta_writeback_dirty; // @[MSHR.scala:215:38, :310:71]
wire [1:0] _io_schedule_bits_dir_bits_data_WIRE_state = final_meta_writeback_state; // @[MSHR.scala:215:38, :310:71]
wire [3:0] _io_schedule_bits_dir_bits_data_WIRE_clients = final_meta_writeback_clients; // @[MSHR.scala:215:38, :310:71]
wire [12:0] _io_schedule_bits_dir_bits_data_WIRE_tag = final_meta_writeback_tag; // @[MSHR.scala:215:38, :310:71]
wire final_meta_writeback_hit; // @[MSHR.scala:215:38]
wire _req_clientBit_T = request_source == 7'h44; // @[Parameters.scala:46:9]
wire _req_clientBit_T_1 = request_source == 7'h40; // @[Parameters.scala:46:9]
wire [2:0] req_clientBit_uncommonBits = _req_clientBit_uncommonBits_T[2:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] _req_clientBit_T_2 = request_source[6:3]; // @[Parameters.scala:54:10]
wire [3:0] _req_clientBit_T_8 = request_source[6:3]; // @[Parameters.scala:54:10]
wire _req_clientBit_T_3 = _req_clientBit_T_2 == 4'h6; // @[Parameters.scala:54:{10,32}]
wire _req_clientBit_T_5 = _req_clientBit_T_3; // @[Parameters.scala:54:{32,67}]
wire _req_clientBit_T_6 = req_clientBit_uncommonBits < 3'h5; // @[Parameters.scala:52:56, :57:20]
wire _req_clientBit_T_7 = _req_clientBit_T_5 & _req_clientBit_T_6; // @[Parameters.scala:54:67, :56:48, :57:20]
wire [2:0] req_clientBit_uncommonBits_1 = _req_clientBit_uncommonBits_T_1[2:0]; // @[Parameters.scala:52:{29,56}]
wire _req_clientBit_T_9 = _req_clientBit_T_8 == 4'h4; // @[Parameters.scala:54:{10,32}]
wire _req_clientBit_T_11 = _req_clientBit_T_9; // @[Parameters.scala:54:{32,67}]
wire _req_clientBit_T_12 = req_clientBit_uncommonBits_1 < 3'h5; // @[Parameters.scala:52:56, :57:20]
wire _req_clientBit_T_13 = _req_clientBit_T_11 & _req_clientBit_T_12; // @[Parameters.scala:54:67, :56:48, :57:20]
wire [1:0] req_clientBit_lo = {_req_clientBit_T_1, _req_clientBit_T}; // @[Parameters.scala:46:9]
wire [1:0] req_clientBit_hi = {_req_clientBit_T_13, _req_clientBit_T_7}; // @[Parameters.scala:56:48]
wire [3:0] req_clientBit = {req_clientBit_hi, req_clientBit_lo}; // @[Parameters.scala:201:10]
wire _req_needT_T = request_opcode[2]; // @[Parameters.scala:269:12]
wire _final_meta_writeback_dirty_T_3 = request_opcode[2]; // @[Parameters.scala:269:12]
wire _req_needT_T_1 = ~_req_needT_T; // @[Parameters.scala:269:{5,12}]
wire _GEN = request_opcode == 3'h5; // @[Parameters.scala:270:13]
wire _req_needT_T_2; // @[Parameters.scala:270:13]
assign _req_needT_T_2 = _GEN; // @[Parameters.scala:270:13]
wire _excluded_client_T_6; // @[Parameters.scala:279:117]
assign _excluded_client_T_6 = _GEN; // @[Parameters.scala:270:13, :279:117]
wire _GEN_0 = request_param == 3'h1; // @[Parameters.scala:270:42]
wire _req_needT_T_3; // @[Parameters.scala:270:42]
assign _req_needT_T_3 = _GEN_0; // @[Parameters.scala:270:42]
wire _final_meta_writeback_clients_T; // @[Parameters.scala:282:11]
assign _final_meta_writeback_clients_T = _GEN_0; // @[Parameters.scala:270:42, :282:11]
wire _io_schedule_bits_d_bits_param_T_7; // @[MSHR.scala:299:79]
assign _io_schedule_bits_d_bits_param_T_7 = _GEN_0; // @[Parameters.scala:270:42]
wire _req_needT_T_4 = _req_needT_T_2 & _req_needT_T_3; // @[Parameters.scala:270:{13,33,42}]
wire _req_needT_T_5 = _req_needT_T_1 | _req_needT_T_4; // @[Parameters.scala:269:{5,16}, :270:33]
wire _GEN_1 = request_opcode == 3'h6; // @[Parameters.scala:271:14]
wire _req_needT_T_6; // @[Parameters.scala:271:14]
assign _req_needT_T_6 = _GEN_1; // @[Parameters.scala:271:14]
wire _req_acquire_T; // @[MSHR.scala:219:36]
assign _req_acquire_T = _GEN_1; // @[Parameters.scala:271:14]
wire _excluded_client_T_1; // @[Parameters.scala:279:12]
assign _excluded_client_T_1 = _GEN_1; // @[Parameters.scala:271:14, :279:12]
wire _req_needT_T_7 = &request_opcode; // @[Parameters.scala:271:52]
wire _req_needT_T_8 = _req_needT_T_6 | _req_needT_T_7; // @[Parameters.scala:271:{14,42,52}]
wire _req_needT_T_9 = |request_param; // @[Parameters.scala:271:89]
wire _req_needT_T_10 = _req_needT_T_8 & _req_needT_T_9; // @[Parameters.scala:271:{42,80,89}]
wire req_needT = _req_needT_T_5 | _req_needT_T_10; // @[Parameters.scala:269:16, :270:70, :271:80]
wire _req_acquire_T_1 = &request_opcode; // @[Parameters.scala:271:52]
wire req_acquire = _req_acquire_T | _req_acquire_T_1; // @[MSHR.scala:219:{36,53,71}]
wire _meta_no_clients_T = |meta_clients; // @[MSHR.scala:100:17, :220:39]
wire meta_no_clients = ~_meta_no_clients_T; // @[MSHR.scala:220:{25,39}]
wire _req_promoteT_T = &meta_state; // @[MSHR.scala:100:17, :221:81]
wire _req_promoteT_T_1 = meta_no_clients & _req_promoteT_T; // @[MSHR.scala:220:25, :221:{67,81}]
wire _req_promoteT_T_2 = meta_hit ? _req_promoteT_T_1 : gotT; // @[MSHR.scala:100:17, :148:17, :221:{40,67}]
wire req_promoteT = req_acquire & _req_promoteT_T_2; // @[MSHR.scala:219:53, :221:{34,40}]
wire _final_meta_writeback_dirty_T = request_opcode[0]; // @[MSHR.scala:98:20, :224:65]
wire _final_meta_writeback_dirty_T_1 = meta_dirty | _final_meta_writeback_dirty_T; // @[MSHR.scala:100:17, :224:{48,65}]
wire _final_meta_writeback_state_T = request_param != 3'h3; // @[MSHR.scala:98:20, :225:55]
wire _GEN_2 = meta_state == 2'h2; // @[MSHR.scala:100:17, :225:78]
wire _final_meta_writeback_state_T_1; // @[MSHR.scala:225:78]
assign _final_meta_writeback_state_T_1 = _GEN_2; // @[MSHR.scala:225:78]
wire _final_meta_writeback_state_T_12; // @[MSHR.scala:240:70]
assign _final_meta_writeback_state_T_12 = _GEN_2; // @[MSHR.scala:225:78, :240:70]
wire _evict_T_2; // @[MSHR.scala:317:26]
assign _evict_T_2 = _GEN_2; // @[MSHR.scala:225:78, :317:26]
wire _before_T_1; // @[MSHR.scala:317:26]
assign _before_T_1 = _GEN_2; // @[MSHR.scala:225:78, :317:26]
wire _final_meta_writeback_state_T_2 = _final_meta_writeback_state_T & _final_meta_writeback_state_T_1; // @[MSHR.scala:225:{55,64,78}]
wire [1:0] _final_meta_writeback_state_T_3 = _final_meta_writeback_state_T_2 ? 2'h3 : meta_state; // @[MSHR.scala:100:17, :225:{40,64}]
wire _GEN_3 = request_param == 3'h2; // @[Parameters.scala:282:43]
wire _final_meta_writeback_clients_T_1; // @[Parameters.scala:282:43]
assign _final_meta_writeback_clients_T_1 = _GEN_3; // @[Parameters.scala:282:43]
wire _io_schedule_bits_d_bits_param_T_5; // @[MSHR.scala:299:79]
assign _io_schedule_bits_d_bits_param_T_5 = _GEN_3; // @[Parameters.scala:282:43]
wire _final_meta_writeback_clients_T_2 = _final_meta_writeback_clients_T | _final_meta_writeback_clients_T_1; // @[Parameters.scala:282:{11,34,43}]
wire _final_meta_writeback_clients_T_3 = request_param == 3'h5; // @[Parameters.scala:282:75]
wire _final_meta_writeback_clients_T_4 = _final_meta_writeback_clients_T_2 | _final_meta_writeback_clients_T_3; // @[Parameters.scala:282:{34,66,75}]
wire [3:0] _final_meta_writeback_clients_T_5 = _final_meta_writeback_clients_T_4 ? req_clientBit : 4'h0; // @[Parameters.scala:201:10, :282:66]
wire [3:0] _final_meta_writeback_clients_T_6 = ~_final_meta_writeback_clients_T_5; // @[MSHR.scala:226:{52,56}]
wire [3:0] _final_meta_writeback_clients_T_7 = meta_clients & _final_meta_writeback_clients_T_6; // @[MSHR.scala:100:17, :226:{50,52}]
wire [3:0] _final_meta_writeback_clients_T_8 = ~probes_toN; // @[MSHR.scala:151:23, :232:54]
wire [3:0] _final_meta_writeback_clients_T_9 = meta_clients & _final_meta_writeback_clients_T_8; // @[MSHR.scala:100:17, :232:{52,54}]
wire _final_meta_writeback_dirty_T_2 = meta_hit & meta_dirty; // @[MSHR.scala:100:17, :236:45]
wire _final_meta_writeback_dirty_T_4 = ~_final_meta_writeback_dirty_T_3; // @[MSHR.scala:236:{63,78}]
wire _final_meta_writeback_dirty_T_5 = _final_meta_writeback_dirty_T_2 | _final_meta_writeback_dirty_T_4; // @[MSHR.scala:236:{45,60,63}]
wire [1:0] _GEN_4 = {1'h1, ~req_acquire}; // @[MSHR.scala:219:53, :238:40]
wire [1:0] _final_meta_writeback_state_T_4; // @[MSHR.scala:238:40]
assign _final_meta_writeback_state_T_4 = _GEN_4; // @[MSHR.scala:238:40]
wire [1:0] _final_meta_writeback_state_T_6; // @[MSHR.scala:239:65]
assign _final_meta_writeback_state_T_6 = _GEN_4; // @[MSHR.scala:238:40, :239:65]
wire _final_meta_writeback_state_T_5 = ~meta_hit; // @[MSHR.scala:100:17, :239:41]
wire [1:0] _final_meta_writeback_state_T_7 = gotT ? _final_meta_writeback_state_T_6 : 2'h1; // @[MSHR.scala:148:17, :239:{55,65}]
wire _final_meta_writeback_state_T_8 = meta_no_clients & req_acquire; // @[MSHR.scala:219:53, :220:25, :244:72]
wire [1:0] _final_meta_writeback_state_T_9 = {1'h1, ~_final_meta_writeback_state_T_8}; // @[MSHR.scala:244:{55,72}]
wire _GEN_5 = meta_state == 2'h1; // @[MSHR.scala:100:17, :240:70]
wire _final_meta_writeback_state_T_10; // @[MSHR.scala:240:70]
assign _final_meta_writeback_state_T_10 = _GEN_5; // @[MSHR.scala:240:70]
wire _io_schedule_bits_c_bits_param_T; // @[MSHR.scala:291:53]
assign _io_schedule_bits_c_bits_param_T = _GEN_5; // @[MSHR.scala:240:70, :291:53]
wire _evict_T_1; // @[MSHR.scala:317:26]
assign _evict_T_1 = _GEN_5; // @[MSHR.scala:240:70, :317:26]
wire _before_T; // @[MSHR.scala:317:26]
assign _before_T = _GEN_5; // @[MSHR.scala:240:70, :317:26]
wire [1:0] _final_meta_writeback_state_T_13 = {_final_meta_writeback_state_T_12, 1'h1}; // @[MSHR.scala:240:70]
wire _final_meta_writeback_state_T_14 = &meta_state; // @[MSHR.scala:100:17, :221:81, :240:70]
wire [1:0] _final_meta_writeback_state_T_15 = _final_meta_writeback_state_T_14 ? _final_meta_writeback_state_T_9 : _final_meta_writeback_state_T_13; // @[MSHR.scala:240:70, :244:55]
wire [1:0] _final_meta_writeback_state_T_16 = _final_meta_writeback_state_T_5 ? _final_meta_writeback_state_T_7 : _final_meta_writeback_state_T_15; // @[MSHR.scala:239:{40,41,55}, :240:70]
wire [1:0] _final_meta_writeback_state_T_17 = req_needT ? _final_meta_writeback_state_T_4 : _final_meta_writeback_state_T_16; // @[Parameters.scala:270:70]
wire [3:0] _final_meta_writeback_clients_T_10 = ~probes_toN; // @[MSHR.scala:151:23, :232:54, :245:66]
wire [3:0] _final_meta_writeback_clients_T_11 = meta_clients & _final_meta_writeback_clients_T_10; // @[MSHR.scala:100:17, :245:{64,66}]
wire [3:0] _final_meta_writeback_clients_T_12 = meta_hit ? _final_meta_writeback_clients_T_11 : 4'h0; // @[MSHR.scala:100:17, :245:{40,64}]
wire [3:0] _final_meta_writeback_clients_T_13 = req_acquire ? req_clientBit : 4'h0; // @[Parameters.scala:201:10]
wire [3:0] _final_meta_writeback_clients_T_14 = _final_meta_writeback_clients_T_12 | _final_meta_writeback_clients_T_13; // @[MSHR.scala:245:{40,84}, :246:40]
assign final_meta_writeback_tag = request_prio_2 | request_control ? meta_tag : request_tag; // @[MSHR.scala:98:20, :100:17, :215:38, :223:52, :228:53, :247:30]
wire [3:0] _final_meta_writeback_clients_T_15 = ~probes_toN; // @[MSHR.scala:151:23, :232:54, :258:54]
wire [3:0] _final_meta_writeback_clients_T_16 = meta_clients & _final_meta_writeback_clients_T_15; // @[MSHR.scala:100:17, :258:{52,54}]
assign final_meta_writeback_hit = bad_grant ? meta_hit : request_prio_2 | ~request_control; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :227:34, :228:53, :234:30, :248:30, :251:20, :252:21]
assign final_meta_writeback_dirty = ~bad_grant & (request_prio_2 ? _final_meta_writeback_dirty_T_1 : request_control ? ~meta_hit & meta_dirty : _final_meta_writeback_dirty_T_5); // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :224:{34,48}, :228:53, :229:21, :230:36, :236:{32,60}, :251:20, :252:21]
assign final_meta_writeback_state = bad_grant ? {1'h0, meta_hit} : request_prio_2 ? _final_meta_writeback_state_T_3 : request_control ? (meta_hit ? 2'h0 : meta_state) : _final_meta_writeback_state_T_17; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :225:{34,40}, :228:53, :229:21, :231:36, :237:{32,38}, :251:20, :252:21, :257:36, :263:36]
assign final_meta_writeback_clients = bad_grant ? (meta_hit ? _final_meta_writeback_clients_T_16 : 4'h0) : request_prio_2 ? _final_meta_writeback_clients_T_7 : request_control ? (meta_hit ? _final_meta_writeback_clients_T_9 : meta_clients) : _final_meta_writeback_clients_T_14; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :226:{34,50}, :228:53, :229:21, :232:{36,52}, :245:{34,84}, :251:20, :252:21, :258:{36,52}, :264:36]
wire [3:0] _honour_BtoT_T = meta_clients & req_clientBit; // @[Parameters.scala:201:10]
wire _honour_BtoT_T_1 = |_honour_BtoT_T; // @[MSHR.scala:276:{47,64}]
wire honour_BtoT = meta_hit & _honour_BtoT_T_1; // @[MSHR.scala:100:17, :276:{30,64}]
wire _excluded_client_T_2 = &request_opcode; // @[Parameters.scala:271:52, :279:50]
wire _excluded_client_T_3 = _excluded_client_T_1 | _excluded_client_T_2; // @[Parameters.scala:279:{12,40,50}]
wire _excluded_client_T_4 = request_opcode == 3'h4; // @[Parameters.scala:279:87]
wire _excluded_client_T_5 = _excluded_client_T_3 | _excluded_client_T_4; // @[Parameters.scala:279:{40,77,87}]
wire _excluded_client_T_8 = _excluded_client_T_5; // @[Parameters.scala:279:{77,106}]
wire [1:0] _io_schedule_bits_a_bits_param_T = meta_hit ? 2'h2 : 2'h1; // @[MSHR.scala:100:17, :282:56]
wire [1:0] _io_schedule_bits_a_bits_param_T_1 = req_needT ? _io_schedule_bits_a_bits_param_T : 2'h0; // @[Parameters.scala:270:70]
assign io_schedule_bits_a_bits_param_0 = {1'h0, _io_schedule_bits_a_bits_param_T_1}; // @[MSHR.scala:84:7, :282:{35,41}]
wire _io_schedule_bits_a_bits_block_T = request_size != 3'h6; // @[MSHR.scala:98:20, :283:51]
wire _io_schedule_bits_a_bits_block_T_1 = request_opcode == 3'h0; // @[MSHR.scala:98:20, :284:55]
wire _io_schedule_bits_a_bits_block_T_2 = &request_opcode; // @[Parameters.scala:271:52]
wire _io_schedule_bits_a_bits_block_T_3 = _io_schedule_bits_a_bits_block_T_1 | _io_schedule_bits_a_bits_block_T_2; // @[MSHR.scala:284:{55,71,89}]
wire _io_schedule_bits_a_bits_block_T_4 = ~_io_schedule_bits_a_bits_block_T_3; // @[MSHR.scala:284:{38,71}]
assign _io_schedule_bits_a_bits_block_T_5 = _io_schedule_bits_a_bits_block_T | _io_schedule_bits_a_bits_block_T_4; // @[MSHR.scala:283:{51,91}, :284:38]
assign io_schedule_bits_a_bits_block_0 = _io_schedule_bits_a_bits_block_T_5; // @[MSHR.scala:84:7, :283:91]
wire _io_schedule_bits_b_bits_param_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31, :286:42]
wire [1:0] _io_schedule_bits_b_bits_param_T_1 = req_needT ? 2'h2 : 2'h1; // @[Parameters.scala:270:70]
wire [2:0] _io_schedule_bits_b_bits_param_T_2 = request_prio_1 ? request_param : {1'h0, _io_schedule_bits_b_bits_param_T_1}; // @[MSHR.scala:98:20, :286:{61,97}]
assign _io_schedule_bits_b_bits_param_T_3 = _io_schedule_bits_b_bits_param_T ? 3'h2 : _io_schedule_bits_b_bits_param_T_2; // @[MSHR.scala:286:{41,42,61}]
assign io_schedule_bits_b_bits_param_0 = _io_schedule_bits_b_bits_param_T_3; // @[MSHR.scala:84:7, :286:41]
wire _io_schedule_bits_b_bits_tag_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31, :287:42]
assign _io_schedule_bits_b_bits_tag_T_1 = _io_schedule_bits_b_bits_tag_T ? meta_tag : request_tag; // @[MSHR.scala:98:20, :100:17, :287:{41,42}]
assign io_schedule_bits_b_bits_tag_0 = _io_schedule_bits_b_bits_tag_T_1; // @[MSHR.scala:84:7, :287:41]
assign io_schedule_bits_b_bits_clients_0 = _io_schedule_bits_b_bits_clients_T_1; // @[MSHR.scala:84:7, :289:51]
assign _io_schedule_bits_c_bits_opcode_T = {2'h3, meta_dirty}; // @[MSHR.scala:100:17, :290:41]
assign io_schedule_bits_c_bits_opcode_0 = _io_schedule_bits_c_bits_opcode_T; // @[MSHR.scala:84:7, :290:41]
assign _io_schedule_bits_c_bits_param_T_1 = _io_schedule_bits_c_bits_param_T ? 3'h2 : 3'h1; // @[MSHR.scala:291:{41,53}]
assign io_schedule_bits_c_bits_param_0 = _io_schedule_bits_c_bits_param_T_1; // @[MSHR.scala:84:7, :291:41]
wire _io_schedule_bits_d_bits_param_T = ~req_acquire; // @[MSHR.scala:219:53, :298:42]
wire [1:0] _io_schedule_bits_d_bits_param_T_1 = {1'h0, req_promoteT}; // @[MSHR.scala:221:34, :300:53]
wire [1:0] _io_schedule_bits_d_bits_param_T_2 = honour_BtoT ? 2'h2 : 2'h1; // @[MSHR.scala:276:30, :301:53]
wire _io_schedule_bits_d_bits_param_T_3 = ~(|request_param); // @[Parameters.scala:271:89]
wire [2:0] _io_schedule_bits_d_bits_param_T_4 = _io_schedule_bits_d_bits_param_T_3 ? {1'h0, _io_schedule_bits_d_bits_param_T_1} : request_param; // @[MSHR.scala:98:20, :299:79, :300:53]
wire [2:0] _io_schedule_bits_d_bits_param_T_6 = _io_schedule_bits_d_bits_param_T_5 ? {1'h0, _io_schedule_bits_d_bits_param_T_2} : _io_schedule_bits_d_bits_param_T_4; // @[MSHR.scala:299:79, :301:53]
wire [2:0] _io_schedule_bits_d_bits_param_T_8 = _io_schedule_bits_d_bits_param_T_7 ? 3'h1 : _io_schedule_bits_d_bits_param_T_6; // @[MSHR.scala:299:79]
assign _io_schedule_bits_d_bits_param_T_9 = _io_schedule_bits_d_bits_param_T ? request_param : _io_schedule_bits_d_bits_param_T_8; // @[MSHR.scala:98:20, :298:{41,42}, :299:79]
assign io_schedule_bits_d_bits_param_0 = _io_schedule_bits_d_bits_param_T_9; // @[MSHR.scala:84:7, :298:41]
wire _io_schedule_bits_dir_bits_data_T = ~s_release; // @[MSHR.scala:124:33, :186:32, :310:42]
assign _io_schedule_bits_dir_bits_data_T_1_dirty = ~_io_schedule_bits_dir_bits_data_T & _io_schedule_bits_dir_bits_data_WIRE_dirty; // @[MSHR.scala:310:{41,42,71}]
assign _io_schedule_bits_dir_bits_data_T_1_state = _io_schedule_bits_dir_bits_data_T ? 2'h0 : _io_schedule_bits_dir_bits_data_WIRE_state; // @[MSHR.scala:310:{41,42,71}]
assign _io_schedule_bits_dir_bits_data_T_1_clients = _io_schedule_bits_dir_bits_data_T ? 4'h0 : _io_schedule_bits_dir_bits_data_WIRE_clients; // @[MSHR.scala:310:{41,42,71}]
assign _io_schedule_bits_dir_bits_data_T_1_tag = _io_schedule_bits_dir_bits_data_T ? 13'h0 : _io_schedule_bits_dir_bits_data_WIRE_tag; // @[MSHR.scala:310:{41,42,71}]
assign io_schedule_bits_dir_bits_data_dirty_0 = _io_schedule_bits_dir_bits_data_T_1_dirty; // @[MSHR.scala:84:7, :310:41]
assign io_schedule_bits_dir_bits_data_state_0 = _io_schedule_bits_dir_bits_data_T_1_state; // @[MSHR.scala:84:7, :310:41]
assign io_schedule_bits_dir_bits_data_clients_0 = _io_schedule_bits_dir_bits_data_T_1_clients; // @[MSHR.scala:84:7, :310:41]
assign io_schedule_bits_dir_bits_data_tag_0 = _io_schedule_bits_dir_bits_data_T_1_tag; // @[MSHR.scala:84:7, :310:41]
wire _evict_T = ~meta_hit; // @[MSHR.scala:100:17, :239:41, :338:32]
wire [3:0] evict; // @[MSHR.scala:314:26]
wire evict_c = |meta_clients; // @[MSHR.scala:100:17, :220:39, :315:27]
wire _evict_out_T = ~evict_c; // @[MSHR.scala:315:27, :318:32]
wire [1:0] _GEN_6 = {1'h1, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32]
wire [1:0] _evict_out_T_1; // @[MSHR.scala:319:32]
assign _evict_out_T_1 = _GEN_6; // @[MSHR.scala:319:32]
wire [1:0] _before_out_T_1; // @[MSHR.scala:319:32]
assign _before_out_T_1 = _GEN_6; // @[MSHR.scala:319:32]
wire _evict_T_3 = &meta_state; // @[MSHR.scala:100:17, :221:81, :317:26]
wire [2:0] _GEN_7 = {2'h2, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32, :320:39]
wire [2:0] _evict_out_T_2; // @[MSHR.scala:320:39]
assign _evict_out_T_2 = _GEN_7; // @[MSHR.scala:320:39]
wire [2:0] _before_out_T_2; // @[MSHR.scala:320:39]
assign _before_out_T_2 = _GEN_7; // @[MSHR.scala:320:39]
wire [2:0] _GEN_8 = {2'h3, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32, :320:76]
wire [2:0] _evict_out_T_3; // @[MSHR.scala:320:76]
assign _evict_out_T_3 = _GEN_8; // @[MSHR.scala:320:76]
wire [2:0] _before_out_T_3; // @[MSHR.scala:320:76]
assign _before_out_T_3 = _GEN_8; // @[MSHR.scala:320:76]
wire [2:0] _evict_out_T_4 = evict_c ? _evict_out_T_2 : _evict_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}]
wire _evict_T_4 = ~(|meta_state); // @[MSHR.scala:100:17, :104:22, :317:26]
wire _evict_T_5 = ~_evict_T; // @[MSHR.scala:323:11, :338:32]
assign evict = _evict_T_5 ? 4'h8 : _evict_T_1 ? {3'h0, _evict_out_T} : _evict_T_2 ? {2'h0, _evict_out_T_1} : _evict_T_3 ? {1'h0, _evict_out_T_4} : {_evict_T_4, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26, :323:{11,17,23}]
wire [3:0] before_0; // @[MSHR.scala:314:26]
wire before_c = |meta_clients; // @[MSHR.scala:100:17, :220:39, :315:27]
wire _before_out_T = ~before_c; // @[MSHR.scala:315:27, :318:32]
wire _before_T_2 = &meta_state; // @[MSHR.scala:100:17, :221:81, :317:26]
wire [2:0] _before_out_T_4 = before_c ? _before_out_T_2 : _before_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}]
wire _before_T_3 = ~(|meta_state); // @[MSHR.scala:100:17, :104:22, :317:26]
wire _before_T_4 = ~meta_hit; // @[MSHR.scala:100:17, :239:41, :323:11]
assign before_0 = _before_T_4 ? 4'h8 : _before_T ? {3'h0, _before_out_T} : _before_T_1 ? {2'h0, _before_out_T_1} : _before_T_2 ? {1'h0, _before_out_T_4} : {_before_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26, :323:{11,17,23}]
wire [3:0] after; // @[MSHR.scala:314:26]
wire after_c = |final_meta_writeback_clients; // @[MSHR.scala:215:38, :315:27]
wire _GEN_9 = final_meta_writeback_state == 2'h1; // @[MSHR.scala:215:38, :317:26]
wire _after_T; // @[MSHR.scala:317:26]
assign _after_T = _GEN_9; // @[MSHR.scala:317:26]
wire _prior_T; // @[MSHR.scala:317:26]
assign _prior_T = _GEN_9; // @[MSHR.scala:317:26]
wire _after_out_T = ~after_c; // @[MSHR.scala:315:27, :318:32]
wire _GEN_10 = final_meta_writeback_state == 2'h2; // @[MSHR.scala:215:38, :317:26]
wire _after_T_1; // @[MSHR.scala:317:26]
assign _after_T_1 = _GEN_10; // @[MSHR.scala:317:26]
wire _prior_T_1; // @[MSHR.scala:317:26]
assign _prior_T_1 = _GEN_10; // @[MSHR.scala:317:26]
wire [1:0] _GEN_11 = {1'h1, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32]
wire [1:0] _after_out_T_1; // @[MSHR.scala:319:32]
assign _after_out_T_1 = _GEN_11; // @[MSHR.scala:319:32]
wire [1:0] _prior_out_T_1; // @[MSHR.scala:319:32]
assign _prior_out_T_1 = _GEN_11; // @[MSHR.scala:319:32]
wire _after_T_2 = &final_meta_writeback_state; // @[MSHR.scala:215:38, :317:26]
wire [2:0] _GEN_12 = {2'h2, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32, :320:39]
wire [2:0] _after_out_T_2; // @[MSHR.scala:320:39]
assign _after_out_T_2 = _GEN_12; // @[MSHR.scala:320:39]
wire [2:0] _prior_out_T_2; // @[MSHR.scala:320:39]
assign _prior_out_T_2 = _GEN_12; // @[MSHR.scala:320:39]
wire [2:0] _GEN_13 = {2'h3, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32, :320:76]
wire [2:0] _after_out_T_3; // @[MSHR.scala:320:76]
assign _after_out_T_3 = _GEN_13; // @[MSHR.scala:320:76]
wire [2:0] _prior_out_T_3; // @[MSHR.scala:320:76]
assign _prior_out_T_3 = _GEN_13; // @[MSHR.scala:320:76]
wire [2:0] _after_out_T_4 = after_c ? _after_out_T_2 : _after_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}]
wire _GEN_14 = final_meta_writeback_state == 2'h0; // @[MSHR.scala:215:38, :317:26]
wire _after_T_3; // @[MSHR.scala:317:26]
assign _after_T_3 = _GEN_14; // @[MSHR.scala:317:26]
wire _prior_T_3; // @[MSHR.scala:317:26]
assign _prior_T_3 = _GEN_14; // @[MSHR.scala:317:26]
assign after = _after_T ? {3'h0, _after_out_T} : _after_T_1 ? {2'h0, _after_out_T_1} : _after_T_2 ? {1'h0, _after_out_T_4} : {_after_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26]
wire _probe_bit_T = io_sinkc_bits_source_0 == 7'h44; // @[Parameters.scala:46:9]
wire _probe_bit_T_1 = io_sinkc_bits_source_0 == 7'h40; // @[Parameters.scala:46:9]
wire [2:0] probe_bit_uncommonBits = _probe_bit_uncommonBits_T[2:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] _probe_bit_T_2 = io_sinkc_bits_source_0[6:3]; // @[Parameters.scala:54:10]
wire [3:0] _probe_bit_T_8 = io_sinkc_bits_source_0[6:3]; // @[Parameters.scala:54:10]
wire _probe_bit_T_3 = _probe_bit_T_2 == 4'h6; // @[Parameters.scala:54:{10,32}]
wire _probe_bit_T_5 = _probe_bit_T_3; // @[Parameters.scala:54:{32,67}]
wire _probe_bit_T_6 = probe_bit_uncommonBits < 3'h5; // @[Parameters.scala:52:56, :57:20]
wire _probe_bit_T_7 = _probe_bit_T_5 & _probe_bit_T_6; // @[Parameters.scala:54:67, :56:48, :57:20]
wire [2:0] probe_bit_uncommonBits_1 = _probe_bit_uncommonBits_T_1[2:0]; // @[Parameters.scala:52:{29,56}]
wire _probe_bit_T_9 = _probe_bit_T_8 == 4'h4; // @[Parameters.scala:54:{10,32}]
wire _probe_bit_T_11 = _probe_bit_T_9; // @[Parameters.scala:54:{32,67}]
wire _probe_bit_T_12 = probe_bit_uncommonBits_1 < 3'h5; // @[Parameters.scala:52:56, :57:20]
wire _probe_bit_T_13 = _probe_bit_T_11 & _probe_bit_T_12; // @[Parameters.scala:54:67, :56:48, :57:20]
wire [1:0] probe_bit_lo = {_probe_bit_T_1, _probe_bit_T}; // @[Parameters.scala:46:9]
wire [1:0] probe_bit_hi = {_probe_bit_T_13, _probe_bit_T_7}; // @[Parameters.scala:56:48]
wire [3:0] probe_bit = {probe_bit_hi, probe_bit_lo}; // @[Parameters.scala:201:10]
wire [3:0] _GEN_15 = probes_done | probe_bit; // @[Parameters.scala:201:10]
wire [3:0] _last_probe_T; // @[MSHR.scala:459:33]
assign _last_probe_T = _GEN_15; // @[MSHR.scala:459:33]
wire [3:0] _probes_done_T; // @[MSHR.scala:467:32]
assign _probes_done_T = _GEN_15; // @[MSHR.scala:459:33, :467:32]
wire last_probe = _last_probe_T == _last_probe_T_2; // @[MSHR.scala:459:{33,46,64}]
wire _probe_toN_T = io_sinkc_bits_param_0 == 3'h1; // @[Parameters.scala:282:11]
wire _probe_toN_T_1 = io_sinkc_bits_param_0 == 3'h2; // @[Parameters.scala:282:43]
wire _probe_toN_T_2 = _probe_toN_T | _probe_toN_T_1; // @[Parameters.scala:282:{11,34,43}]
wire _probe_toN_T_3 = io_sinkc_bits_param_0 == 3'h5; // @[Parameters.scala:282:75]
wire probe_toN = _probe_toN_T_2 | _probe_toN_T_3; // @[Parameters.scala:282:{34,66,75}]
wire [3:0] _probes_toN_T = probe_toN ? probe_bit : 4'h0; // @[Parameters.scala:201:10, :282:66]
wire [3:0] _probes_toN_T_1 = probes_toN | _probes_toN_T; // @[MSHR.scala:151:23, :468:{30,35}]
wire _probes_noT_T = io_sinkc_bits_param_0 != 3'h3; // @[MSHR.scala:84:7, :469:53]
wire _probes_noT_T_1 = probes_noT | _probes_noT_T; // @[MSHR.scala:152:23, :469:{30,53}]
wire _w_rprobeackfirst_T = w_rprobeackfirst | last_probe; // @[MSHR.scala:122:33, :459:46, :470:42]
wire _GEN_16 = last_probe & io_sinkc_bits_last_0; // @[MSHR.scala:84:7, :459:46, :471:55]
wire _w_rprobeacklast_T; // @[MSHR.scala:471:55]
assign _w_rprobeacklast_T = _GEN_16; // @[MSHR.scala:471:55]
wire _w_pprobeacklast_T; // @[MSHR.scala:473:55]
assign _w_pprobeacklast_T = _GEN_16; // @[MSHR.scala:471:55, :473:55]
wire _w_rprobeacklast_T_1 = w_rprobeacklast | _w_rprobeacklast_T; // @[MSHR.scala:123:33, :471:{40,55}]
wire _w_pprobeackfirst_T = w_pprobeackfirst | last_probe; // @[MSHR.scala:132:33, :459:46, :472:42]
wire _w_pprobeacklast_T_1 = w_pprobeacklast | _w_pprobeacklast_T; // @[MSHR.scala:133:33, :473:{40,55}]
wire _set_pprobeack_T = ~(|request_offset); // @[MSHR.scala:98:20, :475:77]
wire _set_pprobeack_T_1 = io_sinkc_bits_last_0 | _set_pprobeack_T; // @[MSHR.scala:84:7, :475:{59,77}]
wire set_pprobeack = last_probe & _set_pprobeack_T_1; // @[MSHR.scala:459:46, :475:{36,59}]
wire _w_pprobeack_T = w_pprobeack | set_pprobeack; // @[MSHR.scala:134:33, :475:36, :476:32]
wire _w_grant_T = ~(|request_offset); // @[MSHR.scala:98:20, :475:77, :490:33]
wire _w_grant_T_1 = _w_grant_T | io_sinkd_bits_last_0; // @[MSHR.scala:84:7, :490:{33,41}]
wire _gotT_T = io_sinkd_bits_param_0 == 3'h0; // @[MSHR.scala:84:7, :493:35]
wire _new_meta_T = io_allocate_valid_0 & io_allocate_bits_repeat_0; // @[MSHR.scala:84:7, :505:40]
wire new_meta_dirty = _new_meta_T ? final_meta_writeback_dirty : io_directory_bits_dirty_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}]
wire [1:0] new_meta_state = _new_meta_T ? final_meta_writeback_state : io_directory_bits_state_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}]
wire [3:0] new_meta_clients = _new_meta_T ? final_meta_writeback_clients : io_directory_bits_clients_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}]
wire [12:0] new_meta_tag = _new_meta_T ? final_meta_writeback_tag : io_directory_bits_tag_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}]
wire new_meta_hit = _new_meta_T ? final_meta_writeback_hit : io_directory_bits_hit_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}]
wire [2:0] new_meta_way = _new_meta_T ? final_meta_writeback_way : io_directory_bits_way_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}]
wire new_request_prio_1 = io_allocate_valid_0 ? allocate_as_full_prio_1 : request_prio_1; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire new_request_prio_2 = io_allocate_valid_0 ? allocate_as_full_prio_2 : request_prio_2; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire new_request_control = io_allocate_valid_0 ? allocate_as_full_control : request_control; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [2:0] new_request_opcode = io_allocate_valid_0 ? allocate_as_full_opcode : request_opcode; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [2:0] new_request_param = io_allocate_valid_0 ? allocate_as_full_param : request_param; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [2:0] new_request_size = io_allocate_valid_0 ? allocate_as_full_size : request_size; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [6:0] new_request_source = io_allocate_valid_0 ? allocate_as_full_source : request_source; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [12:0] new_request_tag = io_allocate_valid_0 ? allocate_as_full_tag : request_tag; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [5:0] new_request_offset = io_allocate_valid_0 ? allocate_as_full_offset : request_offset; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [5:0] new_request_put = io_allocate_valid_0 ? allocate_as_full_put : request_put; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [9:0] new_request_set = io_allocate_valid_0 ? allocate_as_full_set : request_set; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [6:0] _new_clientBit_uncommonBits_T = new_request_source; // @[Parameters.scala:52:29]
wire [6:0] _new_clientBit_uncommonBits_T_1 = new_request_source; // @[Parameters.scala:52:29]
wire _new_needT_T = new_request_opcode[2]; // @[Parameters.scala:269:12]
wire _new_needT_T_1 = ~_new_needT_T; // @[Parameters.scala:269:{5,12}]
wire _GEN_17 = new_request_opcode == 3'h5; // @[Parameters.scala:270:13]
wire _new_needT_T_2; // @[Parameters.scala:270:13]
assign _new_needT_T_2 = _GEN_17; // @[Parameters.scala:270:13]
wire _new_skipProbe_T_5; // @[Parameters.scala:279:117]
assign _new_skipProbe_T_5 = _GEN_17; // @[Parameters.scala:270:13, :279:117]
wire _new_needT_T_3 = new_request_param == 3'h1; // @[Parameters.scala:270:42]
wire _new_needT_T_4 = _new_needT_T_2 & _new_needT_T_3; // @[Parameters.scala:270:{13,33,42}]
wire _new_needT_T_5 = _new_needT_T_1 | _new_needT_T_4; // @[Parameters.scala:269:{5,16}, :270:33]
wire _T_615 = new_request_opcode == 3'h6; // @[Parameters.scala:271:14]
wire _new_needT_T_6; // @[Parameters.scala:271:14]
assign _new_needT_T_6 = _T_615; // @[Parameters.scala:271:14]
wire _new_skipProbe_T; // @[Parameters.scala:279:12]
assign _new_skipProbe_T = _T_615; // @[Parameters.scala:271:14, :279:12]
wire _new_needT_T_7 = &new_request_opcode; // @[Parameters.scala:271:52]
wire _new_needT_T_8 = _new_needT_T_6 | _new_needT_T_7; // @[Parameters.scala:271:{14,42,52}]
wire _new_needT_T_9 = |new_request_param; // @[Parameters.scala:271:89]
wire _new_needT_T_10 = _new_needT_T_8 & _new_needT_T_9; // @[Parameters.scala:271:{42,80,89}]
wire new_needT = _new_needT_T_5 | _new_needT_T_10; // @[Parameters.scala:269:16, :270:70, :271:80]
wire _new_clientBit_T = new_request_source == 7'h44; // @[Parameters.scala:46:9]
wire _new_clientBit_T_1 = new_request_source == 7'h40; // @[Parameters.scala:46:9]
wire [2:0] new_clientBit_uncommonBits = _new_clientBit_uncommonBits_T[2:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] _new_clientBit_T_2 = new_request_source[6:3]; // @[Parameters.scala:54:10]
wire [3:0] _new_clientBit_T_8 = new_request_source[6:3]; // @[Parameters.scala:54:10]
wire _new_clientBit_T_3 = _new_clientBit_T_2 == 4'h6; // @[Parameters.scala:54:{10,32}]
wire _new_clientBit_T_5 = _new_clientBit_T_3; // @[Parameters.scala:54:{32,67}]
wire _new_clientBit_T_6 = new_clientBit_uncommonBits < 3'h5; // @[Parameters.scala:52:56, :57:20]
wire _new_clientBit_T_7 = _new_clientBit_T_5 & _new_clientBit_T_6; // @[Parameters.scala:54:67, :56:48, :57:20]
wire [2:0] new_clientBit_uncommonBits_1 = _new_clientBit_uncommonBits_T_1[2:0]; // @[Parameters.scala:52:{29,56}]
wire _new_clientBit_T_9 = _new_clientBit_T_8 == 4'h4; // @[Parameters.scala:54:{10,32}]
wire _new_clientBit_T_11 = _new_clientBit_T_9; // @[Parameters.scala:54:{32,67}]
wire _new_clientBit_T_12 = new_clientBit_uncommonBits_1 < 3'h5; // @[Parameters.scala:52:56, :57:20]
wire _new_clientBit_T_13 = _new_clientBit_T_11 & _new_clientBit_T_12; // @[Parameters.scala:54:67, :56:48, :57:20]
wire [1:0] new_clientBit_lo = {_new_clientBit_T_1, _new_clientBit_T}; // @[Parameters.scala:46:9]
wire [1:0] new_clientBit_hi = {_new_clientBit_T_13, _new_clientBit_T_7}; // @[Parameters.scala:56:48]
wire [3:0] new_clientBit = {new_clientBit_hi, new_clientBit_lo}; // @[Parameters.scala:201:10]
wire _new_skipProbe_T_1 = &new_request_opcode; // @[Parameters.scala:271:52, :279:50]
wire _new_skipProbe_T_2 = _new_skipProbe_T | _new_skipProbe_T_1; // @[Parameters.scala:279:{12,40,50}]
wire _new_skipProbe_T_3 = new_request_opcode == 3'h4; // @[Parameters.scala:279:87]
wire _new_skipProbe_T_4 = _new_skipProbe_T_2 | _new_skipProbe_T_3; // @[Parameters.scala:279:{40,77,87}]
wire _new_skipProbe_T_7 = _new_skipProbe_T_4; // @[Parameters.scala:279:{77,106}]
wire [3:0] new_skipProbe = _new_skipProbe_T_7 ? new_clientBit : 4'h0; // @[Parameters.scala:201:10, :279:106]
wire [3:0] prior; // @[MSHR.scala:314:26]
wire prior_c = |final_meta_writeback_clients; // @[MSHR.scala:215:38, :315:27]
wire _prior_out_T = ~prior_c; // @[MSHR.scala:315:27, :318:32]
wire _prior_T_2 = &final_meta_writeback_state; // @[MSHR.scala:215:38, :317:26]
wire [2:0] _prior_out_T_4 = prior_c ? _prior_out_T_2 : _prior_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}]
assign prior = _prior_T ? {3'h0, _prior_out_T} : _prior_T_1 ? {2'h0, _prior_out_T_1} : _prior_T_2 ? {1'h0, _prior_out_T_4} : {_prior_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26]
wire _T_574 = io_directory_valid_0 | _new_meta_T; // @[MSHR.scala:84:7, :505:40, :539:28] |
Generate the Verilog code corresponding to the following Chisel files.
File ShiftRegisterPriorityQueue.scala:
package compressacc
import chisel3._
import chisel3.util._
import chisel3.util._
// TODO : support enq & deq at the same cycle
class PriorityQueueStageIO(keyWidth: Int, value: ValueInfo) extends Bundle {
val output_prev = KeyValue(keyWidth, value)
val output_nxt = KeyValue(keyWidth, value)
val input_prev = Flipped(KeyValue(keyWidth, value))
val input_nxt = Flipped(KeyValue(keyWidth, value))
val cmd = Flipped(Valid(UInt(1.W)))
val insert_here = Input(Bool())
val cur_input_keyval = Flipped(KeyValue(keyWidth, value))
val cur_output_keyval = KeyValue(keyWidth, value)
}
class PriorityQueueStage(keyWidth: Int, value: ValueInfo) extends Module {
val io = IO(new PriorityQueueStageIO(keyWidth, value))
dontTouch(io)
val CMD_DEQ = 0.U
val CMD_ENQ = 1.U
val MAX_VALUE = (1 << keyWidth) - 1
val key_reg = RegInit(MAX_VALUE.U(keyWidth.W))
val value_reg = Reg(value)
io.output_prev.key := key_reg
io.output_prev.value := value_reg
io.output_nxt.key := key_reg
io.output_nxt.value := value_reg
io.cur_output_keyval.key := key_reg
io.cur_output_keyval.value := value_reg
when (io.cmd.valid) {
switch (io.cmd.bits) {
is (CMD_DEQ) {
key_reg := io.input_nxt.key
value_reg := io.input_nxt.value
}
is (CMD_ENQ) {
when (io.insert_here) {
key_reg := io.cur_input_keyval.key
value_reg := io.cur_input_keyval.value
} .elsewhen (key_reg >= io.cur_input_keyval.key) {
key_reg := io.input_prev.key
value_reg := io.input_prev.value
} .otherwise {
// do nothing
}
}
}
}
}
object PriorityQueueStage {
def apply(keyWidth: Int, v: ValueInfo): PriorityQueueStage = new PriorityQueueStage(keyWidth, v)
}
// TODO
// - This design is not scalable as the enqued_keyval is broadcasted to all the stages
// - Add pipeline registers later
class PriorityQueueIO(queSize: Int, keyWidth: Int, value: ValueInfo) extends Bundle {
val cnt_bits = log2Ceil(queSize+1)
val counter = Output(UInt(cnt_bits.W))
val enq = Flipped(Decoupled(KeyValue(keyWidth, value)))
val deq = Decoupled(KeyValue(keyWidth, value))
}
class PriorityQueue(queSize: Int, keyWidth: Int, value: ValueInfo) extends Module {
val keyWidthInternal = keyWidth + 1
val CMD_DEQ = 0.U
val CMD_ENQ = 1.U
val io = IO(new PriorityQueueIO(queSize, keyWidthInternal, value))
dontTouch(io)
val MAX_VALUE = ((1 << keyWidthInternal) - 1).U
val cnt_bits = log2Ceil(queSize+1)
// do not consider cases where we are inserting more entries then the queSize
val counter = RegInit(0.U(cnt_bits.W))
io.counter := counter
val full = (counter === queSize.U)
val empty = (counter === 0.U)
io.deq.valid := !empty
io.enq.ready := !full
when (io.enq.fire) {
counter := counter + 1.U
}
when (io.deq.fire) {
counter := counter - 1.U
}
val cmd_valid = io.enq.valid || io.deq.ready
val cmd = Mux(io.enq.valid, CMD_ENQ, CMD_DEQ)
assert(!(io.enq.valid && io.deq.ready))
val stages = Seq.fill(queSize)(Module(new PriorityQueueStage(keyWidthInternal, value)))
for (i <- 0 until (queSize - 1)) {
stages(i+1).io.input_prev <> stages(i).io.output_nxt
stages(i).io.input_nxt <> stages(i+1).io.output_prev
}
stages(queSize-1).io.input_nxt.key := MAX_VALUE
// stages(queSize-1).io.input_nxt.value :=
stages(queSize-1).io.input_nxt.value.symbol := 0.U
// stages(queSize-1).io.input_nxt.value.child(0) := 0.U
// stages(queSize-1).io.input_nxt.value.child(1) := 0.U
stages(0).io.input_prev.key := io.enq.bits.key
stages(0).io.input_prev.value <> io.enq.bits.value
for (i <- 0 until queSize) {
stages(i).io.cmd.valid := cmd_valid
stages(i).io.cmd.bits := cmd
stages(i).io.cur_input_keyval <> io.enq.bits
}
val is_large_or_equal = WireInit(VecInit(Seq.fill(queSize)(false.B)))
for (i <- 0 until queSize) {
is_large_or_equal(i) := (stages(i).io.cur_output_keyval.key >= io.enq.bits.key)
}
val is_large_or_equal_cat = Wire(UInt(queSize.W))
is_large_or_equal_cat := Cat(is_large_or_equal.reverse)
val insert_here_idx = PriorityEncoder(is_large_or_equal_cat)
for (i <- 0 until queSize) {
when (i.U === insert_here_idx) {
stages(i).io.insert_here := true.B
} .otherwise {
stages(i).io.insert_here := false.B
}
}
io.deq.bits <> stages(0).io.output_prev
}
| module PriorityQueueStage_35( // @[ShiftRegisterPriorityQueue.scala:21:7]
input clock, // @[ShiftRegisterPriorityQueue.scala:21:7]
input reset, // @[ShiftRegisterPriorityQueue.scala:21:7]
output [30:0] io_output_prev_key, // @[ShiftRegisterPriorityQueue.scala:22:14]
output [9:0] io_output_prev_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14]
output [30:0] io_output_nxt_key, // @[ShiftRegisterPriorityQueue.scala:22:14]
output [9:0] io_output_nxt_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14]
input [30:0] io_input_prev_key, // @[ShiftRegisterPriorityQueue.scala:22:14]
input [9:0] io_input_prev_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14]
input [30:0] io_input_nxt_key, // @[ShiftRegisterPriorityQueue.scala:22:14]
input [9:0] io_input_nxt_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14]
input io_cmd_valid, // @[ShiftRegisterPriorityQueue.scala:22:14]
input io_cmd_bits, // @[ShiftRegisterPriorityQueue.scala:22:14]
input io_insert_here, // @[ShiftRegisterPriorityQueue.scala:22:14]
input [30:0] io_cur_input_keyval_key, // @[ShiftRegisterPriorityQueue.scala:22:14]
input [9:0] io_cur_input_keyval_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14]
output [30:0] io_cur_output_keyval_key, // @[ShiftRegisterPriorityQueue.scala:22:14]
output [9:0] io_cur_output_keyval_value_symbol // @[ShiftRegisterPriorityQueue.scala:22:14]
);
wire [30:0] io_input_prev_key_0 = io_input_prev_key; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [9:0] io_input_prev_value_symbol_0 = io_input_prev_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [30:0] io_input_nxt_key_0 = io_input_nxt_key; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [9:0] io_input_nxt_value_symbol_0 = io_input_nxt_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire io_cmd_valid_0 = io_cmd_valid; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire io_cmd_bits_0 = io_cmd_bits; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire io_insert_here_0 = io_insert_here; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [30:0] io_cur_input_keyval_key_0 = io_cur_input_keyval_key; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [9:0] io_cur_input_keyval_value_symbol_0 = io_cur_input_keyval_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [9:0] io_output_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [30:0] io_output_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [9:0] io_output_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [30:0] io_output_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [9:0] io_cur_output_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [30:0] io_cur_output_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
reg [30:0] key_reg; // @[ShiftRegisterPriorityQueue.scala:30:24]
assign io_output_prev_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]
assign io_output_nxt_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]
assign io_cur_output_keyval_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]
reg [9:0] value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:31:22]
assign io_output_prev_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]
assign io_output_nxt_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]
assign io_cur_output_keyval_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]
wire _T_2 = key_reg >= io_cur_input_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24, :52:30]
always @(posedge clock) begin // @[ShiftRegisterPriorityQueue.scala:21:7]
if (reset) // @[ShiftRegisterPriorityQueue.scala:21:7]
key_reg <= 31'h7FFFFFFF; // @[ShiftRegisterPriorityQueue.scala:30:24]
else if (io_cmd_valid_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7]
if (io_cmd_bits_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7]
if (io_insert_here_0) // @[ShiftRegisterPriorityQueue.scala:21:7]
key_reg <= io_cur_input_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]
else if (_T_2) // @[ShiftRegisterPriorityQueue.scala:52:30]
key_reg <= io_input_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]
end
else // @[ShiftRegisterPriorityQueue.scala:21:7]
key_reg <= io_input_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]
end
if (io_cmd_valid_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7]
if (io_cmd_bits_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7]
if (io_insert_here_0) // @[ShiftRegisterPriorityQueue.scala:21:7]
value_reg_symbol <= io_cur_input_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]
else if (_T_2) // @[ShiftRegisterPriorityQueue.scala:52:30]
value_reg_symbol <= io_input_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]
end
else // @[ShiftRegisterPriorityQueue.scala:21:7]
value_reg_symbol <= io_input_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]
end
always @(posedge)
assign io_output_prev_key = io_output_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
assign io_output_prev_value_symbol = io_output_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
assign io_output_nxt_key = io_output_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
assign io_output_nxt_value_symbol = io_output_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
assign io_cur_output_keyval_key = io_cur_output_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
assign io_cur_output_keyval_value_symbol = io_cur_output_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File ShiftReg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
// Similar to the Chisel ShiftRegister but allows the user to suggest a
// name to the registers that get instantiated, and
// to provide a reset value.
object ShiftRegInit {
def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T =
(0 until n).foldRight(in) {
case (i, next) => {
val r = RegNext(next, init)
name.foreach { na => r.suggestName(s"${na}_${i}") }
r
}
}
}
/** These wrap behavioral
* shift registers into specific modules to allow for
* backend flows to replace or constrain
* them properly when used for CDC synchronization,
* rather than buffering.
*
* The different types vary in their reset behavior:
* AsyncResetShiftReg -- Asynchronously reset register array
* A W(width) x D(depth) sized array is constructed from D instantiations of a
* W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg,
* but only used for timing applications
*/
abstract class AbstractPipelineReg(w: Int = 1) extends Module {
val io = IO(new Bundle {
val d = Input(UInt(w.W))
val q = Output(UInt(w.W))
}
)
}
object AbstractPipelineReg {
def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = {
val chain = Module(gen)
name.foreach{ chain.suggestName(_) }
chain.io.d := in.asUInt
chain.io.q.asTypeOf(in)
}
}
class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) {
require(depth > 0, "Depth must be greater than 0.")
override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}"
val chain = List.tabulate(depth) { i =>
Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}")
}
chain.last.io.d := io.d
chain.last.io.en := true.B
(chain.init zip chain.tail).foreach { case (sink, source) =>
sink.io.d := source.io.q
sink.io.en := true.B
}
io.q := chain.head.io.q
}
object AsyncResetShiftReg {
def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T =
AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name)
def apply [T <: Data](in: T, depth: Int, name: Option[String]): T =
apply(in, depth, 0, name)
def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T =
apply(in, depth, init.litValue.toInt, name)
def apply [T <: Data](in: T, depth: Int, init: T): T =
apply (in, depth, init.litValue.toInt, None)
}
File SynchronizerReg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util.{RegEnable, Cat}
/** These wrap behavioral
* shift and next registers into specific modules to allow for
* backend flows to replace or constrain
* them properly when used for CDC synchronization,
* rather than buffering.
*
*
* These are built up of *ResetSynchronizerPrimitiveShiftReg,
* intended to be replaced by the integrator's metastable flops chains or replaced
* at this level if they have a multi-bit wide synchronizer primitive.
* The different types vary in their reset behavior:
* NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin
* AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep
* 1-bit-wide shift registers.
* SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg
*
* [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference.
*
* ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross
* Clock Domains.
*/
object SynchronizerResetType extends Enumeration {
val NonSync, Inferred, Sync, Async = Value
}
// Note: this should not be used directly.
// Use the companion object to generate this with the correct reset type mixin.
private class SynchronizerPrimitiveShiftReg(
sync: Int,
init: Boolean,
resetType: SynchronizerResetType.Value)
extends AbstractPipelineReg(1) {
val initInt = if (init) 1 else 0
val initPostfix = resetType match {
case SynchronizerResetType.NonSync => ""
case _ => s"_i${initInt}"
}
override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}"
val chain = List.tabulate(sync) { i =>
val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B)
reg.suggestName(s"sync_$i")
}
chain.last := io.d.asBool
(chain.init zip chain.tail).foreach { case (sink, source) =>
sink := source
}
io.q := chain.head.asUInt
}
private object SynchronizerPrimitiveShiftReg {
def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = {
val gen: () => SynchronizerPrimitiveShiftReg = resetType match {
case SynchronizerResetType.NonSync =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType)
case SynchronizerResetType.Async =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset
case SynchronizerResetType.Sync =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset
case SynchronizerResetType.Inferred =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType)
}
AbstractPipelineReg(gen(), in)
}
}
// Note: This module may end up with a non-AsyncReset type reset.
// But the Primitives within will always have AsyncReset type.
class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int)
extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
withReset(reset.asAsyncReset){
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async)
}
}
io.q := Cat(output.reverse)
}
object AsyncResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
// Note: This module may end up with a non-Bool type reset.
// But the Primitives within will always have Bool reset type.
@deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2")
class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
withReset(reset.asBool){
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync)
}
}
io.q := Cat(output.reverse)
}
object SyncResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred)
}
io.q := Cat(output.reverse)
}
object ResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}"
val output = Seq.tabulate(w) { i =>
SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync)
}
io.q := Cat(output.reverse)
}
object SynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T =
if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, None)
def apply [T <: Data](in: T): T =
apply (in, 3, None)
}
class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module {
override def desiredName = s"ClockCrossingReg_w${w}"
val io = IO(new Bundle{
val d = Input(UInt(w.W))
val q = Output(UInt(w.W))
val en = Input(Bool())
})
val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en)
io.q := cdc_reg
}
object ClockCrossingReg {
def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = {
val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit))
name.foreach{ cdc_reg.suggestName(_) }
cdc_reg.io.d := in.asUInt
cdc_reg.io.en := en
cdc_reg.io.q.asTypeOf(in)
}
}
| module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_164( // @[SynchronizerReg.scala:68:19]
input clock, // @[SynchronizerReg.scala:68:19]
input reset, // @[SynchronizerReg.scala:68:19]
output io_q // @[ShiftReg.scala:36:14]
);
wire io_d = 1'h1; // @[SynchronizerReg.scala:54:22, :68:19]
wire _sync_2_T = 1'h1; // @[SynchronizerReg.scala:54:22, :68:19]
wire io_q_0; // @[SynchronizerReg.scala:68:19]
reg sync_0; // @[SynchronizerReg.scala:51:87]
assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19]
reg sync_1; // @[SynchronizerReg.scala:51:87]
reg sync_2; // @[SynchronizerReg.scala:51:87]
always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19]
if (reset) begin // @[SynchronizerReg.scala:68:19]
sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87]
sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87]
sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87]
end
else begin // @[SynchronizerReg.scala:68:19]
sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87]
sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87]
sync_2 <= 1'h1; // @[SynchronizerReg.scala:51:87, :54:22, :68:19]
end
always @(posedge, posedge) |
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